From: Luke Kenneth Casson Leighton Date: Fri, 2 Oct 2020 10:02:53 +0000 (+0000) Subject: really really cut down core X-Git-Tag: partial-core-ls180-gdsii~49 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3920526653c11ac61d6684de5601812635d1eae7;p=soclayout.git really really cut down core --- diff --git a/experiments9/Makefile b/experiments9/Makefile index d90a63b..50562d3 100755 --- a/experiments9/Makefile +++ b/experiments9/Makefile @@ -5,7 +5,7 @@ # YOSYS_SET_TOP = Yes CHIP = chip - CORE = ls180 + #CORE = ls180 MARGIN = 2 BOOMOPT = BOOGOPT = @@ -14,9 +14,10 @@ USE_CLOCKTREE = Yes USE_DEBUG = No USE_KITE = No - VST_FLAGS = --vst-use-concat + #VST_FLAGS = --vst-use-concat - NETLISTS = $(shell cat cells.lst) + #NETLISTS = $(shell cat cells.lst) + NETLISTS = ls180 # YOSYS_FLATTEN = $(shell cat flatten.lst) @@ -24,11 +25,12 @@ include ./mk/design-flow.mk pinmux: - python ../pinmux/src/pinmux_generator.py -v -s ls180 -o coriolis2/ls180 + (cd coriolis2 && python ../../pinmux/src/pinmux_generator.py -v -s ls180 -o ls180) ln -f -s ../pinmux/src/parse.py coriolis2/pinparse.py -blif: ls180.blif -vst: ls180.vst +# comment out for now +#blif: ls180.blif +#vst: ls180.vst lvx: lvx-chip_cts_r druc: druc-chip_cts_r diff --git a/experiments9/coriolis2/ioring.py b/experiments9/coriolis2/ioring.py index babf856..c61fa47 100644 --- a/experiments9/coriolis2/ioring.py +++ b/experiments9/coriolis2/ioring.py @@ -4,11 +4,31 @@ from helpers import l, u, n import os import json +def _byteify(data, ignore_dicts = False): + # if this is a unicode string, return its string representation + if isinstance(data, unicode): + return data.encode('utf-8') + # if this is a list of values, return list of byteified values + if isinstance(data, list): + return [ _byteify(item, ignore_dicts=True) for item in data ] + # if this is a dictionary, return dictionary of byteified keys and values + # but only if we haven't already byteified it + if isinstance(data, dict) and not ignore_dicts: + return dict((_byteify(key, ignore_dicts=True), + _byteify(value, ignore_dicts=True)) + for key, value in data.iteritems()) + # if it's anything else, return it in its original form + return data + # load JSON-formatted pad info from pinmux pth = os.path.abspath(__file__) pth = os.path.split(pth)[0] +print "path", pth with open("%s/ls180/litex_pinpads.json" % pth) as f: - chip = json.loads(f.read()) + txt = f.read() +chip = json.loads(txt, object_hook=_byteify) +chip = _byteify(chip, ignore_dicts=True) +print chip chip.update({ 'pads.ioPadGauge' : 'pxlib', # core option (big, time-consuming) @@ -18,4 +38,4 @@ chip.update({ 'pads.ioPadGauge' : 'pxlib', 'core.size' : ( l(13000), l(13000) ), 'chip.size' : ( l(17000), l(17000) ), 'chip.clockTree' : True, - } + }) diff --git a/experiments9/non_generated/ls180.il b/experiments9/non_generated/ls180.il deleted file mode 100644 index 0b6e584..0000000 --- a/experiments9/non_generated/ls180.il +++ /dev/null @@ -1,146332 +0,0 @@ -# Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os) -autoidx 3715 -attribute \src "libresoc.v:5.1-277.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.jtag._fsm" -attribute \generator "nMigen" -module \_fsm - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $0\fsm_state$next[3:0]$25 - attribute \src "libresoc.v:91.3-92.35" - wire width 4 $0\fsm_state[3:0] - attribute \src "libresoc.v:6.7-6.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:97.3-124.6" - wire $0\isdr$next[0:0]$21 - attribute \src "libresoc.v:93.3-94.25" - wire $0\isdr[0:0] - attribute \src "libresoc.v:240.3-267.6" - wire $0\isir$next[0:0]$38 - attribute \src "libresoc.v:95.3-96.25" - wire $0\isir[0:0] - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $10\fsm_state$next[3:0]$35 - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $11\fsm_state$next[3:0]$36 - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $1\fsm_state$next[3:0]$26 - attribute \src "libresoc.v:46.13-46.29" - wire width 4 $1\fsm_state[3:0] - attribute \src "libresoc.v:97.3-124.6" - wire $1\isdr$next[0:0]$22 - attribute \src "libresoc.v:51.7-51.18" - wire $1\isdr[0:0] - attribute \src "libresoc.v:240.3-267.6" - wire $1\isir$next[0:0]$39 - attribute \src "libresoc.v:56.7-56.18" - wire $1\isir[0:0] - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $2\fsm_state$next[3:0]$27 - attribute \src "libresoc.v:97.3-124.6" - wire $2\isdr$next[0:0]$23 - attribute \src "libresoc.v:240.3-267.6" - wire $2\isir$next[0:0]$40 - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $3\fsm_state$next[3:0]$28 - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $4\fsm_state$next[3:0]$29 - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $5\fsm_state$next[3:0]$30 - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $6\fsm_state$next[3:0]$31 - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $7\fsm_state$next[3:0]$32 - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $8\fsm_state$next[3:0]$33 - attribute \src "libresoc.v:125.3-239.6" - wire width 4 $9\fsm_state$next[3:0]$34 - attribute \src "libresoc.v:75.17-75.110" - wire $eq$libresoc.v:75$1_Y - attribute \src "libresoc.v:76.18-76.111" - wire $eq$libresoc.v:76$2_Y - attribute \src "libresoc.v:77.18-77.111" - wire $eq$libresoc.v:77$3_Y - attribute \src "libresoc.v:78.18-78.111" - wire $eq$libresoc.v:78$4_Y - attribute \src "libresoc.v:79.18-79.111" - wire $eq$libresoc.v:79$5_Y - attribute \src "libresoc.v:80.17-80.108" - wire $eq$libresoc.v:80$6_Y - attribute \src "libresoc.v:81.18-81.111" - wire $eq$libresoc.v:81$7_Y - attribute \src "libresoc.v:82.18-82.111" - wire $eq$libresoc.v:82$8_Y - attribute \src "libresoc.v:83.18-83.111" - wire $eq$libresoc.v:83$9_Y - attribute \src "libresoc.v:84.18-84.111" - wire $eq$libresoc.v:84$10_Y - attribute \src "libresoc.v:85.18-85.111" - wire $eq$libresoc.v:85$11_Y - attribute \src "libresoc.v:86.18-86.111" - wire $eq$libresoc.v:86$12_Y - attribute \src "libresoc.v:87.18-87.112" - wire $eq$libresoc.v:87$13_Y - attribute \src "libresoc.v:88.17-88.108" - wire $eq$libresoc.v:88$14_Y - attribute \src "libresoc.v:89.17-89.108" - wire $eq$libresoc.v:89$15_Y - attribute \src "libresoc.v:90.17-90.108" - wire $eq$libresoc.v:90$16_Y - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:117" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire input 9 \TAP_bus__tck - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire input 10 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" - wire output 11 \capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" - wire width 4 \fsm_state - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" - wire width 4 \fsm_state$next - attribute \src "libresoc.v:6.7-6.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" - wire output 1 \isdr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" - wire \isdr$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" - wire output 4 \isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" - wire \isir$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:50" - wire \local_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" - wire output 8 \negjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" - wire output 6 \negjtag_rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" - wire output 7 \posjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" - wire output 5 \posjtag_rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:37" - wire \rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" - wire output 2 \shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:27" - wire output 3 \update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" - cell $eq $eq$libresoc.v:75$1 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:75$1_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" - cell $eq $eq$libresoc.v:76$2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:76$2_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" - cell $eq $eq$libresoc.v:77$3 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:77$3_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" - cell $eq $eq$libresoc.v:78$4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'1 - connect \Y $eq$libresoc.v:78$4_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" - cell $eq $eq$libresoc.v:79$5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:79$5_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" - cell $eq $eq$libresoc.v:80$6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 1'0 - connect \Y $eq$libresoc.v:80$6_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" - cell $eq $eq$libresoc.v:81$7 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:81$7_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" - cell $eq $eq$libresoc.v:82$8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:82$8_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" - cell $eq $eq$libresoc.v:83$9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'1 - connect \Y $eq$libresoc.v:83$9_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" - cell $eq $eq$libresoc.v:84$10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:84$10_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" - cell $eq $eq$libresoc.v:85$11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'1 - connect \Y $eq$libresoc.v:85$11_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" - cell $eq $eq$libresoc.v:86$12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:86$12_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" - cell $eq $eq$libresoc.v:87$13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:87$13_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" - cell $eq $eq$libresoc.v:88$14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 2'11 - connect \Y $eq$libresoc.v:88$14_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" - cell $eq $eq$libresoc.v:89$15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 3'101 - connect \Y $eq$libresoc.v:89$15_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:117" - cell $eq $eq$libresoc.v:90$16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 4'1000 - connect \Y $eq$libresoc.v:90$16_Y - end - attribute \src "libresoc.v:125.3-239.6" - process $proc$libresoc.v:125$24 - assign { } { } - assign { } { } - assign $0\fsm_state$next[3:0]$25 $1\fsm_state$next[3:0]$26 - attribute \src "libresoc.v:126.5-126.29" - switch \initial - attribute \src "libresoc.v:126.9-126.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\fsm_state$next[3:0]$26 $2\fsm_state$next[3:0]$27 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" - switch \$13 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fsm_state$next[3:0]$27 4'0001 - case - assign $2\fsm_state$next[3:0]$27 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\fsm_state$next[3:0]$26 $3\fsm_state$next[3:0]$28 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" - switch \$15 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fsm_state$next[3:0]$28 4'0010 - case - assign $3\fsm_state$next[3:0]$28 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\fsm_state$next[3:0]$26 $4\fsm_state$next[3:0]$29 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" - switch \$17 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$next[3:0]$29 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\fsm_state$next[3:0]$29 4'0100 - end - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\fsm_state$next[3:0]$26 $5\fsm_state$next[3:0]$30 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" - switch \$19 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\fsm_state$next[3:0]$30 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $5\fsm_state$next[3:0]$30 4'0000 - end - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\fsm_state$next[3:0]$26 $6\fsm_state$next[3:0]$31 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" - switch \$21 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\fsm_state$next[3:0]$31 4'0101 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $6\fsm_state$next[3:0]$31 4'0110 - end - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\fsm_state$next[3:0]$26 $7\fsm_state$next[3:0]$32 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" - switch \$23 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\fsm_state$next[3:0]$32 4'0110 - case - assign $7\fsm_state$next[3:0]$32 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\fsm_state$next[3:0]$26 $8\fsm_state$next[3:0]$33 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" - switch \$25 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $8\fsm_state$next[3:0]$33 4'0111 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $8\fsm_state$next[3:0]$33 4'1000 - end - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\fsm_state$next[3:0]$26 $9\fsm_state$next[3:0]$34 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" - switch \$27 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $9\fsm_state$next[3:0]$34 4'1001 - case - assign $9\fsm_state$next[3:0]$34 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\fsm_state$next[3:0]$26 $10\fsm_state$next[3:0]$35 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" - switch \$29 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $10\fsm_state$next[3:0]$35 4'0101 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $10\fsm_state$next[3:0]$35 4'1000 - end - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\fsm_state$next[3:0]$26 $11\fsm_state$next[3:0]$36 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" - switch \$31 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $11\fsm_state$next[3:0]$36 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $11\fsm_state$next[3:0]$36 4'0010 - end - case - assign $1\fsm_state$next[3:0]$26 \fsm_state - end - sync always - update \fsm_state$next $0\fsm_state$next[3:0]$25 - end - attribute \src "libresoc.v:240.3-267.6" - process $proc$libresoc.v:240$37 - assign { } { } - assign { } { } - assign $0\isir$next[0:0]$38 $1\isir$next[0:0]$39 - attribute \src "libresoc.v:241.5-241.29" - switch \initial - attribute \src "libresoc.v:241.9-241.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\isir$next[0:0]$39 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\isir$next[0:0]$39 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\isir$next[0:0]$39 $2\isir$next[0:0]$40 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\isir$next[0:0]$40 1'1 - case - assign $2\isir$next[0:0]$40 \isir - end - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\isir$next[0:0]$39 1'0 - case - assign $1\isir$next[0:0]$39 \isir - end - sync always - update \isir$next $0\isir$next[0:0]$38 - end - attribute \src "libresoc.v:46.13-46.29" - process $proc$libresoc.v:46$42 - assign { } { } - assign $1\fsm_state[3:0] 4'0000 - sync always - sync init - update \fsm_state $1\fsm_state[3:0] - end - attribute \src "libresoc.v:51.7-51.18" - process $proc$libresoc.v:51$43 - assign { } { } - assign $1\isdr[0:0] 1'0 - sync always - sync init - update \isdr $1\isdr[0:0] - end - attribute \src "libresoc.v:56.7-56.18" - process $proc$libresoc.v:56$44 - assign { } { } - assign $1\isir[0:0] 1'0 - sync always - sync init - update \isir $1\isir[0:0] - end - attribute \src "libresoc.v:6.7-6.20" - process $proc$libresoc.v:6$41 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:91.3-92.35" - process $proc$libresoc.v:91$17 - assign { } { } - assign $0\fsm_state[3:0] \fsm_state$next - sync posedge \local_clk - update \fsm_state $0\fsm_state[3:0] - end - attribute \src "libresoc.v:93.3-94.25" - process $proc$libresoc.v:93$18 - assign { } { } - assign $0\isdr[0:0] \isdr$next - sync posedge \local_clk - update \isdr $0\isdr[0:0] - end - attribute \src "libresoc.v:95.3-96.25" - process $proc$libresoc.v:95$19 - assign { } { } - assign $0\isir[0:0] \isir$next - sync posedge \local_clk - update \isir $0\isir[0:0] - end - attribute \src "libresoc.v:97.3-124.6" - process $proc$libresoc.v:97$20 - assign { } { } - assign { } { } - assign $0\isdr$next[0:0]$21 $1\isdr$next[0:0]$22 - attribute \src "libresoc.v:98.5-98.29" - switch \initial - attribute \src "libresoc.v:98.9-98.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\isdr$next[0:0]$22 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\isdr$next[0:0]$22 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\isdr$next[0:0]$22 $2\isdr$next[0:0]$23 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" - switch \$11 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\isdr$next[0:0]$23 1'1 - case - assign $2\isdr$next[0:0]$23 \isdr - end - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\isdr$next[0:0]$22 1'0 - case - assign $1\isdr$next[0:0]$22 \isdr - end - sync always - update \isdr$next $0\isdr$next[0:0]$21 - end - connect \$9 $eq$libresoc.v:75$1_Y - connect \$11 $eq$libresoc.v:76$2_Y - connect \$13 $eq$libresoc.v:77$3_Y - connect \$15 $eq$libresoc.v:78$4_Y - connect \$17 $eq$libresoc.v:79$5_Y - connect \$1 $eq$libresoc.v:80$6_Y - connect \$19 $eq$libresoc.v:81$7_Y - connect \$21 $eq$libresoc.v:82$8_Y - connect \$23 $eq$libresoc.v:83$9_Y - connect \$25 $eq$libresoc.v:84$10_Y - connect \$27 $eq$libresoc.v:85$11_Y - connect \$29 $eq$libresoc.v:86$12_Y - connect \$31 $eq$libresoc.v:87$13_Y - connect \$3 $eq$libresoc.v:88$14_Y - connect \$5 $eq$libresoc.v:89$15_Y - connect \$7 $eq$libresoc.v:90$16_Y - connect \update \$7 - connect \shift \$5 - connect \capture \$3 - connect \rst \$1 - connect \local_clk \TAP_bus__tck - connect \negjtag_rst \rst - connect \negjtag_clk \TAP_bus__tck - connect \posjtag_rst \rst - connect \posjtag_clk \TAP_bus__tck -end -attribute \src "libresoc.v:281.1-392.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.jtag._idblock" -attribute \generator "nMigen" -module \_idblock - attribute \src "libresoc.v:365.3-385.6" - wire width 32 $0\TAP_id_sr$next[31:0]$63 - attribute \src "libresoc.v:363.3-364.35" - wire width 32 $0\TAP_id_sr[31:0] - attribute \src "libresoc.v:282.7-282.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:365.3-385.6" - wire width 32 $1\TAP_id_sr$next[31:0]$64 - attribute \src "libresoc.v:318.14-318.31" - wire width 32 $1\TAP_id_sr[31:0] - attribute \src "libresoc.v:365.3-385.6" - wire width 32 $2\TAP_id_sr$next[31:0]$65 - attribute \src "libresoc.v:347.17-347.105" - wire $and$libresoc.v:347$45_Y - attribute \src "libresoc.v:351.18-351.103" - wire $and$libresoc.v:351$49_Y - attribute \src "libresoc.v:353.18-353.105" - wire $and$libresoc.v:353$51_Y - attribute \src "libresoc.v:357.18-357.103" - wire $and$libresoc.v:357$55_Y - attribute \src "libresoc.v:358.18-358.106" - wire $and$libresoc.v:358$56_Y - attribute \src "libresoc.v:362.17-362.101" - wire $and$libresoc.v:362$60_Y - attribute \src "libresoc.v:348.18-348.102" - wire $eq$libresoc.v:348$46_Y - attribute \src "libresoc.v:349.18-349.102" - wire $eq$libresoc.v:349$47_Y - attribute \src "libresoc.v:352.17-352.101" - wire $eq$libresoc.v:352$50_Y - attribute \src "libresoc.v:354.18-354.102" - wire $eq$libresoc.v:354$52_Y - attribute \src "libresoc.v:355.18-355.102" - wire $eq$libresoc.v:355$53_Y - attribute \src "libresoc.v:359.18-359.102" - wire $eq$libresoc.v:359$57_Y - attribute \src "libresoc.v:360.17-360.101" - wire $eq$libresoc.v:360$58_Y - attribute \src "libresoc.v:350.18-350.104" - wire $or$libresoc.v:350$48_Y - attribute \src "libresoc.v:356.18-356.104" - wire $or$libresoc.v:356$54_Y - attribute \src "libresoc.v:361.17-361.101" - wire $or$libresoc.v:361$59_Y - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:369" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire input 5 \TAP_bus__tdi - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:226" - wire width 32 \TAP_id_sr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:226" - wire width 32 \TAP_id_sr$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:215" - wire output 6 \TAP_id_tdo - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:233" - wire \_bypass - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:230" - wire \_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:231" - wire \_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:229" - wire \_tdi - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:232" - wire \_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" - wire input 1 \capture - attribute \src "libresoc.v:282.7-282.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" - wire width 4 input 9 \ir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" - wire input 2 \isdr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" - wire input 8 \posjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" - wire input 7 \posjtag_rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" - wire input 3 \shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:27" - wire input 4 \update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" - cell $and $and$libresoc.v:347$45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$7 - connect \B \capture - connect \Y $and$libresoc.v:347$45_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $and $and$libresoc.v:351$49 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isdr - connect \B \$15 - connect \Y $and$libresoc.v:351$49_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" - cell $and $and$libresoc.v:353$51 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$17 - connect \B \shift - connect \Y $and$libresoc.v:353$51_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $and $and$libresoc.v:357$55 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isdr - connect \B \$25 - connect \Y $and$libresoc.v:357$55_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" - cell $and $and$libresoc.v:358$56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$27 - connect \B \update - connect \Y $and$libresoc.v:358$56_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $and $and$libresoc.v:362$60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isdr - connect \B \$5 - connect \Y $and$libresoc.v:362$60_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $eq $eq$libresoc.v:348$46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ir - connect \B 1'1 - connect \Y $eq$libresoc.v:348$46_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $eq $eq$libresoc.v:349$47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \ir - connect \B 4'1111 - connect \Y $eq$libresoc.v:349$47_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $eq $eq$libresoc.v:352$50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ir - connect \B 1'1 - connect \Y $eq$libresoc.v:352$50_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $eq $eq$libresoc.v:354$52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ir - connect \B 1'1 - connect \Y $eq$libresoc.v:354$52_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $eq $eq$libresoc.v:355$53 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \ir - connect \B 4'1111 - connect \Y $eq$libresoc.v:355$53_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:369" - cell $eq $eq$libresoc.v:359$57 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \ir - connect \B 4'1111 - connect \Y $eq$libresoc.v:359$57_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $eq $eq$libresoc.v:360$58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \ir - connect \B 4'1111 - connect \Y $eq$libresoc.v:360$58_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $or $or$libresoc.v:350$48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$11 - connect \B \$13 - connect \Y $or$libresoc.v:350$48_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $or $or$libresoc.v:356$54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$21 - connect \B \$23 - connect \Y $or$libresoc.v:356$54_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $or $or$libresoc.v:361$59 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \$3 - connect \Y $or$libresoc.v:361$59_Y - end - attribute \src "libresoc.v:282.7-282.20" - process $proc$libresoc.v:282$66 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:318.14-318.31" - process $proc$libresoc.v:318$67 - assign { } { } - assign $1\TAP_id_sr[31:0] 0 - sync always - sync init - update \TAP_id_sr $1\TAP_id_sr[31:0] - end - attribute \src "libresoc.v:363.3-364.35" - process $proc$libresoc.v:363$61 - assign { } { } - assign $0\TAP_id_sr[31:0] \TAP_id_sr$next - sync posedge \posjtag_clk - update \TAP_id_sr $0\TAP_id_sr[31:0] - end - attribute \src "libresoc.v:365.3-385.6" - process $proc$libresoc.v:365$62 - assign { } { } - assign { } { } - assign $0\TAP_id_sr$next[31:0]$63 $1\TAP_id_sr$next[31:0]$64 - attribute \src "libresoc.v:366.5-366.29" - switch \initial - attribute \src "libresoc.v:366.9-366.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:244" - switch { \_shift \_capture } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\TAP_id_sr$next[31:0]$64 6399 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\TAP_id_sr$next[31:0]$64 $2\TAP_id_sr$next[31:0]$65 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:247" - switch \_bypass - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\TAP_id_sr$next[31:0]$65 [31:1] \TAP_id_sr [31:1] - assign $2\TAP_id_sr$next[31:0]$65 [0] \_tdi - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\TAP_id_sr$next[31:0]$65 { \_tdi \TAP_id_sr [31:1] } - end - case - assign $1\TAP_id_sr$next[31:0]$64 \TAP_id_sr - end - sync always - update \TAP_id_sr$next $0\TAP_id_sr$next[31:0]$63 - end - connect \$9 $and$libresoc.v:347$45_Y - connect \$11 $eq$libresoc.v:348$46_Y - connect \$13 $eq$libresoc.v:349$47_Y - connect \$15 $or$libresoc.v:350$48_Y - connect \$17 $and$libresoc.v:351$49_Y - connect \$1 $eq$libresoc.v:352$50_Y - connect \$19 $and$libresoc.v:353$51_Y - connect \$21 $eq$libresoc.v:354$52_Y - connect \$23 $eq$libresoc.v:355$53_Y - connect \$25 $or$libresoc.v:356$54_Y - connect \$27 $and$libresoc.v:357$55_Y - connect \$29 $and$libresoc.v:358$56_Y - connect \$31 $eq$libresoc.v:359$57_Y - connect \$3 $eq$libresoc.v:360$58_Y - connect \$5 $or$libresoc.v:361$59_Y - connect \$7 $and$libresoc.v:362$60_Y - connect \TAP_id_tdo \TAP_id_sr [0] - connect \_bypass \$31 - connect \_update \$29 - connect \_shift \$19 - connect \_capture \$9 - connect \_tdi \TAP_bus__tdi -end -attribute \src "libresoc.v:396.1-480.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.jtag._irblock" -attribute \generator "nMigen" -module \_irblock - attribute \src "libresoc.v:397.7-397.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:458.3-478.6" - wire width 4 $0\ir$next[3:0]$80 - attribute \src "libresoc.v:441.3-442.21" - wire width 4 $0\ir[3:0] - attribute \src "libresoc.v:445.3-457.6" - wire width 4 $0\shift_ir$next[3:0]$77 - attribute \src "libresoc.v:443.3-444.33" - wire width 4 $0\shift_ir[3:0] - attribute \src "libresoc.v:458.3-478.6" - wire width 4 $1\ir$next[3:0]$81 - attribute \src "libresoc.v:416.13-416.22" - wire width 4 $1\ir[3:0] - attribute \src "libresoc.v:445.3-457.6" - wire width 4 $1\shift_ir$next[3:0]$78 - attribute \src "libresoc.v:428.13-428.28" - wire width 4 $1\shift_ir[3:0] - attribute \src "libresoc.v:458.3-478.6" - wire width 4 $2\ir$next[3:0]$82 - attribute \src "libresoc.v:435.17-435.103" - wire $and$libresoc.v:435$68_Y - attribute \src "libresoc.v:436.18-436.105" - wire $and$libresoc.v:436$69_Y - attribute \src "libresoc.v:437.17-437.105" - wire $and$libresoc.v:437$70_Y - attribute \src "libresoc.v:438.17-438.103" - wire $and$libresoc.v:438$71_Y - attribute \src "libresoc.v:439.17-439.104" - wire $and$libresoc.v:439$72_Y - attribute \src "libresoc.v:440.17-440.105" - wire $and$libresoc.v:440$73_Y - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:355" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:357" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:356" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:357" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:355" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:356" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire input 4 \TAP_bus__tdi - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" - wire input 1 \capture - attribute \src "libresoc.v:397.7-397.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" - wire width 4 output 9 \ir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" - wire width 4 \ir$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" - wire input 5 \isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" - wire input 8 \posjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" - wire input 7 \posjtag_rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" - wire input 2 \shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:139" - wire width 4 \shift_ir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:139" - wire width 4 \shift_ir$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:129" - wire output 6 \tdo - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:27" - wire input 3 \update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:356" - cell $and $and$libresoc.v:435$68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isir - connect \B \shift - connect \Y $and$libresoc.v:435$68_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:357" - cell $and $and$libresoc.v:436$69 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isir - connect \B \update - connect \Y $and$libresoc.v:436$69_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:355" - cell $and $and$libresoc.v:437$70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isir - connect \B \capture - connect \Y $and$libresoc.v:437$70_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:356" - cell $and $and$libresoc.v:438$71 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isir - connect \B \shift - connect \Y $and$libresoc.v:438$71_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:357" - cell $and $and$libresoc.v:439$72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isir - connect \B \update - connect \Y $and$libresoc.v:439$72_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:355" - cell $and $and$libresoc.v:440$73 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isir - connect \B \capture - connect \Y $and$libresoc.v:440$73_Y - end - attribute \src "libresoc.v:397.7-397.20" - process $proc$libresoc.v:397$83 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:416.13-416.22" - process $proc$libresoc.v:416$84 - assign { } { } - assign $1\ir[3:0] 4'0001 - sync always - sync init - update \ir $1\ir[3:0] - end - attribute \src "libresoc.v:428.13-428.28" - process $proc$libresoc.v:428$85 - assign { } { } - assign $1\shift_ir[3:0] 4'0000 - sync always - sync init - update \shift_ir $1\shift_ir[3:0] - end - attribute \src "libresoc.v:441.3-442.21" - process $proc$libresoc.v:441$74 - assign { } { } - assign $0\ir[3:0] \ir$next - sync posedge \posjtag_clk - update \ir $0\ir[3:0] - end - attribute \src "libresoc.v:443.3-444.33" - process $proc$libresoc.v:443$75 - assign { } { } - assign $0\shift_ir[3:0] \shift_ir$next - sync posedge \posjtag_clk - update \shift_ir $0\shift_ir[3:0] - end - attribute \src "libresoc.v:445.3-457.6" - process $proc$libresoc.v:445$76 - assign { } { } - assign { } { } - assign $0\shift_ir$next[3:0]$77 $1\shift_ir$next[3:0]$78 - attribute \src "libresoc.v:446.5-446.29" - switch \initial - attribute \src "libresoc.v:446.9-446.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:142" - switch { \$5 \$3 \$1 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $1\shift_ir$next[3:0]$78 \ir - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $1\shift_ir$next[3:0]$78 { \TAP_bus__tdi \shift_ir [3:1] } - case - assign $1\shift_ir$next[3:0]$78 \shift_ir - end - sync always - update \shift_ir$next $0\shift_ir$next[3:0]$77 - end - attribute \src "libresoc.v:458.3-478.6" - process $proc$libresoc.v:458$79 - assign { } { } - assign { } { } - assign { } { } - assign $0\ir$next[3:0]$80 $2\ir$next[3:0]$82 - attribute \src "libresoc.v:459.5-459.29" - switch \initial - attribute \src "libresoc.v:459.9-459.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:142" - switch { \$11 \$9 \$7 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $1\ir$next[3:0]$81 \ir - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $1\ir$next[3:0]$81 \ir - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $1\ir$next[3:0]$81 \shift_ir - case - assign $1\ir$next[3:0]$81 \ir - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ir$next[3:0]$82 4'0001 - case - assign $2\ir$next[3:0]$82 $1\ir$next[3:0]$81 - end - sync always - update \ir$next $0\ir$next[3:0]$80 - end - connect \$9 $and$libresoc.v:435$68_Y - connect \$11 $and$libresoc.v:436$69_Y - connect \$1 $and$libresoc.v:437$70_Y - connect \$3 $and$libresoc.v:438$71_Y - connect \$5 $and$libresoc.v:439$72_Y - connect \$7 $and$libresoc.v:440$73_Y - connect \tdo \ir [0] -end -attribute \src "libresoc.v:484.1-671.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.clksel" -attribute \generator "nMigen" -module \clksel - attribute \src "libresoc.v:621.3-640.6" - wire $0\clk1$next[0:0]$115 - attribute \src "libresoc.v:555.3-556.25" - wire $0\clk1[0:0] - attribute \src "libresoc.v:574.3-588.6" - wire $0\clk2$next[0:0]$103 - attribute \src "libresoc.v:561.3-562.25" - wire $0\clk2[0:0] - attribute \src "libresoc.v:606.3-620.6" - wire $0\clk3$next[0:0]$111 - attribute \src "libresoc.v:557.3-558.25" - wire $0\clk3[0:0] - attribute \src "libresoc.v:565.3-573.6" - wire $0\clk4$next[0:0]$100 - attribute \src "libresoc.v:563.3-564.25" - wire $0\clk4[0:0] - attribute \src "libresoc.v:641.3-663.6" - wire $0\core_clk_o[0:0] - attribute \src "libresoc.v:589.3-605.6" - wire width 2 $0\counter3$next[1:0]$107 - attribute \src "libresoc.v:559.3-560.33" - wire width 2 $0\counter3[1:0] - attribute \src "libresoc.v:485.7-485.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:621.3-640.6" - wire $1\clk1$next[0:0]$116 - attribute \src "libresoc.v:507.7-507.18" - wire $1\clk1[0:0] - attribute \src "libresoc.v:574.3-588.6" - wire $1\clk2$next[0:0]$104 - attribute \src "libresoc.v:511.7-511.18" - wire $1\clk2[0:0] - attribute \src "libresoc.v:606.3-620.6" - wire $1\clk3$next[0:0]$112 - attribute \src "libresoc.v:515.7-515.18" - wire $1\clk3[0:0] - attribute \src "libresoc.v:565.3-573.6" - wire $1\clk4$next[0:0]$101 - attribute \src "libresoc.v:519.7-519.18" - wire $1\clk4[0:0] - attribute \src "libresoc.v:641.3-663.6" - wire $1\core_clk_o[0:0] - attribute \src "libresoc.v:589.3-605.6" - wire width 2 $1\counter3$next[1:0]$108 - attribute \src "libresoc.v:536.13-536.28" - wire width 2 $1\counter3[1:0] - attribute \src "libresoc.v:621.3-640.6" - wire $2\clk1$next[0:0]$117 - attribute \src "libresoc.v:574.3-588.6" - wire $2\clk2$next[0:0]$105 - attribute \src "libresoc.v:606.3-620.6" - wire $2\clk3$next[0:0]$113 - attribute \src "libresoc.v:589.3-605.6" - wire width 2 $2\counter3$next[1:0]$109 - attribute \src "libresoc.v:621.3-640.6" - wire $3\clk1$next[0:0]$118 - attribute \src "libresoc.v:554.17-554.101" - wire width 3 $add$libresoc.v:554$93_Y - attribute \src "libresoc.v:547.18-547.103" - wire $eq$libresoc.v:547$86_Y - attribute \src "libresoc.v:549.18-549.103" - wire $eq$libresoc.v:549$88_Y - attribute \src "libresoc.v:553.17-553.102" - wire $eq$libresoc.v:553$92_Y - attribute \src "libresoc.v:548.18-548.93" - wire $not$libresoc.v:548$87_Y - attribute \src "libresoc.v:550.18-550.93" - wire $not$libresoc.v:550$89_Y - attribute \src "libresoc.v:551.17-551.92" - wire $not$libresoc.v:551$90_Y - attribute \src "libresoc.v:552.17-552.92" - wire $not$libresoc.v:552$91_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:55" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" - wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:60" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" - wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:62" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:57" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:64" - wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:64" - wire width 3 \$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" - wire \clk0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" - wire \clk1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" - wire \clk1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" - wire \clk2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" - wire \clk2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" - wire \clk3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" - wire \clk3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" - wire \clk4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" - wire \clk4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" - wire \clk5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" - wire \clk6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" - wire \clk7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:34" - wire input 2 \clk_24_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:36" - wire width 3 input 4 \clk_sel_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:37" - wire output 6 \core_clk_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:47" - wire width 2 \counter3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:47" - wire width 2 \counter3$next - attribute \src "libresoc.v:485.7-485.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:35" - wire output 5 \pll_48_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" - wire input 1 \pllclk_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" - wire \pllclk_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:38" - wire input 3 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:64" - cell $add $add$libresoc.v:554$93 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \counter3 - connect \B 1'1 - connect \Y $add$libresoc.v:554$93_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" - cell $eq $eq$libresoc.v:547$86 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \counter3 - connect \B 2'10 - connect \Y $eq$libresoc.v:547$86_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" - cell $eq $eq$libresoc.v:549$88 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \counter3 - connect \B 2'10 - connect \Y $eq$libresoc.v:549$88_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" - cell $eq $eq$libresoc.v:553$92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \counter3 - connect \B 2'10 - connect \Y $eq$libresoc.v:553$92_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:60" - cell $not $not$libresoc.v:548$87 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clk3 - connect \Y $not$libresoc.v:548$87_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:62" - cell $not $not$libresoc.v:550$89 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clk1 - connect \Y $not$libresoc.v:550$89_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:55" - cell $not $not$libresoc.v:551$90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clk4 - connect \Y $not$libresoc.v:551$90_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:57" - cell $not $not$libresoc.v:552$91 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clk2 - connect \Y $not$libresoc.v:552$91_Y - end - attribute \src "libresoc.v:485.7-485.20" - process $proc$libresoc.v:485$120 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:507.7-507.18" - process $proc$libresoc.v:507$121 - assign { } { } - assign $1\clk1[0:0] 1'0 - sync always - sync init - update \clk1 $1\clk1[0:0] - end - attribute \src "libresoc.v:511.7-511.18" - process $proc$libresoc.v:511$122 - assign { } { } - assign $1\clk2[0:0] 1'0 - sync always - sync init - update \clk2 $1\clk2[0:0] - end - attribute \src "libresoc.v:515.7-515.18" - process $proc$libresoc.v:515$123 - assign { } { } - assign $1\clk3[0:0] 1'0 - sync always - sync init - update \clk3 $1\clk3[0:0] - end - attribute \src "libresoc.v:519.7-519.18" - process $proc$libresoc.v:519$124 - assign { } { } - assign $1\clk4[0:0] 1'0 - sync always - sync init - update \clk4 $1\clk4[0:0] - end - attribute \src "libresoc.v:536.13-536.28" - process $proc$libresoc.v:536$125 - assign { } { } - assign $1\counter3[1:0] 2'00 - sync always - sync init - update \counter3 $1\counter3[1:0] - end - attribute \src "libresoc.v:555.3-556.25" - process $proc$libresoc.v:555$94 - assign { } { } - assign $0\clk1[0:0] \clk1$next - sync posedge \pllclk_clk - update \clk1 $0\clk1[0:0] - end - attribute \src "libresoc.v:557.3-558.25" - process $proc$libresoc.v:557$95 - assign { } { } - assign $0\clk3[0:0] \clk3$next - sync posedge \pllclk_clk - update \clk3 $0\clk3[0:0] - end - attribute \src "libresoc.v:559.3-560.33" - process $proc$libresoc.v:559$96 - assign { } { } - assign $0\counter3[1:0] \counter3$next - sync posedge \pllclk_clk - update \counter3 $0\counter3[1:0] - end - attribute \src "libresoc.v:561.3-562.25" - process $proc$libresoc.v:561$97 - assign { } { } - assign $0\clk2[0:0] \clk2$next - sync posedge \pllclk_clk - update \clk2 $0\clk2[0:0] - end - attribute \src "libresoc.v:563.3-564.25" - process $proc$libresoc.v:563$98 - assign { } { } - assign $0\clk4[0:0] \clk4$next - sync posedge \pllclk_clk - update \clk4 $0\clk4[0:0] - end - attribute \src "libresoc.v:565.3-573.6" - process $proc$libresoc.v:565$99 - assign { } { } - assign { } { } - assign $0\clk4$next[0:0]$100 $1\clk4$next[0:0]$101 - attribute \src "libresoc.v:566.5-566.29" - switch \initial - attribute \src "libresoc.v:566.9-566.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \pllclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\clk4$next[0:0]$101 1'0 - case - assign $1\clk4$next[0:0]$101 \$1 - end - sync always - update \clk4$next $0\clk4$next[0:0]$100 - end - attribute \src "libresoc.v:574.3-588.6" - process $proc$libresoc.v:574$102 - assign { } { } - assign { } { } - assign { } { } - assign $0\clk2$next[0:0]$103 $2\clk2$next[0:0]$105 - attribute \src "libresoc.v:575.5-575.29" - switch \initial - attribute \src "libresoc.v:575.9-575.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:56" - switch \clk4 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\clk2$next[0:0]$104 \$3 - case - assign $1\clk2$next[0:0]$104 \clk2 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \pllclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\clk2$next[0:0]$105 1'0 - case - assign $2\clk2$next[0:0]$105 $1\clk2$next[0:0]$104 - end - sync always - update \clk2$next $0\clk2$next[0:0]$103 - end - attribute \src "libresoc.v:589.3-605.6" - process $proc$libresoc.v:589$106 - assign { } { } - assign { } { } - assign $0\counter3$next[1:0]$107 $2\counter3$next[1:0]$109 - attribute \src "libresoc.v:590.5-590.29" - switch \initial - attribute \src "libresoc.v:590.9-590.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" - switch \$5 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\counter3$next[1:0]$108 2'00 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\counter3$next[1:0]$108 \$7 [1:0] - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \pllclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\counter3$next[1:0]$109 2'00 - case - assign $2\counter3$next[1:0]$109 $1\counter3$next[1:0]$108 - end - sync always - update \counter3$next $0\counter3$next[1:0]$107 - end - attribute \src "libresoc.v:606.3-620.6" - process $proc$libresoc.v:606$110 - assign { } { } - assign { } { } - assign { } { } - assign $0\clk3$next[0:0]$111 $2\clk3$next[0:0]$113 - attribute \src "libresoc.v:607.5-607.29" - switch \initial - attribute \src "libresoc.v:607.9-607.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" - switch \$10 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\clk3$next[0:0]$112 \$12 - case - assign $1\clk3$next[0:0]$112 \clk3 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \pllclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\clk3$next[0:0]$113 1'0 - case - assign $2\clk3$next[0:0]$113 $1\clk3$next[0:0]$112 - end - sync always - update \clk3$next $0\clk3$next[0:0]$111 - end - attribute \src "libresoc.v:621.3-640.6" - process $proc$libresoc.v:621$114 - assign { } { } - assign { } { } - assign { } { } - assign $0\clk1$next[0:0]$115 $3\clk1$next[0:0]$118 - attribute \src "libresoc.v:622.5-622.29" - switch \initial - attribute \src "libresoc.v:622.9-622.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" - switch \$14 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\clk1$next[0:0]$116 $2\clk1$next[0:0]$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:61" - switch \clk3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\clk1$next[0:0]$117 \$16 - case - assign $2\clk1$next[0:0]$117 \clk1 - end - case - assign $1\clk1$next[0:0]$116 \clk1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \pllclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\clk1$next[0:0]$118 1'0 - case - assign $3\clk1$next[0:0]$118 $1\clk1$next[0:0]$116 - end - sync always - update \clk1$next $0\clk1$next[0:0]$115 - end - attribute \src "libresoc.v:641.3-663.6" - process $proc$libresoc.v:641$119 - assign { } { } - assign { } { } - assign $0\core_clk_o[0:0] $1\core_clk_o[0:0] - attribute \src "libresoc.v:642.5-642.29" - switch \initial - attribute \src "libresoc.v:642.9-642.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:67" - switch \clk_sel_i - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\core_clk_o[0:0] \clk0 - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\core_clk_o[0:0] \clk1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\core_clk_o[0:0] \clk2 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\core_clk_o[0:0] \clk3 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\core_clk_o[0:0] \clk4 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\core_clk_o[0:0] \clk5 - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\core_clk_o[0:0] \clk6 - attribute \src "libresoc.v:0.0-0.0" - case 3'--- - assign { } { } - assign $1\core_clk_o[0:0] \clk7 - case - assign $1\core_clk_o[0:0] 1'0 - end - sync always - update \core_clk_o $0\core_clk_o[0:0] - end - connect \$10 $eq$libresoc.v:547$86_Y - connect \$12 $not$libresoc.v:548$87_Y - connect \$14 $eq$libresoc.v:549$88_Y - connect \$16 $not$libresoc.v:550$89_Y - connect \$1 $not$libresoc.v:551$90_Y - connect \$3 $not$libresoc.v:552$91_Y - connect \$5 $eq$libresoc.v:553$92_Y - connect \$8 $add$libresoc.v:554$93_Y - connect \$7 \$8 - connect \clk5 1'0 - connect \pll_48_o \clk1 - connect \clk7 1'1 - connect \clk6 1'0 - connect \clk0 \clk_24_i - connect \pllclk_rst \rst -end -attribute \src "libresoc.v:675.1-1389.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dbg" -attribute \generator "nMigen" -module \dbg - attribute \src "libresoc.v:1205.3-1214.6" - wire $0\d_cr_req[0:0] - attribute \src "libresoc.v:1012.3-1021.6" - wire $0\d_gpr_req[0:0] - attribute \src "libresoc.v:1215.3-1224.6" - wire $0\d_xer_req[0:0] - attribute \src "libresoc.v:994.3-1011.6" - wire $0\dmi_ack_o[0:0] - attribute \src "libresoc.v:1225.3-1255.6" - wire width 64 $0\dmi_dout[63:0] - attribute \src "libresoc.v:1196.3-1204.6" - wire $0\dmi_read_log_data$next[0:0]$239 - attribute \src "libresoc.v:972.3-973.51" - wire $0\dmi_read_log_data[0:0] - attribute \src "libresoc.v:1187.3-1195.6" - wire $0\dmi_read_log_data_1$next[0:0]$236 - attribute \src "libresoc.v:974.3-975.55" - wire $0\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:1022.3-1030.6" - wire $0\dmi_req_i_1$next[0:0]$202 - attribute \src "libresoc.v:984.3-985.39" - wire $0\dmi_req_i_1[0:0] - attribute \src "libresoc.v:1346.3-1379.6" - wire $0\do_dmi_log_rd$next[0:0]$266 - attribute \src "libresoc.v:986.3-987.43" - wire $0\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:1316.3-1345.6" - wire $0\do_icreset$next[0:0]$259 - attribute \src "libresoc.v:988.3-989.37" - wire $0\do_icreset[0:0] - attribute \src "libresoc.v:1286.3-1315.6" - wire $0\do_reset$next[0:0]$252 - attribute \src "libresoc.v:990.3-991.33" - wire $0\do_reset[0:0] - attribute \src "libresoc.v:1256.3-1285.6" - wire $0\do_step$next[0:0]$245 - attribute \src "libresoc.v:992.3-993.31" - wire $0\do_step[0:0] - attribute \src "libresoc.v:1125.3-1152.6" - wire width 7 $0\gspr_index$next[6:0]$224 - attribute \src "libresoc.v:978.3-979.37" - wire width 7 $0\gspr_index[6:0] - attribute \src "libresoc.v:676.7-676.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:1153.3-1186.6" - wire width 32 $0\log_dmi_addr$next[31:0]$230 - attribute \src "libresoc.v:976.3-977.41" - wire width 32 $0\log_dmi_addr[31:0] - attribute \src "libresoc.v:1081.3-1124.6" - wire $0\stopping$next[0:0]$215 - attribute \src "libresoc.v:980.3-981.33" - wire $0\stopping[0:0] - attribute \src "libresoc.v:1031.3-1080.6" - wire $0\terminated$next[0:0]$205 - attribute \src "libresoc.v:982.3-983.37" - wire $0\terminated[0:0] - attribute \src "libresoc.v:1205.3-1214.6" - wire $1\d_cr_req[0:0] - attribute \src "libresoc.v:1012.3-1021.6" - wire $1\d_gpr_req[0:0] - attribute \src "libresoc.v:1215.3-1224.6" - wire $1\d_xer_req[0:0] - attribute \src "libresoc.v:994.3-1011.6" - wire $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:1225.3-1255.6" - wire width 64 $1\dmi_dout[63:0] - attribute \src "libresoc.v:1196.3-1204.6" - wire $1\dmi_read_log_data$next[0:0]$240 - attribute \src "libresoc.v:847.7-847.31" - wire $1\dmi_read_log_data[0:0] - attribute \src "libresoc.v:1187.3-1195.6" - wire $1\dmi_read_log_data_1$next[0:0]$237 - attribute \src "libresoc.v:851.7-851.33" - wire $1\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:1022.3-1030.6" - wire $1\dmi_req_i_1$next[0:0]$203 - attribute \src "libresoc.v:857.7-857.25" - wire $1\dmi_req_i_1[0:0] - attribute \src "libresoc.v:1346.3-1379.6" - wire $1\do_dmi_log_rd$next[0:0]$267 - attribute \src "libresoc.v:863.7-863.27" - wire $1\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:1316.3-1345.6" - wire $1\do_icreset$next[0:0]$260 - attribute \src "libresoc.v:867.7-867.24" - wire $1\do_icreset[0:0] - attribute \src "libresoc.v:1286.3-1315.6" - wire $1\do_reset$next[0:0]$253 - attribute \src "libresoc.v:871.7-871.22" - wire $1\do_reset[0:0] - attribute \src "libresoc.v:1256.3-1285.6" - wire $1\do_step$next[0:0]$246 - attribute \src "libresoc.v:875.7-875.21" - wire $1\do_step[0:0] - attribute \src "libresoc.v:1125.3-1152.6" - wire width 7 $1\gspr_index$next[6:0]$225 - attribute \src "libresoc.v:879.13-879.31" - wire width 7 $1\gspr_index[6:0] - attribute \src "libresoc.v:1153.3-1186.6" - wire width 32 $1\log_dmi_addr$next[31:0]$231 - attribute \src "libresoc.v:889.14-889.34" - wire width 32 $1\log_dmi_addr[31:0] - attribute \src "libresoc.v:1081.3-1124.6" - wire $1\stopping$next[0:0]$216 - attribute \src "libresoc.v:899.7-899.22" - wire $1\stopping[0:0] - attribute \src "libresoc.v:1031.3-1080.6" - wire $1\terminated$next[0:0]$206 - attribute \src "libresoc.v:905.7-905.24" - wire $1\terminated[0:0] - attribute \src "libresoc.v:1346.3-1379.6" - wire $2\do_dmi_log_rd$next[0:0]$268 - attribute \src "libresoc.v:1316.3-1345.6" - wire $2\do_icreset$next[0:0]$261 - attribute \src "libresoc.v:1286.3-1315.6" - wire $2\do_reset$next[0:0]$254 - attribute \src "libresoc.v:1256.3-1285.6" - wire $2\do_step$next[0:0]$247 - attribute \src "libresoc.v:1125.3-1152.6" - wire width 7 $2\gspr_index$next[6:0]$226 - attribute \src "libresoc.v:1153.3-1186.6" - wire width 32 $2\log_dmi_addr$next[31:0]$232 - attribute \src "libresoc.v:1081.3-1124.6" - wire $2\stopping$next[0:0]$217 - attribute \src "libresoc.v:1031.3-1080.6" - wire $2\terminated$next[0:0]$207 - attribute \src "libresoc.v:1346.3-1379.6" - wire $3\do_dmi_log_rd$next[0:0]$269 - attribute \src "libresoc.v:1316.3-1345.6" - wire $3\do_icreset$next[0:0]$262 - attribute \src "libresoc.v:1286.3-1315.6" - wire $3\do_reset$next[0:0]$255 - attribute \src "libresoc.v:1256.3-1285.6" - wire $3\do_step$next[0:0]$248 - attribute \src "libresoc.v:1125.3-1152.6" - wire width 7 $3\gspr_index$next[6:0]$227 - attribute \src "libresoc.v:1153.3-1186.6" - wire width 32 $3\log_dmi_addr$next[31:0]$233 - attribute \src "libresoc.v:1081.3-1124.6" - wire $3\stopping$next[0:0]$218 - attribute \src "libresoc.v:1031.3-1080.6" - wire $3\terminated$next[0:0]$208 - attribute \src "libresoc.v:1346.3-1379.6" - wire $4\do_dmi_log_rd$next[0:0]$270 - attribute \src "libresoc.v:1316.3-1345.6" - wire $4\do_icreset$next[0:0]$263 - attribute \src "libresoc.v:1286.3-1315.6" - wire $4\do_reset$next[0:0]$256 - attribute \src "libresoc.v:1256.3-1285.6" - wire $4\do_step$next[0:0]$249 - attribute \src "libresoc.v:1125.3-1152.6" - wire width 7 $4\gspr_index$next[6:0]$228 - attribute \src "libresoc.v:1153.3-1186.6" - wire width 32 $4\log_dmi_addr$next[31:0]$234 - attribute \src "libresoc.v:1081.3-1124.6" - wire $4\stopping$next[0:0]$219 - attribute \src "libresoc.v:1031.3-1080.6" - wire $4\terminated$next[0:0]$209 - attribute \src "libresoc.v:1316.3-1345.6" - wire $5\do_icreset$next[0:0]$264 - attribute \src "libresoc.v:1286.3-1315.6" - wire $5\do_reset$next[0:0]$257 - attribute \src "libresoc.v:1256.3-1285.6" - wire $5\do_step$next[0:0]$250 - attribute \src "libresoc.v:1081.3-1124.6" - wire $5\stopping$next[0:0]$220 - attribute \src "libresoc.v:1031.3-1080.6" - wire $5\terminated$next[0:0]$210 - attribute \src "libresoc.v:1081.3-1124.6" - wire $6\stopping$next[0:0]$221 - attribute \src "libresoc.v:1031.3-1080.6" - wire $6\terminated$next[0:0]$211 - attribute \src "libresoc.v:1081.3-1124.6" - wire $7\stopping$next[0:0]$222 - attribute \src "libresoc.v:1031.3-1080.6" - wire $7\terminated$next[0:0]$212 - attribute \src "libresoc.v:1031.3-1080.6" - wire $8\terminated$next[0:0]$213 - attribute \src "libresoc.v:919.19-919.110" - wire width 3 $add$libresoc.v:919$135_Y - attribute \src "libresoc.v:910.17-910.109" - wire $and$libresoc.v:910$126_Y - attribute \src "libresoc.v:913.19-913.103" - wire $and$libresoc.v:913$129_Y - attribute \src "libresoc.v:915.19-915.113" - wire $and$libresoc.v:915$131_Y - attribute \src "libresoc.v:922.19-922.103" - wire $and$libresoc.v:922$138_Y - attribute \src "libresoc.v:924.19-924.102" - wire $and$libresoc.v:924$140_Y - attribute \src "libresoc.v:929.18-929.101" - wire $and$libresoc.v:929$145_Y - attribute \src "libresoc.v:931.18-931.111" - wire $and$libresoc.v:931$147_Y - attribute \src "libresoc.v:936.18-936.101" - wire $and$libresoc.v:936$152_Y - attribute \src "libresoc.v:938.18-938.111" - wire $and$libresoc.v:938$154_Y - attribute \src "libresoc.v:944.18-944.101" - wire $and$libresoc.v:944$160_Y - attribute \src "libresoc.v:946.18-946.111" - wire $and$libresoc.v:946$162_Y - attribute \src "libresoc.v:950.17-950.99" - wire $and$libresoc.v:950$166_Y - attribute \src "libresoc.v:952.18-952.101" - wire $and$libresoc.v:952$168_Y - attribute \src "libresoc.v:954.18-954.111" - wire $and$libresoc.v:954$170_Y - attribute \src "libresoc.v:959.18-959.101" - wire $and$libresoc.v:959$175_Y - attribute \src "libresoc.v:962.18-962.111" - wire $and$libresoc.v:962$178_Y - attribute \src "libresoc.v:967.18-967.101" - wire $and$libresoc.v:967$183_Y - attribute \src "libresoc.v:969.18-969.111" - wire $and$libresoc.v:969$185_Y - attribute \src "libresoc.v:911.18-911.103" - wire $eq$libresoc.v:911$127_Y - attribute \src "libresoc.v:916.19-916.104" - wire $eq$libresoc.v:916$132_Y - attribute \src "libresoc.v:917.19-917.104" - wire $eq$libresoc.v:917$133_Y - attribute \src "libresoc.v:918.19-918.104" - wire $eq$libresoc.v:918$134_Y - attribute \src "libresoc.v:920.19-920.104" - wire $eq$libresoc.v:920$136_Y - attribute \src "libresoc.v:921.18-921.103" - wire $eq$libresoc.v:921$137_Y - attribute \src "libresoc.v:925.18-925.103" - wire $eq$libresoc.v:925$141_Y - attribute \src "libresoc.v:926.18-926.103" - wire $eq$libresoc.v:926$142_Y - attribute \src "libresoc.v:932.18-932.103" - wire $eq$libresoc.v:932$148_Y - attribute \src "libresoc.v:933.18-933.103" - wire $eq$libresoc.v:933$149_Y - attribute \src "libresoc.v:934.18-934.103" - wire $eq$libresoc.v:934$150_Y - attribute \src "libresoc.v:940.18-940.103" - wire $eq$libresoc.v:940$156_Y - attribute \src "libresoc.v:941.18-941.103" - wire $eq$libresoc.v:941$157_Y - attribute \src "libresoc.v:942.18-942.103" - wire $eq$libresoc.v:942$158_Y - attribute \src "libresoc.v:947.18-947.103" - wire $eq$libresoc.v:947$163_Y - attribute \src "libresoc.v:948.18-948.103" - wire $eq$libresoc.v:948$164_Y - attribute \src "libresoc.v:949.18-949.103" - wire $eq$libresoc.v:949$165_Y - attribute \src "libresoc.v:955.18-955.103" - wire $eq$libresoc.v:955$171_Y - attribute \src "libresoc.v:956.18-956.103" - wire $eq$libresoc.v:956$172_Y - attribute \src "libresoc.v:957.18-957.103" - wire $eq$libresoc.v:957$173_Y - attribute \src "libresoc.v:963.18-963.103" - wire $eq$libresoc.v:963$179_Y - attribute \src "libresoc.v:964.18-964.103" - wire $eq$libresoc.v:964$180_Y - attribute \src "libresoc.v:965.18-965.103" - wire $eq$libresoc.v:965$181_Y - attribute \src "libresoc.v:970.18-970.103" - wire $eq$libresoc.v:970$186_Y - attribute \src "libresoc.v:971.18-971.103" - wire $eq$libresoc.v:971$187_Y - attribute \src "libresoc.v:912.19-912.99" - wire $not$libresoc.v:912$128_Y - attribute \src "libresoc.v:914.19-914.105" - wire $not$libresoc.v:914$130_Y - attribute \src "libresoc.v:923.19-923.95" - wire $not$libresoc.v:923$139_Y - attribute \src "libresoc.v:927.18-927.98" - wire $not$libresoc.v:927$143_Y - attribute \src "libresoc.v:930.18-930.104" - wire $not$libresoc.v:930$146_Y - attribute \src "libresoc.v:935.18-935.98" - wire $not$libresoc.v:935$151_Y - attribute \src "libresoc.v:937.18-937.104" - wire $not$libresoc.v:937$153_Y - attribute \src "libresoc.v:939.17-939.97" - wire $not$libresoc.v:939$155_Y - attribute \src "libresoc.v:943.18-943.98" - wire $not$libresoc.v:943$159_Y - attribute \src "libresoc.v:945.18-945.104" - wire $not$libresoc.v:945$161_Y - attribute \src "libresoc.v:951.18-951.98" - wire $not$libresoc.v:951$167_Y - attribute \src "libresoc.v:953.18-953.104" - wire $not$libresoc.v:953$169_Y - attribute \src "libresoc.v:958.18-958.98" - wire $not$libresoc.v:958$174_Y - attribute \src "libresoc.v:960.18-960.104" - wire $not$libresoc.v:960$176_Y - attribute \src "libresoc.v:961.17-961.103" - wire $not$libresoc.v:961$177_Y - attribute \src "libresoc.v:966.18-966.98" - wire $not$libresoc.v:966$182_Y - attribute \src "libresoc.v:968.18-968.104" - wire $not$libresoc.v:968$184_Y - attribute \src "libresoc.v:928.17-928.126" - wire width 64 $pos$libresoc.v:928$144_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170" - wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - wire \$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - wire \$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - wire \$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - wire width 3 \$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - wire width 3 \$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" - wire \$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" - wire \$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" - wire \$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" - wire \$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - wire \$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - wire \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - wire \$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - wire \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - wire \$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - wire \$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - wire \$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 input 10 \core_dbg_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 input 9 \core_dbg_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" - wire output 7 \core_rst_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:97" - wire output 11 \core_stop_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" - wire input 12 \core_stopped_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" - wire input 19 \d_cr_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" - wire width 64 input 18 \d_cr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" - wire output 17 \d_cr_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" - wire input 16 \d_gpr_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" - wire width 7 output 14 \d_gpr_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" - wire width 64 input 15 \d_gpr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" - wire output 13 \d_gpr_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" - wire input 22 \d_xer_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" - wire width 64 input 21 \d_xer_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" - wire output 20 \d_xer_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" - wire output 4 \dmi_ack_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 4 input 24 \dmi_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 64 input 3 \dmi_din - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" - wire width 64 output 5 \dmi_dout - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" - wire \dmi_read_log_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" - wire \dmi_read_log_data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" - wire \dmi_read_log_data_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" - wire \dmi_read_log_data_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" - wire input 1 \dmi_req_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" - wire \dmi_req_i_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" - wire \dmi_req_i_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" - wire input 2 \dmi_we_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" - wire \do_dmi_log_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" - wire \do_dmi_log_rd$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" - wire \do_icreset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" - wire \do_icreset$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" - wire \do_reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" - wire \do_reset$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" - wire \do_step - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" - wire \do_step$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143" - wire width 7 \gspr_index - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143" - wire width 7 \gspr_index$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" - wire \icache_rst_o - attribute \src "libresoc.v:676.7-676.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" - wire input 6 \intclk_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" - wire input 23 \intclk_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145" - wire width 32 \log_dmi_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145" - wire width 32 \log_dmi_addr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" - wire width 64 \log_dmi_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:119" - wire width 32 \log_write_addr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:134" - wire width 64 \stat_reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" - wire \stopping - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" - wire \stopping$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102" - wire input 8 \terminate_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" - wire \terminated - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" - wire \terminated$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:122" - wire \terminated_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $add $add$libresoc.v:919$135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \log_dmi_addr [1:0] - connect \B 1'1 - connect \Y $add$libresoc.v:919$135_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:910$126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$7 - connect \Y $and$libresoc.v:910$126_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:913$129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$101 - connect \Y $and$libresoc.v:913$129_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:915$131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$105 - connect \Y $and$libresoc.v:915$131_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" - cell $and $and$libresoc.v:922$138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$118 - connect \Y $and$libresoc.v:922$138_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" - cell $and $and$libresoc.v:924$140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \stopping - connect \B \$122 - connect \Y $and$libresoc.v:924$140_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:929$145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$17 - connect \Y $and$libresoc.v:929$145_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:931$147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$21 - connect \Y $and$libresoc.v:931$147_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:936$152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$31 - connect \Y $and$libresoc.v:936$152_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:938$154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$35 - connect \Y $and$libresoc.v:938$154_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:944$160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$45 - connect \Y $and$libresoc.v:944$160_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:946$162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$49 - connect \Y $and$libresoc.v:946$162_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:950$166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$3 - connect \Y $and$libresoc.v:950$166_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:952$168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$59 - connect \Y $and$libresoc.v:952$168_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:954$170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$63 - connect \Y $and$libresoc.v:954$170_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:959$175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$73 - connect \Y $and$libresoc.v:959$175_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:962$178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$77 - connect \Y $and$libresoc.v:962$178_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:967$183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$87 - connect \Y $and$libresoc.v:967$183_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:969$185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$91 - connect \Y $and$libresoc.v:969$185_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:911$127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$libresoc.v:911$127_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:916$132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$libresoc.v:916$132_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:917$133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$libresoc.v:917$133_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:918$134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$libresoc.v:918$134_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" - cell $eq $eq$libresoc.v:920$136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'111 - connect \Y $eq$libresoc.v:920$136_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:921$137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$libresoc.v:921$137_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:925$141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$libresoc.v:925$141_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:926$142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$libresoc.v:926$142_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:932$148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$libresoc.v:932$148_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:933$149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$libresoc.v:933$149_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:934$150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$libresoc.v:934$150_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:940$156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$libresoc.v:940$156_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:941$157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$libresoc.v:941$157_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:942$158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$libresoc.v:942$158_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:947$163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$libresoc.v:947$163_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:948$164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$libresoc.v:948$164_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:949$165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$libresoc.v:949$165_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:955$171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$libresoc.v:955$171_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:956$172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$libresoc.v:956$172_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:957$173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$libresoc.v:957$173_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:963$179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$libresoc.v:963$179_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:964$180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$libresoc.v:964$180_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:965$181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$libresoc.v:965$181_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:970$186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$libresoc.v:970$186_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:971$187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$libresoc.v:971$187_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:912$128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:912$128_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:914$130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:914$130_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" - cell $not $not$libresoc.v:923$139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \do_step - connect \Y $not$libresoc.v:923$139_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:927$143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:927$143_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:930$146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:930$146_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:935$151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:935$151_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:937$153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:937$153_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:939$155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:939$155_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:943$159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:943$159_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:945$161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:945$161_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:951$167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:951$167_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:953$169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:953$169_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:958$174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:958$174_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:960$176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:960$176_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:961$177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:961$177_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:966$182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:966$182_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:968$184 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:968$184_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170" - cell $pos $pos$libresoc.v:928$144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } - connect \Y $pos$libresoc.v:928$144_Y - end - attribute \src "libresoc.v:1012.3-1021.6" - process $proc$libresoc.v:1012$200 - assign { } { } - assign { } { } - assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] - attribute \src "libresoc.v:1013.5-1013.29" - switch \initial - attribute \src "libresoc.v:1013.9-1013.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" - switch \dmi_addr_i - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\d_gpr_req[0:0] \dmi_req_i - case - assign $1\d_gpr_req[0:0] 1'0 - end - sync always - update \d_gpr_req $0\d_gpr_req[0:0] - end - attribute \src "libresoc.v:1022.3-1030.6" - process $proc$libresoc.v:1022$201 - assign { } { } - assign { } { } - assign $0\dmi_req_i_1$next[0:0]$202 $1\dmi_req_i_1$next[0:0]$203 - attribute \src "libresoc.v:1023.5-1023.29" - switch \initial - attribute \src "libresoc.v:1023.9-1023.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi_req_i_1$next[0:0]$203 1'0 - case - assign $1\dmi_req_i_1$next[0:0]$203 \dmi_req_i - end - sync always - update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$202 - end - attribute \src "libresoc.v:1031.3-1080.6" - process $proc$libresoc.v:1031$204 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\terminated$next[0:0]$205 $8\terminated$next[0:0]$213 - attribute \src "libresoc.v:1032.5-1032.29" - switch \initial - attribute \src "libresoc.v:1032.9-1032.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$65 \$61 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\terminated$next[0:0]$206 $2\terminated$next[0:0]$207 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\terminated$next[0:0]$207 $3\terminated$next[0:0]$208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$71 \$69 \$67 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign { } { } - assign { } { } - assign $3\terminated$next[0:0]$208 $6\terminated$next[0:0]$211 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" - switch \dmi_din [1] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\terminated$next[0:0]$209 1'0 - case - assign $4\terminated$next[0:0]$209 \terminated - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" - switch \dmi_din [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\terminated$next[0:0]$210 1'0 - case - assign $5\terminated$next[0:0]$210 $4\terminated$next[0:0]$209 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" - switch \dmi_din [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\terminated$next[0:0]$211 1'0 - case - assign $6\terminated$next[0:0]$211 $5\terminated$next[0:0]$210 - end - case - assign $3\terminated$next[0:0]$208 \terminated - end - case - assign $2\terminated$next[0:0]$207 \terminated - end - case - assign $1\terminated$next[0:0]$206 \terminated - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" - switch \terminate_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\terminated$next[0:0]$212 1'1 - case - assign $7\terminated$next[0:0]$212 $1\terminated$next[0:0]$206 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $8\terminated$next[0:0]$213 1'0 - case - assign $8\terminated$next[0:0]$213 $7\terminated$next[0:0]$212 - end - sync always - update \terminated$next $0\terminated$next[0:0]$205 - end - attribute \src "libresoc.v:1081.3-1124.6" - process $proc$libresoc.v:1081$214 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\stopping$next[0:0]$215 $7\stopping$next[0:0]$222 - attribute \src "libresoc.v:1082.5-1082.29" - switch \initial - attribute \src "libresoc.v:1082.9-1082.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$79 \$75 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\stopping$next[0:0]$216 $2\stopping$next[0:0]$217 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\stopping$next[0:0]$217 $3\stopping$next[0:0]$218 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$85 \$83 \$81 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign { } { } - assign $3\stopping$next[0:0]$218 $5\stopping$next[0:0]$220 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" - switch \dmi_din [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\stopping$next[0:0]$219 1'1 - case - assign $4\stopping$next[0:0]$219 \stopping - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" - switch \dmi_din [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\stopping$next[0:0]$220 1'0 - case - assign $5\stopping$next[0:0]$220 $4\stopping$next[0:0]$219 - end - case - assign $3\stopping$next[0:0]$218 \stopping - end - case - assign $2\stopping$next[0:0]$217 \stopping - end - case - assign $1\stopping$next[0:0]$216 \stopping - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" - switch \terminate_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\stopping$next[0:0]$221 1'1 - case - assign $6\stopping$next[0:0]$221 $1\stopping$next[0:0]$216 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\stopping$next[0:0]$222 1'0 - case - assign $7\stopping$next[0:0]$222 $6\stopping$next[0:0]$221 - end - sync always - update \stopping$next $0\stopping$next[0:0]$215 - end - attribute \src "libresoc.v:1125.3-1152.6" - process $proc$libresoc.v:1125$223 - assign { } { } - assign { } { } - assign { } { } - assign $0\gspr_index$next[6:0]$224 $4\gspr_index$next[6:0]$228 - attribute \src "libresoc.v:1126.5-1126.29" - switch \initial - attribute \src "libresoc.v:1126.9-1126.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$93 \$89 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\gspr_index$next[6:0]$225 $2\gspr_index$next[6:0]$226 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\gspr_index$next[6:0]$226 $3\gspr_index$next[6:0]$227 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$99 \$97 \$95 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $3\gspr_index$next[6:0]$227 \gspr_index - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $3\gspr_index$next[6:0]$227 \dmi_din [6:0] - case - assign $3\gspr_index$next[6:0]$227 \gspr_index - end - case - assign $2\gspr_index$next[6:0]$226 \gspr_index - end - case - assign $1\gspr_index$next[6:0]$225 \gspr_index - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\gspr_index$next[6:0]$228 7'0000000 - case - assign $4\gspr_index$next[6:0]$228 $1\gspr_index$next[6:0]$225 - end - sync always - update \gspr_index$next $0\gspr_index$next[6:0]$224 - end - attribute \src "libresoc.v:1153.3-1186.6" - process $proc$libresoc.v:1153$229 - assign { } { } - assign { } { } - assign { } { } - assign $0\log_dmi_addr$next[31:0]$230 $4\log_dmi_addr$next[31:0]$234 - attribute \src "libresoc.v:1154.5-1154.29" - switch \initial - attribute \src "libresoc.v:1154.9-1154.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$107 \$103 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\log_dmi_addr$next[31:0]$231 $2\log_dmi_addr$next[31:0]$232 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\log_dmi_addr$next[31:0]$232 $3\log_dmi_addr$next[31:0]$233 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$113 \$111 \$109 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $3\log_dmi_addr$next[31:0]$233 \log_dmi_addr - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $3\log_dmi_addr$next[31:0]$233 \log_dmi_addr - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $3\log_dmi_addr$next[31:0]$233 \dmi_din [31:0] - case - assign $3\log_dmi_addr$next[31:0]$233 \log_dmi_addr - end - case - assign $2\log_dmi_addr$next[31:0]$232 \log_dmi_addr - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign $1\log_dmi_addr$next[31:0]$231 [31:2] \log_dmi_addr [31:2] - assign $1\log_dmi_addr$next[31:0]$231 [1:0] \$115 [1:0] - case - assign $1\log_dmi_addr$next[31:0]$231 \log_dmi_addr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\log_dmi_addr$next[31:0]$234 0 - case - assign $4\log_dmi_addr$next[31:0]$234 $1\log_dmi_addr$next[31:0]$231 - end - sync always - update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$230 - end - attribute \src "libresoc.v:1187.3-1195.6" - process $proc$libresoc.v:1187$235 - assign { } { } - assign { } { } - assign $0\dmi_read_log_data_1$next[0:0]$236 $1\dmi_read_log_data_1$next[0:0]$237 - attribute \src "libresoc.v:1188.5-1188.29" - switch \initial - attribute \src "libresoc.v:1188.9-1188.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi_read_log_data_1$next[0:0]$237 1'0 - case - assign $1\dmi_read_log_data_1$next[0:0]$237 \dmi_read_log_data - end - sync always - update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$236 - end - attribute \src "libresoc.v:1196.3-1204.6" - process $proc$libresoc.v:1196$238 - assign { } { } - assign { } { } - assign $0\dmi_read_log_data$next[0:0]$239 $1\dmi_read_log_data$next[0:0]$240 - attribute \src "libresoc.v:1197.5-1197.29" - switch \initial - attribute \src "libresoc.v:1197.9-1197.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi_read_log_data$next[0:0]$240 1'0 - case - assign $1\dmi_read_log_data$next[0:0]$240 \$120 - end - sync always - update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$239 - end - attribute \src "libresoc.v:1205.3-1214.6" - process $proc$libresoc.v:1205$241 - assign { } { } - assign { } { } - assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] - attribute \src "libresoc.v:1206.5-1206.29" - switch \initial - attribute \src "libresoc.v:1206.9-1206.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" - switch \dmi_addr_i - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\d_cr_req[0:0] \dmi_req_i - case - assign $1\d_cr_req[0:0] 1'0 - end - sync always - update \d_cr_req $0\d_cr_req[0:0] - end - attribute \src "libresoc.v:1215.3-1224.6" - process $proc$libresoc.v:1215$242 - assign { } { } - assign { } { } - assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] - attribute \src "libresoc.v:1216.5-1216.29" - switch \initial - attribute \src "libresoc.v:1216.9-1216.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" - switch \dmi_addr_i - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\d_xer_req[0:0] \dmi_req_i - case - assign $1\d_xer_req[0:0] 1'0 - end - sync always - update \d_xer_req $0\d_xer_req[0:0] - end - attribute \src "libresoc.v:1225.3-1255.6" - process $proc$libresoc.v:1225$243 - assign { } { } - assign { } { } - assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] - attribute \src "libresoc.v:1226.5-1226.29" - switch \initial - attribute \src "libresoc.v:1226.9-1226.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:173" - switch \dmi_addr_i - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dmi_dout[63:0] \stat_reg - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dmi_dout[63:0] \core_dbg_pc - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dmi_dout[63:0] \core_dbg_msr - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dmi_dout[63:0] \d_gpr_data - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dmi_dout[63:0] { \log_write_addr_o \log_dmi_addr } - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dmi_dout[63:0] \log_dmi_data - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dmi_dout[63:0] \d_cr_data - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dmi_dout[63:0] \d_xer_data - case - assign $1\dmi_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dmi_dout $0\dmi_dout[63:0] - end - attribute \src "libresoc.v:1256.3-1285.6" - process $proc$libresoc.v:1256$244 - assign { } { } - assign { } { } - assign { } { } - assign $0\do_step$next[0:0]$245 $5\do_step$next[0:0]$250 - attribute \src "libresoc.v:1257.5-1257.29" - switch \initial - attribute \src "libresoc.v:1257.9-1257.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$9 \$5 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\do_step$next[0:0]$246 $2\do_step$next[0:0]$247 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\do_step$next[0:0]$247 $3\do_step$next[0:0]$248 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$15 \$13 \$11 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $3\do_step$next[0:0]$248 $4\do_step$next[0:0]$249 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" - switch \dmi_din [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\do_step$next[0:0]$249 1'1 - case - assign $4\do_step$next[0:0]$249 1'0 - end - case - assign $3\do_step$next[0:0]$248 1'0 - end - case - assign $2\do_step$next[0:0]$247 1'0 - end - case - assign $1\do_step$next[0:0]$246 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\do_step$next[0:0]$250 1'0 - case - assign $5\do_step$next[0:0]$250 $1\do_step$next[0:0]$246 - end - sync always - update \do_step$next $0\do_step$next[0:0]$245 - end - attribute \src "libresoc.v:1286.3-1315.6" - process $proc$libresoc.v:1286$251 - assign { } { } - assign { } { } - assign { } { } - assign $0\do_reset$next[0:0]$252 $5\do_reset$next[0:0]$257 - attribute \src "libresoc.v:1287.5-1287.29" - switch \initial - attribute \src "libresoc.v:1287.9-1287.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$23 \$19 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\do_reset$next[0:0]$253 $2\do_reset$next[0:0]$254 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\do_reset$next[0:0]$254 $3\do_reset$next[0:0]$255 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$29 \$27 \$25 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $3\do_reset$next[0:0]$255 $4\do_reset$next[0:0]$256 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" - switch \dmi_din [1] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\do_reset$next[0:0]$256 1'1 - case - assign $4\do_reset$next[0:0]$256 1'0 - end - case - assign $3\do_reset$next[0:0]$255 1'0 - end - case - assign $2\do_reset$next[0:0]$254 1'0 - end - case - assign $1\do_reset$next[0:0]$253 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\do_reset$next[0:0]$257 1'0 - case - assign $5\do_reset$next[0:0]$257 $1\do_reset$next[0:0]$253 - end - sync always - update \do_reset$next $0\do_reset$next[0:0]$252 - end - attribute \src "libresoc.v:1316.3-1345.6" - process $proc$libresoc.v:1316$258 - assign { } { } - assign { } { } - assign { } { } - assign $0\do_icreset$next[0:0]$259 $5\do_icreset$next[0:0]$264 - attribute \src "libresoc.v:1317.5-1317.29" - switch \initial - attribute \src "libresoc.v:1317.9-1317.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$37 \$33 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\do_icreset$next[0:0]$260 $2\do_icreset$next[0:0]$261 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\do_icreset$next[0:0]$261 $3\do_icreset$next[0:0]$262 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$43 \$41 \$39 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $3\do_icreset$next[0:0]$262 $4\do_icreset$next[0:0]$263 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" - switch \dmi_din [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\do_icreset$next[0:0]$263 1'1 - case - assign $4\do_icreset$next[0:0]$263 1'0 - end - case - assign $3\do_icreset$next[0:0]$262 1'0 - end - case - assign $2\do_icreset$next[0:0]$261 1'0 - end - case - assign $1\do_icreset$next[0:0]$260 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\do_icreset$next[0:0]$264 1'0 - case - assign $5\do_icreset$next[0:0]$264 $1\do_icreset$next[0:0]$260 - end - sync always - update \do_icreset$next $0\do_icreset$next[0:0]$259 - end - attribute \src "libresoc.v:1346.3-1379.6" - process $proc$libresoc.v:1346$265 - assign { } { } - assign { } { } - assign { } { } - assign $0\do_dmi_log_rd$next[0:0]$266 $4\do_dmi_log_rd$next[0:0]$270 - attribute \src "libresoc.v:1347.5-1347.29" - switch \initial - attribute \src "libresoc.v:1347.9-1347.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$51 \$47 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\do_dmi_log_rd$next[0:0]$267 $2\do_dmi_log_rd$next[0:0]$268 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\do_dmi_log_rd$next[0:0]$268 $3\do_dmi_log_rd$next[0:0]$269 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$57 \$55 \$53 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $3\do_dmi_log_rd$next[0:0]$269 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $3\do_dmi_log_rd$next[0:0]$269 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $3\do_dmi_log_rd$next[0:0]$269 1'1 - case - assign $3\do_dmi_log_rd$next[0:0]$269 1'0 - end - case - assign $2\do_dmi_log_rd$next[0:0]$268 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\do_dmi_log_rd$next[0:0]$267 1'1 - case - assign $1\do_dmi_log_rd$next[0:0]$267 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\do_dmi_log_rd$next[0:0]$270 1'0 - case - assign $4\do_dmi_log_rd$next[0:0]$270 $1\do_dmi_log_rd$next[0:0]$267 - end - sync always - update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$266 - end - attribute \src "libresoc.v:676.7-676.20" - process $proc$libresoc.v:676$271 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:847.7-847.31" - process $proc$libresoc.v:847$272 - assign { } { } - assign $1\dmi_read_log_data[0:0] 1'0 - sync always - sync init - update \dmi_read_log_data $1\dmi_read_log_data[0:0] - end - attribute \src "libresoc.v:851.7-851.33" - process $proc$libresoc.v:851$273 - assign { } { } - assign $1\dmi_read_log_data_1[0:0] 1'0 - sync always - sync init - update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] - end - attribute \src "libresoc.v:857.7-857.25" - process $proc$libresoc.v:857$274 - assign { } { } - assign $1\dmi_req_i_1[0:0] 1'0 - sync always - sync init - update \dmi_req_i_1 $1\dmi_req_i_1[0:0] - end - attribute \src "libresoc.v:863.7-863.27" - process $proc$libresoc.v:863$275 - assign { } { } - assign $1\do_dmi_log_rd[0:0] 1'0 - sync always - sync init - update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] - end - attribute \src "libresoc.v:867.7-867.24" - process $proc$libresoc.v:867$276 - assign { } { } - assign $1\do_icreset[0:0] 1'0 - sync always - sync init - update \do_icreset $1\do_icreset[0:0] - end - attribute \src "libresoc.v:871.7-871.22" - process $proc$libresoc.v:871$277 - assign { } { } - assign $1\do_reset[0:0] 1'0 - sync always - sync init - update \do_reset $1\do_reset[0:0] - end - attribute \src "libresoc.v:875.7-875.21" - process $proc$libresoc.v:875$278 - assign { } { } - assign $1\do_step[0:0] 1'0 - sync always - sync init - update \do_step $1\do_step[0:0] - end - attribute \src "libresoc.v:879.13-879.31" - process $proc$libresoc.v:879$279 - assign { } { } - assign $1\gspr_index[6:0] 7'0000000 - sync always - sync init - update \gspr_index $1\gspr_index[6:0] - end - attribute \src "libresoc.v:889.14-889.34" - process $proc$libresoc.v:889$280 - assign { } { } - assign $1\log_dmi_addr[31:0] 0 - sync always - sync init - update \log_dmi_addr $1\log_dmi_addr[31:0] - end - attribute \src "libresoc.v:899.7-899.22" - process $proc$libresoc.v:899$281 - assign { } { } - assign $1\stopping[0:0] 1'0 - sync always - sync init - update \stopping $1\stopping[0:0] - end - attribute \src "libresoc.v:905.7-905.24" - process $proc$libresoc.v:905$282 - assign { } { } - assign $1\terminated[0:0] 1'0 - sync always - sync init - update \terminated $1\terminated[0:0] - end - attribute \src "libresoc.v:972.3-973.51" - process $proc$libresoc.v:972$188 - assign { } { } - assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next - sync posedge \intclk_clk - update \dmi_read_log_data $0\dmi_read_log_data[0:0] - end - attribute \src "libresoc.v:974.3-975.55" - process $proc$libresoc.v:974$189 - assign { } { } - assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next - sync posedge \intclk_clk - update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] - end - attribute \src "libresoc.v:976.3-977.41" - process $proc$libresoc.v:976$190 - assign { } { } - assign $0\log_dmi_addr[31:0] \log_dmi_addr$next - sync posedge \intclk_clk - update \log_dmi_addr $0\log_dmi_addr[31:0] - end - attribute \src "libresoc.v:978.3-979.37" - process $proc$libresoc.v:978$191 - assign { } { } - assign $0\gspr_index[6:0] \gspr_index$next - sync posedge \intclk_clk - update \gspr_index $0\gspr_index[6:0] - end - attribute \src "libresoc.v:980.3-981.33" - process $proc$libresoc.v:980$192 - assign { } { } - assign $0\stopping[0:0] \stopping$next - sync posedge \intclk_clk - update \stopping $0\stopping[0:0] - end - attribute \src "libresoc.v:982.3-983.37" - process $proc$libresoc.v:982$193 - assign { } { } - assign $0\terminated[0:0] \terminated$next - sync posedge \intclk_clk - update \terminated $0\terminated[0:0] - end - attribute \src "libresoc.v:984.3-985.39" - process $proc$libresoc.v:984$194 - assign { } { } - assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next - sync posedge \intclk_clk - update \dmi_req_i_1 $0\dmi_req_i_1[0:0] - end - attribute \src "libresoc.v:986.3-987.43" - process $proc$libresoc.v:986$195 - assign { } { } - assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next - sync posedge \intclk_clk - update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] - end - attribute \src "libresoc.v:988.3-989.37" - process $proc$libresoc.v:988$196 - assign { } { } - assign $0\do_icreset[0:0] \do_icreset$next - sync posedge \intclk_clk - update \do_icreset $0\do_icreset[0:0] - end - attribute \src "libresoc.v:990.3-991.33" - process $proc$libresoc.v:990$197 - assign { } { } - assign $0\do_reset[0:0] \do_reset$next - sync posedge \intclk_clk - update \do_reset $0\do_reset[0:0] - end - attribute \src "libresoc.v:992.3-993.31" - process $proc$libresoc.v:992$198 - assign { } { } - assign $0\do_step[0:0] \do_step$next - sync posedge \intclk_clk - update \do_step $0\do_step[0:0] - end - attribute \src "libresoc.v:994.3-1011.6" - process $proc$libresoc.v:994$199 - assign { } { } - assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:995.5-995.29" - switch \initial - attribute \src "libresoc.v:995.9-995.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" - switch \dmi_addr_i - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dmi_ack_o[0:0] \d_gpr_ack - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dmi_ack_o[0:0] \d_cr_ack - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dmi_ack_o[0:0] \d_xer_ack - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\dmi_ack_o[0:0] \dmi_req_i - end - sync always - update \dmi_ack_o $0\dmi_ack_o[0:0] - end - connect \$9 $and$libresoc.v:910$126_Y - connect \$99 $eq$libresoc.v:911$127_Y - connect \$101 $not$libresoc.v:912$128_Y - connect \$103 $and$libresoc.v:913$129_Y - connect \$105 $not$libresoc.v:914$130_Y - connect \$107 $and$libresoc.v:915$131_Y - connect \$109 $eq$libresoc.v:916$132_Y - connect \$111 $eq$libresoc.v:917$133_Y - connect \$113 $eq$libresoc.v:918$134_Y - connect \$116 $add$libresoc.v:919$135_Y - connect \$118 $eq$libresoc.v:920$136_Y - connect \$11 $eq$libresoc.v:921$137_Y - connect \$120 $and$libresoc.v:922$138_Y - connect \$122 $not$libresoc.v:923$139_Y - connect \$124 $and$libresoc.v:924$140_Y - connect \$13 $eq$libresoc.v:925$141_Y - connect \$15 $eq$libresoc.v:926$142_Y - connect \$17 $not$libresoc.v:927$143_Y - connect \$1 $pos$libresoc.v:928$144_Y - connect \$19 $and$libresoc.v:929$145_Y - connect \$21 $not$libresoc.v:930$146_Y - connect \$23 $and$libresoc.v:931$147_Y - connect \$25 $eq$libresoc.v:932$148_Y - connect \$27 $eq$libresoc.v:933$149_Y - connect \$29 $eq$libresoc.v:934$150_Y - connect \$31 $not$libresoc.v:935$151_Y - connect \$33 $and$libresoc.v:936$152_Y - connect \$35 $not$libresoc.v:937$153_Y - connect \$37 $and$libresoc.v:938$154_Y - connect \$3 $not$libresoc.v:939$155_Y - connect \$39 $eq$libresoc.v:940$156_Y - connect \$41 $eq$libresoc.v:941$157_Y - connect \$43 $eq$libresoc.v:942$158_Y - connect \$45 $not$libresoc.v:943$159_Y - connect \$47 $and$libresoc.v:944$160_Y - connect \$49 $not$libresoc.v:945$161_Y - connect \$51 $and$libresoc.v:946$162_Y - connect \$53 $eq$libresoc.v:947$163_Y - connect \$55 $eq$libresoc.v:948$164_Y - connect \$57 $eq$libresoc.v:949$165_Y - connect \$5 $and$libresoc.v:950$166_Y - connect \$59 $not$libresoc.v:951$167_Y - connect \$61 $and$libresoc.v:952$168_Y - connect \$63 $not$libresoc.v:953$169_Y - connect \$65 $and$libresoc.v:954$170_Y - connect \$67 $eq$libresoc.v:955$171_Y - connect \$69 $eq$libresoc.v:956$172_Y - connect \$71 $eq$libresoc.v:957$173_Y - connect \$73 $not$libresoc.v:958$174_Y - connect \$75 $and$libresoc.v:959$175_Y - connect \$77 $not$libresoc.v:960$176_Y - connect \$7 $not$libresoc.v:961$177_Y - connect \$79 $and$libresoc.v:962$178_Y - connect \$81 $eq$libresoc.v:963$179_Y - connect \$83 $eq$libresoc.v:964$180_Y - connect \$85 $eq$libresoc.v:965$181_Y - connect \$87 $not$libresoc.v:966$182_Y - connect \$89 $and$libresoc.v:967$183_Y - connect \$91 $not$libresoc.v:968$184_Y - connect \$93 $and$libresoc.v:969$185_Y - connect \$95 $eq$libresoc.v:970$186_Y - connect \$97 $eq$libresoc.v:971$187_Y - connect \$115 \$116 - connect \log_write_addr_o 0 - connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \terminated_o \terminated - connect \icache_rst_o \do_icreset - connect \core_rst_o \do_reset - connect \core_stop_o \$124 - connect \d_gpr_addr \gspr_index - connect \stat_reg \$1 -end -attribute \src "libresoc.v:1393.1-7326.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec" -attribute \generator "nMigen" -module \dec - attribute \src "libresoc.v:3587.3-3725.6" - wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:5572.3-5713.6" - wire $0\br[0:0] - attribute \src "libresoc.v:4294.3-4435.6" - wire width 3 $0\cr_in[2:0] - attribute \src "libresoc.v:4436.3-4577.6" - wire width 3 $0\cr_out[2:0] - attribute \src "libresoc.v:5004.3-5145.6" - wire width 2 $0\cry_in[1:0] - attribute \src "libresoc.v:5430.3-5571.6" - wire $0\cry_out[0:0] - attribute \src "libresoc.v:6850.3-6991.6" - wire width 5 $0\form[4:0] - attribute \src "libresoc.v:6566.3-6707.6" - wire width 12 $0\function_unit[11:0] - attribute \src "libresoc.v:3726.3-3867.6" - wire width 3 $0\in1_sel[2:0] - attribute \src "libresoc.v:3868.3-4009.6" - wire width 4 $0\in2_sel[3:0] - attribute \src "libresoc.v:4010.3-4151.6" - wire width 2 $0\in3_sel[1:0] - attribute \src "libresoc.v:1394.7-1394.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:6708.3-6849.6" - wire width 7 $0\internal_op[6:0] - attribute \src "libresoc.v:5146.3-5287.6" - wire $0\inv_a[0:0] - attribute \src "libresoc.v:5288.3-5429.6" - wire $0\inv_out[0:0] - attribute \src "libresoc.v:5998.3-6139.6" - wire $0\is_32b[0:0] - attribute \src "libresoc.v:4578.3-4719.6" - wire width 4 $0\ldst_len[3:0] - attribute \src "libresoc.v:6282.3-6423.6" - wire $0\lk[0:0] - attribute \src "libresoc.v:4152.3-4293.6" - wire width 2 $0\out_sel[1:0] - attribute \src "libresoc.v:4862.3-5003.6" - wire width 2 $0\rc_sel[1:0] - attribute \src "libresoc.v:5856.3-5997.6" - wire $0\rsrv[0:0] - attribute \src "libresoc.v:6424.3-6565.6" - wire $0\sgl_pipe[0:0] - attribute \src "libresoc.v:6140.3-6281.6" - wire $0\sgn[0:0] - attribute \src "libresoc.v:5714.3-5855.6" - wire $0\sgn_ext[0:0] - attribute \src "libresoc.v:4720.3-4861.6" - wire width 2 $0\upd[1:0] - attribute \src "libresoc.v:3587.3-3725.6" - wire width 8 $1\asmcode[7:0] - attribute \src "libresoc.v:5572.3-5713.6" - wire $1\br[0:0] - attribute \src "libresoc.v:4294.3-4435.6" - wire width 3 $1\cr_in[2:0] - attribute \src "libresoc.v:4436.3-4577.6" - wire width 3 $1\cr_out[2:0] - attribute \src "libresoc.v:5004.3-5145.6" - wire width 2 $1\cry_in[1:0] - attribute \src "libresoc.v:5430.3-5571.6" - wire $1\cry_out[0:0] - attribute \src "libresoc.v:6850.3-6991.6" - wire width 5 $1\form[4:0] - attribute \src "libresoc.v:6566.3-6707.6" - wire width 12 $1\function_unit[11:0] - attribute \src "libresoc.v:3726.3-3867.6" - wire width 3 $1\in1_sel[2:0] - attribute \src "libresoc.v:3868.3-4009.6" - wire width 4 $1\in2_sel[3:0] - attribute \src "libresoc.v:4010.3-4151.6" - wire width 2 $1\in3_sel[1:0] - attribute \src "libresoc.v:6708.3-6849.6" - wire width 7 $1\internal_op[6:0] - attribute \src "libresoc.v:5146.3-5287.6" - wire $1\inv_a[0:0] - attribute \src "libresoc.v:5288.3-5429.6" - wire $1\inv_out[0:0] - attribute \src "libresoc.v:5998.3-6139.6" - wire $1\is_32b[0:0] - attribute \src "libresoc.v:4578.3-4719.6" - wire width 4 $1\ldst_len[3:0] - attribute \src "libresoc.v:6282.3-6423.6" - wire $1\lk[0:0] - attribute \src "libresoc.v:4152.3-4293.6" - wire width 2 $1\out_sel[1:0] - attribute \src "libresoc.v:4862.3-5003.6" - wire width 2 $1\rc_sel[1:0] - attribute \src "libresoc.v:5856.3-5997.6" - wire $1\rsrv[0:0] - attribute \src "libresoc.v:6424.3-6565.6" - wire $1\sgl_pipe[0:0] - attribute \src "libresoc.v:6140.3-6281.6" - wire $1\sgn[0:0] - attribute \src "libresoc.v:5714.3-5855.6" - wire $1\sgn_ext[0:0] - attribute \src "libresoc.v:4720.3-4861.6" - wire width 2 $1\upd[1:0] - attribute \src "libresoc.v:3587.3-3725.6" - wire width 8 $2\asmcode[7:0] - attribute \src "libresoc.v:5572.3-5713.6" - wire $2\br[0:0] - attribute \src "libresoc.v:4294.3-4435.6" - wire width 3 $2\cr_in[2:0] - attribute \src "libresoc.v:4436.3-4577.6" - wire width 3 $2\cr_out[2:0] - attribute \src "libresoc.v:5004.3-5145.6" - wire width 2 $2\cry_in[1:0] - attribute \src "libresoc.v:5430.3-5571.6" - wire $2\cry_out[0:0] - attribute \src "libresoc.v:6850.3-6991.6" - wire width 5 $2\form[4:0] - attribute \src "libresoc.v:6566.3-6707.6" - wire width 12 $2\function_unit[11:0] - attribute \src "libresoc.v:3726.3-3867.6" - wire width 3 $2\in1_sel[2:0] - attribute \src "libresoc.v:3868.3-4009.6" - wire width 4 $2\in2_sel[3:0] - attribute \src "libresoc.v:4010.3-4151.6" - wire width 2 $2\in3_sel[1:0] - attribute \src "libresoc.v:6708.3-6849.6" - wire width 7 $2\internal_op[6:0] - attribute \src "libresoc.v:5146.3-5287.6" - wire $2\inv_a[0:0] - attribute \src "libresoc.v:5288.3-5429.6" - wire $2\inv_out[0:0] - attribute \src "libresoc.v:5998.3-6139.6" - wire $2\is_32b[0:0] - attribute \src "libresoc.v:4578.3-4719.6" - wire width 4 $2\ldst_len[3:0] - attribute \src "libresoc.v:6282.3-6423.6" - wire $2\lk[0:0] - attribute \src "libresoc.v:4152.3-4293.6" - wire width 2 $2\out_sel[1:0] - attribute \src "libresoc.v:4862.3-5003.6" - wire width 2 $2\rc_sel[1:0] - attribute \src "libresoc.v:5856.3-5997.6" - wire $2\rsrv[0:0] - attribute \src "libresoc.v:6424.3-6565.6" - wire $2\sgl_pipe[0:0] - attribute \src "libresoc.v:6140.3-6281.6" - wire $2\sgn[0:0] - attribute \src "libresoc.v:5714.3-5855.6" - wire $2\sgn_ext[0:0] - attribute \src "libresoc.v:4720.3-4861.6" - wire width 2 $2\upd[1:0] - attribute \src "libresoc.v:3451.17-3451.211" - wire width 32 $ternary$libresoc.v:3451$283_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - wire width 32 \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 25 \BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 24 \BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 30 \BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 \BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 3 \BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 2 \BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 29 \BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 28 \BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 26 \BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 10 \CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 \DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 output 27 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 24 \LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire output 11 \LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire output 23 \OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 20 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 21 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 18 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 19 \RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire output 22 \Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 10 output 31 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 output 34 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 output 35 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 output 32 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 output 33 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 16 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire input 36 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 4 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec19_dec19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec19_dec19_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec19_dec19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec19_dec19_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec19_dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec19_dec19_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec19_dec19_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec19_dec19_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec19_dec19_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec19_dec19_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec19_dec19_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec19_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec19_dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec19_dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec19_dec19_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec19_dec19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec19_dec19_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec19_dec19_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec19_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec19_dec19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec19_dec19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec19_dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec19_dec19_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec19_dec19_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec19_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec30_dec30_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec30_dec30_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec30_dec30_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec30_dec30_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec30_dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec30_dec30_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec30_dec30_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec30_dec30_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec30_dec30_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec30_dec30_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec30_dec30_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec30_dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec30_dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec30_dec30_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec30_dec30_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec30_dec30_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec30_dec30_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec30_dec30_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec30_dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec30_dec30_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec30_dec30_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec30_dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec30_dec30_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec30_dec30_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec30_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec31_dec31_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec31_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec31_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec31_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec31_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec31_dec31_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec31_dec31_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec31_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec31_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec31_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec31_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec31_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec31_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec31_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec31_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec31_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec31_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec31_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec31_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec31_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec58_dec58_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec58_dec58_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec58_dec58_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec58_dec58_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec58_dec58_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec58_dec58_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec58_dec58_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec58_dec58_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec58_dec58_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec58_dec58_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec58_dec58_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec58_dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec58_dec58_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec58_dec58_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec58_dec58_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec58_dec58_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec58_dec58_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec58_dec58_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec58_dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec58_dec58_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec58_dec58_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec58_dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec58_dec58_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec58_dec58_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec58_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec62_dec62_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec62_dec62_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec62_dec62_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec62_dec62_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec62_dec62_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec62_dec62_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec62_dec62_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec62_dec62_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec62_dec62_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec62_dec62_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec62_dec62_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec62_dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec62_dec62_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec62_dec62_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec62_dec62_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec62_dec62_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec62_dec62_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec62_dec62_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec62_dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec62_dec62_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec62_dec62_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec62_dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec62_dec62_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec62_dec62_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec62_opcode_in - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 7 \function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 12 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 13 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \in3_sel - attribute \src "libresoc.v:1394.7-1394.15" - wire \initial - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 6 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 9 \is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 32 \opcode_switch$1 - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 15 \out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 input 1 \raw_opcode_in - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 3 \rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 \sh - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 17 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - cell $mux $ternary$libresoc.v:3451$283 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $ternary$libresoc.v:3451$283_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:3452.9-3478.4" - cell \dec19 \dec19 - connect \dec19_asmcode \dec19_dec19_asmcode - connect \dec19_br \dec19_dec19_br - connect \dec19_cr_in \dec19_dec19_cr_in - connect \dec19_cr_out \dec19_dec19_cr_out - connect \dec19_cry_in \dec19_dec19_cry_in - connect \dec19_cry_out \dec19_dec19_cry_out - connect \dec19_form \dec19_dec19_form - connect \dec19_function_unit \dec19_dec19_function_unit - connect \dec19_in1_sel \dec19_dec19_in1_sel - connect \dec19_in2_sel \dec19_dec19_in2_sel - connect \dec19_in3_sel \dec19_dec19_in3_sel - connect \dec19_internal_op \dec19_dec19_internal_op - connect \dec19_inv_a \dec19_dec19_inv_a - connect \dec19_inv_out \dec19_dec19_inv_out - connect \dec19_is_32b \dec19_dec19_is_32b - connect \dec19_ldst_len \dec19_dec19_ldst_len - connect \dec19_lk \dec19_dec19_lk - connect \dec19_out_sel \dec19_dec19_out_sel - connect \dec19_rc_sel \dec19_dec19_rc_sel - connect \dec19_rsrv \dec19_dec19_rsrv - connect \dec19_sgl_pipe \dec19_dec19_sgl_pipe - connect \dec19_sgn \dec19_dec19_sgn - connect \dec19_sgn_ext \dec19_dec19_sgn_ext - connect \dec19_upd \dec19_dec19_upd - connect \opcode_in \dec19_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:3479.9-3505.4" - cell \dec30 \dec30 - connect \dec30_asmcode \dec30_dec30_asmcode - connect \dec30_br \dec30_dec30_br - connect \dec30_cr_in \dec30_dec30_cr_in - connect \dec30_cr_out \dec30_dec30_cr_out - connect \dec30_cry_in \dec30_dec30_cry_in - connect \dec30_cry_out \dec30_dec30_cry_out - connect \dec30_form \dec30_dec30_form - connect \dec30_function_unit \dec30_dec30_function_unit - connect \dec30_in1_sel \dec30_dec30_in1_sel - connect \dec30_in2_sel \dec30_dec30_in2_sel - connect \dec30_in3_sel \dec30_dec30_in3_sel - connect \dec30_internal_op \dec30_dec30_internal_op - connect \dec30_inv_a \dec30_dec30_inv_a - connect \dec30_inv_out \dec30_dec30_inv_out - connect \dec30_is_32b \dec30_dec30_is_32b - connect \dec30_ldst_len \dec30_dec30_ldst_len - connect \dec30_lk \dec30_dec30_lk - connect \dec30_out_sel \dec30_dec30_out_sel - connect \dec30_rc_sel \dec30_dec30_rc_sel - connect \dec30_rsrv \dec30_dec30_rsrv - connect \dec30_sgl_pipe \dec30_dec30_sgl_pipe - connect \dec30_sgn \dec30_dec30_sgn - connect \dec30_sgn_ext \dec30_dec30_sgn_ext - connect \dec30_upd \dec30_dec30_upd - connect \opcode_in \dec30_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:3506.9-3532.4" - cell \dec31 \dec31 - connect \dec31_asmcode \dec31_dec31_asmcode - connect \dec31_br \dec31_dec31_br - connect \dec31_cr_in \dec31_dec31_cr_in - connect \dec31_cr_out \dec31_dec31_cr_out - connect \dec31_cry_in \dec31_dec31_cry_in - connect \dec31_cry_out \dec31_dec31_cry_out - connect \dec31_form \dec31_dec31_form - connect \dec31_function_unit \dec31_dec31_function_unit - connect \dec31_in1_sel \dec31_dec31_in1_sel - connect \dec31_in2_sel \dec31_dec31_in2_sel - connect \dec31_in3_sel \dec31_dec31_in3_sel - connect \dec31_internal_op \dec31_dec31_internal_op - connect \dec31_inv_a \dec31_dec31_inv_a - connect \dec31_inv_out \dec31_dec31_inv_out - connect \dec31_is_32b \dec31_dec31_is_32b - connect \dec31_ldst_len \dec31_dec31_ldst_len - connect \dec31_lk \dec31_dec31_lk - connect \dec31_out_sel \dec31_dec31_out_sel - connect \dec31_rc_sel \dec31_dec31_rc_sel - connect \dec31_rsrv \dec31_dec31_rsrv - connect \dec31_sgl_pipe \dec31_dec31_sgl_pipe - connect \dec31_sgn \dec31_dec31_sgn - connect \dec31_sgn_ext \dec31_dec31_sgn_ext - connect \dec31_upd \dec31_dec31_upd - connect \opcode_in \dec31_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:3533.9-3559.4" - cell \dec58 \dec58 - connect \dec58_asmcode \dec58_dec58_asmcode - connect \dec58_br \dec58_dec58_br - connect \dec58_cr_in \dec58_dec58_cr_in - connect \dec58_cr_out \dec58_dec58_cr_out - connect \dec58_cry_in \dec58_dec58_cry_in - connect \dec58_cry_out \dec58_dec58_cry_out - connect \dec58_form \dec58_dec58_form - connect \dec58_function_unit \dec58_dec58_function_unit - connect \dec58_in1_sel \dec58_dec58_in1_sel - connect \dec58_in2_sel \dec58_dec58_in2_sel - connect \dec58_in3_sel \dec58_dec58_in3_sel - connect \dec58_internal_op \dec58_dec58_internal_op - connect \dec58_inv_a \dec58_dec58_inv_a - connect \dec58_inv_out \dec58_dec58_inv_out - connect \dec58_is_32b \dec58_dec58_is_32b - connect \dec58_ldst_len \dec58_dec58_ldst_len - connect \dec58_lk \dec58_dec58_lk - connect \dec58_out_sel \dec58_dec58_out_sel - connect \dec58_rc_sel \dec58_dec58_rc_sel - connect \dec58_rsrv \dec58_dec58_rsrv - connect \dec58_sgl_pipe \dec58_dec58_sgl_pipe - connect \dec58_sgn \dec58_dec58_sgn - connect \dec58_sgn_ext \dec58_dec58_sgn_ext - connect \dec58_upd \dec58_dec58_upd - connect \opcode_in \dec58_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:3560.9-3586.4" - cell \dec62 \dec62 - connect \dec62_asmcode \dec62_dec62_asmcode - connect \dec62_br \dec62_dec62_br - connect \dec62_cr_in \dec62_dec62_cr_in - connect \dec62_cr_out \dec62_dec62_cr_out - connect \dec62_cry_in \dec62_dec62_cry_in - connect \dec62_cry_out \dec62_dec62_cry_out - connect \dec62_form \dec62_dec62_form - connect \dec62_function_unit \dec62_dec62_function_unit - connect \dec62_in1_sel \dec62_dec62_in1_sel - connect \dec62_in2_sel \dec62_dec62_in2_sel - connect \dec62_in3_sel \dec62_dec62_in3_sel - connect \dec62_internal_op \dec62_dec62_internal_op - connect \dec62_inv_a \dec62_dec62_inv_a - connect \dec62_inv_out \dec62_dec62_inv_out - connect \dec62_is_32b \dec62_dec62_is_32b - connect \dec62_ldst_len \dec62_dec62_ldst_len - connect \dec62_lk \dec62_dec62_lk - connect \dec62_out_sel \dec62_dec62_out_sel - connect \dec62_rc_sel \dec62_dec62_rc_sel - connect \dec62_rsrv \dec62_dec62_rsrv - connect \dec62_sgl_pipe \dec62_dec62_sgl_pipe - connect \dec62_sgn \dec62_dec62_sgn - connect \dec62_sgn_ext \dec62_dec62_sgn_ext - connect \dec62_upd \dec62_dec62_upd - connect \opcode_in \dec62_opcode_in - end - attribute \src "libresoc.v:1394.7-1394.20" - process $proc$libresoc.v:1394$308 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:3587.3-3725.6" - process $proc$libresoc.v:3587$284 - assign { } { } - assign { } { } - assign { } { } - assign $0\asmcode[7:0] $2\asmcode[7:0] - attribute \src "libresoc.v:3588.5-3588.29" - switch \initial - attribute \src "libresoc.v:3588.9-3588.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\asmcode[7:0] \dec19_dec19_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\asmcode[7:0] \dec30_dec30_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\asmcode[7:0] \dec31_dec31_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\asmcode[7:0] \dec58_dec58_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\asmcode[7:0] \dec62_dec62_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\asmcode[7:0] 8'00000111 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\asmcode[7:0] 8'00001000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\asmcode[7:0] 8'00000110 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\asmcode[7:0] 8'00001001 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\asmcode[7:0] 8'00010001 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\asmcode[7:0] 8'00010010 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\asmcode[7:0] 8'00010100 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\asmcode[7:0] 8'00010101 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\asmcode[7:0] 8'00011101 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\asmcode[7:0] 8'00011111 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\asmcode[7:0] 8'01001110 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\asmcode[7:0] 8'01001111 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\asmcode[7:0] 8'01011000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\asmcode[7:0] 8'01011010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\asmcode[7:0] 8'01011110 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\asmcode[7:0] 8'01011111 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\asmcode[7:0] 8'01100111 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\asmcode[7:0] 8'01101001 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\asmcode[7:0] 8'10000000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\asmcode[7:0] 8'10001010 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\asmcode[7:0] 8'10001011 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\asmcode[7:0] 8'10011000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\asmcode[7:0] 8'10011001 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\asmcode[7:0] 8'10011010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\asmcode[7:0] 8'10100110 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\asmcode[7:0] 8'10101001 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\asmcode[7:0] 8'10110010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\asmcode[7:0] 8'10110101 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\asmcode[7:0] 8'10111000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\asmcode[7:0] 8'10111011 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\asmcode[7:0] 8'11000011 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\asmcode[7:0] 8'11001011 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\asmcode[7:0] 8'11001111 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\asmcode[7:0] 8'11010001 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\asmcode[7:0] 8'11010010 - case - assign $1\asmcode[7:0] 8'00000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\asmcode[7:0] 8'00010011 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\asmcode[7:0] 8'10000110 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\asmcode[7:0] 8'10011100 - case - assign $2\asmcode[7:0] $1\asmcode[7:0] - end - sync always - update \asmcode $0\asmcode[7:0] - end - attribute \src "libresoc.v:3726.3-3867.6" - process $proc$libresoc.v:3726$285 - assign { } { } - assign { } { } - assign { } { } - assign $0\in1_sel[2:0] $2\in1_sel[2:0] - attribute \src "libresoc.v:3727.5-3727.29" - switch \initial - attribute \src "libresoc.v:3727.9-3727.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\in1_sel[2:0] \dec19_dec19_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\in1_sel[2:0] \dec30_dec30_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\in1_sel[2:0] \dec31_dec31_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\in1_sel[2:0] \dec58_dec58_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\in1_sel[2:0] \dec62_dec62_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\in1_sel[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\in1_sel[2:0] 3'100 - case - assign $1\in1_sel[2:0] 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\in1_sel[2:0] 3'000 - case - assign $2\in1_sel[2:0] $1\in1_sel[2:0] - end - sync always - update \in1_sel $0\in1_sel[2:0] - end - attribute \src "libresoc.v:3868.3-4009.6" - process $proc$libresoc.v:3868$286 - assign { } { } - assign { } { } - assign { } { } - assign $0\in2_sel[3:0] $2\in2_sel[3:0] - attribute \src "libresoc.v:3869.5-3869.29" - switch \initial - attribute \src "libresoc.v:3869.9-3869.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\in2_sel[3:0] \dec19_dec19_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\in2_sel[3:0] \dec30_dec30_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\in2_sel[3:0] \dec31_dec31_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\in2_sel[3:0] \dec58_dec58_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\in2_sel[3:0] \dec62_dec62_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\in2_sel[3:0] 4'0101 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\in2_sel[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\in2_sel[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\in2_sel[3:0] 4'0110 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\in2_sel[3:0] 4'0111 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\in2_sel[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\in2_sel[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\in2_sel[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\in2_sel[3:0] 4'1011 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\in2_sel[3:0] 4'1011 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\in2_sel[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\in2_sel[3:0] 4'0100 - case - assign $1\in2_sel[3:0] 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\in2_sel[3:0] 4'0000 - case - assign $2\in2_sel[3:0] $1\in2_sel[3:0] - end - sync always - update \in2_sel $0\in2_sel[3:0] - end - attribute \src "libresoc.v:4010.3-4151.6" - process $proc$libresoc.v:4010$287 - assign { } { } - assign { } { } - assign { } { } - assign $0\in3_sel[1:0] $2\in3_sel[1:0] - attribute \src "libresoc.v:4011.5-4011.29" - switch \initial - attribute \src "libresoc.v:4011.9-4011.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\in3_sel[1:0] \dec19_dec19_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\in3_sel[1:0] \dec30_dec30_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\in3_sel[1:0] \dec31_dec31_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\in3_sel[1:0] \dec58_dec58_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\in3_sel[1:0] \dec62_dec62_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - case - assign $1\in3_sel[1:0] 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\in3_sel[1:0] 2'00 - case - assign $2\in3_sel[1:0] $1\in3_sel[1:0] - end - sync always - update \in3_sel $0\in3_sel[1:0] - end - attribute \src "libresoc.v:4152.3-4293.6" - process $proc$libresoc.v:4152$288 - assign { } { } - assign { } { } - assign { } { } - assign $0\out_sel[1:0] $2\out_sel[1:0] - attribute \src "libresoc.v:4153.5-4153.29" - switch \initial - attribute \src "libresoc.v:4153.9-4153.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\out_sel[1:0] \dec19_dec19_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\out_sel[1:0] \dec30_dec30_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\out_sel[1:0] \dec31_dec31_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\out_sel[1:0] \dec58_dec58_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\out_sel[1:0] \dec62_dec62_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\out_sel[1:0] 2'11 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\out_sel[1:0] 2'10 - case - assign $1\out_sel[1:0] 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\out_sel[1:0] 2'01 - case - assign $2\out_sel[1:0] $1\out_sel[1:0] - end - sync always - update \out_sel $0\out_sel[1:0] - end - attribute \src "libresoc.v:4294.3-4435.6" - process $proc$libresoc.v:4294$289 - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_in[2:0] $2\cr_in[2:0] - attribute \src "libresoc.v:4295.5-4295.29" - switch \initial - attribute \src "libresoc.v:4295.9-4295.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\cr_in[2:0] \dec19_dec19_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\cr_in[2:0] \dec30_dec30_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\cr_in[2:0] \dec31_dec31_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\cr_in[2:0] \dec58_dec58_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\cr_in[2:0] \dec62_dec62_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\cr_in[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\cr_in[2:0] 3'000 - case - assign $1\cr_in[2:0] 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\cr_in[2:0] 3'000 - case - assign $2\cr_in[2:0] $1\cr_in[2:0] - end - sync always - update \cr_in $0\cr_in[2:0] - end - attribute \src "libresoc.v:4436.3-4577.6" - process $proc$libresoc.v:4436$290 - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_out[2:0] $2\cr_out[2:0] - attribute \src "libresoc.v:4437.5-4437.29" - switch \initial - attribute \src "libresoc.v:4437.9-4437.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\cr_out[2:0] \dec19_dec19_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\cr_out[2:0] \dec30_dec30_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\cr_out[2:0] \dec31_dec31_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\cr_out[2:0] \dec58_dec58_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\cr_out[2:0] \dec62_dec62_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\cr_out[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\cr_out[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\cr_out[2:0] 3'000 - case - assign $1\cr_out[2:0] 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\cr_out[2:0] 3'000 - case - assign $2\cr_out[2:0] $1\cr_out[2:0] - end - sync always - update \cr_out $0\cr_out[2:0] - end - attribute \src "libresoc.v:4578.3-4719.6" - process $proc$libresoc.v:4578$291 - assign { } { } - assign { } { } - assign { } { } - assign $0\ldst_len[3:0] $2\ldst_len[3:0] - attribute \src "libresoc.v:4579.5-4579.29" - switch \initial - attribute \src "libresoc.v:4579.9-4579.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ldst_len[3:0] \dec19_dec19_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\ldst_len[3:0] \dec30_dec30_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ldst_len[3:0] \dec31_dec31_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\ldst_len[3:0] \dec58_dec58_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\ldst_len[3:0] \dec62_dec62_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - case - assign $1\ldst_len[3:0] 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\ldst_len[3:0] 4'0000 - case - assign $2\ldst_len[3:0] $1\ldst_len[3:0] - end - sync always - update \ldst_len $0\ldst_len[3:0] - end - attribute \src "libresoc.v:4720.3-4861.6" - process $proc$libresoc.v:4720$292 - assign { } { } - assign { } { } - assign { } { } - assign $0\upd[1:0] $2\upd[1:0] - attribute \src "libresoc.v:4721.5-4721.29" - switch \initial - attribute \src "libresoc.v:4721.9-4721.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\upd[1:0] \dec19_dec19_upd - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\upd[1:0] \dec30_dec30_upd - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\upd[1:0] \dec31_dec31_upd - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\upd[1:0] \dec58_dec58_upd - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\upd[1:0] \dec62_dec62_upd - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\upd[1:0] 2'00 - case - assign $1\upd[1:0] 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\upd[1:0] 2'00 - case - assign $2\upd[1:0] $1\upd[1:0] - end - sync always - update \upd $0\upd[1:0] - end - attribute \src "libresoc.v:4862.3-5003.6" - process $proc$libresoc.v:4862$293 - assign { } { } - assign { } { } - assign { } { } - assign $0\rc_sel[1:0] $2\rc_sel[1:0] - attribute \src "libresoc.v:4863.5-4863.29" - switch \initial - attribute \src "libresoc.v:4863.9-4863.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\rc_sel[1:0] \dec19_dec19_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\rc_sel[1:0] \dec30_dec30_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\rc_sel[1:0] \dec31_dec31_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\rc_sel[1:0] \dec58_dec58_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\rc_sel[1:0] \dec62_dec62_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\rc_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\rc_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\rc_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - case - assign $1\rc_sel[1:0] 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\rc_sel[1:0] 2'00 - case - assign $2\rc_sel[1:0] $1\rc_sel[1:0] - end - sync always - update \rc_sel $0\rc_sel[1:0] - end - attribute \src "libresoc.v:5004.3-5145.6" - process $proc$libresoc.v:5004$294 - assign { } { } - assign { } { } - assign { } { } - assign $0\cry_in[1:0] $2\cry_in[1:0] - attribute \src "libresoc.v:5005.5-5005.29" - switch \initial - attribute \src "libresoc.v:5005.9-5005.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\cry_in[1:0] \dec19_dec19_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\cry_in[1:0] \dec30_dec30_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\cry_in[1:0] \dec31_dec31_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\cry_in[1:0] \dec58_dec58_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\cry_in[1:0] \dec62_dec62_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\cry_in[1:0] 2'00 - case - assign $1\cry_in[1:0] 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\cry_in[1:0] 2'00 - case - assign $2\cry_in[1:0] $1\cry_in[1:0] - end - sync always - update \cry_in $0\cry_in[1:0] - end - attribute \src "libresoc.v:5146.3-5287.6" - process $proc$libresoc.v:5146$295 - assign { } { } - assign { } { } - assign { } { } - assign $0\inv_a[0:0] $2\inv_a[0:0] - attribute \src "libresoc.v:5147.5-5147.29" - switch \initial - attribute \src "libresoc.v:5147.9-5147.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\inv_a[0:0] \dec19_dec19_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\inv_a[0:0] \dec30_dec30_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\inv_a[0:0] \dec31_dec31_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\inv_a[0:0] \dec58_dec58_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\inv_a[0:0] \dec62_dec62_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\inv_a[0:0] 1'0 - case - assign $1\inv_a[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\inv_a[0:0] 1'0 - case - assign $2\inv_a[0:0] $1\inv_a[0:0] - end - sync always - update \inv_a $0\inv_a[0:0] - end - attribute \src "libresoc.v:5288.3-5429.6" - process $proc$libresoc.v:5288$296 - assign { } { } - assign { } { } - assign { } { } - assign $0\inv_out[0:0] $2\inv_out[0:0] - attribute \src "libresoc.v:5289.5-5289.29" - switch \initial - attribute \src "libresoc.v:5289.9-5289.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\inv_out[0:0] \dec19_dec19_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\inv_out[0:0] \dec30_dec30_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\inv_out[0:0] \dec31_dec31_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\inv_out[0:0] \dec58_dec58_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\inv_out[0:0] \dec62_dec62_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\inv_out[0:0] 1'0 - case - assign $1\inv_out[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\inv_out[0:0] 1'0 - case - assign $2\inv_out[0:0] $1\inv_out[0:0] - end - sync always - update \inv_out $0\inv_out[0:0] - end - attribute \src "libresoc.v:5430.3-5571.6" - process $proc$libresoc.v:5430$297 - assign { } { } - assign { } { } - assign { } { } - assign $0\cry_out[0:0] $2\cry_out[0:0] - attribute \src "libresoc.v:5431.5-5431.29" - switch \initial - attribute \src "libresoc.v:5431.9-5431.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\cry_out[0:0] \dec19_dec19_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\cry_out[0:0] \dec30_dec30_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\cry_out[0:0] \dec31_dec31_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\cry_out[0:0] \dec58_dec58_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\cry_out[0:0] \dec62_dec62_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\cry_out[0:0] 1'0 - case - assign $1\cry_out[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\cry_out[0:0] 1'0 - case - assign $2\cry_out[0:0] $1\cry_out[0:0] - end - sync always - update \cry_out $0\cry_out[0:0] - end - attribute \src "libresoc.v:5572.3-5713.6" - process $proc$libresoc.v:5572$298 - assign { } { } - assign { } { } - assign { } { } - assign $0\br[0:0] $2\br[0:0] - attribute \src "libresoc.v:5573.5-5573.29" - switch \initial - attribute \src "libresoc.v:5573.9-5573.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\br[0:0] \dec19_dec19_br - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\br[0:0] \dec30_dec30_br - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\br[0:0] \dec31_dec31_br - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\br[0:0] \dec58_dec58_br - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\br[0:0] \dec62_dec62_br - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\br[0:0] 1'0 - case - assign $1\br[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\br[0:0] 1'0 - case - assign $2\br[0:0] $1\br[0:0] - end - sync always - update \br $0\br[0:0] - end - attribute \src "libresoc.v:5714.3-5855.6" - process $proc$libresoc.v:5714$299 - assign { } { } - assign { } { } - assign { } { } - assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] - attribute \src "libresoc.v:5715.5-5715.29" - switch \initial - attribute \src "libresoc.v:5715.9-5715.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\sgn_ext[0:0] \dec19_dec19_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\sgn_ext[0:0] \dec30_dec30_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\sgn_ext[0:0] \dec31_dec31_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\sgn_ext[0:0] \dec58_dec58_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\sgn_ext[0:0] \dec62_dec62_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - case - assign $1\sgn_ext[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\sgn_ext[0:0] 1'0 - case - assign $2\sgn_ext[0:0] $1\sgn_ext[0:0] - end - sync always - update \sgn_ext $0\sgn_ext[0:0] - end - attribute \src "libresoc.v:5856.3-5997.6" - process $proc$libresoc.v:5856$300 - assign { } { } - assign { } { } - assign { } { } - assign $0\rsrv[0:0] $2\rsrv[0:0] - attribute \src "libresoc.v:5857.5-5857.29" - switch \initial - attribute \src "libresoc.v:5857.9-5857.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\rsrv[0:0] \dec19_dec19_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\rsrv[0:0] \dec30_dec30_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\rsrv[0:0] \dec31_dec31_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\rsrv[0:0] \dec58_dec58_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\rsrv[0:0] \dec62_dec62_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\rsrv[0:0] 1'0 - case - assign $1\rsrv[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\rsrv[0:0] 1'0 - case - assign $2\rsrv[0:0] $1\rsrv[0:0] - end - sync always - update \rsrv $0\rsrv[0:0] - end - attribute \src "libresoc.v:5998.3-6139.6" - process $proc$libresoc.v:5998$301 - assign { } { } - assign { } { } - assign { } { } - assign $0\is_32b[0:0] $2\is_32b[0:0] - attribute \src "libresoc.v:5999.5-5999.29" - switch \initial - attribute \src "libresoc.v:5999.9-5999.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\is_32b[0:0] \dec19_dec19_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\is_32b[0:0] \dec30_dec30_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\is_32b[0:0] \dec31_dec31_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\is_32b[0:0] \dec58_dec58_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\is_32b[0:0] \dec62_dec62_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\is_32b[0:0] 1'0 - case - assign $1\is_32b[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\is_32b[0:0] 1'0 - case - assign $2\is_32b[0:0] $1\is_32b[0:0] - end - sync always - update \is_32b $0\is_32b[0:0] - end - attribute \src "libresoc.v:6140.3-6281.6" - process $proc$libresoc.v:6140$302 - assign { } { } - assign { } { } - assign { } { } - assign $0\sgn[0:0] $2\sgn[0:0] - attribute \src "libresoc.v:6141.5-6141.29" - switch \initial - attribute \src "libresoc.v:6141.9-6141.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\sgn[0:0] \dec19_dec19_sgn - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\sgn[0:0] \dec30_dec30_sgn - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\sgn[0:0] \dec31_dec31_sgn - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\sgn[0:0] \dec58_dec58_sgn - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\sgn[0:0] \dec62_dec62_sgn - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\sgn[0:0] 1'0 - case - assign $1\sgn[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\sgn[0:0] 1'0 - case - assign $2\sgn[0:0] $1\sgn[0:0] - end - sync always - update \sgn $0\sgn[0:0] - end - attribute \src "libresoc.v:6282.3-6423.6" - process $proc$libresoc.v:6282$303 - assign { } { } - assign { } { } - assign { } { } - assign $0\lk[0:0] $2\lk[0:0] - attribute \src "libresoc.v:6283.5-6283.29" - switch \initial - attribute \src "libresoc.v:6283.9-6283.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\lk[0:0] \dec19_dec19_lk - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\lk[0:0] \dec30_dec30_lk - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\lk[0:0] \dec31_dec31_lk - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\lk[0:0] \dec58_dec58_lk - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\lk[0:0] \dec62_dec62_lk - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\lk[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\lk[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\lk[0:0] 1'0 - case - assign $1\lk[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\lk[0:0] 1'0 - case - assign $2\lk[0:0] $1\lk[0:0] - end - sync always - update \lk $0\lk[0:0] - end - attribute \src "libresoc.v:6424.3-6565.6" - process $proc$libresoc.v:6424$304 - assign { } { } - assign { } { } - assign { } { } - assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] - attribute \src "libresoc.v:6425.5-6425.29" - switch \initial - attribute \src "libresoc.v:6425.9-6425.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\sgl_pipe[0:0] \dec19_dec19_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\sgl_pipe[0:0] \dec30_dec30_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\sgl_pipe[0:0] \dec31_dec31_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\sgl_pipe[0:0] \dec58_dec58_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\sgl_pipe[0:0] \dec62_dec62_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - case - assign $1\sgl_pipe[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\sgl_pipe[0:0] 1'1 - case - assign $2\sgl_pipe[0:0] $1\sgl_pipe[0:0] - end - sync always - update \sgl_pipe $0\sgl_pipe[0:0] - end - attribute \src "libresoc.v:6566.3-6707.6" - process $proc$libresoc.v:6566$305 - assign { } { } - assign { } { } - assign { } { } - assign $0\function_unit[11:0] $2\function_unit[11:0] - attribute \src "libresoc.v:6567.5-6567.29" - switch \initial - attribute \src "libresoc.v:6567.9-6567.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\function_unit[11:0] \dec19_dec19_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\function_unit[11:0] \dec30_dec30_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\function_unit[11:0] \dec31_dec31_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\function_unit[11:0] \dec58_dec58_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\function_unit[11:0] \dec62_dec62_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\function_unit[11:0] 12'000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\function_unit[11:0] 12'000000100000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\function_unit[11:0] 12'000000100000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\function_unit[11:0] 12'000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\function_unit[11:0] 12'000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\function_unit[11:0] 12'000000010000 - case - assign $1\function_unit[11:0] 12'000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\function_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\function_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\function_unit[11:0] 12'000000000000 - case - assign $2\function_unit[11:0] $1\function_unit[11:0] - end - sync always - update \function_unit $0\function_unit[11:0] - end - attribute \src "libresoc.v:6708.3-6849.6" - process $proc$libresoc.v:6708$306 - assign { } { } - assign { } { } - assign { } { } - assign $0\internal_op[6:0] $2\internal_op[6:0] - attribute \src "libresoc.v:6709.5-6709.29" - switch \initial - attribute \src "libresoc.v:6709.9-6709.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\internal_op[6:0] \dec19_dec19_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\internal_op[6:0] \dec30_dec30_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\internal_op[6:0] \dec31_dec31_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\internal_op[6:0] \dec58_dec58_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\internal_op[6:0] \dec62_dec62_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\internal_op[6:0] 7'1001001 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\internal_op[6:0] 7'0000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\internal_op[6:0] 7'0000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\internal_op[6:0] 7'0000110 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\internal_op[6:0] 7'0000111 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\internal_op[6:0] 7'0001010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\internal_op[6:0] 7'0001010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\internal_op[6:0] 7'0110010 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\internal_op[6:0] 7'0110101 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\internal_op[6:0] 7'0110101 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\internal_op[6:0] 7'0111000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\internal_op[6:0] 7'0111000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\internal_op[6:0] 7'0111000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\internal_op[6:0] 7'0111111 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\internal_op[6:0] 7'0111111 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\internal_op[6:0] 7'1000011 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\internal_op[6:0] 7'1000011 - case - assign $1\internal_op[6:0] 7'0000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\internal_op[6:0] 7'0000101 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\internal_op[6:0] 7'1000100 - case - assign $2\internal_op[6:0] $1\internal_op[6:0] - end - sync always - update \internal_op $0\internal_op[6:0] - end - attribute \src "libresoc.v:6850.3-6991.6" - process $proc$libresoc.v:6850$307 - assign { } { } - assign { } { } - assign { } { } - assign $0\form[4:0] $2\form[4:0] - attribute \src "libresoc.v:6851.5-6851.29" - switch \initial - attribute \src "libresoc.v:6851.9-6851.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\form[4:0] \dec19_dec19_form - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\form[4:0] \dec30_dec30_form - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\form[4:0] \dec31_dec31_form - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\form[4:0] \dec58_dec58_form - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\form[4:0] \dec62_dec62_form - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\form[4:0] 5'00011 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\form[4:0] 5'00010 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\form[4:0] 5'00010 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\form[4:0] 5'00001 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\form[4:0] 5'00010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\form[4:0] 5'10011 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\form[4:0] 5'10011 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\form[4:0] 5'10011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\form[4:0] 5'00100 - case - assign $1\form[4:0] 5'00000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\form[4:0] 5'00000 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\form[4:0] 5'00000 - case - assign $2\form[4:0] $1\form[4:0] - end - sync always - update \form $0\form[4:0] - end - connect \$2 $ternary$libresoc.v:3451$283_Y - connect \VC_XO \opcode_in [9:0] - connect \VC_VRT \opcode_in [25:21] - connect \VC_VRB \opcode_in [15:11] - connect \VC_VRA \opcode_in [20:16] - connect \VC_Rc \opcode_in [10] - connect \XS_XO \opcode_in [10:2] - connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } - connect \XS_RS \opcode_in [25:21] - connect \XS_Rc \opcode_in [0] - connect \XS_RA \opcode_in [20:16] - connect \VA_XO \opcode_in [5:0] - connect \VA_VRT \opcode_in [25:21] - connect \VA_VRC \opcode_in [10:6] - connect \VA_VRB \opcode_in [15:11] - connect \VA_VRA \opcode_in [20:16] - connect \VA_SHB \opcode_in [9:6] - connect \VA_RT \opcode_in [25:21] - connect \VA_RC \opcode_in [10:6] - connect \VA_RB \opcode_in [15:11] - connect \VA_RA \opcode_in [20:16] - connect \TX_XO \opcode_in [6:1] - connect \TX_XBI \opcode_in [10:7] - connect \TX_UI \opcode_in [15:11] - connect \TX_RA \opcode_in [20:16] - connect \DQE_XO \opcode_in [1:0] - connect \DQE_RT \opcode_in [25:21] - connect \DQE_RA \opcode_in [20:16] - connect \XO_XO \opcode_in [9:1] - connect \XO_RT \opcode_in [25:21] - connect \XO_Rc \opcode_in [0] - connect \XO_RB \opcode_in [15:11] - connect \XO_RA \opcode_in [20:16] - connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] - connect \MD_XO \opcode_in [4:2] - connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MD_RS \opcode_in [25:21] - connect \MD_Rc \opcode_in [0] - connect \MD_RA \opcode_in [20:16] - connect \MD_me \opcode_in [10:5] - connect \MD_mb \opcode_in [10:5] - connect \M_SH \opcode_in [15:11] - connect \M_RS \opcode_in [25:21] - connect \M_Rc \opcode_in [0] - connect \M_RB \opcode_in [15:11] - connect \M_RA \opcode_in [20:16] - connect \M_ME \opcode_in [5:1] - connect \M_MB \opcode_in [10:6] - connect \SC_XO_1 \opcode_in [1:0] - connect \SC_XO \opcode_in [1] - connect \SC_LEV \opcode_in [11:5] - connect \MDS_XO \opcode_in [4:1] - connect \MDS_XBI_1 \opcode_in [10:7] - connect \MDS_XBI \opcode_in [10:7] - connect \MDS_RS \opcode_in [25:21] - connect \MDS_Rc \opcode_in [0] - connect \MDS_RB \opcode_in [15:11] - connect \MDS_RA \opcode_in [20:16] - connect \MDS_me \opcode_in [10:5] - connect \MDS_mb \opcode_in [10:5] - connect \MDS_IS \opcode_in [25:21] - connect \MDS_IB \opcode_in [15:11] - connect \Z23_XO \opcode_in [8:1] - connect \Z23_TE \opcode_in [20:16] - connect \Z23_RMC \opcode_in [10:9] - connect \Z23_Rc \opcode_in [0] - connect \Z23_R \opcode_in [16] - connect \Z23_FRTp \opcode_in [25:21] - connect \Z23_FRT \opcode_in [25:21] - connect \Z23_FRBp \opcode_in [15:11] - connect \Z23_FRB \opcode_in [15:11] - connect \Z23_FRAp \opcode_in [20:16] - connect \Z23_FRA \opcode_in [20:16] - connect \XFL_XO \opcode_in [10:1] - connect \XFL_W \opcode_in [16] - connect \XFL_Rc \opcode_in [0] - connect \XFL_L \opcode_in [25] - connect \XFL_FRB \opcode_in [15:11] - connect \XFL_FLM \opcode_in [24:17] - connect \VX_XO_1 \opcode_in [10:0] - connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } - connect \VX_VRT \opcode_in [25:21] - connect \VX_VRB \opcode_in [15:11] - connect \VX_VRA \opcode_in [20:16] - connect \VX_UIM_3 \opcode_in [17:16] - connect \VX_UIM_2 \opcode_in [18:16] - connect \VX_UIM_1 \opcode_in [19:16] - connect \VX_UIM \opcode_in [20:16] - connect \VX_SIM \opcode_in [20:16] - connect \VX_RT \opcode_in [25:21] - connect \VX_RA \opcode_in [20:16] - connect \VX_PS \opcode_in [9] - connect \VX_EO \opcode_in [20:16] - connect \DS_XO \opcode_in [1:0] - connect \DS_VRT \opcode_in [25:21] - connect \DS_VRS \opcode_in [25:21] - connect \DS_RT \opcode_in [25:21] - connect \DS_RSp \opcode_in [25:21] - connect \DS_RS \opcode_in [25:21] - connect \DS_RA \opcode_in [20:16] - connect \DS_FRTp \opcode_in [25:21] - connect \DS_FRSp \opcode_in [25:21] - connect \DS_DS \opcode_in [15:2] - connect \DQ_XO \opcode_in [2:0] - connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_T \opcode_in [25:21] - connect \DQ_TX \opcode_in [3] - connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_S \opcode_in [25:21] - connect \DQ_SX \opcode_in [3] - connect \DQ_RTp \opcode_in [25:21] - connect \DQ_RA \opcode_in [20:16] - connect \DQ_PT \opcode_in [3:0] - connect \DQ_DQ \opcode_in [15:4] - connect \DX_XO \opcode_in [5:1] - connect \DX_RT \opcode_in [25:21] - connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } - connect \DX_d2 \opcode_in [0] - connect \DX_d1 \opcode_in [20:16] - connect \DX_d0 \opcode_in [15:6] - connect \XFX_XO \opcode_in [10:1] - connect \XFX_SPR \opcode_in [20:11] - connect \XFX_RT \opcode_in [25:21] - connect \XFX_RS \opcode_in [25:21] - connect \XFX_FXM \opcode_in [19:12] - connect \XFX_DUIS \opcode_in [20:11] - connect \XFX_DUI \opcode_in [25:21] - connect \XFX_BHRBE \opcode_in [20:11] - connect \EVS_BFA \opcode_in [2:0] - connect \Z22_XO \opcode_in [9:1] - connect \Z22_SH \opcode_in [15:10] - connect \Z22_Rc \opcode_in [0] - connect \Z22_FRTp \opcode_in [25:21] - connect \Z22_FRT \opcode_in [25:21] - connect \Z22_FRAp \opcode_in [20:16] - connect \Z22_FRA \opcode_in [20:16] - connect \Z22_DGM \opcode_in [15:10] - connect \Z22_DCM \opcode_in [15:10] - connect \Z22_BF \opcode_in [25:23] - connect \XX2_XO_1 \opcode_in [10:2] - connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } - connect \XX2_UIM_1 \opcode_in [17:16] - connect \XX2_UIM \opcode_in [19:16] - connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX2_T \opcode_in [25:21] - connect \XX2_TX \opcode_in [0] - connect \XX2_RT \opcode_in [25:21] - connect \XX2_EO \opcode_in [20:16] - connect \XX2_DCMX \opcode_in [22:16] - connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } - connect \XX2_dx \opcode_in [20:16] - connect \XX2_dm \opcode_in [2] - connect \XX2_dc \opcode_in [6] - connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX2_B \opcode_in [15:11] - connect \XX2_BX \opcode_in [1] - connect \XX2_BF \opcode_in [25:23] - connect \D_UI \opcode_in [15:0] - connect \D_TO \opcode_in [25:21] - connect \D_SI \opcode_in [15:0] - connect \D_RT \opcode_in [25:21] - connect \D_RS \opcode_in [25:21] - connect \D_RA \opcode_in [20:16] - connect \D_L \opcode_in [21] - connect \D_FRT \opcode_in [25:21] - connect \D_FRS \opcode_in [25:21] - connect \D_D \opcode_in [15:0] - connect \D_BF \opcode_in [25:23] - connect \A_XO \opcode_in [5:1] - connect \A_RT \opcode_in [25:21] - connect \A_Rc \opcode_in [0] - connect \A_RB \opcode_in [15:11] - connect \A_RA \opcode_in [20:16] - connect \A_FRT \opcode_in [25:21] - connect \A_FRC \opcode_in [10:6] - connect \A_FRB \opcode_in [15:11] - connect \A_FRA \opcode_in [20:16] - connect \A_BC \opcode_in [10:6] - connect \XL_XO \opcode_in [10:1] - connect \XL_S \opcode_in [11] - connect \XL_OC \opcode_in [25:11] - connect \XL_LK \opcode_in [0] - connect \XL_BT \opcode_in [25:21] - connect \XL_BO_1 \opcode_in [25:21] - connect \XL_BO \opcode_in [25:21] - connect \XL_BI \opcode_in [20:16] - connect \XL_BH \opcode_in [12:11] - connect \XL_BFA \opcode_in [20:18] - connect \XL_BF \opcode_in [25:23] - connect \XL_BB \opcode_in [15:11] - connect \XL_BA \opcode_in [20:16] - connect \XX4_XO \opcode_in [5:4] - connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX4_T \opcode_in [25:21] - connect \XX4_TX \opcode_in [0] - connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } - connect \XX4_C \opcode_in [10:6] - connect \XX4_CX \opcode_in [3] - connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX4_B \opcode_in [15:11] - connect \XX4_BX \opcode_in [1] - connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX4_A \opcode_in [20:16] - connect \XX4_AX \opcode_in [2] - connect \XX3_XO_2 \opcode_in [9:1] - connect \XX3_XO_1 \opcode_in [10:3] - connect \XX3_XO \opcode_in [10:7] - connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX3_T \opcode_in [25:21] - connect \XX3_TX \opcode_in [0] - connect \XX3_SHW \opcode_in [9:8] - connect \XX3_Rc \opcode_in [10] - connect \XX3_DM \opcode_in [9:8] - connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX3_B \opcode_in [15:11] - connect \XX3_BX \opcode_in [1] - connect \XX3_BF \opcode_in [25:23] - connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX3_A \opcode_in [20:16] - connect \XX3_AX \opcode_in [2] - connect \I_LK \opcode_in [0] - connect \I_LI \opcode_in [25:2] - connect \I_AA \opcode_in [1] - connect \B_LK \opcode_in [0] - connect \B_BO \opcode_in [25:21] - connect \B_BI \opcode_in [20:16] - connect \B_BD \opcode_in [15:2] - connect \B_AA \opcode_in [1] - connect \X_XO_1 \opcode_in [8:1] - connect \X_XO \opcode_in [10:1] - connect \X_WC \opcode_in [22:21] - connect \X_W \opcode_in [16] - connect \X_VRT \opcode_in [25:21] - connect \X_VRS \opcode_in [25:21] - connect \X_UIM \opcode_in [20:16] - connect \X_U \opcode_in [15:12] - connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \X_TX \opcode_in [0] - connect \X_TO \opcode_in [25:21] - connect \X_TH \opcode_in [25:21] - connect \X_TBR \opcode_in [20:11] - connect \X_T \opcode_in [25:21] - connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } - connect \X_SX \opcode_in [0] - connect \X_SR \opcode_in [19:16] - connect \X_SP \opcode_in [20:19] - connect \X_SI \opcode_in [15:11] - connect \X_SH \opcode_in [15:11] - connect \X_S \opcode_in [25:21] - connect \X_RTp \opcode_in [25:21] - connect \X_RT \opcode_in [25:21] - connect \X_RSp \opcode_in [25:21] - connect \X_RS \opcode_in [25:21] - connect \X_RO \opcode_in [0] - connect \X_RM \opcode_in [12:11] - connect \X_RIC \opcode_in [19:18] - connect \X_Rc \opcode_in [0] - connect \X_RB \opcode_in [15:11] - connect \X_RA \opcode_in [20:16] - connect \X_R_1 \opcode_in [16] - connect \X_R \opcode_in [21] - connect \X_PRS \opcode_in [17] - connect \X_NB \opcode_in [15:11] - connect \X_MO \opcode_in [25:21] - connect \X_L3 \opcode_in [17:16] - connect \X_L1 \opcode_in [16] - connect \X_L \opcode_in [21] - connect \X_L2 \opcode_in [22:21] - connect \X_IMM8 \opcode_in [18:11] - connect \X_IH \opcode_in [23:21] - connect \X_FRTp \opcode_in [25:21] - connect \X_FRT \opcode_in [25:21] - connect \X_FRSp \opcode_in [25:21] - connect \X_FRS \opcode_in [25:21] - connect \X_FRBp \opcode_in [15:11] - connect \X_FRB \opcode_in [15:11] - connect \X_FRAp \opcode_in [20:16] - connect \X_FRA \opcode_in [20:16] - connect \X_FC \opcode_in [15:11] - connect \X_EX \opcode_in [0] - connect \X_EO_1 \opcode_in [20:16] - connect \X_EO \opcode_in [20:19] - connect \X_E_1 \opcode_in [19:16] - connect \X_E \opcode_in [15] - connect \X_DRM \opcode_in [13:11] - connect \X_DCMX \opcode_in [22:16] - connect \X_CT \opcode_in [24:21] - connect \X_BO \opcode_in [25:21] - connect \X_BFA \opcode_in [20:18] - connect \X_BF \opcode_in [25:23] - connect \X_A \opcode_in [25] - connect \SPR \opcode_in [20:11] - connect \MB \opcode_in [10:6] - connect \ME \opcode_in [5:1] - connect \SH \opcode_in [15:11] - connect \BC \opcode_in [10:6] - connect \TO \opcode_in [25:21] - connect \DS \opcode_in [15:2] - connect \D \opcode_in [15:0] - connect \BH \opcode_in [12:11] - connect \BI \opcode_in [20:16] - connect \BO \opcode_in [25:21] - connect \FXM \opcode_in [19:12] - connect \BT \opcode_in [25:21] - connect \BA \opcode_in [20:16] - connect \BB \opcode_in [15:11] - connect \CR \opcode_in [10:1] - connect \BF \opcode_in [25:23] - connect \BD \opcode_in [15:2] - connect \OE \opcode_in [10] - connect \Rc \opcode_in [0] - connect \AA \opcode_in [1] - connect \LK \opcode_in [0] - connect \LI \opcode_in [25:2] - connect \ME32 \opcode_in [5:1] - connect \MB32 \opcode_in [10:6] - connect \sh { \opcode_in [1] \opcode_in [15:11] } - connect \SH32 \opcode_in [15:11] - connect \L \opcode_in [21] - connect \UI \opcode_in [15:0] - connect \SI \opcode_in [15:0] - connect \RB \opcode_in [15:11] - connect \RA \opcode_in [20:16] - connect \RT \opcode_in [25:21] - connect \RS \opcode_in [25:21] - connect \opcode_in \$2 - connect \opcode_switch$1 \opcode_in - connect \dec62_opcode_in \opcode_in - connect \dec58_opcode_in \opcode_in - connect \dec31_opcode_in \opcode_in - connect \dec30_opcode_in \opcode_in - connect \dec19_opcode_in \opcode_in - connect \opcode_switch \opcode_in [31:26] -end -attribute \src "libresoc.v:7330.1-8837.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19" -attribute \generator "nMigen" -module \dec19 - attribute \src "libresoc.v:7848.3-7899.6" - wire width 8 $0\dec19_asmcode[7:0] - attribute \src "libresoc.v:8056.3-8107.6" - wire $0\dec19_br[0:0] - attribute \src "libresoc.v:8732.3-8783.6" - wire width 3 $0\dec19_cr_in[2:0] - attribute \src "libresoc.v:8784.3-8835.6" - wire width 3 $0\dec19_cr_out[2:0] - attribute \src "libresoc.v:7796.3-7847.6" - wire width 2 $0\dec19_cry_in[1:0] - attribute \src "libresoc.v:8004.3-8055.6" - wire $0\dec19_cry_out[0:0] - attribute \src "libresoc.v:8472.3-8523.6" - wire width 5 $0\dec19_form[4:0] - attribute \src "libresoc.v:7588.3-7639.6" - wire width 12 $0\dec19_function_unit[11:0] - attribute \src "libresoc.v:8524.3-8575.6" - wire width 3 $0\dec19_in1_sel[2:0] - attribute \src "libresoc.v:8576.3-8627.6" - wire width 4 $0\dec19_in2_sel[3:0] - attribute \src "libresoc.v:8628.3-8679.6" - wire width 2 $0\dec19_in3_sel[1:0] - attribute \src "libresoc.v:8160.3-8211.6" - wire width 7 $0\dec19_internal_op[6:0] - attribute \src "libresoc.v:7900.3-7951.6" - wire $0\dec19_inv_a[0:0] - attribute \src "libresoc.v:7952.3-8003.6" - wire $0\dec19_inv_out[0:0] - attribute \src "libresoc.v:8264.3-8315.6" - wire $0\dec19_is_32b[0:0] - attribute \src "libresoc.v:7640.3-7691.6" - wire width 4 $0\dec19_ldst_len[3:0] - attribute \src "libresoc.v:8368.3-8419.6" - wire $0\dec19_lk[0:0] - attribute \src "libresoc.v:8680.3-8731.6" - wire width 2 $0\dec19_out_sel[1:0] - attribute \src "libresoc.v:7744.3-7795.6" - wire width 2 $0\dec19_rc_sel[1:0] - attribute \src "libresoc.v:8212.3-8263.6" - wire $0\dec19_rsrv[0:0] - attribute \src "libresoc.v:8420.3-8471.6" - wire $0\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:8316.3-8367.6" - wire $0\dec19_sgn[0:0] - attribute \src "libresoc.v:8108.3-8159.6" - wire $0\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:7692.3-7743.6" - wire width 2 $0\dec19_upd[1:0] - attribute \src "libresoc.v:7331.7-7331.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:7848.3-7899.6" - wire width 8 $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:8056.3-8107.6" - wire $1\dec19_br[0:0] - attribute \src "libresoc.v:8732.3-8783.6" - wire width 3 $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:8784.3-8835.6" - wire width 3 $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:7796.3-7847.6" - wire width 2 $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:8004.3-8055.6" - wire $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:8472.3-8523.6" - wire width 5 $1\dec19_form[4:0] - attribute \src "libresoc.v:7588.3-7639.6" - wire width 12 $1\dec19_function_unit[11:0] - attribute \src "libresoc.v:8524.3-8575.6" - wire width 3 $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:8576.3-8627.6" - wire width 4 $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:8628.3-8679.6" - wire width 2 $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:8160.3-8211.6" - wire width 7 $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:7900.3-7951.6" - wire $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:7952.3-8003.6" - wire $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:8264.3-8315.6" - wire $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:7640.3-7691.6" - wire width 4 $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:8368.3-8419.6" - wire $1\dec19_lk[0:0] - attribute \src "libresoc.v:8680.3-8731.6" - wire width 2 $1\dec19_out_sel[1:0] - attribute \src "libresoc.v:7744.3-7795.6" - wire width 2 $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:8212.3-8263.6" - wire $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:8420.3-8471.6" - wire $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:8316.3-8367.6" - wire $1\dec19_sgn[0:0] - attribute \src "libresoc.v:8108.3-8159.6" - wire $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:7692.3-7743.6" - wire width 2 $1\dec19_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec19_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec19_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec19_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec19_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec19_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec19_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec19_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec19_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec19_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec19_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec19_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec19_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec19_upd - attribute \src "libresoc.v:7331.7-7331.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 10 \opcode_switch - attribute \src "libresoc.v:7331.7-7331.20" - process $proc$libresoc.v:7331$333 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:7588.3-7639.6" - process $proc$libresoc.v:7588$309 - assign { } { } - assign { } { } - assign $0\dec19_function_unit[11:0] $1\dec19_function_unit[11:0] - attribute \src "libresoc.v:7589.5-7589.29" - switch \initial - attribute \src "libresoc.v:7589.9-7589.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000000100000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000000100000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000000100000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000010000000 - case - assign $1\dec19_function_unit[11:0] 12'000000000000 - end - sync always - update \dec19_function_unit $0\dec19_function_unit[11:0] - end - attribute \src "libresoc.v:7640.3-7691.6" - process $proc$libresoc.v:7640$310 - assign { } { } - assign { } { } - assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:7641.5-7641.29" - switch \initial - attribute \src "libresoc.v:7641.9-7641.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - case - assign $1\dec19_ldst_len[3:0] 4'0000 - end - sync always - update \dec19_ldst_len $0\dec19_ldst_len[3:0] - end - attribute \src "libresoc.v:7692.3-7743.6" - process $proc$libresoc.v:7692$311 - assign { } { } - assign { } { } - assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] - attribute \src "libresoc.v:7693.5-7693.29" - switch \initial - attribute \src "libresoc.v:7693.9-7693.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - case - assign $1\dec19_upd[1:0] 2'00 - end - sync always - update \dec19_upd $0\dec19_upd[1:0] - end - attribute \src "libresoc.v:7744.3-7795.6" - process $proc$libresoc.v:7744$312 - assign { } { } - assign { } { } - assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:7745.5-7745.29" - switch \initial - attribute \src "libresoc.v:7745.9-7745.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - case - assign $1\dec19_rc_sel[1:0] 2'00 - end - sync always - update \dec19_rc_sel $0\dec19_rc_sel[1:0] - end - attribute \src "libresoc.v:7796.3-7847.6" - process $proc$libresoc.v:7796$313 - assign { } { } - assign { } { } - assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:7797.5-7797.29" - switch \initial - attribute \src "libresoc.v:7797.9-7797.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - case - assign $1\dec19_cry_in[1:0] 2'00 - end - sync always - update \dec19_cry_in $0\dec19_cry_in[1:0] - end - attribute \src "libresoc.v:7848.3-7899.6" - process $proc$libresoc.v:7848$314 - assign { } { } - assign { } { } - assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:7849.5-7849.29" - switch \initial - attribute \src "libresoc.v:7849.9-7849.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'01101100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00100101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00100110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00100111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00010110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00010111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00011000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'01001100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'10010001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'01001000 - case - assign $1\dec19_asmcode[7:0] 8'00000000 - end - sync always - update \dec19_asmcode $0\dec19_asmcode[7:0] - end - attribute \src "libresoc.v:7900.3-7951.6" - process $proc$libresoc.v:7900$315 - assign { } { } - assign { } { } - assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:7901.5-7901.29" - switch \initial - attribute \src "libresoc.v:7901.9-7901.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - case - assign $1\dec19_inv_a[0:0] 1'0 - end - sync always - update \dec19_inv_a $0\dec19_inv_a[0:0] - end - attribute \src "libresoc.v:7952.3-8003.6" - process $proc$libresoc.v:7952$316 - assign { } { } - assign { } { } - assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:7953.5-7953.29" - switch \initial - attribute \src "libresoc.v:7953.9-7953.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - case - assign $1\dec19_inv_out[0:0] 1'0 - end - sync always - update \dec19_inv_out $0\dec19_inv_out[0:0] - end - attribute \src "libresoc.v:8004.3-8055.6" - process $proc$libresoc.v:8004$317 - assign { } { } - assign { } { } - assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:8005.5-8005.29" - switch \initial - attribute \src "libresoc.v:8005.9-8005.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - case - assign $1\dec19_cry_out[0:0] 1'0 - end - sync always - update \dec19_cry_out $0\dec19_cry_out[0:0] - end - attribute \src "libresoc.v:8056.3-8107.6" - process $proc$libresoc.v:8056$318 - assign { } { } - assign { } { } - assign $0\dec19_br[0:0] $1\dec19_br[0:0] - attribute \src "libresoc.v:8057.5-8057.29" - switch \initial - attribute \src "libresoc.v:8057.9-8057.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - case - assign $1\dec19_br[0:0] 1'0 - end - sync always - update \dec19_br $0\dec19_br[0:0] - end - attribute \src "libresoc.v:8108.3-8159.6" - process $proc$libresoc.v:8108$319 - assign { } { } - assign { } { } - assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:8109.5-8109.29" - switch \initial - attribute \src "libresoc.v:8109.9-8109.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - case - assign $1\dec19_sgn_ext[0:0] 1'0 - end - sync always - update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] - end - attribute \src "libresoc.v:8160.3-8211.6" - process $proc$libresoc.v:8160$320 - assign { } { } - assign { } { } - assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:8161.5-8161.29" - switch \initial - attribute \src "libresoc.v:8161.9-8161.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'0101010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'0001000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'0001000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'0001000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'0100100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000110 - case - assign $1\dec19_internal_op[6:0] 7'0000000 - end - sync always - update \dec19_internal_op $0\dec19_internal_op[6:0] - end - attribute \src "libresoc.v:8212.3-8263.6" - process $proc$libresoc.v:8212$321 - assign { } { } - assign { } { } - assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:8213.5-8213.29" - switch \initial - attribute \src "libresoc.v:8213.9-8213.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - case - assign $1\dec19_rsrv[0:0] 1'0 - end - sync always - update \dec19_rsrv $0\dec19_rsrv[0:0] - end - attribute \src "libresoc.v:8264.3-8315.6" - process $proc$libresoc.v:8264$322 - assign { } { } - assign { } { } - assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:8265.5-8265.29" - switch \initial - attribute \src "libresoc.v:8265.9-8265.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - case - assign $1\dec19_is_32b[0:0] 1'0 - end - sync always - update \dec19_is_32b $0\dec19_is_32b[0:0] - end - attribute \src "libresoc.v:8316.3-8367.6" - process $proc$libresoc.v:8316$323 - assign { } { } - assign { } { } - assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] - attribute \src "libresoc.v:8317.5-8317.29" - switch \initial - attribute \src "libresoc.v:8317.9-8317.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - case - assign $1\dec19_sgn[0:0] 1'0 - end - sync always - update \dec19_sgn $0\dec19_sgn[0:0] - end - attribute \src "libresoc.v:8368.3-8419.6" - process $proc$libresoc.v:8368$324 - assign { } { } - assign { } { } - assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] - attribute \src "libresoc.v:8369.5-8369.29" - switch \initial - attribute \src "libresoc.v:8369.9-8369.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_lk[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_lk[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_lk[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - case - assign $1\dec19_lk[0:0] 1'0 - end - sync always - update \dec19_lk $0\dec19_lk[0:0] - end - attribute \src "libresoc.v:8420.3-8471.6" - process $proc$libresoc.v:8420$325 - assign { } { } - assign { } { } - assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:8421.5-8421.29" - switch \initial - attribute \src "libresoc.v:8421.9-8421.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - case - assign $1\dec19_sgl_pipe[0:0] 1'0 - end - sync always - update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] - end - attribute \src "libresoc.v:8472.3-8523.6" - process $proc$libresoc.v:8472$326 - assign { } { } - assign { } { } - assign $0\dec19_form[4:0] $1\dec19_form[4:0] - attribute \src "libresoc.v:8473.5-8473.29" - switch \initial - attribute \src "libresoc.v:8473.9-8473.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - case - assign $1\dec19_form[4:0] 5'00000 - end - sync always - update \dec19_form $0\dec19_form[4:0] - end - attribute \src "libresoc.v:8524.3-8575.6" - process $proc$libresoc.v:8524$327 - assign { } { } - assign { } { } - assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:8525.5-8525.29" - switch \initial - attribute \src "libresoc.v:8525.9-8525.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 - case - assign $1\dec19_in1_sel[2:0] 3'000 - end - sync always - update \dec19_in1_sel $0\dec19_in1_sel[2:0] - end - attribute \src "libresoc.v:8576.3-8627.6" - process $proc$libresoc.v:8576$328 - assign { } { } - assign { } { } - assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:8577.5-8577.29" - switch \initial - attribute \src "libresoc.v:8577.9-8577.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 - case - assign $1\dec19_in2_sel[3:0] 4'0000 - end - sync always - update \dec19_in2_sel $0\dec19_in2_sel[3:0] - end - attribute \src "libresoc.v:8628.3-8679.6" - process $proc$libresoc.v:8628$329 - assign { } { } - assign { } { } - assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:8629.5-8629.29" - switch \initial - attribute \src "libresoc.v:8629.9-8629.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - case - assign $1\dec19_in3_sel[1:0] 2'00 - end - sync always - update \dec19_in3_sel $0\dec19_in3_sel[1:0] - end - attribute \src "libresoc.v:8680.3-8731.6" - process $proc$libresoc.v:8680$330 - assign { } { } - assign { } { } - assign $0\dec19_out_sel[1:0] $1\dec19_out_sel[1:0] - attribute \src "libresoc.v:8681.5-8681.29" - switch \initial - attribute \src "libresoc.v:8681.9-8681.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'11 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'11 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'11 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - case - assign $1\dec19_out_sel[1:0] 2'00 - end - sync always - update \dec19_out_sel $0\dec19_out_sel[1:0] - end - attribute \src "libresoc.v:8732.3-8783.6" - process $proc$libresoc.v:8732$331 - assign { } { } - assign { } { } - assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:8733.5-8733.29" - switch \initial - attribute \src "libresoc.v:8733.9-8733.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'000 - case - assign $1\dec19_cr_in[2:0] 3'000 - end - sync always - update \dec19_cr_in $0\dec19_cr_in[2:0] - end - attribute \src "libresoc.v:8784.3-8835.6" - process $proc$libresoc.v:8784$332 - assign { } { } - assign { } { } - assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:8785.5-8785.29" - switch \initial - attribute \src "libresoc.v:8785.9-8785.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 - case - assign $1\dec19_cr_out[2:0] 3'000 - end - sync always - update \dec19_cr_out $0\dec19_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "libresoc.v:8841.1-10730.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2" -attribute \generator "nMigen" -module \dec2 - attribute \src "libresoc.v:10596.3-10677.6" - wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 64 $0\cia[63:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $0\cr_in1[2:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\cr_in1_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $0\cr_in2$1[2:0]$352 - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $0\cr_in2[2:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\cr_in2_ok$2[0:0]$353 - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\cr_in2_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $0\cr_out[2:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\cr_out_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 8 $0\cr_rd[7:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\cr_rd_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 8 $0\cr_wr[7:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\cr_wr_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 5 $0\ea[4:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\ea_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $0\fast1[2:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $0\fast2[2:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $0\fasto1[2:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\fasto1_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $0\fasto2[2:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\fasto2_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 12 $0\fn_unit[11:0] - attribute \src "libresoc.v:8842.7-8842.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 2 $0\input_carry[1:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 32 $0\insn[31:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 7 $0\insn_type[6:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\is_32bit[0:0] - attribute \src "libresoc.v:10576.3-10595.6" - wire $0\is_priv_insn[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\lk[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 5 $0\reg1[4:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\reg1_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 5 $0\reg2[4:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\reg2_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 5 $0\reg3[4:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\reg3_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 5 $0\rego[4:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\rego_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 10 $0\spr1[9:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 10 $0\spro[9:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\spro_ok[0:0] - attribute \src "libresoc.v:10530.3-10539.6" - wire $0\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:10566.3-10575.6" - wire width 13 $0\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:10540.3-10555.6" - wire width 3 $0\tmp_xer_in[2:0] - attribute \src "libresoc.v:10556.3-10565.6" - wire $0\tmp_xer_out[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 13 $0\trapaddr[12:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 7 $0\traptype[6:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $0\xer_in[2:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $0\xer_out[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 8 $1\asmcode[7:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 64 $1\cia[63:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $1\cr_in1[2:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\cr_in1_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $1\cr_in2$1[2:0]$354 - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $1\cr_in2[2:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\cr_in2_ok$2[0:0]$355 - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\cr_in2_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $1\cr_out[2:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\cr_out_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 8 $1\cr_rd[7:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\cr_rd_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 8 $1\cr_wr[7:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\cr_wr_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 5 $1\ea[4:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\ea_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $1\fast1[2:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $1\fast2[2:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $1\fasto1[2:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\fasto1_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $1\fasto2[2:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\fasto2_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 12 $1\fn_unit[11:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 2 $1\input_carry[1:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 32 $1\insn[31:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 7 $1\insn_type[6:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\is_32bit[0:0] - attribute \src "libresoc.v:10576.3-10595.6" - wire $1\is_priv_insn[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\lk[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\rc_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 5 $1\reg1[4:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\reg1_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 5 $1\reg2[4:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\reg2_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 5 $1\reg3[4:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\reg3_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 5 $1\rego[4:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\rego_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 10 $1\spr1[9:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 10 $1\spro[9:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\spro_ok[0:0] - attribute \src "libresoc.v:10530.3-10539.6" - wire $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:10566.3-10575.6" - wire width 13 $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:10540.3-10555.6" - wire width 3 $1\tmp_xer_in[2:0] - attribute \src "libresoc.v:10556.3-10565.6" - wire $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 13 $1\trapaddr[12:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 7 $1\traptype[6:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $1\xer_in[2:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $1\xer_out[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $2\fast1[2:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $2\fast2[2:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $2\fast2_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $2\fasto1[2:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $2\fasto1_ok[0:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire width 3 $2\fasto2[2:0] - attribute \src "libresoc.v:10596.3-10677.6" - wire $2\fasto2_ok[0:0] - attribute \src "libresoc.v:10576.3-10595.6" - wire $2\is_priv_insn[0:0] - attribute \src "libresoc.v:10540.3-10555.6" - wire width 3 $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:10381.18-10381.120" - wire $and$libresoc.v:10381$338_Y - attribute \src "libresoc.v:10382.18-10382.123" - wire $and$libresoc.v:10382$339_Y - attribute \src "libresoc.v:10383.18-10383.124" - wire $and$libresoc.v:10383$340_Y - attribute \src "libresoc.v:10377.18-10377.122" - wire $eq$libresoc.v:10377$334_Y - attribute \src "libresoc.v:10378.18-10378.122" - wire $eq$libresoc.v:10378$335_Y - attribute \src "libresoc.v:10379.18-10379.122" - wire $eq$libresoc.v:10379$336_Y - attribute \src "libresoc.v:10380.18-10380.122" - wire $eq$libresoc.v:10380$337_Y - attribute \src "libresoc.v:10384.18-10384.122" - wire $eq$libresoc.v:10384$341_Y - attribute \src "libresoc.v:10385.18-10385.116" - wire $eq$libresoc.v:10385$342_Y - attribute \src "libresoc.v:10386.18-10386.116" - wire $eq$libresoc.v:10386$343_Y - attribute \src "libresoc.v:10388.18-10388.116" - wire $eq$libresoc.v:10388$345_Y - attribute \src "libresoc.v:10387.18-10387.110" - wire $or$libresoc.v:10387$344_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:859" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:861" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:863" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:867" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:889" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:890" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:891" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:892" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:923" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:933" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" - wire width 8 output 5 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" - wire width 64 output 39 \cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 30 \cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 31 \cr_in1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 32 \cr_in2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 34 \cr_in2$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 33 \cr_in2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 35 \cr_in2_ok$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 36 \cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 37 \cr_out_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 output 51 \cr_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 52 \cr_rd_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 output 53 \cr_wr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 54 \cr_wr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" - wire width 64 input 56 \cur_dec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" - wire input 57 \cur_eint - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 input 3 \cur_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 input 2 \cur_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 \dec_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 10 \dec_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \dec_XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_a_fast_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_a_fast_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec_a_reg_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_a_reg_a_ok - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:85" - wire width 3 \dec_a_sel_in - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \dec_a_spr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_a_spr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_b_fast_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_b_fast_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec_b_reg_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_b_reg_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - wire width 4 \dec_b_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec_c_reg_c - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_c_reg_c_ok - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" - wire width 2 \dec_c_sel_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_cr_in_cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_cr_in_cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_cr_in_cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_cr_in_cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_cr_in_cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_cr_in_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \dec_cr_in_cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_cr_in_cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 3 \dec_cr_in_sel_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_cr_out_cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \dec_cr_out_cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_cr_out_cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 3 \dec_cr_out_sel_in - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec_cry_in - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:885" - wire \dec_irq_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_o2_fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_o2_fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363" - wire \dec_o2_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec_o2_reg_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_o2_reg_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_o_fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_o_fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec_o_reg_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_o_reg_o_ok - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" - wire width 2 \dec_o_sel_in - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \dec_o_spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_o_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_oe_oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec_opcode_in - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_rc_rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec_rc_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" - wire width 2 \dec_rc_sel_in - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 output 8 \ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 9 \ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:884" - wire \ext_irq_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 22 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 23 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 24 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 25 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 26 \fasto1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 27 \fasto1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 28 \fasto2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 29 \fasto2_ok - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" - wire width 12 output 42 \fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:887" - wire \illeg_ok - attribute \src "libresoc.v:8842.7-8842.15" - wire \initial - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" - wire width 2 output 48 \input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" - wire width 32 output 40 \insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" - wire width 32 \insn_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" - wire width 32 \insn_in$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" - wire width 32 \insn_in$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" - wire width 32 \insn_in$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" - wire width 32 \insn_in$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" - wire width 32 \insn_in$9 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" - wire width 7 output 41 \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire output 55 \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:41" - wire \is_priv_insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire output 43 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" - wire width 64 output 38 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 46 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 47 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" - wire \priv_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 input 4 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 44 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 45 \rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 output 10 \reg1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 11 \reg1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 output 12 \reg2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 13 \reg2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 output 14 \reg3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 15 \reg3_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 output 6 \rego - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 7 \rego_ok - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:362" - wire width 2 \sel_in - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 output 18 \spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 19 \spr1_ok - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 output 16 \spro - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 17 \spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" - wire width 8 \tmp_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \tmp_cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_cr_in1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \tmp_cr_in2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \tmp_cr_in2$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_cr_in2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_cr_in2_ok$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \tmp_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_cr_out_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \tmp_ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \tmp_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \tmp_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \tmp_fasto1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_fasto1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \tmp_fasto2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_fasto2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \tmp_reg1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_reg1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \tmp_reg2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_reg2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \tmp_reg3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_reg3_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \tmp_rego - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_rego_ok - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \tmp_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_spr1_ok - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \tmp_spro - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" - wire width 64 \tmp_tmp_cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \tmp_tmp_cr_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_tmp_cr_rd_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \tmp_tmp_cr_wr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_tmp_cr_wr_ok - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" - wire width 12 \tmp_tmp_fn_unit - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" - wire width 2 \tmp_tmp_input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" - wire width 32 \tmp_tmp_insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" - wire width 7 \tmp_tmp_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire \tmp_tmp_is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire \tmp_tmp_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" - wire width 64 \tmp_tmp_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_tmp_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_tmp_oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_tmp_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_tmp_rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 13 \tmp_tmp_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 7 \tmp_tmp_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" - wire width 3 \tmp_xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" - wire \tmp_xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 13 output 50 \trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 7 output 49 \traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" - wire width 3 output 20 \xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" - wire output 21 \xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:889" - cell $and $and$libresoc.v:10381$338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cur_eint - connect \B \cur_msr [15] - connect \Y $and$libresoc.v:10381$338_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:890" - cell $and $and$libresoc.v:10382$339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cur_dec [63] - connect \B \cur_msr [15] - connect \Y $and$libresoc.v:10382$339_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:891" - cell $and $and$libresoc.v:10383$340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_priv_insn - connect \B \cur_msr [14] - connect \Y $and$libresoc.v:10383$340_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:859" - cell $eq $eq$libresoc.v:10377$334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0101110 - connect \Y $eq$libresoc.v:10377$334_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:861" - cell $eq $eq$libresoc.v:10378$335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0001010 - connect \Y $eq$libresoc.v:10378$335_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:863" - cell $eq $eq$libresoc.v:10379$336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0110001 - connect \Y $eq$libresoc.v:10379$336_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:867" - cell $eq $eq$libresoc.v:10380$337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0111111 - connect \Y $eq$libresoc.v:10380$337_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:892" - cell $eq $eq$libresoc.v:10384$341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0000000 - connect \Y $eq$libresoc.v:10384$341_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:923" - cell $eq $eq$libresoc.v:10385$342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'0111111 - connect \Y $eq$libresoc.v:10385$342_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924" - cell $eq $eq$libresoc.v:10386$343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'1001001 - connect \Y $eq$libresoc.v:10386$343_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:933" - cell $eq $eq$libresoc.v:10388$345 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'1000110 - connect \Y $eq$libresoc.v:10388$345_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924" - cell $or $or$libresoc.v:10387$344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$29 - connect \B \$31 - connect \Y $or$libresoc.v:10387$344_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:10389.7-10426.4" - cell \dec \dec - connect \BA \dec_BA - connect \BB \dec_BB - connect \BC \dec_BC - connect \BI \dec_BI - connect \BO \dec_BO - connect \BT \dec_BT - connect \FXM \dec_FXM - connect \LK \dec_LK - connect \OE \dec_OE - connect \RA \dec_RA - connect \RB \dec_RB - connect \RS \dec_RS - connect \RT \dec_RT - connect \Rc \dec_Rc - connect \SPR \dec_SPR - connect \XL_BT \dec_XL_BT - connect \XL_XO \dec_XL_XO - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \asmcode \dec_asmcode - connect \bigendian \bigendian - connect \cr_in \dec_cr_in - connect \cr_out \dec_cr_out - connect \cry_in \dec_cry_in - connect \function_unit \dec_function_unit - connect \in1_sel \dec_in1_sel - connect \in2_sel \dec_in2_sel - connect \in3_sel \dec_in3_sel - connect \internal_op \dec_internal_op - connect \is_32b \dec_is_32b - connect \lk \dec_lk - connect \opcode_in \dec_opcode_in - connect \out_sel \dec_out_sel - connect \raw_opcode_in \raw_opcode_in - connect \rc_sel \dec_rc_sel - connect \upd \dec_upd - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:10427.9-10441.4" - cell \dec_a \dec_a - connect \BO \dec_BO - connect \RA \dec_RA - connect \RS \dec_RS - connect \SPR \dec_SPR - connect \XL_XO \dec_XL_XO - connect \fast_a \dec_a_fast_a - connect \fast_a_ok \dec_a_fast_a_ok - connect \internal_op \dec_internal_op - connect \reg_a \dec_a_reg_a - connect \reg_a_ok \dec_a_reg_a_ok - connect \sel_in \dec_a_sel_in - connect \spr_a \dec_a_spr_a - connect \spr_a_ok \dec_a_spr_a_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:10442.9-10452.4" - cell \dec_b \dec_b - connect \RB \dec_RB - connect \RS \dec_RS - connect \XL_XO \dec_XL_XO - connect \fast_b \dec_b_fast_b - connect \fast_b_ok \dec_b_fast_b_ok - connect \internal_op \dec_internal_op - connect \reg_b \dec_b_reg_b - connect \reg_b_ok \dec_b_reg_b_ok - connect \sel_in \dec_b_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:10453.9-10459.4" - cell \dec_c \dec_c - connect \RB \dec_RB - connect \RS \dec_RS - connect \reg_c \dec_c_reg_c - connect \reg_c_ok \dec_c_reg_c_ok - connect \sel_in \dec_c_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:10460.13-10479.4" - cell \dec_cr_in \dec_cr_in$3 - connect \BA \dec_BA - connect \BB \dec_BB - connect \BC \dec_BC - connect \BI \dec_BI - connect \BT \dec_BT - connect \FXM \dec_FXM - connect \X_BFA \dec_X_BFA - connect \cr_bitfield \dec_cr_in_cr_bitfield - connect \cr_bitfield_b \dec_cr_in_cr_bitfield_b - connect \cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b_ok - connect \cr_bitfield_o \dec_cr_in_cr_bitfield_o - connect \cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o_ok - connect \cr_bitfield_ok \dec_cr_in_cr_bitfield_ok - connect \cr_fxm \dec_cr_in_cr_fxm - connect \cr_fxm_ok \dec_cr_in_cr_fxm_ok - connect \insn_in \dec_cr_in_insn_in - connect \internal_op \dec_internal_op - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:10480.14-10492.4" - cell \dec_cr_out \dec_cr_out$4 - connect \FXM \dec_FXM - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield \dec_cr_out_cr_bitfield - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \cr_fxm \dec_cr_out_cr_fxm - connect \cr_fxm_ok \dec_cr_out_cr_fxm_ok - connect \insn_in \dec_cr_out_insn_in - connect \internal_op \dec_internal_op - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:10493.9-10506.4" - cell \dec_o \dec_o - connect \BO \dec_BO - connect \RA \dec_RA - connect \RT \dec_RT - connect \SPR \dec_SPR - connect \fast_o \dec_o_fast_o - connect \fast_o_ok \dec_o_fast_o_ok - connect \internal_op \dec_internal_op - connect \reg_o \dec_o_reg_o - connect \reg_o_ok \dec_o_reg_o_ok - connect \sel_in \dec_o_sel_in - connect \spr_o \dec_o_spr_o - connect \spr_o_ok \dec_o_spr_o_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:10507.10-10516.4" - cell \dec_o2 \dec_o2 - connect \RA \dec_RA - connect \fast_o \dec_o2_fast_o - connect \fast_o_ok \dec_o2_fast_o_ok - connect \internal_op \dec_internal_op - connect \lk \dec_o2_lk - connect \reg_o \dec_o2_reg_o - connect \reg_o_ok \dec_o2_reg_o_ok - connect \upd \dec_upd - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:10517.10-10523.4" - cell \dec_oe \dec_oe - connect \OE \dec_OE - connect \internal_op \dec_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \sel_in \dec_oe_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:10524.10-10529.4" - cell \dec_rc \dec_rc - connect \Rc \dec_Rc - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \sel_in \dec_rc_sel_in - end - attribute \src "libresoc.v:10530.3-10539.6" - process $proc$libresoc.v:10530$346 - assign { } { } - assign { } { } - assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:10531.5-10531.29" - switch \initial - attribute \src "libresoc.v:10531.9-10531.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:758" - switch \dec_lk - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\tmp_tmp_lk[0:0] \dec_LK - case - assign $1\tmp_tmp_lk[0:0] 1'0 - end - sync always - update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] - end - attribute \src "libresoc.v:10540.3-10555.6" - process $proc$libresoc.v:10540$347 - assign { } { } - assign { } { } - assign { } { } - assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:10541.5-10541.29" - switch \initial - attribute \src "libresoc.v:10541.9-10541.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:859" - switch \$13 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\tmp_xer_in[2:0] 3'111 - case - assign $1\tmp_xer_in[2:0] 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:861" - switch \$15 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\tmp_xer_in[2:0] 3'001 - case - assign $2\tmp_xer_in[2:0] $1\tmp_xer_in[2:0] - end - sync always - update \tmp_xer_in $0\tmp_xer_in[2:0] - end - attribute \src "libresoc.v:10556.3-10565.6" - process $proc$libresoc.v:10556$348 - assign { } { } - assign { } { } - assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:10557.5-10557.29" - switch \initial - attribute \src "libresoc.v:10557.9-10557.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:863" - switch \$17 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\tmp_xer_out[0:0] 1'1 - case - assign $1\tmp_xer_out[0:0] 1'0 - end - sync always - update \tmp_xer_out $0\tmp_xer_out[0:0] - end - attribute \src "libresoc.v:10566.3-10575.6" - process $proc$libresoc.v:10566$349 - assign { } { } - assign { } { } - assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:10567.5-10567.29" - switch \initial - attribute \src "libresoc.v:10567.9-10567.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:867" - switch \$19 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\tmp_tmp_trapaddr[12:0] 13'0000001110000 - case - assign $1\tmp_tmp_trapaddr[12:0] 13'0000000000000 - end - sync always - update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] - end - attribute \src "libresoc.v:10576.3-10595.6" - process $proc$libresoc.v:10576$350 - assign { } { } - assign { } { } - assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] - attribute \src "libresoc.v:10577.5-10577.29" - switch \initial - attribute \src "libresoc.v:10577.9-10577.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:42" - switch \dec_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110 - assign { } { } - assign $1\is_priv_insn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'0101110 , 7'0110001 - assign { } { } - assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:49" - switch \tmp_tmp_insn [20] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\is_priv_insn[0:0] 1'1 - case - assign $2\is_priv_insn[0:0] 1'0 - end - case - assign $1\is_priv_insn[0:0] 1'0 - end - sync always - update \is_priv_insn $0\is_priv_insn[0:0] - end - attribute \src "libresoc.v:10596.3-10677.6" - process $proc$libresoc.v:10596$351 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_out[2:0] $1\cr_out[2:0] - assign $0\lk[0:0] $1\lk[0:0] - assign $0\cia[63:0] $1\cia[63:0] - assign $0\cr_in1[2:0] $1\cr_in1[2:0] - assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0] - assign $0\cr_in2[2:0] $1\cr_in2[2:0] - assign $0\cr_in2$1[2:0]$352 $1\cr_in2$1[2:0]$354 - assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0] - assign $0\cr_in2_ok$2[0:0]$353 $1\cr_in2_ok$2[0:0]$355 - assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0] - assign $0\cr_rd[7:0] $1\cr_rd[7:0] - assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0] - assign $0\cr_wr[7:0] $1\cr_wr[7:0] - assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0] - assign $0\ea[4:0] $1\ea[4:0] - assign $0\ea_ok[0:0] $1\ea_ok[0:0] - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fn_unit[11:0] $1\fn_unit[11:0] - assign $0\input_carry[1:0] $1\input_carry[1:0] - assign $0\insn[31:0] $1\insn[31:0] - assign $0\insn_type[6:0] $1\insn_type[6:0] - assign $0\is_32bit[0:0] $1\is_32bit[0:0] - assign $0\msr[63:0] $1\msr[63:0] - assign $0\oe[0:0] $1\oe[0:0] - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - assign $0\rc[0:0] $1\rc[0:0] - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - assign $0\reg1[4:0] $1\reg1[4:0] - assign $0\reg1_ok[0:0] $1\reg1_ok[0:0] - assign $0\reg2[4:0] $1\reg2[4:0] - assign $0\reg2_ok[0:0] $1\reg2_ok[0:0] - assign $0\reg3[4:0] $1\reg3[4:0] - assign $0\reg3_ok[0:0] $1\reg3_ok[0:0] - assign $0\rego[4:0] $1\rego[4:0] - assign $0\rego_ok[0:0] $1\rego_ok[0:0] - assign $0\spr1[9:0] $1\spr1[9:0] - assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] - assign $0\spro[9:0] $1\spro[9:0] - assign $0\spro_ok[0:0] $1\spro_ok[0:0] - assign $0\trapaddr[12:0] $1\trapaddr[12:0] - assign $0\traptype[6:0] $1\traptype[6:0] - assign $0\xer_in[2:0] $1\xer_in[2:0] - assign $0\xer_out[0:0] $1\xer_out[0:0] - assign $0\fasto1[2:0] $2\fasto1[2:0] - assign $0\fasto1_ok[0:0] $2\fasto1_ok[0:0] - assign $0\fasto2[2:0] $2\fasto2[2:0] - assign $0\fasto2_ok[0:0] $2\fasto2_ok[0:0] - assign $0\fast1[2:0] $2\fast1[2:0] - assign $0\fast1_ok[0:0] $2\fast1_ok[0:0] - assign $0\fast2[2:0] $2\fast2[2:0] - assign $0\fast2_ok[0:0] $2\fast2_ok[0:0] - assign $0\asmcode[7:0] \dec_asmcode - attribute \src "libresoc.v:10597.5-10597.29" - switch \initial - attribute \src "libresoc.v:10597.9-10597.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:895" - switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok } - attribute \src "libresoc.v:0.0-0.0" - case 4'---1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$355 $1\cr_in2$1[2:0]$354 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $1\insn[31:0] \dec_opcode_in - assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[11:0] 12'000010000000 - assign $1\trapaddr[12:0] 13'0000010010000 - assign $1\traptype[6:0] 7'0100000 - assign $1\msr[63:0] \cur_msr - assign $1\cia[63:0] \cur_pc - attribute \src "libresoc.v:0.0-0.0" - case 4'--1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$355 $1\cr_in2$1[2:0]$354 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $1\insn[31:0] \dec_opcode_in - assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[11:0] 12'000010000000 - assign $1\trapaddr[12:0] 13'0000001010000 - assign $1\traptype[6:0] 7'0010000 - assign $1\msr[63:0] \cur_msr - assign $1\cia[63:0] \cur_pc - attribute \src "libresoc.v:0.0-0.0" - case 4'-1-- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$355 $1\cr_in2$1[2:0]$354 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $1\insn[31:0] \dec_opcode_in - assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[11:0] 12'000010000000 - assign $1\trapaddr[12:0] 13'0000001110000 - assign $1\traptype[6:0] 7'0000010 - assign $1\msr[63:0] \cur_msr - assign $1\cia[63:0] \cur_pc - attribute \src "libresoc.v:0.0-0.0" - case 4'1--- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$355 $1\cr_in2$1[2:0]$354 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $1\insn[31:0] \dec_opcode_in - assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[11:0] 12'000010000000 - assign $1\trapaddr[12:0] 13'0000001110000 - assign $1\traptype[6:0] 7'1000000 - assign $1\msr[63:0] \cur_msr - assign $1\cia[63:0] \cur_pc - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\traptype[6:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[11:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$355 $1\cr_in2$1[2:0]$354 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$12 \tmp_cr_in2$11 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924" - switch \$33 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\fasto1[2:0] 3'011 - assign $2\fasto1_ok[0:0] 1'1 - assign $2\fasto2[2:0] 3'100 - assign $2\fasto2_ok[0:0] 1'1 - case - assign $2\fasto1[2:0] $1\fasto1[2:0] - assign $2\fasto1_ok[0:0] $1\fasto1_ok[0:0] - assign $2\fasto2[2:0] $1\fasto2[2:0] - assign $2\fasto2_ok[0:0] $1\fasto2_ok[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:933" - switch \$35 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\fast1[2:0] 3'011 - assign $2\fast1_ok[0:0] 1'1 - assign $2\fast2[2:0] 3'100 - assign $2\fast2_ok[0:0] 1'1 - case - assign $2\fast1[2:0] $1\fast1[2:0] - assign $2\fast1_ok[0:0] $1\fast1_ok[0:0] - assign $2\fast2[2:0] $1\fast2[2:0] - assign $2\fast2_ok[0:0] $1\fast2_ok[0:0] - end - sync always - update \asmcode $0\asmcode[7:0] - update \cr_out $0\cr_out[2:0] - update \lk $0\lk[0:0] - update \cia $0\cia[63:0] - update \cr_in1 $0\cr_in1[2:0] - update \cr_in1_ok $0\cr_in1_ok[0:0] - update \cr_in2 $0\cr_in2[2:0] - update \cr_in2$1 $0\cr_in2$1[2:0]$352 - update \cr_in2_ok $0\cr_in2_ok[0:0] - update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$353 - update \cr_out_ok $0\cr_out_ok[0:0] - update \cr_rd $0\cr_rd[7:0] - update \cr_rd_ok $0\cr_rd_ok[0:0] - update \cr_wr $0\cr_wr[7:0] - update \cr_wr_ok $0\cr_wr_ok[0:0] - update \ea $0\ea[4:0] - update \ea_ok $0\ea_ok[0:0] - update \fast1 $0\fast1[2:0] - update \fast1_ok $0\fast1_ok[0:0] - update \fast2 $0\fast2[2:0] - update \fast2_ok $0\fast2_ok[0:0] - update \fasto1 $0\fasto1[2:0] - update \fasto1_ok $0\fasto1_ok[0:0] - update \fasto2 $0\fasto2[2:0] - update \fasto2_ok $0\fasto2_ok[0:0] - update \fn_unit $0\fn_unit[11:0] - update \input_carry $0\input_carry[1:0] - update \insn $0\insn[31:0] - update \insn_type $0\insn_type[6:0] - update \is_32bit $0\is_32bit[0:0] - update \msr $0\msr[63:0] - update \oe $0\oe[0:0] - update \oe_ok $0\oe_ok[0:0] - update \rc $0\rc[0:0] - update \rc_ok $0\rc_ok[0:0] - update \reg1 $0\reg1[4:0] - update \reg1_ok $0\reg1_ok[0:0] - update \reg2 $0\reg2[4:0] - update \reg2_ok $0\reg2_ok[0:0] - update \reg3 $0\reg3[4:0] - update \reg3_ok $0\reg3_ok[0:0] - update \rego $0\rego[4:0] - update \rego_ok $0\rego_ok[0:0] - update \spr1 $0\spr1[9:0] - update \spr1_ok $0\spr1_ok[0:0] - update \spro $0\spro[9:0] - update \spro_ok $0\spro_ok[0:0] - update \trapaddr $0\trapaddr[12:0] - update \traptype $0\traptype[6:0] - update \xer_in $0\xer_in[2:0] - update \xer_out $0\xer_out[0:0] - end - attribute \src "libresoc.v:8842.7-8842.20" - process $proc$libresoc.v:8842$356 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - connect \$13 $eq$libresoc.v:10377$334_Y - connect \$15 $eq$libresoc.v:10378$335_Y - connect \$17 $eq$libresoc.v:10379$336_Y - connect \$19 $eq$libresoc.v:10380$337_Y - connect \$21 $and$libresoc.v:10381$338_Y - connect \$23 $and$libresoc.v:10382$339_Y - connect \$25 $and$libresoc.v:10383$340_Y - connect \$27 $eq$libresoc.v:10384$341_Y - connect \$29 $eq$libresoc.v:10385$342_Y - connect \$31 $eq$libresoc.v:10386$343_Y - connect \$33 $or$libresoc.v:10387$344_Y - connect \$35 $eq$libresoc.v:10388$345_Y - connect \tmp_asmcode 8'00000000 - connect \tmp_tmp_traptype 7'0000000 - connect \illeg_ok \$27 - connect \priv_ok \$25 - connect \dec_irq_ok \$23 - connect \ext_irq_ok \$21 - connect { \tmp_cr_out_ok \tmp_cr_out } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield } - connect { \tmp_cr_in2_ok$12 \tmp_cr_in2$11 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o } - connect { \tmp_cr_in2_ok \tmp_cr_in2 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b } - connect { \tmp_cr_in1_ok \tmp_cr_in1 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield } - connect { \tmp_fasto2_ok \tmp_fasto2 } { \dec_o2_fast_o_ok \dec_o2_fast_o } - connect { \tmp_fasto1_ok \tmp_fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o } - connect { \tmp_fast2_ok \tmp_fast2 } { \dec_b_fast_b_ok \dec_b_fast_b } - connect { \tmp_fast1_ok \tmp_fast1 } { \dec_a_fast_a_ok \dec_a_fast_a } - connect { \tmp_spro_ok \tmp_spro } { \dec_o_spr_o_ok \dec_o_spr_o } - connect { \tmp_spr1_ok \tmp_spr1 } { \dec_a_spr_a_ok \dec_a_spr_a } - connect { \tmp_ea_ok \tmp_ea } { \dec_o2_reg_o_ok \dec_o2_reg_o } - connect { \tmp_rego_ok \tmp_rego } { \dec_o_reg_o_ok \dec_o_reg_o } - connect { \tmp_reg3_ok \tmp_reg3 } { \dec_c_reg_c_ok \dec_c_reg_c } - connect { \tmp_reg2_ok \tmp_reg2 } { \dec_b_reg_b_ok \dec_b_reg_b } - connect { \tmp_reg1_ok \tmp_reg1 } { \dec_a_reg_a_ok \dec_a_reg_a } - connect \dec_o2_lk \tmp_tmp_lk - connect \sel_in \dec_out_sel - connect \dec_o_sel_in \dec_out_sel - connect \dec_c_sel_in \dec_in3_sel - connect \dec_b_sel_in \dec_in2_sel - connect \dec_a_sel_in \dec_in1_sel - connect \insn_in$10 \dec_opcode_in - connect \insn_in$9 \dec_opcode_in - connect \insn_in$8 \dec_opcode_in - connect \insn_in$7 \dec_opcode_in - connect \insn_in$6 \dec_opcode_in - connect \tmp_tmp_is_32bit \dec_is_32b - connect \tmp_tmp_input_carry \dec_cry_in - connect { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm } - connect { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm } - connect { \tmp_tmp_oe_ok \tmp_tmp_oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \tmp_tmp_rc_ok \tmp_tmp_rc } { \dec_rc_rc_ok \dec_rc_rc } - connect \tmp_tmp_fn_unit \dec_function_unit - connect \tmp_tmp_insn_type \dec_internal_op - connect \tmp_tmp_cia \cur_pc - connect \tmp_tmp_msr \cur_msr - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_cr_out - connect \dec_cr_in_sel_in \dec_cr_in - connect \dec_oe_sel_in \dec_rc_sel - connect \dec_rc_sel_in \dec_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$5 \dec_opcode_in - connect \insn_in \dec_opcode_in - connect \tmp_tmp_insn \dec_opcode_in -end -attribute \src "libresoc.v:10734.1-11881.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30" -attribute \generator "nMigen" -module \dec30 - attribute \src "libresoc.v:11177.3-11213.6" - wire width 8 $0\dec30_asmcode[7:0] - attribute \src "libresoc.v:11325.3-11361.6" - wire $0\dec30_br[0:0] - attribute \src "libresoc.v:11806.3-11842.6" - wire width 3 $0\dec30_cr_in[2:0] - attribute \src "libresoc.v:11843.3-11879.6" - wire width 3 $0\dec30_cr_out[2:0] - attribute \src "libresoc.v:11140.3-11176.6" - wire width 2 $0\dec30_cry_in[1:0] - attribute \src "libresoc.v:11288.3-11324.6" - wire $0\dec30_cry_out[0:0] - attribute \src "libresoc.v:11621.3-11657.6" - wire width 5 $0\dec30_form[4:0] - attribute \src "libresoc.v:10992.3-11028.6" - wire width 12 $0\dec30_function_unit[11:0] - attribute \src "libresoc.v:11658.3-11694.6" - wire width 3 $0\dec30_in1_sel[2:0] - attribute \src "libresoc.v:11695.3-11731.6" - wire width 4 $0\dec30_in2_sel[3:0] - attribute \src "libresoc.v:11732.3-11768.6" - wire width 2 $0\dec30_in3_sel[1:0] - attribute \src "libresoc.v:11399.3-11435.6" - wire width 7 $0\dec30_internal_op[6:0] - attribute \src "libresoc.v:11214.3-11250.6" - wire $0\dec30_inv_a[0:0] - attribute \src "libresoc.v:11251.3-11287.6" - wire $0\dec30_inv_out[0:0] - attribute \src "libresoc.v:11473.3-11509.6" - wire $0\dec30_is_32b[0:0] - attribute \src "libresoc.v:11029.3-11065.6" - wire width 4 $0\dec30_ldst_len[3:0] - attribute \src "libresoc.v:11547.3-11583.6" - wire $0\dec30_lk[0:0] - attribute \src "libresoc.v:11769.3-11805.6" - wire width 2 $0\dec30_out_sel[1:0] - attribute \src "libresoc.v:11103.3-11139.6" - wire width 2 $0\dec30_rc_sel[1:0] - attribute \src "libresoc.v:11436.3-11472.6" - wire $0\dec30_rsrv[0:0] - attribute \src "libresoc.v:11584.3-11620.6" - wire $0\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:11510.3-11546.6" - wire $0\dec30_sgn[0:0] - attribute \src "libresoc.v:11362.3-11398.6" - wire $0\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:11066.3-11102.6" - wire width 2 $0\dec30_upd[1:0] - attribute \src "libresoc.v:10735.7-10735.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:11177.3-11213.6" - wire width 8 $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:11325.3-11361.6" - wire $1\dec30_br[0:0] - attribute \src "libresoc.v:11806.3-11842.6" - wire width 3 $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:11843.3-11879.6" - wire width 3 $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:11140.3-11176.6" - wire width 2 $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:11288.3-11324.6" - wire $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:11621.3-11657.6" - wire width 5 $1\dec30_form[4:0] - attribute \src "libresoc.v:10992.3-11028.6" - wire width 12 $1\dec30_function_unit[11:0] - attribute \src "libresoc.v:11658.3-11694.6" - wire width 3 $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:11695.3-11731.6" - wire width 4 $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:11732.3-11768.6" - wire width 2 $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:11399.3-11435.6" - wire width 7 $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:11214.3-11250.6" - wire $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:11251.3-11287.6" - wire $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:11473.3-11509.6" - wire $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:11029.3-11065.6" - wire width 4 $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:11547.3-11583.6" - wire $1\dec30_lk[0:0] - attribute \src "libresoc.v:11769.3-11805.6" - wire width 2 $1\dec30_out_sel[1:0] - attribute \src "libresoc.v:11103.3-11139.6" - wire width 2 $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:11436.3-11472.6" - wire $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:11584.3-11620.6" - wire $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:11510.3-11546.6" - wire $1\dec30_sgn[0:0] - attribute \src "libresoc.v:11362.3-11398.6" - wire $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:11066.3-11102.6" - wire width 2 $1\dec30_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec30_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec30_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec30_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec30_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec30_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec30_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec30_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec30_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec30_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec30_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec30_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec30_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec30_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec30_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec30_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec30_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec30_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec30_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec30_upd - attribute \src "libresoc.v:10735.7-10735.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 4 \opcode_switch - attribute \src "libresoc.v:10735.7-10735.20" - process $proc$libresoc.v:10735$381 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:10992.3-11028.6" - process $proc$libresoc.v:10992$357 - assign { } { } - assign { } { } - assign $0\dec30_function_unit[11:0] $1\dec30_function_unit[11:0] - attribute \src "libresoc.v:10993.5-10993.29" - switch \initial - attribute \src "libresoc.v:10993.9-10993.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - case - assign $1\dec30_function_unit[11:0] 12'000000000000 - end - sync always - update \dec30_function_unit $0\dec30_function_unit[11:0] - end - attribute \src "libresoc.v:11029.3-11065.6" - process $proc$libresoc.v:11029$358 - assign { } { } - assign { } { } - assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:11030.5-11030.29" - switch \initial - attribute \src "libresoc.v:11030.9-11030.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - case - assign $1\dec30_ldst_len[3:0] 4'0000 - end - sync always - update \dec30_ldst_len $0\dec30_ldst_len[3:0] - end - attribute \src "libresoc.v:11066.3-11102.6" - process $proc$libresoc.v:11066$359 - assign { } { } - assign { } { } - assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] - attribute \src "libresoc.v:11067.5-11067.29" - switch \initial - attribute \src "libresoc.v:11067.9-11067.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - case - assign $1\dec30_upd[1:0] 2'00 - end - sync always - update \dec30_upd $0\dec30_upd[1:0] - end - attribute \src "libresoc.v:11103.3-11139.6" - process $proc$libresoc.v:11103$360 - assign { } { } - assign { } { } - assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:11104.5-11104.29" - switch \initial - attribute \src "libresoc.v:11104.9-11104.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - case - assign $1\dec30_rc_sel[1:0] 2'00 - end - sync always - update \dec30_rc_sel $0\dec30_rc_sel[1:0] - end - attribute \src "libresoc.v:11140.3-11176.6" - process $proc$libresoc.v:11140$361 - assign { } { } - assign { } { } - assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:11141.5-11141.29" - switch \initial - attribute \src "libresoc.v:11141.9-11141.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - case - assign $1\dec30_cry_in[1:0] 2'00 - end - sync always - update \dec30_cry_in $0\dec30_cry_in[1:0] - end - attribute \src "libresoc.v:11177.3-11213.6" - process $proc$libresoc.v:11177$362 - assign { } { } - assign { } { } - assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:11178.5-11178.29" - switch \initial - attribute \src "libresoc.v:11178.9-11178.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010100 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010100 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010101 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010101 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010110 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010110 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010111 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010111 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010010 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010011 - case - assign $1\dec30_asmcode[7:0] 8'00000000 - end - sync always - update \dec30_asmcode $0\dec30_asmcode[7:0] - end - attribute \src "libresoc.v:11214.3-11250.6" - process $proc$libresoc.v:11214$363 - assign { } { } - assign { } { } - assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:11215.5-11215.29" - switch \initial - attribute \src "libresoc.v:11215.9-11215.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - case - assign $1\dec30_inv_a[0:0] 1'0 - end - sync always - update \dec30_inv_a $0\dec30_inv_a[0:0] - end - attribute \src "libresoc.v:11251.3-11287.6" - process $proc$libresoc.v:11251$364 - assign { } { } - assign { } { } - assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:11252.5-11252.29" - switch \initial - attribute \src "libresoc.v:11252.9-11252.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - case - assign $1\dec30_inv_out[0:0] 1'0 - end - sync always - update \dec30_inv_out $0\dec30_inv_out[0:0] - end - attribute \src "libresoc.v:11288.3-11324.6" - process $proc$libresoc.v:11288$365 - assign { } { } - assign { } { } - assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:11289.5-11289.29" - switch \initial - attribute \src "libresoc.v:11289.9-11289.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - case - assign $1\dec30_cry_out[0:0] 1'0 - end - sync always - update \dec30_cry_out $0\dec30_cry_out[0:0] - end - attribute \src "libresoc.v:11325.3-11361.6" - process $proc$libresoc.v:11325$366 - assign { } { } - assign { } { } - assign $0\dec30_br[0:0] $1\dec30_br[0:0] - attribute \src "libresoc.v:11326.5-11326.29" - switch \initial - attribute \src "libresoc.v:11326.9-11326.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - case - assign $1\dec30_br[0:0] 1'0 - end - sync always - update \dec30_br $0\dec30_br[0:0] - end - attribute \src "libresoc.v:11362.3-11398.6" - process $proc$libresoc.v:11362$367 - assign { } { } - assign { } { } - assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:11363.5-11363.29" - switch \initial - attribute \src "libresoc.v:11363.9-11363.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - case - assign $1\dec30_sgn_ext[0:0] 1'0 - end - sync always - update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] - end - attribute \src "libresoc.v:11399.3-11435.6" - process $proc$libresoc.v:11399$368 - assign { } { } - assign { } { } - assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:11400.5-11400.29" - switch \initial - attribute \src "libresoc.v:11400.9-11400.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111001 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111010 - case - assign $1\dec30_internal_op[6:0] 7'0000000 - end - sync always - update \dec30_internal_op $0\dec30_internal_op[6:0] - end - attribute \src "libresoc.v:11436.3-11472.6" - process $proc$libresoc.v:11436$369 - assign { } { } - assign { } { } - assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:11437.5-11437.29" - switch \initial - attribute \src "libresoc.v:11437.9-11437.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - case - assign $1\dec30_rsrv[0:0] 1'0 - end - sync always - update \dec30_rsrv $0\dec30_rsrv[0:0] - end - attribute \src "libresoc.v:11473.3-11509.6" - process $proc$libresoc.v:11473$370 - assign { } { } - assign { } { } - assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:11474.5-11474.29" - switch \initial - attribute \src "libresoc.v:11474.9-11474.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - case - assign $1\dec30_is_32b[0:0] 1'0 - end - sync always - update \dec30_is_32b $0\dec30_is_32b[0:0] - end - attribute \src "libresoc.v:11510.3-11546.6" - process $proc$libresoc.v:11510$371 - assign { } { } - assign { } { } - assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] - attribute \src "libresoc.v:11511.5-11511.29" - switch \initial - attribute \src "libresoc.v:11511.9-11511.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - case - assign $1\dec30_sgn[0:0] 1'0 - end - sync always - update \dec30_sgn $0\dec30_sgn[0:0] - end - attribute \src "libresoc.v:11547.3-11583.6" - process $proc$libresoc.v:11547$372 - assign { } { } - assign { } { } - assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] - attribute \src "libresoc.v:11548.5-11548.29" - switch \initial - attribute \src "libresoc.v:11548.9-11548.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - case - assign $1\dec30_lk[0:0] 1'0 - end - sync always - update \dec30_lk $0\dec30_lk[0:0] - end - attribute \src "libresoc.v:11584.3-11620.6" - process $proc$libresoc.v:11584$373 - assign { } { } - assign { } { } - assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:11585.5-11585.29" - switch \initial - attribute \src "libresoc.v:11585.9-11585.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - case - assign $1\dec30_sgl_pipe[0:0] 1'0 - end - sync always - update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] - end - attribute \src "libresoc.v:11621.3-11657.6" - process $proc$libresoc.v:11621$374 - assign { } { } - assign { } { } - assign $0\dec30_form[4:0] $1\dec30_form[4:0] - attribute \src "libresoc.v:11622.5-11622.29" - switch \initial - attribute \src "libresoc.v:11622.9-11622.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_form[4:0] 5'10101 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_form[4:0] 5'10101 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - case - assign $1\dec30_form[4:0] 5'00000 - end - sync always - update \dec30_form $0\dec30_form[4:0] - end - attribute \src "libresoc.v:11658.3-11694.6" - process $proc$libresoc.v:11658$375 - assign { } { } - assign { } { } - assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:11659.5-11659.29" - switch \initial - attribute \src "libresoc.v:11659.9-11659.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - case - assign $1\dec30_in1_sel[2:0] 3'000 - end - sync always - update \dec30_in1_sel $0\dec30_in1_sel[2:0] - end - attribute \src "libresoc.v:11695.3-11731.6" - process $proc$libresoc.v:11695$376 - assign { } { } - assign { } { } - assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:11696.5-11696.29" - switch \initial - attribute \src "libresoc.v:11696.9-11696.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'0001 - case - assign $1\dec30_in2_sel[3:0] 4'0000 - end - sync always - update \dec30_in2_sel $0\dec30_in2_sel[3:0] - end - attribute \src "libresoc.v:11732.3-11768.6" - process $proc$libresoc.v:11732$377 - assign { } { } - assign { } { } - assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:11733.5-11733.29" - switch \initial - attribute \src "libresoc.v:11733.9-11733.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - case - assign $1\dec30_in3_sel[1:0] 2'00 - end - sync always - update \dec30_in3_sel $0\dec30_in3_sel[1:0] - end - attribute \src "libresoc.v:11769.3-11805.6" - process $proc$libresoc.v:11769$378 - assign { } { } - assign { } { } - assign $0\dec30_out_sel[1:0] $1\dec30_out_sel[1:0] - attribute \src "libresoc.v:11770.5-11770.29" - switch \initial - attribute \src "libresoc.v:11770.9-11770.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - case - assign $1\dec30_out_sel[1:0] 2'00 - end - sync always - update \dec30_out_sel $0\dec30_out_sel[1:0] - end - attribute \src "libresoc.v:11806.3-11842.6" - process $proc$libresoc.v:11806$379 - assign { } { } - assign { } { } - assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:11807.5-11807.29" - switch \initial - attribute \src "libresoc.v:11807.9-11807.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - case - assign $1\dec30_cr_in[2:0] 3'000 - end - sync always - update \dec30_cr_in $0\dec30_cr_in[2:0] - end - attribute \src "libresoc.v:11843.3-11879.6" - process $proc$libresoc.v:11843$380 - assign { } { } - assign { } { } - assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:11844.5-11844.29" - switch \initial - attribute \src "libresoc.v:11844.9-11844.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - case - assign $1\dec30_cr_out[2:0] 3'000 - end - sync always - update \dec30_cr_out $0\dec30_cr_out[2:0] - end - connect \opcode_switch \opcode_in [4:1] -end -attribute \src "libresoc.v:11885.1-18255.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31" -attribute \generator "nMigen" -module \dec31 - attribute \src "libresoc.v:16954.3-17014.6" - wire width 8 $0\dec31_asmcode[7:0] - attribute \src "libresoc.v:17808.3-17868.6" - wire $0\dec31_br[0:0] - attribute \src "libresoc.v:17259.3-17319.6" - wire width 3 $0\dec31_cr_in[2:0] - attribute \src "libresoc.v:17320.3-17380.6" - wire width 3 $0\dec31_cr_out[2:0] - attribute \src "libresoc.v:17564.3-17624.6" - wire width 2 $0\dec31_cry_in[1:0] - attribute \src "libresoc.v:17747.3-17807.6" - wire $0\dec31_cry_out[0:0] - attribute \src "libresoc.v:16893.3-16953.6" - wire width 5 $0\dec31_form[4:0] - attribute \src "libresoc.v:16771.3-16831.6" - wire width 12 $0\dec31_function_unit[11:0] - attribute \src "libresoc.v:17015.3-17075.6" - wire width 3 $0\dec31_in1_sel[2:0] - attribute \src "libresoc.v:17076.3-17136.6" - wire width 4 $0\dec31_in2_sel[3:0] - attribute \src "libresoc.v:17137.3-17197.6" - wire width 2 $0\dec31_in3_sel[1:0] - attribute \src "libresoc.v:16832.3-16892.6" - wire width 7 $0\dec31_internal_op[6:0] - attribute \src "libresoc.v:17625.3-17685.6" - wire $0\dec31_inv_a[0:0] - attribute \src "libresoc.v:17686.3-17746.6" - wire $0\dec31_inv_out[0:0] - attribute \src "libresoc.v:17991.3-18051.6" - wire $0\dec31_is_32b[0:0] - attribute \src "libresoc.v:17381.3-17441.6" - wire width 4 $0\dec31_ldst_len[3:0] - attribute \src "libresoc.v:18113.3-18173.6" - wire $0\dec31_lk[0:0] - attribute \src "libresoc.v:17198.3-17258.6" - wire width 2 $0\dec31_out_sel[1:0] - attribute \src "libresoc.v:17503.3-17563.6" - wire width 2 $0\dec31_rc_sel[1:0] - attribute \src "libresoc.v:17930.3-17990.6" - wire $0\dec31_rsrv[0:0] - attribute \src "libresoc.v:18174.3-18234.6" - wire $0\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:18052.3-18112.6" - wire $0\dec31_sgn[0:0] - attribute \src "libresoc.v:17869.3-17929.6" - wire $0\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:17442.3-17502.6" - wire width 2 $0\dec31_upd[1:0] - attribute \src "libresoc.v:11886.7-11886.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:16954.3-17014.6" - wire width 8 $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:17808.3-17868.6" - wire $1\dec31_br[0:0] - attribute \src "libresoc.v:17259.3-17319.6" - wire width 3 $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:17320.3-17380.6" - wire width 3 $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:17564.3-17624.6" - wire width 2 $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:17747.3-17807.6" - wire $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:16893.3-16953.6" - wire width 5 $1\dec31_form[4:0] - attribute \src "libresoc.v:16771.3-16831.6" - wire width 12 $1\dec31_function_unit[11:0] - attribute \src "libresoc.v:17015.3-17075.6" - wire width 3 $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:17076.3-17136.6" - wire width 4 $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:17137.3-17197.6" - wire width 2 $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:16832.3-16892.6" - wire width 7 $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:17625.3-17685.6" - wire $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:17686.3-17746.6" - wire $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:17991.3-18051.6" - wire $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:17381.3-17441.6" - wire width 4 $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:18113.3-18173.6" - wire $1\dec31_lk[0:0] - attribute \src "libresoc.v:17198.3-17258.6" - wire width 2 $1\dec31_out_sel[1:0] - attribute \src "libresoc.v:17503.3-17563.6" - wire width 2 $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:17930.3-17990.6" - wire $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:18174.3-18234.6" - wire $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:18052.3-18112.6" - wire $1\dec31_sgn[0:0] - attribute \src "libresoc.v:17869.3-17929.6" - wire $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:17442.3-17502.6" - wire width 2 $1\dec31_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec31_dec_sub0_dec31_dec_sub0_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub0_dec31_dec_sub0_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub0_dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub0_dec31_dec_sub0_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec31_dec_sub0_dec31_dec_sub0_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec31_dec_sub0_dec31_dec_sub0_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub0_dec31_dec_sub0_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub0_dec31_dec_sub0_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub0_dec31_dec_sub0_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec31_dec_sub0_dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub0_dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub0_dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub0_dec31_dec_sub0_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub0_dec31_dec_sub0_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub0_dec31_dec_sub0_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub0_dec31_dec_sub0_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub0_dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub0_dec31_dec_sub0_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub0_dec31_dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub0_dec31_dec_sub0_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub0_dec31_dec_sub0_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec31_dec_sub0_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec31_dec_sub10_dec31_dec_sub10_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub10_dec31_dec_sub10_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub10_dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub10_dec31_dec_sub10_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec31_dec_sub10_dec31_dec_sub10_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec31_dec_sub10_dec31_dec_sub10_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub10_dec31_dec_sub10_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub10_dec31_dec_sub10_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub10_dec31_dec_sub10_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec31_dec_sub10_dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub10_dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub10_dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub10_dec31_dec_sub10_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub10_dec31_dec_sub10_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub10_dec31_dec_sub10_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub10_dec31_dec_sub10_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub10_dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub10_dec31_dec_sub10_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub10_dec31_dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub10_dec31_dec_sub10_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub10_dec31_dec_sub10_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec31_dec_sub10_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec31_dec_sub11_dec31_dec_sub11_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub11_dec31_dec_sub11_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub11_dec31_dec_sub11_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub11_dec31_dec_sub11_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub11_dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub11_dec31_dec_sub11_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec31_dec_sub11_dec31_dec_sub11_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec31_dec_sub11_dec31_dec_sub11_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub11_dec31_dec_sub11_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub11_dec31_dec_sub11_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub11_dec31_dec_sub11_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec31_dec_sub11_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub11_dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub11_dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub11_dec31_dec_sub11_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub11_dec31_dec_sub11_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub11_dec31_dec_sub11_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub11_dec31_dec_sub11_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub11_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub11_dec31_dec_sub11_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub11_dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub11_dec31_dec_sub11_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub11_dec31_dec_sub11_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec31_dec_sub11_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec31_dec_sub15_dec31_dec_sub15_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub15_dec31_dec_sub15_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub15_dec31_dec_sub15_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub15_dec31_dec_sub15_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub15_dec31_dec_sub15_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub15_dec31_dec_sub15_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec31_dec_sub15_dec31_dec_sub15_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec31_dec_sub15_dec31_dec_sub15_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub15_dec31_dec_sub15_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub15_dec31_dec_sub15_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub15_dec31_dec_sub15_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec31_dec_sub15_dec31_dec_sub15_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub15_dec31_dec_sub15_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub15_dec31_dec_sub15_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub15_dec31_dec_sub15_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub15_dec31_dec_sub15_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub15_dec31_dec_sub15_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub15_dec31_dec_sub15_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub15_dec31_dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub15_dec31_dec_sub15_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub15_dec31_dec_sub15_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub15_dec31_dec_sub15_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub15_dec31_dec_sub15_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec31_dec_sub15_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec31_dec_sub16_dec31_dec_sub16_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub16_dec31_dec_sub16_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub16_dec31_dec_sub16_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub16_dec31_dec_sub16_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub16_dec31_dec_sub16_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub16_dec31_dec_sub16_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec31_dec_sub16_dec31_dec_sub16_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec31_dec_sub16_dec31_dec_sub16_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub16_dec31_dec_sub16_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub16_dec31_dec_sub16_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub16_dec31_dec_sub16_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec31_dec_sub16_dec31_dec_sub16_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub16_dec31_dec_sub16_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub16_dec31_dec_sub16_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub16_dec31_dec_sub16_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub16_dec31_dec_sub16_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub16_dec31_dec_sub16_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub16_dec31_dec_sub16_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub16_dec31_dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub16_dec31_dec_sub16_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub16_dec31_dec_sub16_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub16_dec31_dec_sub16_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub16_dec31_dec_sub16_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec31_dec_sub16_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec31_dec_sub18_dec31_dec_sub18_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub18_dec31_dec_sub18_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub18_dec31_dec_sub18_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub18_dec31_dec_sub18_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub18_dec31_dec_sub18_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub18_dec31_dec_sub18_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec31_dec_sub18_dec31_dec_sub18_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec31_dec_sub18_dec31_dec_sub18_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub18_dec31_dec_sub18_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub18_dec31_dec_sub18_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub18_dec31_dec_sub18_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec31_dec_sub18_dec31_dec_sub18_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub18_dec31_dec_sub18_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub18_dec31_dec_sub18_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub18_dec31_dec_sub18_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub18_dec31_dec_sub18_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub18_dec31_dec_sub18_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub18_dec31_dec_sub18_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub18_dec31_dec_sub18_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub18_dec31_dec_sub18_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub18_dec31_dec_sub18_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub18_dec31_dec_sub18_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub18_dec31_dec_sub18_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec31_dec_sub18_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec31_dec_sub19_dec31_dec_sub19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub19_dec31_dec_sub19_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub19_dec31_dec_sub19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub19_dec31_dec_sub19_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub19_dec31_dec_sub19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub19_dec31_dec_sub19_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec31_dec_sub19_dec31_dec_sub19_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec31_dec_sub19_dec31_dec_sub19_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub19_dec31_dec_sub19_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub19_dec31_dec_sub19_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub19_dec31_dec_sub19_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec31_dec_sub19_dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub19_dec31_dec_sub19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub19_dec31_dec_sub19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub19_dec31_dec_sub19_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub19_dec31_dec_sub19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub19_dec31_dec_sub19_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub19_dec31_dec_sub19_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub19_dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub19_dec31_dec_sub19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub19_dec31_dec_sub19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub19_dec31_dec_sub19_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub19_dec31_dec_sub19_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec31_dec_sub19_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec31_dec_sub20_dec31_dec_sub20_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub20_dec31_dec_sub20_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub20_dec31_dec_sub20_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub20_dec31_dec_sub20_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub20_dec31_dec_sub20_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub20_dec31_dec_sub20_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec31_dec_sub20_dec31_dec_sub20_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec31_dec_sub20_dec31_dec_sub20_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub20_dec31_dec_sub20_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub20_dec31_dec_sub20_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub20_dec31_dec_sub20_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec31_dec_sub20_dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub20_dec31_dec_sub20_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub20_dec31_dec_sub20_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub20_dec31_dec_sub20_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub20_dec31_dec_sub20_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub20_dec31_dec_sub20_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub20_dec31_dec_sub20_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub20_dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub20_dec31_dec_sub20_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub20_dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub20_dec31_dec_sub20_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub20_dec31_dec_sub20_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec31_dec_sub20_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec31_dec_sub21_dec31_dec_sub21_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub21_dec31_dec_sub21_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub21_dec31_dec_sub21_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub21_dec31_dec_sub21_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub21_dec31_dec_sub21_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub21_dec31_dec_sub21_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec31_dec_sub21_dec31_dec_sub21_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec31_dec_sub21_dec31_dec_sub21_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub21_dec31_dec_sub21_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub21_dec31_dec_sub21_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub21_dec31_dec_sub21_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec31_dec_sub21_dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub21_dec31_dec_sub21_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub21_dec31_dec_sub21_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub21_dec31_dec_sub21_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub21_dec31_dec_sub21_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub21_dec31_dec_sub21_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub21_dec31_dec_sub21_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub21_dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub21_dec31_dec_sub21_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub21_dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub21_dec31_dec_sub21_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub21_dec31_dec_sub21_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec31_dec_sub21_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec31_dec_sub22_dec31_dec_sub22_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub22_dec31_dec_sub22_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub22_dec31_dec_sub22_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub22_dec31_dec_sub22_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub22_dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub22_dec31_dec_sub22_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec31_dec_sub22_dec31_dec_sub22_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec31_dec_sub22_dec31_dec_sub22_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub22_dec31_dec_sub22_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub22_dec31_dec_sub22_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub22_dec31_dec_sub22_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec31_dec_sub22_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub22_dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub22_dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub22_dec31_dec_sub22_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub22_dec31_dec_sub22_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub22_dec31_dec_sub22_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub22_dec31_dec_sub22_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub22_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub22_dec31_dec_sub22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub22_dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub22_dec31_dec_sub22_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub22_dec31_dec_sub22_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec31_dec_sub22_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec31_dec_sub23_dec31_dec_sub23_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub23_dec31_dec_sub23_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub23_dec31_dec_sub23_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub23_dec31_dec_sub23_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub23_dec31_dec_sub23_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub23_dec31_dec_sub23_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec31_dec_sub23_dec31_dec_sub23_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec31_dec_sub23_dec31_dec_sub23_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub23_dec31_dec_sub23_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub23_dec31_dec_sub23_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub23_dec31_dec_sub23_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec31_dec_sub23_dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub23_dec31_dec_sub23_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub23_dec31_dec_sub23_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub23_dec31_dec_sub23_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub23_dec31_dec_sub23_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub23_dec31_dec_sub23_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub23_dec31_dec_sub23_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub23_dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub23_dec31_dec_sub23_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub23_dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub23_dec31_dec_sub23_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub23_dec31_dec_sub23_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec31_dec_sub23_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec31_dec_sub24_dec31_dec_sub24_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub24_dec31_dec_sub24_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub24_dec31_dec_sub24_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub24_dec31_dec_sub24_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub24_dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub24_dec31_dec_sub24_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec31_dec_sub24_dec31_dec_sub24_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec31_dec_sub24_dec31_dec_sub24_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub24_dec31_dec_sub24_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub24_dec31_dec_sub24_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub24_dec31_dec_sub24_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec31_dec_sub24_dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub24_dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub24_dec31_dec_sub24_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub24_dec31_dec_sub24_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub24_dec31_dec_sub24_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub24_dec31_dec_sub24_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub24_dec31_dec_sub24_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub24_dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub24_dec31_dec_sub24_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub24_dec31_dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub24_dec31_dec_sub24_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub24_dec31_dec_sub24_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec31_dec_sub24_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec31_dec_sub26_dec31_dec_sub26_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub26_dec31_dec_sub26_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub26_dec31_dec_sub26_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub26_dec31_dec_sub26_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub26_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub26_dec31_dec_sub26_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec31_dec_sub26_dec31_dec_sub26_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec31_dec_sub26_dec31_dec_sub26_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub26_dec31_dec_sub26_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub26_dec31_dec_sub26_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub26_dec31_dec_sub26_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec31_dec_sub26_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub26_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub26_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub26_dec31_dec_sub26_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub26_dec31_dec_sub26_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub26_dec31_dec_sub26_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub26_dec31_dec_sub26_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub26_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub26_dec31_dec_sub26_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub26_dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub26_dec31_dec_sub26_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub26_dec31_dec_sub26_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec31_dec_sub26_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec31_dec_sub27_dec31_dec_sub27_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub27_dec31_dec_sub27_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub27_dec31_dec_sub27_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub27_dec31_dec_sub27_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub27_dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub27_dec31_dec_sub27_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec31_dec_sub27_dec31_dec_sub27_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec31_dec_sub27_dec31_dec_sub27_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub27_dec31_dec_sub27_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub27_dec31_dec_sub27_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub27_dec31_dec_sub27_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec31_dec_sub27_dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub27_dec31_dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub27_dec31_dec_sub27_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub27_dec31_dec_sub27_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub27_dec31_dec_sub27_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub27_dec31_dec_sub27_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub27_dec31_dec_sub27_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub27_dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub27_dec31_dec_sub27_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub27_dec31_dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub27_dec31_dec_sub27_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub27_dec31_dec_sub27_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec31_dec_sub27_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec31_dec_sub28_dec31_dec_sub28_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub28_dec31_dec_sub28_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub28_dec31_dec_sub28_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub28_dec31_dec_sub28_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub28_dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub28_dec31_dec_sub28_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec31_dec_sub28_dec31_dec_sub28_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec31_dec_sub28_dec31_dec_sub28_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub28_dec31_dec_sub28_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub28_dec31_dec_sub28_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub28_dec31_dec_sub28_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec31_dec_sub28_dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub28_dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub28_dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub28_dec31_dec_sub28_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub28_dec31_dec_sub28_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub28_dec31_dec_sub28_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub28_dec31_dec_sub28_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub28_dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub28_dec31_dec_sub28_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub28_dec31_dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub28_dec31_dec_sub28_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub28_dec31_dec_sub28_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec31_dec_sub28_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec31_dec_sub4_dec31_dec_sub4_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub4_dec31_dec_sub4_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub4_dec31_dec_sub4_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub4_dec31_dec_sub4_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub4_dec31_dec_sub4_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub4_dec31_dec_sub4_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec31_dec_sub4_dec31_dec_sub4_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec31_dec_sub4_dec31_dec_sub4_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub4_dec31_dec_sub4_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub4_dec31_dec_sub4_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub4_dec31_dec_sub4_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec31_dec_sub4_dec31_dec_sub4_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub4_dec31_dec_sub4_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub4_dec31_dec_sub4_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub4_dec31_dec_sub4_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub4_dec31_dec_sub4_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub4_dec31_dec_sub4_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub4_dec31_dec_sub4_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub4_dec31_dec_sub4_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub4_dec31_dec_sub4_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub4_dec31_dec_sub4_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub4_dec31_dec_sub4_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub4_dec31_dec_sub4_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec31_dec_sub4_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec31_dec_sub8_dec31_dec_sub8_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub8_dec31_dec_sub8_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub8_dec31_dec_sub8_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub8_dec31_dec_sub8_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub8_dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub8_dec31_dec_sub8_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec31_dec_sub8_dec31_dec_sub8_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec31_dec_sub8_dec31_dec_sub8_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub8_dec31_dec_sub8_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub8_dec31_dec_sub8_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub8_dec31_dec_sub8_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec31_dec_sub8_dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub8_dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub8_dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub8_dec31_dec_sub8_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub8_dec31_dec_sub8_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub8_dec31_dec_sub8_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub8_dec31_dec_sub8_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub8_dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub8_dec31_dec_sub8_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub8_dec31_dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub8_dec31_dec_sub8_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub8_dec31_dec_sub8_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec31_dec_sub8_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 \dec31_dec_sub9_dec31_dec_sub9_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub9_dec31_dec_sub9_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub9_dec31_dec_sub9_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub9_dec31_dec_sub9_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub9_dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub9_dec31_dec_sub9_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 \dec31_dec_sub9_dec31_dec_sub9_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec31_dec_sub9_dec31_dec_sub9_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec31_dec_sub9_dec31_dec_sub9_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub9_dec31_dec_sub9_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub9_dec31_dec_sub9_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec31_dec_sub9_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub9_dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub9_dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub9_dec31_dec_sub9_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec31_dec_sub9_dec31_dec_sub9_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub9_dec31_dec_sub9_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub9_dec31_dec_sub9_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub9_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub9_dec31_dec_sub9_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub9_dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec31_dec_sub9_dec31_dec_sub9_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec31_dec_sub9_dec31_dec_sub9_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec31_dec_sub9_opcode_in - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_upd - attribute \src "libresoc.v:11886.7-11886.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" - wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 10 \opcode_switch - attribute \module_not_derived 1 - attribute \src "libresoc.v:16285.18-16311.4" - cell \dec31_dec_sub0 \dec31_dec_sub0 - connect \dec31_dec_sub0_asmcode \dec31_dec_sub0_dec31_dec_sub0_asmcode - connect \dec31_dec_sub0_br \dec31_dec_sub0_dec31_dec_sub0_br - connect \dec31_dec_sub0_cr_in \dec31_dec_sub0_dec31_dec_sub0_cr_in - connect \dec31_dec_sub0_cr_out \dec31_dec_sub0_dec31_dec_sub0_cr_out - connect \dec31_dec_sub0_cry_in \dec31_dec_sub0_dec31_dec_sub0_cry_in - connect \dec31_dec_sub0_cry_out \dec31_dec_sub0_dec31_dec_sub0_cry_out - connect \dec31_dec_sub0_form \dec31_dec_sub0_dec31_dec_sub0_form - connect \dec31_dec_sub0_function_unit \dec31_dec_sub0_dec31_dec_sub0_function_unit - connect \dec31_dec_sub0_in1_sel \dec31_dec_sub0_dec31_dec_sub0_in1_sel - connect \dec31_dec_sub0_in2_sel \dec31_dec_sub0_dec31_dec_sub0_in2_sel - connect \dec31_dec_sub0_in3_sel \dec31_dec_sub0_dec31_dec_sub0_in3_sel - connect \dec31_dec_sub0_internal_op \dec31_dec_sub0_dec31_dec_sub0_internal_op - connect \dec31_dec_sub0_inv_a \dec31_dec_sub0_dec31_dec_sub0_inv_a - connect \dec31_dec_sub0_inv_out \dec31_dec_sub0_dec31_dec_sub0_inv_out - connect \dec31_dec_sub0_is_32b \dec31_dec_sub0_dec31_dec_sub0_is_32b - connect \dec31_dec_sub0_ldst_len \dec31_dec_sub0_dec31_dec_sub0_ldst_len - connect \dec31_dec_sub0_lk \dec31_dec_sub0_dec31_dec_sub0_lk - connect \dec31_dec_sub0_out_sel \dec31_dec_sub0_dec31_dec_sub0_out_sel - connect \dec31_dec_sub0_rc_sel \dec31_dec_sub0_dec31_dec_sub0_rc_sel - connect \dec31_dec_sub0_rsrv \dec31_dec_sub0_dec31_dec_sub0_rsrv - connect \dec31_dec_sub0_sgl_pipe \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe - connect \dec31_dec_sub0_sgn \dec31_dec_sub0_dec31_dec_sub0_sgn - connect \dec31_dec_sub0_sgn_ext \dec31_dec_sub0_dec31_dec_sub0_sgn_ext - connect \dec31_dec_sub0_upd \dec31_dec_sub0_dec31_dec_sub0_upd - connect \opcode_in \dec31_dec_sub0_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16312.19-16338.4" - cell \dec31_dec_sub10 \dec31_dec_sub10 - connect \dec31_dec_sub10_asmcode \dec31_dec_sub10_dec31_dec_sub10_asmcode - connect \dec31_dec_sub10_br \dec31_dec_sub10_dec31_dec_sub10_br - connect \dec31_dec_sub10_cr_in \dec31_dec_sub10_dec31_dec_sub10_cr_in - connect \dec31_dec_sub10_cr_out \dec31_dec_sub10_dec31_dec_sub10_cr_out - connect \dec31_dec_sub10_cry_in \dec31_dec_sub10_dec31_dec_sub10_cry_in - connect \dec31_dec_sub10_cry_out \dec31_dec_sub10_dec31_dec_sub10_cry_out - connect \dec31_dec_sub10_form \dec31_dec_sub10_dec31_dec_sub10_form - connect \dec31_dec_sub10_function_unit \dec31_dec_sub10_dec31_dec_sub10_function_unit - connect \dec31_dec_sub10_in1_sel \dec31_dec_sub10_dec31_dec_sub10_in1_sel - connect \dec31_dec_sub10_in2_sel \dec31_dec_sub10_dec31_dec_sub10_in2_sel - connect \dec31_dec_sub10_in3_sel \dec31_dec_sub10_dec31_dec_sub10_in3_sel - connect \dec31_dec_sub10_internal_op \dec31_dec_sub10_dec31_dec_sub10_internal_op - connect \dec31_dec_sub10_inv_a \dec31_dec_sub10_dec31_dec_sub10_inv_a - connect \dec31_dec_sub10_inv_out \dec31_dec_sub10_dec31_dec_sub10_inv_out - connect \dec31_dec_sub10_is_32b \dec31_dec_sub10_dec31_dec_sub10_is_32b - connect \dec31_dec_sub10_ldst_len \dec31_dec_sub10_dec31_dec_sub10_ldst_len - connect \dec31_dec_sub10_lk \dec31_dec_sub10_dec31_dec_sub10_lk - connect \dec31_dec_sub10_out_sel \dec31_dec_sub10_dec31_dec_sub10_out_sel - connect \dec31_dec_sub10_rc_sel \dec31_dec_sub10_dec31_dec_sub10_rc_sel - connect \dec31_dec_sub10_rsrv \dec31_dec_sub10_dec31_dec_sub10_rsrv - connect \dec31_dec_sub10_sgl_pipe \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe - connect \dec31_dec_sub10_sgn \dec31_dec_sub10_dec31_dec_sub10_sgn - connect \dec31_dec_sub10_sgn_ext \dec31_dec_sub10_dec31_dec_sub10_sgn_ext - connect \dec31_dec_sub10_upd \dec31_dec_sub10_dec31_dec_sub10_upd - connect \opcode_in \dec31_dec_sub10_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16339.19-16365.4" - cell \dec31_dec_sub11 \dec31_dec_sub11 - connect \dec31_dec_sub11_asmcode \dec31_dec_sub11_dec31_dec_sub11_asmcode - connect \dec31_dec_sub11_br \dec31_dec_sub11_dec31_dec_sub11_br - connect \dec31_dec_sub11_cr_in \dec31_dec_sub11_dec31_dec_sub11_cr_in - connect \dec31_dec_sub11_cr_out \dec31_dec_sub11_dec31_dec_sub11_cr_out - connect \dec31_dec_sub11_cry_in \dec31_dec_sub11_dec31_dec_sub11_cry_in - connect \dec31_dec_sub11_cry_out \dec31_dec_sub11_dec31_dec_sub11_cry_out - connect \dec31_dec_sub11_form \dec31_dec_sub11_dec31_dec_sub11_form - connect \dec31_dec_sub11_function_unit \dec31_dec_sub11_dec31_dec_sub11_function_unit - connect \dec31_dec_sub11_in1_sel \dec31_dec_sub11_dec31_dec_sub11_in1_sel - connect \dec31_dec_sub11_in2_sel \dec31_dec_sub11_dec31_dec_sub11_in2_sel - connect \dec31_dec_sub11_in3_sel \dec31_dec_sub11_dec31_dec_sub11_in3_sel - connect \dec31_dec_sub11_internal_op \dec31_dec_sub11_dec31_dec_sub11_internal_op - connect \dec31_dec_sub11_inv_a \dec31_dec_sub11_dec31_dec_sub11_inv_a - connect \dec31_dec_sub11_inv_out \dec31_dec_sub11_dec31_dec_sub11_inv_out - connect \dec31_dec_sub11_is_32b \dec31_dec_sub11_dec31_dec_sub11_is_32b - connect \dec31_dec_sub11_ldst_len \dec31_dec_sub11_dec31_dec_sub11_ldst_len - connect \dec31_dec_sub11_lk \dec31_dec_sub11_dec31_dec_sub11_lk - connect \dec31_dec_sub11_out_sel \dec31_dec_sub11_dec31_dec_sub11_out_sel - connect \dec31_dec_sub11_rc_sel \dec31_dec_sub11_dec31_dec_sub11_rc_sel - connect \dec31_dec_sub11_rsrv \dec31_dec_sub11_dec31_dec_sub11_rsrv - connect \dec31_dec_sub11_sgl_pipe \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe - connect \dec31_dec_sub11_sgn \dec31_dec_sub11_dec31_dec_sub11_sgn - connect \dec31_dec_sub11_sgn_ext \dec31_dec_sub11_dec31_dec_sub11_sgn_ext - connect \dec31_dec_sub11_upd \dec31_dec_sub11_dec31_dec_sub11_upd - connect \opcode_in \dec31_dec_sub11_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16366.19-16392.4" - cell \dec31_dec_sub15 \dec31_dec_sub15 - connect \dec31_dec_sub15_asmcode \dec31_dec_sub15_dec31_dec_sub15_asmcode - connect \dec31_dec_sub15_br \dec31_dec_sub15_dec31_dec_sub15_br - connect \dec31_dec_sub15_cr_in \dec31_dec_sub15_dec31_dec_sub15_cr_in - connect \dec31_dec_sub15_cr_out \dec31_dec_sub15_dec31_dec_sub15_cr_out - connect \dec31_dec_sub15_cry_in \dec31_dec_sub15_dec31_dec_sub15_cry_in - connect \dec31_dec_sub15_cry_out \dec31_dec_sub15_dec31_dec_sub15_cry_out - connect \dec31_dec_sub15_form \dec31_dec_sub15_dec31_dec_sub15_form - connect \dec31_dec_sub15_function_unit \dec31_dec_sub15_dec31_dec_sub15_function_unit - connect \dec31_dec_sub15_in1_sel \dec31_dec_sub15_dec31_dec_sub15_in1_sel - connect \dec31_dec_sub15_in2_sel \dec31_dec_sub15_dec31_dec_sub15_in2_sel - connect \dec31_dec_sub15_in3_sel \dec31_dec_sub15_dec31_dec_sub15_in3_sel - connect \dec31_dec_sub15_internal_op \dec31_dec_sub15_dec31_dec_sub15_internal_op - connect \dec31_dec_sub15_inv_a \dec31_dec_sub15_dec31_dec_sub15_inv_a - connect \dec31_dec_sub15_inv_out \dec31_dec_sub15_dec31_dec_sub15_inv_out - connect \dec31_dec_sub15_is_32b \dec31_dec_sub15_dec31_dec_sub15_is_32b - connect \dec31_dec_sub15_ldst_len \dec31_dec_sub15_dec31_dec_sub15_ldst_len - connect \dec31_dec_sub15_lk \dec31_dec_sub15_dec31_dec_sub15_lk - connect \dec31_dec_sub15_out_sel \dec31_dec_sub15_dec31_dec_sub15_out_sel - connect \dec31_dec_sub15_rc_sel \dec31_dec_sub15_dec31_dec_sub15_rc_sel - connect \dec31_dec_sub15_rsrv \dec31_dec_sub15_dec31_dec_sub15_rsrv - connect \dec31_dec_sub15_sgl_pipe \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe - connect \dec31_dec_sub15_sgn \dec31_dec_sub15_dec31_dec_sub15_sgn - connect \dec31_dec_sub15_sgn_ext \dec31_dec_sub15_dec31_dec_sub15_sgn_ext - connect \dec31_dec_sub15_upd \dec31_dec_sub15_dec31_dec_sub15_upd - connect \opcode_in \dec31_dec_sub15_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16393.19-16419.4" - cell \dec31_dec_sub16 \dec31_dec_sub16 - connect \dec31_dec_sub16_asmcode \dec31_dec_sub16_dec31_dec_sub16_asmcode - connect \dec31_dec_sub16_br \dec31_dec_sub16_dec31_dec_sub16_br - connect \dec31_dec_sub16_cr_in \dec31_dec_sub16_dec31_dec_sub16_cr_in - connect \dec31_dec_sub16_cr_out \dec31_dec_sub16_dec31_dec_sub16_cr_out - connect \dec31_dec_sub16_cry_in \dec31_dec_sub16_dec31_dec_sub16_cry_in - connect \dec31_dec_sub16_cry_out \dec31_dec_sub16_dec31_dec_sub16_cry_out - connect \dec31_dec_sub16_form \dec31_dec_sub16_dec31_dec_sub16_form - connect \dec31_dec_sub16_function_unit \dec31_dec_sub16_dec31_dec_sub16_function_unit - connect \dec31_dec_sub16_in1_sel \dec31_dec_sub16_dec31_dec_sub16_in1_sel - connect \dec31_dec_sub16_in2_sel \dec31_dec_sub16_dec31_dec_sub16_in2_sel - connect \dec31_dec_sub16_in3_sel \dec31_dec_sub16_dec31_dec_sub16_in3_sel - connect \dec31_dec_sub16_internal_op \dec31_dec_sub16_dec31_dec_sub16_internal_op - connect \dec31_dec_sub16_inv_a \dec31_dec_sub16_dec31_dec_sub16_inv_a - connect \dec31_dec_sub16_inv_out \dec31_dec_sub16_dec31_dec_sub16_inv_out - connect \dec31_dec_sub16_is_32b \dec31_dec_sub16_dec31_dec_sub16_is_32b - connect \dec31_dec_sub16_ldst_len \dec31_dec_sub16_dec31_dec_sub16_ldst_len - connect \dec31_dec_sub16_lk \dec31_dec_sub16_dec31_dec_sub16_lk - connect \dec31_dec_sub16_out_sel \dec31_dec_sub16_dec31_dec_sub16_out_sel - connect \dec31_dec_sub16_rc_sel \dec31_dec_sub16_dec31_dec_sub16_rc_sel - connect \dec31_dec_sub16_rsrv \dec31_dec_sub16_dec31_dec_sub16_rsrv - connect \dec31_dec_sub16_sgl_pipe \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe - connect \dec31_dec_sub16_sgn \dec31_dec_sub16_dec31_dec_sub16_sgn - connect \dec31_dec_sub16_sgn_ext \dec31_dec_sub16_dec31_dec_sub16_sgn_ext - connect \dec31_dec_sub16_upd \dec31_dec_sub16_dec31_dec_sub16_upd - connect \opcode_in \dec31_dec_sub16_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16420.19-16446.4" - cell \dec31_dec_sub18 \dec31_dec_sub18 - connect \dec31_dec_sub18_asmcode \dec31_dec_sub18_dec31_dec_sub18_asmcode - connect \dec31_dec_sub18_br \dec31_dec_sub18_dec31_dec_sub18_br - connect \dec31_dec_sub18_cr_in \dec31_dec_sub18_dec31_dec_sub18_cr_in - connect \dec31_dec_sub18_cr_out \dec31_dec_sub18_dec31_dec_sub18_cr_out - connect \dec31_dec_sub18_cry_in \dec31_dec_sub18_dec31_dec_sub18_cry_in - connect \dec31_dec_sub18_cry_out \dec31_dec_sub18_dec31_dec_sub18_cry_out - connect \dec31_dec_sub18_form \dec31_dec_sub18_dec31_dec_sub18_form - connect \dec31_dec_sub18_function_unit \dec31_dec_sub18_dec31_dec_sub18_function_unit - connect \dec31_dec_sub18_in1_sel \dec31_dec_sub18_dec31_dec_sub18_in1_sel - connect \dec31_dec_sub18_in2_sel \dec31_dec_sub18_dec31_dec_sub18_in2_sel - connect \dec31_dec_sub18_in3_sel \dec31_dec_sub18_dec31_dec_sub18_in3_sel - connect \dec31_dec_sub18_internal_op \dec31_dec_sub18_dec31_dec_sub18_internal_op - connect \dec31_dec_sub18_inv_a \dec31_dec_sub18_dec31_dec_sub18_inv_a - connect \dec31_dec_sub18_inv_out \dec31_dec_sub18_dec31_dec_sub18_inv_out - connect \dec31_dec_sub18_is_32b \dec31_dec_sub18_dec31_dec_sub18_is_32b - connect \dec31_dec_sub18_ldst_len \dec31_dec_sub18_dec31_dec_sub18_ldst_len - connect \dec31_dec_sub18_lk \dec31_dec_sub18_dec31_dec_sub18_lk - connect \dec31_dec_sub18_out_sel \dec31_dec_sub18_dec31_dec_sub18_out_sel - connect \dec31_dec_sub18_rc_sel \dec31_dec_sub18_dec31_dec_sub18_rc_sel - connect \dec31_dec_sub18_rsrv \dec31_dec_sub18_dec31_dec_sub18_rsrv - connect \dec31_dec_sub18_sgl_pipe \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe - connect \dec31_dec_sub18_sgn \dec31_dec_sub18_dec31_dec_sub18_sgn - connect \dec31_dec_sub18_sgn_ext \dec31_dec_sub18_dec31_dec_sub18_sgn_ext - connect \dec31_dec_sub18_upd \dec31_dec_sub18_dec31_dec_sub18_upd - connect \opcode_in \dec31_dec_sub18_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16447.19-16473.4" - cell \dec31_dec_sub19 \dec31_dec_sub19 - connect \dec31_dec_sub19_asmcode \dec31_dec_sub19_dec31_dec_sub19_asmcode - connect \dec31_dec_sub19_br \dec31_dec_sub19_dec31_dec_sub19_br - connect \dec31_dec_sub19_cr_in \dec31_dec_sub19_dec31_dec_sub19_cr_in - connect \dec31_dec_sub19_cr_out \dec31_dec_sub19_dec31_dec_sub19_cr_out - connect \dec31_dec_sub19_cry_in \dec31_dec_sub19_dec31_dec_sub19_cry_in - connect \dec31_dec_sub19_cry_out \dec31_dec_sub19_dec31_dec_sub19_cry_out - connect \dec31_dec_sub19_form \dec31_dec_sub19_dec31_dec_sub19_form - connect \dec31_dec_sub19_function_unit \dec31_dec_sub19_dec31_dec_sub19_function_unit - connect \dec31_dec_sub19_in1_sel \dec31_dec_sub19_dec31_dec_sub19_in1_sel - connect \dec31_dec_sub19_in2_sel \dec31_dec_sub19_dec31_dec_sub19_in2_sel - connect \dec31_dec_sub19_in3_sel \dec31_dec_sub19_dec31_dec_sub19_in3_sel - connect \dec31_dec_sub19_internal_op \dec31_dec_sub19_dec31_dec_sub19_internal_op - connect \dec31_dec_sub19_inv_a \dec31_dec_sub19_dec31_dec_sub19_inv_a - connect \dec31_dec_sub19_inv_out \dec31_dec_sub19_dec31_dec_sub19_inv_out - connect \dec31_dec_sub19_is_32b \dec31_dec_sub19_dec31_dec_sub19_is_32b - connect \dec31_dec_sub19_ldst_len \dec31_dec_sub19_dec31_dec_sub19_ldst_len - connect \dec31_dec_sub19_lk \dec31_dec_sub19_dec31_dec_sub19_lk - connect \dec31_dec_sub19_out_sel \dec31_dec_sub19_dec31_dec_sub19_out_sel - connect \dec31_dec_sub19_rc_sel \dec31_dec_sub19_dec31_dec_sub19_rc_sel - connect \dec31_dec_sub19_rsrv \dec31_dec_sub19_dec31_dec_sub19_rsrv - connect \dec31_dec_sub19_sgl_pipe \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe - connect \dec31_dec_sub19_sgn \dec31_dec_sub19_dec31_dec_sub19_sgn - connect \dec31_dec_sub19_sgn_ext \dec31_dec_sub19_dec31_dec_sub19_sgn_ext - connect \dec31_dec_sub19_upd \dec31_dec_sub19_dec31_dec_sub19_upd - connect \opcode_in \dec31_dec_sub19_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16474.19-16500.4" - cell \dec31_dec_sub20 \dec31_dec_sub20 - connect \dec31_dec_sub20_asmcode \dec31_dec_sub20_dec31_dec_sub20_asmcode - connect \dec31_dec_sub20_br \dec31_dec_sub20_dec31_dec_sub20_br - connect \dec31_dec_sub20_cr_in \dec31_dec_sub20_dec31_dec_sub20_cr_in - connect \dec31_dec_sub20_cr_out \dec31_dec_sub20_dec31_dec_sub20_cr_out - connect \dec31_dec_sub20_cry_in \dec31_dec_sub20_dec31_dec_sub20_cry_in - connect \dec31_dec_sub20_cry_out \dec31_dec_sub20_dec31_dec_sub20_cry_out - connect \dec31_dec_sub20_form \dec31_dec_sub20_dec31_dec_sub20_form - connect \dec31_dec_sub20_function_unit \dec31_dec_sub20_dec31_dec_sub20_function_unit - connect \dec31_dec_sub20_in1_sel \dec31_dec_sub20_dec31_dec_sub20_in1_sel - connect \dec31_dec_sub20_in2_sel \dec31_dec_sub20_dec31_dec_sub20_in2_sel - connect \dec31_dec_sub20_in3_sel \dec31_dec_sub20_dec31_dec_sub20_in3_sel - connect \dec31_dec_sub20_internal_op \dec31_dec_sub20_dec31_dec_sub20_internal_op - connect \dec31_dec_sub20_inv_a \dec31_dec_sub20_dec31_dec_sub20_inv_a - connect \dec31_dec_sub20_inv_out \dec31_dec_sub20_dec31_dec_sub20_inv_out - connect \dec31_dec_sub20_is_32b \dec31_dec_sub20_dec31_dec_sub20_is_32b - connect \dec31_dec_sub20_ldst_len \dec31_dec_sub20_dec31_dec_sub20_ldst_len - connect \dec31_dec_sub20_lk \dec31_dec_sub20_dec31_dec_sub20_lk - connect \dec31_dec_sub20_out_sel \dec31_dec_sub20_dec31_dec_sub20_out_sel - connect \dec31_dec_sub20_rc_sel \dec31_dec_sub20_dec31_dec_sub20_rc_sel - connect \dec31_dec_sub20_rsrv \dec31_dec_sub20_dec31_dec_sub20_rsrv - connect \dec31_dec_sub20_sgl_pipe \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe - connect \dec31_dec_sub20_sgn \dec31_dec_sub20_dec31_dec_sub20_sgn - connect \dec31_dec_sub20_sgn_ext \dec31_dec_sub20_dec31_dec_sub20_sgn_ext - connect \dec31_dec_sub20_upd \dec31_dec_sub20_dec31_dec_sub20_upd - connect \opcode_in \dec31_dec_sub20_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16501.19-16527.4" - cell \dec31_dec_sub21 \dec31_dec_sub21 - connect \dec31_dec_sub21_asmcode \dec31_dec_sub21_dec31_dec_sub21_asmcode - connect \dec31_dec_sub21_br \dec31_dec_sub21_dec31_dec_sub21_br - connect \dec31_dec_sub21_cr_in \dec31_dec_sub21_dec31_dec_sub21_cr_in - connect \dec31_dec_sub21_cr_out \dec31_dec_sub21_dec31_dec_sub21_cr_out - connect \dec31_dec_sub21_cry_in \dec31_dec_sub21_dec31_dec_sub21_cry_in - connect \dec31_dec_sub21_cry_out \dec31_dec_sub21_dec31_dec_sub21_cry_out - connect \dec31_dec_sub21_form \dec31_dec_sub21_dec31_dec_sub21_form - connect \dec31_dec_sub21_function_unit \dec31_dec_sub21_dec31_dec_sub21_function_unit - connect \dec31_dec_sub21_in1_sel \dec31_dec_sub21_dec31_dec_sub21_in1_sel - connect \dec31_dec_sub21_in2_sel \dec31_dec_sub21_dec31_dec_sub21_in2_sel - connect \dec31_dec_sub21_in3_sel \dec31_dec_sub21_dec31_dec_sub21_in3_sel - connect \dec31_dec_sub21_internal_op \dec31_dec_sub21_dec31_dec_sub21_internal_op - connect \dec31_dec_sub21_inv_a \dec31_dec_sub21_dec31_dec_sub21_inv_a - connect \dec31_dec_sub21_inv_out \dec31_dec_sub21_dec31_dec_sub21_inv_out - connect \dec31_dec_sub21_is_32b \dec31_dec_sub21_dec31_dec_sub21_is_32b - connect \dec31_dec_sub21_ldst_len \dec31_dec_sub21_dec31_dec_sub21_ldst_len - connect \dec31_dec_sub21_lk \dec31_dec_sub21_dec31_dec_sub21_lk - connect \dec31_dec_sub21_out_sel \dec31_dec_sub21_dec31_dec_sub21_out_sel - connect \dec31_dec_sub21_rc_sel \dec31_dec_sub21_dec31_dec_sub21_rc_sel - connect \dec31_dec_sub21_rsrv \dec31_dec_sub21_dec31_dec_sub21_rsrv - connect \dec31_dec_sub21_sgl_pipe \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe - connect \dec31_dec_sub21_sgn \dec31_dec_sub21_dec31_dec_sub21_sgn - connect \dec31_dec_sub21_sgn_ext \dec31_dec_sub21_dec31_dec_sub21_sgn_ext - connect \dec31_dec_sub21_upd \dec31_dec_sub21_dec31_dec_sub21_upd - connect \opcode_in \dec31_dec_sub21_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16528.19-16554.4" - cell \dec31_dec_sub22 \dec31_dec_sub22 - connect \dec31_dec_sub22_asmcode \dec31_dec_sub22_dec31_dec_sub22_asmcode - connect \dec31_dec_sub22_br \dec31_dec_sub22_dec31_dec_sub22_br - connect \dec31_dec_sub22_cr_in \dec31_dec_sub22_dec31_dec_sub22_cr_in - connect \dec31_dec_sub22_cr_out \dec31_dec_sub22_dec31_dec_sub22_cr_out - connect \dec31_dec_sub22_cry_in \dec31_dec_sub22_dec31_dec_sub22_cry_in - connect \dec31_dec_sub22_cry_out \dec31_dec_sub22_dec31_dec_sub22_cry_out - connect \dec31_dec_sub22_form \dec31_dec_sub22_dec31_dec_sub22_form - connect \dec31_dec_sub22_function_unit \dec31_dec_sub22_dec31_dec_sub22_function_unit - connect \dec31_dec_sub22_in1_sel \dec31_dec_sub22_dec31_dec_sub22_in1_sel - connect \dec31_dec_sub22_in2_sel \dec31_dec_sub22_dec31_dec_sub22_in2_sel - connect \dec31_dec_sub22_in3_sel \dec31_dec_sub22_dec31_dec_sub22_in3_sel - connect \dec31_dec_sub22_internal_op \dec31_dec_sub22_dec31_dec_sub22_internal_op - connect \dec31_dec_sub22_inv_a \dec31_dec_sub22_dec31_dec_sub22_inv_a - connect \dec31_dec_sub22_inv_out \dec31_dec_sub22_dec31_dec_sub22_inv_out - connect \dec31_dec_sub22_is_32b \dec31_dec_sub22_dec31_dec_sub22_is_32b - connect \dec31_dec_sub22_ldst_len \dec31_dec_sub22_dec31_dec_sub22_ldst_len - connect \dec31_dec_sub22_lk \dec31_dec_sub22_dec31_dec_sub22_lk - connect \dec31_dec_sub22_out_sel \dec31_dec_sub22_dec31_dec_sub22_out_sel - connect \dec31_dec_sub22_rc_sel \dec31_dec_sub22_dec31_dec_sub22_rc_sel - connect \dec31_dec_sub22_rsrv \dec31_dec_sub22_dec31_dec_sub22_rsrv - connect \dec31_dec_sub22_sgl_pipe \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe - connect \dec31_dec_sub22_sgn \dec31_dec_sub22_dec31_dec_sub22_sgn - connect \dec31_dec_sub22_sgn_ext \dec31_dec_sub22_dec31_dec_sub22_sgn_ext - connect \dec31_dec_sub22_upd \dec31_dec_sub22_dec31_dec_sub22_upd - connect \opcode_in \dec31_dec_sub22_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16555.19-16581.4" - cell \dec31_dec_sub23 \dec31_dec_sub23 - connect \dec31_dec_sub23_asmcode \dec31_dec_sub23_dec31_dec_sub23_asmcode - connect \dec31_dec_sub23_br \dec31_dec_sub23_dec31_dec_sub23_br - connect \dec31_dec_sub23_cr_in \dec31_dec_sub23_dec31_dec_sub23_cr_in - connect \dec31_dec_sub23_cr_out \dec31_dec_sub23_dec31_dec_sub23_cr_out - connect \dec31_dec_sub23_cry_in \dec31_dec_sub23_dec31_dec_sub23_cry_in - connect \dec31_dec_sub23_cry_out \dec31_dec_sub23_dec31_dec_sub23_cry_out - connect \dec31_dec_sub23_form \dec31_dec_sub23_dec31_dec_sub23_form - connect \dec31_dec_sub23_function_unit \dec31_dec_sub23_dec31_dec_sub23_function_unit - connect \dec31_dec_sub23_in1_sel \dec31_dec_sub23_dec31_dec_sub23_in1_sel - connect \dec31_dec_sub23_in2_sel \dec31_dec_sub23_dec31_dec_sub23_in2_sel - connect \dec31_dec_sub23_in3_sel \dec31_dec_sub23_dec31_dec_sub23_in3_sel - connect \dec31_dec_sub23_internal_op \dec31_dec_sub23_dec31_dec_sub23_internal_op - connect \dec31_dec_sub23_inv_a \dec31_dec_sub23_dec31_dec_sub23_inv_a - connect \dec31_dec_sub23_inv_out \dec31_dec_sub23_dec31_dec_sub23_inv_out - connect \dec31_dec_sub23_is_32b \dec31_dec_sub23_dec31_dec_sub23_is_32b - connect \dec31_dec_sub23_ldst_len \dec31_dec_sub23_dec31_dec_sub23_ldst_len - connect \dec31_dec_sub23_lk \dec31_dec_sub23_dec31_dec_sub23_lk - connect \dec31_dec_sub23_out_sel \dec31_dec_sub23_dec31_dec_sub23_out_sel - connect \dec31_dec_sub23_rc_sel \dec31_dec_sub23_dec31_dec_sub23_rc_sel - connect \dec31_dec_sub23_rsrv \dec31_dec_sub23_dec31_dec_sub23_rsrv - connect \dec31_dec_sub23_sgl_pipe \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe - connect \dec31_dec_sub23_sgn \dec31_dec_sub23_dec31_dec_sub23_sgn - connect \dec31_dec_sub23_sgn_ext \dec31_dec_sub23_dec31_dec_sub23_sgn_ext - connect \dec31_dec_sub23_upd \dec31_dec_sub23_dec31_dec_sub23_upd - connect \opcode_in \dec31_dec_sub23_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16582.19-16608.4" - cell \dec31_dec_sub24 \dec31_dec_sub24 - connect \dec31_dec_sub24_asmcode \dec31_dec_sub24_dec31_dec_sub24_asmcode - connect \dec31_dec_sub24_br \dec31_dec_sub24_dec31_dec_sub24_br - connect \dec31_dec_sub24_cr_in \dec31_dec_sub24_dec31_dec_sub24_cr_in - connect \dec31_dec_sub24_cr_out \dec31_dec_sub24_dec31_dec_sub24_cr_out - connect \dec31_dec_sub24_cry_in \dec31_dec_sub24_dec31_dec_sub24_cry_in - connect \dec31_dec_sub24_cry_out \dec31_dec_sub24_dec31_dec_sub24_cry_out - connect \dec31_dec_sub24_form \dec31_dec_sub24_dec31_dec_sub24_form - connect \dec31_dec_sub24_function_unit \dec31_dec_sub24_dec31_dec_sub24_function_unit - connect \dec31_dec_sub24_in1_sel \dec31_dec_sub24_dec31_dec_sub24_in1_sel - connect \dec31_dec_sub24_in2_sel \dec31_dec_sub24_dec31_dec_sub24_in2_sel - connect \dec31_dec_sub24_in3_sel \dec31_dec_sub24_dec31_dec_sub24_in3_sel - connect \dec31_dec_sub24_internal_op \dec31_dec_sub24_dec31_dec_sub24_internal_op - connect \dec31_dec_sub24_inv_a \dec31_dec_sub24_dec31_dec_sub24_inv_a - connect \dec31_dec_sub24_inv_out \dec31_dec_sub24_dec31_dec_sub24_inv_out - connect \dec31_dec_sub24_is_32b \dec31_dec_sub24_dec31_dec_sub24_is_32b - connect \dec31_dec_sub24_ldst_len \dec31_dec_sub24_dec31_dec_sub24_ldst_len - connect \dec31_dec_sub24_lk \dec31_dec_sub24_dec31_dec_sub24_lk - connect \dec31_dec_sub24_out_sel \dec31_dec_sub24_dec31_dec_sub24_out_sel - connect \dec31_dec_sub24_rc_sel \dec31_dec_sub24_dec31_dec_sub24_rc_sel - connect \dec31_dec_sub24_rsrv \dec31_dec_sub24_dec31_dec_sub24_rsrv - connect \dec31_dec_sub24_sgl_pipe \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe - connect \dec31_dec_sub24_sgn \dec31_dec_sub24_dec31_dec_sub24_sgn - connect \dec31_dec_sub24_sgn_ext \dec31_dec_sub24_dec31_dec_sub24_sgn_ext - connect \dec31_dec_sub24_upd \dec31_dec_sub24_dec31_dec_sub24_upd - connect \opcode_in \dec31_dec_sub24_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16609.19-16635.4" - cell \dec31_dec_sub26 \dec31_dec_sub26 - connect \dec31_dec_sub26_asmcode \dec31_dec_sub26_dec31_dec_sub26_asmcode - connect \dec31_dec_sub26_br \dec31_dec_sub26_dec31_dec_sub26_br - connect \dec31_dec_sub26_cr_in \dec31_dec_sub26_dec31_dec_sub26_cr_in - connect \dec31_dec_sub26_cr_out \dec31_dec_sub26_dec31_dec_sub26_cr_out - connect \dec31_dec_sub26_cry_in \dec31_dec_sub26_dec31_dec_sub26_cry_in - connect \dec31_dec_sub26_cry_out \dec31_dec_sub26_dec31_dec_sub26_cry_out - connect \dec31_dec_sub26_form \dec31_dec_sub26_dec31_dec_sub26_form - connect \dec31_dec_sub26_function_unit \dec31_dec_sub26_dec31_dec_sub26_function_unit - connect \dec31_dec_sub26_in1_sel \dec31_dec_sub26_dec31_dec_sub26_in1_sel - connect \dec31_dec_sub26_in2_sel \dec31_dec_sub26_dec31_dec_sub26_in2_sel - connect \dec31_dec_sub26_in3_sel \dec31_dec_sub26_dec31_dec_sub26_in3_sel - connect \dec31_dec_sub26_internal_op \dec31_dec_sub26_dec31_dec_sub26_internal_op - connect \dec31_dec_sub26_inv_a \dec31_dec_sub26_dec31_dec_sub26_inv_a - connect \dec31_dec_sub26_inv_out \dec31_dec_sub26_dec31_dec_sub26_inv_out - connect \dec31_dec_sub26_is_32b \dec31_dec_sub26_dec31_dec_sub26_is_32b - connect \dec31_dec_sub26_ldst_len \dec31_dec_sub26_dec31_dec_sub26_ldst_len - connect \dec31_dec_sub26_lk \dec31_dec_sub26_dec31_dec_sub26_lk - connect \dec31_dec_sub26_out_sel \dec31_dec_sub26_dec31_dec_sub26_out_sel - connect \dec31_dec_sub26_rc_sel \dec31_dec_sub26_dec31_dec_sub26_rc_sel - connect \dec31_dec_sub26_rsrv \dec31_dec_sub26_dec31_dec_sub26_rsrv - connect \dec31_dec_sub26_sgl_pipe \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe - connect \dec31_dec_sub26_sgn \dec31_dec_sub26_dec31_dec_sub26_sgn - connect \dec31_dec_sub26_sgn_ext \dec31_dec_sub26_dec31_dec_sub26_sgn_ext - connect \dec31_dec_sub26_upd \dec31_dec_sub26_dec31_dec_sub26_upd - connect \opcode_in \dec31_dec_sub26_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16636.19-16662.4" - cell \dec31_dec_sub27 \dec31_dec_sub27 - connect \dec31_dec_sub27_asmcode \dec31_dec_sub27_dec31_dec_sub27_asmcode - connect \dec31_dec_sub27_br \dec31_dec_sub27_dec31_dec_sub27_br - connect \dec31_dec_sub27_cr_in \dec31_dec_sub27_dec31_dec_sub27_cr_in - connect \dec31_dec_sub27_cr_out \dec31_dec_sub27_dec31_dec_sub27_cr_out - connect \dec31_dec_sub27_cry_in \dec31_dec_sub27_dec31_dec_sub27_cry_in - connect \dec31_dec_sub27_cry_out \dec31_dec_sub27_dec31_dec_sub27_cry_out - connect \dec31_dec_sub27_form \dec31_dec_sub27_dec31_dec_sub27_form - connect \dec31_dec_sub27_function_unit \dec31_dec_sub27_dec31_dec_sub27_function_unit - connect \dec31_dec_sub27_in1_sel \dec31_dec_sub27_dec31_dec_sub27_in1_sel - connect \dec31_dec_sub27_in2_sel \dec31_dec_sub27_dec31_dec_sub27_in2_sel - connect \dec31_dec_sub27_in3_sel \dec31_dec_sub27_dec31_dec_sub27_in3_sel - connect \dec31_dec_sub27_internal_op \dec31_dec_sub27_dec31_dec_sub27_internal_op - connect \dec31_dec_sub27_inv_a \dec31_dec_sub27_dec31_dec_sub27_inv_a - connect \dec31_dec_sub27_inv_out \dec31_dec_sub27_dec31_dec_sub27_inv_out - connect \dec31_dec_sub27_is_32b \dec31_dec_sub27_dec31_dec_sub27_is_32b - connect \dec31_dec_sub27_ldst_len \dec31_dec_sub27_dec31_dec_sub27_ldst_len - connect \dec31_dec_sub27_lk \dec31_dec_sub27_dec31_dec_sub27_lk - connect \dec31_dec_sub27_out_sel \dec31_dec_sub27_dec31_dec_sub27_out_sel - connect \dec31_dec_sub27_rc_sel \dec31_dec_sub27_dec31_dec_sub27_rc_sel - connect \dec31_dec_sub27_rsrv \dec31_dec_sub27_dec31_dec_sub27_rsrv - connect \dec31_dec_sub27_sgl_pipe \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe - connect \dec31_dec_sub27_sgn \dec31_dec_sub27_dec31_dec_sub27_sgn - connect \dec31_dec_sub27_sgn_ext \dec31_dec_sub27_dec31_dec_sub27_sgn_ext - connect \dec31_dec_sub27_upd \dec31_dec_sub27_dec31_dec_sub27_upd - connect \opcode_in \dec31_dec_sub27_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16663.19-16689.4" - cell \dec31_dec_sub28 \dec31_dec_sub28 - connect \dec31_dec_sub28_asmcode \dec31_dec_sub28_dec31_dec_sub28_asmcode - connect \dec31_dec_sub28_br \dec31_dec_sub28_dec31_dec_sub28_br - connect \dec31_dec_sub28_cr_in \dec31_dec_sub28_dec31_dec_sub28_cr_in - connect \dec31_dec_sub28_cr_out \dec31_dec_sub28_dec31_dec_sub28_cr_out - connect \dec31_dec_sub28_cry_in \dec31_dec_sub28_dec31_dec_sub28_cry_in - connect \dec31_dec_sub28_cry_out \dec31_dec_sub28_dec31_dec_sub28_cry_out - connect \dec31_dec_sub28_form \dec31_dec_sub28_dec31_dec_sub28_form - connect \dec31_dec_sub28_function_unit \dec31_dec_sub28_dec31_dec_sub28_function_unit - connect \dec31_dec_sub28_in1_sel \dec31_dec_sub28_dec31_dec_sub28_in1_sel - connect \dec31_dec_sub28_in2_sel \dec31_dec_sub28_dec31_dec_sub28_in2_sel - connect \dec31_dec_sub28_in3_sel \dec31_dec_sub28_dec31_dec_sub28_in3_sel - connect \dec31_dec_sub28_internal_op \dec31_dec_sub28_dec31_dec_sub28_internal_op - connect \dec31_dec_sub28_inv_a \dec31_dec_sub28_dec31_dec_sub28_inv_a - connect \dec31_dec_sub28_inv_out \dec31_dec_sub28_dec31_dec_sub28_inv_out - connect \dec31_dec_sub28_is_32b \dec31_dec_sub28_dec31_dec_sub28_is_32b - connect \dec31_dec_sub28_ldst_len \dec31_dec_sub28_dec31_dec_sub28_ldst_len - connect \dec31_dec_sub28_lk \dec31_dec_sub28_dec31_dec_sub28_lk - connect \dec31_dec_sub28_out_sel \dec31_dec_sub28_dec31_dec_sub28_out_sel - connect \dec31_dec_sub28_rc_sel \dec31_dec_sub28_dec31_dec_sub28_rc_sel - connect \dec31_dec_sub28_rsrv \dec31_dec_sub28_dec31_dec_sub28_rsrv - connect \dec31_dec_sub28_sgl_pipe \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe - connect \dec31_dec_sub28_sgn \dec31_dec_sub28_dec31_dec_sub28_sgn - connect \dec31_dec_sub28_sgn_ext \dec31_dec_sub28_dec31_dec_sub28_sgn_ext - connect \dec31_dec_sub28_upd \dec31_dec_sub28_dec31_dec_sub28_upd - connect \opcode_in \dec31_dec_sub28_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16690.18-16716.4" - cell \dec31_dec_sub4 \dec31_dec_sub4 - connect \dec31_dec_sub4_asmcode \dec31_dec_sub4_dec31_dec_sub4_asmcode - connect \dec31_dec_sub4_br \dec31_dec_sub4_dec31_dec_sub4_br - connect \dec31_dec_sub4_cr_in \dec31_dec_sub4_dec31_dec_sub4_cr_in - connect \dec31_dec_sub4_cr_out \dec31_dec_sub4_dec31_dec_sub4_cr_out - connect \dec31_dec_sub4_cry_in \dec31_dec_sub4_dec31_dec_sub4_cry_in - connect \dec31_dec_sub4_cry_out \dec31_dec_sub4_dec31_dec_sub4_cry_out - connect \dec31_dec_sub4_form \dec31_dec_sub4_dec31_dec_sub4_form - connect \dec31_dec_sub4_function_unit \dec31_dec_sub4_dec31_dec_sub4_function_unit - connect \dec31_dec_sub4_in1_sel \dec31_dec_sub4_dec31_dec_sub4_in1_sel - connect \dec31_dec_sub4_in2_sel \dec31_dec_sub4_dec31_dec_sub4_in2_sel - connect \dec31_dec_sub4_in3_sel \dec31_dec_sub4_dec31_dec_sub4_in3_sel - connect \dec31_dec_sub4_internal_op \dec31_dec_sub4_dec31_dec_sub4_internal_op - connect \dec31_dec_sub4_inv_a \dec31_dec_sub4_dec31_dec_sub4_inv_a - connect \dec31_dec_sub4_inv_out \dec31_dec_sub4_dec31_dec_sub4_inv_out - connect \dec31_dec_sub4_is_32b \dec31_dec_sub4_dec31_dec_sub4_is_32b - connect \dec31_dec_sub4_ldst_len \dec31_dec_sub4_dec31_dec_sub4_ldst_len - connect \dec31_dec_sub4_lk \dec31_dec_sub4_dec31_dec_sub4_lk - connect \dec31_dec_sub4_out_sel \dec31_dec_sub4_dec31_dec_sub4_out_sel - connect \dec31_dec_sub4_rc_sel \dec31_dec_sub4_dec31_dec_sub4_rc_sel - connect \dec31_dec_sub4_rsrv \dec31_dec_sub4_dec31_dec_sub4_rsrv - connect \dec31_dec_sub4_sgl_pipe \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe - connect \dec31_dec_sub4_sgn \dec31_dec_sub4_dec31_dec_sub4_sgn - connect \dec31_dec_sub4_sgn_ext \dec31_dec_sub4_dec31_dec_sub4_sgn_ext - connect \dec31_dec_sub4_upd \dec31_dec_sub4_dec31_dec_sub4_upd - connect \opcode_in \dec31_dec_sub4_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16717.18-16743.4" - cell \dec31_dec_sub8 \dec31_dec_sub8 - connect \dec31_dec_sub8_asmcode \dec31_dec_sub8_dec31_dec_sub8_asmcode - connect \dec31_dec_sub8_br \dec31_dec_sub8_dec31_dec_sub8_br - connect \dec31_dec_sub8_cr_in \dec31_dec_sub8_dec31_dec_sub8_cr_in - connect \dec31_dec_sub8_cr_out \dec31_dec_sub8_dec31_dec_sub8_cr_out - connect \dec31_dec_sub8_cry_in \dec31_dec_sub8_dec31_dec_sub8_cry_in - connect \dec31_dec_sub8_cry_out \dec31_dec_sub8_dec31_dec_sub8_cry_out - connect \dec31_dec_sub8_form \dec31_dec_sub8_dec31_dec_sub8_form - connect \dec31_dec_sub8_function_unit \dec31_dec_sub8_dec31_dec_sub8_function_unit - connect \dec31_dec_sub8_in1_sel \dec31_dec_sub8_dec31_dec_sub8_in1_sel - connect \dec31_dec_sub8_in2_sel \dec31_dec_sub8_dec31_dec_sub8_in2_sel - connect \dec31_dec_sub8_in3_sel \dec31_dec_sub8_dec31_dec_sub8_in3_sel - connect \dec31_dec_sub8_internal_op \dec31_dec_sub8_dec31_dec_sub8_internal_op - connect \dec31_dec_sub8_inv_a \dec31_dec_sub8_dec31_dec_sub8_inv_a - connect \dec31_dec_sub8_inv_out \dec31_dec_sub8_dec31_dec_sub8_inv_out - connect \dec31_dec_sub8_is_32b \dec31_dec_sub8_dec31_dec_sub8_is_32b - connect \dec31_dec_sub8_ldst_len \dec31_dec_sub8_dec31_dec_sub8_ldst_len - connect \dec31_dec_sub8_lk \dec31_dec_sub8_dec31_dec_sub8_lk - connect \dec31_dec_sub8_out_sel \dec31_dec_sub8_dec31_dec_sub8_out_sel - connect \dec31_dec_sub8_rc_sel \dec31_dec_sub8_dec31_dec_sub8_rc_sel - connect \dec31_dec_sub8_rsrv \dec31_dec_sub8_dec31_dec_sub8_rsrv - connect \dec31_dec_sub8_sgl_pipe \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe - connect \dec31_dec_sub8_sgn \dec31_dec_sub8_dec31_dec_sub8_sgn - connect \dec31_dec_sub8_sgn_ext \dec31_dec_sub8_dec31_dec_sub8_sgn_ext - connect \dec31_dec_sub8_upd \dec31_dec_sub8_dec31_dec_sub8_upd - connect \opcode_in \dec31_dec_sub8_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16744.18-16770.4" - cell \dec31_dec_sub9 \dec31_dec_sub9 - connect \dec31_dec_sub9_asmcode \dec31_dec_sub9_dec31_dec_sub9_asmcode - connect \dec31_dec_sub9_br \dec31_dec_sub9_dec31_dec_sub9_br - connect \dec31_dec_sub9_cr_in \dec31_dec_sub9_dec31_dec_sub9_cr_in - connect \dec31_dec_sub9_cr_out \dec31_dec_sub9_dec31_dec_sub9_cr_out - connect \dec31_dec_sub9_cry_in \dec31_dec_sub9_dec31_dec_sub9_cry_in - connect \dec31_dec_sub9_cry_out \dec31_dec_sub9_dec31_dec_sub9_cry_out - connect \dec31_dec_sub9_form \dec31_dec_sub9_dec31_dec_sub9_form - connect \dec31_dec_sub9_function_unit \dec31_dec_sub9_dec31_dec_sub9_function_unit - connect \dec31_dec_sub9_in1_sel \dec31_dec_sub9_dec31_dec_sub9_in1_sel - connect \dec31_dec_sub9_in2_sel \dec31_dec_sub9_dec31_dec_sub9_in2_sel - connect \dec31_dec_sub9_in3_sel \dec31_dec_sub9_dec31_dec_sub9_in3_sel - connect \dec31_dec_sub9_internal_op \dec31_dec_sub9_dec31_dec_sub9_internal_op - connect \dec31_dec_sub9_inv_a \dec31_dec_sub9_dec31_dec_sub9_inv_a - connect \dec31_dec_sub9_inv_out \dec31_dec_sub9_dec31_dec_sub9_inv_out - connect \dec31_dec_sub9_is_32b \dec31_dec_sub9_dec31_dec_sub9_is_32b - connect \dec31_dec_sub9_ldst_len \dec31_dec_sub9_dec31_dec_sub9_ldst_len - connect \dec31_dec_sub9_lk \dec31_dec_sub9_dec31_dec_sub9_lk - connect \dec31_dec_sub9_out_sel \dec31_dec_sub9_dec31_dec_sub9_out_sel - connect \dec31_dec_sub9_rc_sel \dec31_dec_sub9_dec31_dec_sub9_rc_sel - connect \dec31_dec_sub9_rsrv \dec31_dec_sub9_dec31_dec_sub9_rsrv - connect \dec31_dec_sub9_sgl_pipe \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe - connect \dec31_dec_sub9_sgn \dec31_dec_sub9_dec31_dec_sub9_sgn - connect \dec31_dec_sub9_sgn_ext \dec31_dec_sub9_dec31_dec_sub9_sgn_ext - connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd - connect \opcode_in \dec31_dec_sub9_opcode_in - end - attribute \src "libresoc.v:11886.7-11886.20" - process $proc$libresoc.v:11886$406 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:16771.3-16831.6" - process $proc$libresoc.v:16771$382 - assign { } { } - assign { } { } - assign $0\dec31_function_unit[11:0] $1\dec31_function_unit[11:0] - attribute \src "libresoc.v:16772.5-16772.29" - switch \initial - attribute \src "libresoc.v:16772.9-16772.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub10_dec31_dec_sub10_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub28_dec31_dec_sub28_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub0_dec31_dec_sub0_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub26_dec31_dec_sub26_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub19_dec31_dec_sub19_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub22_dec31_dec_sub22_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub9_dec31_dec_sub9_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub11_dec31_dec_sub11_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub27_dec31_dec_sub27_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub15_dec31_dec_sub15_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub20_dec31_dec_sub20_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub21_dec31_dec_sub21_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub23_dec31_dec_sub23_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub16_dec31_dec_sub16_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub18_dec31_dec_sub18_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub8_dec31_dec_sub8_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub24_dec31_dec_sub24_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub4_dec31_dec_sub4_function_unit - case - assign $1\dec31_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_function_unit $0\dec31_function_unit[11:0] - end - attribute \src "libresoc.v:16832.3-16892.6" - process $proc$libresoc.v:16832$383 - assign { } { } - assign { } { } - assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:16833.5-16833.29" - switch \initial - attribute \src "libresoc.v:16833.9-16833.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub10_dec31_dec_sub10_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub28_dec31_dec_sub28_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub0_dec31_dec_sub0_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub26_dec31_dec_sub26_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub19_dec31_dec_sub19_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub22_dec31_dec_sub22_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub9_dec31_dec_sub9_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub11_dec31_dec_sub11_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub27_dec31_dec_sub27_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub15_dec31_dec_sub15_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub20_dec31_dec_sub20_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub21_dec31_dec_sub21_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub23_dec31_dec_sub23_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub16_dec31_dec_sub16_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub18_dec31_dec_sub18_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub8_dec31_dec_sub8_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub24_dec31_dec_sub24_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub4_dec31_dec_sub4_internal_op - case - assign $1\dec31_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_internal_op $0\dec31_internal_op[6:0] - end - attribute \src "libresoc.v:16893.3-16953.6" - process $proc$libresoc.v:16893$384 - assign { } { } - assign { } { } - assign $0\dec31_form[4:0] $1\dec31_form[4:0] - attribute \src "libresoc.v:16894.5-16894.29" - switch \initial - attribute \src "libresoc.v:16894.9-16894.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub10_dec31_dec_sub10_form - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub28_dec31_dec_sub28_form - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub0_dec31_dec_sub0_form - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub26_dec31_dec_sub26_form - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub19_dec31_dec_sub19_form - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub22_dec31_dec_sub22_form - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub9_dec31_dec_sub9_form - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub11_dec31_dec_sub11_form - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub27_dec31_dec_sub27_form - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub15_dec31_dec_sub15_form - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub20_dec31_dec_sub20_form - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub21_dec31_dec_sub21_form - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub23_dec31_dec_sub23_form - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub16_dec31_dec_sub16_form - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub18_dec31_dec_sub18_form - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub8_dec31_dec_sub8_form - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub24_dec31_dec_sub24_form - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub4_dec31_dec_sub4_form - case - assign $1\dec31_form[4:0] 5'00000 - end - sync always - update \dec31_form $0\dec31_form[4:0] - end - attribute \src "libresoc.v:16954.3-17014.6" - process $proc$libresoc.v:16954$385 - assign { } { } - assign { } { } - assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:16955.5-16955.29" - switch \initial - attribute \src "libresoc.v:16955.9-16955.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub10_dec31_dec_sub10_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub28_dec31_dec_sub28_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub0_dec31_dec_sub0_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub26_dec31_dec_sub26_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub19_dec31_dec_sub19_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub22_dec31_dec_sub22_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub9_dec31_dec_sub9_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub11_dec31_dec_sub11_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub27_dec31_dec_sub27_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub15_dec31_dec_sub15_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub20_dec31_dec_sub20_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub21_dec31_dec_sub21_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub23_dec31_dec_sub23_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub16_dec31_dec_sub16_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub18_dec31_dec_sub18_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub8_dec31_dec_sub8_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub24_dec31_dec_sub24_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub4_dec31_dec_sub4_asmcode - case - assign $1\dec31_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_asmcode $0\dec31_asmcode[7:0] - end - attribute \src "libresoc.v:17015.3-17075.6" - process $proc$libresoc.v:17015$386 - assign { } { } - assign { } { } - assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:17016.5-17016.29" - switch \initial - attribute \src "libresoc.v:17016.9-17016.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub10_dec31_dec_sub10_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub28_dec31_dec_sub28_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub0_dec31_dec_sub0_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub26_dec31_dec_sub26_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub19_dec31_dec_sub19_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub22_dec31_dec_sub22_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub9_dec31_dec_sub9_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub11_dec31_dec_sub11_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub27_dec31_dec_sub27_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub15_dec31_dec_sub15_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub20_dec31_dec_sub20_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub21_dec31_dec_sub21_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub23_dec31_dec_sub23_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub16_dec31_dec_sub16_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub18_dec31_dec_sub18_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub8_dec31_dec_sub8_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub24_dec31_dec_sub24_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub4_dec31_dec_sub4_in1_sel - case - assign $1\dec31_in1_sel[2:0] 3'000 - end - sync always - update \dec31_in1_sel $0\dec31_in1_sel[2:0] - end - attribute \src "libresoc.v:17076.3-17136.6" - process $proc$libresoc.v:17076$387 - assign { } { } - assign { } { } - assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:17077.5-17077.29" - switch \initial - attribute \src "libresoc.v:17077.9-17077.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub10_dec31_dec_sub10_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub28_dec31_dec_sub28_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub0_dec31_dec_sub0_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub26_dec31_dec_sub26_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub19_dec31_dec_sub19_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub22_dec31_dec_sub22_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub9_dec31_dec_sub9_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub11_dec31_dec_sub11_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub27_dec31_dec_sub27_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub15_dec31_dec_sub15_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub20_dec31_dec_sub20_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub21_dec31_dec_sub21_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub23_dec31_dec_sub23_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub16_dec31_dec_sub16_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub18_dec31_dec_sub18_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub8_dec31_dec_sub8_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub24_dec31_dec_sub24_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub4_dec31_dec_sub4_in2_sel - case - assign $1\dec31_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_in2_sel $0\dec31_in2_sel[3:0] - end - attribute \src "libresoc.v:17137.3-17197.6" - process $proc$libresoc.v:17137$388 - assign { } { } - assign { } { } - assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:17138.5-17138.29" - switch \initial - attribute \src "libresoc.v:17138.9-17138.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_in3_sel - case - assign $1\dec31_in3_sel[1:0] 2'00 - end - sync always - update \dec31_in3_sel $0\dec31_in3_sel[1:0] - end - attribute \src "libresoc.v:17198.3-17258.6" - process $proc$libresoc.v:17198$389 - assign { } { } - assign { } { } - assign $0\dec31_out_sel[1:0] $1\dec31_out_sel[1:0] - attribute \src "libresoc.v:17199.5-17199.29" - switch \initial - attribute \src "libresoc.v:17199.9-17199.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_out_sel - case - assign $1\dec31_out_sel[1:0] 2'00 - end - sync always - update \dec31_out_sel $0\dec31_out_sel[1:0] - end - attribute \src "libresoc.v:17259.3-17319.6" - process $proc$libresoc.v:17259$390 - assign { } { } - assign { } { } - assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:17260.5-17260.29" - switch \initial - attribute \src "libresoc.v:17260.9-17260.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_in - case - assign $1\dec31_cr_in[2:0] 3'000 - end - sync always - update \dec31_cr_in $0\dec31_cr_in[2:0] - end - attribute \src "libresoc.v:17320.3-17380.6" - process $proc$libresoc.v:17320$391 - assign { } { } - assign { } { } - assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:17321.5-17321.29" - switch \initial - attribute \src "libresoc.v:17321.9-17321.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_out - case - assign $1\dec31_cr_out[2:0] 3'000 - end - sync always - update \dec31_cr_out $0\dec31_cr_out[2:0] - end - attribute \src "libresoc.v:17381.3-17441.6" - process $proc$libresoc.v:17381$392 - assign { } { } - assign { } { } - assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:17382.5-17382.29" - switch \initial - attribute \src "libresoc.v:17382.9-17382.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub10_dec31_dec_sub10_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub28_dec31_dec_sub28_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub0_dec31_dec_sub0_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub26_dec31_dec_sub26_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub19_dec31_dec_sub19_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub22_dec31_dec_sub22_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub9_dec31_dec_sub9_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub11_dec31_dec_sub11_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub27_dec31_dec_sub27_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub15_dec31_dec_sub15_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub20_dec31_dec_sub20_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub21_dec31_dec_sub21_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub23_dec31_dec_sub23_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub16_dec31_dec_sub16_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub18_dec31_dec_sub18_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub8_dec31_dec_sub8_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub24_dec31_dec_sub24_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub4_dec31_dec_sub4_ldst_len - case - assign $1\dec31_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_ldst_len $0\dec31_ldst_len[3:0] - end - attribute \src "libresoc.v:17442.3-17502.6" - process $proc$libresoc.v:17442$393 - assign { } { } - assign { } { } - assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] - attribute \src "libresoc.v:17443.5-17443.29" - switch \initial - attribute \src "libresoc.v:17443.9-17443.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub10_dec31_dec_sub10_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub28_dec31_dec_sub28_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub0_dec31_dec_sub0_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub26_dec31_dec_sub26_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub19_dec31_dec_sub19_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub22_dec31_dec_sub22_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub9_dec31_dec_sub9_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub11_dec31_dec_sub11_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub27_dec31_dec_sub27_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub15_dec31_dec_sub15_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub20_dec31_dec_sub20_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub21_dec31_dec_sub21_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub23_dec31_dec_sub23_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub16_dec31_dec_sub16_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub18_dec31_dec_sub18_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub8_dec31_dec_sub8_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub24_dec31_dec_sub24_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub4_dec31_dec_sub4_upd - case - assign $1\dec31_upd[1:0] 2'00 - end - sync always - update \dec31_upd $0\dec31_upd[1:0] - end - attribute \src "libresoc.v:17503.3-17563.6" - process $proc$libresoc.v:17503$394 - assign { } { } - assign { } { } - assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:17504.5-17504.29" - switch \initial - attribute \src "libresoc.v:17504.9-17504.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_rc_sel - case - assign $1\dec31_rc_sel[1:0] 2'00 - end - sync always - update \dec31_rc_sel $0\dec31_rc_sel[1:0] - end - attribute \src "libresoc.v:17564.3-17624.6" - process $proc$libresoc.v:17564$395 - assign { } { } - assign { } { } - assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:17565.5-17565.29" - switch \initial - attribute \src "libresoc.v:17565.9-17565.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub10_dec31_dec_sub10_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub28_dec31_dec_sub28_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub0_dec31_dec_sub0_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub26_dec31_dec_sub26_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub19_dec31_dec_sub19_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub22_dec31_dec_sub22_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub9_dec31_dec_sub9_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub11_dec31_dec_sub11_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub27_dec31_dec_sub27_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub15_dec31_dec_sub15_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub20_dec31_dec_sub20_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub21_dec31_dec_sub21_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub23_dec31_dec_sub23_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub16_dec31_dec_sub16_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub18_dec31_dec_sub18_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub8_dec31_dec_sub8_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub24_dec31_dec_sub24_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub4_dec31_dec_sub4_cry_in - case - assign $1\dec31_cry_in[1:0] 2'00 - end - sync always - update \dec31_cry_in $0\dec31_cry_in[1:0] - end - attribute \src "libresoc.v:17625.3-17685.6" - process $proc$libresoc.v:17625$396 - assign { } { } - assign { } { } - assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:17626.5-17626.29" - switch \initial - attribute \src "libresoc.v:17626.9-17626.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_a - case - assign $1\dec31_inv_a[0:0] 1'0 - end - sync always - update \dec31_inv_a $0\dec31_inv_a[0:0] - end - attribute \src "libresoc.v:17686.3-17746.6" - process $proc$libresoc.v:17686$397 - assign { } { } - assign { } { } - assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:17687.5-17687.29" - switch \initial - attribute \src "libresoc.v:17687.9-17687.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_out - case - assign $1\dec31_inv_out[0:0] 1'0 - end - sync always - update \dec31_inv_out $0\dec31_inv_out[0:0] - end - attribute \src "libresoc.v:17747.3-17807.6" - process $proc$libresoc.v:17747$398 - assign { } { } - assign { } { } - assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:17748.5-17748.29" - switch \initial - attribute \src "libresoc.v:17748.9-17748.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_cry_out - case - assign $1\dec31_cry_out[0:0] 1'0 - end - sync always - update \dec31_cry_out $0\dec31_cry_out[0:0] - end - attribute \src "libresoc.v:17808.3-17868.6" - process $proc$libresoc.v:17808$399 - assign { } { } - assign { } { } - assign $0\dec31_br[0:0] $1\dec31_br[0:0] - attribute \src "libresoc.v:17809.5-17809.29" - switch \initial - attribute \src "libresoc.v:17809.9-17809.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub10_dec31_dec_sub10_br - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub28_dec31_dec_sub28_br - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub0_dec31_dec_sub0_br - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub26_dec31_dec_sub26_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub19_dec31_dec_sub19_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub22_dec31_dec_sub22_br - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub9_dec31_dec_sub9_br - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub11_dec31_dec_sub11_br - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub27_dec31_dec_sub27_br - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub15_dec31_dec_sub15_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub20_dec31_dec_sub20_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub21_dec31_dec_sub21_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub23_dec31_dec_sub23_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub16_dec31_dec_sub16_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub18_dec31_dec_sub18_br - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub8_dec31_dec_sub8_br - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub24_dec31_dec_sub24_br - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub4_dec31_dec_sub4_br - case - assign $1\dec31_br[0:0] 1'0 - end - sync always - update \dec31_br $0\dec31_br[0:0] - end - attribute \src "libresoc.v:17869.3-17929.6" - process $proc$libresoc.v:17869$400 - assign { } { } - assign { } { } - assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:17870.5-17870.29" - switch \initial - attribute \src "libresoc.v:17870.9-17870.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn_ext - case - assign $1\dec31_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] - end - attribute \src "libresoc.v:17930.3-17990.6" - process $proc$libresoc.v:17930$401 - assign { } { } - assign { } { } - assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:17931.5-17931.29" - switch \initial - attribute \src "libresoc.v:17931.9-17931.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub10_dec31_dec_sub10_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub28_dec31_dec_sub28_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub0_dec31_dec_sub0_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub26_dec31_dec_sub26_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub19_dec31_dec_sub19_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub22_dec31_dec_sub22_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub9_dec31_dec_sub9_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub11_dec31_dec_sub11_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub27_dec31_dec_sub27_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub15_dec31_dec_sub15_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub20_dec31_dec_sub20_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub21_dec31_dec_sub21_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub23_dec31_dec_sub23_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub16_dec31_dec_sub16_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub18_dec31_dec_sub18_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub8_dec31_dec_sub8_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub24_dec31_dec_sub24_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub4_dec31_dec_sub4_rsrv - case - assign $1\dec31_rsrv[0:0] 1'0 - end - sync always - update \dec31_rsrv $0\dec31_rsrv[0:0] - end - attribute \src "libresoc.v:17991.3-18051.6" - process $proc$libresoc.v:17991$402 - assign { } { } - assign { } { } - assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:17992.5-17992.29" - switch \initial - attribute \src "libresoc.v:17992.9-17992.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub10_dec31_dec_sub10_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub28_dec31_dec_sub28_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub0_dec31_dec_sub0_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub26_dec31_dec_sub26_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub19_dec31_dec_sub19_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub22_dec31_dec_sub22_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub9_dec31_dec_sub9_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub11_dec31_dec_sub11_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub27_dec31_dec_sub27_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub15_dec31_dec_sub15_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub20_dec31_dec_sub20_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub21_dec31_dec_sub21_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub23_dec31_dec_sub23_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub16_dec31_dec_sub16_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub18_dec31_dec_sub18_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub8_dec31_dec_sub8_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub24_dec31_dec_sub24_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub4_dec31_dec_sub4_is_32b - case - assign $1\dec31_is_32b[0:0] 1'0 - end - sync always - update \dec31_is_32b $0\dec31_is_32b[0:0] - end - attribute \src "libresoc.v:18052.3-18112.6" - process $proc$libresoc.v:18052$403 - assign { } { } - assign { } { } - assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] - attribute \src "libresoc.v:18053.5-18053.29" - switch \initial - attribute \src "libresoc.v:18053.9-18053.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn - case - assign $1\dec31_sgn[0:0] 1'0 - end - sync always - update \dec31_sgn $0\dec31_sgn[0:0] - end - attribute \src "libresoc.v:18113.3-18173.6" - process $proc$libresoc.v:18113$404 - assign { } { } - assign { } { } - assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] - attribute \src "libresoc.v:18114.5-18114.29" - switch \initial - attribute \src "libresoc.v:18114.9-18114.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub10_dec31_dec_sub10_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub28_dec31_dec_sub28_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub0_dec31_dec_sub0_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub26_dec31_dec_sub26_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub19_dec31_dec_sub19_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub22_dec31_dec_sub22_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub9_dec31_dec_sub9_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub11_dec31_dec_sub11_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub27_dec31_dec_sub27_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub15_dec31_dec_sub15_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub20_dec31_dec_sub20_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub21_dec31_dec_sub21_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub23_dec31_dec_sub23_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub16_dec31_dec_sub16_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub18_dec31_dec_sub18_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub8_dec31_dec_sub8_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub24_dec31_dec_sub24_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub4_dec31_dec_sub4_lk - case - assign $1\dec31_lk[0:0] 1'0 - end - sync always - update \dec31_lk $0\dec31_lk[0:0] - end - attribute \src "libresoc.v:18174.3-18234.6" - process $proc$libresoc.v:18174$405 - assign { } { } - assign { } { } - assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:18175.5-18175.29" - switch \initial - attribute \src "libresoc.v:18175.9-18175.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe - case - assign $1\dec31_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_sgl_pipe $0\dec31_sgl_pipe[0:0] - end - connect \dec31_dec_sub4_opcode_in \opcode_in - connect \dec31_dec_sub24_opcode_in \opcode_in - connect \dec31_dec_sub8_opcode_in \opcode_in - connect \dec31_dec_sub18_opcode_in \opcode_in - connect \dec31_dec_sub16_opcode_in \opcode_in - connect \dec31_dec_sub23_opcode_in \opcode_in - connect \dec31_dec_sub21_opcode_in \opcode_in - connect \dec31_dec_sub20_opcode_in \opcode_in - connect \dec31_dec_sub15_opcode_in \opcode_in - connect \dec31_dec_sub27_opcode_in \opcode_in - connect \dec31_dec_sub11_opcode_in \opcode_in - connect \dec31_dec_sub9_opcode_in \opcode_in - connect \dec31_dec_sub22_opcode_in \opcode_in - connect \dec31_dec_sub19_opcode_in \opcode_in - connect \dec31_dec_sub26_opcode_in \opcode_in - connect \dec31_dec_sub0_opcode_in \opcode_in - connect \dec31_dec_sub28_opcode_in \opcode_in - connect \dec31_dec_sub10_opcode_in \opcode_in - connect \opc_in \opcode_switch [4:0] - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "libresoc.v:18259.1-18974.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0" -attribute \generator "nMigen" -module \dec31_dec_sub0 - attribute \src "libresoc.v:18612.3-18630.6" - wire width 8 $0\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:18688.3-18706.6" - wire $0\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:18935.3-18953.6" - wire width 3 $0\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:18954.3-18972.6" - wire width 3 $0\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:18593.3-18611.6" - wire width 2 $0\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:18669.3-18687.6" - wire $0\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:18840.3-18858.6" - wire width 5 $0\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:18517.3-18535.6" - wire width 12 $0\dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:18859.3-18877.6" - wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:18878.3-18896.6" - wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:18897.3-18915.6" - wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:18726.3-18744.6" - wire width 7 $0\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:18631.3-18649.6" - wire $0\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:18650.3-18668.6" - wire $0\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:18764.3-18782.6" - wire $0\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:18536.3-18554.6" - wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:18802.3-18820.6" - wire $0\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:18916.3-18934.6" - wire width 2 $0\dec31_dec_sub0_out_sel[1:0] - attribute \src "libresoc.v:18574.3-18592.6" - wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:18745.3-18763.6" - wire $0\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:18821.3-18839.6" - wire $0\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:18783.3-18801.6" - wire $0\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:18707.3-18725.6" - wire $0\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:18555.3-18573.6" - wire width 2 $0\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:18260.7-18260.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:18612.3-18630.6" - wire width 8 $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:18688.3-18706.6" - wire $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:18935.3-18953.6" - wire width 3 $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:18954.3-18972.6" - wire width 3 $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:18593.3-18611.6" - wire width 2 $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:18669.3-18687.6" - wire $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:18840.3-18858.6" - wire width 5 $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:18517.3-18535.6" - wire width 12 $1\dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:18859.3-18877.6" - wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:18878.3-18896.6" - wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:18897.3-18915.6" - wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:18726.3-18744.6" - wire width 7 $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:18631.3-18649.6" - wire $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:18650.3-18668.6" - wire $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:18764.3-18782.6" - wire $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:18536.3-18554.6" - wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:18802.3-18820.6" - wire $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:18916.3-18934.6" - wire width 2 $1\dec31_dec_sub0_out_sel[1:0] - attribute \src "libresoc.v:18574.3-18592.6" - wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:18745.3-18763.6" - wire $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:18821.3-18839.6" - wire $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:18783.3-18801.6" - wire $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:18707.3-18725.6" - wire $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:18555.3-18573.6" - wire width 2 $1\dec31_dec_sub0_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub0_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub0_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub0_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub0_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub0_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub0_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub0_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub0_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub0_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub0_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub0_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub0_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub0_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub0_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub0_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub0_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub0_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub0_upd - attribute \src "libresoc.v:18260.7-18260.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "libresoc.v:18260.7-18260.20" - process $proc$libresoc.v:18260$431 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:18517.3-18535.6" - process $proc$libresoc.v:18517$407 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_function_unit[11:0] $1\dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:18518.5-18518.29" - switch \initial - attribute \src "libresoc.v:18518.9-18518.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_function_unit[11:0] 12'000001000000 - case - assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[11:0] - end - attribute \src "libresoc.v:18536.3-18554.6" - process $proc$libresoc.v:18536$408 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:18537.5-18537.29" - switch \initial - attribute \src "libresoc.v:18537.9-18537.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] - end - attribute \src "libresoc.v:18555.3-18573.6" - process $proc$libresoc.v:18555$409 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:18556.5-18556.29" - switch \initial - attribute \src "libresoc.v:18556.9-18556.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub0_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] - end - attribute \src "libresoc.v:18574.3-18592.6" - process $proc$libresoc.v:18574$410 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:18575.5-18575.29" - switch \initial - attribute \src "libresoc.v:18575.9-18575.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] - end - attribute \src "libresoc.v:18593.3-18611.6" - process $proc$libresoc.v:18593$411 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:18594.5-18594.29" - switch \initial - attribute \src "libresoc.v:18594.9-18594.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] - end - attribute \src "libresoc.v:18612.3-18630.6" - process $proc$libresoc.v:18612$412 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:18613.5-18613.29" - switch \initial - attribute \src "libresoc.v:18613.9-18613.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_asmcode[7:0] 8'10011011 - case - assign $1\dec31_dec_sub0_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] - end - attribute \src "libresoc.v:18631.3-18649.6" - process $proc$libresoc.v:18631$413 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:18632.5-18632.29" - switch \initial - attribute \src "libresoc.v:18632.9-18632.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] - end - attribute \src "libresoc.v:18650.3-18668.6" - process $proc$libresoc.v:18650$414 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:18651.5-18651.29" - switch \initial - attribute \src "libresoc.v:18651.9-18651.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] - end - attribute \src "libresoc.v:18669.3-18687.6" - process $proc$libresoc.v:18669$415 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:18670.5-18670.29" - switch \initial - attribute \src "libresoc.v:18670.9-18670.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] - end - attribute \src "libresoc.v:18688.3-18706.6" - process $proc$libresoc.v:18688$416 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:18689.5-18689.29" - switch \initial - attribute \src "libresoc.v:18689.9-18689.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_br[0:0] 1'0 - case - assign $1\dec31_dec_sub0_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] - end - attribute \src "libresoc.v:18707.3-18725.6" - process $proc$libresoc.v:18707$417 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:18708.5-18708.29" - switch \initial - attribute \src "libresoc.v:18708.9-18708.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] - end - attribute \src "libresoc.v:18726.3-18744.6" - process $proc$libresoc.v:18726$418 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:18727.5-18727.29" - switch \initial - attribute \src "libresoc.v:18727.9-18727.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0111011 - case - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] - end - attribute \src "libresoc.v:18745.3-18763.6" - process $proc$libresoc.v:18745$419 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:18746.5-18746.29" - switch \initial - attribute \src "libresoc.v:18746.9-18746.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] - end - attribute \src "libresoc.v:18764.3-18782.6" - process $proc$libresoc.v:18764$420 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:18765.5-18765.29" - switch \initial - attribute \src "libresoc.v:18765.9-18765.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] - end - attribute \src "libresoc.v:18783.3-18801.6" - process $proc$libresoc.v:18783$421 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:18784.5-18784.29" - switch \initial - attribute \src "libresoc.v:18784.9-18784.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub0_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] - end - attribute \src "libresoc.v:18802.3-18820.6" - process $proc$libresoc.v:18802$422 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:18803.5-18803.29" - switch \initial - attribute \src "libresoc.v:18803.9-18803.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub0_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] - end - attribute \src "libresoc.v:18821.3-18839.6" - process $proc$libresoc.v:18821$423 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:18822.5-18822.29" - switch \initial - attribute \src "libresoc.v:18822.9-18822.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] - end - attribute \src "libresoc.v:18840.3-18858.6" - process $proc$libresoc.v:18840$424 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:18841.5-18841.29" - switch \initial - attribute \src "libresoc.v:18841.9-18841.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'11000 - case - assign $1\dec31_dec_sub0_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] - end - attribute \src "libresoc.v:18859.3-18877.6" - process $proc$libresoc.v:18859$425 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:18860.5-18860.29" - switch \initial - attribute \src "libresoc.v:18860.9-18860.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] - end - attribute \src "libresoc.v:18878.3-18896.6" - process $proc$libresoc.v:18878$426 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:18879.5-18879.29" - switch \initial - attribute \src "libresoc.v:18879.9-18879.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 - case - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] - end - attribute \src "libresoc.v:18897.3-18915.6" - process $proc$libresoc.v:18897$427 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:18898.5-18898.29" - switch \initial - attribute \src "libresoc.v:18898.9-18898.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] - end - attribute \src "libresoc.v:18916.3-18934.6" - process $proc$libresoc.v:18916$428 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_out_sel[1:0] $1\dec31_dec_sub0_out_sel[1:0] - attribute \src "libresoc.v:18917.5-18917.29" - switch \initial - attribute \src "libresoc.v:18917.9-18917.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub0_out_sel $0\dec31_dec_sub0_out_sel[1:0] - end - attribute \src "libresoc.v:18935.3-18953.6" - process $proc$libresoc.v:18935$429 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:18936.5-18936.29" - switch \initial - attribute \src "libresoc.v:18936.9-18936.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_cr_in[2:0] 3'011 - case - assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] - end - attribute \src "libresoc.v:18954.3-18972.6" - process $proc$libresoc.v:18954$430 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:18955.5-18955.29" - switch \initial - attribute \src "libresoc.v:18955.9-18955.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:18978.1-20125.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10" -attribute \generator "nMigen" -module \dec31_dec_sub10 - attribute \src "libresoc.v:19421.3-19457.6" - wire width 8 $0\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:19569.3-19605.6" - wire $0\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:20050.3-20086.6" - wire width 3 $0\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:20087.3-20123.6" - wire width 3 $0\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:19384.3-19420.6" - wire width 2 $0\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:19532.3-19568.6" - wire $0\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:19865.3-19901.6" - wire width 5 $0\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:19236.3-19272.6" - wire width 12 $0\dec31_dec_sub10_function_unit[11:0] - attribute \src "libresoc.v:19902.3-19938.6" - wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:19939.3-19975.6" - wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:19976.3-20012.6" - wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:19643.3-19679.6" - wire width 7 $0\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:19458.3-19494.6" - wire $0\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:19495.3-19531.6" - wire $0\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:19717.3-19753.6" - wire $0\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:19273.3-19309.6" - wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:19791.3-19827.6" - wire $0\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:20013.3-20049.6" - wire width 2 $0\dec31_dec_sub10_out_sel[1:0] - attribute \src "libresoc.v:19347.3-19383.6" - wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:19680.3-19716.6" - wire $0\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:19828.3-19864.6" - wire $0\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:19754.3-19790.6" - wire $0\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:19606.3-19642.6" - wire $0\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:19310.3-19346.6" - wire width 2 $0\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:18979.7-18979.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:19421.3-19457.6" - wire width 8 $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:19569.3-19605.6" - wire $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:20050.3-20086.6" - wire width 3 $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:20087.3-20123.6" - wire width 3 $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:19384.3-19420.6" - wire width 2 $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:19532.3-19568.6" - wire $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:19865.3-19901.6" - wire width 5 $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:19236.3-19272.6" - wire width 12 $1\dec31_dec_sub10_function_unit[11:0] - attribute \src "libresoc.v:19902.3-19938.6" - wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:19939.3-19975.6" - wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:19976.3-20012.6" - wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:19643.3-19679.6" - wire width 7 $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:19458.3-19494.6" - wire $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:19495.3-19531.6" - wire $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:19717.3-19753.6" - wire $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:19273.3-19309.6" - wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:19791.3-19827.6" - wire $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:20013.3-20049.6" - wire width 2 $1\dec31_dec_sub10_out_sel[1:0] - attribute \src "libresoc.v:19347.3-19383.6" - wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:19680.3-19716.6" - wire $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:19828.3-19864.6" - wire $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:19754.3-19790.6" - wire $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:19606.3-19642.6" - wire $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:19310.3-19346.6" - wire width 2 $1\dec31_dec_sub10_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub10_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub10_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub10_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub10_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub10_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub10_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub10_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub10_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub10_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub10_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub10_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub10_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub10_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub10_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub10_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub10_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub10_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub10_upd - attribute \src "libresoc.v:18979.7-18979.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "libresoc.v:18979.7-18979.20" - process $proc$libresoc.v:18979$456 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:19236.3-19272.6" - process $proc$libresoc.v:19236$432 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_function_unit[11:0] $1\dec31_dec_sub10_function_unit[11:0] - attribute \src "libresoc.v:19237.5-19237.29" - switch \initial - attribute \src "libresoc.v:19237.9-19237.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - case - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[11:0] - end - attribute \src "libresoc.v:19273.3-19309.6" - process $proc$libresoc.v:19273$433 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:19274.5-19274.29" - switch \initial - attribute \src "libresoc.v:19274.9-19274.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] - end - attribute \src "libresoc.v:19310.3-19346.6" - process $proc$libresoc.v:19310$434 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:19311.5-19311.29" - switch \initial - attribute \src "libresoc.v:19311.9-19311.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] - end - attribute \src "libresoc.v:19347.3-19383.6" - process $proc$libresoc.v:19347$435 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:19348.5-19348.29" - switch \initial - attribute \src "libresoc.v:19348.9-19348.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] - end - attribute \src "libresoc.v:19384.3-19420.6" - process $proc$libresoc.v:19384$436 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:19385.5-19385.29" - switch \initial - attribute \src "libresoc.v:19385.9-19385.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - case - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] - end - attribute \src "libresoc.v:19421.3-19457.6" - process $proc$libresoc.v:19421$437 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:19422.5-19422.29" - switch \initial - attribute \src "libresoc.v:19422.9-19422.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001110 - case - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] - end - attribute \src "libresoc.v:19458.3-19494.6" - process $proc$libresoc.v:19458$438 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:19459.5-19459.29" - switch \initial - attribute \src "libresoc.v:19459.9-19459.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] - end - attribute \src "libresoc.v:19495.3-19531.6" - process $proc$libresoc.v:19495$439 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:19496.5-19496.29" - switch \initial - attribute \src "libresoc.v:19496.9-19496.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] - end - attribute \src "libresoc.v:19532.3-19568.6" - process $proc$libresoc.v:19532$440 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:19533.5-19533.29" - switch \initial - attribute \src "libresoc.v:19533.9-19533.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - case - assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] - end - attribute \src "libresoc.v:19569.3-19605.6" - process $proc$libresoc.v:19569$441 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:19570.5-19570.29" - switch \initial - attribute \src "libresoc.v:19570.9-19570.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - case - assign $1\dec31_dec_sub10_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] - end - attribute \src "libresoc.v:19606.3-19642.6" - process $proc$libresoc.v:19606$442 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:19607.5-19607.29" - switch \initial - attribute \src "libresoc.v:19607.9-19607.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] - end - attribute \src "libresoc.v:19643.3-19679.6" - process $proc$libresoc.v:19643$443 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:19644.5-19644.29" - switch \initial - attribute \src "libresoc.v:19644.9-19644.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - case - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] - end - attribute \src "libresoc.v:19680.3-19716.6" - process $proc$libresoc.v:19680$444 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:19681.5-19681.29" - switch \initial - attribute \src "libresoc.v:19681.9-19681.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] - end - attribute \src "libresoc.v:19717.3-19753.6" - process $proc$libresoc.v:19717$445 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:19718.5-19718.29" - switch \initial - attribute \src "libresoc.v:19718.9-19718.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] - end - attribute \src "libresoc.v:19754.3-19790.6" - process $proc$libresoc.v:19754$446 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:19755.5-19755.29" - switch \initial - attribute \src "libresoc.v:19755.9-19755.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] - end - attribute \src "libresoc.v:19791.3-19827.6" - process $proc$libresoc.v:19791$447 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:19792.5-19792.29" - switch \initial - attribute \src "libresoc.v:19792.9-19792.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] - end - attribute \src "libresoc.v:19828.3-19864.6" - process $proc$libresoc.v:19828$448 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:19829.5-19829.29" - switch \initial - attribute \src "libresoc.v:19829.9-19829.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] - end - attribute \src "libresoc.v:19865.3-19901.6" - process $proc$libresoc.v:19865$449 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:19866.5-19866.29" - switch \initial - attribute \src "libresoc.v:19866.9-19866.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - case - assign $1\dec31_dec_sub10_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] - end - attribute \src "libresoc.v:19902.3-19938.6" - process $proc$libresoc.v:19902$450 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:19903.5-19903.29" - switch \initial - attribute \src "libresoc.v:19903.9-19903.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - case - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] - end - attribute \src "libresoc.v:19939.3-19975.6" - process $proc$libresoc.v:19939$451 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:19940.5-19940.29" - switch \initial - attribute \src "libresoc.v:19940.9-19940.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 - case - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] - end - attribute \src "libresoc.v:19976.3-20012.6" - process $proc$libresoc.v:19976$452 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:19977.5-19977.29" - switch \initial - attribute \src "libresoc.v:19977.9-19977.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] - end - attribute \src "libresoc.v:20013.3-20049.6" - process $proc$libresoc.v:20013$453 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_out_sel[1:0] $1\dec31_dec_sub10_out_sel[1:0] - attribute \src "libresoc.v:20014.5-20014.29" - switch \initial - attribute \src "libresoc.v:20014.9-20014.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub10_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub10_out_sel $0\dec31_dec_sub10_out_sel[1:0] - end - attribute \src "libresoc.v:20050.3-20086.6" - process $proc$libresoc.v:20050$454 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:20051.5-20051.29" - switch \initial - attribute \src "libresoc.v:20051.9-20051.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] - end - attribute \src "libresoc.v:20087.3-20123.6" - process $proc$libresoc.v:20087$455 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:20088.5-20088.29" - switch \initial - attribute \src "libresoc.v:20088.9-20088.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub10_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:20129.1-21708.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11" -attribute \generator "nMigen" -module \dec31_dec_sub11 - attribute \src "libresoc.v:20662.3-20716.6" - wire width 8 $0\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:20882.3-20936.6" - wire $0\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:21597.3-21651.6" - wire width 3 $0\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:21652.3-21706.6" - wire width 3 $0\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:20607.3-20661.6" - wire width 2 $0\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:20827.3-20881.6" - wire $0\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:21322.3-21376.6" - wire width 5 $0\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:20387.3-20441.6" - wire width 12 $0\dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:21377.3-21431.6" - wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:21432.3-21486.6" - wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:21487.3-21541.6" - wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:20992.3-21046.6" - wire width 7 $0\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:20717.3-20771.6" - wire $0\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:20772.3-20826.6" - wire $0\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:21102.3-21156.6" - wire $0\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:20442.3-20496.6" - wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:21212.3-21266.6" - wire $0\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:21542.3-21596.6" - wire width 2 $0\dec31_dec_sub11_out_sel[1:0] - attribute \src "libresoc.v:20552.3-20606.6" - wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:21047.3-21101.6" - wire $0\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:21267.3-21321.6" - wire $0\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:21157.3-21211.6" - wire $0\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:20937.3-20991.6" - wire $0\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:20497.3-20551.6" - wire width 2 $0\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:20130.7-20130.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:20662.3-20716.6" - wire width 8 $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:20882.3-20936.6" - wire $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:21597.3-21651.6" - wire width 3 $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:21652.3-21706.6" - wire width 3 $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:20607.3-20661.6" - wire width 2 $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:20827.3-20881.6" - wire $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:21322.3-21376.6" - wire width 5 $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:20387.3-20441.6" - wire width 12 $1\dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:21377.3-21431.6" - wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:21432.3-21486.6" - wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:21487.3-21541.6" - wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:20992.3-21046.6" - wire width 7 $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:20717.3-20771.6" - wire $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:20772.3-20826.6" - wire $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:21102.3-21156.6" - wire $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:20442.3-20496.6" - wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:21212.3-21266.6" - wire $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:21542.3-21596.6" - wire width 2 $1\dec31_dec_sub11_out_sel[1:0] - attribute \src "libresoc.v:20552.3-20606.6" - wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:21047.3-21101.6" - wire $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:21267.3-21321.6" - wire $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:21157.3-21211.6" - wire $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:20937.3-20991.6" - wire $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:20497.3-20551.6" - wire width 2 $1\dec31_dec_sub11_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub11_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub11_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub11_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub11_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub11_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub11_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub11_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub11_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub11_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub11_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub11_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub11_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub11_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub11_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub11_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub11_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub11_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub11_upd - attribute \src "libresoc.v:20130.7-20130.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "libresoc.v:20130.7-20130.20" - process $proc$libresoc.v:20130$481 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:20387.3-20441.6" - process $proc$libresoc.v:20387$457 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_function_unit[11:0] $1\dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:20388.5-20388.29" - switch \initial - attribute \src "libresoc.v:20388.9-20388.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 - case - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[11:0] - end - attribute \src "libresoc.v:20442.3-20496.6" - process $proc$libresoc.v:20442$458 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:20443.5-20443.29" - switch \initial - attribute \src "libresoc.v:20443.9-20443.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] - end - attribute \src "libresoc.v:20497.3-20551.6" - process $proc$libresoc.v:20497$459 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:20498.5-20498.29" - switch \initial - attribute \src "libresoc.v:20498.9-20498.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] - end - attribute \src "libresoc.v:20552.3-20606.6" - process $proc$libresoc.v:20552$460 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:20553.5-20553.29" - switch \initial - attribute \src "libresoc.v:20553.9-20553.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] - end - attribute \src "libresoc.v:20607.3-20661.6" - process $proc$libresoc.v:20607$461 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:20608.5-20608.29" - switch \initial - attribute \src "libresoc.v:20608.9-20608.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] - end - attribute \src "libresoc.v:20662.3-20716.6" - process $proc$libresoc.v:20662$462 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:20663.5-20663.29" - switch \initial - attribute \src "libresoc.v:20663.9-20663.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000010 - case - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] - end - attribute \src "libresoc.v:20717.3-20771.6" - process $proc$libresoc.v:20717$463 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:20718.5-20718.29" - switch \initial - attribute \src "libresoc.v:20718.9-20718.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] - end - attribute \src "libresoc.v:20772.3-20826.6" - process $proc$libresoc.v:20772$464 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:20773.5-20773.29" - switch \initial - attribute \src "libresoc.v:20773.9-20773.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] - end - attribute \src "libresoc.v:20827.3-20881.6" - process $proc$libresoc.v:20827$465 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:20828.5-20828.29" - switch \initial - attribute \src "libresoc.v:20828.9-20828.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] - end - attribute \src "libresoc.v:20882.3-20936.6" - process $proc$libresoc.v:20882$466 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:20883.5-20883.29" - switch \initial - attribute \src "libresoc.v:20883.9-20883.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - case - assign $1\dec31_dec_sub11_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] - end - attribute \src "libresoc.v:20937.3-20991.6" - process $proc$libresoc.v:20937$467 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:20938.5-20938.29" - switch \initial - attribute \src "libresoc.v:20938.9-20938.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] - end - attribute \src "libresoc.v:20992.3-21046.6" - process $proc$libresoc.v:20992$468 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:20993.5-20993.29" - switch \initial - attribute \src "libresoc.v:20993.9-20993.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 - case - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] - end - attribute \src "libresoc.v:21047.3-21101.6" - process $proc$libresoc.v:21047$469 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:21048.5-21048.29" - switch \initial - attribute \src "libresoc.v:21048.9-21048.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] - end - attribute \src "libresoc.v:21102.3-21156.6" - process $proc$libresoc.v:21102$470 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:21103.5-21103.29" - switch \initial - attribute \src "libresoc.v:21103.9-21103.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - case - assign $1\dec31_dec_sub11_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] - end - attribute \src "libresoc.v:21157.3-21211.6" - process $proc$libresoc.v:21157$471 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:21158.5-21158.29" - switch \initial - attribute \src "libresoc.v:21158.9-21158.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - case - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] - end - attribute \src "libresoc.v:21212.3-21266.6" - process $proc$libresoc.v:21212$472 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:21213.5-21213.29" - switch \initial - attribute \src "libresoc.v:21213.9-21213.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] - end - attribute \src "libresoc.v:21267.3-21321.6" - process $proc$libresoc.v:21267$473 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:21268.5-21268.29" - switch \initial - attribute \src "libresoc.v:21268.9-21268.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] - end - attribute \src "libresoc.v:21322.3-21376.6" - process $proc$libresoc.v:21322$474 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:21323.5-21323.29" - switch \initial - attribute \src "libresoc.v:21323.9-21323.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - case - assign $1\dec31_dec_sub11_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] - end - attribute \src "libresoc.v:21377.3-21431.6" - process $proc$libresoc.v:21377$475 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:21378.5-21378.29" - switch \initial - attribute \src "libresoc.v:21378.9-21378.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - case - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] - end - attribute \src "libresoc.v:21432.3-21486.6" - process $proc$libresoc.v:21432$476 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:21433.5-21433.29" - switch \initial - attribute \src "libresoc.v:21433.9-21433.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] - end - attribute \src "libresoc.v:21487.3-21541.6" - process $proc$libresoc.v:21487$477 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:21488.5-21488.29" - switch \initial - attribute \src "libresoc.v:21488.9-21488.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] - end - attribute \src "libresoc.v:21542.3-21596.6" - process $proc$libresoc.v:21542$478 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_out_sel[1:0] $1\dec31_dec_sub11_out_sel[1:0] - attribute \src "libresoc.v:21543.5-21543.29" - switch \initial - attribute \src "libresoc.v:21543.9-21543.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub11_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub11_out_sel $0\dec31_dec_sub11_out_sel[1:0] - end - attribute \src "libresoc.v:21597.3-21651.6" - process $proc$libresoc.v:21597$479 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:21598.5-21598.29" - switch \initial - attribute \src "libresoc.v:21598.9-21598.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] - end - attribute \src "libresoc.v:21652.3-21706.6" - process $proc$libresoc.v:21652$480 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:21653.5-21653.29" - switch \initial - attribute \src "libresoc.v:21653.9-21653.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:21712.1-24443.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15" -attribute \generator "nMigen" -module \dec31_dec_sub15 - attribute \src "libresoc.v:22485.3-22587.6" - wire width 8 $0\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:22897.3-22999.6" - wire $0\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:24236.3-24338.6" - wire width 3 $0\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:24339.3-24441.6" - wire width 3 $0\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:22382.3-22484.6" - wire width 2 $0\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:22794.3-22896.6" - wire $0\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:23721.3-23823.6" - wire width 5 $0\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:21970.3-22072.6" - wire width 12 $0\dec31_dec_sub15_function_unit[11:0] - attribute \src "libresoc.v:23824.3-23926.6" - wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:23927.3-24029.6" - wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:24030.3-24132.6" - wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:23103.3-23205.6" - wire width 7 $0\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:22588.3-22690.6" - wire $0\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:22691.3-22793.6" - wire $0\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:23309.3-23411.6" - wire $0\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:22073.3-22175.6" - wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:23515.3-23617.6" - wire $0\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:24133.3-24235.6" - wire width 2 $0\dec31_dec_sub15_out_sel[1:0] - attribute \src "libresoc.v:22279.3-22381.6" - wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:23206.3-23308.6" - wire $0\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:23618.3-23720.6" - wire $0\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:23412.3-23514.6" - wire $0\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:23000.3-23102.6" - wire $0\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:22176.3-22278.6" - wire width 2 $0\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:21713.7-21713.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:22485.3-22587.6" - wire width 8 $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:22897.3-22999.6" - wire $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:24236.3-24338.6" - wire width 3 $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:24339.3-24441.6" - wire width 3 $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:22382.3-22484.6" - wire width 2 $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:22794.3-22896.6" - wire $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:23721.3-23823.6" - wire width 5 $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:21970.3-22072.6" - wire width 12 $1\dec31_dec_sub15_function_unit[11:0] - attribute \src "libresoc.v:23824.3-23926.6" - wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:23927.3-24029.6" - wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:24030.3-24132.6" - wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:23103.3-23205.6" - wire width 7 $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:22588.3-22690.6" - wire $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:22691.3-22793.6" - wire $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:23309.3-23411.6" - wire $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:22073.3-22175.6" - wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:23515.3-23617.6" - wire $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:24133.3-24235.6" - wire width 2 $1\dec31_dec_sub15_out_sel[1:0] - attribute \src "libresoc.v:22279.3-22381.6" - wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:23206.3-23308.6" - wire $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:23618.3-23720.6" - wire $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:23412.3-23514.6" - wire $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:23000.3-23102.6" - wire $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:22176.3-22278.6" - wire width 2 $1\dec31_dec_sub15_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub15_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub15_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub15_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub15_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub15_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub15_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub15_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub15_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub15_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub15_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub15_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub15_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub15_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub15_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub15_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub15_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub15_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub15_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub15_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub15_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub15_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub15_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub15_upd - attribute \src "libresoc.v:21713.7-21713.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "libresoc.v:21713.7-21713.20" - process $proc$libresoc.v:21713$506 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:21970.3-22072.6" - process $proc$libresoc.v:21970$482 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_function_unit[11:0] $1\dec31_dec_sub15_function_unit[11:0] - attribute \src "libresoc.v:21971.5-21971.29" - switch \initial - attribute \src "libresoc.v:21971.9-21971.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - case - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[11:0] - end - attribute \src "libresoc.v:22073.3-22175.6" - process $proc$libresoc.v:22073$483 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:22074.5-22074.29" - switch \initial - attribute \src "libresoc.v:22074.9-22074.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] - end - attribute \src "libresoc.v:22176.3-22278.6" - process $proc$libresoc.v:22176$484 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:22177.5-22177.29" - switch \initial - attribute \src "libresoc.v:22177.9-22177.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] - end - attribute \src "libresoc.v:22279.3-22381.6" - process $proc$libresoc.v:22279$485 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:22280.5-22280.29" - switch \initial - attribute \src "libresoc.v:22280.9-22280.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] - end - attribute \src "libresoc.v:22382.3-22484.6" - process $proc$libresoc.v:22382$486 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:22383.5-22383.29" - switch \initial - attribute \src "libresoc.v:22383.9-22383.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] - end - attribute \src "libresoc.v:22485.3-22587.6" - process $proc$libresoc.v:22485$487 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:22486.5-22486.29" - switch \initial - attribute \src "libresoc.v:22486.9-22486.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - case - assign $1\dec31_dec_sub15_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] - end - attribute \src "libresoc.v:22588.3-22690.6" - process $proc$libresoc.v:22588$488 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:22589.5-22589.29" - switch \initial - attribute \src "libresoc.v:22589.9-22589.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] - end - attribute \src "libresoc.v:22691.3-22793.6" - process $proc$libresoc.v:22691$489 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:22692.5-22692.29" - switch \initial - attribute \src "libresoc.v:22692.9-22692.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] - end - attribute \src "libresoc.v:22794.3-22896.6" - process $proc$libresoc.v:22794$490 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:22795.5-22795.29" - switch \initial - attribute \src "libresoc.v:22795.9-22795.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] - end - attribute \src "libresoc.v:22897.3-22999.6" - process $proc$libresoc.v:22897$491 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:22898.5-22898.29" - switch \initial - attribute \src "libresoc.v:22898.9-22898.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - case - assign $1\dec31_dec_sub15_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] - end - attribute \src "libresoc.v:23000.3-23102.6" - process $proc$libresoc.v:23000$492 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:23001.5-23001.29" - switch \initial - attribute \src "libresoc.v:23001.9-23001.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] - end - attribute \src "libresoc.v:23103.3-23205.6" - process $proc$libresoc.v:23103$493 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:23104.5-23104.29" - switch \initial - attribute \src "libresoc.v:23104.9-23104.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - case - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] - end - attribute \src "libresoc.v:23206.3-23308.6" - process $proc$libresoc.v:23206$494 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:23207.5-23207.29" - switch \initial - attribute \src "libresoc.v:23207.9-23207.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] - end - attribute \src "libresoc.v:23309.3-23411.6" - process $proc$libresoc.v:23309$495 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:23310.5-23310.29" - switch \initial - attribute \src "libresoc.v:23310.9-23310.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] - end - attribute \src "libresoc.v:23412.3-23514.6" - process $proc$libresoc.v:23412$496 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:23413.5-23413.29" - switch \initial - attribute \src "libresoc.v:23413.9-23413.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] - end - attribute \src "libresoc.v:23515.3-23617.6" - process $proc$libresoc.v:23515$497 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:23516.5-23516.29" - switch \initial - attribute \src "libresoc.v:23516.9-23516.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] - end - attribute \src "libresoc.v:23618.3-23720.6" - process $proc$libresoc.v:23618$498 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:23619.5-23619.29" - switch \initial - attribute \src "libresoc.v:23619.9-23619.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] - end - attribute \src "libresoc.v:23721.3-23823.6" - process $proc$libresoc.v:23721$499 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:23722.5-23722.29" - switch \initial - attribute \src "libresoc.v:23722.9-23722.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - case - assign $1\dec31_dec_sub15_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] - end - attribute \src "libresoc.v:23824.3-23926.6" - process $proc$libresoc.v:23824$500 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:23825.5-23825.29" - switch \initial - attribute \src "libresoc.v:23825.9-23825.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - case - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] - end - attribute \src "libresoc.v:23927.3-24029.6" - process $proc$libresoc.v:23927$501 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:23928.5-23928.29" - switch \initial - attribute \src "libresoc.v:23928.9-23928.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] - end - attribute \src "libresoc.v:24030.3-24132.6" - process $proc$libresoc.v:24030$502 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:24031.5-24031.29" - switch \initial - attribute \src "libresoc.v:24031.9-24031.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] - end - attribute \src "libresoc.v:24133.3-24235.6" - process $proc$libresoc.v:24133$503 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_out_sel[1:0] $1\dec31_dec_sub15_out_sel[1:0] - attribute \src "libresoc.v:24134.5-24134.29" - switch \initial - attribute \src "libresoc.v:24134.9-24134.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub15_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub15_out_sel $0\dec31_dec_sub15_out_sel[1:0] - end - attribute \src "libresoc.v:24236.3-24338.6" - process $proc$libresoc.v:24236$504 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:24237.5-24237.29" - switch \initial - attribute \src "libresoc.v:24237.9-24237.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - case - assign $1\dec31_dec_sub15_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] - end - attribute \src "libresoc.v:24339.3-24441.6" - process $proc$libresoc.v:24339$505 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:24340.5-24340.29" - switch \initial - attribute \src "libresoc.v:24340.9-24340.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:24447.1-24946.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16" -attribute \generator "nMigen" -module \dec31_dec_sub16 - attribute \src "libresoc.v:24755.3-24764.6" - wire width 8 $0\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:24795.3-24804.6" - wire $0\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:24925.3-24934.6" - wire width 3 $0\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:24935.3-24944.6" - wire width 3 $0\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:24745.3-24754.6" - wire width 2 $0\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:24785.3-24794.6" - wire $0\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:24875.3-24884.6" - wire width 5 $0\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:24705.3-24714.6" - wire width 12 $0\dec31_dec_sub16_function_unit[11:0] - attribute \src "libresoc.v:24885.3-24894.6" - wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:24895.3-24904.6" - wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:24905.3-24914.6" - wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:24815.3-24824.6" - wire width 7 $0\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:24765.3-24774.6" - wire $0\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:24775.3-24784.6" - wire $0\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:24835.3-24844.6" - wire $0\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:24715.3-24724.6" - wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:24855.3-24864.6" - wire $0\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:24915.3-24924.6" - wire width 2 $0\dec31_dec_sub16_out_sel[1:0] - attribute \src "libresoc.v:24735.3-24744.6" - wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:24825.3-24834.6" - wire $0\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:24865.3-24874.6" - wire $0\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:24845.3-24854.6" - wire $0\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:24805.3-24814.6" - wire $0\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:24725.3-24734.6" - wire width 2 $0\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:24448.7-24448.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:24755.3-24764.6" - wire width 8 $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:24795.3-24804.6" - wire $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:24925.3-24934.6" - wire width 3 $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:24935.3-24944.6" - wire width 3 $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:24745.3-24754.6" - wire width 2 $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:24785.3-24794.6" - wire $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:24875.3-24884.6" - wire width 5 $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:24705.3-24714.6" - wire width 12 $1\dec31_dec_sub16_function_unit[11:0] - attribute \src "libresoc.v:24885.3-24894.6" - wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:24895.3-24904.6" - wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:24905.3-24914.6" - wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:24815.3-24824.6" - wire width 7 $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:24765.3-24774.6" - wire $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:24775.3-24784.6" - wire $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:24835.3-24844.6" - wire $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:24715.3-24724.6" - wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:24855.3-24864.6" - wire $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:24915.3-24924.6" - wire width 2 $1\dec31_dec_sub16_out_sel[1:0] - attribute \src "libresoc.v:24735.3-24744.6" - wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:24825.3-24834.6" - wire $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:24865.3-24874.6" - wire $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:24845.3-24854.6" - wire $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:24805.3-24814.6" - wire $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:24725.3-24734.6" - wire width 2 $1\dec31_dec_sub16_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub16_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub16_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub16_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub16_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub16_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub16_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub16_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub16_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub16_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub16_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub16_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub16_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub16_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub16_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub16_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub16_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub16_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub16_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub16_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub16_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub16_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub16_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub16_upd - attribute \src "libresoc.v:24448.7-24448.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "libresoc.v:24448.7-24448.20" - process $proc$libresoc.v:24448$531 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:24705.3-24714.6" - process $proc$libresoc.v:24705$507 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_function_unit[11:0] $1\dec31_dec_sub16_function_unit[11:0] - attribute \src "libresoc.v:24706.5-24706.29" - switch \initial - attribute \src "libresoc.v:24706.9-24706.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_function_unit[11:0] 12'000001000000 - case - assign $1\dec31_dec_sub16_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[11:0] - end - attribute \src "libresoc.v:24715.3-24724.6" - process $proc$libresoc.v:24715$508 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:24716.5-24716.29" - switch \initial - attribute \src "libresoc.v:24716.9-24716.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] - end - attribute \src "libresoc.v:24725.3-24734.6" - process $proc$libresoc.v:24725$509 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:24726.5-24726.29" - switch \initial - attribute \src "libresoc.v:24726.9-24726.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub16_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] - end - attribute \src "libresoc.v:24735.3-24744.6" - process $proc$libresoc.v:24735$510 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:24736.5-24736.29" - switch \initial - attribute \src "libresoc.v:24736.9-24736.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] - end - attribute \src "libresoc.v:24745.3-24754.6" - process $proc$libresoc.v:24745$511 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:24746.5-24746.29" - switch \initial - attribute \src "libresoc.v:24746.9-24746.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] - end - attribute \src "libresoc.v:24755.3-24764.6" - process $proc$libresoc.v:24755$512 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:24756.5-24756.29" - switch \initial - attribute \src "libresoc.v:24756.9-24756.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_asmcode[7:0] 8'01110110 - case - assign $1\dec31_dec_sub16_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] - end - attribute \src "libresoc.v:24765.3-24774.6" - process $proc$libresoc.v:24765$513 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:24766.5-24766.29" - switch \initial - attribute \src "libresoc.v:24766.9-24766.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] - end - attribute \src "libresoc.v:24775.3-24784.6" - process $proc$libresoc.v:24775$514 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:24776.5-24776.29" - switch \initial - attribute \src "libresoc.v:24776.9-24776.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] - end - attribute \src "libresoc.v:24785.3-24794.6" - process $proc$libresoc.v:24785$515 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:24786.5-24786.29" - switch \initial - attribute \src "libresoc.v:24786.9-24786.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] - end - attribute \src "libresoc.v:24795.3-24804.6" - process $proc$libresoc.v:24795$516 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:24796.5-24796.29" - switch \initial - attribute \src "libresoc.v:24796.9-24796.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_br[0:0] 1'0 - case - assign $1\dec31_dec_sub16_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] - end - attribute \src "libresoc.v:24805.3-24814.6" - process $proc$libresoc.v:24805$517 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:24806.5-24806.29" - switch \initial - attribute \src "libresoc.v:24806.9-24806.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] - end - attribute \src "libresoc.v:24815.3-24824.6" - process $proc$libresoc.v:24815$518 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:24816.5-24816.29" - switch \initial - attribute \src "libresoc.v:24816.9-24816.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_internal_op[6:0] 7'0110000 - case - assign $1\dec31_dec_sub16_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] - end - attribute \src "libresoc.v:24825.3-24834.6" - process $proc$libresoc.v:24825$519 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:24826.5-24826.29" - switch \initial - attribute \src "libresoc.v:24826.9-24826.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] - end - attribute \src "libresoc.v:24835.3-24844.6" - process $proc$libresoc.v:24835$520 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:24836.5-24836.29" - switch \initial - attribute \src "libresoc.v:24836.9-24836.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] - end - attribute \src "libresoc.v:24845.3-24854.6" - process $proc$libresoc.v:24845$521 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:24846.5-24846.29" - switch \initial - attribute \src "libresoc.v:24846.9-24846.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub16_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] - end - attribute \src "libresoc.v:24855.3-24864.6" - process $proc$libresoc.v:24855$522 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:24856.5-24856.29" - switch \initial - attribute \src "libresoc.v:24856.9-24856.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub16_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] - end - attribute \src "libresoc.v:24865.3-24874.6" - process $proc$libresoc.v:24865$523 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:24866.5-24866.29" - switch \initial - attribute \src "libresoc.v:24866.9-24866.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] - end - attribute \src "libresoc.v:24875.3-24884.6" - process $proc$libresoc.v:24875$524 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:24876.5-24876.29" - switch \initial - attribute \src "libresoc.v:24876.9-24876.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_form[4:0] 5'01010 - case - assign $1\dec31_dec_sub16_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] - end - attribute \src "libresoc.v:24885.3-24894.6" - process $proc$libresoc.v:24885$525 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:24886.5-24886.29" - switch \initial - attribute \src "libresoc.v:24886.9-24886.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_in1_sel[2:0] 3'100 - case - assign $1\dec31_dec_sub16_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] - end - attribute \src "libresoc.v:24895.3-24904.6" - process $proc$libresoc.v:24895$526 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:24896.5-24896.29" - switch \initial - attribute \src "libresoc.v:24896.9-24896.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 - case - assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] - end - attribute \src "libresoc.v:24905.3-24914.6" - process $proc$libresoc.v:24905$527 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:24906.5-24906.29" - switch \initial - attribute \src "libresoc.v:24906.9-24906.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] - end - attribute \src "libresoc.v:24915.3-24924.6" - process $proc$libresoc.v:24915$528 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_out_sel[1:0] $1\dec31_dec_sub16_out_sel[1:0] - attribute \src "libresoc.v:24916.5-24916.29" - switch \initial - attribute \src "libresoc.v:24916.9-24916.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub16_out_sel $0\dec31_dec_sub16_out_sel[1:0] - end - attribute \src "libresoc.v:24925.3-24934.6" - process $proc$libresoc.v:24925$529 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:24926.5-24926.29" - switch \initial - attribute \src "libresoc.v:24926.9-24926.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_cr_in[2:0] 3'110 - case - assign $1\dec31_dec_sub16_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] - end - attribute \src "libresoc.v:24935.3-24944.6" - process $proc$libresoc.v:24935$530 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:24936.5-24936.29" - switch \initial - attribute \src "libresoc.v:24936.9-24936.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_cr_out[2:0] 3'100 - case - assign $1\dec31_dec_sub16_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:24950.1-25737.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" -attribute \generator "nMigen" -module \dec31_dec_sub18 - attribute \src "libresoc.v:25318.3-25339.6" - wire width 8 $0\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:25406.3-25427.6" - wire $0\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:25692.3-25713.6" - wire width 3 $0\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:25714.3-25735.6" - wire width 3 $0\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:25296.3-25317.6" - wire width 2 $0\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:25384.3-25405.6" - wire $0\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:25582.3-25603.6" - wire width 5 $0\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:25208.3-25229.6" - wire width 12 $0\dec31_dec_sub18_function_unit[11:0] - attribute \src "libresoc.v:25604.3-25625.6" - wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:25626.3-25647.6" - wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:25648.3-25669.6" - wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:25450.3-25471.6" - wire width 7 $0\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:25340.3-25361.6" - wire $0\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:25362.3-25383.6" - wire $0\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:25494.3-25515.6" - wire $0\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:25230.3-25251.6" - wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:25538.3-25559.6" - wire $0\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:25670.3-25691.6" - wire width 2 $0\dec31_dec_sub18_out_sel[1:0] - attribute \src "libresoc.v:25274.3-25295.6" - wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:25472.3-25493.6" - wire $0\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:25560.3-25581.6" - wire $0\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:25516.3-25537.6" - wire $0\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:25428.3-25449.6" - wire $0\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:25252.3-25273.6" - wire width 2 $0\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:24951.7-24951.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:25318.3-25339.6" - wire width 8 $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:25406.3-25427.6" - wire $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:25692.3-25713.6" - wire width 3 $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:25714.3-25735.6" - wire width 3 $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:25296.3-25317.6" - wire width 2 $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:25384.3-25405.6" - wire $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:25582.3-25603.6" - wire width 5 $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:25208.3-25229.6" - wire width 12 $1\dec31_dec_sub18_function_unit[11:0] - attribute \src "libresoc.v:25604.3-25625.6" - wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:25626.3-25647.6" - wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:25648.3-25669.6" - wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:25450.3-25471.6" - wire width 7 $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:25340.3-25361.6" - wire $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:25362.3-25383.6" - wire $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:25494.3-25515.6" - wire $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:25230.3-25251.6" - wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:25538.3-25559.6" - wire $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:25670.3-25691.6" - wire width 2 $1\dec31_dec_sub18_out_sel[1:0] - attribute \src "libresoc.v:25274.3-25295.6" - wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:25472.3-25493.6" - wire $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:25560.3-25581.6" - wire $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:25516.3-25537.6" - wire $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:25428.3-25449.6" - wire $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:25252.3-25273.6" - wire width 2 $1\dec31_dec_sub18_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub18_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub18_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub18_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub18_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub18_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub18_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub18_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub18_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub18_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub18_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub18_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub18_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub18_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub18_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub18_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub18_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub18_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub18_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub18_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub18_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub18_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub18_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub18_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub18_upd - attribute \src "libresoc.v:24951.7-24951.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "libresoc.v:24951.7-24951.20" - process $proc$libresoc.v:24951$556 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:25208.3-25229.6" - process $proc$libresoc.v:25208$532 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_function_unit[11:0] $1\dec31_dec_sub18_function_unit[11:0] - attribute \src "libresoc.v:25209.5-25209.29" - switch \initial - attribute \src "libresoc.v:25209.9-25209.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 - case - assign $1\dec31_dec_sub18_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[11:0] - end - attribute \src "libresoc.v:25230.3-25251.6" - process $proc$libresoc.v:25230$533 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:25231.5-25231.29" - switch \initial - attribute \src "libresoc.v:25231.9-25231.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] - end - attribute \src "libresoc.v:25252.3-25273.6" - process $proc$libresoc.v:25252$534 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:25253.5-25253.29" - switch \initial - attribute \src "libresoc.v:25253.9-25253.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] - end - attribute \src "libresoc.v:25274.3-25295.6" - process $proc$libresoc.v:25274$535 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:25275.5-25275.29" - switch \initial - attribute \src "libresoc.v:25275.9-25275.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] - end - attribute \src "libresoc.v:25296.3-25317.6" - process $proc$libresoc.v:25296$536 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:25297.5-25297.29" - switch \initial - attribute \src "libresoc.v:25297.9-25297.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] - end - attribute \src "libresoc.v:25318.3-25339.6" - process $proc$libresoc.v:25318$537 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:25319.5-25319.29" - switch \initial - attribute \src "libresoc.v:25319.9-25319.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'01111000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'01110111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'10011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001101 - case - assign $1\dec31_dec_sub18_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] - end - attribute \src "libresoc.v:25340.3-25361.6" - process $proc$libresoc.v:25340$538 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:25341.5-25341.29" - switch \initial - attribute \src "libresoc.v:25341.9-25341.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] - end - attribute \src "libresoc.v:25362.3-25383.6" - process $proc$libresoc.v:25362$539 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:25363.5-25363.29" - switch \initial - attribute \src "libresoc.v:25363.9-25363.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] - end - attribute \src "libresoc.v:25384.3-25405.6" - process $proc$libresoc.v:25384$540 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:25385.5-25385.29" - switch \initial - attribute \src "libresoc.v:25385.9-25385.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] - end - attribute \src "libresoc.v:25406.3-25427.6" - process $proc$libresoc.v:25406$541 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:25407.5-25407.29" - switch \initial - attribute \src "libresoc.v:25407.9-25407.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 - case - assign $1\dec31_dec_sub18_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] - end - attribute \src "libresoc.v:25428.3-25449.6" - process $proc$libresoc.v:25428$542 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:25429.5-25429.29" - switch \initial - attribute \src "libresoc.v:25429.9-25429.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] - end - attribute \src "libresoc.v:25450.3-25471.6" - process $proc$libresoc.v:25450$543 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:25451.5-25451.29" - switch \initial - attribute \src "libresoc.v:25451.9-25451.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 - case - assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] - end - attribute \src "libresoc.v:25472.3-25493.6" - process $proc$libresoc.v:25472$544 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:25473.5-25473.29" - switch \initial - attribute \src "libresoc.v:25473.9-25473.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] - end - attribute \src "libresoc.v:25494.3-25515.6" - process $proc$libresoc.v:25494$545 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:25495.5-25495.29" - switch \initial - attribute \src "libresoc.v:25495.9-25495.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] - end - attribute \src "libresoc.v:25516.3-25537.6" - process $proc$libresoc.v:25516$546 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:25517.5-25517.29" - switch \initial - attribute \src "libresoc.v:25517.9-25517.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] - end - attribute \src "libresoc.v:25538.3-25559.6" - process $proc$libresoc.v:25538$547 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:25539.5-25539.29" - switch \initial - attribute \src "libresoc.v:25539.9-25539.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub18_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] - end - attribute \src "libresoc.v:25560.3-25581.6" - process $proc$libresoc.v:25560$548 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:25561.5-25561.29" - switch \initial - attribute \src "libresoc.v:25561.9-25561.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] - end - attribute \src "libresoc.v:25582.3-25603.6" - process $proc$libresoc.v:25582$549 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:25583.5-25583.29" - switch \initial - attribute \src "libresoc.v:25583.9-25583.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub18_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] - end - attribute \src "libresoc.v:25604.3-25625.6" - process $proc$libresoc.v:25604$550 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:25605.5-25605.29" - switch \initial - attribute \src "libresoc.v:25605.9-25605.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] - end - attribute \src "libresoc.v:25626.3-25647.6" - process $proc$libresoc.v:25626$551 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:25627.5-25627.29" - switch \initial - attribute \src "libresoc.v:25627.9-25627.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] - end - attribute \src "libresoc.v:25648.3-25669.6" - process $proc$libresoc.v:25648$552 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:25649.5-25649.29" - switch \initial - attribute \src "libresoc.v:25649.9-25649.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] - end - attribute \src "libresoc.v:25670.3-25691.6" - process $proc$libresoc.v:25670$553 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_out_sel[1:0] $1\dec31_dec_sub18_out_sel[1:0] - attribute \src "libresoc.v:25671.5-25671.29" - switch \initial - attribute \src "libresoc.v:25671.9-25671.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[1:0] - end - attribute \src "libresoc.v:25692.3-25713.6" - process $proc$libresoc.v:25692$554 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:25693.5-25693.29" - switch \initial - attribute \src "libresoc.v:25693.9-25693.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] - end - attribute \src "libresoc.v:25714.3-25735.6" - process $proc$libresoc.v:25714$555 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:25715.5-25715.29" - switch \initial - attribute \src "libresoc.v:25715.9-25715.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:25741.1-26456.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" -attribute \generator "nMigen" -module \dec31_dec_sub19 - attribute \src "libresoc.v:26094.3-26112.6" - wire width 8 $0\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:26170.3-26188.6" - wire $0\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:26417.3-26435.6" - wire width 3 $0\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:26436.3-26454.6" - wire width 3 $0\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:26075.3-26093.6" - wire width 2 $0\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:26151.3-26169.6" - wire $0\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:26322.3-26340.6" - wire width 5 $0\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:25999.3-26017.6" - wire width 12 $0\dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:26341.3-26359.6" - wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:26360.3-26378.6" - wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:26379.3-26397.6" - wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:26208.3-26226.6" - wire width 7 $0\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:26113.3-26131.6" - wire $0\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:26132.3-26150.6" - wire $0\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:26246.3-26264.6" - wire $0\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:26018.3-26036.6" - wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:26284.3-26302.6" - wire $0\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:26398.3-26416.6" - wire width 2 $0\dec31_dec_sub19_out_sel[1:0] - attribute \src "libresoc.v:26056.3-26074.6" - wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:26227.3-26245.6" - wire $0\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:26303.3-26321.6" - wire $0\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:26265.3-26283.6" - wire $0\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:26189.3-26207.6" - wire $0\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:26037.3-26055.6" - wire width 2 $0\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:25742.7-25742.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:26094.3-26112.6" - wire width 8 $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:26170.3-26188.6" - wire $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:26417.3-26435.6" - wire width 3 $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:26436.3-26454.6" - wire width 3 $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:26075.3-26093.6" - wire width 2 $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:26151.3-26169.6" - wire $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:26322.3-26340.6" - wire width 5 $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:25999.3-26017.6" - wire width 12 $1\dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:26341.3-26359.6" - wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:26360.3-26378.6" - wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:26379.3-26397.6" - wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:26208.3-26226.6" - wire width 7 $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:26113.3-26131.6" - wire $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:26132.3-26150.6" - wire $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:26246.3-26264.6" - wire $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:26018.3-26036.6" - wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:26284.3-26302.6" - wire $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:26398.3-26416.6" - wire width 2 $1\dec31_dec_sub19_out_sel[1:0] - attribute \src "libresoc.v:26056.3-26074.6" - wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:26227.3-26245.6" - wire $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:26303.3-26321.6" - wire $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:26265.3-26283.6" - wire $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:26189.3-26207.6" - wire $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:26037.3-26055.6" - wire width 2 $1\dec31_dec_sub19_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub19_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub19_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub19_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub19_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub19_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub19_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub19_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub19_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub19_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub19_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub19_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub19_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub19_upd - attribute \src "libresoc.v:25742.7-25742.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "libresoc.v:25742.7-25742.20" - process $proc$libresoc.v:25742$581 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:25999.3-26017.6" - process $proc$libresoc.v:25999$557 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_function_unit[11:0] $1\dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:26000.5-26000.29" - switch \initial - attribute \src "libresoc.v:26000.9-26000.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[11:0] 12'000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 - case - assign $1\dec31_dec_sub19_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[11:0] - end - attribute \src "libresoc.v:26018.3-26036.6" - process $proc$libresoc.v:26018$558 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:26019.5-26019.29" - switch \initial - attribute \src "libresoc.v:26019.9-26019.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] - end - attribute \src "libresoc.v:26037.3-26055.6" - process $proc$libresoc.v:26037$559 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:26038.5-26038.29" - switch \initial - attribute \src "libresoc.v:26038.9-26038.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub19_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] - end - attribute \src "libresoc.v:26056.3-26074.6" - process $proc$libresoc.v:26056$560 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:26057.5-26057.29" - switch \initial - attribute \src "libresoc.v:26057.9-26057.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] - end - attribute \src "libresoc.v:26075.3-26093.6" - process $proc$libresoc.v:26075$561 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:26076.5-26076.29" - switch \initial - attribute \src "libresoc.v:26076.9-26076.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] - end - attribute \src "libresoc.v:26094.3-26112.6" - process $proc$libresoc.v:26094$562 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:26095.5-26095.29" - switch \initial - attribute \src "libresoc.v:26095.9-26095.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_asmcode[7:0] 8'01101111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_asmcode[7:0] 8'01111001 - case - assign $1\dec31_dec_sub19_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] - end - attribute \src "libresoc.v:26113.3-26131.6" - process $proc$libresoc.v:26113$563 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:26114.5-26114.29" - switch \initial - attribute \src "libresoc.v:26114.9-26114.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] - end - attribute \src "libresoc.v:26132.3-26150.6" - process $proc$libresoc.v:26132$564 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:26133.5-26133.29" - switch \initial - attribute \src "libresoc.v:26133.9-26133.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] - end - attribute \src "libresoc.v:26151.3-26169.6" - process $proc$libresoc.v:26151$565 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:26152.5-26152.29" - switch \initial - attribute \src "libresoc.v:26152.9-26152.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] - end - attribute \src "libresoc.v:26170.3-26188.6" - process $proc$libresoc.v:26170$566 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:26171.5-26171.29" - switch \initial - attribute \src "libresoc.v:26171.9-26171.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_br[0:0] 1'0 - case - assign $1\dec31_dec_sub19_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] - end - attribute \src "libresoc.v:26189.3-26207.6" - process $proc$libresoc.v:26189$567 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:26190.5-26190.29" - switch \initial - attribute \src "libresoc.v:26190.9-26190.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] - end - attribute \src "libresoc.v:26208.3-26226.6" - process $proc$libresoc.v:26208$568 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:26209.5-26209.29" - switch \initial - attribute \src "libresoc.v:26209.9-26209.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001 - case - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] - end - attribute \src "libresoc.v:26227.3-26245.6" - process $proc$libresoc.v:26227$569 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:26228.5-26228.29" - switch \initial - attribute \src "libresoc.v:26228.9-26228.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] - end - attribute \src "libresoc.v:26246.3-26264.6" - process $proc$libresoc.v:26246$570 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:26247.5-26247.29" - switch \initial - attribute \src "libresoc.v:26247.9-26247.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] - end - attribute \src "libresoc.v:26265.3-26283.6" - process $proc$libresoc.v:26265$571 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:26266.5-26266.29" - switch \initial - attribute \src "libresoc.v:26266.9-26266.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] - end - attribute \src "libresoc.v:26284.3-26302.6" - process $proc$libresoc.v:26284$572 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:26285.5-26285.29" - switch \initial - attribute \src "libresoc.v:26285.9-26285.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] - end - attribute \src "libresoc.v:26303.3-26321.6" - process $proc$libresoc.v:26303$573 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:26304.5-26304.29" - switch \initial - attribute \src "libresoc.v:26304.9-26304.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] - end - attribute \src "libresoc.v:26322.3-26340.6" - process $proc$libresoc.v:26322$574 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:26323.5-26323.29" - switch \initial - attribute \src "libresoc.v:26323.9-26323.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01010 - case - assign $1\dec31_dec_sub19_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] - end - attribute \src "libresoc.v:26341.3-26359.6" - process $proc$libresoc.v:26341$575 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:26342.5-26342.29" - switch \initial - attribute \src "libresoc.v:26342.9-26342.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'100 - case - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] - end - attribute \src "libresoc.v:26360.3-26378.6" - process $proc$libresoc.v:26360$576 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:26361.5-26361.29" - switch \initial - attribute \src "libresoc.v:26361.9-26361.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 - case - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] - end - attribute \src "libresoc.v:26379.3-26397.6" - process $proc$libresoc.v:26379$577 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:26380.5-26380.29" - switch \initial - attribute \src "libresoc.v:26380.9-26380.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] - end - attribute \src "libresoc.v:26398.3-26416.6" - process $proc$libresoc.v:26398$578 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_out_sel[1:0] $1\dec31_dec_sub19_out_sel[1:0] - attribute \src "libresoc.v:26399.5-26399.29" - switch \initial - attribute \src "libresoc.v:26399.9-26399.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'11 - case - assign $1\dec31_dec_sub19_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[1:0] - end - attribute \src "libresoc.v:26417.3-26435.6" - process $proc$libresoc.v:26417$579 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:26418.5-26418.29" - switch \initial - attribute \src "libresoc.v:26418.9-26418.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] - end - attribute \src "libresoc.v:26436.3-26454.6" - process $proc$libresoc.v:26436$580 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:26437.5-26437.29" - switch \initial - attribute \src "libresoc.v:26437.9-26437.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:26460.1-27319.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" -attribute \generator "nMigen" -module \dec31_dec_sub20 - attribute \src "libresoc.v:26843.3-26867.6" - wire width 8 $0\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:26943.3-26967.6" - wire $0\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:27268.3-27292.6" - wire width 3 $0\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:27293.3-27317.6" - wire width 3 $0\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:26818.3-26842.6" - wire width 2 $0\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:26918.3-26942.6" - wire $0\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:27143.3-27167.6" - wire width 5 $0\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:26718.3-26742.6" - wire width 12 $0\dec31_dec_sub20_function_unit[11:0] - attribute \src "libresoc.v:27168.3-27192.6" - wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:27193.3-27217.6" - wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:27218.3-27242.6" - wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:26993.3-27017.6" - wire width 7 $0\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:26868.3-26892.6" - wire $0\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:26893.3-26917.6" - wire $0\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:27043.3-27067.6" - wire $0\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:26743.3-26767.6" - wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:27093.3-27117.6" - wire $0\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:27243.3-27267.6" - wire width 2 $0\dec31_dec_sub20_out_sel[1:0] - attribute \src "libresoc.v:26793.3-26817.6" - wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:27018.3-27042.6" - wire $0\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:27118.3-27142.6" - wire $0\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:27068.3-27092.6" - wire $0\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:26968.3-26992.6" - wire $0\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:26768.3-26792.6" - wire width 2 $0\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:26461.7-26461.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:26843.3-26867.6" - wire width 8 $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:26943.3-26967.6" - wire $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:27268.3-27292.6" - wire width 3 $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:27293.3-27317.6" - wire width 3 $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:26818.3-26842.6" - wire width 2 $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:26918.3-26942.6" - wire $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:27143.3-27167.6" - wire width 5 $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:26718.3-26742.6" - wire width 12 $1\dec31_dec_sub20_function_unit[11:0] - attribute \src "libresoc.v:27168.3-27192.6" - wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:27193.3-27217.6" - wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:27218.3-27242.6" - wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:26993.3-27017.6" - wire width 7 $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:26868.3-26892.6" - wire $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:26893.3-26917.6" - wire $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:27043.3-27067.6" - wire $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:26743.3-26767.6" - wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:27093.3-27117.6" - wire $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:27243.3-27267.6" - wire width 2 $1\dec31_dec_sub20_out_sel[1:0] - attribute \src "libresoc.v:26793.3-26817.6" - wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:27018.3-27042.6" - wire $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:27118.3-27142.6" - wire $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:27068.3-27092.6" - wire $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:26968.3-26992.6" - wire $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:26768.3-26792.6" - wire width 2 $1\dec31_dec_sub20_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub20_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub20_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub20_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub20_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub20_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub20_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub20_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub20_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub20_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub20_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub20_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub20_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub20_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub20_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub20_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub20_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub20_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub20_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub20_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub20_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub20_upd - attribute \src "libresoc.v:26461.7-26461.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "libresoc.v:26461.7-26461.20" - process $proc$libresoc.v:26461$606 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:26718.3-26742.6" - process $proc$libresoc.v:26718$582 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_function_unit[11:0] $1\dec31_dec_sub20_function_unit[11:0] - attribute \src "libresoc.v:26719.5-26719.29" - switch \initial - attribute \src "libresoc.v:26719.9-26719.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - case - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[11:0] - end - attribute \src "libresoc.v:26743.3-26767.6" - process $proc$libresoc.v:26743$583 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:26744.5-26744.29" - switch \initial - attribute \src "libresoc.v:26744.9-26744.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 - case - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] - end - attribute \src "libresoc.v:26768.3-26792.6" - process $proc$libresoc.v:26768$584 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:26769.5-26769.29" - switch \initial - attribute \src "libresoc.v:26769.9-26769.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] - end - attribute \src "libresoc.v:26793.3-26817.6" - process $proc$libresoc.v:26793$585 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:26794.5-26794.29" - switch \initial - attribute \src "libresoc.v:26794.9-26794.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] - end - attribute \src "libresoc.v:26818.3-26842.6" - process $proc$libresoc.v:26818$586 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:26819.5-26819.29" - switch \initial - attribute \src "libresoc.v:26819.9-26819.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] - end - attribute \src "libresoc.v:26843.3-26867.6" - process $proc$libresoc.v:26843$587 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:26844.5-26844.29" - switch \initial - attribute \src "libresoc.v:26844.9-26844.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01001101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01011001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'10101101 - case - assign $1\dec31_dec_sub20_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] - end - attribute \src "libresoc.v:26868.3-26892.6" - process $proc$libresoc.v:26868$588 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:26869.5-26869.29" - switch \initial - attribute \src "libresoc.v:26869.9-26869.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] - end - attribute \src "libresoc.v:26893.3-26917.6" - process $proc$libresoc.v:26893$589 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:26894.5-26894.29" - switch \initial - attribute \src "libresoc.v:26894.9-26894.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] - end - attribute \src "libresoc.v:26918.3-26942.6" - process $proc$libresoc.v:26918$590 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:26919.5-26919.29" - switch \initial - attribute \src "libresoc.v:26919.9-26919.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] - end - attribute \src "libresoc.v:26943.3-26967.6" - process $proc$libresoc.v:26943$591 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:26944.5-26944.29" - switch \initial - attribute \src "libresoc.v:26944.9-26944.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'1 - case - assign $1\dec31_dec_sub20_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] - end - attribute \src "libresoc.v:26968.3-26992.6" - process $proc$libresoc.v:26968$592 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:26969.5-26969.29" - switch \initial - attribute \src "libresoc.v:26969.9-26969.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] - end - attribute \src "libresoc.v:26993.3-27017.6" - process $proc$libresoc.v:26993$593 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:26994.5-26994.29" - switch \initial - attribute \src "libresoc.v:26994.9-26994.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100110 - case - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] - end - attribute \src "libresoc.v:27018.3-27042.6" - process $proc$libresoc.v:27018$594 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:27019.5-27019.29" - switch \initial - attribute \src "libresoc.v:27019.9-27019.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] - end - attribute \src "libresoc.v:27043.3-27067.6" - process $proc$libresoc.v:27043$595 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:27044.5-27044.29" - switch \initial - attribute \src "libresoc.v:27044.9-27044.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] - end - attribute \src "libresoc.v:27068.3-27092.6" - process $proc$libresoc.v:27068$596 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:27069.5-27069.29" - switch \initial - attribute \src "libresoc.v:27069.9-27069.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] - end - attribute \src "libresoc.v:27093.3-27117.6" - process $proc$libresoc.v:27093$597 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:27094.5-27094.29" - switch \initial - attribute \src "libresoc.v:27094.9-27094.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] - end - attribute \src "libresoc.v:27118.3-27142.6" - process $proc$libresoc.v:27118$598 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:27119.5-27119.29" - switch \initial - attribute \src "libresoc.v:27119.9-27119.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] - end - attribute \src "libresoc.v:27143.3-27167.6" - process $proc$libresoc.v:27143$599 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:27144.5-27144.29" - switch \initial - attribute \src "libresoc.v:27144.9-27144.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub20_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] - end - attribute \src "libresoc.v:27168.3-27192.6" - process $proc$libresoc.v:27168$600 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:27169.5-27169.29" - switch \initial - attribute \src "libresoc.v:27169.9-27169.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - case - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] - end - attribute \src "libresoc.v:27193.3-27217.6" - process $proc$libresoc.v:27193$601 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:27194.5-27194.29" - switch \initial - attribute \src "libresoc.v:27194.9-27194.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] - end - attribute \src "libresoc.v:27218.3-27242.6" - process $proc$libresoc.v:27218$602 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:27219.5-27219.29" - switch \initial - attribute \src "libresoc.v:27219.9-27219.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] - end - attribute \src "libresoc.v:27243.3-27267.6" - process $proc$libresoc.v:27243$603 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_out_sel[1:0] $1\dec31_dec_sub20_out_sel[1:0] - attribute \src "libresoc.v:27244.5-27244.29" - switch \initial - attribute \src "libresoc.v:27244.9-27244.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[1:0] - end - attribute \src "libresoc.v:27268.3-27292.6" - process $proc$libresoc.v:27268$604 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:27269.5-27269.29" - switch \initial - attribute \src "libresoc.v:27269.9-27269.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] - end - attribute \src "libresoc.v:27293.3-27317.6" - process $proc$libresoc.v:27293$605 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:27294.5-27294.29" - switch \initial - attribute \src "libresoc.v:27294.9-27294.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:27323.1-28740.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21" -attribute \generator "nMigen" -module \dec31_dec_sub21 - attribute \src "libresoc.v:28365.3-28395.6" - wire width 8 $0\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:27973.3-28021.6" - wire $0\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:28641.3-28689.6" - wire width 3 $0\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:28690.3-28738.6" - wire width 3 $0\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:27777.3-27825.6" - wire width 2 $0\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:27924.3-27972.6" - wire $0\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:28396.3-28444.6" - wire width 5 $0\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:27581.3-27629.6" - wire width 12 $0\dec31_dec_sub21_function_unit[11:0] - attribute \src "libresoc.v:28445.3-28493.6" - wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:28494.3-28542.6" - wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:28543.3-28591.6" - wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:28120.3-28168.6" - wire width 7 $0\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:27826.3-27874.6" - wire $0\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:27875.3-27923.6" - wire $0\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:28169.3-28217.6" - wire $0\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:27630.3-27678.6" - wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:28267.3-28315.6" - wire $0\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:28592.3-28640.6" - wire width 2 $0\dec31_dec_sub21_out_sel[1:0] - attribute \src "libresoc.v:27728.3-27776.6" - wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:28071.3-28119.6" - wire $0\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:28316.3-28364.6" - wire $0\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:28218.3-28266.6" - wire $0\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:28022.3-28070.6" - wire $0\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:27679.3-27727.6" - wire width 2 $0\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:27324.7-27324.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:28365.3-28395.6" - wire width 8 $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:27973.3-28021.6" - wire $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:28641.3-28689.6" - wire width 3 $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:28690.3-28738.6" - wire width 3 $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:27777.3-27825.6" - wire width 2 $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:27924.3-27972.6" - wire $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:28396.3-28444.6" - wire width 5 $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:27581.3-27629.6" - wire width 12 $1\dec31_dec_sub21_function_unit[11:0] - attribute \src "libresoc.v:28445.3-28493.6" - wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:28494.3-28542.6" - wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:28543.3-28591.6" - wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:28120.3-28168.6" - wire width 7 $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:27826.3-27874.6" - wire $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:27875.3-27923.6" - wire $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:28169.3-28217.6" - wire $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:27630.3-27678.6" - wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:28267.3-28315.6" - wire $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:28592.3-28640.6" - wire width 2 $1\dec31_dec_sub21_out_sel[1:0] - attribute \src "libresoc.v:27728.3-27776.6" - wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:28071.3-28119.6" - wire $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:28316.3-28364.6" - wire $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:28218.3-28266.6" - wire $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:28022.3-28070.6" - wire $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:27679.3-27727.6" - wire width 2 $1\dec31_dec_sub21_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub21_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub21_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub21_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub21_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub21_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub21_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub21_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub21_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub21_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub21_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub21_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub21_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub21_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub21_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub21_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub21_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub21_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub21_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub21_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub21_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub21_upd - attribute \src "libresoc.v:27324.7-27324.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "libresoc.v:27324.7-27324.20" - process $proc$libresoc.v:27324$631 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:27581.3-27629.6" - process $proc$libresoc.v:27581$607 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_function_unit[11:0] $1\dec31_dec_sub21_function_unit[11:0] - attribute \src "libresoc.v:27582.5-27582.29" - switch \initial - attribute \src "libresoc.v:27582.9-27582.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - case - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[11:0] - end - attribute \src "libresoc.v:27630.3-27678.6" - process $proc$libresoc.v:27630$608 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:27631.5-27631.29" - switch \initial - attribute \src "libresoc.v:27631.9-27631.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 - case - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] - end - attribute \src "libresoc.v:27679.3-27727.6" - process $proc$libresoc.v:27679$609 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:27680.5-27680.29" - switch \initial - attribute \src "libresoc.v:27680.9-27680.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - case - assign $1\dec31_dec_sub21_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] - end - attribute \src "libresoc.v:27728.3-27776.6" - process $proc$libresoc.v:27728$610 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:27729.5-27729.29" - switch \initial - attribute \src "libresoc.v:27729.9-27729.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] - end - attribute \src "libresoc.v:27777.3-27825.6" - process $proc$libresoc.v:27777$611 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:27778.5-27778.29" - switch \initial - attribute \src "libresoc.v:27778.9-27778.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] - end - attribute \src "libresoc.v:27826.3-27874.6" - process $proc$libresoc.v:27826$612 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:27827.5-27827.29" - switch \initial - attribute \src "libresoc.v:27827.9-27827.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] - end - attribute \src "libresoc.v:27875.3-27923.6" - process $proc$libresoc.v:27875$613 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:27876.5-27876.29" - switch \initial - attribute \src "libresoc.v:27876.9-27876.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] - end - attribute \src "libresoc.v:27924.3-27972.6" - process $proc$libresoc.v:27924$614 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:27925.5-27925.29" - switch \initial - attribute \src "libresoc.v:27925.9-27925.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] - end - attribute \src "libresoc.v:27973.3-28021.6" - process $proc$libresoc.v:27973$615 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:27974.5-27974.29" - switch \initial - attribute \src "libresoc.v:27974.9-27974.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - case - assign $1\dec31_dec_sub21_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] - end - attribute \src "libresoc.v:28022.3-28070.6" - process $proc$libresoc.v:28022$616 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:28023.5-28023.29" - switch \initial - attribute \src "libresoc.v:28023.9-28023.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] - end - attribute \src "libresoc.v:28071.3-28119.6" - process $proc$libresoc.v:28071$617 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:28072.5-28072.29" - switch \initial - attribute \src "libresoc.v:28072.9-28072.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] - end - attribute \src "libresoc.v:28120.3-28168.6" - process $proc$libresoc.v:28120$618 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:28121.5-28121.29" - switch \initial - attribute \src "libresoc.v:28121.9-28121.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 - case - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] - end - attribute \src "libresoc.v:28169.3-28217.6" - process $proc$libresoc.v:28169$619 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:28170.5-28170.29" - switch \initial - attribute \src "libresoc.v:28170.9-28170.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] - end - attribute \src "libresoc.v:28218.3-28266.6" - process $proc$libresoc.v:28218$620 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:28219.5-28219.29" - switch \initial - attribute \src "libresoc.v:28219.9-28219.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] - end - attribute \src "libresoc.v:28267.3-28315.6" - process $proc$libresoc.v:28267$621 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:28268.5-28268.29" - switch \initial - attribute \src "libresoc.v:28268.9-28268.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] - end - attribute \src "libresoc.v:28316.3-28364.6" - process $proc$libresoc.v:28316$622 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:28317.5-28317.29" - switch \initial - attribute \src "libresoc.v:28317.9-28317.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] - end - attribute \src "libresoc.v:28365.3-28395.6" - process $proc$libresoc.v:28365$623 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:28366.5-28366.29" - switch \initial - attribute \src "libresoc.v:28366.9-28366.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01101000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'10100111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110001 - case - assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] - end - attribute \src "libresoc.v:28396.3-28444.6" - process $proc$libresoc.v:28396$624 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:28397.5-28397.29" - switch \initial - attribute \src "libresoc.v:28397.9-28397.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub21_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] - end - attribute \src "libresoc.v:28445.3-28493.6" - process $proc$libresoc.v:28445$625 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:28446.5-28446.29" - switch \initial - attribute \src "libresoc.v:28446.9-28446.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - case - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] - end - attribute \src "libresoc.v:28494.3-28542.6" - process $proc$libresoc.v:28494$626 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:28495.5-28495.29" - switch \initial - attribute \src "libresoc.v:28495.9-28495.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] - end - attribute \src "libresoc.v:28543.3-28591.6" - process $proc$libresoc.v:28543$627 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:28544.5-28544.29" - switch \initial - attribute \src "libresoc.v:28544.9-28544.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] - end - attribute \src "libresoc.v:28592.3-28640.6" - process $proc$libresoc.v:28592$628 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_out_sel[1:0] $1\dec31_dec_sub21_out_sel[1:0] - attribute \src "libresoc.v:28593.5-28593.29" - switch \initial - attribute \src "libresoc.v:28593.9-28593.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub21_out_sel $0\dec31_dec_sub21_out_sel[1:0] - end - attribute \src "libresoc.v:28641.3-28689.6" - process $proc$libresoc.v:28641$629 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:28642.5-28642.29" - switch \initial - attribute \src "libresoc.v:28642.9-28642.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] - end - attribute \src "libresoc.v:28690.3-28738.6" - process $proc$libresoc.v:28690$630 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:28691.5-28691.29" - switch \initial - attribute \src "libresoc.v:28691.9-28691.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:28744.1-30323.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" -attribute \generator "nMigen" -module \dec31_dec_sub22 - attribute \src "libresoc.v:29277.3-29331.6" - wire width 8 $0\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:29497.3-29551.6" - wire $0\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:30212.3-30266.6" - wire width 3 $0\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:30267.3-30321.6" - wire width 3 $0\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:29222.3-29276.6" - wire width 2 $0\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:29442.3-29496.6" - wire $0\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:29937.3-29991.6" - wire width 5 $0\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:29002.3-29056.6" - wire width 12 $0\dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:29992.3-30046.6" - wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:30047.3-30101.6" - wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:30102.3-30156.6" - wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:29607.3-29661.6" - wire width 7 $0\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:29332.3-29386.6" - wire $0\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:29387.3-29441.6" - wire $0\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:29717.3-29771.6" - wire $0\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:29057.3-29111.6" - wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:29827.3-29881.6" - wire $0\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:30157.3-30211.6" - wire width 2 $0\dec31_dec_sub22_out_sel[1:0] - attribute \src "libresoc.v:29167.3-29221.6" - wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:29662.3-29716.6" - wire $0\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:29882.3-29936.6" - wire $0\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:29772.3-29826.6" - wire $0\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:29552.3-29606.6" - wire $0\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:29112.3-29166.6" - wire width 2 $0\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:28745.7-28745.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:29277.3-29331.6" - wire width 8 $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:29497.3-29551.6" - wire $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:30212.3-30266.6" - wire width 3 $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:30267.3-30321.6" - wire width 3 $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:29222.3-29276.6" - wire width 2 $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:29442.3-29496.6" - wire $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:29937.3-29991.6" - wire width 5 $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:29002.3-29056.6" - wire width 12 $1\dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:29992.3-30046.6" - wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:30047.3-30101.6" - wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:30102.3-30156.6" - wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:29607.3-29661.6" - wire width 7 $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:29332.3-29386.6" - wire $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:29387.3-29441.6" - wire $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:29717.3-29771.6" - wire $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:29057.3-29111.6" - wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:29827.3-29881.6" - wire $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:30157.3-30211.6" - wire width 2 $1\dec31_dec_sub22_out_sel[1:0] - attribute \src "libresoc.v:29167.3-29221.6" - wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:29662.3-29716.6" - wire $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:29882.3-29936.6" - wire $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:29772.3-29826.6" - wire $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:29552.3-29606.6" - wire $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:29112.3-29166.6" - wire width 2 $1\dec31_dec_sub22_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub22_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub22_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub22_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub22_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub22_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub22_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub22_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub22_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub22_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub22_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub22_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub22_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub22_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub22_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub22_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub22_upd - attribute \src "libresoc.v:28745.7-28745.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "libresoc.v:28745.7-28745.20" - process $proc$libresoc.v:28745$656 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:29002.3-29056.6" - process $proc$libresoc.v:29002$632 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_function_unit[11:0] $1\dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:29003.5-29003.29" - switch \initial - attribute \src "libresoc.v:29003.9-29003.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'100000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - case - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[11:0] - end - attribute \src "libresoc.v:29057.3-29111.6" - process $proc$libresoc.v:29057$633 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:29058.5-29058.29" - switch \initial - attribute \src "libresoc.v:29058.9-29058.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] - end - attribute \src "libresoc.v:29112.3-29166.6" - process $proc$libresoc.v:29112$634 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:29113.5-29113.29" - switch \initial - attribute \src "libresoc.v:29113.9-29113.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] - end - attribute \src "libresoc.v:29167.3-29221.6" - process $proc$libresoc.v:29167$635 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:29168.5-29168.29" - switch \initial - attribute \src "libresoc.v:29168.9-29168.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] - end - attribute \src "libresoc.v:29222.3-29276.6" - process $proc$libresoc.v:29222$636 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:29223.5-29223.29" - switch \initial - attribute \src "libresoc.v:29223.9-29223.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] - end - attribute \src "libresoc.v:29277.3-29331.6" - process $proc$libresoc.v:29277$637 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:29278.5-29278.29" - switch \initial - attribute \src "libresoc.v:29278.9-29278.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'01011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'01100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'11001001 - case - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] - end - attribute \src "libresoc.v:29332.3-29386.6" - process $proc$libresoc.v:29332$638 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:29333.5-29333.29" - switch \initial - attribute \src "libresoc.v:29333.9-29333.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] - end - attribute \src "libresoc.v:29387.3-29441.6" - process $proc$libresoc.v:29387$639 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:29388.5-29388.29" - switch \initial - attribute \src "libresoc.v:29388.9-29388.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] - end - attribute \src "libresoc.v:29442.3-29496.6" - process $proc$libresoc.v:29442$640 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:29443.5-29443.29" - switch \initial - attribute \src "libresoc.v:29443.9-29443.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] - end - attribute \src "libresoc.v:29497.3-29551.6" - process $proc$libresoc.v:29497$641 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:29498.5-29498.29" - switch \initial - attribute \src "libresoc.v:29498.9-29498.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - case - assign $1\dec31_dec_sub22_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] - end - attribute \src "libresoc.v:29552.3-29606.6" - process $proc$libresoc.v:29552$642 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:29553.5-29553.29" - switch \initial - attribute \src "libresoc.v:29553.9-29553.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] - end - attribute \src "libresoc.v:29607.3-29661.6" - process $proc$libresoc.v:29607$643 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:29608.5-29608.29" - switch \initial - attribute \src "libresoc.v:29608.9-29608.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0011100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - case - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] - end - attribute \src "libresoc.v:29662.3-29716.6" - process $proc$libresoc.v:29662$644 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:29663.5-29663.29" - switch \initial - attribute \src "libresoc.v:29663.9-29663.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] - end - attribute \src "libresoc.v:29717.3-29771.6" - process $proc$libresoc.v:29717$645 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:29718.5-29718.29" - switch \initial - attribute \src "libresoc.v:29718.9-29718.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] - end - attribute \src "libresoc.v:29772.3-29826.6" - process $proc$libresoc.v:29772$646 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:29773.5-29773.29" - switch \initial - attribute \src "libresoc.v:29773.9-29773.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] - end - attribute \src "libresoc.v:29827.3-29881.6" - process $proc$libresoc.v:29827$647 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:29828.5-29828.29" - switch \initial - attribute \src "libresoc.v:29828.9-29828.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] - end - attribute \src "libresoc.v:29882.3-29936.6" - process $proc$libresoc.v:29882$648 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:29883.5-29883.29" - switch \initial - attribute \src "libresoc.v:29883.9-29883.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] - end - attribute \src "libresoc.v:29937.3-29991.6" - process $proc$libresoc.v:29937$649 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:29938.5-29938.29" - switch \initial - attribute \src "libresoc.v:29938.9-29938.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub22_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] - end - attribute \src "libresoc.v:29992.3-30046.6" - process $proc$libresoc.v:29992$650 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:29993.5-29993.29" - switch \initial - attribute \src "libresoc.v:29993.9-29993.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] - end - attribute \src "libresoc.v:30047.3-30101.6" - process $proc$libresoc.v:30047$651 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:30048.5-30048.29" - switch \initial - attribute \src "libresoc.v:30048.9-30048.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - case - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] - end - attribute \src "libresoc.v:30102.3-30156.6" - process $proc$libresoc.v:30102$652 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:30103.5-30103.29" - switch \initial - attribute \src "libresoc.v:30103.9-30103.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] - end - attribute \src "libresoc.v:30157.3-30211.6" - process $proc$libresoc.v:30157$653 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_out_sel[1:0] $1\dec31_dec_sub22_out_sel[1:0] - attribute \src "libresoc.v:30158.5-30158.29" - switch \initial - attribute \src "libresoc.v:30158.9-30158.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub22_out_sel $0\dec31_dec_sub22_out_sel[1:0] - end - attribute \src "libresoc.v:30212.3-30266.6" - process $proc$libresoc.v:30212$654 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:30213.5-30213.29" - switch \initial - attribute \src "libresoc.v:30213.9-30213.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] - end - attribute \src "libresoc.v:30267.3-30321.6" - process $proc$libresoc.v:30267$655 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:30268.5-30268.29" - switch \initial - attribute \src "libresoc.v:30268.9-30268.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:30327.1-31762.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" -attribute \generator "nMigen" -module \dec31_dec_sub23 - attribute \src "libresoc.v:30830.3-30878.6" - wire width 8 $0\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:31026.3-31074.6" - wire $0\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:31663.3-31711.6" - wire width 3 $0\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:31712.3-31760.6" - wire width 3 $0\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:30781.3-30829.6" - wire width 2 $0\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:30977.3-31025.6" - wire $0\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:31418.3-31466.6" - wire width 5 $0\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:30585.3-30633.6" - wire width 12 $0\dec31_dec_sub23_function_unit[11:0] - attribute \src "libresoc.v:31467.3-31515.6" - wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:31516.3-31564.6" - wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:31565.3-31613.6" - wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:31124.3-31172.6" - wire width 7 $0\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:30879.3-30927.6" - wire $0\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:30928.3-30976.6" - wire $0\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:31222.3-31270.6" - wire $0\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:30634.3-30682.6" - wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:31320.3-31368.6" - wire $0\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:31614.3-31662.6" - wire width 2 $0\dec31_dec_sub23_out_sel[1:0] - attribute \src "libresoc.v:30732.3-30780.6" - wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:31173.3-31221.6" - wire $0\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:31369.3-31417.6" - wire $0\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:31271.3-31319.6" - wire $0\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:31075.3-31123.6" - wire $0\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:30683.3-30731.6" - wire width 2 $0\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:30328.7-30328.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:30830.3-30878.6" - wire width 8 $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:31026.3-31074.6" - wire $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:31663.3-31711.6" - wire width 3 $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:31712.3-31760.6" - wire width 3 $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:30781.3-30829.6" - wire width 2 $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:30977.3-31025.6" - wire $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:31418.3-31466.6" - wire width 5 $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:30585.3-30633.6" - wire width 12 $1\dec31_dec_sub23_function_unit[11:0] - attribute \src "libresoc.v:31467.3-31515.6" - wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:31516.3-31564.6" - wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:31565.3-31613.6" - wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:31124.3-31172.6" - wire width 7 $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:30879.3-30927.6" - wire $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:30928.3-30976.6" - wire $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:31222.3-31270.6" - wire $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:30634.3-30682.6" - wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:31320.3-31368.6" - wire $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:31614.3-31662.6" - wire width 2 $1\dec31_dec_sub23_out_sel[1:0] - attribute \src "libresoc.v:30732.3-30780.6" - wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:31173.3-31221.6" - wire $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:31369.3-31417.6" - wire $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:31271.3-31319.6" - wire $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:31075.3-31123.6" - wire $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:30683.3-30731.6" - wire width 2 $1\dec31_dec_sub23_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub23_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub23_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub23_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub23_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub23_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub23_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub23_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub23_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub23_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub23_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub23_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub23_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub23_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub23_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub23_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub23_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub23_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub23_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub23_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub23_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub23_upd - attribute \src "libresoc.v:30328.7-30328.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "libresoc.v:30328.7-30328.20" - process $proc$libresoc.v:30328$681 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:30585.3-30633.6" - process $proc$libresoc.v:30585$657 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_function_unit[11:0] $1\dec31_dec_sub23_function_unit[11:0] - attribute \src "libresoc.v:30586.5-30586.29" - switch \initial - attribute \src "libresoc.v:30586.9-30586.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - case - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[11:0] - end - attribute \src "libresoc.v:30634.3-30682.6" - process $proc$libresoc.v:30634$658 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:30635.5-30635.29" - switch \initial - attribute \src "libresoc.v:30635.9-30635.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 - case - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] - end - attribute \src "libresoc.v:30683.3-30731.6" - process $proc$libresoc.v:30683$659 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:30684.5-30684.29" - switch \initial - attribute \src "libresoc.v:30684.9-30684.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] - end - attribute \src "libresoc.v:30732.3-30780.6" - process $proc$libresoc.v:30732$660 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:30733.5-30733.29" - switch \initial - attribute \src "libresoc.v:30733.9-30733.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] - end - attribute \src "libresoc.v:30781.3-30829.6" - process $proc$libresoc.v:30781$661 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:30782.5-30782.29" - switch \initial - attribute \src "libresoc.v:30782.9-30782.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] - end - attribute \src "libresoc.v:30830.3-30878.6" - process $proc$libresoc.v:30830$662 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:30831.5-30831.29" - switch \initial - attribute \src "libresoc.v:30831.9-30831.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111101 - case - assign $1\dec31_dec_sub23_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] - end - attribute \src "libresoc.v:30879.3-30927.6" - process $proc$libresoc.v:30879$663 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:30880.5-30880.29" - switch \initial - attribute \src "libresoc.v:30880.9-30880.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] - end - attribute \src "libresoc.v:30928.3-30976.6" - process $proc$libresoc.v:30928$664 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:30929.5-30929.29" - switch \initial - attribute \src "libresoc.v:30929.9-30929.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] - end - attribute \src "libresoc.v:30977.3-31025.6" - process $proc$libresoc.v:30977$665 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:30978.5-30978.29" - switch \initial - attribute \src "libresoc.v:30978.9-30978.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] - end - attribute \src "libresoc.v:31026.3-31074.6" - process $proc$libresoc.v:31026$666 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:31027.5-31027.29" - switch \initial - attribute \src "libresoc.v:31027.9-31027.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - case - assign $1\dec31_dec_sub23_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] - end - attribute \src "libresoc.v:31075.3-31123.6" - process $proc$libresoc.v:31075$667 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:31076.5-31076.29" - switch \initial - attribute \src "libresoc.v:31076.9-31076.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] - end - attribute \src "libresoc.v:31124.3-31172.6" - process $proc$libresoc.v:31124$668 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:31125.5-31125.29" - switch \initial - attribute \src "libresoc.v:31125.9-31125.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - case - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] - end - attribute \src "libresoc.v:31173.3-31221.6" - process $proc$libresoc.v:31173$669 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:31174.5-31174.29" - switch \initial - attribute \src "libresoc.v:31174.9-31174.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] - end - attribute \src "libresoc.v:31222.3-31270.6" - process $proc$libresoc.v:31222$670 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:31223.5-31223.29" - switch \initial - attribute \src "libresoc.v:31223.9-31223.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] - end - attribute \src "libresoc.v:31271.3-31319.6" - process $proc$libresoc.v:31271$671 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:31272.5-31272.29" - switch \initial - attribute \src "libresoc.v:31272.9-31272.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] - end - attribute \src "libresoc.v:31320.3-31368.6" - process $proc$libresoc.v:31320$672 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:31321.5-31321.29" - switch \initial - attribute \src "libresoc.v:31321.9-31321.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] - end - attribute \src "libresoc.v:31369.3-31417.6" - process $proc$libresoc.v:31369$673 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:31370.5-31370.29" - switch \initial - attribute \src "libresoc.v:31370.9-31370.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] - end - attribute \src "libresoc.v:31418.3-31466.6" - process $proc$libresoc.v:31418$674 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:31419.5-31419.29" - switch \initial - attribute \src "libresoc.v:31419.9-31419.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub23_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] - end - attribute \src "libresoc.v:31467.3-31515.6" - process $proc$libresoc.v:31467$675 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:31468.5-31468.29" - switch \initial - attribute \src "libresoc.v:31468.9-31468.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - case - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] - end - attribute \src "libresoc.v:31516.3-31564.6" - process $proc$libresoc.v:31516$676 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:31517.5-31517.29" - switch \initial - attribute \src "libresoc.v:31517.9-31517.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] - end - attribute \src "libresoc.v:31565.3-31613.6" - process $proc$libresoc.v:31565$677 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:31566.5-31566.29" - switch \initial - attribute \src "libresoc.v:31566.9-31566.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] - end - attribute \src "libresoc.v:31614.3-31662.6" - process $proc$libresoc.v:31614$678 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_out_sel[1:0] $1\dec31_dec_sub23_out_sel[1:0] - attribute \src "libresoc.v:31615.5-31615.29" - switch \initial - attribute \src "libresoc.v:31615.9-31615.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub23_out_sel $0\dec31_dec_sub23_out_sel[1:0] - end - attribute \src "libresoc.v:31663.3-31711.6" - process $proc$libresoc.v:31663$679 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:31664.5-31664.29" - switch \initial - attribute \src "libresoc.v:31664.9-31664.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] - end - attribute \src "libresoc.v:31712.3-31760.6" - process $proc$libresoc.v:31712$680 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:31713.5-31713.29" - switch \initial - attribute \src "libresoc.v:31713.9-31713.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:31766.1-32481.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" -attribute \generator "nMigen" -module \dec31_dec_sub24 - attribute \src "libresoc.v:32119.3-32137.6" - wire width 8 $0\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:32195.3-32213.6" - wire $0\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:32442.3-32460.6" - wire width 3 $0\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:32461.3-32479.6" - wire width 3 $0\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:32100.3-32118.6" - wire width 2 $0\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:32176.3-32194.6" - wire $0\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:32347.3-32365.6" - wire width 5 $0\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:32024.3-32042.6" - wire width 12 $0\dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:32366.3-32384.6" - wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:32385.3-32403.6" - wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:32404.3-32422.6" - wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:32233.3-32251.6" - wire width 7 $0\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:32138.3-32156.6" - wire $0\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:32157.3-32175.6" - wire $0\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:32271.3-32289.6" - wire $0\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:32043.3-32061.6" - wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:32309.3-32327.6" - wire $0\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:32423.3-32441.6" - wire width 2 $0\dec31_dec_sub24_out_sel[1:0] - attribute \src "libresoc.v:32081.3-32099.6" - wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:32252.3-32270.6" - wire $0\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:32328.3-32346.6" - wire $0\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:32290.3-32308.6" - wire $0\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:32214.3-32232.6" - wire $0\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:32062.3-32080.6" - wire width 2 $0\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:31767.7-31767.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:32119.3-32137.6" - wire width 8 $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:32195.3-32213.6" - wire $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:32442.3-32460.6" - wire width 3 $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:32461.3-32479.6" - wire width 3 $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:32100.3-32118.6" - wire width 2 $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:32176.3-32194.6" - wire $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:32347.3-32365.6" - wire width 5 $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:32024.3-32042.6" - wire width 12 $1\dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:32366.3-32384.6" - wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:32385.3-32403.6" - wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:32404.3-32422.6" - wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:32233.3-32251.6" - wire width 7 $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:32138.3-32156.6" - wire $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:32157.3-32175.6" - wire $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:32271.3-32289.6" - wire $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:32043.3-32061.6" - wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:32309.3-32327.6" - wire $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:32423.3-32441.6" - wire width 2 $1\dec31_dec_sub24_out_sel[1:0] - attribute \src "libresoc.v:32081.3-32099.6" - wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:32252.3-32270.6" - wire $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:32328.3-32346.6" - wire $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:32290.3-32308.6" - wire $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:32214.3-32232.6" - wire $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:32062.3-32080.6" - wire width 2 $1\dec31_dec_sub24_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub24_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub24_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub24_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub24_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub24_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub24_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub24_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub24_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub24_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub24_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub24_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub24_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub24_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub24_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub24_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub24_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub24_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub24_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub24_upd - attribute \src "libresoc.v:31767.7-31767.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "libresoc.v:31767.7-31767.20" - process $proc$libresoc.v:31767$706 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:32024.3-32042.6" - process $proc$libresoc.v:32024$682 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_function_unit[11:0] $1\dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:32025.5-32025.29" - switch \initial - attribute \src "libresoc.v:32025.9-32025.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 - case - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[11:0] - end - attribute \src "libresoc.v:32043.3-32061.6" - process $proc$libresoc.v:32043$683 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:32044.5-32044.29" - switch \initial - attribute \src "libresoc.v:32044.9-32044.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] - end - attribute \src "libresoc.v:32062.3-32080.6" - process $proc$libresoc.v:32062$684 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:32063.5-32063.29" - switch \initial - attribute \src "libresoc.v:32063.9-32063.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub24_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] - end - attribute \src "libresoc.v:32081.3-32099.6" - process $proc$libresoc.v:32081$685 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:32082.5-32082.29" - switch \initial - attribute \src "libresoc.v:32082.9-32082.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] - end - attribute \src "libresoc.v:32100.3-32118.6" - process $proc$libresoc.v:32100$686 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:32101.5-32101.29" - switch \initial - attribute \src "libresoc.v:32101.9-32101.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] - end - attribute \src "libresoc.v:32119.3-32137.6" - process $proc$libresoc.v:32119$687 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:32120.5-32120.29" - switch \initial - attribute \src "libresoc.v:32120.9-32120.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_asmcode[7:0] 8'10011111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100101 - case - assign $1\dec31_dec_sub24_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] - end - attribute \src "libresoc.v:32138.3-32156.6" - process $proc$libresoc.v:32138$688 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:32139.5-32139.29" - switch \initial - attribute \src "libresoc.v:32139.9-32139.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] - end - attribute \src "libresoc.v:32157.3-32175.6" - process $proc$libresoc.v:32157$689 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:32158.5-32158.29" - switch \initial - attribute \src "libresoc.v:32158.9-32158.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] - end - attribute \src "libresoc.v:32176.3-32194.6" - process $proc$libresoc.v:32176$690 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:32177.5-32177.29" - switch \initial - attribute \src "libresoc.v:32177.9-32177.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] - end - attribute \src "libresoc.v:32195.3-32213.6" - process $proc$libresoc.v:32195$691 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:32196.5-32196.29" - switch \initial - attribute \src "libresoc.v:32196.9-32196.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_br[0:0] 1'0 - case - assign $1\dec31_dec_sub24_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] - end - attribute \src "libresoc.v:32214.3-32232.6" - process $proc$libresoc.v:32214$692 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:32215.5-32215.29" - switch \initial - attribute \src "libresoc.v:32215.9-32215.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] - end - attribute \src "libresoc.v:32233.3-32251.6" - process $proc$libresoc.v:32233$693 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:32234.5-32234.29" - switch \initial - attribute \src "libresoc.v:32234.9-32234.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 - case - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] - end - attribute \src "libresoc.v:32252.3-32270.6" - process $proc$libresoc.v:32252$694 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:32253.5-32253.29" - switch \initial - attribute \src "libresoc.v:32253.9-32253.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] - end - attribute \src "libresoc.v:32271.3-32289.6" - process $proc$libresoc.v:32271$695 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:32272.5-32272.29" - switch \initial - attribute \src "libresoc.v:32272.9-32272.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 - case - assign $1\dec31_dec_sub24_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] - end - attribute \src "libresoc.v:32290.3-32308.6" - process $proc$libresoc.v:32290$696 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:32291.5-32291.29" - switch \initial - attribute \src "libresoc.v:32291.9-32291.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub24_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] - end - attribute \src "libresoc.v:32309.3-32327.6" - process $proc$libresoc.v:32309$697 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:32310.5-32310.29" - switch \initial - attribute \src "libresoc.v:32310.9-32310.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] - end - attribute \src "libresoc.v:32328.3-32346.6" - process $proc$libresoc.v:32328$698 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:32329.5-32329.29" - switch \initial - attribute \src "libresoc.v:32329.9-32329.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] - end - attribute \src "libresoc.v:32347.3-32365.6" - process $proc$libresoc.v:32347$699 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:32348.5-32348.29" - switch \initial - attribute \src "libresoc.v:32348.9-32348.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub24_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] - end - attribute \src "libresoc.v:32366.3-32384.6" - process $proc$libresoc.v:32366$700 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:32367.5-32367.29" - switch \initial - attribute \src "libresoc.v:32367.9-32367.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] - end - attribute \src "libresoc.v:32385.3-32403.6" - process $proc$libresoc.v:32385$701 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:32386.5-32386.29" - switch \initial - attribute \src "libresoc.v:32386.9-32386.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'1011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] - end - attribute \src "libresoc.v:32404.3-32422.6" - process $proc$libresoc.v:32404$702 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:32405.5-32405.29" - switch \initial - attribute \src "libresoc.v:32405.9-32405.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] - end - attribute \src "libresoc.v:32423.3-32441.6" - process $proc$libresoc.v:32423$703 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_out_sel[1:0] $1\dec31_dec_sub24_out_sel[1:0] - attribute \src "libresoc.v:32424.5-32424.29" - switch \initial - attribute \src "libresoc.v:32424.9-32424.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub24_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_out_sel $0\dec31_dec_sub24_out_sel[1:0] - end - attribute \src "libresoc.v:32442.3-32460.6" - process $proc$libresoc.v:32442$704 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:32443.5-32443.29" - switch \initial - attribute \src "libresoc.v:32443.9-32443.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] - end - attribute \src "libresoc.v:32461.3-32479.6" - process $proc$libresoc.v:32461$705 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:32462.5-32462.29" - switch \initial - attribute \src "libresoc.v:32462.9-32462.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub24_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:32485.1-33992.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" -attribute \generator "nMigen" -module \dec31_dec_sub26 - attribute \src "libresoc.v:33003.3-33054.6" - wire width 8 $0\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:33211.3-33262.6" - wire $0\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:33887.3-33938.6" - wire width 3 $0\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:33939.3-33990.6" - wire width 3 $0\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:32951.3-33002.6" - wire width 2 $0\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:33159.3-33210.6" - wire $0\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:33627.3-33678.6" - wire width 5 $0\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:32743.3-32794.6" - wire width 12 $0\dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:33679.3-33730.6" - wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:33731.3-33782.6" - wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:33783.3-33834.6" - wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:33315.3-33366.6" - wire width 7 $0\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:33055.3-33106.6" - wire $0\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:33107.3-33158.6" - wire $0\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:33419.3-33470.6" - wire $0\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:32795.3-32846.6" - wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:33523.3-33574.6" - wire $0\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:33835.3-33886.6" - wire width 2 $0\dec31_dec_sub26_out_sel[1:0] - attribute \src "libresoc.v:32899.3-32950.6" - wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:33367.3-33418.6" - wire $0\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:33575.3-33626.6" - wire $0\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:33471.3-33522.6" - wire $0\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:33263.3-33314.6" - wire $0\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:32847.3-32898.6" - wire width 2 $0\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:32486.7-32486.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:33003.3-33054.6" - wire width 8 $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:33211.3-33262.6" - wire $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:33887.3-33938.6" - wire width 3 $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:33939.3-33990.6" - wire width 3 $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:32951.3-33002.6" - wire width 2 $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:33159.3-33210.6" - wire $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:33627.3-33678.6" - wire width 5 $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:32743.3-32794.6" - wire width 12 $1\dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:33679.3-33730.6" - wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:33731.3-33782.6" - wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:33783.3-33834.6" - wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:33315.3-33366.6" - wire width 7 $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:33055.3-33106.6" - wire $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:33107.3-33158.6" - wire $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:33419.3-33470.6" - wire $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:32795.3-32846.6" - wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:33523.3-33574.6" - wire $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:33835.3-33886.6" - wire width 2 $1\dec31_dec_sub26_out_sel[1:0] - attribute \src "libresoc.v:32899.3-32950.6" - wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:33367.3-33418.6" - wire $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:33575.3-33626.6" - wire $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:33471.3-33522.6" - wire $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:33263.3-33314.6" - wire $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:32847.3-32898.6" - wire width 2 $1\dec31_dec_sub26_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub26_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub26_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub26_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub26_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub26_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub26_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub26_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub26_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub26_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub26_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub26_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub26_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub26_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub26_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub26_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub26_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub26_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub26_upd - attribute \src "libresoc.v:32486.7-32486.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "libresoc.v:32486.7-32486.20" - process $proc$libresoc.v:32486$731 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:32743.3-32794.6" - process $proc$libresoc.v:32743$707 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_function_unit[11:0] $1\dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:32744.5-32744.29" - switch \initial - attribute \src "libresoc.v:32744.9-32744.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 - case - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[11:0] - end - attribute \src "libresoc.v:32795.3-32846.6" - process $proc$libresoc.v:32795$708 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:32796.5-32796.29" - switch \initial - attribute \src "libresoc.v:32796.9-32796.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] - end - attribute \src "libresoc.v:32847.3-32898.6" - process $proc$libresoc.v:32847$709 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:32848.5-32848.29" - switch \initial - attribute \src "libresoc.v:32848.9-32848.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] - end - attribute \src "libresoc.v:32899.3-32950.6" - process $proc$libresoc.v:32899$710 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:32900.5-32900.29" - switch \initial - attribute \src "libresoc.v:32900.9-32900.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] - end - attribute \src "libresoc.v:32951.3-33002.6" - process $proc$libresoc.v:32951$711 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:32952.5-32952.29" - switch \initial - attribute \src "libresoc.v:32952.9-32952.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] - end - attribute \src "libresoc.v:33003.3-33054.6" - process $proc$libresoc.v:33003$712 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:33004.5-33004.29" - switch \initial - attribute \src "libresoc.v:33004.9-33004.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100001 - case - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] - end - attribute \src "libresoc.v:33055.3-33106.6" - process $proc$libresoc.v:33055$713 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:33056.5-33056.29" - switch \initial - attribute \src "libresoc.v:33056.9-33056.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] - end - attribute \src "libresoc.v:33107.3-33158.6" - process $proc$libresoc.v:33107$714 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:33108.5-33108.29" - switch \initial - attribute \src "libresoc.v:33108.9-33108.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] - end - attribute \src "libresoc.v:33159.3-33210.6" - process $proc$libresoc.v:33159$715 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:33160.5-33160.29" - switch \initial - attribute \src "libresoc.v:33160.9-33160.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 - case - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] - end - attribute \src "libresoc.v:33211.3-33262.6" - process $proc$libresoc.v:33211$716 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:33212.5-33212.29" - switch \initial - attribute \src "libresoc.v:33212.9-33212.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - case - assign $1\dec31_dec_sub26_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] - end - attribute \src "libresoc.v:33263.3-33314.6" - process $proc$libresoc.v:33263$717 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:33264.5-33264.29" - switch \initial - attribute \src "libresoc.v:33264.9-33264.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] - end - attribute \src "libresoc.v:33315.3-33366.6" - process $proc$libresoc.v:33315$718 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:33316.5-33316.29" - switch \initial - attribute \src "libresoc.v:33316.9-33316.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0100000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 - case - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] - end - attribute \src "libresoc.v:33367.3-33418.6" - process $proc$libresoc.v:33367$719 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:33368.5-33368.29" - switch \initial - attribute \src "libresoc.v:33368.9-33368.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] - end - attribute \src "libresoc.v:33419.3-33470.6" - process $proc$libresoc.v:33419$720 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:33420.5-33420.29" - switch \initial - attribute \src "libresoc.v:33420.9-33420.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] - end - attribute \src "libresoc.v:33471.3-33522.6" - process $proc$libresoc.v:33471$721 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:33472.5-33472.29" - switch \initial - attribute \src "libresoc.v:33472.9-33472.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'1 - case - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] - end - attribute \src "libresoc.v:33523.3-33574.6" - process $proc$libresoc.v:33523$722 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:33524.5-33524.29" - switch \initial - attribute \src "libresoc.v:33524.9-33524.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] - end - attribute \src "libresoc.v:33575.3-33626.6" - process $proc$libresoc.v:33575$723 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:33576.5-33576.29" - switch \initial - attribute \src "libresoc.v:33576.9-33576.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] - end - attribute \src "libresoc.v:33627.3-33678.6" - process $proc$libresoc.v:33627$724 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:33628.5-33628.29" - switch \initial - attribute \src "libresoc.v:33628.9-33628.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'10000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'10000 - case - assign $1\dec31_dec_sub26_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] - end - attribute \src "libresoc.v:33679.3-33730.6" - process $proc$libresoc.v:33679$725 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:33680.5-33680.29" - switch \initial - attribute \src "libresoc.v:33680.9-33680.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] - end - attribute \src "libresoc.v:33731.3-33782.6" - process $proc$libresoc.v:33731$726 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:33732.5-33732.29" - switch \initial - attribute \src "libresoc.v:33732.9-33732.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 - case - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] - end - attribute \src "libresoc.v:33783.3-33834.6" - process $proc$libresoc.v:33783$727 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:33784.5-33784.29" - switch \initial - attribute \src "libresoc.v:33784.9-33784.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] - end - attribute \src "libresoc.v:33835.3-33886.6" - process $proc$libresoc.v:33835$728 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_out_sel[1:0] $1\dec31_dec_sub26_out_sel[1:0] - attribute \src "libresoc.v:33836.5-33836.29" - switch \initial - attribute \src "libresoc.v:33836.9-33836.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub26_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub26_out_sel $0\dec31_dec_sub26_out_sel[1:0] - end - attribute \src "libresoc.v:33887.3-33938.6" - process $proc$libresoc.v:33887$729 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:33888.5-33888.29" - switch \initial - attribute \src "libresoc.v:33888.9-33888.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] - end - attribute \src "libresoc.v:33939.3-33990.6" - process $proc$libresoc.v:33939$730 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:33940.5-33940.29" - switch \initial - attribute \src "libresoc.v:33940.9-33940.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:33996.1-34711.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" -attribute \generator "nMigen" -module \dec31_dec_sub27 - attribute \src "libresoc.v:34349.3-34367.6" - wire width 8 $0\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:34425.3-34443.6" - wire $0\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:34672.3-34690.6" - wire width 3 $0\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:34691.3-34709.6" - wire width 3 $0\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:34330.3-34348.6" - wire width 2 $0\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:34406.3-34424.6" - wire $0\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:34577.3-34595.6" - wire width 5 $0\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:34254.3-34272.6" - wire width 12 $0\dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:34596.3-34614.6" - wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:34615.3-34633.6" - wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:34634.3-34652.6" - wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:34463.3-34481.6" - wire width 7 $0\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:34368.3-34386.6" - wire $0\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:34387.3-34405.6" - wire $0\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:34501.3-34519.6" - wire $0\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:34273.3-34291.6" - wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:34539.3-34557.6" - wire $0\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:34653.3-34671.6" - wire width 2 $0\dec31_dec_sub27_out_sel[1:0] - attribute \src "libresoc.v:34311.3-34329.6" - wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:34482.3-34500.6" - wire $0\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:34558.3-34576.6" - wire $0\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:34520.3-34538.6" - wire $0\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:34444.3-34462.6" - wire $0\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:34292.3-34310.6" - wire width 2 $0\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:33997.7-33997.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:34349.3-34367.6" - wire width 8 $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:34425.3-34443.6" - wire $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:34672.3-34690.6" - wire width 3 $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:34691.3-34709.6" - wire width 3 $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:34330.3-34348.6" - wire width 2 $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:34406.3-34424.6" - wire $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:34577.3-34595.6" - wire width 5 $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:34254.3-34272.6" - wire width 12 $1\dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:34596.3-34614.6" - wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:34615.3-34633.6" - wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:34634.3-34652.6" - wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:34463.3-34481.6" - wire width 7 $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:34368.3-34386.6" - wire $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:34387.3-34405.6" - wire $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:34501.3-34519.6" - wire $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:34273.3-34291.6" - wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:34539.3-34557.6" - wire $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:34653.3-34671.6" - wire width 2 $1\dec31_dec_sub27_out_sel[1:0] - attribute \src "libresoc.v:34311.3-34329.6" - wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:34482.3-34500.6" - wire $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:34558.3-34576.6" - wire $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:34520.3-34538.6" - wire $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:34444.3-34462.6" - wire $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:34292.3-34310.6" - wire width 2 $1\dec31_dec_sub27_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub27_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub27_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub27_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub27_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub27_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub27_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub27_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub27_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub27_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub27_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub27_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub27_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub27_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub27_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub27_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub27_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub27_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub27_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub27_upd - attribute \src "libresoc.v:33997.7-33997.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "libresoc.v:33997.7-33997.20" - process $proc$libresoc.v:33997$756 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:34254.3-34272.6" - process $proc$libresoc.v:34254$732 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_function_unit[11:0] $1\dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:34255.5-34255.29" - switch \initial - attribute \src "libresoc.v:34255.9-34255.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 - case - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[11:0] - end - attribute \src "libresoc.v:34273.3-34291.6" - process $proc$libresoc.v:34273$733 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:34274.5-34274.29" - switch \initial - attribute \src "libresoc.v:34274.9-34274.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] - end - attribute \src "libresoc.v:34292.3-34310.6" - process $proc$libresoc.v:34292$734 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:34293.5-34293.29" - switch \initial - attribute \src "libresoc.v:34293.9-34293.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub27_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] - end - attribute \src "libresoc.v:34311.3-34329.6" - process $proc$libresoc.v:34311$735 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:34312.5-34312.29" - switch \initial - attribute \src "libresoc.v:34312.9-34312.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] - end - attribute \src "libresoc.v:34330.3-34348.6" - process $proc$libresoc.v:34330$736 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:34331.5-34331.29" - switch \initial - attribute \src "libresoc.v:34331.9-34331.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] - end - attribute \src "libresoc.v:34349.3-34367.6" - process $proc$libresoc.v:34349$737 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:34350.5-34350.29" - switch \initial - attribute \src "libresoc.v:34350.9-34350.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_asmcode[7:0] 8'01000111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_asmcode[7:0] 8'10011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100100 - case - assign $1\dec31_dec_sub27_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] - end - attribute \src "libresoc.v:34368.3-34386.6" - process $proc$libresoc.v:34368$738 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:34369.5-34369.29" - switch \initial - attribute \src "libresoc.v:34369.9-34369.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] - end - attribute \src "libresoc.v:34387.3-34405.6" - process $proc$libresoc.v:34387$739 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:34388.5-34388.29" - switch \initial - attribute \src "libresoc.v:34388.9-34388.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] - end - attribute \src "libresoc.v:34406.3-34424.6" - process $proc$libresoc.v:34406$740 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:34407.5-34407.29" - switch \initial - attribute \src "libresoc.v:34407.9-34407.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] - end - attribute \src "libresoc.v:34425.3-34443.6" - process $proc$libresoc.v:34425$741 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:34426.5-34426.29" - switch \initial - attribute \src "libresoc.v:34426.9-34426.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_br[0:0] 1'0 - case - assign $1\dec31_dec_sub27_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] - end - attribute \src "libresoc.v:34444.3-34462.6" - process $proc$libresoc.v:34444$742 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:34445.5-34445.29" - switch \initial - attribute \src "libresoc.v:34445.9-34445.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] - end - attribute \src "libresoc.v:34463.3-34481.6" - process $proc$libresoc.v:34463$743 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:34464.5-34464.29" - switch \initial - attribute \src "libresoc.v:34464.9-34464.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0100000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 - case - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] - end - attribute \src "libresoc.v:34482.3-34500.6" - process $proc$libresoc.v:34482$744 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:34483.5-34483.29" - switch \initial - attribute \src "libresoc.v:34483.9-34483.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] - end - attribute \src "libresoc.v:34501.3-34519.6" - process $proc$libresoc.v:34501$745 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:34502.5-34502.29" - switch \initial - attribute \src "libresoc.v:34502.9-34502.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] - end - attribute \src "libresoc.v:34520.3-34538.6" - process $proc$libresoc.v:34520$746 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:34521.5-34521.29" - switch \initial - attribute \src "libresoc.v:34521.9-34521.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub27_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] - end - attribute \src "libresoc.v:34539.3-34557.6" - process $proc$libresoc.v:34539$747 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:34540.5-34540.29" - switch \initial - attribute \src "libresoc.v:34540.9-34540.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub27_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] - end - attribute \src "libresoc.v:34558.3-34576.6" - process $proc$libresoc.v:34558$748 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:34559.5-34559.29" - switch \initial - attribute \src "libresoc.v:34559.9-34559.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] - end - attribute \src "libresoc.v:34577.3-34595.6" - process $proc$libresoc.v:34577$749 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:34578.5-34578.29" - switch \initial - attribute \src "libresoc.v:34578.9-34578.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'10000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'10000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub27_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] - end - attribute \src "libresoc.v:34596.3-34614.6" - process $proc$libresoc.v:34596$750 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:34597.5-34597.29" - switch \initial - attribute \src "libresoc.v:34597.9-34597.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] - end - attribute \src "libresoc.v:34615.3-34633.6" - process $proc$libresoc.v:34615$751 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:34616.5-34616.29" - switch \initial - attribute \src "libresoc.v:34616.9-34616.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] - end - attribute \src "libresoc.v:34634.3-34652.6" - process $proc$libresoc.v:34634$752 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:34635.5-34635.29" - switch \initial - attribute \src "libresoc.v:34635.9-34635.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] - end - attribute \src "libresoc.v:34653.3-34671.6" - process $proc$libresoc.v:34653$753 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_out_sel[1:0] $1\dec31_dec_sub27_out_sel[1:0] - attribute \src "libresoc.v:34654.5-34654.29" - switch \initial - attribute \src "libresoc.v:34654.9-34654.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub27_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub27_out_sel $0\dec31_dec_sub27_out_sel[1:0] - end - attribute \src "libresoc.v:34672.3-34690.6" - process $proc$libresoc.v:34672$754 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:34673.5-34673.29" - switch \initial - attribute \src "libresoc.v:34673.9-34673.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] - end - attribute \src "libresoc.v:34691.3-34709.6" - process $proc$libresoc.v:34691$755 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:34692.5-34692.29" - switch \initial - attribute \src "libresoc.v:34692.9-34692.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub27_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:34715.1-35862.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" -attribute \generator "nMigen" -module \dec31_dec_sub28 - attribute \src "libresoc.v:35158.3-35194.6" - wire width 8 $0\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:35306.3-35342.6" - wire $0\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:35787.3-35823.6" - wire width 3 $0\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:35824.3-35860.6" - wire width 3 $0\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:35121.3-35157.6" - wire width 2 $0\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:35269.3-35305.6" - wire $0\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:35602.3-35638.6" - wire width 5 $0\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:34973.3-35009.6" - wire width 12 $0\dec31_dec_sub28_function_unit[11:0] - attribute \src "libresoc.v:35639.3-35675.6" - wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:35676.3-35712.6" - wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:35713.3-35749.6" - wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:35380.3-35416.6" - wire width 7 $0\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:35195.3-35231.6" - wire $0\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:35232.3-35268.6" - wire $0\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:35454.3-35490.6" - wire $0\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:35010.3-35046.6" - wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:35528.3-35564.6" - wire $0\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:35750.3-35786.6" - wire width 2 $0\dec31_dec_sub28_out_sel[1:0] - attribute \src "libresoc.v:35084.3-35120.6" - wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:35417.3-35453.6" - wire $0\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:35565.3-35601.6" - wire $0\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:35491.3-35527.6" - wire $0\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:35343.3-35379.6" - wire $0\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:35047.3-35083.6" - wire width 2 $0\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:34716.7-34716.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:35158.3-35194.6" - wire width 8 $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:35306.3-35342.6" - wire $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:35787.3-35823.6" - wire width 3 $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:35824.3-35860.6" - wire width 3 $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:35121.3-35157.6" - wire width 2 $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:35269.3-35305.6" - wire $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:35602.3-35638.6" - wire width 5 $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:34973.3-35009.6" - wire width 12 $1\dec31_dec_sub28_function_unit[11:0] - attribute \src "libresoc.v:35639.3-35675.6" - wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:35676.3-35712.6" - wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:35713.3-35749.6" - wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:35380.3-35416.6" - wire width 7 $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:35195.3-35231.6" - wire $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:35232.3-35268.6" - wire $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:35454.3-35490.6" - wire $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:35010.3-35046.6" - wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:35528.3-35564.6" - wire $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:35750.3-35786.6" - wire width 2 $1\dec31_dec_sub28_out_sel[1:0] - attribute \src "libresoc.v:35084.3-35120.6" - wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:35417.3-35453.6" - wire $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:35565.3-35601.6" - wire $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:35491.3-35527.6" - wire $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:35343.3-35379.6" - wire $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:35047.3-35083.6" - wire width 2 $1\dec31_dec_sub28_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub28_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub28_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub28_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub28_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub28_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub28_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub28_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub28_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub28_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub28_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub28_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub28_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub28_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub28_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub28_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub28_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub28_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub28_upd - attribute \src "libresoc.v:34716.7-34716.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "libresoc.v:34716.7-34716.20" - process $proc$libresoc.v:34716$781 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:34973.3-35009.6" - process $proc$libresoc.v:34973$757 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_function_unit[11:0] $1\dec31_dec_sub28_function_unit[11:0] - attribute \src "libresoc.v:34974.5-34974.29" - switch \initial - attribute \src "libresoc.v:34974.9-34974.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - case - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[11:0] - end - attribute \src "libresoc.v:35010.3-35046.6" - process $proc$libresoc.v:35010$758 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:35011.5-35011.29" - switch \initial - attribute \src "libresoc.v:35011.9-35011.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] - end - attribute \src "libresoc.v:35047.3-35083.6" - process $proc$libresoc.v:35047$759 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:35048.5-35048.29" - switch \initial - attribute \src "libresoc.v:35048.9-35048.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] - end - attribute \src "libresoc.v:35084.3-35120.6" - process $proc$libresoc.v:35084$760 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:35085.5-35085.29" - switch \initial - attribute \src "libresoc.v:35085.9-35085.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] - end - attribute \src "libresoc.v:35121.3-35157.6" - process $proc$libresoc.v:35121$761 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:35122.5-35122.29" - switch \initial - attribute \src "libresoc.v:35122.9-35122.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] - end - attribute \src "libresoc.v:35158.3-35194.6" - process $proc$libresoc.v:35158$762 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:35159.5-35159.29" - switch \initial - attribute \src "libresoc.v:35159.9-35159.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00001111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'01000011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'11010000 - case - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] - end - attribute \src "libresoc.v:35195.3-35231.6" - process $proc$libresoc.v:35195$763 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:35196.5-35196.29" - switch \initial - attribute \src "libresoc.v:35196.9-35196.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] - end - attribute \src "libresoc.v:35232.3-35268.6" - process $proc$libresoc.v:35232$764 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:35233.5-35233.29" - switch \initial - attribute \src "libresoc.v:35233.9-35233.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] - end - attribute \src "libresoc.v:35269.3-35305.6" - process $proc$libresoc.v:35269$765 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:35270.5-35270.29" - switch \initial - attribute \src "libresoc.v:35270.9-35270.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] - end - attribute \src "libresoc.v:35306.3-35342.6" - process $proc$libresoc.v:35306$766 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:35307.5-35307.29" - switch \initial - attribute \src "libresoc.v:35307.9-35307.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - case - assign $1\dec31_dec_sub28_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] - end - attribute \src "libresoc.v:35343.3-35379.6" - process $proc$libresoc.v:35343$767 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:35344.5-35344.29" - switch \initial - attribute \src "libresoc.v:35344.9-35344.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] - end - attribute \src "libresoc.v:35380.3-35416.6" - process $proc$libresoc.v:35380$768 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:35381.5-35381.29" - switch \initial - attribute \src "libresoc.v:35381.9-35381.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 - case - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] - end - attribute \src "libresoc.v:35417.3-35453.6" - process $proc$libresoc.v:35417$769 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:35418.5-35418.29" - switch \initial - attribute \src "libresoc.v:35418.9-35418.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] - end - attribute \src "libresoc.v:35454.3-35490.6" - process $proc$libresoc.v:35454$770 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:35455.5-35455.29" - switch \initial - attribute \src "libresoc.v:35455.9-35455.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] - end - attribute \src "libresoc.v:35491.3-35527.6" - process $proc$libresoc.v:35491$771 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:35492.5-35492.29" - switch \initial - attribute \src "libresoc.v:35492.9-35492.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] - end - attribute \src "libresoc.v:35528.3-35564.6" - process $proc$libresoc.v:35528$772 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:35529.5-35529.29" - switch \initial - attribute \src "libresoc.v:35529.9-35529.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] - end - attribute \src "libresoc.v:35565.3-35601.6" - process $proc$libresoc.v:35565$773 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:35566.5-35566.29" - switch \initial - attribute \src "libresoc.v:35566.9-35566.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] - end - attribute \src "libresoc.v:35602.3-35638.6" - process $proc$libresoc.v:35602$774 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:35603.5-35603.29" - switch \initial - attribute \src "libresoc.v:35603.9-35603.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub28_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] - end - attribute \src "libresoc.v:35639.3-35675.6" - process $proc$libresoc.v:35639$775 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:35640.5-35640.29" - switch \initial - attribute \src "libresoc.v:35640.9-35640.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - case - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] - end - attribute \src "libresoc.v:35676.3-35712.6" - process $proc$libresoc.v:35676$776 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:35677.5-35677.29" - switch \initial - attribute \src "libresoc.v:35677.9-35677.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] - end - attribute \src "libresoc.v:35713.3-35749.6" - process $proc$libresoc.v:35713$777 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:35714.5-35714.29" - switch \initial - attribute \src "libresoc.v:35714.9-35714.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] - end - attribute \src "libresoc.v:35750.3-35786.6" - process $proc$libresoc.v:35750$778 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_out_sel[1:0] $1\dec31_dec_sub28_out_sel[1:0] - attribute \src "libresoc.v:35751.5-35751.29" - switch \initial - attribute \src "libresoc.v:35751.9-35751.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub28_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub28_out_sel $0\dec31_dec_sub28_out_sel[1:0] - end - attribute \src "libresoc.v:35787.3-35823.6" - process $proc$libresoc.v:35787$779 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:35788.5-35788.29" - switch \initial - attribute \src "libresoc.v:35788.9-35788.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] - end - attribute \src "libresoc.v:35824.3-35860.6" - process $proc$libresoc.v:35824$780 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:35825.5-35825.29" - switch \initial - attribute \src "libresoc.v:35825.9-35825.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:35866.1-36437.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" -attribute \generator "nMigen" -module \dec31_dec_sub4 - attribute \src "libresoc.v:36189.3-36201.6" - wire width 8 $0\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:36241.3-36253.6" - wire $0\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:36410.3-36422.6" - wire width 3 $0\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:36423.3-36435.6" - wire width 3 $0\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:36176.3-36188.6" - wire width 2 $0\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:36228.3-36240.6" - wire $0\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:36345.3-36357.6" - wire width 5 $0\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:36124.3-36136.6" - wire width 12 $0\dec31_dec_sub4_function_unit[11:0] - attribute \src "libresoc.v:36358.3-36370.6" - wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:36371.3-36383.6" - wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:36384.3-36396.6" - wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:36267.3-36279.6" - wire width 7 $0\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:36202.3-36214.6" - wire $0\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:36215.3-36227.6" - wire $0\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:36293.3-36305.6" - wire $0\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:36137.3-36149.6" - wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:36319.3-36331.6" - wire $0\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:36397.3-36409.6" - wire width 2 $0\dec31_dec_sub4_out_sel[1:0] - attribute \src "libresoc.v:36163.3-36175.6" - wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:36280.3-36292.6" - wire $0\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:36332.3-36344.6" - wire $0\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:36306.3-36318.6" - wire $0\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:36254.3-36266.6" - wire $0\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:36150.3-36162.6" - wire width 2 $0\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:35867.7-35867.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:36189.3-36201.6" - wire width 8 $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:36241.3-36253.6" - wire $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:36410.3-36422.6" - wire width 3 $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:36423.3-36435.6" - wire width 3 $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:36176.3-36188.6" - wire width 2 $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:36228.3-36240.6" - wire $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:36345.3-36357.6" - wire width 5 $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:36124.3-36136.6" - wire width 12 $1\dec31_dec_sub4_function_unit[11:0] - attribute \src "libresoc.v:36358.3-36370.6" - wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:36371.3-36383.6" - wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:36384.3-36396.6" - wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:36267.3-36279.6" - wire width 7 $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:36202.3-36214.6" - wire $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:36215.3-36227.6" - wire $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:36293.3-36305.6" - wire $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:36137.3-36149.6" - wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:36319.3-36331.6" - wire $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:36397.3-36409.6" - wire width 2 $1\dec31_dec_sub4_out_sel[1:0] - attribute \src "libresoc.v:36163.3-36175.6" - wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:36280.3-36292.6" - wire $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:36332.3-36344.6" - wire $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:36306.3-36318.6" - wire $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:36254.3-36266.6" - wire $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:36150.3-36162.6" - wire width 2 $1\dec31_dec_sub4_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub4_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub4_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub4_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub4_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub4_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub4_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub4_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub4_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub4_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub4_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub4_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub4_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub4_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub4_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub4_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub4_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub4_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub4_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub4_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub4_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub4_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub4_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub4_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub4_upd - attribute \src "libresoc.v:35867.7-35867.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "libresoc.v:35867.7-35867.20" - process $proc$libresoc.v:35867$806 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:36124.3-36136.6" - process $proc$libresoc.v:36124$782 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_function_unit[11:0] $1\dec31_dec_sub4_function_unit[11:0] - attribute \src "libresoc.v:36125.5-36125.29" - switch \initial - attribute \src "libresoc.v:36125.9-36125.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 - case - assign $1\dec31_dec_sub4_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[11:0] - end - attribute \src "libresoc.v:36137.3-36149.6" - process $proc$libresoc.v:36137$783 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:36138.5-36138.29" - switch \initial - attribute \src "libresoc.v:36138.9-36138.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] - end - attribute \src "libresoc.v:36150.3-36162.6" - process $proc$libresoc.v:36150$784 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:36151.5-36151.29" - switch \initial - attribute \src "libresoc.v:36151.9-36151.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub4_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] - end - attribute \src "libresoc.v:36163.3-36175.6" - process $proc$libresoc.v:36163$785 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:36164.5-36164.29" - switch \initial - attribute \src "libresoc.v:36164.9-36164.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] - end - attribute \src "libresoc.v:36176.3-36188.6" - process $proc$libresoc.v:36176$786 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:36177.5-36177.29" - switch \initial - attribute \src "libresoc.v:36177.9-36177.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] - end - attribute \src "libresoc.v:36189.3-36201.6" - process $proc$libresoc.v:36189$787 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:36190.5-36190.29" - switch \initial - attribute \src "libresoc.v:36190.9-36190.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001110 - case - assign $1\dec31_dec_sub4_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] - end - attribute \src "libresoc.v:36202.3-36214.6" - process $proc$libresoc.v:36202$788 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:36203.5-36203.29" - switch \initial - attribute \src "libresoc.v:36203.9-36203.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] - end - attribute \src "libresoc.v:36215.3-36227.6" - process $proc$libresoc.v:36215$789 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:36216.5-36216.29" - switch \initial - attribute \src "libresoc.v:36216.9-36216.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] - end - attribute \src "libresoc.v:36228.3-36240.6" - process $proc$libresoc.v:36228$790 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:36229.5-36229.29" - switch \initial - attribute \src "libresoc.v:36229.9-36229.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] - end - attribute \src "libresoc.v:36241.3-36253.6" - process $proc$libresoc.v:36241$791 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:36242.5-36242.29" - switch \initial - attribute \src "libresoc.v:36242.9-36242.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_br[0:0] 1'0 - case - assign $1\dec31_dec_sub4_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] - end - attribute \src "libresoc.v:36254.3-36266.6" - process $proc$libresoc.v:36254$792 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:36255.5-36255.29" - switch \initial - attribute \src "libresoc.v:36255.9-36255.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] - end - attribute \src "libresoc.v:36267.3-36279.6" - process $proc$libresoc.v:36267$793 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:36268.5-36268.29" - switch \initial - attribute \src "libresoc.v:36268.9-36268.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 - case - assign $1\dec31_dec_sub4_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] - end - attribute \src "libresoc.v:36280.3-36292.6" - process $proc$libresoc.v:36280$794 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:36281.5-36281.29" - switch \initial - attribute \src "libresoc.v:36281.9-36281.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] - end - attribute \src "libresoc.v:36293.3-36305.6" - process $proc$libresoc.v:36293$795 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:36294.5-36294.29" - switch \initial - attribute \src "libresoc.v:36294.9-36294.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_is_32b[0:0] 1'1 - case - assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] - end - attribute \src "libresoc.v:36306.3-36318.6" - process $proc$libresoc.v:36306$796 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:36307.5-36307.29" - switch \initial - attribute \src "libresoc.v:36307.9-36307.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub4_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] - end - attribute \src "libresoc.v:36319.3-36331.6" - process $proc$libresoc.v:36319$797 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:36320.5-36320.29" - switch \initial - attribute \src "libresoc.v:36320.9-36320.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub4_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] - end - attribute \src "libresoc.v:36332.3-36344.6" - process $proc$libresoc.v:36332$798 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:36333.5-36333.29" - switch \initial - attribute \src "libresoc.v:36333.9-36333.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] - end - attribute \src "libresoc.v:36345.3-36357.6" - process $proc$libresoc.v:36345$799 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:36346.5-36346.29" - switch \initial - attribute \src "libresoc.v:36346.9-36346.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub4_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] - end - attribute \src "libresoc.v:36358.3-36370.6" - process $proc$libresoc.v:36358$800 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:36359.5-36359.29" - switch \initial - attribute \src "libresoc.v:36359.9-36359.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 - case - assign $1\dec31_dec_sub4_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] - end - attribute \src "libresoc.v:36371.3-36383.6" - process $proc$libresoc.v:36371$801 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:36372.5-36372.29" - switch \initial - attribute \src "libresoc.v:36372.9-36372.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] - end - attribute \src "libresoc.v:36384.3-36396.6" - process $proc$libresoc.v:36384$802 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:36385.5-36385.29" - switch \initial - attribute \src "libresoc.v:36385.9-36385.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] - end - attribute \src "libresoc.v:36397.3-36409.6" - process $proc$libresoc.v:36397$803 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_out_sel[1:0] $1\dec31_dec_sub4_out_sel[1:0] - attribute \src "libresoc.v:36398.5-36398.29" - switch \initial - attribute \src "libresoc.v:36398.9-36398.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub4_out_sel $0\dec31_dec_sub4_out_sel[1:0] - end - attribute \src "libresoc.v:36410.3-36422.6" - process $proc$libresoc.v:36410$804 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:36411.5-36411.29" - switch \initial - attribute \src "libresoc.v:36411.9-36411.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] - end - attribute \src "libresoc.v:36423.3-36435.6" - process $proc$libresoc.v:36423$805 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:36424.5-36424.29" - switch \initial - attribute \src "libresoc.v:36424.9-36424.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:36441.1-37732.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" -attribute \generator "nMigen" -module \dec31_dec_sub8 - attribute \src "libresoc.v:36914.3-36956.6" - wire width 8 $0\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:37086.3-37128.6" - wire $0\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:37645.3-37687.6" - wire width 3 $0\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:37688.3-37730.6" - wire width 3 $0\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:36871.3-36913.6" - wire width 2 $0\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:37043.3-37085.6" - wire $0\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:37430.3-37472.6" - wire width 5 $0\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:36699.3-36741.6" - wire width 12 $0\dec31_dec_sub8_function_unit[11:0] - attribute \src "libresoc.v:37473.3-37515.6" - wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:37516.3-37558.6" - wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:37559.3-37601.6" - wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:37172.3-37214.6" - wire width 7 $0\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:36957.3-36999.6" - wire $0\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:37000.3-37042.6" - wire $0\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:37258.3-37300.6" - wire $0\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:36742.3-36784.6" - wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:37344.3-37386.6" - wire $0\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:37602.3-37644.6" - wire width 2 $0\dec31_dec_sub8_out_sel[1:0] - attribute \src "libresoc.v:36828.3-36870.6" - wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:37215.3-37257.6" - wire $0\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:37387.3-37429.6" - wire $0\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:37301.3-37343.6" - wire $0\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:37129.3-37171.6" - wire $0\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:36785.3-36827.6" - wire width 2 $0\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:36442.7-36442.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:36914.3-36956.6" - wire width 8 $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:37086.3-37128.6" - wire $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:37645.3-37687.6" - wire width 3 $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:37688.3-37730.6" - wire width 3 $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:36871.3-36913.6" - wire width 2 $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:37043.3-37085.6" - wire $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:37430.3-37472.6" - wire width 5 $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:36699.3-36741.6" - wire width 12 $1\dec31_dec_sub8_function_unit[11:0] - attribute \src "libresoc.v:37473.3-37515.6" - wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:37516.3-37558.6" - wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:37559.3-37601.6" - wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:37172.3-37214.6" - wire width 7 $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:36957.3-36999.6" - wire $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:37000.3-37042.6" - wire $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:37258.3-37300.6" - wire $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:36742.3-36784.6" - wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:37344.3-37386.6" - wire $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:37602.3-37644.6" - wire width 2 $1\dec31_dec_sub8_out_sel[1:0] - attribute \src "libresoc.v:36828.3-36870.6" - wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:37215.3-37257.6" - wire $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:37387.3-37429.6" - wire $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:37301.3-37343.6" - wire $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:37129.3-37171.6" - wire $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:36785.3-36827.6" - wire width 2 $1\dec31_dec_sub8_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub8_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub8_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub8_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub8_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub8_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub8_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub8_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub8_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub8_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub8_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub8_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub8_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub8_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub8_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub8_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub8_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub8_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub8_upd - attribute \src "libresoc.v:36442.7-36442.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "libresoc.v:36442.7-36442.20" - process $proc$libresoc.v:36442$831 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:36699.3-36741.6" - process $proc$libresoc.v:36699$807 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_function_unit[11:0] $1\dec31_dec_sub8_function_unit[11:0] - attribute \src "libresoc.v:36700.5-36700.29" - switch \initial - attribute \src "libresoc.v:36700.9-36700.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - case - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[11:0] - end - attribute \src "libresoc.v:36742.3-36784.6" - process $proc$libresoc.v:36742$808 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:36743.5-36743.29" - switch \initial - attribute \src "libresoc.v:36743.9-36743.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] - end - attribute \src "libresoc.v:36785.3-36827.6" - process $proc$libresoc.v:36785$809 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:36786.5-36786.29" - switch \initial - attribute \src "libresoc.v:36786.9-36786.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] - end - attribute \src "libresoc.v:36828.3-36870.6" - process $proc$libresoc.v:36828$810 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:36829.5-36829.29" - switch \initial - attribute \src "libresoc.v:36829.9-36829.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] - end - attribute \src "libresoc.v:36871.3-36913.6" - process $proc$libresoc.v:36871$811 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:36872.5-36872.29" - switch \initial - attribute \src "libresoc.v:36872.9-36872.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - case - assign $1\dec31_dec_sub8_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] - end - attribute \src "libresoc.v:36914.3-36956.6" - process $proc$libresoc.v:36914$812 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:36915.5-36915.29" - switch \initial - attribute \src "libresoc.v:36915.9-36915.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111111 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000111 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11001000 - case - assign $1\dec31_dec_sub8_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] - end - attribute \src "libresoc.v:36957.3-36999.6" - process $proc$libresoc.v:36957$813 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:36958.5-36958.29" - switch \initial - attribute \src "libresoc.v:36958.9-36958.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - case - assign $1\dec31_dec_sub8_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] - end - attribute \src "libresoc.v:37000.3-37042.6" - process $proc$libresoc.v:37000$814 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:37001.5-37001.29" - switch \initial - attribute \src "libresoc.v:37001.9-37001.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] - end - attribute \src "libresoc.v:37043.3-37085.6" - process $proc$libresoc.v:37043$815 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:37044.5-37044.29" - switch \initial - attribute \src "libresoc.v:37044.9-37044.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - case - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] - end - attribute \src "libresoc.v:37086.3-37128.6" - process $proc$libresoc.v:37086$816 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:37087.5-37087.29" - switch \initial - attribute \src "libresoc.v:37087.9-37087.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - case - assign $1\dec31_dec_sub8_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] - end - attribute \src "libresoc.v:37129.3-37171.6" - process $proc$libresoc.v:37129$817 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:37130.5-37130.29" - switch \initial - attribute \src "libresoc.v:37130.9-37130.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] - end - attribute \src "libresoc.v:37172.3-37214.6" - process $proc$libresoc.v:37172$818 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:37173.5-37173.29" - switch \initial - attribute \src "libresoc.v:37173.9-37173.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - case - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] - end - attribute \src "libresoc.v:37215.3-37257.6" - process $proc$libresoc.v:37215$819 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:37216.5-37216.29" - switch \initial - attribute \src "libresoc.v:37216.9-37216.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] - end - attribute \src "libresoc.v:37258.3-37300.6" - process $proc$libresoc.v:37258$820 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:37259.5-37259.29" - switch \initial - attribute \src "libresoc.v:37259.9-37259.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] - end - attribute \src "libresoc.v:37301.3-37343.6" - process $proc$libresoc.v:37301$821 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:37302.5-37302.29" - switch \initial - attribute \src "libresoc.v:37302.9-37302.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] - end - attribute \src "libresoc.v:37344.3-37386.6" - process $proc$libresoc.v:37344$822 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:37345.5-37345.29" - switch \initial - attribute \src "libresoc.v:37345.9-37345.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] - end - attribute \src "libresoc.v:37387.3-37429.6" - process $proc$libresoc.v:37387$823 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:37388.5-37388.29" - switch \initial - attribute \src "libresoc.v:37388.9-37388.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] - end - attribute \src "libresoc.v:37430.3-37472.6" - process $proc$libresoc.v:37430$824 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:37431.5-37431.29" - switch \initial - attribute \src "libresoc.v:37431.9-37431.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - case - assign $1\dec31_dec_sub8_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] - end - attribute \src "libresoc.v:37473.3-37515.6" - process $proc$libresoc.v:37473$825 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:37474.5-37474.29" - switch \initial - attribute \src "libresoc.v:37474.9-37474.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - case - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] - end - attribute \src "libresoc.v:37516.3-37558.6" - process $proc$libresoc.v:37516$826 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:37517.5-37517.29" - switch \initial - attribute \src "libresoc.v:37517.9-37517.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 - case - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] - end - attribute \src "libresoc.v:37559.3-37601.6" - process $proc$libresoc.v:37559$827 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:37560.5-37560.29" - switch \initial - attribute \src "libresoc.v:37560.9-37560.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] - end - attribute \src "libresoc.v:37602.3-37644.6" - process $proc$libresoc.v:37602$828 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_out_sel[1:0] $1\dec31_dec_sub8_out_sel[1:0] - attribute \src "libresoc.v:37603.5-37603.29" - switch \initial - attribute \src "libresoc.v:37603.9-37603.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub8_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub8_out_sel $0\dec31_dec_sub8_out_sel[1:0] - end - attribute \src "libresoc.v:37645.3-37687.6" - process $proc$libresoc.v:37645$829 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:37646.5-37646.29" - switch \initial - attribute \src "libresoc.v:37646.9-37646.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] - end - attribute \src "libresoc.v:37688.3-37730.6" - process $proc$libresoc.v:37688$830 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:37689.5-37689.29" - switch \initial - attribute \src "libresoc.v:37689.9-37689.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:37736.1-39315.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" -attribute \generator "nMigen" -module \dec31_dec_sub9 - attribute \src "libresoc.v:38269.3-38323.6" - wire width 8 $0\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:38489.3-38543.6" - wire $0\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:39204.3-39258.6" - wire width 3 $0\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:39259.3-39313.6" - wire width 3 $0\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:38214.3-38268.6" - wire width 2 $0\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:38434.3-38488.6" - wire $0\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:38929.3-38983.6" - wire width 5 $0\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:37994.3-38048.6" - wire width 12 $0\dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:38984.3-39038.6" - wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:39039.3-39093.6" - wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:39094.3-39148.6" - wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:38599.3-38653.6" - wire width 7 $0\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:38324.3-38378.6" - wire $0\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:38379.3-38433.6" - wire $0\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:38709.3-38763.6" - wire $0\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:38049.3-38103.6" - wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:38819.3-38873.6" - wire $0\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:39149.3-39203.6" - wire width 2 $0\dec31_dec_sub9_out_sel[1:0] - attribute \src "libresoc.v:38159.3-38213.6" - wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:38654.3-38708.6" - wire $0\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:38874.3-38928.6" - wire $0\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:38764.3-38818.6" - wire $0\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:38544.3-38598.6" - wire $0\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:38104.3-38158.6" - wire width 2 $0\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:37737.7-37737.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:38269.3-38323.6" - wire width 8 $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:38489.3-38543.6" - wire $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:39204.3-39258.6" - wire width 3 $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:39259.3-39313.6" - wire width 3 $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:38214.3-38268.6" - wire width 2 $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:38434.3-38488.6" - wire $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:38929.3-38983.6" - wire width 5 $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:37994.3-38048.6" - wire width 12 $1\dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:38984.3-39038.6" - wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:39039.3-39093.6" - wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:39094.3-39148.6" - wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:38599.3-38653.6" - wire width 7 $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:38324.3-38378.6" - wire $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:38379.3-38433.6" - wire $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:38709.3-38763.6" - wire $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:38049.3-38103.6" - wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:38819.3-38873.6" - wire $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:39149.3-39203.6" - wire width 2 $1\dec31_dec_sub9_out_sel[1:0] - attribute \src "libresoc.v:38159.3-38213.6" - wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:38654.3-38708.6" - wire $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:38874.3-38928.6" - wire $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:38764.3-38818.6" - wire $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:38544.3-38598.6" - wire $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:38104.3-38158.6" - wire width 2 $1\dec31_dec_sub9_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub9_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub9_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub9_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub9_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub9_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub9_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub9_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub9_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub9_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub9_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub9_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub9_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub9_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub9_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub9_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub9_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub9_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub9_upd - attribute \src "libresoc.v:37737.7-37737.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "libresoc.v:37737.7-37737.20" - process $proc$libresoc.v:37737$856 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:37994.3-38048.6" - process $proc$libresoc.v:37994$832 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_function_unit[11:0] $1\dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:37995.5-37995.29" - switch \initial - attribute \src "libresoc.v:37995.9-37995.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - case - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[11:0] - end - attribute \src "libresoc.v:38049.3-38103.6" - process $proc$libresoc.v:38049$833 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:38050.5-38050.29" - switch \initial - attribute \src "libresoc.v:38050.9-38050.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] - end - attribute \src "libresoc.v:38104.3-38158.6" - process $proc$libresoc.v:38104$834 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:38105.5-38105.29" - switch \initial - attribute \src "libresoc.v:38105.9-38105.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] - end - attribute \src "libresoc.v:38159.3-38213.6" - process $proc$libresoc.v:38159$835 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:38160.5-38160.29" - switch \initial - attribute \src "libresoc.v:38160.9-38160.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] - end - attribute \src "libresoc.v:38214.3-38268.6" - process $proc$libresoc.v:38214$836 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:38215.5-38215.29" - switch \initial - attribute \src "libresoc.v:38215.9-38215.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] - end - attribute \src "libresoc.v:38269.3-38323.6" - process $proc$libresoc.v:38269$837 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:38270.5-38270.29" - switch \initial - attribute \src "libresoc.v:38270.9-38270.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111111 - case - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] - end - attribute \src "libresoc.v:38324.3-38378.6" - process $proc$libresoc.v:38324$838 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:38325.5-38325.29" - switch \initial - attribute \src "libresoc.v:38325.9-38325.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] - end - attribute \src "libresoc.v:38379.3-38433.6" - process $proc$libresoc.v:38379$839 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:38380.5-38380.29" - switch \initial - attribute \src "libresoc.v:38380.9-38380.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] - end - attribute \src "libresoc.v:38434.3-38488.6" - process $proc$libresoc.v:38434$840 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:38435.5-38435.29" - switch \initial - attribute \src "libresoc.v:38435.9-38435.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] - end - attribute \src "libresoc.v:38489.3-38543.6" - process $proc$libresoc.v:38489$841 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:38490.5-38490.29" - switch \initial - attribute \src "libresoc.v:38490.9-38490.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - case - assign $1\dec31_dec_sub9_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] - end - attribute \src "libresoc.v:38544.3-38598.6" - process $proc$libresoc.v:38544$842 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:38545.5-38545.29" - switch \initial - attribute \src "libresoc.v:38545.9-38545.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] - end - attribute \src "libresoc.v:38599.3-38653.6" - process $proc$libresoc.v:38599$843 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:38600.5-38600.29" - switch \initial - attribute \src "libresoc.v:38600.9-38600.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 - case - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] - end - attribute \src "libresoc.v:38654.3-38708.6" - process $proc$libresoc.v:38654$844 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:38655.5-38655.29" - switch \initial - attribute \src "libresoc.v:38655.9-38655.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] - end - attribute \src "libresoc.v:38709.3-38763.6" - process $proc$libresoc.v:38709$845 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:38710.5-38710.29" - switch \initial - attribute \src "libresoc.v:38710.9-38710.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] - end - attribute \src "libresoc.v:38764.3-38818.6" - process $proc$libresoc.v:38764$846 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:38765.5-38765.29" - switch \initial - attribute \src "libresoc.v:38765.9-38765.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - case - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] - end - attribute \src "libresoc.v:38819.3-38873.6" - process $proc$libresoc.v:38819$847 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:38820.5-38820.29" - switch \initial - attribute \src "libresoc.v:38820.9-38820.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] - end - attribute \src "libresoc.v:38874.3-38928.6" - process $proc$libresoc.v:38874$848 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:38875.5-38875.29" - switch \initial - attribute \src "libresoc.v:38875.9-38875.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] - end - attribute \src "libresoc.v:38929.3-38983.6" - process $proc$libresoc.v:38929$849 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:38930.5-38930.29" - switch \initial - attribute \src "libresoc.v:38930.9-38930.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - case - assign $1\dec31_dec_sub9_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] - end - attribute \src "libresoc.v:38984.3-39038.6" - process $proc$libresoc.v:38984$850 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:38985.5-38985.29" - switch \initial - attribute \src "libresoc.v:38985.9-38985.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - case - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] - end - attribute \src "libresoc.v:39039.3-39093.6" - process $proc$libresoc.v:39039$851 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:39040.5-39040.29" - switch \initial - attribute \src "libresoc.v:39040.9-39040.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] - end - attribute \src "libresoc.v:39094.3-39148.6" - process $proc$libresoc.v:39094$852 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:39095.5-39095.29" - switch \initial - attribute \src "libresoc.v:39095.9-39095.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] - end - attribute \src "libresoc.v:39149.3-39203.6" - process $proc$libresoc.v:39149$853 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_out_sel[1:0] $1\dec31_dec_sub9_out_sel[1:0] - attribute \src "libresoc.v:39150.5-39150.29" - switch \initial - attribute \src "libresoc.v:39150.9-39150.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub9_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub9_out_sel $0\dec31_dec_sub9_out_sel[1:0] - end - attribute \src "libresoc.v:39204.3-39258.6" - process $proc$libresoc.v:39204$854 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:39205.5-39205.29" - switch \initial - attribute \src "libresoc.v:39205.9-39205.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] - end - attribute \src "libresoc.v:39259.3-39313.6" - process $proc$libresoc.v:39259$855 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:39260.5-39260.29" - switch \initial - attribute \src "libresoc.v:39260.9-39260.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:39319.1-39962.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58" -attribute \generator "nMigen" -module \dec58 - attribute \src "libresoc.v:39657.3-39672.6" - wire width 8 $0\dec58_asmcode[7:0] - attribute \src "libresoc.v:39721.3-39736.6" - wire $0\dec58_br[0:0] - attribute \src "libresoc.v:39929.3-39944.6" - wire width 3 $0\dec58_cr_in[2:0] - attribute \src "libresoc.v:39945.3-39960.6" - wire width 3 $0\dec58_cr_out[2:0] - attribute \src "libresoc.v:39641.3-39656.6" - wire width 2 $0\dec58_cry_in[1:0] - attribute \src "libresoc.v:39705.3-39720.6" - wire $0\dec58_cry_out[0:0] - attribute \src "libresoc.v:39849.3-39864.6" - wire width 5 $0\dec58_form[4:0] - attribute \src "libresoc.v:39577.3-39592.6" - wire width 12 $0\dec58_function_unit[11:0] - attribute \src "libresoc.v:39865.3-39880.6" - wire width 3 $0\dec58_in1_sel[2:0] - attribute \src "libresoc.v:39881.3-39896.6" - wire width 4 $0\dec58_in2_sel[3:0] - attribute \src "libresoc.v:39897.3-39912.6" - wire width 2 $0\dec58_in3_sel[1:0] - attribute \src "libresoc.v:39753.3-39768.6" - wire width 7 $0\dec58_internal_op[6:0] - attribute \src "libresoc.v:39673.3-39688.6" - wire $0\dec58_inv_a[0:0] - attribute \src "libresoc.v:39689.3-39704.6" - wire $0\dec58_inv_out[0:0] - attribute \src "libresoc.v:39785.3-39800.6" - wire $0\dec58_is_32b[0:0] - attribute \src "libresoc.v:39593.3-39608.6" - wire width 4 $0\dec58_ldst_len[3:0] - attribute \src "libresoc.v:39817.3-39832.6" - wire $0\dec58_lk[0:0] - attribute \src "libresoc.v:39913.3-39928.6" - wire width 2 $0\dec58_out_sel[1:0] - attribute \src "libresoc.v:39625.3-39640.6" - wire width 2 $0\dec58_rc_sel[1:0] - attribute \src "libresoc.v:39769.3-39784.6" - wire $0\dec58_rsrv[0:0] - attribute \src "libresoc.v:39833.3-39848.6" - wire $0\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:39801.3-39816.6" - wire $0\dec58_sgn[0:0] - attribute \src "libresoc.v:39737.3-39752.6" - wire $0\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:39609.3-39624.6" - wire width 2 $0\dec58_upd[1:0] - attribute \src "libresoc.v:39320.7-39320.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:39657.3-39672.6" - wire width 8 $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:39721.3-39736.6" - wire $1\dec58_br[0:0] - attribute \src "libresoc.v:39929.3-39944.6" - wire width 3 $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:39945.3-39960.6" - wire width 3 $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:39641.3-39656.6" - wire width 2 $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:39705.3-39720.6" - wire $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:39849.3-39864.6" - wire width 5 $1\dec58_form[4:0] - attribute \src "libresoc.v:39577.3-39592.6" - wire width 12 $1\dec58_function_unit[11:0] - attribute \src "libresoc.v:39865.3-39880.6" - wire width 3 $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:39881.3-39896.6" - wire width 4 $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:39897.3-39912.6" - wire width 2 $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:39753.3-39768.6" - wire width 7 $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:39673.3-39688.6" - wire $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:39689.3-39704.6" - wire $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:39785.3-39800.6" - wire $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:39593.3-39608.6" - wire width 4 $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:39817.3-39832.6" - wire $1\dec58_lk[0:0] - attribute \src "libresoc.v:39913.3-39928.6" - wire width 2 $1\dec58_out_sel[1:0] - attribute \src "libresoc.v:39625.3-39640.6" - wire width 2 $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:39769.3-39784.6" - wire $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:39833.3-39848.6" - wire $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:39801.3-39816.6" - wire $1\dec58_sgn[0:0] - attribute \src "libresoc.v:39737.3-39752.6" - wire $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:39609.3-39624.6" - wire width 2 $1\dec58_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec58_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec58_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec58_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec58_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec58_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec58_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec58_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec58_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec58_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec58_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec58_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec58_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec58_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec58_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec58_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec58_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec58_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec58_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec58_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec58_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec58_upd - attribute \src "libresoc.v:39320.7-39320.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 2 \opcode_switch - attribute \src "libresoc.v:39320.7-39320.20" - process $proc$libresoc.v:39320$881 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:39577.3-39592.6" - process $proc$libresoc.v:39577$857 - assign { } { } - assign { } { } - assign $0\dec58_function_unit[11:0] $1\dec58_function_unit[11:0] - attribute \src "libresoc.v:39578.5-39578.29" - switch \initial - attribute \src "libresoc.v:39578.9-39578.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_function_unit[11:0] 12'000000000100 - case - assign $1\dec58_function_unit[11:0] 12'000000000000 - end - sync always - update \dec58_function_unit $0\dec58_function_unit[11:0] - end - attribute \src "libresoc.v:39593.3-39608.6" - process $proc$libresoc.v:39593$858 - assign { } { } - assign { } { } - assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:39594.5-39594.29" - switch \initial - attribute \src "libresoc.v:39594.9-39594.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_ldst_len[3:0] 4'0100 - case - assign $1\dec58_ldst_len[3:0] 4'0000 - end - sync always - update \dec58_ldst_len $0\dec58_ldst_len[3:0] - end - attribute \src "libresoc.v:39609.3-39624.6" - process $proc$libresoc.v:39609$859 - assign { } { } - assign { } { } - assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] - attribute \src "libresoc.v:39610.5-39610.29" - switch \initial - attribute \src "libresoc.v:39610.9-39610.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_upd[1:0] 2'00 - case - assign $1\dec58_upd[1:0] 2'00 - end - sync always - update \dec58_upd $0\dec58_upd[1:0] - end - attribute \src "libresoc.v:39625.3-39640.6" - process $proc$libresoc.v:39625$860 - assign { } { } - assign { } { } - assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:39626.5-39626.29" - switch \initial - attribute \src "libresoc.v:39626.9-39626.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_rc_sel[1:0] 2'00 - case - assign $1\dec58_rc_sel[1:0] 2'00 - end - sync always - update \dec58_rc_sel $0\dec58_rc_sel[1:0] - end - attribute \src "libresoc.v:39641.3-39656.6" - process $proc$libresoc.v:39641$861 - assign { } { } - assign { } { } - assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:39642.5-39642.29" - switch \initial - attribute \src "libresoc.v:39642.9-39642.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_cry_in[1:0] 2'00 - case - assign $1\dec58_cry_in[1:0] 2'00 - end - sync always - update \dec58_cry_in $0\dec58_cry_in[1:0] - end - attribute \src "libresoc.v:39657.3-39672.6" - process $proc$libresoc.v:39657$862 - assign { } { } - assign { } { } - assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:39658.5-39658.29" - switch \initial - attribute \src "libresoc.v:39658.9-39658.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_asmcode[7:0] 8'01010010 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_asmcode[7:0] 8'01010101 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_asmcode[7:0] 8'01100010 - case - assign $1\dec58_asmcode[7:0] 8'00000000 - end - sync always - update \dec58_asmcode $0\dec58_asmcode[7:0] - end - attribute \src "libresoc.v:39673.3-39688.6" - process $proc$libresoc.v:39673$863 - assign { } { } - assign { } { } - assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:39674.5-39674.29" - switch \initial - attribute \src "libresoc.v:39674.9-39674.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_inv_a[0:0] 1'0 - case - assign $1\dec58_inv_a[0:0] 1'0 - end - sync always - update \dec58_inv_a $0\dec58_inv_a[0:0] - end - attribute \src "libresoc.v:39689.3-39704.6" - process $proc$libresoc.v:39689$864 - assign { } { } - assign { } { } - assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:39690.5-39690.29" - switch \initial - attribute \src "libresoc.v:39690.9-39690.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_inv_out[0:0] 1'0 - case - assign $1\dec58_inv_out[0:0] 1'0 - end - sync always - update \dec58_inv_out $0\dec58_inv_out[0:0] - end - attribute \src "libresoc.v:39705.3-39720.6" - process $proc$libresoc.v:39705$865 - assign { } { } - assign { } { } - assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:39706.5-39706.29" - switch \initial - attribute \src "libresoc.v:39706.9-39706.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_cry_out[0:0] 1'0 - case - assign $1\dec58_cry_out[0:0] 1'0 - end - sync always - update \dec58_cry_out $0\dec58_cry_out[0:0] - end - attribute \src "libresoc.v:39721.3-39736.6" - process $proc$libresoc.v:39721$866 - assign { } { } - assign { } { } - assign $0\dec58_br[0:0] $1\dec58_br[0:0] - attribute \src "libresoc.v:39722.5-39722.29" - switch \initial - attribute \src "libresoc.v:39722.9-39722.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_br[0:0] 1'0 - case - assign $1\dec58_br[0:0] 1'0 - end - sync always - update \dec58_br $0\dec58_br[0:0] - end - attribute \src "libresoc.v:39737.3-39752.6" - process $proc$libresoc.v:39737$867 - assign { } { } - assign { } { } - assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:39738.5-39738.29" - switch \initial - attribute \src "libresoc.v:39738.9-39738.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_sgn_ext[0:0] 1'1 - case - assign $1\dec58_sgn_ext[0:0] 1'0 - end - sync always - update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] - end - attribute \src "libresoc.v:39753.3-39768.6" - process $proc$libresoc.v:39753$868 - assign { } { } - assign { } { } - assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:39754.5-39754.29" - switch \initial - attribute \src "libresoc.v:39754.9-39754.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_internal_op[6:0] 7'0100101 - case - assign $1\dec58_internal_op[6:0] 7'0000000 - end - sync always - update \dec58_internal_op $0\dec58_internal_op[6:0] - end - attribute \src "libresoc.v:39769.3-39784.6" - process $proc$libresoc.v:39769$869 - assign { } { } - assign { } { } - assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:39770.5-39770.29" - switch \initial - attribute \src "libresoc.v:39770.9-39770.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_rsrv[0:0] 1'0 - case - assign $1\dec58_rsrv[0:0] 1'0 - end - sync always - update \dec58_rsrv $0\dec58_rsrv[0:0] - end - attribute \src "libresoc.v:39785.3-39800.6" - process $proc$libresoc.v:39785$870 - assign { } { } - assign { } { } - assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:39786.5-39786.29" - switch \initial - attribute \src "libresoc.v:39786.9-39786.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_is_32b[0:0] 1'0 - case - assign $1\dec58_is_32b[0:0] 1'0 - end - sync always - update \dec58_is_32b $0\dec58_is_32b[0:0] - end - attribute \src "libresoc.v:39801.3-39816.6" - process $proc$libresoc.v:39801$871 - assign { } { } - assign { } { } - assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] - attribute \src "libresoc.v:39802.5-39802.29" - switch \initial - attribute \src "libresoc.v:39802.9-39802.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_sgn[0:0] 1'0 - case - assign $1\dec58_sgn[0:0] 1'0 - end - sync always - update \dec58_sgn $0\dec58_sgn[0:0] - end - attribute \src "libresoc.v:39817.3-39832.6" - process $proc$libresoc.v:39817$872 - assign { } { } - assign { } { } - assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] - attribute \src "libresoc.v:39818.5-39818.29" - switch \initial - attribute \src "libresoc.v:39818.9-39818.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_lk[0:0] 1'0 - case - assign $1\dec58_lk[0:0] 1'0 - end - sync always - update \dec58_lk $0\dec58_lk[0:0] - end - attribute \src "libresoc.v:39833.3-39848.6" - process $proc$libresoc.v:39833$873 - assign { } { } - assign { } { } - assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:39834.5-39834.29" - switch \initial - attribute \src "libresoc.v:39834.9-39834.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_sgl_pipe[0:0] 1'1 - case - assign $1\dec58_sgl_pipe[0:0] 1'0 - end - sync always - update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] - end - attribute \src "libresoc.v:39849.3-39864.6" - process $proc$libresoc.v:39849$874 - assign { } { } - assign { } { } - assign $0\dec58_form[4:0] $1\dec58_form[4:0] - attribute \src "libresoc.v:39850.5-39850.29" - switch \initial - attribute \src "libresoc.v:39850.9-39850.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_form[4:0] 5'00101 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_form[4:0] 5'00101 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_form[4:0] 5'00101 - case - assign $1\dec58_form[4:0] 5'00000 - end - sync always - update \dec58_form $0\dec58_form[4:0] - end - attribute \src "libresoc.v:39865.3-39880.6" - process $proc$libresoc.v:39865$875 - assign { } { } - assign { } { } - assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:39866.5-39866.29" - switch \initial - attribute \src "libresoc.v:39866.9-39866.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_in1_sel[2:0] 3'010 - case - assign $1\dec58_in1_sel[2:0] 3'000 - end - sync always - update \dec58_in1_sel $0\dec58_in1_sel[2:0] - end - attribute \src "libresoc.v:39881.3-39896.6" - process $proc$libresoc.v:39881$876 - assign { } { } - assign { } { } - assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:39882.5-39882.29" - switch \initial - attribute \src "libresoc.v:39882.9-39882.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_in2_sel[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_in2_sel[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_in2_sel[3:0] 4'1000 - case - assign $1\dec58_in2_sel[3:0] 4'0000 - end - sync always - update \dec58_in2_sel $0\dec58_in2_sel[3:0] - end - attribute \src "libresoc.v:39897.3-39912.6" - process $proc$libresoc.v:39897$877 - assign { } { } - assign { } { } - assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:39898.5-39898.29" - switch \initial - attribute \src "libresoc.v:39898.9-39898.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_in3_sel[1:0] 2'00 - case - assign $1\dec58_in3_sel[1:0] 2'00 - end - sync always - update \dec58_in3_sel $0\dec58_in3_sel[1:0] - end - attribute \src "libresoc.v:39913.3-39928.6" - process $proc$libresoc.v:39913$878 - assign { } { } - assign { } { } - assign $0\dec58_out_sel[1:0] $1\dec58_out_sel[1:0] - attribute \src "libresoc.v:39914.5-39914.29" - switch \initial - attribute \src "libresoc.v:39914.9-39914.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_out_sel[1:0] 2'01 - case - assign $1\dec58_out_sel[1:0] 2'00 - end - sync always - update \dec58_out_sel $0\dec58_out_sel[1:0] - end - attribute \src "libresoc.v:39929.3-39944.6" - process $proc$libresoc.v:39929$879 - assign { } { } - assign { } { } - assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:39930.5-39930.29" - switch \initial - attribute \src "libresoc.v:39930.9-39930.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_cr_in[2:0] 3'000 - case - assign $1\dec58_cr_in[2:0] 3'000 - end - sync always - update \dec58_cr_in $0\dec58_cr_in[2:0] - end - attribute \src "libresoc.v:39945.3-39960.6" - process $proc$libresoc.v:39945$880 - assign { } { } - assign { } { } - assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:39946.5-39946.29" - switch \initial - attribute \src "libresoc.v:39946.9-39946.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_cr_out[2:0] 3'000 - case - assign $1\dec58_cr_out[2:0] 3'000 - end - sync always - update \dec58_cr_out $0\dec58_cr_out[2:0] - end - connect \opcode_switch \opcode_in [1:0] -end -attribute \src "libresoc.v:39966.1-40537.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62" -attribute \generator "nMigen" -module \dec62 - attribute \src "libresoc.v:40289.3-40301.6" - wire width 8 $0\dec62_asmcode[7:0] - attribute \src "libresoc.v:40341.3-40353.6" - wire $0\dec62_br[0:0] - attribute \src "libresoc.v:40510.3-40522.6" - wire width 3 $0\dec62_cr_in[2:0] - attribute \src "libresoc.v:40523.3-40535.6" - wire width 3 $0\dec62_cr_out[2:0] - attribute \src "libresoc.v:40276.3-40288.6" - wire width 2 $0\dec62_cry_in[1:0] - attribute \src "libresoc.v:40328.3-40340.6" - wire $0\dec62_cry_out[0:0] - attribute \src "libresoc.v:40445.3-40457.6" - wire width 5 $0\dec62_form[4:0] - attribute \src "libresoc.v:40224.3-40236.6" - wire width 12 $0\dec62_function_unit[11:0] - attribute \src "libresoc.v:40458.3-40470.6" - wire width 3 $0\dec62_in1_sel[2:0] - attribute \src "libresoc.v:40471.3-40483.6" - wire width 4 $0\dec62_in2_sel[3:0] - attribute \src "libresoc.v:40484.3-40496.6" - wire width 2 $0\dec62_in3_sel[1:0] - attribute \src "libresoc.v:40367.3-40379.6" - wire width 7 $0\dec62_internal_op[6:0] - attribute \src "libresoc.v:40302.3-40314.6" - wire $0\dec62_inv_a[0:0] - attribute \src "libresoc.v:40315.3-40327.6" - wire $0\dec62_inv_out[0:0] - attribute \src "libresoc.v:40393.3-40405.6" - wire $0\dec62_is_32b[0:0] - attribute \src "libresoc.v:40237.3-40249.6" - wire width 4 $0\dec62_ldst_len[3:0] - attribute \src "libresoc.v:40419.3-40431.6" - wire $0\dec62_lk[0:0] - attribute \src "libresoc.v:40497.3-40509.6" - wire width 2 $0\dec62_out_sel[1:0] - attribute \src "libresoc.v:40263.3-40275.6" - wire width 2 $0\dec62_rc_sel[1:0] - attribute \src "libresoc.v:40380.3-40392.6" - wire $0\dec62_rsrv[0:0] - attribute \src "libresoc.v:40432.3-40444.6" - wire $0\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:40406.3-40418.6" - wire $0\dec62_sgn[0:0] - attribute \src "libresoc.v:40354.3-40366.6" - wire $0\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:40250.3-40262.6" - wire width 2 $0\dec62_upd[1:0] - attribute \src "libresoc.v:39967.7-39967.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:40289.3-40301.6" - wire width 8 $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:40341.3-40353.6" - wire $1\dec62_br[0:0] - attribute \src "libresoc.v:40510.3-40522.6" - wire width 3 $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:40523.3-40535.6" - wire width 3 $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:40276.3-40288.6" - wire width 2 $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:40328.3-40340.6" - wire $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:40445.3-40457.6" - wire width 5 $1\dec62_form[4:0] - attribute \src "libresoc.v:40224.3-40236.6" - wire width 12 $1\dec62_function_unit[11:0] - attribute \src "libresoc.v:40458.3-40470.6" - wire width 3 $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:40471.3-40483.6" - wire width 4 $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:40484.3-40496.6" - wire width 2 $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:40367.3-40379.6" - wire width 7 $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:40302.3-40314.6" - wire $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:40315.3-40327.6" - wire $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:40393.3-40405.6" - wire $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:40237.3-40249.6" - wire width 4 $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:40419.3-40431.6" - wire $1\dec62_lk[0:0] - attribute \src "libresoc.v:40497.3-40509.6" - wire width 2 $1\dec62_out_sel[1:0] - attribute \src "libresoc.v:40263.3-40275.6" - wire width 2 $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:40380.3-40392.6" - wire $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:40432.3-40444.6" - wire $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:40406.3-40418.6" - wire $1\dec62_sgn[0:0] - attribute \src "libresoc.v:40354.3-40366.6" - wire $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:40250.3-40262.6" - wire width 2 $1\dec62_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec62_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec62_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec62_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec62_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec62_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec62_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec62_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec62_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec62_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec62_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec62_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec62_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec62_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec62_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec62_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec62_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec62_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec62_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec62_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec62_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec62_upd - attribute \src "libresoc.v:39967.7-39967.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 2 \opcode_switch - attribute \src "libresoc.v:39967.7-39967.20" - process $proc$libresoc.v:39967$906 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:40224.3-40236.6" - process $proc$libresoc.v:40224$882 - assign { } { } - assign { } { } - assign $0\dec62_function_unit[11:0] $1\dec62_function_unit[11:0] - attribute \src "libresoc.v:40225.5-40225.29" - switch \initial - attribute \src "libresoc.v:40225.9-40225.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_function_unit[11:0] 12'000000000100 - case - assign $1\dec62_function_unit[11:0] 12'000000000000 - end - sync always - update \dec62_function_unit $0\dec62_function_unit[11:0] - end - attribute \src "libresoc.v:40237.3-40249.6" - process $proc$libresoc.v:40237$883 - assign { } { } - assign { } { } - assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:40238.5-40238.29" - switch \initial - attribute \src "libresoc.v:40238.9-40238.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_ldst_len[3:0] 4'1000 - case - assign $1\dec62_ldst_len[3:0] 4'0000 - end - sync always - update \dec62_ldst_len $0\dec62_ldst_len[3:0] - end - attribute \src "libresoc.v:40250.3-40262.6" - process $proc$libresoc.v:40250$884 - assign { } { } - assign { } { } - assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] - attribute \src "libresoc.v:40251.5-40251.29" - switch \initial - attribute \src "libresoc.v:40251.9-40251.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_upd[1:0] 2'01 - case - assign $1\dec62_upd[1:0] 2'00 - end - sync always - update \dec62_upd $0\dec62_upd[1:0] - end - attribute \src "libresoc.v:40263.3-40275.6" - process $proc$libresoc.v:40263$885 - assign { } { } - assign { } { } - assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:40264.5-40264.29" - switch \initial - attribute \src "libresoc.v:40264.9-40264.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_rc_sel[1:0] 2'00 - case - assign $1\dec62_rc_sel[1:0] 2'00 - end - sync always - update \dec62_rc_sel $0\dec62_rc_sel[1:0] - end - attribute \src "libresoc.v:40276.3-40288.6" - process $proc$libresoc.v:40276$886 - assign { } { } - assign { } { } - assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:40277.5-40277.29" - switch \initial - attribute \src "libresoc.v:40277.9-40277.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_cry_in[1:0] 2'00 - case - assign $1\dec62_cry_in[1:0] 2'00 - end - sync always - update \dec62_cry_in $0\dec62_cry_in[1:0] - end - attribute \src "libresoc.v:40289.3-40301.6" - process $proc$libresoc.v:40289$887 - assign { } { } - assign { } { } - assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:40290.5-40290.29" - switch \initial - attribute \src "libresoc.v:40290.9-40290.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_asmcode[7:0] 8'10101100 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_asmcode[7:0] 8'10101111 - case - assign $1\dec62_asmcode[7:0] 8'00000000 - end - sync always - update \dec62_asmcode $0\dec62_asmcode[7:0] - end - attribute \src "libresoc.v:40302.3-40314.6" - process $proc$libresoc.v:40302$888 - assign { } { } - assign { } { } - assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:40303.5-40303.29" - switch \initial - attribute \src "libresoc.v:40303.9-40303.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_inv_a[0:0] 1'0 - case - assign $1\dec62_inv_a[0:0] 1'0 - end - sync always - update \dec62_inv_a $0\dec62_inv_a[0:0] - end - attribute \src "libresoc.v:40315.3-40327.6" - process $proc$libresoc.v:40315$889 - assign { } { } - assign { } { } - assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:40316.5-40316.29" - switch \initial - attribute \src "libresoc.v:40316.9-40316.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_inv_out[0:0] 1'0 - case - assign $1\dec62_inv_out[0:0] 1'0 - end - sync always - update \dec62_inv_out $0\dec62_inv_out[0:0] - end - attribute \src "libresoc.v:40328.3-40340.6" - process $proc$libresoc.v:40328$890 - assign { } { } - assign { } { } - assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:40329.5-40329.29" - switch \initial - attribute \src "libresoc.v:40329.9-40329.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_cry_out[0:0] 1'0 - case - assign $1\dec62_cry_out[0:0] 1'0 - end - sync always - update \dec62_cry_out $0\dec62_cry_out[0:0] - end - attribute \src "libresoc.v:40341.3-40353.6" - process $proc$libresoc.v:40341$891 - assign { } { } - assign { } { } - assign $0\dec62_br[0:0] $1\dec62_br[0:0] - attribute \src "libresoc.v:40342.5-40342.29" - switch \initial - attribute \src "libresoc.v:40342.9-40342.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_br[0:0] 1'0 - case - assign $1\dec62_br[0:0] 1'0 - end - sync always - update \dec62_br $0\dec62_br[0:0] - end - attribute \src "libresoc.v:40354.3-40366.6" - process $proc$libresoc.v:40354$892 - assign { } { } - assign { } { } - assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:40355.5-40355.29" - switch \initial - attribute \src "libresoc.v:40355.9-40355.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_sgn_ext[0:0] 1'0 - case - assign $1\dec62_sgn_ext[0:0] 1'0 - end - sync always - update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] - end - attribute \src "libresoc.v:40367.3-40379.6" - process $proc$libresoc.v:40367$893 - assign { } { } - assign { } { } - assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:40368.5-40368.29" - switch \initial - attribute \src "libresoc.v:40368.9-40368.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_internal_op[6:0] 7'0100110 - case - assign $1\dec62_internal_op[6:0] 7'0000000 - end - sync always - update \dec62_internal_op $0\dec62_internal_op[6:0] - end - attribute \src "libresoc.v:40380.3-40392.6" - process $proc$libresoc.v:40380$894 - assign { } { } - assign { } { } - assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:40381.5-40381.29" - switch \initial - attribute \src "libresoc.v:40381.9-40381.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_rsrv[0:0] 1'0 - case - assign $1\dec62_rsrv[0:0] 1'0 - end - sync always - update \dec62_rsrv $0\dec62_rsrv[0:0] - end - attribute \src "libresoc.v:40393.3-40405.6" - process $proc$libresoc.v:40393$895 - assign { } { } - assign { } { } - assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:40394.5-40394.29" - switch \initial - attribute \src "libresoc.v:40394.9-40394.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_is_32b[0:0] 1'0 - case - assign $1\dec62_is_32b[0:0] 1'0 - end - sync always - update \dec62_is_32b $0\dec62_is_32b[0:0] - end - attribute \src "libresoc.v:40406.3-40418.6" - process $proc$libresoc.v:40406$896 - assign { } { } - assign { } { } - assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] - attribute \src "libresoc.v:40407.5-40407.29" - switch \initial - attribute \src "libresoc.v:40407.9-40407.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_sgn[0:0] 1'0 - case - assign $1\dec62_sgn[0:0] 1'0 - end - sync always - update \dec62_sgn $0\dec62_sgn[0:0] - end - attribute \src "libresoc.v:40419.3-40431.6" - process $proc$libresoc.v:40419$897 - assign { } { } - assign { } { } - assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] - attribute \src "libresoc.v:40420.5-40420.29" - switch \initial - attribute \src "libresoc.v:40420.9-40420.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_lk[0:0] 1'0 - case - assign $1\dec62_lk[0:0] 1'0 - end - sync always - update \dec62_lk $0\dec62_lk[0:0] - end - attribute \src "libresoc.v:40432.3-40444.6" - process $proc$libresoc.v:40432$898 - assign { } { } - assign { } { } - assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:40433.5-40433.29" - switch \initial - attribute \src "libresoc.v:40433.9-40433.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_sgl_pipe[0:0] 1'1 - case - assign $1\dec62_sgl_pipe[0:0] 1'0 - end - sync always - update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] - end - attribute \src "libresoc.v:40445.3-40457.6" - process $proc$libresoc.v:40445$899 - assign { } { } - assign { } { } - assign $0\dec62_form[4:0] $1\dec62_form[4:0] - attribute \src "libresoc.v:40446.5-40446.29" - switch \initial - attribute \src "libresoc.v:40446.9-40446.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_form[4:0] 5'00101 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_form[4:0] 5'00101 - case - assign $1\dec62_form[4:0] 5'00000 - end - sync always - update \dec62_form $0\dec62_form[4:0] - end - attribute \src "libresoc.v:40458.3-40470.6" - process $proc$libresoc.v:40458$900 - assign { } { } - assign { } { } - assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:40459.5-40459.29" - switch \initial - attribute \src "libresoc.v:40459.9-40459.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_in1_sel[2:0] 3'010 - case - assign $1\dec62_in1_sel[2:0] 3'000 - end - sync always - update \dec62_in1_sel $0\dec62_in1_sel[2:0] - end - attribute \src "libresoc.v:40471.3-40483.6" - process $proc$libresoc.v:40471$901 - assign { } { } - assign { } { } - assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:40472.5-40472.29" - switch \initial - attribute \src "libresoc.v:40472.9-40472.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_in2_sel[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_in2_sel[3:0] 4'1000 - case - assign $1\dec62_in2_sel[3:0] 4'0000 - end - sync always - update \dec62_in2_sel $0\dec62_in2_sel[3:0] - end - attribute \src "libresoc.v:40484.3-40496.6" - process $proc$libresoc.v:40484$902 - assign { } { } - assign { } { } - assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:40485.5-40485.29" - switch \initial - attribute \src "libresoc.v:40485.9-40485.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_in3_sel[1:0] 2'01 - case - assign $1\dec62_in3_sel[1:0] 2'00 - end - sync always - update \dec62_in3_sel $0\dec62_in3_sel[1:0] - end - attribute \src "libresoc.v:40497.3-40509.6" - process $proc$libresoc.v:40497$903 - assign { } { } - assign { } { } - assign $0\dec62_out_sel[1:0] $1\dec62_out_sel[1:0] - attribute \src "libresoc.v:40498.5-40498.29" - switch \initial - attribute \src "libresoc.v:40498.9-40498.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_out_sel[1:0] 2'00 - case - assign $1\dec62_out_sel[1:0] 2'00 - end - sync always - update \dec62_out_sel $0\dec62_out_sel[1:0] - end - attribute \src "libresoc.v:40510.3-40522.6" - process $proc$libresoc.v:40510$904 - assign { } { } - assign { } { } - assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:40511.5-40511.29" - switch \initial - attribute \src "libresoc.v:40511.9-40511.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_cr_in[2:0] 3'000 - case - assign $1\dec62_cr_in[2:0] 3'000 - end - sync always - update \dec62_cr_in $0\dec62_cr_in[2:0] - end - attribute \src "libresoc.v:40523.3-40535.6" - process $proc$libresoc.v:40523$905 - assign { } { } - assign { } { } - assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:40524.5-40524.29" - switch \initial - attribute \src "libresoc.v:40524.9-40524.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_cr_out[2:0] 3'000 - case - assign $1\dec62_cr_out[2:0] 3'000 - end - sync always - update \dec62_cr_out $0\dec62_cr_out[2:0] - end - connect \opcode_switch \opcode_in [1:0] -end -attribute \src "libresoc.v:40541.1-41046.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a" -attribute \generator "nMigen" -module \dec_a - attribute \src "libresoc.v:40975.3-41010.6" - wire width 3 $0\fast_a[2:0] - attribute \src "libresoc.v:40975.3-41010.6" - wire $0\fast_a_ok[0:0] - attribute \src "libresoc.v:40542.7-40542.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:40943.3-40958.6" - wire width 5 $0\reg_a[4:0] - attribute \src "libresoc.v:40959.3-40974.6" - wire $0\reg_a_ok[0:0] - attribute \src "libresoc.v:41011.3-41021.6" - wire width 10 $0\spr[9:0] - attribute \src "libresoc.v:41033.3-41044.6" - wire width 10 $0\spr_a[9:0] - attribute \src "libresoc.v:41033.3-41044.6" - wire $0\spr_a_ok[0:0] - attribute \src "libresoc.v:41022.3-41032.6" - wire width 10 $0\sprmap_spr_i[9:0] - attribute \src "libresoc.v:40975.3-41010.6" - wire width 3 $1\fast_a[2:0] - attribute \src "libresoc.v:40975.3-41010.6" - wire $1\fast_a_ok[0:0] - attribute \src "libresoc.v:40943.3-40958.6" - wire width 5 $1\reg_a[4:0] - attribute \src "libresoc.v:40959.3-40974.6" - wire $1\reg_a_ok[0:0] - attribute \src "libresoc.v:41011.3-41021.6" - wire width 10 $1\spr[9:0] - attribute \src "libresoc.v:41033.3-41044.6" - wire width 10 $1\spr_a[9:0] - attribute \src "libresoc.v:41033.3-41044.6" - wire $1\spr_a_ok[0:0] - attribute \src "libresoc.v:41022.3-41032.6" - wire width 10 $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:40975.3-41010.6" - wire width 3 $2\fast_a[2:0] - attribute \src "libresoc.v:40975.3-41010.6" - wire $2\fast_a_ok[0:0] - attribute \src "libresoc.v:40943.3-40958.6" - wire width 5 $2\reg_a[4:0] - attribute \src "libresoc.v:40959.3-40974.6" - wire $2\reg_a_ok[0:0] - attribute \src "libresoc.v:40975.3-41010.6" - wire width 3 $3\fast_a[2:0] - attribute \src "libresoc.v:40975.3-41010.6" - wire $3\fast_a_ok[0:0] - attribute \src "libresoc.v:40927.18-40927.110" - wire $and$libresoc.v:40927$913_Y - attribute \src "libresoc.v:40932.18-40932.113" - wire $and$libresoc.v:40932$918_Y - attribute \src "libresoc.v:40935.17-40935.107" - wire $and$libresoc.v:40935$921_Y - attribute \src "libresoc.v:40922.18-40922.112" - wire $eq$libresoc.v:40922$908_Y - attribute \src "libresoc.v:40923.18-40923.111" - wire $eq$libresoc.v:40923$909_Y - attribute \src "libresoc.v:40924.18-40924.112" - wire $eq$libresoc.v:40924$910_Y - attribute \src "libresoc.v:40926.17-40926.110" - wire $eq$libresoc.v:40926$912_Y - attribute \src "libresoc.v:40929.18-40929.112" - wire $eq$libresoc.v:40929$915_Y - attribute \src "libresoc.v:40933.17-40933.111" - wire $eq$libresoc.v:40933$919_Y - attribute \src "libresoc.v:40925.18-40925.109" - wire $ne$libresoc.v:40925$911_Y - attribute \src "libresoc.v:40934.17-40934.108" - wire $ne$libresoc.v:40934$920_Y - attribute \src "libresoc.v:40930.18-40930.105" - wire $not$libresoc.v:40930$916_Y - attribute \src "libresoc.v:40931.18-40931.108" - wire $not$libresoc.v:40931$917_Y - attribute \src "libresoc.v:40921.17-40921.107" - wire $or$libresoc.v:40921$907_Y - attribute \src "libresoc.v:40928.18-40928.110" - wire $or$libresoc.v:40928$914_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 10 \BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 9 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 8 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 10 input 11 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 input 12 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 6 \fast_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 7 \fast_a_ok - attribute \src "libresoc.v:40542.7-40542.15" - wire \initial - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 13 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" - wire width 5 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 output 2 \reg_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \reg_a_ok - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:85" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - wire width 10 \spr - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 output 4 \spr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 5 \spr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \sprmap_fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \sprmap_fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" - wire width 10 \sprmap_spr_i - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \sprmap_spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \sprmap_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - cell $and $and$libresoc.v:40927$913 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$15 - connect \B \$17 - connect \Y $and$libresoc.v:40927$913_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" - cell $and $and$libresoc.v:40932$918 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [9] - connect \B \$27 - connect \Y $and$libresoc.v:40932$918_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - cell $and $and$libresoc.v:40935$921 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \$5 - connect \Y $and$libresoc.v:40935$921_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" - cell $eq $eq$libresoc.v:40922$908 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'100 - connect \Y $eq$libresoc.v:40922$908_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" - cell $eq $eq$libresoc.v:40923$909 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'001 - connect \Y $eq$libresoc.v:40923$909_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" - cell $eq $eq$libresoc.v:40924$910 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'010 - connect \Y $eq$libresoc.v:40924$910_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" - cell $eq $eq$libresoc.v:40926$912 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'001 - connect \Y $eq$libresoc.v:40926$912_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" - cell $eq $eq$libresoc.v:40929$915 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'100 - connect \Y $eq$libresoc.v:40929$915_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" - cell $eq $eq$libresoc.v:40933$919 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'010 - connect \Y $eq$libresoc.v:40933$919_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - cell $ne $ne$libresoc.v:40925$911 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \ra - connect \B 5'00000 - connect \Y $ne$libresoc.v:40925$911_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - cell $ne $ne$libresoc.v:40934$920 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \ra - connect \B 5'00000 - connect \Y $ne$libresoc.v:40934$920_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" - cell $not $not$libresoc.v:40930$916 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \BO [2] - connect \Y $not$libresoc.v:40930$916_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" - cell $not $not$libresoc.v:40931$917 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [5] - connect \Y $not$libresoc.v:40931$917_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - cell $or $or$libresoc.v:40921$907 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \$7 - connect \Y $or$libresoc.v:40921$907_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - cell $or $or$libresoc.v:40928$914 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$13 - connect \B \$19 - connect \Y $or$libresoc.v:40928$914_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:40936.10-40942.4" - cell \sprmap \sprmap - connect \fast_o \sprmap_fast_o - connect \fast_o_ok \sprmap_fast_o_ok - connect \spr_i \sprmap_spr_i - connect \spr_o \sprmap_spr_o - connect \spr_o_ok \sprmap_spr_o_ok - end - attribute \src "libresoc.v:40542.7-40542.20" - process $proc$libresoc.v:40542$928 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:40943.3-40958.6" - process $proc$libresoc.v:40943$922 - assign { } { } - assign { } { } - assign { } { } - assign $0\reg_a[4:0] $2\reg_a[4:0] - attribute \src "libresoc.v:40944.5-40944.29" - switch \initial - attribute \src "libresoc.v:40944.9-40944.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg_a[4:0] \ra - case - assign $1\reg_a[4:0] 5'00000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" - switch \$11 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg_a[4:0] \RS - case - assign $2\reg_a[4:0] $1\reg_a[4:0] - end - sync always - update \reg_a $0\reg_a[4:0] - end - attribute \src "libresoc.v:40959.3-40974.6" - process $proc$libresoc.v:40959$923 - assign { } { } - assign { } { } - assign { } { } - assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0] - attribute \src "libresoc.v:40960.5-40960.29" - switch \initial - attribute \src "libresoc.v:40960.9-40960.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - switch \$21 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg_a_ok[0:0] 1'1 - case - assign $1\reg_a_ok[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" - switch \$23 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg_a_ok[0:0] 1'1 - case - assign $2\reg_a_ok[0:0] $1\reg_a_ok[0:0] - end - sync always - update \reg_a_ok $0\reg_a_ok[0:0] - end - attribute \src "libresoc.v:40975.3-41010.6" - process $proc$libresoc.v:40975$924 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fast_a[2:0] $1\fast_a[2:0] - assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0] - attribute \src "libresoc.v:40976.5-40976.29" - switch \initial - attribute \src "libresoc.v:40976.9-40976.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0000111 - assign { } { } - assign { } { } - assign $1\fast_a[2:0] $2\fast_a[2:0] - assign $1\fast_a_ok[0:0] $2\fast_a_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" - switch \$25 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $2\fast_a[2:0] 3'000 - assign $2\fast_a_ok[0:0] 1'1 - case - assign $2\fast_a[2:0] 3'000 - assign $2\fast_a_ok[0:0] 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'0001000 - assign { } { } - assign { } { } - assign $1\fast_a[2:0] $3\fast_a[2:0] - assign $1\fast_a_ok[0:0] $3\fast_a_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" - switch \$29 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $3\fast_a[2:0] 3'000 - assign $3\fast_a_ok[0:0] 1'1 - case - assign $3\fast_a[2:0] 3'000 - assign $3\fast_a_ok[0:0] 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'0101110 - assign { } { } - assign { } { } - assign { $1\fast_a_ok[0:0] $1\fast_a[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } - case - assign $1\fast_a[2:0] 3'000 - assign $1\fast_a_ok[0:0] 1'0 - end - sync always - update \fast_a $0\fast_a[2:0] - update \fast_a_ok $0\fast_a_ok[0:0] - end - attribute \src "libresoc.v:41011.3-41021.6" - process $proc$libresoc.v:41011$925 - assign { } { } - assign { } { } - assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:41012.5-41012.29" - switch \initial - attribute \src "libresoc.v:41012.9-41012.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0101110 - assign { } { } - assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } - case - assign $1\spr[9:0] 10'0000000000 - end - sync always - update \spr $0\spr[9:0] - end - attribute \src "libresoc.v:41022.3-41032.6" - process $proc$libresoc.v:41022$926 - assign { } { } - assign { } { } - assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:41023.5-41023.29" - switch \initial - attribute \src "libresoc.v:41023.9-41023.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0101110 - assign { } { } - assign $1\sprmap_spr_i[9:0] \spr - case - assign $1\sprmap_spr_i[9:0] 10'0000000000 - end - sync always - update \sprmap_spr_i $0\sprmap_spr_i[9:0] - end - attribute \src "libresoc.v:41033.3-41044.6" - process $proc$libresoc.v:41033$927 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\spr_a[9:0] $1\spr_a[9:0] - assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0] - attribute \src "libresoc.v:41034.5-41034.29" - switch \initial - attribute \src "libresoc.v:41034.9-41034.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0101110 - assign { } { } - assign { } { } - assign { $1\spr_a_ok[0:0] $1\spr_a[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } - case - assign $1\spr_a[9:0] 10'0000000000 - assign $1\spr_a_ok[0:0] 1'0 - end - sync always - update \spr_a $0\spr_a[9:0] - update \spr_a_ok $0\spr_a_ok[0:0] - end - connect \$9 $or$libresoc.v:40921$907_Y - connect \$11 $eq$libresoc.v:40922$908_Y - connect \$13 $eq$libresoc.v:40923$909_Y - connect \$15 $eq$libresoc.v:40924$910_Y - connect \$17 $ne$libresoc.v:40925$911_Y - connect \$1 $eq$libresoc.v:40926$912_Y - connect \$19 $and$libresoc.v:40927$913_Y - connect \$21 $or$libresoc.v:40928$914_Y - connect \$23 $eq$libresoc.v:40929$915_Y - connect \$25 $not$libresoc.v:40930$916_Y - connect \$27 $not$libresoc.v:40931$917_Y - connect \$29 $and$libresoc.v:40932$918_Y - connect \$3 $eq$libresoc.v:40933$919_Y - connect \$5 $ne$libresoc.v:40934$920_Y - connect \$7 $and$libresoc.v:40935$921_Y - connect \ra \RA -end -attribute \src "libresoc.v:41050.1-41241.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_b" -attribute \generator "nMigen" -module \dec_b - attribute \src "libresoc.v:41205.3-41222.6" - wire width 3 $0\fast_b[2:0] - attribute \src "libresoc.v:41223.3-41240.6" - wire $0\fast_b_ok[0:0] - attribute \src "libresoc.v:41051.7-41051.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:41175.3-41189.6" - wire width 5 $0\reg_b[4:0] - attribute \src "libresoc.v:41190.3-41204.6" - wire $0\reg_b_ok[0:0] - attribute \src "libresoc.v:41205.3-41222.6" - wire width 3 $1\fast_b[2:0] - attribute \src "libresoc.v:41223.3-41240.6" - wire $1\fast_b_ok[0:0] - attribute \src "libresoc.v:41175.3-41189.6" - wire width 5 $1\reg_b[4:0] - attribute \src "libresoc.v:41190.3-41204.6" - wire $1\reg_b_ok[0:0] - attribute \src "libresoc.v:41205.3-41222.6" - wire width 3 $2\fast_b[2:0] - attribute \src "libresoc.v:41223.3-41240.6" - wire $2\fast_b_ok[0:0] - attribute \src "libresoc.v:41171.17-41171.117" - wire $eq$libresoc.v:41171$929_Y - attribute \src "libresoc.v:41173.17-41173.117" - wire $eq$libresoc.v:41173$931_Y - attribute \src "libresoc.v:41172.17-41172.107" - wire $not$libresoc.v:41172$930_Y - attribute \src "libresoc.v:41174.17-41174.107" - wire $not$libresoc.v:41174$932_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 7 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 6 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 input 8 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 4 \fast_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 5 \fast_b_ok - attribute \src "libresoc.v:41051.7-41051.15" - wire \initial - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 9 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 output 2 \reg_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \reg_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - wire width 4 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - cell $eq $eq$libresoc.v:41171$929 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0001000 - connect \Y $eq$libresoc.v:41171$929_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - cell $eq $eq$libresoc.v:41173$931 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0001000 - connect \Y $eq$libresoc.v:41173$931_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - cell $not $not$libresoc.v:41172$930 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [9] - connect \Y $not$libresoc.v:41172$930_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - cell $not $not$libresoc.v:41174$932 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [9] - connect \Y $not$libresoc.v:41174$932_Y - end - attribute \src "libresoc.v:41051.7-41051.20" - process $proc$libresoc.v:41051$937 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:41175.3-41189.6" - process $proc$libresoc.v:41175$933 - assign { } { } - assign { } { } - assign $0\reg_b[4:0] $1\reg_b[4:0] - attribute \src "libresoc.v:41176.5-41176.29" - switch \initial - attribute \src "libresoc.v:41176.9-41176.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\reg_b[4:0] \RB - attribute \src "libresoc.v:0.0-0.0" - case 4'1101 - assign { } { } - assign $1\reg_b[4:0] \RS - case - assign $1\reg_b[4:0] 5'00000 - end - sync always - update \reg_b $0\reg_b[4:0] - end - attribute \src "libresoc.v:41190.3-41204.6" - process $proc$libresoc.v:41190$934 - assign { } { } - assign { } { } - assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0] - attribute \src "libresoc.v:41191.5-41191.29" - switch \initial - attribute \src "libresoc.v:41191.9-41191.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\reg_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1101 - assign { } { } - assign $1\reg_b_ok[0:0] 1'1 - case - assign $1\reg_b_ok[0:0] 1'0 - end - sync always - update \reg_b_ok $0\reg_b_ok[0:0] - end - attribute \src "libresoc.v:41205.3-41222.6" - process $proc$libresoc.v:41205$935 - assign { } { } - assign { } { } - assign $0\fast_b[2:0] $1\fast_b[2:0] - attribute \src "libresoc.v:41206.5-41206.29" - switch \initial - attribute \src "libresoc.v:41206.9-41206.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fast_b[2:0] $2\fast_b[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - switch { \XL_XO [5] \$3 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\fast_b[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\fast_b[2:0] 3'010 - case - assign $2\fast_b[2:0] 3'000 - end - case - assign $1\fast_b[2:0] 3'000 - end - sync always - update \fast_b $0\fast_b[2:0] - end - attribute \src "libresoc.v:41223.3-41240.6" - process $proc$libresoc.v:41223$936 - assign { } { } - assign { } { } - assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0] - attribute \src "libresoc.v:41224.5-41224.29" - switch \initial - attribute \src "libresoc.v:41224.9-41224.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - switch \$5 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fast_b_ok[0:0] $2\fast_b_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - switch { \XL_XO [5] \$7 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\fast_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\fast_b_ok[0:0] 1'1 - case - assign $2\fast_b_ok[0:0] 1'0 - end - case - assign $1\fast_b_ok[0:0] 1'0 - end - sync always - update \fast_b_ok $0\fast_b_ok[0:0] - end - connect \$1 $eq$libresoc.v:41171$929_Y - connect \$3 $not$libresoc.v:41172$930_Y - connect \$5 $eq$libresoc.v:41173$931_Y - connect \$7 $not$libresoc.v:41174$932_Y -end -attribute \src "libresoc.v:41245.1-41293.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c" -attribute \generator "nMigen" -module \dec_c - attribute \src "libresoc.v:41246.7-41246.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:41263.3-41277.6" - wire width 5 $0\reg_c[4:0] - attribute \src "libresoc.v:41278.3-41292.6" - wire $0\reg_c_ok[0:0] - attribute \src "libresoc.v:41263.3-41277.6" - wire width 5 $1\reg_c[4:0] - attribute \src "libresoc.v:41278.3-41292.6" - wire $1\reg_c_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 4 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 3 \RS - attribute \src "libresoc.v:41246.7-41246.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 output 1 \reg_c - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \reg_c_ok - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" - wire width 2 input 5 \sel_in - attribute \src "libresoc.v:41246.7-41246.20" - process $proc$libresoc.v:41246$940 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:41263.3-41277.6" - process $proc$libresoc.v:41263$938 - assign { } { } - assign { } { } - assign $0\reg_c[4:0] $1\reg_c[4:0] - attribute \src "libresoc.v:41264.5-41264.29" - switch \initial - attribute \src "libresoc.v:41264.9-41264.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\reg_c[4:0] \RB - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\reg_c[4:0] \RS - case - assign $1\reg_c[4:0] 5'00000 - end - sync always - update \reg_c $0\reg_c[4:0] - end - attribute \src "libresoc.v:41278.3-41292.6" - process $proc$libresoc.v:41278$939 - assign { } { } - assign { } { } - assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] - attribute \src "libresoc.v:41279.5-41279.29" - switch \initial - attribute \src "libresoc.v:41279.9-41279.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\reg_c_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\reg_c_ok[0:0] 1'1 - case - assign $1\reg_c_ok[0:0] 1'0 - end - sync always - update \reg_c_ok $0\reg_c_ok[0:0] - end -end -attribute \src "libresoc.v:41297.1-41602.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in - attribute \src "libresoc.v:41496.3-41522.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:41523.3-41533.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:41474.3-41484.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:41534.3-41544.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:41545.3-41555.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:41447.3-41473.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:41583.3-41601.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:41485.3-41495.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:41298.7-41298.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:41556.3-41566.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:41567.3-41582.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:41496.3-41522.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:41523.3-41533.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:41474.3-41484.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:41534.3-41544.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:41545.3-41555.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:41447.3-41473.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:41583.3-41601.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:41485.3-41495.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:41556.3-41566.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:41567.3-41582.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:41583.3-41601.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:41567.3-41582.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:41440.17-41440.112" - wire $and$libresoc.v:41440$942_Y - attribute \src "libresoc.v:41442.17-41442.112" - wire $and$libresoc.v:41442$944_Y - attribute \src "libresoc.v:41439.17-41439.117" - wire $eq$libresoc.v:41439$941_Y - attribute \src "libresoc.v:41441.17-41441.117" - wire $eq$libresoc.v:41441$943_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 12 \BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 11 \BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 16 \BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 15 \BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 13 \BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 14 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 17 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 5 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 7 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 8 \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 9 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 10 \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 6 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 output 3 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 4 \cr_fxm_ok - attribute \src "libresoc.v:41298.7-41298.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" - wire width 32 input 18 \insn_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 2 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:41440$942 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:41440$942_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:41442$944 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:41442$944_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:41439$941 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:41439$941_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:41441$943 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:41441$943_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:41443.9-41446.4" - cell \ppick \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:41298.7-41298.20" - process $proc$libresoc.v:41298$955 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:41447.3-41473.6" - process $proc$libresoc.v:41447$945 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:41448.5-41448.29" - switch \initial - attribute \src "libresoc.v:41448.9-41448.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:41474.3-41484.6" - process $proc$libresoc.v:41474$946 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:41475.5-41475.29" - switch \initial - attribute \src "libresoc.v:41475.9-41475.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "libresoc.v:41485.3-41495.6" - process $proc$libresoc.v:41485$947 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:41486.5-41486.29" - switch \initial - attribute \src "libresoc.v:41486.9-41486.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:41496.3-41522.6" - process $proc$libresoc.v:41496$948 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:41497.5-41497.29" - switch \initial - attribute \src "libresoc.v:41497.9-41497.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:41523.3-41533.6" - process $proc$libresoc.v:41523$949 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:41524.5-41524.29" - switch \initial - attribute \src "libresoc.v:41524.9-41524.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "libresoc.v:41534.3-41544.6" - process $proc$libresoc.v:41534$950 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:41535.5-41535.29" - switch \initial - attribute \src "libresoc.v:41535.9-41535.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "libresoc.v:41545.3-41555.6" - process $proc$libresoc.v:41545$951 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:41546.5-41546.29" - switch \initial - attribute \src "libresoc.v:41546.9-41546.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:41556.3-41566.6" - process $proc$libresoc.v:41556$952 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:41557.5-41557.29" - switch \initial - attribute \src "libresoc.v:41557.9-41557.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:41567.3-41582.6" - process $proc$libresoc.v:41567$953 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:41568.5-41568.29" - switch \initial - attribute \src "libresoc.v:41568.9-41568.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:41583.3-41601.6" - process $proc$libresoc.v:41583$954 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:41584.5-41584.29" - switch \initial - attribute \src "libresoc.v:41584.9-41584.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:41439$941_Y - connect \$3 $and$libresoc.v:41440$942_Y - connect \$5 $eq$libresoc.v:41441$943_Y - connect \$7 $and$libresoc.v:41442$944_Y -end -attribute \src "libresoc.v:41606.1-41849.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out" -attribute \generator "nMigen" -module \dec_cr_out - attribute \src "libresoc.v:41763.3-41781.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:41733.3-41751.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:41814.3-41848.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:41752.3-41762.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:41607.7-41607.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:41782.3-41792.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:41793.3-41813.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:41763.3-41781.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:41733.3-41751.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:41814.3-41848.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:41752.3-41762.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:41782.3-41792.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:41793.3-41813.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:41814.3-41848.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:41793.3-41813.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:41814.3-41848.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:41793.3-41813.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:41814.3-41848.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:41726.17-41726.117" - wire $eq$libresoc.v:41726$956_Y - attribute \src "libresoc.v:41727.17-41727.117" - wire $eq$libresoc.v:41727$957_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 8 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 input 10 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 9 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 6 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 7 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 output 4 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 5 \cr_fxm_ok - attribute \src "libresoc.v:41607.7-41607.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" - wire width 32 input 11 \insn_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 3 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:41726$956 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:41726$956_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:41727$957 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:41727$957_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:41728.13-41732.4" - cell \ppick$1 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:41607.7-41607.20" - process $proc$libresoc.v:41607$964 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:41733.3-41751.6" - process $proc$libresoc.v:41733$958 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:41734.5-41734.29" - switch \initial - attribute \src "libresoc.v:41734.9-41734.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:41752.3-41762.6" - process $proc$libresoc.v:41752$959 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:41753.5-41753.29" - switch \initial - attribute \src "libresoc.v:41753.9-41753.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:41763.3-41781.6" - process $proc$libresoc.v:41763$960 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:41764.5-41764.29" - switch \initial - attribute \src "libresoc.v:41764.9-41764.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:41782.3-41792.6" - process $proc$libresoc.v:41782$961 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:41783.5-41783.29" - switch \initial - attribute \src "libresoc.v:41783.9-41783.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:41793.3-41813.6" - process $proc$libresoc.v:41793$962 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:41794.5-41794.29" - switch \initial - attribute \src "libresoc.v:41794.9-41794.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:41814.3-41848.6" - process $proc$libresoc.v:41814$963 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:41815.5-41815.29" - switch \initial - attribute \src "libresoc.v:41815.9-41815.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \FXM - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:41726$956_Y - connect \$3 $eq$libresoc.v:41727$957_Y -end -attribute \src "libresoc.v:41853.1-42330.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o" -attribute \generator "nMigen" -module \dec_o - attribute \src "libresoc.v:42291.3-42329.6" - wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:42291.3-42329.6" - wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:41854.7-41854.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:42217.3-42231.6" - wire width 5 $0\reg_o[4:0] - attribute \src "libresoc.v:42232.3-42246.6" - wire $0\reg_o_ok[0:0] - attribute \src "libresoc.v:42247.3-42257.6" - wire width 10 $0\spr[9:0] - attribute \src "libresoc.v:42274.3-42290.6" - wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:42274.3-42290.6" - wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:42258.3-42273.6" - wire width 10 $0\sprmap_spr_i[9:0] - attribute \src "libresoc.v:42291.3-42329.6" - wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:42291.3-42329.6" - wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:42217.3-42231.6" - wire width 5 $1\reg_o[4:0] - attribute \src "libresoc.v:42232.3-42246.6" - wire $1\reg_o_ok[0:0] - attribute \src "libresoc.v:42247.3-42257.6" - wire width 10 $1\spr[9:0] - attribute \src "libresoc.v:42274.3-42290.6" - wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:42274.3-42290.6" - wire $1\spr_o_ok[0:0] - attribute \src "libresoc.v:42258.3-42273.6" - wire width 10 $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:42291.3-42329.6" - wire width 3 $2\fast_o[2:0] - attribute \src "libresoc.v:42291.3-42329.6" - wire $2\fast_o_ok[0:0] - attribute \src "libresoc.v:42274.3-42290.6" - wire width 10 $2\spr_o[9:0] - attribute \src "libresoc.v:42274.3-42290.6" - wire $2\spr_o_ok[0:0] - attribute \src "libresoc.v:42258.3-42273.6" - wire width 10 $2\sprmap_spr_i[9:0] - attribute \src "libresoc.v:42291.3-42329.6" - wire width 3 $3\fast_o[2:0] - attribute \src "libresoc.v:42291.3-42329.6" - wire $3\fast_o_ok[0:0] - attribute \src "libresoc.v:42291.3-42329.6" - wire width 3 $4\fast_o[2:0] - attribute \src "libresoc.v:42291.3-42329.6" - wire $4\fast_o_ok[0:0] - attribute \src "libresoc.v:42206.17-42206.117" - wire $eq$libresoc.v:42206$965_Y - attribute \src "libresoc.v:42207.17-42207.117" - wire $eq$libresoc.v:42207$966_Y - attribute \src "libresoc.v:42208.17-42208.117" - wire $eq$libresoc.v:42208$967_Y - attribute \src "libresoc.v:42209.17-42209.104" - wire $not$libresoc.v:42209$968_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 10 \BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 9 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 8 \RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 10 input 11 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 6 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 7 \fast_o_ok - attribute \src "libresoc.v:41854.7-41854.15" - wire \initial - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 12 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 output 2 \reg_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \reg_o_ok - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" - wire width 2 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" - wire width 10 \spr - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 output 4 \spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 5 \spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \sprmap_fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \sprmap_fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" - wire width 10 \sprmap_spr_i - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \sprmap_spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \sprmap_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - cell $eq $eq$libresoc.v:42206$965 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110001 - connect \Y $eq$libresoc.v:42206$965_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - cell $eq $eq$libresoc.v:42207$966 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110001 - connect \Y $eq$libresoc.v:42207$966_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - cell $eq $eq$libresoc.v:42208$967 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110001 - connect \Y $eq$libresoc.v:42208$967_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" - cell $not $not$libresoc.v:42209$968 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \BO [2] - connect \Y $not$libresoc.v:42209$968_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:42210.14-42216.4" - cell \sprmap$2 \sprmap - connect \fast_o \sprmap_fast_o - connect \fast_o_ok \sprmap_fast_o_ok - connect \spr_i \sprmap_spr_i - connect \spr_o \sprmap_spr_o - connect \spr_o_ok \sprmap_spr_o_ok - end - attribute \src "libresoc.v:41854.7-41854.20" - process $proc$libresoc.v:41854$975 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:42217.3-42231.6" - process $proc$libresoc.v:42217$969 - assign { } { } - assign { } { } - assign $0\reg_o[4:0] $1\reg_o[4:0] - attribute \src "libresoc.v:42218.5-42218.29" - switch \initial - attribute \src "libresoc.v:42218.9-42218.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\reg_o[4:0] \RT - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\reg_o[4:0] \RA - case - assign $1\reg_o[4:0] 5'00000 - end - sync always - update \reg_o $0\reg_o[4:0] - end - attribute \src "libresoc.v:42232.3-42246.6" - process $proc$libresoc.v:42232$970 - assign { } { } - assign { } { } - assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] - attribute \src "libresoc.v:42233.5-42233.29" - switch \initial - attribute \src "libresoc.v:42233.9-42233.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\reg_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\reg_o_ok[0:0] 1'1 - case - assign $1\reg_o_ok[0:0] 1'0 - end - sync always - update \reg_o_ok $0\reg_o_ok[0:0] - end - attribute \src "libresoc.v:42247.3-42257.6" - process $proc$libresoc.v:42247$971 - assign { } { } - assign { } { } - assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:42248.5-42248.29" - switch \initial - attribute \src "libresoc.v:42248.9-42248.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } - case - assign $1\spr[9:0] 10'0000000000 - end - sync always - update \spr $0\spr[9:0] - end - attribute \src "libresoc.v:42258.3-42273.6" - process $proc$libresoc.v:42258$972 - assign { } { } - assign { } { } - assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:42259.5-42259.29" - switch \initial - attribute \src "libresoc.v:42259.9-42259.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\sprmap_spr_i[9:0] \spr - case - assign $2\sprmap_spr_i[9:0] 10'0000000000 - end - case - assign $1\sprmap_spr_i[9:0] 10'0000000000 - end - sync always - update \sprmap_spr_i $0\sprmap_spr_i[9:0] - end - attribute \src "libresoc.v:42274.3-42290.6" - process $proc$libresoc.v:42274$973 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\spr_o[9:0] $1\spr_o[9:0] - assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:42275.5-42275.29" - switch \initial - attribute \src "libresoc.v:42275.9-42275.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign { } { } - assign $1\spr_o[9:0] $2\spr_o[9:0] - assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\spr_o_ok[0:0] $2\spr_o[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } - case - assign $2\spr_o[9:0] 10'0000000000 - assign $2\spr_o_ok[0:0] 1'0 - end - case - assign $1\spr_o[9:0] 10'0000000000 - assign $1\spr_o_ok[0:0] 1'0 - end - sync always - update \spr_o $0\spr_o[9:0] - update \spr_o_ok $0\spr_o_ok[0:0] - end - attribute \src "libresoc.v:42291.3-42329.6" - process $proc$libresoc.v:42291$974 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fast_o[2:0] $3\fast_o[2:0] - assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] - attribute \src "libresoc.v:42292.5-42292.29" - switch \initial - attribute \src "libresoc.v:42292.9-42292.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign { } { } - assign $1\fast_o[2:0] $2\fast_o[2:0] - assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - switch \$5 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\fast_o_ok[0:0] $2\fast_o[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } - case - assign $2\fast_o[2:0] 3'000 - assign $2\fast_o_ok[0:0] 1'0 - end - case - assign $1\fast_o[2:0] 3'000 - assign $1\fast_o_ok[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:337" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0000111 , 7'0001000 - assign { } { } - assign { } { } - assign $3\fast_o[2:0] $4\fast_o[2:0] - assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $4\fast_o[2:0] 3'000 - assign $4\fast_o_ok[0:0] 1'1 - case - assign $4\fast_o[2:0] $1\fast_o[2:0] - assign $4\fast_o_ok[0:0] $1\fast_o_ok[0:0] - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign { } { } - assign { } { } - assign $3\fast_o[2:0] 3'011 - assign $3\fast_o_ok[0:0] 1'1 - case - assign $3\fast_o[2:0] $1\fast_o[2:0] - assign $3\fast_o_ok[0:0] $1\fast_o_ok[0:0] - end - sync always - update \fast_o $0\fast_o[2:0] - update \fast_o_ok $0\fast_o_ok[0:0] - end - connect \$1 $eq$libresoc.v:42206$965_Y - connect \$3 $eq$libresoc.v:42207$966_Y - connect \$5 $eq$libresoc.v:42208$967_Y - connect \$7 $not$libresoc.v:42209$968_Y -end -attribute \src "libresoc.v:42334.1-42495.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2" -attribute \generator "nMigen" -module \dec_o2 - attribute \src "libresoc.v:42455.3-42474.6" - wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:42475.3-42494.6" - wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:42335.7-42335.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:42441.3-42454.6" - wire width 5 $0\reg_o[4:0] - attribute \src "libresoc.v:42441.3-42454.6" - wire $0\reg_o_ok[0:0] - attribute \src "libresoc.v:42455.3-42474.6" - wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:42475.3-42494.6" - wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:42441.3-42454.6" - wire width 5 $1\reg_o[4:0] - attribute \src "libresoc.v:42441.3-42454.6" - wire $1\reg_o_ok[0:0] - attribute \src "libresoc.v:42455.3-42474.6" - wire width 3 $2\fast_o[2:0] - attribute \src "libresoc.v:42475.3-42494.6" - wire $2\fast_o_ok[0:0] - attribute \src "libresoc.v:42439.17-42439.108" - wire $eq$libresoc.v:42439$976_Y - attribute \src "libresoc.v:42440.17-42440.100" - wire width 6 $extend$libresoc.v:42440$977_Y - attribute \src "libresoc.v:42440.17-42440.100" - wire width 6 $pos$libresoc.v:42440$978_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 7 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 4 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 5 \fast_o_ok - attribute \src "libresoc.v:42335.7-42335.15" - wire \initial - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 8 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363" - wire input 1 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 output 2 \reg_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \reg_o_ok - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 input 6 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" - cell $eq $eq$libresoc.v:42439$976 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \upd - connect \B 2'01 - connect \Y $eq$libresoc.v:42439$976_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:42440$977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 6 - connect \A \RA - connect \Y $extend$libresoc.v:42440$977_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:42440$978 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $extend$libresoc.v:42440$977_Y - connect \Y $pos$libresoc.v:42440$978_Y - end - attribute \src "libresoc.v:42335.7-42335.20" - process $proc$libresoc.v:42335$982 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:42441.3-42454.6" - process $proc$libresoc.v:42441$979 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg_o[4:0] $1\reg_o[4:0] - assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] - attribute \src "libresoc.v:42442.5-42442.29" - switch \initial - attribute \src "libresoc.v:42442.9-42442.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\reg_o[4:0] \$3 [4:0] - assign $1\reg_o_ok[0:0] 1'1 - case - assign $1\reg_o[4:0] 5'00000 - assign $1\reg_o_ok[0:0] 1'0 - end - sync always - update \reg_o $0\reg_o[4:0] - update \reg_o_ok $0\reg_o_ok[0:0] - end - attribute \src "libresoc.v:42455.3-42474.6" - process $proc$libresoc.v:42455$980 - assign { } { } - assign { } { } - assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:42456.5-42456.29" - switch \initial - attribute \src "libresoc.v:42456.9-42456.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:381" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0000111 , 7'0000110 , 7'0001000 - assign { } { } - assign $1\fast_o[2:0] $2\fast_o[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:385" - switch \lk - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast_o[2:0] 3'001 - case - assign $2\fast_o[2:0] 3'000 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign { } { } - assign $1\fast_o[2:0] 3'100 - case - assign $1\fast_o[2:0] 3'000 - end - sync always - update \fast_o $0\fast_o[2:0] - end - attribute \src "libresoc.v:42475.3-42494.6" - process $proc$libresoc.v:42475$981 - assign { } { } - assign { } { } - assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:42476.5-42476.29" - switch \initial - attribute \src "libresoc.v:42476.9-42476.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:381" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0000111 , 7'0000110 , 7'0001000 - assign { } { } - assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:385" - switch \lk - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast_o_ok[0:0] 1'1 - case - assign $2\fast_o_ok[0:0] 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - case - assign $1\fast_o_ok[0:0] 1'0 - end - sync always - update \fast_o_ok $0\fast_o_ok[0:0] - end - connect \$1 $eq$libresoc.v:42439$976_Y - connect \$3 $pos$libresoc.v:42440$978_Y -end -attribute \src "libresoc.v:42499.1-42633.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe" -attribute \generator "nMigen" -module \dec_oe - attribute \src "libresoc.v:42500.7-42500.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:42591.3-42611.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:42612.3-42632.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:42591.3-42611.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:42612.3-42632.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:42591.3-42611.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:42612.3-42632.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 4 \OE - attribute \src "libresoc.v:42500.7-42500.15" - wire \initial - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 1 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" - wire width 2 input 5 \sel_in - attribute \src "libresoc.v:42500.7-42500.20" - process $proc$libresoc.v:42500$985 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:42591.3-42611.6" - process $proc$libresoc.v:42591$983 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:42592.5-42592.29" - switch \initial - attribute \src "libresoc.v:42592.9-42592.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "libresoc.v:42612.3-42632.6" - process $proc$libresoc.v:42612$984 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:42613.5-42613.29" - switch \initial - attribute \src "libresoc.v:42613.9-42613.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "libresoc.v:42637.1-42691.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc" -attribute \generator "nMigen" -module \dec_rc - attribute \src "libresoc.v:42638.7-42638.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:42653.3-42671.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:42672.3-42690.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:42653.3-42671.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:42672.3-42690.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 3 \Rc - attribute \src "libresoc.v:42638.7-42638.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" - wire width 2 input 4 \sel_in - attribute \src "libresoc.v:42638.7-42638.20" - process $proc$libresoc.v:42638$988 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:42653.3-42671.6" - process $proc$libresoc.v:42653$986 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:42654.5-42654.29" - switch \initial - attribute \src "libresoc.v:42654.9-42654.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \Rc - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "libresoc.v:42672.3-42690.6" - process $proc$libresoc.v:42672$987 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:42673.5-42673.29" - switch \initial - attribute \src "libresoc.v:42673.9-42673.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "libresoc.v:42695.1-43017.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.imem" -attribute \generator "nMigen" -module \imem - attribute \src "libresoc.v:42974.3-42988.6" - wire width 45 $0\f_badaddr_o$next[44:0]$1051 - attribute \src "libresoc.v:42835.3-42836.39" - wire width 45 $0\f_badaddr_o[44:0] - attribute \src "libresoc.v:42989.3-43000.6" - wire $0\f_busy_o[0:0] - attribute \src "libresoc.v:42956.3-42973.6" - wire $0\f_fetch_err_o$next[0:0]$1047 - attribute \src "libresoc.v:42837.3-42838.43" - wire $0\f_fetch_err_o[0:0] - attribute \src "libresoc.v:43001.3-43013.6" - wire width 64 $0\f_instr_o[63:0] - attribute \src "libresoc.v:42938.3-42955.6" - wire width 45 $0\ibus__adr$next[44:0]$1043 - attribute \src "libresoc.v:42839.3-42840.35" - wire width 45 $0\ibus__adr[44:0] - attribute \src "libresoc.v:42849.3-42871.6" - wire $0\ibus__cyc$next[0:0]$1023 - attribute \src "libresoc.v:42847.3-42848.35" - wire $0\ibus__cyc[0:0] - attribute \src "libresoc.v:42895.3-42917.6" - wire width 8 $0\ibus__sel$next[7:0]$1033 - attribute \src "libresoc.v:42843.3-42844.35" - wire width 8 $0\ibus__sel[7:0] - attribute \src "libresoc.v:42872.3-42894.6" - wire $0\ibus__stb$next[0:0]$1028 - attribute \src "libresoc.v:42845.3-42846.35" - wire $0\ibus__stb[0:0] - attribute \src "libresoc.v:42918.3-42937.6" - wire width 64 $0\ibus_rdata$next[63:0]$1038 - attribute \src "libresoc.v:42841.3-42842.37" - wire width 64 $0\ibus_rdata[63:0] - attribute \src "libresoc.v:42696.7-42696.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:42974.3-42988.6" - wire width 45 $1\f_badaddr_o$next[44:0]$1052 - attribute \src "libresoc.v:42758.14-42758.44" - wire width 45 $1\f_badaddr_o[44:0] - attribute \src "libresoc.v:42989.3-43000.6" - wire $1\f_busy_o[0:0] - attribute \src "libresoc.v:42956.3-42973.6" - wire $1\f_fetch_err_o$next[0:0]$1048 - attribute \src "libresoc.v:42765.7-42765.27" - wire $1\f_fetch_err_o[0:0] - attribute \src "libresoc.v:43001.3-43013.6" - wire width 64 $1\f_instr_o[63:0] - attribute \src "libresoc.v:42938.3-42955.6" - wire width 45 $1\ibus__adr$next[44:0]$1044 - attribute \src "libresoc.v:42779.14-42779.42" - wire width 45 $1\ibus__adr[44:0] - attribute \src "libresoc.v:42849.3-42871.6" - wire $1\ibus__cyc$next[0:0]$1024 - attribute \src "libresoc.v:42784.7-42784.23" - wire $1\ibus__cyc[0:0] - attribute \src "libresoc.v:42895.3-42917.6" - wire width 8 $1\ibus__sel$next[7:0]$1034 - attribute \src "libresoc.v:42793.13-42793.30" - wire width 8 $1\ibus__sel[7:0] - attribute \src "libresoc.v:42872.3-42894.6" - wire $1\ibus__stb$next[0:0]$1029 - attribute \src "libresoc.v:42798.7-42798.23" - wire $1\ibus__stb[0:0] - attribute \src "libresoc.v:42918.3-42937.6" - wire width 64 $1\ibus_rdata$next[63:0]$1039 - attribute \src "libresoc.v:42802.14-42802.47" - wire width 64 $1\ibus_rdata[63:0] - attribute \src "libresoc.v:42974.3-42988.6" - wire width 45 $2\f_badaddr_o$next[44:0]$1053 - attribute \src "libresoc.v:42956.3-42973.6" - wire $2\f_fetch_err_o$next[0:0]$1049 - attribute \src "libresoc.v:42938.3-42955.6" - wire width 45 $2\ibus__adr$next[44:0]$1045 - attribute \src "libresoc.v:42849.3-42871.6" - wire $2\ibus__cyc$next[0:0]$1025 - attribute \src "libresoc.v:42895.3-42917.6" - wire width 8 $2\ibus__sel$next[7:0]$1035 - attribute \src "libresoc.v:42872.3-42894.6" - wire $2\ibus__stb$next[0:0]$1030 - attribute \src "libresoc.v:42918.3-42937.6" - wire width 64 $2\ibus_rdata$next[63:0]$1040 - attribute \src "libresoc.v:42849.3-42871.6" - wire $3\ibus__cyc$next[0:0]$1026 - attribute \src "libresoc.v:42895.3-42917.6" - wire width 8 $3\ibus__sel$next[7:0]$1036 - attribute \src "libresoc.v:42872.3-42894.6" - wire $3\ibus__stb$next[0:0]$1031 - attribute \src "libresoc.v:42918.3-42937.6" - wire width 64 $3\ibus_rdata$next[63:0]$1041 - attribute \src "libresoc.v:42811.18-42811.110" - wire $and$libresoc.v:42811$991_Y - attribute \src "libresoc.v:42817.18-42817.110" - wire $and$libresoc.v:42817$997_Y - attribute \src "libresoc.v:42822.18-42822.110" - wire $and$libresoc.v:42822$1002_Y - attribute \src "libresoc.v:42825.17-42825.108" - wire $and$libresoc.v:42825$1005_Y - attribute \src "libresoc.v:42828.18-42828.110" - wire $and$libresoc.v:42828$1008_Y - attribute \src "libresoc.v:42829.18-42829.115" - wire $and$libresoc.v:42829$1009_Y - attribute \src "libresoc.v:42831.18-42831.115" - wire $and$libresoc.v:42831$1011_Y - attribute \src "libresoc.v:42810.18-42810.105" - wire $not$libresoc.v:42810$990_Y - attribute \src "libresoc.v:42813.18-42813.105" - wire $not$libresoc.v:42813$993_Y - attribute \src "libresoc.v:42814.17-42814.104" - wire $not$libresoc.v:42814$994_Y - attribute \src "libresoc.v:42816.18-42816.105" - wire $not$libresoc.v:42816$996_Y - attribute \src "libresoc.v:42819.18-42819.105" - wire $not$libresoc.v:42819$999_Y - attribute \src "libresoc.v:42821.18-42821.105" - wire $not$libresoc.v:42821$1001_Y - attribute \src "libresoc.v:42824.18-42824.105" - wire $not$libresoc.v:42824$1004_Y - attribute \src "libresoc.v:42827.18-42827.105" - wire $not$libresoc.v:42827$1007_Y - attribute \src "libresoc.v:42830.18-42830.105" - wire $not$libresoc.v:42830$1010_Y - attribute \src "libresoc.v:42832.18-42832.105" - wire $not$libresoc.v:42832$1012_Y - attribute \src "libresoc.v:42834.17-42834.104" - wire $not$libresoc.v:42834$1014_Y - attribute \src "libresoc.v:42809.17-42809.103" - wire $or$libresoc.v:42809$989_Y - attribute \src "libresoc.v:42812.18-42812.115" - wire $or$libresoc.v:42812$992_Y - attribute \src "libresoc.v:42815.18-42815.106" - wire $or$libresoc.v:42815$995_Y - attribute \src "libresoc.v:42818.18-42818.115" - wire $or$libresoc.v:42818$998_Y - attribute \src "libresoc.v:42820.18-42820.106" - wire $or$libresoc.v:42820$1000_Y - attribute \src "libresoc.v:42823.18-42823.115" - wire $or$libresoc.v:42823$1003_Y - attribute \src "libresoc.v:42826.18-42826.106" - wire $or$libresoc.v:42826$1006_Y - attribute \src "libresoc.v:42833.17-42833.114" - wire $or$libresoc.v:42833$1013_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31" - wire \a_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" - wire width 48 input 1 \a_pc_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25" - wire \a_stall_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" - wire input 2 \a_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" - wire width 45 \f_badaddr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" - wire width 45 \f_badaddr_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" - wire output 4 \f_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" - wire \f_fetch_err_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" - wire \f_fetch_err_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" - wire width 64 output 5 \f_instr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27" - wire \f_stall_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" - wire input 3 \f_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 8 \ibus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 output 13 \ibus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 \ibus__adr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 7 \ibus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire \ibus__cyc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 12 \ibus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 9 \ibus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 output 11 \ibus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 \ibus__sel$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 10 \ibus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire \ibus__stb$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59" - wire width 64 \ibus_rdata - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59" - wire width 64 \ibus_rdata$next - attribute \src "libresoc.v:42696.7-42696.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" - wire input 14 \intclk_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" - wire input 6 \intclk_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $and$libresoc.v:42811$991 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$11 - connect \Y $and$libresoc.v:42811$991_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $and$libresoc.v:42817$997 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$21 - connect \Y $and$libresoc.v:42817$997_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $and$libresoc.v:42822$1002 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$31 - connect \Y $and$libresoc.v:42822$1002_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $and$libresoc.v:42825$1005 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$1 - connect \Y $and$libresoc.v:42825$1005_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $and$libresoc.v:42828$1008 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$41 - connect \Y $and$libresoc.v:42828$1008_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - cell $and $and$libresoc.v:42829$1009 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__cyc - connect \B \ibus__err - connect \Y $and$libresoc.v:42829$1009_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - cell $and $and$libresoc.v:42831$1011 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__cyc - connect \B \ibus__err - connect \Y $and$libresoc.v:42831$1011_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $not$libresoc.v:42810$990 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$libresoc.v:42810$990_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $not $not$libresoc.v:42813$993 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $not$libresoc.v:42813$993_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $not$libresoc.v:42814$994 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$libresoc.v:42814$994_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $not$libresoc.v:42816$996 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$libresoc.v:42816$996_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $not $not$libresoc.v:42819$999 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $not$libresoc.v:42819$999_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $not$libresoc.v:42821$1001 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$libresoc.v:42821$1001_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $not $not$libresoc.v:42824$1004 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $not$libresoc.v:42824$1004_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $not$libresoc.v:42827$1007 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$libresoc.v:42827$1007_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - cell $not $not$libresoc.v:42830$1010 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_stall_i - connect \Y $not$libresoc.v:42830$1010_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - cell $not $not$libresoc.v:42832$1012 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_stall_i - connect \Y $not$libresoc.v:42832$1012_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $not $not$libresoc.v:42834$1014 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $not$libresoc.v:42834$1014_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$libresoc.v:42809$989 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \$7 - connect \Y $or$libresoc.v:42809$989_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$libresoc.v:42812$992 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $or$libresoc.v:42812$992_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$libresoc.v:42815$995 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$15 - connect \B \$17 - connect \Y $or$libresoc.v:42815$995_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$libresoc.v:42818$998 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $or$libresoc.v:42818$998_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$libresoc.v:42820$1000 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$25 - connect \B \$27 - connect \Y $or$libresoc.v:42820$1000_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$libresoc.v:42823$1003 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $or$libresoc.v:42823$1003_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$libresoc.v:42826$1006 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$35 - connect \B \$37 - connect \Y $or$libresoc.v:42826$1006_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$libresoc.v:42833$1013 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $or$libresoc.v:42833$1013_Y - end - attribute \src "libresoc.v:42696.7-42696.20" - process $proc$libresoc.v:42696$1056 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:42758.14-42758.44" - process $proc$libresoc.v:42758$1057 - assign { } { } - assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 - sync always - sync init - update \f_badaddr_o $1\f_badaddr_o[44:0] - end - attribute \src "libresoc.v:42765.7-42765.27" - process $proc$libresoc.v:42765$1058 - assign { } { } - assign $1\f_fetch_err_o[0:0] 1'0 - sync always - sync init - update \f_fetch_err_o $1\f_fetch_err_o[0:0] - end - attribute \src "libresoc.v:42779.14-42779.42" - process $proc$libresoc.v:42779$1059 - assign { } { } - assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 - sync always - sync init - update \ibus__adr $1\ibus__adr[44:0] - end - attribute \src "libresoc.v:42784.7-42784.23" - process $proc$libresoc.v:42784$1060 - assign { } { } - assign $1\ibus__cyc[0:0] 1'0 - sync always - sync init - update \ibus__cyc $1\ibus__cyc[0:0] - end - attribute \src "libresoc.v:42793.13-42793.30" - process $proc$libresoc.v:42793$1061 - assign { } { } - assign $1\ibus__sel[7:0] 8'00000000 - sync always - sync init - update \ibus__sel $1\ibus__sel[7:0] - end - attribute \src "libresoc.v:42798.7-42798.23" - process $proc$libresoc.v:42798$1062 - assign { } { } - assign $1\ibus__stb[0:0] 1'0 - sync always - sync init - update \ibus__stb $1\ibus__stb[0:0] - end - attribute \src "libresoc.v:42802.14-42802.47" - process $proc$libresoc.v:42802$1063 - assign { } { } - assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \ibus_rdata $1\ibus_rdata[63:0] - end - attribute \src "libresoc.v:42835.3-42836.39" - process $proc$libresoc.v:42835$1015 - assign { } { } - assign $0\f_badaddr_o[44:0] \f_badaddr_o$next - sync posedge \intclk_clk - update \f_badaddr_o $0\f_badaddr_o[44:0] - end - attribute \src "libresoc.v:42837.3-42838.43" - process $proc$libresoc.v:42837$1016 - assign { } { } - assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next - sync posedge \intclk_clk - update \f_fetch_err_o $0\f_fetch_err_o[0:0] - end - attribute \src "libresoc.v:42839.3-42840.35" - process $proc$libresoc.v:42839$1017 - assign { } { } - assign $0\ibus__adr[44:0] \ibus__adr$next - sync posedge \intclk_clk - update \ibus__adr $0\ibus__adr[44:0] - end - attribute \src "libresoc.v:42841.3-42842.37" - process $proc$libresoc.v:42841$1018 - assign { } { } - assign $0\ibus_rdata[63:0] \ibus_rdata$next - sync posedge \intclk_clk - update \ibus_rdata $0\ibus_rdata[63:0] - end - attribute \src "libresoc.v:42843.3-42844.35" - process $proc$libresoc.v:42843$1019 - assign { } { } - assign $0\ibus__sel[7:0] \ibus__sel$next - sync posedge \intclk_clk - update \ibus__sel $0\ibus__sel[7:0] - end - attribute \src "libresoc.v:42845.3-42846.35" - process $proc$libresoc.v:42845$1020 - assign { } { } - assign $0\ibus__stb[0:0] \ibus__stb$next - sync posedge \intclk_clk - update \ibus__stb $0\ibus__stb[0:0] - end - attribute \src "libresoc.v:42847.3-42848.35" - process $proc$libresoc.v:42847$1021 - assign { } { } - assign $0\ibus__cyc[0:0] \ibus__cyc$next - sync posedge \intclk_clk - update \ibus__cyc $0\ibus__cyc[0:0] - end - attribute \src "libresoc.v:42849.3-42871.6" - process $proc$libresoc.v:42849$1022 - assign { } { } - assign { } { } - assign { } { } - assign $0\ibus__cyc$next[0:0]$1023 $3\ibus__cyc$next[0:0]$1026 - attribute \src "libresoc.v:42850.5-42850.29" - switch \initial - attribute \src "libresoc.v:42850.9-42850.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { \$3 \ibus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\ibus__cyc$next[0:0]$1024 $2\ibus__cyc$next[0:0]$1025 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ibus__cyc$next[0:0]$1025 1'0 - case - assign $2\ibus__cyc$next[0:0]$1025 \ibus__cyc - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\ibus__cyc$next[0:0]$1024 1'1 - case - assign $1\ibus__cyc$next[0:0]$1024 \ibus__cyc - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus__cyc$next[0:0]$1026 1'0 - case - assign $3\ibus__cyc$next[0:0]$1026 $1\ibus__cyc$next[0:0]$1024 - end - sync always - update \ibus__cyc$next $0\ibus__cyc$next[0:0]$1023 - end - attribute \src "libresoc.v:42872.3-42894.6" - process $proc$libresoc.v:42872$1027 - assign { } { } - assign { } { } - assign { } { } - assign $0\ibus__stb$next[0:0]$1028 $3\ibus__stb$next[0:0]$1031 - attribute \src "libresoc.v:42873.5-42873.29" - switch \initial - attribute \src "libresoc.v:42873.9-42873.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { \$13 \ibus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\ibus__stb$next[0:0]$1029 $2\ibus__stb$next[0:0]$1030 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - switch \$19 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ibus__stb$next[0:0]$1030 1'0 - case - assign $2\ibus__stb$next[0:0]$1030 \ibus__stb - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\ibus__stb$next[0:0]$1029 1'1 - case - assign $1\ibus__stb$next[0:0]$1029 \ibus__stb - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus__stb$next[0:0]$1031 1'0 - case - assign $3\ibus__stb$next[0:0]$1031 $1\ibus__stb$next[0:0]$1029 - end - sync always - update \ibus__stb$next $0\ibus__stb$next[0:0]$1028 - end - attribute \src "libresoc.v:42895.3-42917.6" - process $proc$libresoc.v:42895$1032 - assign { } { } - assign { } { } - assign { } { } - assign $0\ibus__sel$next[7:0]$1033 $3\ibus__sel$next[7:0]$1036 - attribute \src "libresoc.v:42896.5-42896.29" - switch \initial - attribute \src "libresoc.v:42896.9-42896.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { \$23 \ibus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\ibus__sel$next[7:0]$1034 $2\ibus__sel$next[7:0]$1035 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - switch \$29 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ibus__sel$next[7:0]$1035 8'00000000 - case - assign $2\ibus__sel$next[7:0]$1035 \ibus__sel - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\ibus__sel$next[7:0]$1034 8'11111111 - case - assign $1\ibus__sel$next[7:0]$1034 \ibus__sel - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus__sel$next[7:0]$1036 8'00000000 - case - assign $3\ibus__sel$next[7:0]$1036 $1\ibus__sel$next[7:0]$1034 - end - sync always - update \ibus__sel$next $0\ibus__sel$next[7:0]$1033 - end - attribute \src "libresoc.v:42918.3-42937.6" - process $proc$libresoc.v:42918$1037 - assign { } { } - assign { } { } - assign { } { } - assign $0\ibus_rdata$next[63:0]$1038 $3\ibus_rdata$next[63:0]$1041 - attribute \src "libresoc.v:42919.5-42919.29" - switch \initial - attribute \src "libresoc.v:42919.9-42919.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { \$33 \ibus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\ibus_rdata$next[63:0]$1039 $2\ibus_rdata$next[63:0]$1040 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - switch \$39 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ibus_rdata$next[63:0]$1040 \ibus__dat_r - case - assign $2\ibus_rdata$next[63:0]$1040 \ibus_rdata - end - case - assign $1\ibus_rdata$next[63:0]$1039 \ibus_rdata - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus_rdata$next[63:0]$1041 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\ibus_rdata$next[63:0]$1041 $1\ibus_rdata$next[63:0]$1039 - end - sync always - update \ibus_rdata$next $0\ibus_rdata$next[63:0]$1038 - end - attribute \src "libresoc.v:42938.3-42955.6" - process $proc$libresoc.v:42938$1042 - assign { } { } - assign { } { } - assign { } { } - assign $0\ibus__adr$next[44:0]$1043 $2\ibus__adr$next[44:0]$1045 - attribute \src "libresoc.v:42939.5-42939.29" - switch \initial - attribute \src "libresoc.v:42939.9-42939.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { \$43 \ibus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign $1\ibus__adr$next[44:0]$1044 \ibus__adr - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\ibus__adr$next[44:0]$1044 \a_pc_i [47:3] - case - assign $1\ibus__adr$next[44:0]$1044 \ibus__adr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ibus__adr$next[44:0]$1045 45'000000000000000000000000000000000000000000000 - case - assign $2\ibus__adr$next[44:0]$1045 $1\ibus__adr$next[44:0]$1044 - end - sync always - update \ibus__adr$next $0\ibus__adr$next[44:0]$1043 - end - attribute \src "libresoc.v:42956.3-42973.6" - process $proc$libresoc.v:42956$1046 - assign { } { } - assign { } { } - assign { } { } - assign $0\f_fetch_err_o$next[0:0]$1047 $2\f_fetch_err_o$next[0:0]$1049 - attribute \src "libresoc.v:42957.5-42957.29" - switch \initial - attribute \src "libresoc.v:42957.9-42957.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - switch { \$47 \$45 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\f_fetch_err_o$next[0:0]$1048 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\f_fetch_err_o$next[0:0]$1048 1'0 - case - assign $1\f_fetch_err_o$next[0:0]$1048 \f_fetch_err_o - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\f_fetch_err_o$next[0:0]$1049 1'0 - case - assign $2\f_fetch_err_o$next[0:0]$1049 $1\f_fetch_err_o$next[0:0]$1048 - end - sync always - update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$1047 - end - attribute \src "libresoc.v:42974.3-42988.6" - process $proc$libresoc.v:42974$1050 - assign { } { } - assign { } { } - assign { } { } - assign $0\f_badaddr_o$next[44:0]$1051 $2\f_badaddr_o$next[44:0]$1053 - attribute \src "libresoc.v:42975.5-42975.29" - switch \initial - attribute \src "libresoc.v:42975.9-42975.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - switch { \$51 \$49 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\f_badaddr_o$next[44:0]$1052 \ibus__adr - case - assign $1\f_badaddr_o$next[44:0]$1052 \f_badaddr_o - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\f_badaddr_o$next[44:0]$1053 45'000000000000000000000000000000000000000000000 - case - assign $2\f_badaddr_o$next[44:0]$1053 $1\f_badaddr_o$next[44:0]$1052 - end - sync always - update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$1051 - end - attribute \src "libresoc.v:42989.3-43000.6" - process $proc$libresoc.v:42989$1054 - assign { } { } - assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] - attribute \src "libresoc.v:42990.5-42990.29" - switch \initial - attribute \src "libresoc.v:42990.9-42990.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - switch \f_fetch_err_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\f_busy_o[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\f_busy_o[0:0] \ibus__cyc - end - sync always - update \f_busy_o $0\f_busy_o[0:0] - end - attribute \src "libresoc.v:43001.3-43013.6" - process $proc$libresoc.v:43001$1055 - assign { } { } - assign { } { } - assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] - attribute \src "libresoc.v:43002.5-43002.29" - switch \initial - attribute \src "libresoc.v:43002.9-43002.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - switch \f_fetch_err_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $1\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\f_instr_o[63:0] \ibus_rdata - end - sync always - update \f_instr_o $0\f_instr_o[63:0] - end - connect \$9 $or$libresoc.v:42809$989_Y - connect \$11 $not$libresoc.v:42810$990_Y - connect \$13 $and$libresoc.v:42811$991_Y - connect \$15 $or$libresoc.v:42812$992_Y - connect \$17 $not$libresoc.v:42813$993_Y - connect \$1 $not$libresoc.v:42814$994_Y - connect \$19 $or$libresoc.v:42815$995_Y - connect \$21 $not$libresoc.v:42816$996_Y - connect \$23 $and$libresoc.v:42817$997_Y - connect \$25 $or$libresoc.v:42818$998_Y - connect \$27 $not$libresoc.v:42819$999_Y - connect \$29 $or$libresoc.v:42820$1000_Y - connect \$31 $not$libresoc.v:42821$1001_Y - connect \$33 $and$libresoc.v:42822$1002_Y - connect \$35 $or$libresoc.v:42823$1003_Y - connect \$37 $not$libresoc.v:42824$1004_Y - connect \$3 $and$libresoc.v:42825$1005_Y - connect \$39 $or$libresoc.v:42826$1006_Y - connect \$41 $not$libresoc.v:42827$1007_Y - connect \$43 $and$libresoc.v:42828$1008_Y - connect \$45 $and$libresoc.v:42829$1009_Y - connect \$47 $not$libresoc.v:42830$1010_Y - connect \$49 $and$libresoc.v:42831$1011_Y - connect \$51 $not$libresoc.v:42832$1012_Y - connect \$5 $or$libresoc.v:42833$1013_Y - connect \$7 $not$libresoc.v:42834$1014_Y - connect \a_stall_i 1'0 - connect \f_stall_i 1'0 - connect \a_busy_o \ibus__cyc -end -attribute \src "libresoc.v:43021.1-44772.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.jtag" -attribute \generator "nMigen" -module \jtag - attribute \src "libresoc.v:44048.3-44071.6" - wire $0\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:44409.3-44424.6" - wire $0\TAP_tdo[0:0] - attribute \src "libresoc.v:44206.3-44238.6" - wire width 4 $0\dmi0_addr_i$next[3:0]$1275 - attribute \src "libresoc.v:43912.3-43913.39" - wire width 4 $0\dmi0_addr_i[3:0] - attribute \src "libresoc.v:44632.3-44648.6" - wire $0\dmi0_addrsr__oe$next[0:0]$1358 - attribute \src "libresoc.v:43932.3-43933.47" - wire $0\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:44649.3-44669.6" - wire width 8 $0\dmi0_addrsr_reg$next[7:0]$1362 - attribute \src "libresoc.v:43930.3-43931.47" - wire width 8 $0\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:44614.3-44622.6" - wire $0\dmi0_addrsr_update_core$next[0:0]$1352 - attribute \src "libresoc.v:43936.3-43937.63" - wire $0\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:44623.3-44631.6" - wire $0\dmi0_addrsr_update_core_prev$next[0:0]$1355 - attribute \src "libresoc.v:43934.3-43935.73" - wire $0\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:44319.3-44339.6" - wire width 64 $0\dmi0_datasr__i$next[63:0]$1293 - attribute \src "libresoc.v:43906.3-43907.45" - wire width 64 $0\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:44010.3-44026.6" - wire width 2 $0\dmi0_datasr__oe$next[1:0]$1242 - attribute \src "libresoc.v:43924.3-43925.47" - wire width 2 $0\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:44027.3-44047.6" - wire width 64 $0\dmi0_datasr_reg$next[63:0]$1246 - attribute \src "libresoc.v:43922.3-43923.47" - wire width 64 $0\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:44670.3-44678.6" - wire $0\dmi0_datasr_update_core$next[0:0]$1367 - attribute \src "libresoc.v:43928.3-43929.63" - wire $0\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:44001.3-44009.6" - wire $0\dmi0_datasr_update_core_prev$next[0:0]$1239 - attribute \src "libresoc.v:43926.3-43927.73" - wire $0\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:44292.3-44318.6" - wire width 64 $0\dmi0_din$next[63:0]$1288 - attribute \src "libresoc.v:43908.3-43909.33" - wire width 64 $0\dmi0_din[63:0] - attribute \src "libresoc.v:44239.3-44291.6" - wire width 3 $0\fsm_state$275$next[2:0]$1281 - attribute \src "libresoc.v:43910.3-43911.45" - wire width 3 $0\fsm_state$275[2:0]$1210 - attribute \src "libresoc.v:43421.13-43421.35" - wire width 3 $0\fsm_state$275[2:0]$1383 - attribute \src "libresoc.v:44105.3-44157.6" - wire width 3 $0\fsm_state$next[2:0]$1258 - attribute \src "libresoc.v:43918.3-43919.35" - wire width 3 $0\fsm_state[2:0] - attribute \src "libresoc.v:43022.7-43022.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:44425.3-44445.6" - wire width 50 $0\io_bd$next[49:0]$1303 - attribute \src "libresoc.v:43962.3-43963.27" - wire width 50 $0\io_bd[49:0] - attribute \src "libresoc.v:44340.3-44408.6" - wire width 50 $0\io_sr$next[49:0]$1298 - attribute \src "libresoc.v:43964.3-43965.27" - wire width 50 $0\io_sr[49:0] - attribute \src "libresoc.v:44072.3-44104.6" - wire width 29 $0\jtag_wb__adr$next[28:0]$1252 - attribute \src "libresoc.v:43920.3-43921.41" - wire width 29 $0\jtag_wb__adr[28:0] - attribute \src "libresoc.v:44158.3-44184.6" - wire width 64 $0\jtag_wb__dat_w$next[63:0]$1265 - attribute \src "libresoc.v:43916.3-43917.45" - wire width 64 $0\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:44520.3-44536.6" - wire $0\jtag_wb_addrsr__oe$next[0:0]$1328 - attribute \src "libresoc.v:43948.3-43949.53" - wire $0\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:44537.3-44557.6" - wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$1332 - attribute \src "libresoc.v:43946.3-43947.53" - wire width 29 $0\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:44502.3-44510.6" - wire $0\jtag_wb_addrsr_update_core$next[0:0]$1322 - attribute \src "libresoc.v:43952.3-43953.69" - wire $0\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:44511.3-44519.6" - wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1325 - attribute \src "libresoc.v:43950.3-43951.79" - wire $0\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:44185.3-44205.6" - wire width 64 $0\jtag_wb_datasr__i$next[63:0]$1270 - attribute \src "libresoc.v:43914.3-43915.51" - wire width 64 $0\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:44576.3-44592.6" - wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$1343 - attribute \src "libresoc.v:43940.3-43941.53" - wire width 2 $0\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:44593.3-44613.6" - wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$1347 - attribute \src "libresoc.v:43938.3-43939.53" - wire width 64 $0\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:44558.3-44566.6" - wire $0\jtag_wb_datasr_update_core$next[0:0]$1337 - attribute \src "libresoc.v:43944.3-43945.69" - wire $0\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:44567.3-44575.6" - wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$1340 - attribute \src "libresoc.v:43942.3-43943.79" - wire $0\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:44464.3-44480.6" - wire $0\sr0__oe$next[0:0]$1313 - attribute \src "libresoc.v:43956.3-43957.31" - wire $0\sr0__oe[0:0] - attribute \src "libresoc.v:44481.3-44501.6" - wire width 3 $0\sr0_reg$next[2:0]$1317 - attribute \src "libresoc.v:43954.3-43955.31" - wire width 3 $0\sr0_reg[2:0] - attribute \src "libresoc.v:44446.3-44454.6" - wire $0\sr0_update_core$next[0:0]$1307 - attribute \src "libresoc.v:43960.3-43961.47" - wire $0\sr0_update_core[0:0] - attribute \src "libresoc.v:44455.3-44463.6" - wire $0\sr0_update_core_prev$next[0:0]$1310 - attribute \src "libresoc.v:43958.3-43959.57" - wire $0\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:44048.3-44071.6" - wire $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:44409.3-44424.6" - wire $1\TAP_tdo[0:0] - attribute \src "libresoc.v:44206.3-44238.6" - wire width 4 $1\dmi0_addr_i$next[3:0]$1276 - attribute \src "libresoc.v:43346.13-43346.31" - wire width 4 $1\dmi0_addr_i[3:0] - attribute \src "libresoc.v:44632.3-44648.6" - wire $1\dmi0_addrsr__oe$next[0:0]$1359 - attribute \src "libresoc.v:43354.7-43354.29" - wire $1\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:44649.3-44669.6" - wire width 8 $1\dmi0_addrsr_reg$next[7:0]$1363 - attribute \src "libresoc.v:43362.13-43362.36" - wire width 8 $1\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:44614.3-44622.6" - wire $1\dmi0_addrsr_update_core$next[0:0]$1353 - attribute \src "libresoc.v:43370.7-43370.37" - wire $1\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:44623.3-44631.6" - wire $1\dmi0_addrsr_update_core_prev$next[0:0]$1356 - attribute \src "libresoc.v:43374.7-43374.42" - wire $1\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:44319.3-44339.6" - wire width 64 $1\dmi0_datasr__i$next[63:0]$1294 - attribute \src "libresoc.v:43378.14-43378.51" - wire width 64 $1\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:44010.3-44026.6" - wire width 2 $1\dmi0_datasr__oe$next[1:0]$1243 - attribute \src "libresoc.v:43384.13-43384.35" - wire width 2 $1\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:44027.3-44047.6" - wire width 64 $1\dmi0_datasr_reg$next[63:0]$1247 - attribute \src "libresoc.v:43392.14-43392.52" - wire width 64 $1\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:44670.3-44678.6" - wire $1\dmi0_datasr_update_core$next[0:0]$1368 - attribute \src "libresoc.v:43400.7-43400.37" - wire $1\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:44001.3-44009.6" - wire $1\dmi0_datasr_update_core_prev$next[0:0]$1240 - attribute \src "libresoc.v:43404.7-43404.42" - wire $1\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:44292.3-44318.6" - wire width 64 $1\dmi0_din$next[63:0]$1289 - attribute \src "libresoc.v:43409.14-43409.45" - wire width 64 $1\dmi0_din[63:0] - attribute \src "libresoc.v:44239.3-44291.6" - wire width 3 $1\fsm_state$275$next[2:0]$1282 - attribute \src "libresoc.v:44105.3-44157.6" - wire width 3 $1\fsm_state$next[2:0]$1259 - attribute \src "libresoc.v:43419.13-43419.29" - wire width 3 $1\fsm_state[2:0] - attribute \src "libresoc.v:44425.3-44445.6" - wire width 50 $1\io_bd$next[49:0]$1304 - attribute \src "libresoc.v:43623.14-43623.39" - wire width 50 $1\io_bd[49:0] - attribute \src "libresoc.v:44340.3-44408.6" - wire width 50 $1\io_sr$next[49:0]$1299 - attribute \src "libresoc.v:43635.14-43635.39" - wire width 50 $1\io_sr[49:0] - attribute \src "libresoc.v:44072.3-44104.6" - wire width 29 $1\jtag_wb__adr$next[28:0]$1253 - attribute \src "libresoc.v:43644.14-43644.41" - wire width 29 $1\jtag_wb__adr[28:0] - attribute \src "libresoc.v:44158.3-44184.6" - wire width 64 $1\jtag_wb__dat_w$next[63:0]$1266 - attribute \src "libresoc.v:43653.14-43653.51" - wire width 64 $1\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:44520.3-44536.6" - wire $1\jtag_wb_addrsr__oe$next[0:0]$1329 - attribute \src "libresoc.v:43667.7-43667.32" - wire $1\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:44537.3-44557.6" - wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$1333 - attribute \src "libresoc.v:43675.14-43675.47" - wire width 29 $1\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:44502.3-44510.6" - wire $1\jtag_wb_addrsr_update_core$next[0:0]$1323 - attribute \src "libresoc.v:43683.7-43683.40" - wire $1\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:44511.3-44519.6" - wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1326 - attribute \src "libresoc.v:43687.7-43687.45" - wire $1\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:44185.3-44205.6" - wire width 64 $1\jtag_wb_datasr__i$next[63:0]$1271 - attribute \src "libresoc.v:43691.14-43691.54" - wire width 64 $1\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:44576.3-44592.6" - wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$1344 - attribute \src "libresoc.v:43697.13-43697.38" - wire width 2 $1\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:44593.3-44613.6" - wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$1348 - attribute \src "libresoc.v:43705.14-43705.55" - wire width 64 $1\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:44558.3-44566.6" - wire $1\jtag_wb_datasr_update_core$next[0:0]$1338 - attribute \src "libresoc.v:43713.7-43713.40" - wire $1\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:44567.3-44575.6" - wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$1341 - attribute \src "libresoc.v:43717.7-43717.45" - wire $1\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:44464.3-44480.6" - wire $1\sr0__oe$next[0:0]$1314 - attribute \src "libresoc.v:43733.7-43733.21" - wire $1\sr0__oe[0:0] - attribute \src "libresoc.v:44481.3-44501.6" - wire width 3 $1\sr0_reg$next[2:0]$1318 - attribute \src "libresoc.v:43741.13-43741.27" - wire width 3 $1\sr0_reg[2:0] - attribute \src "libresoc.v:44446.3-44454.6" - wire $1\sr0_update_core$next[0:0]$1308 - attribute \src "libresoc.v:43749.7-43749.29" - wire $1\sr0_update_core[0:0] - attribute \src "libresoc.v:44455.3-44463.6" - wire $1\sr0_update_core_prev$next[0:0]$1311 - attribute \src "libresoc.v:43753.7-43753.34" - wire $1\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:44206.3-44238.6" - wire width 4 $2\dmi0_addr_i$next[3:0]$1277 - attribute \src "libresoc.v:44632.3-44648.6" - wire $2\dmi0_addrsr__oe$next[0:0]$1360 - attribute \src "libresoc.v:44649.3-44669.6" - wire width 8 $2\dmi0_addrsr_reg$next[7:0]$1364 - attribute \src "libresoc.v:44319.3-44339.6" - wire width 64 $2\dmi0_datasr__i$next[63:0]$1295 - attribute \src "libresoc.v:44010.3-44026.6" - wire width 2 $2\dmi0_datasr__oe$next[1:0]$1244 - attribute \src "libresoc.v:44027.3-44047.6" - wire width 64 $2\dmi0_datasr_reg$next[63:0]$1248 - attribute \src "libresoc.v:44292.3-44318.6" - wire width 64 $2\dmi0_din$next[63:0]$1290 - attribute \src "libresoc.v:44239.3-44291.6" - wire width 3 $2\fsm_state$275$next[2:0]$1283 - attribute \src "libresoc.v:44105.3-44157.6" - wire width 3 $2\fsm_state$next[2:0]$1260 - attribute \src "libresoc.v:44425.3-44445.6" - wire width 50 $2\io_bd$next[49:0]$1305 - attribute \src "libresoc.v:44340.3-44408.6" - wire width 50 $2\io_sr$next[49:0]$1300 - attribute \src "libresoc.v:44072.3-44104.6" - wire width 29 $2\jtag_wb__adr$next[28:0]$1254 - attribute \src "libresoc.v:44158.3-44184.6" - wire width 64 $2\jtag_wb__dat_w$next[63:0]$1267 - attribute \src "libresoc.v:44520.3-44536.6" - wire $2\jtag_wb_addrsr__oe$next[0:0]$1330 - attribute \src "libresoc.v:44537.3-44557.6" - wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$1334 - attribute \src "libresoc.v:44185.3-44205.6" - wire width 64 $2\jtag_wb_datasr__i$next[63:0]$1272 - attribute \src "libresoc.v:44576.3-44592.6" - wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$1345 - attribute \src "libresoc.v:44593.3-44613.6" - wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$1349 - attribute \src "libresoc.v:44464.3-44480.6" - wire $2\sr0__oe$next[0:0]$1315 - attribute \src "libresoc.v:44481.3-44501.6" - wire width 3 $2\sr0_reg$next[2:0]$1319 - attribute \src "libresoc.v:44206.3-44238.6" - wire width 4 $3\dmi0_addr_i$next[3:0]$1278 - attribute \src "libresoc.v:44649.3-44669.6" - wire width 8 $3\dmi0_addrsr_reg$next[7:0]$1365 - attribute \src "libresoc.v:44319.3-44339.6" - wire width 64 $3\dmi0_datasr__i$next[63:0]$1296 - attribute \src "libresoc.v:44027.3-44047.6" - wire width 64 $3\dmi0_datasr_reg$next[63:0]$1249 - attribute \src "libresoc.v:44292.3-44318.6" - wire width 64 $3\dmi0_din$next[63:0]$1291 - attribute \src "libresoc.v:44239.3-44291.6" - wire width 3 $3\fsm_state$275$next[2:0]$1284 - attribute \src "libresoc.v:44105.3-44157.6" - wire width 3 $3\fsm_state$next[2:0]$1261 - attribute \src "libresoc.v:44072.3-44104.6" - wire width 29 $3\jtag_wb__adr$next[28:0]$1255 - attribute \src "libresoc.v:44158.3-44184.6" - wire width 64 $3\jtag_wb__dat_w$next[63:0]$1268 - attribute \src "libresoc.v:44537.3-44557.6" - wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$1335 - attribute \src "libresoc.v:44185.3-44205.6" - wire width 64 $3\jtag_wb_datasr__i$next[63:0]$1273 - attribute \src "libresoc.v:44593.3-44613.6" - wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$1350 - attribute \src "libresoc.v:44481.3-44501.6" - wire width 3 $3\sr0_reg$next[2:0]$1320 - attribute \src "libresoc.v:44206.3-44238.6" - wire width 4 $4\dmi0_addr_i$next[3:0]$1279 - attribute \src "libresoc.v:44239.3-44291.6" - wire width 3 $4\fsm_state$275$next[2:0]$1285 - attribute \src "libresoc.v:44105.3-44157.6" - wire width 3 $4\fsm_state$next[2:0]$1262 - attribute \src "libresoc.v:44072.3-44104.6" - wire width 29 $4\jtag_wb__adr$next[28:0]$1256 - attribute \src "libresoc.v:44239.3-44291.6" - wire width 3 $5\fsm_state$275$next[2:0]$1286 - attribute \src "libresoc.v:44105.3-44157.6" - wire width 3 $5\fsm_state$next[2:0]$1263 - attribute \src "libresoc.v:43858.19-43858.110" - wire width 30 $add$libresoc.v:43858$1158_Y - attribute \src "libresoc.v:43859.19-43859.110" - wire width 30 $add$libresoc.v:43859$1159_Y - attribute \src "libresoc.v:43866.19-43866.109" - wire width 5 $add$libresoc.v:43866$1167_Y - attribute \src "libresoc.v:43867.19-43867.109" - wire width 5 $add$libresoc.v:43867$1168_Y - attribute \src "libresoc.v:43791.19-43791.110" - wire $and$libresoc.v:43791$1091_Y - attribute \src "libresoc.v:43798.19-43798.110" - wire $and$libresoc.v:43798$1098_Y - attribute \src "libresoc.v:43801.19-43801.114" - wire $and$libresoc.v:43801$1101_Y - attribute \src "libresoc.v:43803.19-43803.112" - wire $and$libresoc.v:43803$1103_Y - attribute \src "libresoc.v:43805.19-43805.113" - wire $and$libresoc.v:43805$1105_Y - attribute \src "libresoc.v:43807.19-43807.121" - wire $and$libresoc.v:43807$1107_Y - attribute \src "libresoc.v:43811.19-43811.114" - wire $and$libresoc.v:43811$1111_Y - attribute \src "libresoc.v:43813.19-43813.112" - wire $and$libresoc.v:43813$1113_Y - attribute \src "libresoc.v:43815.19-43815.113" - wire $and$libresoc.v:43815$1115_Y - attribute \src "libresoc.v:43817.19-43817.132" - wire $and$libresoc.v:43817$1117_Y - attribute \src "libresoc.v:43820.18-43820.108" - wire $and$libresoc.v:43820$1120_Y - attribute \src "libresoc.v:43823.19-43823.114" - wire $and$libresoc.v:43823$1123_Y - attribute \src "libresoc.v:43825.19-43825.112" - wire $and$libresoc.v:43825$1125_Y - attribute \src "libresoc.v:43827.19-43827.113" - wire $and$libresoc.v:43827$1127_Y - attribute \src "libresoc.v:43829.19-43829.132" - wire $and$libresoc.v:43829$1129_Y - attribute \src "libresoc.v:43831.18-43831.110" - wire $and$libresoc.v:43831$1131_Y - attribute \src "libresoc.v:43833.19-43833.114" - wire $and$libresoc.v:43833$1133_Y - attribute \src "libresoc.v:43835.19-43835.112" - wire $and$libresoc.v:43835$1135_Y - attribute \src "libresoc.v:43837.19-43837.113" - wire $and$libresoc.v:43837$1137_Y - attribute \src "libresoc.v:43839.19-43839.129" - wire $and$libresoc.v:43839$1139_Y - attribute \src "libresoc.v:43844.19-43844.114" - wire $and$libresoc.v:43844$1144_Y - attribute \src "libresoc.v:43846.19-43846.112" - wire $and$libresoc.v:43846$1146_Y - attribute \src "libresoc.v:43848.19-43848.113" - wire $and$libresoc.v:43848$1148_Y - attribute \src "libresoc.v:43850.19-43850.129" - wire $and$libresoc.v:43850$1150_Y - attribute \src "libresoc.v:43870.18-43870.108" - wire $and$libresoc.v:43870$1171_Y - attribute \src "libresoc.v:43871.18-43871.111" - wire $and$libresoc.v:43871$1172_Y - attribute \src "libresoc.v:43895.17-43895.110" - wire $and$libresoc.v:43895$1196_Y - attribute \src "libresoc.v:43764.17-43764.110" - wire $eq$libresoc.v:43764$1064_Y - attribute \src "libresoc.v:43775.18-43775.111" - wire $eq$libresoc.v:43775$1075_Y - attribute \src "libresoc.v:43788.19-43788.112" - wire $eq$libresoc.v:43788$1088_Y - attribute \src "libresoc.v:43789.19-43789.112" - wire $eq$libresoc.v:43789$1089_Y - attribute \src "libresoc.v:43792.19-43792.112" - wire $eq$libresoc.v:43792$1092_Y - attribute \src "libresoc.v:43793.19-43793.112" - wire $eq$libresoc.v:43793$1093_Y - attribute \src "libresoc.v:43795.19-43795.112" - wire $eq$libresoc.v:43795$1095_Y - attribute \src "libresoc.v:43797.18-43797.111" - wire $eq$libresoc.v:43797$1097_Y - attribute \src "libresoc.v:43799.19-43799.112" - wire $eq$libresoc.v:43799$1099_Y - attribute \src "libresoc.v:43809.19-43809.112" - wire $eq$libresoc.v:43809$1109_Y - attribute \src "libresoc.v:43818.19-43818.112" - wire $eq$libresoc.v:43818$1118_Y - attribute \src "libresoc.v:43819.17-43819.110" - wire $eq$libresoc.v:43819$1119_Y - attribute \src "libresoc.v:43821.19-43821.112" - wire $eq$libresoc.v:43821$1121_Y - attribute \src "libresoc.v:43830.19-43830.112" - wire $eq$libresoc.v:43830$1130_Y - attribute \src "libresoc.v:43840.19-43840.112" - wire $eq$libresoc.v:43840$1140_Y - attribute \src "libresoc.v:43841.19-43841.112" - wire $eq$libresoc.v:43841$1141_Y - attribute \src "libresoc.v:43842.18-43842.111" - wire $eq$libresoc.v:43842$1142_Y - attribute \src "libresoc.v:43851.19-43851.108" - wire $eq$libresoc.v:43851$1151_Y - attribute \src "libresoc.v:43853.18-43853.111" - wire $eq$libresoc.v:43853$1153_Y - attribute \src "libresoc.v:43854.19-43854.108" - wire $eq$libresoc.v:43854$1154_Y - attribute \src "libresoc.v:43855.19-43855.108" - wire $eq$libresoc.v:43855$1155_Y - attribute \src "libresoc.v:43857.19-43857.108" - wire $eq$libresoc.v:43857$1157_Y - attribute \src "libresoc.v:43861.19-43861.114" - wire $eq$libresoc.v:43861$1162_Y - attribute \src "libresoc.v:43862.19-43862.114" - wire $eq$libresoc.v:43862$1163_Y - attribute \src "libresoc.v:43865.19-43865.114" - wire $eq$libresoc.v:43865$1166_Y - attribute \src "libresoc.v:43868.18-43868.111" - wire $eq$libresoc.v:43868$1169_Y - attribute \src "libresoc.v:43872.18-43872.111" - wire $eq$libresoc.v:43872$1173_Y - attribute \src "libresoc.v:43873.17-43873.110" - wire $eq$libresoc.v:43873$1174_Y - attribute \src "libresoc.v:43874.18-43874.111" - wire $eq$libresoc.v:43874$1175_Y - attribute \src "libresoc.v:43860.19-43860.98" - wire width 8 $extend$libresoc.v:43860$1160_Y - attribute \src "libresoc.v:43800.19-43800.109" - wire $ne$libresoc.v:43800$1100_Y - attribute \src "libresoc.v:43802.19-43802.109" - wire $ne$libresoc.v:43802$1102_Y - attribute \src "libresoc.v:43804.19-43804.109" - wire $ne$libresoc.v:43804$1104_Y - attribute \src "libresoc.v:43810.19-43810.120" - wire $ne$libresoc.v:43810$1110_Y - attribute \src "libresoc.v:43812.19-43812.120" - wire $ne$libresoc.v:43812$1112_Y - attribute \src "libresoc.v:43814.19-43814.120" - wire $ne$libresoc.v:43814$1114_Y - attribute \src "libresoc.v:43822.19-43822.120" - wire $ne$libresoc.v:43822$1122_Y - attribute \src "libresoc.v:43824.19-43824.120" - wire $ne$libresoc.v:43824$1124_Y - attribute \src "libresoc.v:43826.19-43826.120" - wire $ne$libresoc.v:43826$1126_Y - attribute \src "libresoc.v:43832.19-43832.117" - wire $ne$libresoc.v:43832$1132_Y - attribute \src "libresoc.v:43834.19-43834.117" - wire $ne$libresoc.v:43834$1134_Y - attribute \src "libresoc.v:43836.19-43836.117" - wire $ne$libresoc.v:43836$1136_Y - attribute \src "libresoc.v:43843.19-43843.117" - wire $ne$libresoc.v:43843$1143_Y - attribute \src "libresoc.v:43845.19-43845.117" - wire $ne$libresoc.v:43845$1145_Y - attribute \src "libresoc.v:43847.19-43847.117" - wire $ne$libresoc.v:43847$1147_Y - attribute \src "libresoc.v:43806.19-43806.110" - wire $not$libresoc.v:43806$1106_Y - attribute \src "libresoc.v:43816.19-43816.121" - wire $not$libresoc.v:43816$1116_Y - attribute \src "libresoc.v:43828.19-43828.121" - wire $not$libresoc.v:43828$1128_Y - attribute \src "libresoc.v:43838.19-43838.118" - wire $not$libresoc.v:43838$1138_Y - attribute \src "libresoc.v:43849.19-43849.118" - wire $not$libresoc.v:43849$1149_Y - attribute \src "libresoc.v:43852.19-43852.98" - wire $not$libresoc.v:43852$1152_Y - attribute \src "libresoc.v:43786.18-43786.103" - wire $or$libresoc.v:43786$1086_Y - attribute \src "libresoc.v:43790.19-43790.107" - wire $or$libresoc.v:43790$1090_Y - attribute \src "libresoc.v:43794.19-43794.107" - wire $or$libresoc.v:43794$1094_Y - attribute \src "libresoc.v:43796.19-43796.107" - wire $or$libresoc.v:43796$1096_Y - attribute \src "libresoc.v:43808.18-43808.104" - wire $or$libresoc.v:43808$1108_Y - attribute \src "libresoc.v:43856.19-43856.105" - wire $or$libresoc.v:43856$1156_Y - attribute \src "libresoc.v:43863.18-43863.104" - wire $or$libresoc.v:43863$1164_Y - attribute \src "libresoc.v:43864.19-43864.105" - wire $or$libresoc.v:43864$1165_Y - attribute \src "libresoc.v:43869.18-43869.104" - wire $or$libresoc.v:43869$1170_Y - attribute \src "libresoc.v:43884.17-43884.101" - wire $or$libresoc.v:43884$1185_Y - attribute \src "libresoc.v:43860.19-43860.98" - wire width 8 $pos$libresoc.v:43860$1161_Y - attribute \src "libresoc.v:43765.18-43765.135" - wire $ternary$libresoc.v:43765$1065_Y - attribute \src "libresoc.v:43766.19-43766.135" - wire $ternary$libresoc.v:43766$1066_Y - attribute \src "libresoc.v:43767.19-43767.136" - wire $ternary$libresoc.v:43767$1067_Y - attribute \src "libresoc.v:43768.19-43768.137" - wire $ternary$libresoc.v:43768$1068_Y - attribute \src "libresoc.v:43769.19-43769.136" - wire $ternary$libresoc.v:43769$1069_Y - attribute \src "libresoc.v:43770.19-43770.137" - wire $ternary$libresoc.v:43770$1070_Y - attribute \src "libresoc.v:43771.19-43771.137" - wire $ternary$libresoc.v:43771$1071_Y - attribute \src "libresoc.v:43772.19-43772.136" - wire $ternary$libresoc.v:43772$1072_Y - attribute \src "libresoc.v:43773.19-43773.137" - wire $ternary$libresoc.v:43773$1073_Y - attribute \src "libresoc.v:43774.19-43774.137" - wire $ternary$libresoc.v:43774$1074_Y - attribute \src "libresoc.v:43776.19-43776.136" - wire $ternary$libresoc.v:43776$1076_Y - attribute \src "libresoc.v:43777.19-43777.137" - wire $ternary$libresoc.v:43777$1077_Y - attribute \src "libresoc.v:43778.19-43778.137" - wire $ternary$libresoc.v:43778$1078_Y - attribute \src "libresoc.v:43779.19-43779.136" - wire $ternary$libresoc.v:43779$1079_Y - attribute \src "libresoc.v:43780.19-43780.137" - wire $ternary$libresoc.v:43780$1080_Y - attribute \src "libresoc.v:43781.19-43781.137" - wire $ternary$libresoc.v:43781$1081_Y - attribute \src "libresoc.v:43782.19-43782.136" - wire $ternary$libresoc.v:43782$1082_Y - attribute \src "libresoc.v:43783.19-43783.137" - wire $ternary$libresoc.v:43783$1083_Y - attribute \src "libresoc.v:43784.19-43784.137" - wire $ternary$libresoc.v:43784$1084_Y - attribute \src "libresoc.v:43785.19-43785.136" - wire $ternary$libresoc.v:43785$1085_Y - attribute \src "libresoc.v:43787.19-43787.137" - wire $ternary$libresoc.v:43787$1087_Y - attribute \src "libresoc.v:43875.18-43875.130" - wire $ternary$libresoc.v:43875$1176_Y - attribute \src "libresoc.v:43876.18-43876.131" - wire $ternary$libresoc.v:43876$1177_Y - attribute \src "libresoc.v:43877.18-43877.134" - wire $ternary$libresoc.v:43877$1178_Y - attribute \src "libresoc.v:43878.18-43878.133" - wire $ternary$libresoc.v:43878$1179_Y - attribute \src "libresoc.v:43879.18-43879.134" - wire $ternary$libresoc.v:43879$1180_Y - attribute \src "libresoc.v:43880.18-43880.134" - wire $ternary$libresoc.v:43880$1181_Y - attribute \src "libresoc.v:43881.18-43881.133" - wire $ternary$libresoc.v:43881$1182_Y - attribute \src "libresoc.v:43882.18-43882.134" - wire $ternary$libresoc.v:43882$1183_Y - attribute \src "libresoc.v:43883.18-43883.134" - wire $ternary$libresoc.v:43883$1184_Y - attribute \src "libresoc.v:43885.18-43885.133" - wire $ternary$libresoc.v:43885$1186_Y - attribute \src "libresoc.v:43886.18-43886.135" - wire $ternary$libresoc.v:43886$1187_Y - attribute \src "libresoc.v:43887.18-43887.135" - wire $ternary$libresoc.v:43887$1188_Y - attribute \src "libresoc.v:43888.18-43888.134" - wire $ternary$libresoc.v:43888$1189_Y - attribute \src "libresoc.v:43889.18-43889.135" - wire $ternary$libresoc.v:43889$1190_Y - attribute \src "libresoc.v:43890.18-43890.135" - wire $ternary$libresoc.v:43890$1191_Y - attribute \src "libresoc.v:43891.18-43891.134" - wire $ternary$libresoc.v:43891$1192_Y - attribute \src "libresoc.v:43892.18-43892.135" - wire $ternary$libresoc.v:43892$1193_Y - attribute \src "libresoc.v:43893.18-43893.135" - wire $ternary$libresoc.v:43893$1194_Y - attribute \src "libresoc.v:43894.18-43894.134" - wire $ternary$libresoc.v:43894$1195_Y - attribute \src "libresoc.v:43896.18-43896.135" - wire $ternary$libresoc.v:43896$1197_Y - attribute \src "libresoc.v:43897.18-43897.135" - wire $ternary$libresoc.v:43897$1198_Y - attribute \src "libresoc.v:43898.18-43898.134" - wire $ternary$libresoc.v:43898$1199_Y - attribute \src "libresoc.v:43899.18-43899.135" - wire $ternary$libresoc.v:43899$1200_Y - attribute \src "libresoc.v:43900.18-43900.135" - wire $ternary$libresoc.v:43900$1201_Y - attribute \src "libresoc.v:43901.18-43901.134" - wire $ternary$libresoc.v:43901$1202_Y - attribute \src "libresoc.v:43902.18-43902.135" - wire $ternary$libresoc.v:43902$1203_Y - attribute \src "libresoc.v:43903.18-43903.135" - wire $ternary$libresoc.v:43903$1204_Y - attribute \src "libresoc.v:43904.18-43904.134" - wire $ternary$libresoc.v:43904$1205_Y - attribute \src "libresoc.v:43905.18-43905.135" - wire $ternary$libresoc.v:43905$1206_Y - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - wire \$101 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - wire \$103 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire \$105 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - wire \$107 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - wire \$109 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire \$111 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - wire \$113 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - wire \$115 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire \$117 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - wire \$119 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - wire \$121 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire \$123 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - wire \$125 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - wire \$127 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire \$129 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - wire \$131 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - wire \$133 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire \$135 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - wire \$137 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - wire \$139 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$141 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$143 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$145 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$147 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - wire \$149 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - wire \$151 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - wire \$153 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" - wire \$155 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" - wire \$157 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" - wire \$159 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" - wire \$161 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - wire \$163 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - wire \$165 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - wire \$167 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - wire \$169 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - wire \$171 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - wire \$173 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - wire \$175 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - wire \$177 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" - wire \$179 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - wire \$181 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - wire \$183 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - wire \$185 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - wire \$187 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - wire \$189 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - wire \$191 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - wire \$193 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - wire \$195 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" - wire \$197 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" - wire \$199 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - wire \$201 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - wire \$203 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - wire \$205 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - wire \$207 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - wire \$209 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - wire \$211 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - wire \$213 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - wire \$215 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" - wire \$217 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - wire \$219 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - wire \$221 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - wire \$223 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - wire \$225 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - wire \$227 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - wire \$229 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - wire \$231 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - wire \$233 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" - wire \$235 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" - wire \$237 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - wire \$239 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - wire \$241 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - wire \$243 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - wire \$245 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - wire \$247 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - wire \$249 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - wire \$251 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - wire \$253 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:229" - wire \$255 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:229" - wire \$256 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" - wire \$259 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" - wire \$261 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" - wire \$263 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:231" - wire \$265 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:201" - wire width 30 \$267 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:201" - wire width 30 \$268 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:225" - wire width 30 \$270 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:225" - wire width 30 \$271 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 8 \$273 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" - wire \$276 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" - wire \$278 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" - wire \$280 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:183" - wire \$282 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:153" - wire width 5 \$284 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:153" - wire width 5 \$285 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:177" - wire width 5 \$287 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:177" - wire width 5 \$288 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:386" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:475" - wire \$41 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:472" - wire \$43 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - wire \$53 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - wire \$55 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire \$57 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - wire \$59 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - wire \$61 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - wire \$65 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - wire \$67 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire \$69 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:382" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - wire \$71 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - wire \$73 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire \$75 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - wire \$83 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - wire \$85 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire \$87 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - wire \$91 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - wire \$95 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - wire \$97 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire input 118 \TAP_bus__tck - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire input 58 \TAP_bus__tdi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire output 109 \TAP_bus__tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire input 119 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" - wire \TAP_tdo - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" - wire \_fsm_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" - wire \_fsm_isdr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" - wire \_fsm_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" - wire \_fsm_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:27" - wire \_fsm_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:215" - wire \_idblock_TAP_id_tdo - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" - wire width 4 \_irblock_ir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:129" - wire \_irblock_tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" - wire input 4 \dmi0_ack_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 4 output 120 \dmi0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 4 \dmi0_addr_i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:130" - wire width 8 \dmi0_addrsr__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:130" - wire width 8 \dmi0_addrsr__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:130" - wire \dmi0_addrsr__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:130" - wire \dmi0_addrsr__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" - wire \dmi0_addrsr_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" - wire \dmi0_addrsr_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" - wire width 8 \dmi0_addrsr_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" - wire width 8 \dmi0_addrsr_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" - wire \dmi0_addrsr_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" - wire \dmi0_addrsr_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" - wire \dmi0_addrsr_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" - wire \dmi0_addrsr_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire \dmi0_addrsr_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire \dmi0_addrsr_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" - wire width 64 \dmi0_datasr__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" - wire width 64 \dmi0_datasr__i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" - wire width 64 \dmi0_datasr__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" - wire width 2 \dmi0_datasr__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" - wire width 2 \dmi0_datasr__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" - wire \dmi0_datasr_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" - wire width 2 \dmi0_datasr_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" - wire width 64 \dmi0_datasr_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" - wire width 64 \dmi0_datasr_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" - wire \dmi0_datasr_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" - wire \dmi0_datasr_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" - wire \dmi0_datasr_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" - wire \dmi0_datasr_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire \dmi0_datasr_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire \dmi0_datasr_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 64 output 3 \dmi0_din - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 64 \dmi0_din$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" - wire width 64 input 5 \dmi0_dout - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" - wire output 1 \dmi0_req_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" - wire output 2 \dmi0_we_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" - wire width 3 \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" - wire width 3 \fsm_state$275 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" - wire width 3 \fsm_state$275$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" - wire width 3 \fsm_state$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 61 \gpio_gpio0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 11 \gpio_gpio0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 12 \gpio_gpio0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 10 \gpio_gpio0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 62 \gpio_gpio0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 63 \gpio_gpio0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 91 \gpio_gpio10__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 41 \gpio_gpio10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 42 \gpio_gpio10__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 40 \gpio_gpio10__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 92 \gpio_gpio10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 93 \gpio_gpio10__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 94 \gpio_gpio11__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 44 \gpio_gpio11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 45 \gpio_gpio11__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 43 \gpio_gpio11__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 95 \gpio_gpio11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 96 \gpio_gpio11__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 97 \gpio_gpio12__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 47 \gpio_gpio12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 48 \gpio_gpio12__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 46 \gpio_gpio12__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 98 \gpio_gpio12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 99 \gpio_gpio12__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 100 \gpio_gpio13__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 50 \gpio_gpio13__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 51 \gpio_gpio13__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 49 \gpio_gpio13__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 101 \gpio_gpio13__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 102 \gpio_gpio13__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 103 \gpio_gpio14__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 53 \gpio_gpio14__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 54 \gpio_gpio14__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 52 \gpio_gpio14__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 104 \gpio_gpio14__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 105 \gpio_gpio14__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 106 \gpio_gpio15__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 56 \gpio_gpio15__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 57 \gpio_gpio15__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 55 \gpio_gpio15__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 107 \gpio_gpio15__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 108 \gpio_gpio15__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 64 \gpio_gpio1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 14 \gpio_gpio1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 15 \gpio_gpio1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 13 \gpio_gpio1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 65 \gpio_gpio1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 66 \gpio_gpio1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 67 \gpio_gpio2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 17 \gpio_gpio2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 18 \gpio_gpio2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 16 \gpio_gpio2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 68 \gpio_gpio2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 69 \gpio_gpio2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 70 \gpio_gpio3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 20 \gpio_gpio3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 21 \gpio_gpio3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 19 \gpio_gpio3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 71 \gpio_gpio3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 72 \gpio_gpio3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 73 \gpio_gpio4__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 23 \gpio_gpio4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 24 \gpio_gpio4__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 22 \gpio_gpio4__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 74 \gpio_gpio4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 75 \gpio_gpio4__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 76 \gpio_gpio5__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 26 \gpio_gpio5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 27 \gpio_gpio5__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 25 \gpio_gpio5__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 77 \gpio_gpio5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 78 \gpio_gpio5__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 79 \gpio_gpio6__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 29 \gpio_gpio6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 30 \gpio_gpio6__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 28 \gpio_gpio6__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 80 \gpio_gpio6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 81 \gpio_gpio6__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 82 \gpio_gpio7__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 32 \gpio_gpio7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 33 \gpio_gpio7__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 31 \gpio_gpio7__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 83 \gpio_gpio7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 84 \gpio_gpio7__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 85 \gpio_gpio8__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 35 \gpio_gpio8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 36 \gpio_gpio8__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 34 \gpio_gpio8__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 86 \gpio_gpio8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 87 \gpio_gpio8__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 88 \gpio_gpio9__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 38 \gpio_gpio9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 39 \gpio_gpio9__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 37 \gpio_gpio9__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 89 \gpio_gpio9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 90 \gpio_gpio9__pad__oe - attribute \src "libresoc.v:43022.7-43022.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" - wire input 6 \intclk_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" - wire input 7 \intclk_rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:437" - wire width 50 \io_bd - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:437" - wire width 50 \io_bd$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - wire \io_bd2core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:376" - wire \io_bd2io - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:373" - wire \io_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - wire \io_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:436" - wire width 50 \io_sr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:436" - wire width 50 \io_sr$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" - wire \io_update - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire input 116 \jtag_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire width 29 output 110 \jtag_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire width 29 \jtag_wb__adr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire output 112 \jtag_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire width 64 input 117 \jtag_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire width 64 output 115 \jtag_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire width 64 \jtag_wb__dat_w$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire output 111 \jtag_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire output 113 \jtag_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire output 114 \jtag_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:78" - wire width 29 \jtag_wb_addrsr__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:78" - wire width 29 \jtag_wb_addrsr__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:78" - wire \jtag_wb_addrsr__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:78" - wire \jtag_wb_addrsr__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" - wire \jtag_wb_addrsr_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" - wire \jtag_wb_addrsr_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" - wire width 29 \jtag_wb_addrsr_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" - wire width 29 \jtag_wb_addrsr_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" - wire \jtag_wb_addrsr_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" - wire \jtag_wb_addrsr_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" - wire \jtag_wb_addrsr_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" - wire \jtag_wb_addrsr_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire \jtag_wb_addrsr_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire \jtag_wb_addrsr_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" - wire width 64 \jtag_wb_datasr__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" - wire width 64 \jtag_wb_datasr__i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" - wire width 64 \jtag_wb_datasr__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" - wire width 2 \jtag_wb_datasr__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" - wire width 2 \jtag_wb_datasr__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" - wire \jtag_wb_datasr_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" - wire width 2 \jtag_wb_datasr_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" - wire width 64 \jtag_wb_datasr_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" - wire width 64 \jtag_wb_datasr_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" - wire \jtag_wb_datasr_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" - wire \jtag_wb_datasr_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" - wire \jtag_wb_datasr_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" - wire \jtag_wb_datasr_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire \jtag_wb_datasr_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire \jtag_wb_datasr_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" - wire \negjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" - wire \negjtag_rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" - wire \posjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" - wire \posjtag_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52" - wire width 3 \sr0__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52" - wire width 3 \sr0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52" - wire \sr0__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52" - wire \sr0__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" - wire \sr0_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" - wire \sr0_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" - wire width 3 \sr0_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" - wire width 3 \sr0_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" - wire \sr0_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" - wire \sr0_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" - wire \sr0_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" - wire \sr0_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire \sr0_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire \sr0_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 60 \uart_rx__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 9 \uart_rx__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 8 \uart_tx__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 59 \uart_tx__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:201" - cell $add $add$libresoc.v:43858$1158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 29 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 30 - connect \A \jtag_wb__adr - connect \B 1'1 - connect \Y $add$libresoc.v:43858$1158_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:225" - cell $add $add$libresoc.v:43859$1159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 29 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 30 - connect \A \jtag_wb__adr - connect \B 1'1 - connect \Y $add$libresoc.v:43859$1159_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:153" - cell $add $add$libresoc.v:43866$1167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \dmi0_addr_i - connect \B 1'1 - connect \Y $add$libresoc.v:43866$1167_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:177" - cell $add $add$libresoc.v:43867$1168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \dmi0_addr_i - connect \B 1'1 - connect \Y $add$libresoc.v:43867$1168_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $and $and$libresoc.v:43791$1091 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$145 - connect \Y $and$libresoc.v:43791$1091_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" - cell $and $and$libresoc.v:43798$1098 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$157 - connect \Y $and$libresoc.v:43798$1098_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - cell $and $and$libresoc.v:43801$1101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$163 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:43801$1101_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - cell $and $and$libresoc.v:43803$1103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$167 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:43803$1103_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - cell $and $and$libresoc.v:43805$1105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$171 - connect \B \_fsm_update - connect \Y $and$libresoc.v:43805$1105_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - cell $and $and$libresoc.v:43807$1107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr0_update_core_prev - connect \B \$175 - connect \Y $and$libresoc.v:43807$1107_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - cell $and $and$libresoc.v:43811$1111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$181 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:43811$1111_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - cell $and $and$libresoc.v:43813$1113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$185 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:43813$1113_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - cell $and $and$libresoc.v:43815$1115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$189 - connect \B \_fsm_update - connect \Y $and$libresoc.v:43815$1115_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - cell $and $and$libresoc.v:43817$1117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_addrsr_update_core_prev - connect \B \$193 - connect \Y $and$libresoc.v:43817$1117_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" - cell $and $and$libresoc.v:43820$1120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$17 - connect \Y $and$libresoc.v:43820$1120_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - cell $and $and$libresoc.v:43823$1123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$201 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:43823$1123_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - cell $and $and$libresoc.v:43825$1125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$205 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:43825$1125_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - cell $and $and$libresoc.v:43827$1127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$209 - connect \B \_fsm_update - connect \Y $and$libresoc.v:43827$1127_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - cell $and $and$libresoc.v:43829$1129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_datasr_update_core_prev - connect \B \$213 - connect \Y $and$libresoc.v:43829$1129_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" - cell $and $and$libresoc.v:43831$1131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$19 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:43831$1131_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - cell $and $and$libresoc.v:43833$1133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$219 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:43833$1133_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - cell $and $and$libresoc.v:43835$1135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$223 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:43835$1135_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - cell $and $and$libresoc.v:43837$1137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$227 - connect \B \_fsm_update - connect \Y $and$libresoc.v:43837$1137_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - cell $and $and$libresoc.v:43839$1139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_addrsr_update_core_prev - connect \B \$231 - connect \Y $and$libresoc.v:43839$1139_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - cell $and $and$libresoc.v:43844$1144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$239 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:43844$1144_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - cell $and $and$libresoc.v:43846$1146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$243 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:43846$1146_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - cell $and $and$libresoc.v:43848$1148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$247 - connect \B \_fsm_update - connect \Y $and$libresoc.v:43848$1148_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - cell $and $and$libresoc.v:43850$1150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_datasr_update_core_prev - connect \B \$251 - connect \Y $and$libresoc.v:43850$1150_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" - cell $and $and$libresoc.v:43870$1171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$31 - connect \Y $and$libresoc.v:43870$1171_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" - cell $and $and$libresoc.v:43871$1172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$33 - connect \B \_fsm_update - connect \Y $and$libresoc.v:43871$1172_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:382" - cell $and $and$libresoc.v:43895$1196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:43895$1196_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:43764$1064 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:43764$1064_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:43775$1075 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:43775$1075_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $eq $eq$libresoc.v:43788$1088 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'1 - connect \Y $eq$libresoc.v:43788$1088_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $eq $eq$libresoc.v:43789$1089 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1111 - connect \Y $eq$libresoc.v:43789$1089_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:43792$1092 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:43792$1092_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:43793$1093 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:43793$1093_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" - cell $eq $eq$libresoc.v:43795$1095 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:43795$1095_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" - cell $eq $eq$libresoc.v:43797$1097 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:43797$1097_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" - cell $eq $eq$libresoc.v:43799$1099 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 3'100 - connect \Y $eq$libresoc.v:43799$1099_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" - cell $eq $eq$libresoc.v:43809$1109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 3'101 - connect \Y $eq$libresoc.v:43809$1109_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" - cell $eq $eq$libresoc.v:43818$1118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 3'110 - connect \Y $eq$libresoc.v:43818$1118_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:43819$1119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:43819$1119_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" - cell $eq $eq$libresoc.v:43821$1121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 3'111 - connect \Y $eq$libresoc.v:43821$1121_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" - cell $eq $eq$libresoc.v:43830$1130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1000 - connect \Y $eq$libresoc.v:43830$1130_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" - cell $eq $eq$libresoc.v:43840$1140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1001 - connect \Y $eq$libresoc.v:43840$1140_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" - cell $eq $eq$libresoc.v:43841$1141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1010 - connect \Y $eq$libresoc.v:43841$1141_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:43842$1142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:43842$1142_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:229" - cell $eq $eq$libresoc.v:43851$1151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 1'0 - connect \Y $eq$libresoc.v:43851$1151_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:43853$1153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:43853$1153_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" - cell $eq $eq$libresoc.v:43854$1154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 1'1 - connect \Y $eq$libresoc.v:43854$1154_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" - cell $eq $eq$libresoc.v:43855$1155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 2'10 - connect \Y $eq$libresoc.v:43855$1155_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:231" - cell $eq $eq$libresoc.v:43857$1157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 2'10 - connect \Y $eq$libresoc.v:43857$1157_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" - cell $eq $eq$libresoc.v:43861$1162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fsm_state$275 - connect \B 1'1 - connect \Y $eq$libresoc.v:43861$1162_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" - cell $eq $eq$libresoc.v:43862$1163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \fsm_state$275 - connect \B 2'10 - connect \Y $eq$libresoc.v:43862$1163_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:183" - cell $eq $eq$libresoc.v:43865$1166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \fsm_state$275 - connect \B 2'10 - connect \Y $eq$libresoc.v:43865$1166_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" - cell $eq $eq$libresoc.v:43868$1169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:43868$1169_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" - cell $eq $eq$libresoc.v:43872$1173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:43872$1173_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:43873$1174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:43873$1174_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:386" - cell $eq $eq$libresoc.v:43874$1175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:43874$1175_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - cell $pos $extend$libresoc.v:43860$1160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \dmi0_addr_i - connect \Y $extend$libresoc.v:43860$1160_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - cell $ne $ne$libresoc.v:43800$1100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr0_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:43800$1100_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - cell $ne $ne$libresoc.v:43802$1102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr0_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:43802$1102_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - cell $ne $ne$libresoc.v:43804$1104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr0_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:43804$1104_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - cell $ne $ne$libresoc.v:43810$1110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:43810$1110_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - cell $ne $ne$libresoc.v:43812$1112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:43812$1112_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - cell $ne $ne$libresoc.v:43814$1114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:43814$1114_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - cell $ne $ne$libresoc.v:43822$1122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:43822$1122_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - cell $ne $ne$libresoc.v:43824$1124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:43824$1124_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - cell $ne $ne$libresoc.v:43826$1126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:43826$1126_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - cell $ne $ne$libresoc.v:43832$1132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:43832$1132_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - cell $ne $ne$libresoc.v:43834$1134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:43834$1134_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - cell $ne $ne$libresoc.v:43836$1136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:43836$1136_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - cell $ne $ne$libresoc.v:43843$1143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:43843$1143_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - cell $ne $ne$libresoc.v:43845$1145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:43845$1145_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - cell $ne $ne$libresoc.v:43847$1147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:43847$1147_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - cell $not $not$libresoc.v:43806$1106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr0_update_core - connect \Y $not$libresoc.v:43806$1106_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - cell $not $not$libresoc.v:43816$1116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_addrsr_update_core - connect \Y $not$libresoc.v:43816$1116_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - cell $not $not$libresoc.v:43828$1128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_datasr_update_core - connect \Y $not$libresoc.v:43828$1128_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - cell $not $not$libresoc.v:43838$1138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_addrsr_update_core - connect \Y $not$libresoc.v:43838$1138_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - cell $not $not$libresoc.v:43849$1149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_datasr_update_core - connect \Y $not$libresoc.v:43849$1149_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:229" - cell $not $not$libresoc.v:43852$1152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$256 - connect \Y $not$libresoc.v:43852$1152_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $or $or$libresoc.v:43786$1086 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \$11 - connect \Y $or$libresoc.v:43786$1086_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $or $or$libresoc.v:43790$1090 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$141 - connect \B \$143 - connect \Y $or$libresoc.v:43790$1090_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $or $or$libresoc.v:43794$1094 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$149 - connect \B \$151 - connect \Y $or$libresoc.v:43794$1094_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" - cell $or $or$libresoc.v:43796$1096 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$153 - connect \B \$155 - connect \Y $or$libresoc.v:43796$1096_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" - cell $or $or$libresoc.v:43808$1108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$13 - connect \B \$15 - connect \Y $or$libresoc.v:43808$1108_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" - cell $or $or$libresoc.v:43856$1156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$259 - connect \B \$261 - connect \Y $or$libresoc.v:43856$1156_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $or $or$libresoc.v:43863$1164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$23 - connect \B \$25 - connect \Y $or$libresoc.v:43863$1164_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" - cell $or $or$libresoc.v:43864$1165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$276 - connect \B \$278 - connect \Y $or$libresoc.v:43864$1165_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" - cell $or $or$libresoc.v:43869$1170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$27 - connect \B \$29 - connect \Y $or$libresoc.v:43869$1170_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $or $or$libresoc.v:43884$1185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \$3 - connect \Y $or$libresoc.v:43884$1185_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - cell $pos $pos$libresoc.v:43860$1161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:43860$1160_Y - connect \Y $pos$libresoc.v:43860$1161_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:43765$1065 - parameter \WIDTH 1 - connect \A \gpio_gpio9__pad__i - connect \B \io_bd [29] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:43765$1065_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:43766$1066 - parameter \WIDTH 1 - connect \A \gpio_gpio9__core__o - connect \B \io_bd [30] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43766$1066_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:43767$1067 - parameter \WIDTH 1 - connect \A \gpio_gpio9__core__oe - connect \B \io_bd [31] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43767$1067_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:43768$1068 - parameter \WIDTH 1 - connect \A \gpio_gpio10__pad__i - connect \B \io_bd [32] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:43768$1068_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:43769$1069 - parameter \WIDTH 1 - connect \A \gpio_gpio10__core__o - connect \B \io_bd [33] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43769$1069_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:43770$1070 - parameter \WIDTH 1 - connect \A \gpio_gpio10__core__oe - connect \B \io_bd [34] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43770$1070_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:43771$1071 - parameter \WIDTH 1 - connect \A \gpio_gpio11__pad__i - connect \B \io_bd [35] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:43771$1071_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:43772$1072 - parameter \WIDTH 1 - connect \A \gpio_gpio11__core__o - connect \B \io_bd [36] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43772$1072_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:43773$1073 - parameter \WIDTH 1 - connect \A \gpio_gpio11__core__oe - connect \B \io_bd [37] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43773$1073_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:43774$1074 - parameter \WIDTH 1 - connect \A \gpio_gpio12__pad__i - connect \B \io_bd [38] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:43774$1074_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:43776$1076 - parameter \WIDTH 1 - connect \A \gpio_gpio12__core__o - connect \B \io_bd [39] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43776$1076_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:43777$1077 - parameter \WIDTH 1 - connect \A \gpio_gpio12__core__oe - connect \B \io_bd [40] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43777$1077_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:43778$1078 - parameter \WIDTH 1 - connect \A \gpio_gpio13__pad__i - connect \B \io_bd [41] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:43778$1078_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:43779$1079 - parameter \WIDTH 1 - connect \A \gpio_gpio13__core__o - connect \B \io_bd [42] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43779$1079_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:43780$1080 - parameter \WIDTH 1 - connect \A \gpio_gpio13__core__oe - connect \B \io_bd [43] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43780$1080_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:43781$1081 - parameter \WIDTH 1 - connect \A \gpio_gpio14__pad__i - connect \B \io_bd [44] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:43781$1081_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:43782$1082 - parameter \WIDTH 1 - connect \A \gpio_gpio14__core__o - connect \B \io_bd [45] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43782$1082_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:43783$1083 - parameter \WIDTH 1 - connect \A \gpio_gpio14__core__oe - connect \B \io_bd [46] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43783$1083_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:43784$1084 - parameter \WIDTH 1 - connect \A \gpio_gpio15__pad__i - connect \B \io_bd [47] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:43784$1084_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:43785$1085 - parameter \WIDTH 1 - connect \A \gpio_gpio15__core__o - connect \B \io_bd [48] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43785$1085_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:43787$1087 - parameter \WIDTH 1 - connect \A \gpio_gpio15__core__oe - connect \B \io_bd [49] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43787$1087_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:475" - cell $mux $ternary$libresoc.v:43875$1176 - parameter \WIDTH 1 - connect \A \uart_tx__core__o - connect \B \io_bd [0] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43875$1176_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:472" - cell $mux $ternary$libresoc.v:43876$1177 - parameter \WIDTH 1 - connect \A \uart_rx__pad__i - connect \B \io_bd [1] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:43876$1177_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:43877$1178 - parameter \WIDTH 1 - connect \A \gpio_gpio0__pad__i - connect \B \io_bd [2] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:43877$1178_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:43878$1179 - parameter \WIDTH 1 - connect \A \gpio_gpio0__core__o - connect \B \io_bd [3] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43878$1179_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:43879$1180 - parameter \WIDTH 1 - connect \A \gpio_gpio0__core__oe - connect \B \io_bd [4] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43879$1180_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:43880$1181 - parameter \WIDTH 1 - connect \A \gpio_gpio1__pad__i - connect \B \io_bd [5] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:43880$1181_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:43881$1182 - parameter \WIDTH 1 - connect \A \gpio_gpio1__core__o - connect \B \io_bd [6] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43881$1182_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:43882$1183 - parameter \WIDTH 1 - connect \A \gpio_gpio1__core__oe - connect \B \io_bd [7] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43882$1183_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:43883$1184 - parameter \WIDTH 1 - connect \A \gpio_gpio2__pad__i - connect \B \io_bd [8] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:43883$1184_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:43885$1186 - parameter \WIDTH 1 - connect \A \gpio_gpio2__core__o - connect \B \io_bd [9] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43885$1186_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:43886$1187 - parameter \WIDTH 1 - connect \A \gpio_gpio2__core__oe - connect \B \io_bd [10] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43886$1187_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:43887$1188 - parameter \WIDTH 1 - connect \A \gpio_gpio3__pad__i - connect \B \io_bd [11] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:43887$1188_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:43888$1189 - parameter \WIDTH 1 - connect \A \gpio_gpio3__core__o - connect \B \io_bd [12] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43888$1189_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:43889$1190 - parameter \WIDTH 1 - connect \A \gpio_gpio3__core__oe - connect \B \io_bd [13] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43889$1190_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:43890$1191 - parameter \WIDTH 1 - connect \A \gpio_gpio4__pad__i - connect \B \io_bd [14] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:43890$1191_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:43891$1192 - parameter \WIDTH 1 - connect \A \gpio_gpio4__core__o - connect \B \io_bd [15] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43891$1192_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:43892$1193 - parameter \WIDTH 1 - connect \A \gpio_gpio4__core__oe - connect \B \io_bd [16] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43892$1193_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:43893$1194 - parameter \WIDTH 1 - connect \A \gpio_gpio5__pad__i - connect \B \io_bd [17] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:43893$1194_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:43894$1195 - parameter \WIDTH 1 - connect \A \gpio_gpio5__core__o - connect \B \io_bd [18] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43894$1195_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:43896$1197 - parameter \WIDTH 1 - connect \A \gpio_gpio5__core__oe - connect \B \io_bd [19] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43896$1197_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:43897$1198 - parameter \WIDTH 1 - connect \A \gpio_gpio6__pad__i - connect \B \io_bd [20] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:43897$1198_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:43898$1199 - parameter \WIDTH 1 - connect \A \gpio_gpio6__core__o - connect \B \io_bd [21] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43898$1199_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:43899$1200 - parameter \WIDTH 1 - connect \A \gpio_gpio6__core__oe - connect \B \io_bd [22] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43899$1200_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:43900$1201 - parameter \WIDTH 1 - connect \A \gpio_gpio7__pad__i - connect \B \io_bd [23] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:43900$1201_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:43901$1202 - parameter \WIDTH 1 - connect \A \gpio_gpio7__core__o - connect \B \io_bd [24] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43901$1202_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:43902$1203 - parameter \WIDTH 1 - connect \A \gpio_gpio7__core__oe - connect \B \io_bd [25] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43902$1203_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:43903$1204 - parameter \WIDTH 1 - connect \A \gpio_gpio8__pad__i - connect \B \io_bd [26] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:43903$1204_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:43904$1205 - parameter \WIDTH 1 - connect \A \gpio_gpio8__core__o - connect \B \io_bd [27] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43904$1205_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:43905$1206 - parameter \WIDTH 1 - connect \A \gpio_gpio8__core__oe - connect \B \io_bd [28] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:43905$1206_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43966.8-43978.4" - cell \_fsm \_fsm - connect \TAP_bus__tck \TAP_bus__tck - connect \TAP_bus__tms \TAP_bus__tms - connect \capture \_fsm_capture - connect \isdr \_fsm_isdr - connect \isir \_fsm_isir - connect \negjtag_clk \negjtag_clk - connect \negjtag_rst \negjtag_rst - connect \posjtag_clk \posjtag_clk - connect \posjtag_rst \posjtag_rst - connect \shift \_fsm_shift - connect \update \_fsm_update - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43979.12-43989.4" - cell \_idblock \_idblock - connect \TAP_bus__tdi \TAP_bus__tdi - connect \TAP_id_tdo \_idblock_TAP_id_tdo - connect \capture \_fsm_capture - connect \ir \_irblock_ir - connect \isdr \_fsm_isdr - connect \posjtag_clk \posjtag_clk - connect \posjtag_rst \posjtag_rst - connect \shift \_fsm_shift - connect \update \_fsm_update - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43990.12-44000.4" - cell \_irblock \_irblock - connect \TAP_bus__tdi \TAP_bus__tdi - connect \capture \_fsm_capture - connect \ir \_irblock_ir - connect \isir \_fsm_isir - connect \posjtag_clk \posjtag_clk - connect \posjtag_rst \posjtag_rst - connect \shift \_fsm_shift - connect \tdo \_irblock_tdo - connect \update \_fsm_update - end - attribute \src "libresoc.v:43022.7-43022.20" - process $proc$libresoc.v:43022$1369 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:43346.13-43346.31" - process $proc$libresoc.v:43346$1370 - assign { } { } - assign $1\dmi0_addr_i[3:0] 4'0000 - sync always - sync init - update \dmi0_addr_i $1\dmi0_addr_i[3:0] - end - attribute \src "libresoc.v:43354.7-43354.29" - process $proc$libresoc.v:43354$1371 - assign { } { } - assign $1\dmi0_addrsr__oe[0:0] 1'0 - sync always - sync init - update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] - end - attribute \src "libresoc.v:43362.13-43362.36" - process $proc$libresoc.v:43362$1372 - assign { } { } - assign $1\dmi0_addrsr_reg[7:0] 8'00000000 - sync always - sync init - update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] - end - attribute \src "libresoc.v:43370.7-43370.37" - process $proc$libresoc.v:43370$1373 - assign { } { } - assign $1\dmi0_addrsr_update_core[0:0] 1'0 - sync always - sync init - update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] - end - attribute \src "libresoc.v:43374.7-43374.42" - process $proc$libresoc.v:43374$1374 - assign { } { } - assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 - sync always - sync init - update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] - end - attribute \src "libresoc.v:43378.14-43378.51" - process $proc$libresoc.v:43378$1375 - assign { } { } - assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] - end - attribute \src "libresoc.v:43384.13-43384.35" - process $proc$libresoc.v:43384$1376 - assign { } { } - assign $1\dmi0_datasr__oe[1:0] 2'00 - sync always - sync init - update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] - end - attribute \src "libresoc.v:43392.14-43392.52" - process $proc$libresoc.v:43392$1377 - assign { } { } - assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] - end - attribute \src "libresoc.v:43400.7-43400.37" - process $proc$libresoc.v:43400$1378 - assign { } { } - assign $1\dmi0_datasr_update_core[0:0] 1'0 - sync always - sync init - update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] - end - attribute \src "libresoc.v:43404.7-43404.42" - process $proc$libresoc.v:43404$1379 - assign { } { } - assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 - sync always - sync init - update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] - end - attribute \src "libresoc.v:43409.14-43409.45" - process $proc$libresoc.v:43409$1380 - assign { } { } - assign $1\dmi0_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dmi0_din $1\dmi0_din[63:0] - end - attribute \src "libresoc.v:43419.13-43419.29" - process $proc$libresoc.v:43419$1381 - assign { } { } - assign $1\fsm_state[2:0] 3'000 - sync always - sync init - update \fsm_state $1\fsm_state[2:0] - end - attribute \src "libresoc.v:43421.13-43421.35" - process $proc$libresoc.v:43421$1382 - assign { } { } - assign $0\fsm_state$275[2:0]$1383 3'000 - sync always - sync init - update \fsm_state$275 $0\fsm_state$275[2:0]$1383 - end - attribute \src "libresoc.v:43623.14-43623.39" - process $proc$libresoc.v:43623$1384 - assign { } { } - assign $1\io_bd[49:0] 50'00000000000000000000000000000000000000000000000000 - sync always - sync init - update \io_bd $1\io_bd[49:0] - end - attribute \src "libresoc.v:43635.14-43635.39" - process $proc$libresoc.v:43635$1385 - assign { } { } - assign $1\io_sr[49:0] 50'00000000000000000000000000000000000000000000000000 - sync always - sync init - update \io_sr $1\io_sr[49:0] - end - attribute \src "libresoc.v:43644.14-43644.41" - process $proc$libresoc.v:43644$1386 - assign { } { } - assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 - sync always - sync init - update \jtag_wb__adr $1\jtag_wb__adr[28:0] - end - attribute \src "libresoc.v:43653.14-43653.51" - process $proc$libresoc.v:43653$1387 - assign { } { } - assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] - end - attribute \src "libresoc.v:43667.7-43667.32" - process $proc$libresoc.v:43667$1388 - assign { } { } - assign $1\jtag_wb_addrsr__oe[0:0] 1'0 - sync always - sync init - update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] - end - attribute \src "libresoc.v:43675.14-43675.47" - process $proc$libresoc.v:43675$1389 - assign { } { } - assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 - sync always - sync init - update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] - end - attribute \src "libresoc.v:43683.7-43683.40" - process $proc$libresoc.v:43683$1390 - assign { } { } - assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 - sync always - sync init - update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] - end - attribute \src "libresoc.v:43687.7-43687.45" - process $proc$libresoc.v:43687$1391 - assign { } { } - assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 - sync always - sync init - update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] - end - attribute \src "libresoc.v:43691.14-43691.54" - process $proc$libresoc.v:43691$1392 - assign { } { } - assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] - end - attribute \src "libresoc.v:43697.13-43697.38" - process $proc$libresoc.v:43697$1393 - assign { } { } - assign $1\jtag_wb_datasr__oe[1:0] 2'00 - sync always - sync init - update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] - end - attribute \src "libresoc.v:43705.14-43705.55" - process $proc$libresoc.v:43705$1394 - assign { } { } - assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] - end - attribute \src "libresoc.v:43713.7-43713.40" - process $proc$libresoc.v:43713$1395 - assign { } { } - assign $1\jtag_wb_datasr_update_core[0:0] 1'0 - sync always - sync init - update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] - end - attribute \src "libresoc.v:43717.7-43717.45" - process $proc$libresoc.v:43717$1396 - assign { } { } - assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 - sync always - sync init - update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] - end - attribute \src "libresoc.v:43733.7-43733.21" - process $proc$libresoc.v:43733$1397 - assign { } { } - assign $1\sr0__oe[0:0] 1'0 - sync always - sync init - update \sr0__oe $1\sr0__oe[0:0] - end - attribute \src "libresoc.v:43741.13-43741.27" - process $proc$libresoc.v:43741$1398 - assign { } { } - assign $1\sr0_reg[2:0] 3'000 - sync always - sync init - update \sr0_reg $1\sr0_reg[2:0] - end - attribute \src "libresoc.v:43749.7-43749.29" - process $proc$libresoc.v:43749$1399 - assign { } { } - assign $1\sr0_update_core[0:0] 1'0 - sync always - sync init - update \sr0_update_core $1\sr0_update_core[0:0] - end - attribute \src "libresoc.v:43753.7-43753.34" - process $proc$libresoc.v:43753$1400 - assign { } { } - assign $1\sr0_update_core_prev[0:0] 1'0 - sync always - sync init - update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] - end - attribute \src "libresoc.v:43906.3-43907.45" - process $proc$libresoc.v:43906$1207 - assign { } { } - assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next - sync posedge \intclk_clk - update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] - end - attribute \src "libresoc.v:43908.3-43909.33" - process $proc$libresoc.v:43908$1208 - assign { } { } - assign $0\dmi0_din[63:0] \dmi0_din$next - sync posedge \intclk_clk - update \dmi0_din $0\dmi0_din[63:0] - end - attribute \src "libresoc.v:43910.3-43911.45" - process $proc$libresoc.v:43910$1209 - assign { } { } - assign $0\fsm_state$275[2:0]$1210 \fsm_state$275$next - sync posedge \intclk_clk - update \fsm_state$275 $0\fsm_state$275[2:0]$1210 - end - attribute \src "libresoc.v:43912.3-43913.39" - process $proc$libresoc.v:43912$1211 - assign { } { } - assign $0\dmi0_addr_i[3:0] \dmi0_addr_i$next - sync posedge \intclk_clk - update \dmi0_addr_i $0\dmi0_addr_i[3:0] - end - attribute \src "libresoc.v:43914.3-43915.51" - process $proc$libresoc.v:43914$1212 - assign { } { } - assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next - sync posedge \intclk_clk - update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] - end - attribute \src "libresoc.v:43916.3-43917.45" - process $proc$libresoc.v:43916$1213 - assign { } { } - assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next - sync posedge \intclk_clk - update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] - end - attribute \src "libresoc.v:43918.3-43919.35" - process $proc$libresoc.v:43918$1214 - assign { } { } - assign $0\fsm_state[2:0] \fsm_state$next - sync posedge \intclk_clk - update \fsm_state $0\fsm_state[2:0] - end - attribute \src "libresoc.v:43920.3-43921.41" - process $proc$libresoc.v:43920$1215 - assign { } { } - assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next - sync posedge \intclk_clk - update \jtag_wb__adr $0\jtag_wb__adr[28:0] - end - attribute \src "libresoc.v:43922.3-43923.47" - process $proc$libresoc.v:43922$1216 - assign { } { } - assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next - sync posedge \posjtag_clk - update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] - end - attribute \src "libresoc.v:43924.3-43925.47" - process $proc$libresoc.v:43924$1217 - assign { } { } - assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next - sync posedge \intclk_clk - update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] - end - attribute \src "libresoc.v:43926.3-43927.73" - process $proc$libresoc.v:43926$1218 - assign { } { } - assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next - sync posedge \intclk_clk - update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] - end - attribute \src "libresoc.v:43928.3-43929.63" - process $proc$libresoc.v:43928$1219 - assign { } { } - assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next - sync posedge \intclk_clk - update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] - end - attribute \src "libresoc.v:43930.3-43931.47" - process $proc$libresoc.v:43930$1220 - assign { } { } - assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next - sync posedge \posjtag_clk - update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] - end - attribute \src "libresoc.v:43932.3-43933.47" - process $proc$libresoc.v:43932$1221 - assign { } { } - assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next - sync posedge \intclk_clk - update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] - end - attribute \src "libresoc.v:43934.3-43935.73" - process $proc$libresoc.v:43934$1222 - assign { } { } - assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next - sync posedge \intclk_clk - update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] - end - attribute \src "libresoc.v:43936.3-43937.63" - process $proc$libresoc.v:43936$1223 - assign { } { } - assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next - sync posedge \intclk_clk - update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] - end - attribute \src "libresoc.v:43938.3-43939.53" - process $proc$libresoc.v:43938$1224 - assign { } { } - assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next - sync posedge \posjtag_clk - update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] - end - attribute \src "libresoc.v:43940.3-43941.53" - process $proc$libresoc.v:43940$1225 - assign { } { } - assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next - sync posedge \intclk_clk - update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] - end - attribute \src "libresoc.v:43942.3-43943.79" - process $proc$libresoc.v:43942$1226 - assign { } { } - assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next - sync posedge \intclk_clk - update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] - end - attribute \src "libresoc.v:43944.3-43945.69" - process $proc$libresoc.v:43944$1227 - assign { } { } - assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next - sync posedge \intclk_clk - update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] - end - attribute \src "libresoc.v:43946.3-43947.53" - process $proc$libresoc.v:43946$1228 - assign { } { } - assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next - sync posedge \posjtag_clk - update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] - end - attribute \src "libresoc.v:43948.3-43949.53" - process $proc$libresoc.v:43948$1229 - assign { } { } - assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next - sync posedge \intclk_clk - update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] - end - attribute \src "libresoc.v:43950.3-43951.79" - process $proc$libresoc.v:43950$1230 - assign { } { } - assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next - sync posedge \intclk_clk - update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] - end - attribute \src "libresoc.v:43952.3-43953.69" - process $proc$libresoc.v:43952$1231 - assign { } { } - assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next - sync posedge \intclk_clk - update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] - end - attribute \src "libresoc.v:43954.3-43955.31" - process $proc$libresoc.v:43954$1232 - assign { } { } - assign $0\sr0_reg[2:0] \sr0_reg$next - sync posedge \posjtag_clk - update \sr0_reg $0\sr0_reg[2:0] - end - attribute \src "libresoc.v:43956.3-43957.31" - process $proc$libresoc.v:43956$1233 - assign { } { } - assign $0\sr0__oe[0:0] \sr0__oe$next - sync posedge \intclk_clk - update \sr0__oe $0\sr0__oe[0:0] - end - attribute \src "libresoc.v:43958.3-43959.57" - process $proc$libresoc.v:43958$1234 - assign { } { } - assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next - sync posedge \intclk_clk - update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] - end - attribute \src "libresoc.v:43960.3-43961.47" - process $proc$libresoc.v:43960$1235 - assign { } { } - assign $0\sr0_update_core[0:0] \sr0_update_core$next - sync posedge \intclk_clk - update \sr0_update_core $0\sr0_update_core[0:0] - end - attribute \src "libresoc.v:43962.3-43963.27" - process $proc$libresoc.v:43962$1236 - assign { } { } - assign $0\io_bd[49:0] \io_bd$next - sync negedge \negjtag_clk - update \io_bd $0\io_bd[49:0] - end - attribute \src "libresoc.v:43964.3-43965.27" - process $proc$libresoc.v:43964$1237 - assign { } { } - assign $0\io_sr[49:0] \io_sr$next - sync posedge \posjtag_clk - update \io_sr $0\io_sr[49:0] - end - attribute \src "libresoc.v:44001.3-44009.6" - process $proc$libresoc.v:44001$1238 - assign { } { } - assign { } { } - assign $0\dmi0_datasr_update_core_prev$next[0:0]$1239 $1\dmi0_datasr_update_core_prev$next[0:0]$1240 - attribute \src "libresoc.v:44002.5-44002.29" - switch \initial - attribute \src "libresoc.v:44002.9-44002.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_datasr_update_core_prev$next[0:0]$1240 1'0 - case - assign $1\dmi0_datasr_update_core_prev$next[0:0]$1240 \dmi0_datasr_update_core - end - sync always - update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$1239 - end - attribute \src "libresoc.v:44010.3-44026.6" - process $proc$libresoc.v:44010$1241 - assign { } { } - assign { } { } - assign $0\dmi0_datasr__oe$next[1:0]$1242 $2\dmi0_datasr__oe$next[1:0]$1244 - attribute \src "libresoc.v:44011.5-44011.29" - switch \initial - attribute \src "libresoc.v:44011.9-44011.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - switch \$253 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$1243 \dmi0_datasr_isir - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$1243 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dmi0_datasr__oe$next[1:0]$1244 2'00 - case - assign $2\dmi0_datasr__oe$next[1:0]$1244 $1\dmi0_datasr__oe$next[1:0]$1243 - end - sync always - update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$1242 - end - attribute \src "libresoc.v:44027.3-44047.6" - process $proc$libresoc.v:44027$1245 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\dmi0_datasr_reg$next[63:0]$1246 $3\dmi0_datasr_reg$next[63:0]$1249 - attribute \src "libresoc.v:44028.5-44028.29" - switch \initial - attribute \src "libresoc.v:44028.9-44028.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" - switch \dmi0_datasr_shift - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_datasr_reg$next[63:0]$1247 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } - case - assign $1\dmi0_datasr_reg$next[63:0]$1247 \dmi0_datasr_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" - switch \dmi0_datasr_capture - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dmi0_datasr_reg$next[63:0]$1248 \dmi0_datasr__i - case - assign $2\dmi0_datasr_reg$next[63:0]$1248 $1\dmi0_datasr_reg$next[63:0]$1247 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dmi0_datasr_reg$next[63:0]$1249 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\dmi0_datasr_reg$next[63:0]$1249 $2\dmi0_datasr_reg$next[63:0]$1248 - end - sync always - update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$1246 - end - attribute \src "libresoc.v:44048.3-44071.6" - process $proc$libresoc.v:44048$1250 - assign { } { } - assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:44049.5-44049.29" - switch \initial - attribute \src "libresoc.v:44049.9-44049.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:571" - switch { \dmi0_datasr_shift \dmi0_addrsr_shift \jtag_wb_datasr_shift \jtag_wb_addrsr_shift \sr0_shift } - attribute \src "libresoc.v:0.0-0.0" - case 5'----1 - assign { } { } - assign $1\TAP_bus__tdo[0:0] \sr0_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case 5'---1- - assign { } { } - assign $1\TAP_bus__tdo[0:0] \jtag_wb_addrsr_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case 5'--1-- - assign { } { } - assign $1\TAP_bus__tdo[0:0] \jtag_wb_datasr_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case 5'-1--- - assign { } { } - assign $1\TAP_bus__tdo[0:0] \dmi0_addrsr_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case 5'1---- - assign { } { } - assign $1\TAP_bus__tdo[0:0] \dmi0_datasr_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\TAP_bus__tdo[0:0] \TAP_tdo - end - sync always - update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] - end - attribute \src "libresoc.v:44072.3-44104.6" - process $proc$libresoc.v:44072$1251 - assign { } { } - assign { } { } - assign { } { } - assign $0\jtag_wb__adr$next[28:0]$1252 $4\jtag_wb__adr$next[28:0]$1256 - attribute \src "libresoc.v:44073.5-44073.29" - switch \initial - attribute \src "libresoc.v:44073.9-44073.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\jtag_wb__adr$next[28:0]$1253 $2\jtag_wb__adr$next[28:0]$1254 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:196" - switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\jtag_wb__adr$next[28:0]$1254 \jtag_wb_addrsr__o - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\jtag_wb__adr$next[28:0]$1254 \$267 [28:0] - case - assign $2\jtag_wb__adr$next[28:0]$1254 \jtag_wb__adr - end - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\jtag_wb__adr$next[28:0]$1253 $3\jtag_wb__adr$next[28:0]$1255 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:224" - switch \jtag_wb__ack - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\jtag_wb__adr$next[28:0]$1255 \$270 [28:0] - case - assign $3\jtag_wb__adr$next[28:0]$1255 \jtag_wb__adr - end - case - assign $1\jtag_wb__adr$next[28:0]$1253 \jtag_wb__adr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\jtag_wb__adr$next[28:0]$1256 29'00000000000000000000000000000 - case - assign $4\jtag_wb__adr$next[28:0]$1256 $1\jtag_wb__adr$next[28:0]$1253 - end - sync always - update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$1252 - end - attribute \src "libresoc.v:44105.3-44157.6" - process $proc$libresoc.v:44105$1257 - assign { } { } - assign { } { } - assign { } { } - assign $0\fsm_state$next[2:0]$1258 $5\fsm_state$next[2:0]$1263 - attribute \src "libresoc.v:44106.5-44106.29" - switch \initial - attribute \src "libresoc.v:44106.9-44106.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\fsm_state$next[2:0]$1259 $2\fsm_state$next[2:0]$1260 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:196" - switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\fsm_state$next[2:0]$1260 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\fsm_state$next[2:0]$1260 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\fsm_state$next[2:0]$1260 3'010 - case - assign $2\fsm_state$next[2:0]$1260 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\fsm_state$next[2:0]$1259 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\fsm_state$next[2:0]$1259 $3\fsm_state$next[2:0]$1261 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:213" - switch \jtag_wb__ack - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fsm_state$next[2:0]$1261 3'000 - case - assign $3\fsm_state$next[2:0]$1261 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\fsm_state$next[2:0]$1259 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\fsm_state$next[2:0]$1259 $4\fsm_state$next[2:0]$1262 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:224" - switch \jtag_wb__ack - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$next[2:0]$1262 3'001 - case - assign $4\fsm_state$next[2:0]$1262 \fsm_state - end - case - assign $1\fsm_state$next[2:0]$1259 \fsm_state - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\fsm_state$next[2:0]$1263 3'000 - case - assign $5\fsm_state$next[2:0]$1263 $1\fsm_state$next[2:0]$1259 - end - sync always - update \fsm_state$next $0\fsm_state$next[2:0]$1258 - end - attribute \src "libresoc.v:44158.3-44184.6" - process $proc$libresoc.v:44158$1264 - assign { } { } - assign { } { } - assign { } { } - assign $0\jtag_wb__dat_w$next[63:0]$1265 $3\jtag_wb__dat_w$next[63:0]$1268 - attribute \src "libresoc.v:44159.5-44159.29" - switch \initial - attribute \src "libresoc.v:44159.9-44159.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\jtag_wb__dat_w$next[63:0]$1266 $2\jtag_wb__dat_w$next[63:0]$1267 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:196" - switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $2\jtag_wb__dat_w$next[63:0]$1267 \jtag_wb__dat_w - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $2\jtag_wb__dat_w$next[63:0]$1267 \jtag_wb__dat_w - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\jtag_wb__dat_w$next[63:0]$1267 \jtag_wb_datasr__o - case - assign $2\jtag_wb__dat_w$next[63:0]$1267 \jtag_wb__dat_w - end - case - assign $1\jtag_wb__dat_w$next[63:0]$1266 \jtag_wb__dat_w - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\jtag_wb__dat_w$next[63:0]$1268 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\jtag_wb__dat_w$next[63:0]$1268 $1\jtag_wb__dat_w$next[63:0]$1266 - end - sync always - update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$1265 - end - attribute \src "libresoc.v:44185.3-44205.6" - process $proc$libresoc.v:44185$1269 - assign { } { } - assign { } { } - assign { } { } - assign $0\jtag_wb_datasr__i$next[63:0]$1270 $3\jtag_wb_datasr__i$next[63:0]$1273 - attribute \src "libresoc.v:44186.5-44186.29" - switch \initial - attribute \src "libresoc.v:44186.9-44186.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\jtag_wb_datasr__i$next[63:0]$1271 $2\jtag_wb_datasr__i$next[63:0]$1272 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:213" - switch \jtag_wb__ack - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\jtag_wb_datasr__i$next[63:0]$1272 \jtag_wb__dat_r - case - assign $2\jtag_wb_datasr__i$next[63:0]$1272 \jtag_wb_datasr__i - end - case - assign $1\jtag_wb_datasr__i$next[63:0]$1271 \jtag_wb_datasr__i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\jtag_wb_datasr__i$next[63:0]$1273 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\jtag_wb_datasr__i$next[63:0]$1273 $1\jtag_wb_datasr__i$next[63:0]$1271 - end - sync always - update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$1270 - end - attribute \src "libresoc.v:44206.3-44238.6" - process $proc$libresoc.v:44206$1274 - assign { } { } - assign { } { } - assign { } { } - assign $0\dmi0_addr_i$next[3:0]$1275 $4\dmi0_addr_i$next[3:0]$1279 - attribute \src "libresoc.v:44207.5-44207.29" - switch \initial - attribute \src "libresoc.v:44207.9-44207.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" - switch \fsm_state$275 - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\dmi0_addr_i$next[3:0]$1276 $2\dmi0_addr_i$next[3:0]$1277 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:148" - switch { \dmi0_datasr__oe \dmi0_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\dmi0_addr_i$next[3:0]$1277 \dmi0_addrsr__o [3:0] - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\dmi0_addr_i$next[3:0]$1277 \$284 [3:0] - case - assign $2\dmi0_addr_i$next[3:0]$1277 \dmi0_addr_i - end - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\dmi0_addr_i$next[3:0]$1276 $3\dmi0_addr_i$next[3:0]$1278 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:176" - switch \dmi0_ack_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dmi0_addr_i$next[3:0]$1278 \$287 [3:0] - case - assign $3\dmi0_addr_i$next[3:0]$1278 \dmi0_addr_i - end - case - assign $1\dmi0_addr_i$next[3:0]$1276 \dmi0_addr_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\dmi0_addr_i$next[3:0]$1279 4'0000 - case - assign $4\dmi0_addr_i$next[3:0]$1279 $1\dmi0_addr_i$next[3:0]$1276 - end - sync always - update \dmi0_addr_i$next $0\dmi0_addr_i$next[3:0]$1275 - end - attribute \src "libresoc.v:44239.3-44291.6" - process $proc$libresoc.v:44239$1280 - assign { } { } - assign { } { } - assign { } { } - assign $0\fsm_state$275$next[2:0]$1281 $5\fsm_state$275$next[2:0]$1286 - attribute \src "libresoc.v:44240.5-44240.29" - switch \initial - attribute \src "libresoc.v:44240.9-44240.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" - switch \fsm_state$275 - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\fsm_state$275$next[2:0]$1282 $2\fsm_state$275$next[2:0]$1283 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:148" - switch { \dmi0_datasr__oe \dmi0_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\fsm_state$275$next[2:0]$1283 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\fsm_state$275$next[2:0]$1283 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\fsm_state$275$next[2:0]$1283 3'010 - case - assign $2\fsm_state$275$next[2:0]$1283 \fsm_state$275 - end - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\fsm_state$275$next[2:0]$1282 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\fsm_state$275$next[2:0]$1282 $3\fsm_state$275$next[2:0]$1284 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:165" - switch \dmi0_ack_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fsm_state$275$next[2:0]$1284 3'000 - case - assign $3\fsm_state$275$next[2:0]$1284 \fsm_state$275 - end - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\fsm_state$275$next[2:0]$1282 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\fsm_state$275$next[2:0]$1282 $4\fsm_state$275$next[2:0]$1285 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:176" - switch \dmi0_ack_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$275$next[2:0]$1285 3'001 - case - assign $4\fsm_state$275$next[2:0]$1285 \fsm_state$275 - end - case - assign $1\fsm_state$275$next[2:0]$1282 \fsm_state$275 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\fsm_state$275$next[2:0]$1286 3'000 - case - assign $5\fsm_state$275$next[2:0]$1286 $1\fsm_state$275$next[2:0]$1282 - end - sync always - update \fsm_state$275$next $0\fsm_state$275$next[2:0]$1281 - end - attribute \src "libresoc.v:44292.3-44318.6" - process $proc$libresoc.v:44292$1287 - assign { } { } - assign { } { } - assign { } { } - assign $0\dmi0_din$next[63:0]$1288 $3\dmi0_din$next[63:0]$1291 - attribute \src "libresoc.v:44293.5-44293.29" - switch \initial - attribute \src "libresoc.v:44293.9-44293.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" - switch \fsm_state$275 - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\dmi0_din$next[63:0]$1289 $2\dmi0_din$next[63:0]$1290 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:148" - switch { \dmi0_datasr__oe \dmi0_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $2\dmi0_din$next[63:0]$1290 \dmi0_din - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $2\dmi0_din$next[63:0]$1290 \dmi0_din - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\dmi0_din$next[63:0]$1290 \dmi0_datasr__o - case - assign $2\dmi0_din$next[63:0]$1290 \dmi0_din - end - case - assign $1\dmi0_din$next[63:0]$1289 \dmi0_din - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dmi0_din$next[63:0]$1291 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\dmi0_din$next[63:0]$1291 $1\dmi0_din$next[63:0]$1289 - end - sync always - update \dmi0_din$next $0\dmi0_din$next[63:0]$1288 - end - attribute \src "libresoc.v:44319.3-44339.6" - process $proc$libresoc.v:44319$1292 - assign { } { } - assign { } { } - assign { } { } - assign $0\dmi0_datasr__i$next[63:0]$1293 $3\dmi0_datasr__i$next[63:0]$1296 - attribute \src "libresoc.v:44320.5-44320.29" - switch \initial - attribute \src "libresoc.v:44320.9-44320.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" - switch \fsm_state$275 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\dmi0_datasr__i$next[63:0]$1294 $2\dmi0_datasr__i$next[63:0]$1295 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:165" - switch \dmi0_ack_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dmi0_datasr__i$next[63:0]$1295 \dmi0_dout - case - assign $2\dmi0_datasr__i$next[63:0]$1295 \dmi0_datasr__i - end - case - assign $1\dmi0_datasr__i$next[63:0]$1294 \dmi0_datasr__i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dmi0_datasr__i$next[63:0]$1296 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\dmi0_datasr__i$next[63:0]$1296 $1\dmi0_datasr__i$next[63:0]$1294 - end - sync always - update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$1293 - end - attribute \src "libresoc.v:44340.3-44408.6" - process $proc$libresoc.v:44340$1297 - assign { } { } - assign { } { } - assign { } { } - assign $0\io_sr$next[49:0]$1298 $2\io_sr$next[49:0]$1300 - attribute \src "libresoc.v:44341.5-44341.29" - switch \initial - attribute \src "libresoc.v:44341.9-44341.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:439" - switch { \io_update \io_shift \io_capture } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $1\io_sr$next[49:0]$1299 [0] \uart_tx__core__o - assign $1\io_sr$next[49:0]$1299 [1] \uart_rx__pad__i - assign $1\io_sr$next[49:0]$1299 [2] \gpio_gpio0__pad__i - assign $1\io_sr$next[49:0]$1299 [3] \gpio_gpio0__core__o - assign $1\io_sr$next[49:0]$1299 [4] \gpio_gpio0__core__oe - assign $1\io_sr$next[49:0]$1299 [5] \gpio_gpio1__pad__i - assign $1\io_sr$next[49:0]$1299 [6] \gpio_gpio1__core__o - assign $1\io_sr$next[49:0]$1299 [7] \gpio_gpio1__core__oe - assign $1\io_sr$next[49:0]$1299 [8] \gpio_gpio2__pad__i - assign $1\io_sr$next[49:0]$1299 [9] \gpio_gpio2__core__o - assign $1\io_sr$next[49:0]$1299 [10] \gpio_gpio2__core__oe - assign $1\io_sr$next[49:0]$1299 [11] \gpio_gpio3__pad__i - assign $1\io_sr$next[49:0]$1299 [12] \gpio_gpio3__core__o - assign $1\io_sr$next[49:0]$1299 [13] \gpio_gpio3__core__oe - assign $1\io_sr$next[49:0]$1299 [14] \gpio_gpio4__pad__i - assign $1\io_sr$next[49:0]$1299 [15] \gpio_gpio4__core__o - assign $1\io_sr$next[49:0]$1299 [16] \gpio_gpio4__core__oe - assign $1\io_sr$next[49:0]$1299 [17] \gpio_gpio5__pad__i - assign $1\io_sr$next[49:0]$1299 [18] \gpio_gpio5__core__o - assign $1\io_sr$next[49:0]$1299 [19] \gpio_gpio5__core__oe - assign $1\io_sr$next[49:0]$1299 [20] \gpio_gpio6__pad__i - assign $1\io_sr$next[49:0]$1299 [21] \gpio_gpio6__core__o - assign $1\io_sr$next[49:0]$1299 [22] \gpio_gpio6__core__oe - assign $1\io_sr$next[49:0]$1299 [23] \gpio_gpio7__pad__i - assign $1\io_sr$next[49:0]$1299 [24] \gpio_gpio7__core__o - assign $1\io_sr$next[49:0]$1299 [25] \gpio_gpio7__core__oe - assign $1\io_sr$next[49:0]$1299 [26] \gpio_gpio8__pad__i - assign $1\io_sr$next[49:0]$1299 [27] \gpio_gpio8__core__o - assign $1\io_sr$next[49:0]$1299 [28] \gpio_gpio8__core__oe - assign $1\io_sr$next[49:0]$1299 [29] \gpio_gpio9__pad__i - assign $1\io_sr$next[49:0]$1299 [30] \gpio_gpio9__core__o - assign $1\io_sr$next[49:0]$1299 [31] \gpio_gpio9__core__oe - assign $1\io_sr$next[49:0]$1299 [32] \gpio_gpio10__pad__i - assign $1\io_sr$next[49:0]$1299 [33] \gpio_gpio10__core__o - assign $1\io_sr$next[49:0]$1299 [34] \gpio_gpio10__core__oe - assign $1\io_sr$next[49:0]$1299 [35] \gpio_gpio11__pad__i - assign $1\io_sr$next[49:0]$1299 [36] \gpio_gpio11__core__o - assign $1\io_sr$next[49:0]$1299 [37] \gpio_gpio11__core__oe - assign $1\io_sr$next[49:0]$1299 [38] \gpio_gpio12__pad__i - assign $1\io_sr$next[49:0]$1299 [39] \gpio_gpio12__core__o - assign $1\io_sr$next[49:0]$1299 [40] \gpio_gpio12__core__oe - assign $1\io_sr$next[49:0]$1299 [41] \gpio_gpio13__pad__i - assign $1\io_sr$next[49:0]$1299 [42] \gpio_gpio13__core__o - assign $1\io_sr$next[49:0]$1299 [43] \gpio_gpio13__core__oe - assign $1\io_sr$next[49:0]$1299 [44] \gpio_gpio14__pad__i - assign $1\io_sr$next[49:0]$1299 [45] \gpio_gpio14__core__o - assign $1\io_sr$next[49:0]$1299 [46] \gpio_gpio14__core__oe - assign $1\io_sr$next[49:0]$1299 [47] \gpio_gpio15__pad__i - assign $1\io_sr$next[49:0]$1299 [48] \gpio_gpio15__core__o - assign $1\io_sr$next[49:0]$1299 [49] \gpio_gpio15__core__oe - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $1\io_sr$next[49:0]$1299 { \io_sr [48:0] \TAP_bus__tdi } - case - assign $1\io_sr$next[49:0]$1299 \io_sr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\io_sr$next[49:0]$1300 50'00000000000000000000000000000000000000000000000000 - case - assign $2\io_sr$next[49:0]$1300 $1\io_sr$next[49:0]$1299 - end - sync always - update \io_sr$next $0\io_sr$next[49:0]$1298 - end - attribute \src "libresoc.v:44409.3-44424.6" - process $proc$libresoc.v:44409$1301 - assign { } { } - assign { } { } - assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] - attribute \src "libresoc.v:44410.5-44410.29" - switch \initial - attribute \src "libresoc.v:44410.9-44410.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" - switch { \$159 \$147 \_fsm_isir } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $1\TAP_tdo[0:0] \_irblock_tdo - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $1\TAP_tdo[0:0] \_idblock_TAP_id_tdo - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $1\TAP_tdo[0:0] \io_sr [49] - case - assign $1\TAP_tdo[0:0] 1'0 - end - sync always - update \TAP_tdo $0\TAP_tdo[0:0] - end - attribute \src "libresoc.v:44425.3-44445.6" - process $proc$libresoc.v:44425$1302 - assign { } { } - assign { } { } - assign { } { } - assign $0\io_bd$next[49:0]$1303 $2\io_bd$next[49:0]$1305 - attribute \src "libresoc.v:44426.5-44426.29" - switch \initial - attribute \src "libresoc.v:44426.9-44426.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:439" - switch { \io_update \io_shift \io_capture } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $1\io_bd$next[49:0]$1304 \io_bd - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $1\io_bd$next[49:0]$1304 \io_bd - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $1\io_bd$next[49:0]$1304 \io_sr - case - assign $1\io_bd$next[49:0]$1304 \io_bd - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \negjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\io_bd$next[49:0]$1305 50'00000000000000000000000000000000000000000000000000 - case - assign $2\io_bd$next[49:0]$1305 $1\io_bd$next[49:0]$1304 - end - sync always - update \io_bd$next $0\io_bd$next[49:0]$1303 - end - attribute \src "libresoc.v:44446.3-44454.6" - process $proc$libresoc.v:44446$1306 - assign { } { } - assign { } { } - assign $0\sr0_update_core$next[0:0]$1307 $1\sr0_update_core$next[0:0]$1308 - attribute \src "libresoc.v:44447.5-44447.29" - switch \initial - attribute \src "libresoc.v:44447.9-44447.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sr0_update_core$next[0:0]$1308 1'0 - case - assign $1\sr0_update_core$next[0:0]$1308 \sr0_update - end - sync always - update \sr0_update_core$next $0\sr0_update_core$next[0:0]$1307 - end - attribute \src "libresoc.v:44455.3-44463.6" - process $proc$libresoc.v:44455$1309 - assign { } { } - assign { } { } - assign $0\sr0_update_core_prev$next[0:0]$1310 $1\sr0_update_core_prev$next[0:0]$1311 - attribute \src "libresoc.v:44456.5-44456.29" - switch \initial - attribute \src "libresoc.v:44456.9-44456.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sr0_update_core_prev$next[0:0]$1311 1'0 - case - assign $1\sr0_update_core_prev$next[0:0]$1311 \sr0_update_core - end - sync always - update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$1310 - end - attribute \src "libresoc.v:44464.3-44480.6" - process $proc$libresoc.v:44464$1312 - assign { } { } - assign { } { } - assign $0\sr0__oe$next[0:0]$1313 $2\sr0__oe$next[0:0]$1315 - attribute \src "libresoc.v:44465.5-44465.29" - switch \initial - attribute \src "libresoc.v:44465.9-44465.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - switch \$177 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sr0__oe$next[0:0]$1314 \sr0_isir - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\sr0__oe$next[0:0]$1314 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\sr0__oe$next[0:0]$1315 1'0 - case - assign $2\sr0__oe$next[0:0]$1315 $1\sr0__oe$next[0:0]$1314 - end - sync always - update \sr0__oe$next $0\sr0__oe$next[0:0]$1313 - end - attribute \src "libresoc.v:44481.3-44501.6" - process $proc$libresoc.v:44481$1316 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\sr0_reg$next[2:0]$1317 $3\sr0_reg$next[2:0]$1320 - attribute \src "libresoc.v:44482.5-44482.29" - switch \initial - attribute \src "libresoc.v:44482.9-44482.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" - switch \sr0_shift - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sr0_reg$next[2:0]$1318 { \TAP_bus__tdi \sr0_reg [2:1] } - case - assign $1\sr0_reg$next[2:0]$1318 \sr0_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" - switch \sr0_capture - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\sr0_reg$next[2:0]$1319 \sr0__i - case - assign $2\sr0_reg$next[2:0]$1319 $1\sr0_reg$next[2:0]$1318 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\sr0_reg$next[2:0]$1320 3'000 - case - assign $3\sr0_reg$next[2:0]$1320 $2\sr0_reg$next[2:0]$1319 - end - sync always - update \sr0_reg$next $0\sr0_reg$next[2:0]$1317 - end - attribute \src "libresoc.v:44502.3-44510.6" - process $proc$libresoc.v:44502$1321 - assign { } { } - assign { } { } - assign $0\jtag_wb_addrsr_update_core$next[0:0]$1322 $1\jtag_wb_addrsr_update_core$next[0:0]$1323 - attribute \src "libresoc.v:44503.5-44503.29" - switch \initial - attribute \src "libresoc.v:44503.9-44503.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_addrsr_update_core$next[0:0]$1323 1'0 - case - assign $1\jtag_wb_addrsr_update_core$next[0:0]$1323 \jtag_wb_addrsr_update - end - sync always - update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$1322 - end - attribute \src "libresoc.v:44511.3-44519.6" - process $proc$libresoc.v:44511$1324 - assign { } { } - assign { } { } - assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1325 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1326 - attribute \src "libresoc.v:44512.5-44512.29" - switch \initial - attribute \src "libresoc.v:44512.9-44512.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1326 1'0 - case - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1326 \jtag_wb_addrsr_update_core - end - sync always - update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1325 - end - attribute \src "libresoc.v:44520.3-44536.6" - process $proc$libresoc.v:44520$1327 - assign { } { } - assign { } { } - assign $0\jtag_wb_addrsr__oe$next[0:0]$1328 $2\jtag_wb_addrsr__oe$next[0:0]$1330 - attribute \src "libresoc.v:44521.5-44521.29" - switch \initial - attribute \src "libresoc.v:44521.9-44521.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - switch \$195 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$1329 \jtag_wb_addrsr_isir - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$1329 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\jtag_wb_addrsr__oe$next[0:0]$1330 1'0 - case - assign $2\jtag_wb_addrsr__oe$next[0:0]$1330 $1\jtag_wb_addrsr__oe$next[0:0]$1329 - end - sync always - update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$1328 - end - attribute \src "libresoc.v:44537.3-44557.6" - process $proc$libresoc.v:44537$1331 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\jtag_wb_addrsr_reg$next[28:0]$1332 $3\jtag_wb_addrsr_reg$next[28:0]$1335 - attribute \src "libresoc.v:44538.5-44538.29" - switch \initial - attribute \src "libresoc.v:44538.9-44538.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" - switch \jtag_wb_addrsr_shift - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_addrsr_reg$next[28:0]$1333 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } - case - assign $1\jtag_wb_addrsr_reg$next[28:0]$1333 \jtag_wb_addrsr_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" - switch \jtag_wb_addrsr_capture - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\jtag_wb_addrsr_reg$next[28:0]$1334 \jtag_wb_addrsr__i - case - assign $2\jtag_wb_addrsr_reg$next[28:0]$1334 $1\jtag_wb_addrsr_reg$next[28:0]$1333 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\jtag_wb_addrsr_reg$next[28:0]$1335 29'00000000000000000000000000000 - case - assign $3\jtag_wb_addrsr_reg$next[28:0]$1335 $2\jtag_wb_addrsr_reg$next[28:0]$1334 - end - sync always - update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$1332 - end - attribute \src "libresoc.v:44558.3-44566.6" - process $proc$libresoc.v:44558$1336 - assign { } { } - assign { } { } - assign $0\jtag_wb_datasr_update_core$next[0:0]$1337 $1\jtag_wb_datasr_update_core$next[0:0]$1338 - attribute \src "libresoc.v:44559.5-44559.29" - switch \initial - attribute \src "libresoc.v:44559.9-44559.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_datasr_update_core$next[0:0]$1338 1'0 - case - assign $1\jtag_wb_datasr_update_core$next[0:0]$1338 \jtag_wb_datasr_update - end - sync always - update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$1337 - end - attribute \src "libresoc.v:44567.3-44575.6" - process $proc$libresoc.v:44567$1339 - assign { } { } - assign { } { } - assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$1340 $1\jtag_wb_datasr_update_core_prev$next[0:0]$1341 - attribute \src "libresoc.v:44568.5-44568.29" - switch \initial - attribute \src "libresoc.v:44568.9-44568.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$1341 1'0 - case - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$1341 \jtag_wb_datasr_update_core - end - sync always - update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$1340 - end - attribute \src "libresoc.v:44576.3-44592.6" - process $proc$libresoc.v:44576$1342 - assign { } { } - assign { } { } - assign $0\jtag_wb_datasr__oe$next[1:0]$1343 $2\jtag_wb_datasr__oe$next[1:0]$1345 - attribute \src "libresoc.v:44577.5-44577.29" - switch \initial - attribute \src "libresoc.v:44577.9-44577.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - switch \$215 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_datasr__oe$next[1:0]$1344 \jtag_wb_datasr_isir - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\jtag_wb_datasr__oe$next[1:0]$1344 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\jtag_wb_datasr__oe$next[1:0]$1345 2'00 - case - assign $2\jtag_wb_datasr__oe$next[1:0]$1345 $1\jtag_wb_datasr__oe$next[1:0]$1344 - end - sync always - update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$1343 - end - attribute \src "libresoc.v:44593.3-44613.6" - process $proc$libresoc.v:44593$1346 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\jtag_wb_datasr_reg$next[63:0]$1347 $3\jtag_wb_datasr_reg$next[63:0]$1350 - attribute \src "libresoc.v:44594.5-44594.29" - switch \initial - attribute \src "libresoc.v:44594.9-44594.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" - switch \jtag_wb_datasr_shift - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_datasr_reg$next[63:0]$1348 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } - case - assign $1\jtag_wb_datasr_reg$next[63:0]$1348 \jtag_wb_datasr_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" - switch \jtag_wb_datasr_capture - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\jtag_wb_datasr_reg$next[63:0]$1349 \jtag_wb_datasr__i - case - assign $2\jtag_wb_datasr_reg$next[63:0]$1349 $1\jtag_wb_datasr_reg$next[63:0]$1348 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\jtag_wb_datasr_reg$next[63:0]$1350 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\jtag_wb_datasr_reg$next[63:0]$1350 $2\jtag_wb_datasr_reg$next[63:0]$1349 - end - sync always - update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$1347 - end - attribute \src "libresoc.v:44614.3-44622.6" - process $proc$libresoc.v:44614$1351 - assign { } { } - assign { } { } - assign $0\dmi0_addrsr_update_core$next[0:0]$1352 $1\dmi0_addrsr_update_core$next[0:0]$1353 - attribute \src "libresoc.v:44615.5-44615.29" - switch \initial - attribute \src "libresoc.v:44615.9-44615.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_addrsr_update_core$next[0:0]$1353 1'0 - case - assign $1\dmi0_addrsr_update_core$next[0:0]$1353 \dmi0_addrsr_update - end - sync always - update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$1352 - end - attribute \src "libresoc.v:44623.3-44631.6" - process $proc$libresoc.v:44623$1354 - assign { } { } - assign { } { } - assign $0\dmi0_addrsr_update_core_prev$next[0:0]$1355 $1\dmi0_addrsr_update_core_prev$next[0:0]$1356 - attribute \src "libresoc.v:44624.5-44624.29" - switch \initial - attribute \src "libresoc.v:44624.9-44624.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$1356 1'0 - case - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$1356 \dmi0_addrsr_update_core - end - sync always - update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$1355 - end - attribute \src "libresoc.v:44632.3-44648.6" - process $proc$libresoc.v:44632$1357 - assign { } { } - assign { } { } - assign $0\dmi0_addrsr__oe$next[0:0]$1358 $2\dmi0_addrsr__oe$next[0:0]$1360 - attribute \src "libresoc.v:44633.5-44633.29" - switch \initial - attribute \src "libresoc.v:44633.9-44633.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - switch \$233 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$1359 \dmi0_addrsr_isir - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$1359 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dmi0_addrsr__oe$next[0:0]$1360 1'0 - case - assign $2\dmi0_addrsr__oe$next[0:0]$1360 $1\dmi0_addrsr__oe$next[0:0]$1359 - end - sync always - update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$1358 - end - attribute \src "libresoc.v:44649.3-44669.6" - process $proc$libresoc.v:44649$1361 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\dmi0_addrsr_reg$next[7:0]$1362 $3\dmi0_addrsr_reg$next[7:0]$1365 - attribute \src "libresoc.v:44650.5-44650.29" - switch \initial - attribute \src "libresoc.v:44650.9-44650.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" - switch \dmi0_addrsr_shift - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_addrsr_reg$next[7:0]$1363 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } - case - assign $1\dmi0_addrsr_reg$next[7:0]$1363 \dmi0_addrsr_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" - switch \dmi0_addrsr_capture - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dmi0_addrsr_reg$next[7:0]$1364 \dmi0_addrsr__i - case - assign $2\dmi0_addrsr_reg$next[7:0]$1364 $1\dmi0_addrsr_reg$next[7:0]$1363 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dmi0_addrsr_reg$next[7:0]$1365 8'00000000 - case - assign $3\dmi0_addrsr_reg$next[7:0]$1365 $2\dmi0_addrsr_reg$next[7:0]$1364 - end - sync always - update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$1362 - end - attribute \src "libresoc.v:44670.3-44678.6" - process $proc$libresoc.v:44670$1366 - assign { } { } - assign { } { } - assign $0\dmi0_datasr_update_core$next[0:0]$1367 $1\dmi0_datasr_update_core$next[0:0]$1368 - attribute \src "libresoc.v:44671.5-44671.29" - switch \initial - attribute \src "libresoc.v:44671.9-44671.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_datasr_update_core$next[0:0]$1368 1'0 - case - assign $1\dmi0_datasr_update_core$next[0:0]$1368 \dmi0_datasr_update - end - sync always - update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$1367 - end - connect \$9 $eq$libresoc.v:43764$1064_Y - connect \$99 $ternary$libresoc.v:43765$1065_Y - connect \$101 $ternary$libresoc.v:43766$1066_Y - connect \$103 $ternary$libresoc.v:43767$1067_Y - connect \$105 $ternary$libresoc.v:43768$1068_Y - connect \$107 $ternary$libresoc.v:43769$1069_Y - connect \$109 $ternary$libresoc.v:43770$1070_Y - connect \$111 $ternary$libresoc.v:43771$1071_Y - connect \$113 $ternary$libresoc.v:43772$1072_Y - connect \$115 $ternary$libresoc.v:43773$1073_Y - connect \$117 $ternary$libresoc.v:43774$1074_Y - connect \$11 $eq$libresoc.v:43775$1075_Y - connect \$119 $ternary$libresoc.v:43776$1076_Y - connect \$121 $ternary$libresoc.v:43777$1077_Y - connect \$123 $ternary$libresoc.v:43778$1078_Y - connect \$125 $ternary$libresoc.v:43779$1079_Y - connect \$127 $ternary$libresoc.v:43780$1080_Y - connect \$129 $ternary$libresoc.v:43781$1081_Y - connect \$131 $ternary$libresoc.v:43782$1082_Y - connect \$133 $ternary$libresoc.v:43783$1083_Y - connect \$135 $ternary$libresoc.v:43784$1084_Y - connect \$137 $ternary$libresoc.v:43785$1085_Y - connect \$13 $or$libresoc.v:43786$1086_Y - connect \$139 $ternary$libresoc.v:43787$1087_Y - connect \$141 $eq$libresoc.v:43788$1088_Y - connect \$143 $eq$libresoc.v:43789$1089_Y - connect \$145 $or$libresoc.v:43790$1090_Y - connect \$147 $and$libresoc.v:43791$1091_Y - connect \$149 $eq$libresoc.v:43792$1092_Y - connect \$151 $eq$libresoc.v:43793$1093_Y - connect \$153 $or$libresoc.v:43794$1094_Y - connect \$155 $eq$libresoc.v:43795$1095_Y - connect \$157 $or$libresoc.v:43796$1096_Y - connect \$15 $eq$libresoc.v:43797$1097_Y - connect \$159 $and$libresoc.v:43798$1098_Y - connect \$161 $eq$libresoc.v:43799$1099_Y - connect \$163 $ne$libresoc.v:43800$1100_Y - connect \$165 $and$libresoc.v:43801$1101_Y - connect \$167 $ne$libresoc.v:43802$1102_Y - connect \$169 $and$libresoc.v:43803$1103_Y - connect \$171 $ne$libresoc.v:43804$1104_Y - connect \$173 $and$libresoc.v:43805$1105_Y - connect \$175 $not$libresoc.v:43806$1106_Y - connect \$177 $and$libresoc.v:43807$1107_Y - connect \$17 $or$libresoc.v:43808$1108_Y - connect \$179 $eq$libresoc.v:43809$1109_Y - connect \$181 $ne$libresoc.v:43810$1110_Y - connect \$183 $and$libresoc.v:43811$1111_Y - connect \$185 $ne$libresoc.v:43812$1112_Y - connect \$187 $and$libresoc.v:43813$1113_Y - connect \$189 $ne$libresoc.v:43814$1114_Y - connect \$191 $and$libresoc.v:43815$1115_Y - connect \$193 $not$libresoc.v:43816$1116_Y - connect \$195 $and$libresoc.v:43817$1117_Y - connect \$197 $eq$libresoc.v:43818$1118_Y - connect \$1 $eq$libresoc.v:43819$1119_Y - connect \$19 $and$libresoc.v:43820$1120_Y - connect \$199 $eq$libresoc.v:43821$1121_Y - connect \$201 $ne$libresoc.v:43822$1122_Y - connect \$203 $and$libresoc.v:43823$1123_Y - connect \$205 $ne$libresoc.v:43824$1124_Y - connect \$207 $and$libresoc.v:43825$1125_Y - connect \$209 $ne$libresoc.v:43826$1126_Y - connect \$211 $and$libresoc.v:43827$1127_Y - connect \$213 $not$libresoc.v:43828$1128_Y - connect \$215 $and$libresoc.v:43829$1129_Y - connect \$217 $eq$libresoc.v:43830$1130_Y - connect \$21 $and$libresoc.v:43831$1131_Y - connect \$219 $ne$libresoc.v:43832$1132_Y - connect \$221 $and$libresoc.v:43833$1133_Y - connect \$223 $ne$libresoc.v:43834$1134_Y - connect \$225 $and$libresoc.v:43835$1135_Y - connect \$227 $ne$libresoc.v:43836$1136_Y - connect \$229 $and$libresoc.v:43837$1137_Y - connect \$231 $not$libresoc.v:43838$1138_Y - connect \$233 $and$libresoc.v:43839$1139_Y - connect \$235 $eq$libresoc.v:43840$1140_Y - connect \$237 $eq$libresoc.v:43841$1141_Y - connect \$23 $eq$libresoc.v:43842$1142_Y - connect \$239 $ne$libresoc.v:43843$1143_Y - connect \$241 $and$libresoc.v:43844$1144_Y - connect \$243 $ne$libresoc.v:43845$1145_Y - connect \$245 $and$libresoc.v:43846$1146_Y - connect \$247 $ne$libresoc.v:43847$1147_Y - connect \$249 $and$libresoc.v:43848$1148_Y - connect \$251 $not$libresoc.v:43849$1149_Y - connect \$253 $and$libresoc.v:43850$1150_Y - connect \$256 $eq$libresoc.v:43851$1151_Y - connect \$255 $not$libresoc.v:43852$1152_Y - connect \$25 $eq$libresoc.v:43853$1153_Y - connect \$259 $eq$libresoc.v:43854$1154_Y - connect \$261 $eq$libresoc.v:43855$1155_Y - connect \$263 $or$libresoc.v:43856$1156_Y - connect \$265 $eq$libresoc.v:43857$1157_Y - connect \$268 $add$libresoc.v:43858$1158_Y - connect \$271 $add$libresoc.v:43859$1159_Y - connect \$273 $pos$libresoc.v:43860$1161_Y - connect \$276 $eq$libresoc.v:43861$1162_Y - connect \$278 $eq$libresoc.v:43862$1163_Y - connect \$27 $or$libresoc.v:43863$1164_Y - connect \$280 $or$libresoc.v:43864$1165_Y - connect \$282 $eq$libresoc.v:43865$1166_Y - connect \$285 $add$libresoc.v:43866$1167_Y - connect \$288 $add$libresoc.v:43867$1168_Y - connect \$29 $eq$libresoc.v:43868$1169_Y - connect \$31 $or$libresoc.v:43869$1170_Y - connect \$33 $and$libresoc.v:43870$1171_Y - connect \$35 $and$libresoc.v:43871$1172_Y - connect \$37 $eq$libresoc.v:43872$1173_Y - connect \$3 $eq$libresoc.v:43873$1174_Y - connect \$39 $eq$libresoc.v:43874$1175_Y - connect \$41 $ternary$libresoc.v:43875$1176_Y - connect \$43 $ternary$libresoc.v:43876$1177_Y - connect \$45 $ternary$libresoc.v:43877$1178_Y - connect \$47 $ternary$libresoc.v:43878$1179_Y - connect \$49 $ternary$libresoc.v:43879$1180_Y - connect \$51 $ternary$libresoc.v:43880$1181_Y - connect \$53 $ternary$libresoc.v:43881$1182_Y - connect \$55 $ternary$libresoc.v:43882$1183_Y - connect \$57 $ternary$libresoc.v:43883$1184_Y - connect \$5 $or$libresoc.v:43884$1185_Y - connect \$59 $ternary$libresoc.v:43885$1186_Y - connect \$61 $ternary$libresoc.v:43886$1187_Y - connect \$63 $ternary$libresoc.v:43887$1188_Y - connect \$65 $ternary$libresoc.v:43888$1189_Y - connect \$67 $ternary$libresoc.v:43889$1190_Y - connect \$69 $ternary$libresoc.v:43890$1191_Y - connect \$71 $ternary$libresoc.v:43891$1192_Y - connect \$73 $ternary$libresoc.v:43892$1193_Y - connect \$75 $ternary$libresoc.v:43893$1194_Y - connect \$77 $ternary$libresoc.v:43894$1195_Y - connect \$7 $and$libresoc.v:43895$1196_Y - connect \$79 $ternary$libresoc.v:43896$1197_Y - connect \$81 $ternary$libresoc.v:43897$1198_Y - connect \$83 $ternary$libresoc.v:43898$1199_Y - connect \$85 $ternary$libresoc.v:43899$1200_Y - connect \$87 $ternary$libresoc.v:43900$1201_Y - connect \$89 $ternary$libresoc.v:43901$1202_Y - connect \$91 $ternary$libresoc.v:43902$1203_Y - connect \$93 $ternary$libresoc.v:43903$1204_Y - connect \$95 $ternary$libresoc.v:43904$1205_Y - connect \$97 $ternary$libresoc.v:43905$1206_Y - connect \$267 \$268 - connect \$270 \$271 - connect \$284 \$285 - connect \$287 \$288 - connect \sr0__i \sr0__o - connect \dmi0_we_i \$282 - connect \dmi0_req_i \$280 - connect \dmi0_addrsr__i \$273 - connect \jtag_wb__we \$265 - connect \jtag_wb__stb \$263 - connect \jtag_wb__cyc \$255 - connect \jtag_wb__sel 1'1 - connect \jtag_wb_addrsr__i \jtag_wb__adr - connect \dmi0_datasr_update \$249 - connect \dmi0_datasr_shift \$245 - connect \dmi0_datasr_capture \$241 - connect \dmi0_datasr_isir { \$237 \$235 } - connect \dmi0_datasr__o \dmi0_datasr_reg - connect \dmi0_addrsr_update \$229 - connect \dmi0_addrsr_shift \$225 - connect \dmi0_addrsr_capture \$221 - connect \dmi0_addrsr_isir \$217 - connect \dmi0_addrsr__o \dmi0_addrsr_reg - connect \jtag_wb_datasr_update \$211 - connect \jtag_wb_datasr_shift \$207 - connect \jtag_wb_datasr_capture \$203 - connect \jtag_wb_datasr_isir { \$199 \$197 } - connect \jtag_wb_datasr__o \jtag_wb_datasr_reg - connect \jtag_wb_addrsr_update \$191 - connect \jtag_wb_addrsr_shift \$187 - connect \jtag_wb_addrsr_capture \$183 - connect \jtag_wb_addrsr_isir \$179 - connect \jtag_wb_addrsr__o \jtag_wb_addrsr_reg - connect \sr0_update \$173 - connect \sr0_shift \$169 - connect \sr0_capture \$165 - connect \sr0_isir \$161 - connect \sr0__o \sr0_reg - connect \gpio_gpio15__pad__oe \$139 - connect \gpio_gpio15__pad__o \$137 - connect \gpio_gpio15__core__i \$135 - connect \gpio_gpio14__pad__oe \$133 - connect \gpio_gpio14__pad__o \$131 - connect \gpio_gpio14__core__i \$129 - connect \gpio_gpio13__pad__oe \$127 - connect \gpio_gpio13__pad__o \$125 - connect \gpio_gpio13__core__i \$123 - connect \gpio_gpio12__pad__oe \$121 - connect \gpio_gpio12__pad__o \$119 - connect \gpio_gpio12__core__i \$117 - connect \gpio_gpio11__pad__oe \$115 - connect \gpio_gpio11__pad__o \$113 - connect \gpio_gpio11__core__i \$111 - connect \gpio_gpio10__pad__oe \$109 - connect \gpio_gpio10__pad__o \$107 - connect \gpio_gpio10__core__i \$105 - connect \gpio_gpio9__pad__oe \$103 - connect \gpio_gpio9__pad__o \$101 - connect \gpio_gpio9__core__i \$99 - connect \gpio_gpio8__pad__oe \$97 - connect \gpio_gpio8__pad__o \$95 - connect \gpio_gpio8__core__i \$93 - connect \gpio_gpio7__pad__oe \$91 - connect \gpio_gpio7__pad__o \$89 - connect \gpio_gpio7__core__i \$87 - connect \gpio_gpio6__pad__oe \$85 - connect \gpio_gpio6__pad__o \$83 - connect \gpio_gpio6__core__i \$81 - connect \gpio_gpio5__pad__oe \$79 - connect \gpio_gpio5__pad__o \$77 - connect \gpio_gpio5__core__i \$75 - connect \gpio_gpio4__pad__oe \$73 - connect \gpio_gpio4__pad__o \$71 - connect \gpio_gpio4__core__i \$69 - connect \gpio_gpio3__pad__oe \$67 - connect \gpio_gpio3__pad__o \$65 - connect \gpio_gpio3__core__i \$63 - connect \gpio_gpio2__pad__oe \$61 - connect \gpio_gpio2__pad__o \$59 - connect \gpio_gpio2__core__i \$57 - connect \gpio_gpio1__pad__oe \$55 - connect \gpio_gpio1__pad__o \$53 - connect \gpio_gpio1__core__i \$51 - connect \gpio_gpio0__pad__oe \$49 - connect \gpio_gpio0__pad__o \$47 - connect \gpio_gpio0__core__i \$45 - connect \uart_rx__core__i \$43 - connect \uart_tx__pad__o \$41 - connect \io_bd2core \$39 - connect \io_bd2io \$37 - connect \io_update \$35 - connect \io_shift \$21 - connect \io_capture \$7 -end -attribute \src "ls180.v:4.1-10347.10" -attribute \cells_not_processed 1 -module \ls180 - attribute \src "ls180.v:10040.1-10050.4" - wire width 7 $0$memwr$\mem$ls180.v:10042$1_ADDR[6:0]$2693 - attribute \src "ls180.v:10040.1-10050.4" - wire width 32 $0$memwr$\mem$ls180.v:10042$1_DATA[31:0]$2694 - attribute \src "ls180.v:10040.1-10050.4" - wire width 32 $0$memwr$\mem$ls180.v:10042$1_EN[31:0]$2695 - attribute \src "ls180.v:10040.1-10050.4" - wire width 7 $0$memwr$\mem$ls180.v:10044$2_ADDR[6:0]$2696 - attribute \src "ls180.v:10040.1-10050.4" - wire width 32 $0$memwr$\mem$ls180.v:10044$2_DATA[31:0]$2697 - attribute \src "ls180.v:10040.1-10050.4" - wire width 32 $0$memwr$\mem$ls180.v:10044$2_EN[31:0]$2698 - attribute \src "ls180.v:10040.1-10050.4" - wire width 7 $0$memwr$\mem$ls180.v:10046$3_ADDR[6:0]$2699 - attribute \src "ls180.v:10040.1-10050.4" - wire width 32 $0$memwr$\mem$ls180.v:10046$3_DATA[31:0]$2700 - attribute \src "ls180.v:10040.1-10050.4" - wire width 32 $0$memwr$\mem$ls180.v:10046$3_EN[31:0]$2701 - attribute \src "ls180.v:10040.1-10050.4" - wire width 7 $0$memwr$\mem$ls180.v:10048$4_ADDR[6:0]$2702 - attribute \src "ls180.v:10040.1-10050.4" - wire width 32 $0$memwr$\mem$ls180.v:10048$4_DATA[31:0]$2703 - attribute \src "ls180.v:10040.1-10050.4" - wire width 32 $0$memwr$\mem$ls180.v:10048$4_EN[31:0]$2704 - attribute \src "ls180.v:10060.1-10064.4" - wire width 3 $0$memwr$\storage$ls180.v:10062$5_ADDR[2:0]$2707 - attribute \src "ls180.v:10060.1-10064.4" - wire width 25 $0$memwr$\storage$ls180.v:10062$5_DATA[24:0]$2708 - attribute \src "ls180.v:10060.1-10064.4" - wire width 25 $0$memwr$\storage$ls180.v:10062$5_EN[24:0]$2709 - attribute \src "ls180.v:10074.1-10078.4" - wire width 3 $0$memwr$\storage_1$ls180.v:10076$6_ADDR[2:0]$2714 - attribute \src "ls180.v:10074.1-10078.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10076$6_DATA[24:0]$2715 - attribute \src "ls180.v:10074.1-10078.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10076$6_EN[24:0]$2716 - attribute \src "ls180.v:10088.1-10092.4" - wire width 3 $0$memwr$\storage_2$ls180.v:10090$7_ADDR[2:0]$2721 - attribute \src "ls180.v:10088.1-10092.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10090$7_DATA[24:0]$2722 - attribute \src "ls180.v:10088.1-10092.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10090$7_EN[24:0]$2723 - attribute \src "ls180.v:10102.1-10106.4" - wire width 3 $0$memwr$\storage_3$ls180.v:10104$8_ADDR[2:0]$2728 - attribute \src "ls180.v:10102.1-10106.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10104$8_DATA[24:0]$2729 - attribute \src "ls180.v:10102.1-10106.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10104$8_EN[24:0]$2730 - attribute \src "ls180.v:10117.1-10121.4" - wire width 4 $0$memwr$\storage_4$ls180.v:10119$9_ADDR[3:0]$2735 - attribute \src "ls180.v:10117.1-10121.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10119$9_DATA[9:0]$2736 - attribute \src "ls180.v:10117.1-10121.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10119$9_EN[9:0]$2737 - attribute \src "ls180.v:10134.1-10138.4" - wire width 4 $0$memwr$\storage_5$ls180.v:10136$10_ADDR[3:0]$2742 - attribute \src "ls180.v:10134.1-10138.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10136$10_DATA[9:0]$2743 - attribute \src "ls180.v:10134.1-10138.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10136$10_EN[9:0]$2744 - attribute \src "ls180.v:10150.1-10154.4" - wire width 5 $0$memwr$\storage_6$ls180.v:10152$11_ADDR[4:0]$2749 - attribute \src "ls180.v:10150.1-10154.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10152$11_DATA[9:0]$2750 - attribute \src "ls180.v:10150.1-10154.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10152$11_EN[9:0]$2751 - attribute \src "ls180.v:10164.1-10168.4" - wire width 5 $0$memwr$\storage_7$ls180.v:10166$12_ADDR[4:0]$2756 - attribute \src "ls180.v:10164.1-10168.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10166$12_DATA[9:0]$2757 - attribute \src "ls180.v:10164.1-10168.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10166$12_EN[9:0]$2758 - attribute \src "ls180.v:3206.1-3299.4" - wire width 3 $0\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:3363.1-3456.4" - wire width 3 $0\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:3520.1-3613.4" - wire width 3 $0\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:3677.1-3770.4" - wire width 3 $0\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:6500.1-6516.4" - wire $0\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:6721.1-6737.4" - wire $0\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:6738.1-6754.4" - wire $0\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:6806.1-6813.4" - wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:6814.1-6821.4" - wire $0\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:6822.1-6829.4" - wire $0\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:6830.1-6837.4" - wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:6838.1-6845.4" - wire $0\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:6846.1-6853.4" - wire $0\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:6854.1-6861.4" - wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:6862.1-6869.4" - wire $0\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:6517.1-6533.4" - wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:6870.1-6877.4" - wire $0\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:6878.1-6885.4" - wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:6886.1-6893.4" - wire $0\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:6894.1-6901.4" - wire $0\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:6902.1-6921.4" - wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:6922.1-6941.4" - wire width 32 $0\builder_comb_rhs_array_muxed25[31:0] - attribute \src "ls180.v:6942.1-6961.4" - wire width 4 $0\builder_comb_rhs_array_muxed26[3:0] - attribute \src "ls180.v:6962.1-6981.4" - wire $0\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:6982.1-7001.4" - wire $0\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:7002.1-7021.4" - wire $0\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:6534.1-6550.4" - wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:7022.1-7041.4" - wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:7042.1-7061.4" - wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:6551.1-6567.4" - wire $0\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:6568.1-6584.4" - wire $0\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:6585.1-6601.4" - wire $0\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:6653.1-6669.4" - wire $0\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:6670.1-6686.4" - wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:6687.1-6703.4" - wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:6704.1-6720.4" - wire $0\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:6602.1-6618.4" - wire $0\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:6619.1-6635.4" - wire $0\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:6636.1-6652.4" - wire $0\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:6755.1-6771.4" - wire $0\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:6772.1-6788.4" - wire $0\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:6789.1-6805.4" - wire $0\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:2770.1-2816.4" - wire $0\builder_converter0_next_state[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_converter0_state[0:0] - attribute \src "ls180.v:2830.1-2876.4" - wire $0\builder_converter1_next_state[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_converter1_state[0:0] - attribute \src "ls180.v:2890.1-2936.4" - wire $0\builder_converter2_next_state[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_converter2_state[0:0] - attribute \src "ls180.v:4023.1-4069.4" - wire $0\builder_converter_next_state[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_converter_state[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 20 $0\builder_count[19:0] - attribute \src "ls180.v:5740.1-5751.4" - wire $0\builder_error[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\builder_grant[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 14 $0\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:5629.1-5665.4" - wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:5629.1-5665.4" - wire $0\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:5629.1-5665.4" - wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:5629.1-5665.4" - wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_libresocsim_we[0:0] - attribute \src "ls180.v:5629.1-5665.4" - wire $0\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:5629.1-5665.4" - wire $0\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:5629.1-5665.4" - wire $0\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:5629.1-5665.4" - wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1857.5-1857.44" - wire $0\builder_libresocsim_wishbone_err[0:0] - attribute \src "ls180.v:1746.5-1746.27" - wire $0\builder_locked0[0:0] - attribute \src "ls180.v:1747.5-1747.27" - wire $0\builder_locked1[0:0] - attribute \src "ls180.v:1748.5-1748.27" - wire $0\builder_locked2[0:0] - attribute \src "ls180.v:1749.5-1749.27" - wire $0\builder_locked3[0:0] - attribute \src "ls180.v:3895.1-3967.4" - wire width 3 $0\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\builder_multiplexer_state[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:5629.1-5665.4" - wire width 2 $0\builder_next_state[1:0] - attribute \src "ls180.v:3112.1-3142.4" - wire width 2 $0\builder_refresher_next_state[1:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 2 $0\builder_refresher_state[1:0] - attribute \src "ls180.v:5380.1-5419.4" - wire width 2 $0\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 2 $0\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:4947.1-5026.4" - wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire width 3 $0\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:5439.1-5476.4" - wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:5477.1-5513.4" - wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:4622.1-4694.4" - wire width 3 $0\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:4467.1-4560.4" - wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:4357.1-4433.4" - wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:4594.1-4621.4" - wire $0\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:4728.1-4829.4" - wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:4323.1-4356.4" - wire $0\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:5740.1-5751.4" - wire $0\builder_shared_ack[0:0] - attribute \src "ls180.v:5740.1-5751.4" - wire width 32 $0\builder_shared_dat_r[31:0] - attribute \src "ls180.v:5690.1-5697.4" - wire width 5 $0\builder_slave_sel[4:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 5 $0\builder_slave_sel_r[4:0] - attribute \src "ls180.v:4213.1-4261.4" - wire width 2 $0\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 2 $0\builder_spimaster0_state[1:0] - attribute \src "ls180.v:5580.1-5628.4" - wire width 2 $0\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 2 $0\builder_spimaster1_state[1:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 2 $0\builder_state[1:0] - attribute \src "ls180.v:7181.1-7209.4" - wire $0\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:7210.1-7238.4" - wire $0\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:7062.1-7078.4" - wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:7079.1-7095.4" - wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:7096.1-7112.4" - wire $0\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:7113.1-7129.4" - wire $0\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:7130.1-7146.4" - wire $0\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:7147.1-7163.4" - wire $0\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:7164.1-7180.4" - wire $0\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\libresocsim_clk_divider1[15:0] - attribute \src "ls180.v:5580.1-5628.4" - wire $0\libresocsim_clk_enable[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\libresocsim_control_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\libresocsim_control_storage[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\libresocsim_count[2:0] - attribute \src "ls180.v:5580.1-5628.4" - wire width 3 $0\libresocsim_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:5580.1-5628.4" - wire $0\libresocsim_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:5580.1-5628.4" - wire $0\libresocsim_cs_enable[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\libresocsim_cs_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\libresocsim_cs_storage[0:0] - attribute \src "ls180.v:5580.1-5628.4" - wire $0\libresocsim_done0[0:0] - attribute \src "ls180.v:5580.1-5628.4" - wire $0\libresocsim_irq[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\libresocsim_loopback_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\libresocsim_loopback_storage[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\libresocsim_miso[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\libresocsim_miso_data[7:0] - attribute \src "ls180.v:5580.1-5628.4" - wire $0\libresocsim_miso_latch[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\libresocsim_mosi_data[7:0] - attribute \src "ls180.v:5580.1-5628.4" - wire $0\libresocsim_mosi_latch[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\libresocsim_mosi_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\libresocsim_mosi_sel[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\libresocsim_mosi_storage[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\libresocsim_re[0:0] - attribute \src "ls180.v:6311.1-6316.4" - wire $0\libresocsim_start1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\libresocsim_storage[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_cmd_consumed[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_converter_counter[0:0] - attribute \src "ls180.v:4023.1-4069.4" - wire $0\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:4023.1-4069.4" - wire $0\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_converter_dat_r[31:0] - attribute \src "ls180.v:4023.1-4069.4" - wire $0\main_converter_skip[0:0] - attribute \src "ls180.v:7339.1-7409.4" - wire width 16 $0\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 36 $0\main_dummy[35:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_gpio_oe_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_gpio_oe_storage[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_gpio_out_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_gpio_out_storage[15:0] - attribute \src "ls180.v:7296.1-7314.4" - wire width 16 $0\main_gpio_status[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_i2c_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_i2c_storage[2:0] - attribute \src "ls180.v:7335.1-7337.4" - wire $0\main_int_rst[0:0] - attribute \src "ls180.v:1496.11-1496.41" - wire width 2 $0\main_interface0_bus_bte[1:0] - attribute \src "ls180.v:1495.11-1495.41" - wire width 3 $0\main_interface0_bus_cti[2:0] - attribute \src "ls180.v:5439.1-5476.4" - wire width 32 $0\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1587.11-1587.41" - wire width 2 $0\main_interface1_bus_bte[1:0] - attribute \src "ls180.v:1586.11-1586.41" - wire width 3 $0\main_interface1_bus_cti[2:0] - attribute \src "ls180.v:5439.1-5476.4" - wire $0\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1579.12-1579.45" - wire width 32 $0\main_interface1_bus_dat_w[31:0] - attribute \src "ls180.v:5439.1-5476.4" - wire width 4 $0\main_interface1_bus_sel[3:0] - attribute \src "ls180.v:5439.1-5476.4" - wire $0\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:5439.1-5476.4" - wire $0\main_interface1_bus_we[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_libresocsim_converter0_counter[0:0] - attribute \src "ls180.v:2770.1-2816.4" - wire $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:2770.1-2816.4" - wire $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 64 $0\main_libresocsim_converter0_dat_r[63:0] - attribute \src "ls180.v:2770.1-2816.4" - wire $0\main_libresocsim_converter0_skip[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_libresocsim_converter1_counter[0:0] - attribute \src "ls180.v:2830.1-2876.4" - wire $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:2830.1-2876.4" - wire $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 64 $0\main_libresocsim_converter1_dat_r[63:0] - attribute \src "ls180.v:2830.1-2876.4" - wire $0\main_libresocsim_converter1_skip[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_libresocsim_converter2_counter[0:0] - attribute \src "ls180.v:2890.1-2936.4" - wire $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] - attribute \src "ls180.v:2890.1-2936.4" - wire $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 64 $0\main_libresocsim_converter2_dat_r[63:0] - attribute \src "ls180.v:2890.1-2936.4" - wire $0\main_libresocsim_converter2_skip[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:2770.1-2816.4" - wire width 30 $0\main_libresocsim_interface0_converted_interface_adr[29:0] - attribute \src "ls180.v:147.11-147.69" - wire width 2 $0\main_libresocsim_interface0_converted_interface_bte[1:0] - attribute \src "ls180.v:146.11-146.69" - wire width 3 $0\main_libresocsim_interface0_converted_interface_cti[2:0] - attribute \src "ls180.v:2770.1-2816.4" - wire $0\main_libresocsim_interface0_converted_interface_cyc[0:0] - attribute \src "ls180.v:2758.1-2768.4" - wire width 32 $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2770.1-2816.4" - wire width 4 $0\main_libresocsim_interface0_converted_interface_sel[3:0] - attribute \src "ls180.v:2770.1-2816.4" - wire $0\main_libresocsim_interface0_converted_interface_stb[0:0] - attribute \src "ls180.v:2770.1-2816.4" - wire $0\main_libresocsim_interface0_converted_interface_we[0:0] - attribute \src "ls180.v:2830.1-2876.4" - wire width 30 $0\main_libresocsim_interface1_converted_interface_adr[29:0] - attribute \src "ls180.v:162.11-162.69" - wire width 2 $0\main_libresocsim_interface1_converted_interface_bte[1:0] - attribute \src "ls180.v:161.11-161.69" - wire width 3 $0\main_libresocsim_interface1_converted_interface_cti[2:0] - attribute \src "ls180.v:2830.1-2876.4" - wire $0\main_libresocsim_interface1_converted_interface_cyc[0:0] - attribute \src "ls180.v:2818.1-2828.4" - wire width 32 $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2830.1-2876.4" - wire width 4 $0\main_libresocsim_interface1_converted_interface_sel[3:0] - attribute \src "ls180.v:2830.1-2876.4" - wire $0\main_libresocsim_interface1_converted_interface_stb[0:0] - attribute \src "ls180.v:2830.1-2876.4" - wire $0\main_libresocsim_interface1_converted_interface_we[0:0] - attribute \src "ls180.v:2890.1-2936.4" - wire width 30 $0\main_libresocsim_interface2_converted_interface_adr[29:0] - attribute \src "ls180.v:177.11-177.69" - wire width 2 $0\main_libresocsim_interface2_converted_interface_bte[1:0] - attribute \src "ls180.v:176.11-176.69" - wire width 3 $0\main_libresocsim_interface2_converted_interface_cti[2:0] - attribute \src "ls180.v:2890.1-2936.4" - wire $0\main_libresocsim_interface2_converted_interface_cyc[0:0] - attribute \src "ls180.v:2878.1-2888.4" - wire width 32 $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2890.1-2936.4" - wire width 4 $0\main_libresocsim_interface2_converted_interface_sel[3:0] - attribute \src "ls180.v:2890.1-2936.4" - wire $0\main_libresocsim_interface2_converted_interface_stb[0:0] - attribute \src "ls180.v:2890.1-2936.4" - wire $0\main_libresocsim_interface2_converted_interface_we[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] - attribute \src "ls180.v:2830.1-2876.4" - wire $0\main_libresocsim_libresoc_dbus_ack[0:0] - attribute \src "ls180.v:76.5-76.46" - wire $0\main_libresocsim_libresoc_dbus_err[0:0] - attribute \src "ls180.v:2770.1-2816.4" - wire $0\main_libresocsim_libresoc_ibus_ack[0:0] - attribute \src "ls180.v:87.5-87.46" - wire $0\main_libresocsim_libresoc_ibus_err[0:0] - attribute \src "ls180.v:2751.1-2756.4" - wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:2890.1-2936.4" - wire $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] - attribute \src "ls180.v:118.5-118.49" - wire $0\main_libresocsim_libresoc_jtag_wb_err[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:193.5-193.40" - wire $0\main_libresocsim_ram_bus_err[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_libresocsim_reload_storage[31:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_libresocsim_reset_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_libresocsim_reset_storage[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_libresocsim_scratch_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_libresocsim_value[31:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:2939.1-2945.4" - wire width 4 $0\main_libresocsim_we[3:0] - attribute \src "ls180.v:2951.1-2956.4" - wire $0\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:4023.1-4069.4" - wire width 30 $0\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:4023.1-4069.4" - wire $0\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:4011.1-4021.4" - wire width 16 $0\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:4023.1-4069.4" - wire width 2 $0\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:4023.1-4069.4" - wire $0\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:4023.1-4069.4" - wire $0\main_litedram_wb_we[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_pwm0_counter[31:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_pwm0_period_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_pwm0_width_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_pwm1_counter[31:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_pwm1_period_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_pwm1_width_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_rddata_en[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 2 $0\main_sdblock2mem_converter_demux[1:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_sdblock2mem_converter_source_payload_data[31:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 5 $0\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 6 $0\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 5 $0\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1520.5-1520.41" - wire $0\main_sdblock2mem_fifo_replace[0:0] - attribute \src "ls180.v:5347.1-5354.4" - wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:5380.1-5419.4" - wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:5380.1-5419.4" - wire width 32 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] - attribute \src "ls180.v:5380.1-5419.4" - wire $0\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:5380.1-5419.4" - wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:5380.1-5419.4" - wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:5380.1-5419.4" - wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:5380.1-5419.4" - wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 10 $0\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:5129.1-5319.4" - wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 128 $0\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:5129.1-5319.4" - wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1329.5-1329.34" - wire $0\main_sdcore_cmd_send_w[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:5035.1-5042.4" - wire $0\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:5091.1-5098.4" - wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:5045.1-5052.4" - wire $0\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:5101.1-5108.4" - wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:5055.1-5062.4" - wire $0\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:5111.1-5118.4" - wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:5065.1-5072.4" - wire $0\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:5121.1-5128.4" - wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:5080.1-5087.4" - wire $0\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1435.5-1435.50" - wire $0\main_sdcore_crc16_checker_source_first[0:0] - attribute \src "ls180.v:5074.1-5079.4" - wire $0\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:5027.1-5032.4" - wire $0\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:4947.1-5026.4" - wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:4947.1-5026.4" - wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:4909.1-4916.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:4919.1-4926.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:4929.1-4936.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:4939.1-4946.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:4947.1-5026.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:4947.1-5026.4" - wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:4947.1-5026.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:4947.1-5026.4" - wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:4947.1-5026.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:4947.1-5026.4" - wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:4947.1-5026.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:4947.1-5026.4" - wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:4947.1-5026.4" - wire $0\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1392.5-1392.51" - wire $0\main_sdcore_crc16_inserter_source_first[0:0] - attribute \src "ls180.v:4947.1-5026.4" - wire $0\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:4947.1-5026.4" - wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:4947.1-5026.4" - wire $0\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:4887.1-4894.4" - wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_sdcore_data_count[31:0] - attribute \src "ls180.v:5129.1-5319.4" - wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdcore_data_done[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdcore_data_error[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 2 $0\main_sdmem2block_converter_mux[1:0] - attribute \src "ls180.v:5525.1-5541.4" - wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 64 $0\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_sdmem2block_dma_data[31:0] - attribute \src "ls180.v:5439.1-5476.4" - wire width 32 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - attribute \src "ls180.v:5439.1-5476.4" - wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:5477.1-5513.4" - wire $0\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:5477.1-5513.4" - wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:5477.1-5513.4" - wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:5477.1-5513.4" - wire $0\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:5477.1-5513.4" - wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:5439.1-5476.4" - wire $0\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:5477.1-5513.4" - wire $0\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1600.5-1600.45" - wire $0\main_sdmem2block_dma_source_first[0:0] - attribute \src "ls180.v:5439.1-5476.4" - wire $0\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:5439.1-5476.4" - wire width 32 $0\main_sdmem2block_dma_source_payload_data[31:0] - attribute \src "ls180.v:5439.1-5476.4" - wire $0\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 5 $0\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 6 $0\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 5 $0\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1656.5-1656.41" - wire $0\main_sdmem2block_fifo_replace[0:0] - attribute \src "ls180.v:5555.1-5562.4" - wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:4293.1-4321.4" - wire $0\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 9 $0\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 9 $0\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1121.5-1121.53" - wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] - attribute \src "ls180.v:1122.5-1122.52" - wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1102.5-1102.46" - wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:4467.1-4560.4" - wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:4467.1-4560.4" - wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:4467.1-4560.4" - wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:4467.1-4560.4" - wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:4467.1-4560.4" - wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1075.5-1075.49" - wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1076.5-1076.48" - wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1077.5-1077.55" - wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1079.5-1079.57" - wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1080.5-1080.58" - wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1082.11-1082.64" - wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1083.5-1083.59" - wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4467.1-4560.4" - wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4467.1-4560.4" - wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4467.1-4560.4" - wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1088.11-1088.57" - wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1089.5-1089.52" - wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:4467.1-4560.4" - wire $0\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:4467.1-4560.4" - wire $0\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:4467.1-4560.4" - wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:4467.1-4560.4" - wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:4467.1-4560.4" - wire $0\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:4467.1-4560.4" - wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:4467.1-4560.4" - wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:4357.1-4433.4" - wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:4357.1-4433.4" - wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:4357.1-4433.4" - wire $0\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:4357.1-4433.4" - wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4357.1-4433.4" - wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4357.1-4433.4" - wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1065.11-1065.57" - wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1066.5-1066.52" - wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:4357.1-4433.4" - wire $0\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 10 $0\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:4728.1-4829.4" - wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:4728.1-4829.4" - wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1277.5-1277.55" - wire $0\main_sdphy_datar_datar_converter_sink_first[0:0] - attribute \src "ls180.v:1278.5-1278.54" - wire $0\main_sdphy_datar_datar_converter_sink_last[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1258.5-1258.48" - wire $0\main_sdphy_datar_datar_pads_in_ready[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:4728.1-4829.4" - wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:4728.1-4829.4" - wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:4728.1-4829.4" - wire $0\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1229.5-1229.50" - wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1230.5-1230.49" - wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1231.5-1231.56" - wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1233.5-1233.58" - wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1234.5-1234.59" - wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1236.11-1236.65" - wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1237.5-1237.60" - wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4728.1-4829.4" - wire $0\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1240.5-1240.51" - wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1241.5-1241.52" - wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1242.11-1242.58" - wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1243.5-1243.53" - wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:4728.1-4829.4" - wire $0\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1250.5-1250.41" - wire $0\main_sdphy_datar_source_first[0:0] - attribute \src "ls180.v:4728.1-4829.4" - wire $0\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:4728.1-4829.4" - wire width 8 $0\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:4728.1-4829.4" - wire width 3 $0\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:4728.1-4829.4" - wire $0\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:4728.1-4829.4" - wire $0\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:4728.1-4829.4" - wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:4728.1-4829.4" - wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:4622.1-4694.4" - wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:4622.1-4694.4" - wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1199.5-1199.54" - wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] - attribute \src "ls180.v:1200.5-1200.53" - wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1180.5-1180.47" - wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:4594.1-4621.4" - wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:4594.1-4621.4" - wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:4594.1-4621.4" - wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:4594.1-4621.4" - wire $0\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1167.5-1167.50" - wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1168.5-1168.49" - wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1169.5-1169.56" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1170.5-1170.58" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] - attribute \src "ls180.v:1171.5-1171.58" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1172.5-1172.59" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1173.11-1173.65" - wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] - attribute \src "ls180.v:1174.11-1174.65" - wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1175.5-1175.60" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:1165.5-1165.50" - wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] - attribute \src "ls180.v:4622.1-4694.4" - wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1154.5-1154.51" - wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1155.5-1155.52" - wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4622.1-4694.4" - wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4622.1-4694.4" - wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:4622.1-4694.4" - wire $0\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:5129.1-5319.4" - wire $0\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:4622.1-4694.4" - wire $0\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:4622.1-4694.4" - wire $0\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:4594.1-4621.4" - wire $0\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\main_sdphy_init_count[7:0] - attribute \src "ls180.v:4323.1-4356.4" - wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:4323.1-4356.4" - wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1047.5-1047.40" - wire $0\main_sdphy_init_initialize_w[0:0] - attribute \src "ls180.v:4323.1-4356.4" - wire $0\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4323.1-4356.4" - wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4323.1-4356.4" - wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4323.1-4356.4" - wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4323.1-4356.4" - wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:7339.1-7409.4" - wire $0\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:7339.1-7409.4" - wire width 4 $0\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_address_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 13 $0\main_sdram_address_storage[12:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 2 $0\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:3168.1-3175.4" - wire $0\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:425.5-425.64" - wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:408.5-408.67" - wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:409.5-409.66" - wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3190.1-3197.4" - wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3157.1-3164.4" - wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:3206.1-3299.4" - wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:3206.1-3299.4" - wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3206.1-3299.4" - wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3206.1-3299.4" - wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3206.1-3299.4" - wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:3206.1-3299.4" - wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:3855.1-3863.4" - wire $0\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:3206.1-3299.4" - wire $0\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:3206.1-3299.4" - wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:3206.1-3299.4" - wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:3206.1-3299.4" - wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 13 $0\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:3206.1-3299.4" - wire $0\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:3206.1-3299.4" - wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3206.1-3299.4" - wire $0\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:467.32-467.76" - wire $0\main_sdram_bankmachine0_trascon_ready[0:0] - attribute \src "ls180.v:465.32-465.75" - wire $0\main_sdram_bankmachine0_trccon_ready[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:3325.1-3332.4" - wire $0\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:507.5-507.64" - wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:490.5-490.67" - wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:491.5-491.66" - wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3347.1-3354.4" - wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3314.1-3321.4" - wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:3363.1-3456.4" - wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:3363.1-3456.4" - wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3363.1-3456.4" - wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3363.1-3456.4" - wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3363.1-3456.4" - wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:3363.1-3456.4" - wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:3864.1-3872.4" - wire $0\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:3363.1-3456.4" - wire $0\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:3363.1-3456.4" - wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:3363.1-3456.4" - wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:3363.1-3456.4" - wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 13 $0\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:3363.1-3456.4" - wire $0\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:3363.1-3456.4" - wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3363.1-3456.4" - wire $0\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:549.32-549.76" - wire $0\main_sdram_bankmachine1_trascon_ready[0:0] - attribute \src "ls180.v:547.32-547.75" - wire $0\main_sdram_bankmachine1_trccon_ready[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:3482.1-3489.4" - wire $0\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:589.5-589.64" - wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:572.5-572.67" - wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:573.5-573.66" - wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3504.1-3511.4" - wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3471.1-3478.4" - wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:3520.1-3613.4" - wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:3520.1-3613.4" - wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3520.1-3613.4" - wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3520.1-3613.4" - wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3520.1-3613.4" - wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:3520.1-3613.4" - wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:3873.1-3881.4" - wire $0\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:3520.1-3613.4" - wire $0\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:3520.1-3613.4" - wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:3520.1-3613.4" - wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:3520.1-3613.4" - wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 13 $0\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:3520.1-3613.4" - wire $0\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:3520.1-3613.4" - wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3520.1-3613.4" - wire $0\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:631.32-631.76" - wire $0\main_sdram_bankmachine2_trascon_ready[0:0] - attribute \src "ls180.v:629.32-629.75" - wire $0\main_sdram_bankmachine2_trccon_ready[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:3639.1-3646.4" - wire $0\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:671.5-671.64" - wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:654.5-654.67" - wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:655.5-655.66" - wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3661.1-3668.4" - wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3628.1-3635.4" - wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:3677.1-3770.4" - wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:3677.1-3770.4" - wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3677.1-3770.4" - wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3677.1-3770.4" - wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3677.1-3770.4" - wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:3677.1-3770.4" - wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:3882.1-3890.4" - wire $0\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:3677.1-3770.4" - wire $0\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:3677.1-3770.4" - wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:3677.1-3770.4" - wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:3677.1-3770.4" - wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 13 $0\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:3677.1-3770.4" - wire $0\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:3677.1-3770.4" - wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3677.1-3770.4" - wire $0\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:713.32-713.76" - wire $0\main_sdram_bankmachine3_trascon_ready[0:0] - attribute \src "ls180.v:711.32-711.75" - wire $0\main_sdram_bankmachine3_trccon_ready[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:3804.1-3809.4" - wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:3810.1-3815.4" - wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:3816.1-3821.4" - wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:721.5-721.43" - wire $0\main_sdram_choose_cmd_cmd_ready[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 2 $0\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:3790.1-3796.4" - wire width 4 $0\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:719.5-719.48" - wire $0\main_sdram_choose_cmd_want_activates[0:0] - attribute \src "ls180.v:718.5-718.43" - wire $0\main_sdram_choose_cmd_want_cmds[0:0] - attribute \src "ls180.v:716.5-716.44" - wire $0\main_sdram_choose_cmd_want_reads[0:0] - attribute \src "ls180.v:717.5-717.45" - wire $0\main_sdram_choose_cmd_want_writes[0:0] - attribute \src "ls180.v:3837.1-3842.4" - wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:3843.1-3848.4" - wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:3849.1-3854.4" - wire $0\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:3895.1-3967.4" - wire $0\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 2 $0\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:3823.1-3829.4" - wire width 4 $0\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:3895.1-3967.4" - wire $0\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:3895.1-3967.4" - wire $0\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:3895.1-3967.4" - wire $0\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:3112.1-3142.4" - wire $0\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 13 $0\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 2 $0\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:369.5-369.42" - wire $0\main_sdram_cmd_payload_is_read[0:0] - attribute \src "ls180.v:370.5-370.43" - wire $0\main_sdram_cmd_payload_is_write[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:3895.1-3967.4" - wire $0\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:3112.1-3142.4" - wire $0\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:305.5-305.38" - wire $0\main_sdram_command_issue_w[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_command_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 6 $0\main_sdram_command_storage[5:0] - attribute \src "ls180.v:354.5-354.35" - wire $0\main_sdram_dfi_p0_act_n[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 13 $0\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 2 $0\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:3895.1-3967.4" - wire $0\main_sdram_en0[0:0] - attribute \src "ls180.v:3895.1-3967.4" - wire $0\main_sdram_en1[0:0] - attribute \src "ls180.v:3991.1-4004.4" - wire width 16 $0\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:3991.1-4004.4" - wire width 2 $0\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:255.5-255.36" - wire $0\main_sdram_inti_p0_act_n[0:0] - attribute \src "ls180.v:3053.1-3069.4" - wire $0\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:3053.1-3069.4" - wire $0\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:3053.1-3069.4" - wire $0\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:2995.1-3049.4" - wire width 16 $0\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:2995.1-3049.4" - wire $0\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:3053.1-3069.4" - wire $0\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:2995.1-3049.4" - wire $0\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:2995.1-3049.4" - wire width 13 $0\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:2995.1-3049.4" - wire width 2 $0\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:2995.1-3049.4" - wire $0\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:2995.1-3049.4" - wire $0\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:2995.1-3049.4" - wire $0\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:2995.1-3049.4" - wire $0\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:2995.1-3049.4" - wire $0\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:2995.1-3049.4" - wire $0\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:2995.1-3049.4" - wire $0\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:2995.1-3049.4" - wire $0\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:2995.1-3049.4" - wire width 16 $0\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:2995.1-3049.4" - wire $0\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:2995.1-3049.4" - wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:752.12-752.36" - wire width 13 $0\main_sdram_nop_a[12:0] - attribute \src "ls180.v:753.11-753.35" - wire width 2 $0\main_sdram_nop_ba[1:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 4 $0\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:3112.1-3142.4" - wire $0\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:2995.1-3049.4" - wire width 16 $0\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:2995.1-3049.4" - wire $0\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdram_status[15:0] - attribute \src "ls180.v:755.5-755.31" - wire $0\main_sdram_steerer0[0:0] - attribute \src "ls180.v:756.5-756.31" - wire $0\main_sdram_steerer1[0:0] - attribute \src "ls180.v:3895.1-3967.4" - wire width 2 $0\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 4 $0\main_sdram_storage[3:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:760.32-760.63" - wire $0\main_sdram_tfawcon_ready[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 5 $0\main_sdram_time0[4:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 4 $0\main_sdram_time1[3:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 10 $0\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:758.32-758.63" - wire $0\main_sdram_trrdcon_ready[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:976.12-976.48" - wire width 16 $0\main_spi_master_clk_divider0[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_spi_master_clk_divider1[15:0] - attribute \src "ls180.v:4213.1-4261.4" - wire $0\main_spi_master_clk_enable[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_spi_master_control_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 16 $0\main_spi_master_control_storage[15:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_spi_master_count[2:0] - attribute \src "ls180.v:4213.1-4261.4" - wire width 3 $0\main_spi_master_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:4213.1-4261.4" - wire $0\main_spi_master_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:4213.1-4261.4" - wire $0\main_spi_master_cs_enable[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_spi_master_cs_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_spi_master_cs_storage[0:0] - attribute \src "ls180.v:4213.1-4261.4" - wire $0\main_spi_master_done0[0:0] - attribute \src "ls180.v:4213.1-4261.4" - wire $0\main_spi_master_irq[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_spi_master_loopback_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_spi_master_loopback_storage[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\main_spi_master_miso[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\main_spi_master_miso_data[7:0] - attribute \src "ls180.v:4213.1-4261.4" - wire $0\main_spi_master_miso_latch[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\main_spi_master_mosi_data[7:0] - attribute \src "ls180.v:4213.1-4261.4" - wire $0\main_spi_master_mosi_latch[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_spi_master_mosi_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 3 $0\main_spi_master_mosi_sel[2:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\main_spi_master_mosi_storage[7:0] - attribute \src "ls180.v:6265.1-6270.4" - wire $0\main_spi_master_start1[0:0] - attribute \src "ls180.v:4131.1-4135.4" - wire width 2 $0\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:4120.1-4124.4" - wire width 2 $0\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 2 $0\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_uart_phy_re[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 4 $0\main_uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_uart_phy_rx_busy[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_uart_phy_rx_r[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\main_uart_phy_rx_reg[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_uart_phy_sink_ready[0:0] - attribute \src "ls180.v:831.5-831.38" - wire $0\main_uart_phy_source_first[0:0] - attribute \src "ls180.v:832.5-832.37" - wire $0\main_uart_phy_source_last[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\main_uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_uart_phy_source_valid[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 32 $0\main_uart_phy_storage[31:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 4 $0\main_uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_uart_phy_tx_busy[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 8 $0\main_uart_phy_tx_reg[7:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:958.5-958.27" - wire $0\main_uart_reset[0:0] - attribute \src "ls180.v:4125.1-4130.4" - wire $0\main_uart_rx_clear[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 4 $0\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 5 $0\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 4 $0\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:940.5-940.37" - wire $0\main_uart_rx_fifo_replace[0:0] - attribute \src "ls180.v:4183.1-4190.4" - wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_uart_rx_pending[0:0] - attribute \src "ls180.v:4114.1-4119.4" - wire $0\main_uart_tx_clear[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 4 $0\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 5 $0\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:7411.1-10036.4" - wire width 4 $0\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:903.5-903.37" - wire $0\main_uart_tx_fifo_replace[0:0] - attribute \src "ls180.v:886.5-886.40" - wire $0\main_uart_tx_fifo_sink_first[0:0] - attribute \src "ls180.v:887.5-887.39" - wire $0\main_uart_tx_fifo_sink_last[0:0] - attribute \src "ls180.v:4153.1-4160.4" - wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_uart_tx_pending[0:0] - attribute \src "ls180.v:4023.1-4069.4" - wire $0\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:799.5-799.29" - wire $0\main_wb_sdram_err[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\main_wdata_consumed[0:0] - attribute \src "ls180.v:10040.1-10050.4" - wire width 7 $0\memadr[6:0] - attribute \src "ls180.v:10060.1-10064.4" - wire width 25 $0\memdat[24:0] - attribute \src "ls180.v:10074.1-10078.4" - wire width 25 $0\memdat_1[24:0] - attribute \src "ls180.v:10088.1-10092.4" - wire width 25 $0\memdat_2[24:0] - attribute \src "ls180.v:10102.1-10106.4" - wire width 25 $0\memdat_3[24:0] - attribute \src "ls180.v:10117.1-10121.4" - wire width 10 $0\memdat_4[9:0] - attribute \src "ls180.v:10123.1-10126.4" - wire width 10 $0\memdat_5[9:0] - attribute \src "ls180.v:10134.1-10138.4" - wire width 10 $0\memdat_6[9:0] - attribute \src "ls180.v:10140.1-10143.4" - wire width 10 $0\memdat_7[9:0] - attribute \src "ls180.v:10150.1-10154.4" - wire width 10 $0\memdat_8[9:0] - attribute \src "ls180.v:10164.1-10168.4" - wire width 10 $0\memdat_9[9:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\pwm0[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\pwm1[0:0] - attribute \src "ls180.v:7339.1-7409.4" - wire $0\sdcard_clk[0:0] - attribute \src "ls180.v:7339.1-7409.4" - wire $0\sdcard_cmd_o[0:0] - attribute \src "ls180.v:7339.1-7409.4" - wire $0\sdcard_cmd_oe[0:0] - attribute \src "ls180.v:7339.1-7409.4" - wire width 4 $0\sdcard_data_o[3:0] - attribute \src "ls180.v:7339.1-7409.4" - wire $0\sdcard_data_oe[0:0] - attribute \src "ls180.v:7339.1-7409.4" - wire width 13 $0\sdram_a[12:0] - attribute \src "ls180.v:7339.1-7409.4" - wire width 2 $0\sdram_ba[1:0] - attribute \src "ls180.v:7339.1-7409.4" - wire $0\sdram_cas_n[0:0] - attribute \src "ls180.v:7339.1-7409.4" - wire $0\sdram_cke[0:0] - attribute \src "ls180.v:7339.1-7409.4" - wire $0\sdram_clock[0:0] - attribute \src "ls180.v:7339.1-7409.4" - wire $0\sdram_cs_n[0:0] - attribute \src "ls180.v:7339.1-7409.4" - wire width 2 $0\sdram_dm[1:0] - attribute \src "ls180.v:7339.1-7409.4" - wire width 16 $0\sdram_dq_o[15:0] - attribute \src "ls180.v:7339.1-7409.4" - wire $0\sdram_dq_oe[0:0] - attribute \src "ls180.v:7339.1-7409.4" - wire $0\sdram_ras_n[0:0] - attribute \src "ls180.v:7339.1-7409.4" - wire $0\sdram_we_n[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\spi_master_clk[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\spi_master_cs_n[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\spi_master_mosi[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\spisdcard_clk[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\spisdcard_cs_n[0:0] - attribute \src "ls180.v:7411.1-10036.4" - wire $0\spisdcard_mosi[0:0] - attribute \src "ls180.v:1725.11-1725.49" - wire width 3 $1\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:1724.11-1724.44" - wire width 3 $1\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:1727.11-1727.49" - wire width 3 $1\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:1726.11-1726.44" - wire width 3 $1\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:1729.11-1729.49" - wire width 3 $1\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:1728.11-1728.44" - wire width 3 $1\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:1731.11-1731.49" - wire width 3 $1\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:1730.11-1730.44" - wire width 3 $1\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:2576.5-2576.41" - wire $1\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:2589.5-2589.42" - wire $1\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:2590.5-2590.42" - wire $1\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:2594.12-2594.50" - wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:2595.5-2595.42" - wire $1\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:2596.5-2596.42" - wire $1\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:2597.12-2597.50" - wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:2598.5-2598.42" - wire $1\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:2599.5-2599.42" - wire $1\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:2600.12-2600.50" - wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:2601.5-2601.42" - wire $1\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:2577.12-2577.49" - wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2602.5-2602.42" - wire $1\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:2603.12-2603.50" - wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:2604.5-2604.42" - wire $1\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:2605.5-2605.42" - wire $1\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:2606.12-2606.50" - wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:2607.12-2607.50" - wire width 32 $1\builder_comb_rhs_array_muxed25[31:0] - attribute \src "ls180.v:2608.11-2608.48" - wire width 4 $1\builder_comb_rhs_array_muxed26[3:0] - attribute \src "ls180.v:2609.5-2609.42" - wire $1\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:2610.5-2610.42" - wire $1\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:2611.5-2611.42" - wire $1\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:2578.11-2578.47" - wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:2612.11-2612.48" - wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:2613.11-2613.48" - wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:2579.5-2579.41" - wire $1\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2580.5-2580.41" - wire $1\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2581.5-2581.41" - wire $1\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2585.5-2585.41" - wire $1\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:2586.12-2586.49" - wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:2587.11-2587.47" - wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:2588.5-2588.41" - wire $1\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:2582.5-2582.39" - wire $1\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:2583.5-2583.39" - wire $1\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:2584.5-2584.39" - wire $1\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:2591.5-2591.39" - wire $1\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:2592.5-2592.39" - wire $1\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:2593.5-2593.39" - wire $1\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:1711.5-1711.41" - wire $1\builder_converter0_next_state[0:0] - attribute \src "ls180.v:1710.5-1710.36" - wire $1\builder_converter0_state[0:0] - attribute \src "ls180.v:1715.5-1715.41" - wire $1\builder_converter1_next_state[0:0] - attribute \src "ls180.v:1714.5-1714.36" - wire $1\builder_converter1_state[0:0] - attribute \src "ls180.v:1719.5-1719.41" - wire $1\builder_converter2_next_state[0:0] - attribute \src "ls180.v:1718.5-1718.36" - wire $1\builder_converter2_state[0:0] - attribute \src "ls180.v:1756.5-1756.40" - wire $1\builder_converter_next_state[0:0] - attribute \src "ls180.v:1755.5-1755.35" - wire $1\builder_converter_state[0:0] - attribute \src "ls180.v:1876.12-1876.39" - wire width 20 $1\builder_count[19:0] - attribute \src "ls180.v:1873.5-1873.25" - wire $1\builder_error[0:0] - attribute \src "ls180.v:1870.11-1870.31" - wire width 3 $1\builder_grant[2:0] - attribute \src "ls180.v:1880.11-1880.51" - wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2382.11-2382.52" - wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2415.11-2415.52" - wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2456.11-2456.52" - wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2521.11-2521.52" - wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2546.11-2546.52" - wire width 8 $1\builder_interface14_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1921.11-1921.51" - wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1950.11-1950.51" - wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1963.11-1963.51" - wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2004.11-2004.51" - wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2045.11-2045.51" - wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2110.11-2110.51" - wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2243.11-2243.51" - wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2324.11-2324.51" - wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2341.11-2341.51" - wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1843.12-1843.43" - wire width 14 $1\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:2572.12-2572.55" - wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:2573.5-2573.50" - wire $1\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:1845.11-1845.43" - wire width 8 $1\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:2570.11-2570.55" - wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:2571.5-2571.52" - wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:1844.5-1844.34" - wire $1\builder_libresocsim_we[0:0] - attribute \src "ls180.v:2574.5-2574.46" - wire $1\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:2575.5-2575.49" - wire $1\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:1853.5-1853.44" - wire $1\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:1849.12-1849.54" - wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1733.11-1733.48" - wire width 3 $1\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:1732.11-1732.43" - wire width 3 $1\builder_multiplexer_state[2:0] - attribute \src "ls180.v:2679.32-2679.66" - wire $1\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:2680.32-2680.66" - wire $1\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:2699.32-2699.67" - wire $1\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:2700.32-2700.67" - wire $1\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:2701.32-2701.67" - wire $1\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:2702.32-2702.67" - wire $1\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:2703.32-2703.67" - wire $1\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:2704.32-2704.67" - wire $1\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:2705.32-2705.67" - wire $1\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:2706.32-2706.67" - wire $1\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:2707.32-2707.67" - wire $1\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:2708.32-2708.67" - wire $1\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:2709.32-2709.67" - wire $1\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:2710.32-2710.67" - wire $1\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:2711.32-2711.67" - wire $1\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:2712.32-2712.67" - wire $1\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:2681.32-2681.66" - wire $1\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:2682.32-2682.66" - wire $1\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:2683.32-2683.66" - wire $1\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:2684.32-2684.66" - wire $1\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:2685.32-2685.66" - wire $1\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:2686.32-2686.66" - wire $1\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:2687.32-2687.66" - wire $1\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:2688.32-2688.66" - wire $1\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:2689.32-2689.66" - wire $1\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:2690.32-2690.66" - wire $1\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:2691.32-2691.66" - wire $1\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:2692.32-2692.66" - wire $1\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:2693.32-2693.66" - wire $1\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:2694.32-2694.66" - wire $1\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:2695.32-2695.66" - wire $1\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:2696.32-2696.66" - wire $1\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:2697.32-2697.66" - wire $1\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:2698.32-2698.66" - wire $1\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:1751.5-1751.43" - wire $1\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:1752.5-1752.43" - wire $1\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:1753.5-1753.43" - wire $1\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:1754.5-1754.43" - wire $1\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:1750.5-1750.42" - wire $1\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:2569.11-2569.36" - wire width 2 $1\builder_next_state[1:0] - attribute \src "ls180.v:1723.11-1723.46" - wire width 2 $1\builder_refresher_next_state[1:0] - attribute \src "ls180.v:1722.11-1722.41" - wire width 2 $1\builder_refresher_state[1:0] - attribute \src "ls180.v:1828.11-1828.51" - wire width 2 $1\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:1827.11-1827.46" - wire width 2 $1\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:1796.5-1796.57" - wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:1795.5-1795.52" - wire $1\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:1808.11-1808.47" - wire width 3 $1\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:1807.11-1807.42" - wire width 3 $1\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:1832.5-1832.49" - wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:1831.5-1831.44" - wire $1\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:1836.11-1836.65" - wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:1835.11-1835.60" - wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:1784.11-1784.46" - wire width 3 $1\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:1783.11-1783.41" - wire width 3 $1\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:1772.11-1772.52" - wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:1771.11-1771.47" - wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:1768.11-1768.52" - wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:1767.11-1767.47" - wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:1780.5-1780.46" - wire $1\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:1779.5-1779.41" - wire $1\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:1788.11-1788.53" - wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:1787.11-1787.48" - wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:1764.5-1764.46" - wire $1\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:1763.5-1763.41" - wire $1\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:1864.5-1864.30" - wire $1\builder_shared_ack[0:0] - attribute \src "ls180.v:1860.12-1860.40" - wire width 32 $1\builder_shared_dat_r[31:0] - attribute \src "ls180.v:1871.11-1871.35" - wire width 5 $1\builder_slave_sel[4:0] - attribute \src "ls180.v:1872.11-1872.37" - wire width 5 $1\builder_slave_sel_r[4:0] - attribute \src "ls180.v:1760.11-1760.47" - wire width 2 $1\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:1759.11-1759.42" - wire width 2 $1\builder_spimaster0_state[1:0] - attribute \src "ls180.v:1840.11-1840.47" - wire width 2 $1\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:1839.11-1839.42" - wire width 2 $1\builder_spimaster1_state[1:0] - attribute \src "ls180.v:2568.11-2568.31" - wire width 2 $1\builder_state[1:0] - attribute \src "ls180.v:2621.5-2621.39" - wire $1\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:2622.5-2622.39" - wire $1\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:2614.11-2614.47" - wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:2615.12-2615.49" - wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2616.5-2616.41" - wire $1\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:2617.5-2617.41" - wire $1\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2618.5-2618.41" - wire $1\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2619.5-2619.41" - wire $1\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2620.5-2620.41" - wire $1\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:1702.12-1702.44" - wire width 16 $1\libresocsim_clk_divider1[15:0] - attribute \src "ls180.v:1697.5-1697.34" - wire $1\libresocsim_clk_enable[0:0] - attribute \src "ls180.v:1684.5-1684.34" - wire $1\libresocsim_control_re[0:0] - attribute \src "ls180.v:1683.12-1683.47" - wire width 16 $1\libresocsim_control_storage[15:0] - attribute \src "ls180.v:1699.11-1699.35" - wire width 3 $1\libresocsim_count[2:0] - attribute \src "ls180.v:1841.11-1841.57" - wire width 3 $1\libresocsim_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:1842.5-1842.54" - wire $1\libresocsim_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:1698.5-1698.33" - wire $1\libresocsim_cs_enable[0:0] - attribute \src "ls180.v:1694.5-1694.29" - wire $1\libresocsim_cs_re[0:0] - attribute \src "ls180.v:1693.5-1693.34" - wire $1\libresocsim_cs_storage[0:0] - attribute \src "ls180.v:1674.5-1674.29" - wire $1\libresocsim_done0[0:0] - attribute \src "ls180.v:1675.5-1675.27" - wire $1\libresocsim_irq[0:0] - attribute \src "ls180.v:1696.5-1696.35" - wire $1\libresocsim_loopback_re[0:0] - attribute \src "ls180.v:1695.5-1695.40" - wire $1\libresocsim_loopback_storage[0:0] - attribute \src "ls180.v:1677.11-1677.34" - wire width 8 $1\libresocsim_miso[7:0] - attribute \src "ls180.v:1707.11-1707.39" - wire width 8 $1\libresocsim_miso_data[7:0] - attribute \src "ls180.v:1701.5-1701.34" - wire $1\libresocsim_miso_latch[0:0] - attribute \src "ls180.v:1705.11-1705.39" - wire width 8 $1\libresocsim_mosi_data[7:0] - attribute \src "ls180.v:1700.5-1700.34" - wire $1\libresocsim_mosi_latch[0:0] - attribute \src "ls180.v:1689.5-1689.31" - wire $1\libresocsim_mosi_re[0:0] - attribute \src "ls180.v:1706.11-1706.38" - wire width 3 $1\libresocsim_mosi_sel[2:0] - attribute \src "ls180.v:1688.11-1688.42" - wire width 8 $1\libresocsim_mosi_storage[7:0] - attribute \src "ls180.v:1709.5-1709.26" - wire $1\libresocsim_re[0:0] - attribute \src "ls180.v:1681.5-1681.30" - wire $1\libresocsim_start1[0:0] - attribute \src "ls180.v:1708.12-1708.41" - wire width 16 $1\libresocsim_storage[15:0] - attribute \src "ls180.v:812.5-812.29" - wire $1\main_cmd_consumed[0:0] - attribute \src "ls180.v:809.5-809.34" - wire $1\main_converter_counter[0:0] - attribute \src "ls180.v:1757.5-1757.55" - wire $1\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:1758.5-1758.58" - wire $1\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:811.12-811.40" - wire width 32 $1\main_converter_dat_r[31:0] - attribute \src "ls180.v:808.5-808.31" - wire $1\main_converter_skip[0:0] - attribute \src "ls180.v:243.12-243.38" - wire width 16 $1\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:244.5-244.36" - wire $1\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:1005.12-1005.30" - wire width 36 $1\main_dummy[35:0] - attribute \src "ls180.v:960.5-960.27" - wire $1\main_gpio_oe_re[0:0] - attribute \src "ls180.v:959.12-959.40" - wire width 16 $1\main_gpio_oe_storage[15:0] - attribute \src "ls180.v:964.5-964.28" - wire $1\main_gpio_out_re[0:0] - attribute \src "ls180.v:963.12-963.41" - wire width 16 $1\main_gpio_out_storage[15:0] - attribute \src "ls180.v:961.12-961.36" - wire width 16 $1\main_gpio_status[15:0] - attribute \src "ls180.v:1030.5-1030.23" - wire $1\main_i2c_re[0:0] - attribute \src "ls180.v:1029.11-1029.34" - wire width 3 $1\main_i2c_storage[2:0] - attribute \src "ls180.v:228.5-228.24" - wire $1\main_int_rst[0:0] - attribute \src "ls180.v:1578.12-1578.43" - wire width 32 $1\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1582.5-1582.35" - wire $1\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1581.11-1581.41" - wire width 4 $1\main_interface1_bus_sel[3:0] - attribute \src "ls180.v:1583.5-1583.35" - wire $1\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:1585.5-1585.34" - wire $1\main_interface1_bus_we[0:0] - attribute \src "ls180.v:63.12-63.47" - wire width 32 $1\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:150.5-150.47" - wire $1\main_libresocsim_converter0_counter[0:0] - attribute \src "ls180.v:1712.5-1712.69" - wire $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:1713.5-1713.72" - wire $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:152.12-152.53" - wire width 64 $1\main_libresocsim_converter0_dat_r[63:0] - attribute \src "ls180.v:149.5-149.44" - wire $1\main_libresocsim_converter0_skip[0:0] - attribute \src "ls180.v:165.5-165.47" - wire $1\main_libresocsim_converter1_counter[0:0] - attribute \src "ls180.v:1716.5-1716.69" - wire $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:1717.5-1717.72" - wire $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:167.12-167.53" - wire width 64 $1\main_libresocsim_converter1_dat_r[63:0] - attribute \src "ls180.v:164.5-164.44" - wire $1\main_libresocsim_converter1_skip[0:0] - attribute \src "ls180.v:180.5-180.47" - wire $1\main_libresocsim_converter2_counter[0:0] - attribute \src "ls180.v:1720.5-1720.69" - wire $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] - attribute \src "ls180.v:1721.5-1721.72" - wire $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:182.12-182.53" - wire width 64 $1\main_libresocsim_converter2_dat_r[63:0] - attribute \src "ls180.v:179.5-179.44" - wire $1\main_libresocsim_converter2_skip[0:0] - attribute \src "ls180.v:203.5-203.34" - wire $1\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:202.5-202.39" - wire $1\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:223.5-223.44" - wire $1\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:222.5-222.49" - wire $1\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:138.12-138.71" - wire width 30 $1\main_libresocsim_interface0_converted_interface_adr[29:0] - attribute \src "ls180.v:142.5-142.63" - wire $1\main_libresocsim_interface0_converted_interface_cyc[0:0] - attribute \src "ls180.v:139.12-139.73" - wire width 32 $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] - attribute \src "ls180.v:141.11-141.69" - wire width 4 $1\main_libresocsim_interface0_converted_interface_sel[3:0] - attribute \src "ls180.v:143.5-143.63" - wire $1\main_libresocsim_interface0_converted_interface_stb[0:0] - attribute \src "ls180.v:145.5-145.62" - wire $1\main_libresocsim_interface0_converted_interface_we[0:0] - attribute \src "ls180.v:153.12-153.71" - wire width 30 $1\main_libresocsim_interface1_converted_interface_adr[29:0] - attribute \src "ls180.v:157.5-157.63" - wire $1\main_libresocsim_interface1_converted_interface_cyc[0:0] - attribute \src "ls180.v:154.12-154.73" - wire width 32 $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] - attribute \src "ls180.v:156.11-156.69" - wire width 4 $1\main_libresocsim_interface1_converted_interface_sel[3:0] - attribute \src "ls180.v:158.5-158.63" - wire $1\main_libresocsim_interface1_converted_interface_stb[0:0] - attribute \src "ls180.v:160.5-160.62" - wire $1\main_libresocsim_interface1_converted_interface_we[0:0] - attribute \src "ls180.v:168.12-168.71" - wire width 30 $1\main_libresocsim_interface2_converted_interface_adr[29:0] - attribute \src "ls180.v:172.5-172.63" - wire $1\main_libresocsim_interface2_converted_interface_cyc[0:0] - attribute \src "ls180.v:169.12-169.73" - wire width 32 $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] - attribute \src "ls180.v:171.11-171.69" - wire width 4 $1\main_libresocsim_interface2_converted_interface_sel[3:0] - attribute \src "ls180.v:173.5-173.63" - wire $1\main_libresocsim_interface2_converted_interface_stb[0:0] - attribute \src "ls180.v:175.5-175.62" - wire $1\main_libresocsim_interface2_converted_interface_we[0:0] - attribute \src "ls180.v:128.5-128.65" - wire $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] - attribute \src "ls180.v:72.5-72.46" - wire $1\main_libresocsim_libresoc_dbus_ack[0:0] - attribute \src "ls180.v:83.5-83.46" - wire $1\main_libresocsim_libresoc_ibus_ack[0:0] - attribute \src "ls180.v:65.12-65.55" - wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:116.5-116.49" - wire $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] - attribute \src "ls180.v:199.5-199.36" - wire $1\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:198.12-198.49" - wire width 32 $1\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:189.5-189.40" - wire $1\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:201.5-201.38" - wire $1\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:200.12-200.51" - wire width 32 $1\main_libresocsim_reload_storage[31:0] - attribute \src "ls180.v:56.5-56.37" - wire $1\main_libresocsim_reset_re[0:0] - attribute \src "ls180.v:55.5-55.42" - wire $1\main_libresocsim_reset_storage[0:0] - attribute \src "ls180.v:58.5-58.39" - wire $1\main_libresocsim_scratch_re[0:0] - attribute \src "ls180.v:57.12-57.60" - wire width 32 $1\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:205.5-205.44" - wire $1\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:204.5-204.49" - wire $1\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:224.12-224.42" - wire width 32 $1\main_libresocsim_value[31:0] - attribute \src "ls180.v:206.12-206.49" - wire width 32 $1\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:196.11-196.37" - wire width 4 $1\main_libresocsim_we[3:0] - attribute \src "ls180.v:212.5-212.39" - wire $1\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:213.5-213.45" - wire $1\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:210.5-210.41" - wire $1\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:800.12-800.40" - wire width 30 $1\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:804.5-804.32" - wire $1\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:801.12-801.42" - wire width 16 $1\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:803.11-803.38" - wire width 2 $1\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:805.5-805.32" - wire $1\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:807.5-807.31" - wire $1\main_litedram_wb_we[0:0] - attribute \src "ls180.v:1009.12-1009.37" - wire width 32 $1\main_pwm0_counter[31:0] - attribute \src "ls180.v:1011.5-1011.31" - wire $1\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:1010.5-1010.36" - wire $1\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:1015.5-1015.31" - wire $1\main_pwm0_period_re[0:0] - attribute \src "ls180.v:1014.12-1014.44" - wire width 32 $1\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:1013.5-1013.30" - wire $1\main_pwm0_width_re[0:0] - attribute \src "ls180.v:1012.12-1012.43" - wire width 32 $1\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:1019.12-1019.37" - wire width 32 $1\main_pwm1_counter[31:0] - attribute \src "ls180.v:1021.5-1021.31" - wire $1\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:1020.5-1020.36" - wire $1\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:1025.5-1025.31" - wire $1\main_pwm1_period_re[0:0] - attribute \src "ls180.v:1024.12-1024.44" - wire width 32 $1\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:1023.5-1023.30" - wire $1\main_pwm1_width_re[0:0] - attribute \src "ls180.v:1022.12-1022.43" - wire width 32 $1\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:245.11-245.32" - wire width 3 $1\main_rddata_en[2:0] - attribute \src "ls180.v:1547.11-1547.50" - wire width 2 $1\main_sdblock2mem_converter_demux[1:0] - attribute \src "ls180.v:1543.5-1543.51" - wire $1\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:1544.5-1544.50" - wire $1\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:1545.12-1545.66" - wire width 32 $1\main_sdblock2mem_converter_source_payload_data[31:0] - attribute \src "ls180.v:1546.11-1546.77" - wire width 3 $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] - attribute \src "ls180.v:1549.5-1549.49" - wire $1\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:1522.11-1522.47" - wire width 5 $1\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:1519.11-1519.45" - wire width 6 $1\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:1521.11-1521.47" - wire width 5 $1\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1523.11-1523.50" - wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1557.12-1557.62" - wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:1558.12-1558.60" - wire width 32 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] - attribute \src "ls180.v:1555.5-1555.45" - wire $1\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:1565.5-1565.54" - wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:1564.12-1564.67" - wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:1569.5-1569.56" - wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:1568.5-1568.61" - wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:1567.5-1567.56" - wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:1566.12-1566.69" - wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:1573.5-1573.54" - wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:1572.5-1572.59" - wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:1575.12-1575.61" - wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:1829.12-1829.87" - wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:1830.5-1830.82" - wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:1560.5-1560.57" - wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:1570.5-1570.53" - wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:1339.5-1339.38" - wire $1\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:1338.12-1338.51" - wire width 32 $1\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:1337.5-1337.39" - wire $1\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:1336.11-1336.51" - wire width 10 $1\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:1323.5-1323.39" - wire $1\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:1322.12-1322.52" - wire width 32 $1\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:1325.5-1325.38" - wire $1\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:1324.12-1324.51" - wire width 32 $1\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:1478.11-1478.39" - wire width 3 $1\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:1813.11-1813.62" - wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:1814.5-1814.59" - wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:1479.5-1479.32" - wire $1\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:1809.5-1809.55" - wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:1810.5-1810.58" - wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:1480.5-1480.33" - wire $1\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:1817.5-1817.56" - wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:1818.5-1818.59" - wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:1330.13-1330.53" - wire width 128 $1\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:1825.13-1825.76" - wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:1826.5-1826.69" - wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1481.5-1481.35" - wire $1\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:1819.5-1819.58" - wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:1820.5-1820.61" - wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:1439.11-1439.47" - wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:1445.5-1445.46" - wire $1\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:1444.12-1444.54" - wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:1440.12-1440.58" - wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:1452.5-1452.46" - wire $1\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:1451.12-1451.54" - wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:1447.12-1447.58" - wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:1459.5-1459.46" - wire $1\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:1458.12-1458.54" - wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:1454.12-1454.58" - wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:1466.5-1466.46" - wire $1\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:1465.12-1465.54" - wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:1461.12-1461.58" - wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:1468.12-1468.53" - wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:1469.12-1469.53" - wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:1470.12-1470.53" - wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:1471.12-1471.53" - wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:1473.12-1473.51" - wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:1474.12-1474.51" - wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:1475.12-1475.51" - wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:1476.12-1476.51" - wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:1430.5-1430.48" - wire $1\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:1431.5-1431.47" - wire $1\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:1432.11-1432.61" - wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:1429.5-1429.48" - wire $1\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:1428.5-1428.48" - wire $1\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1433.5-1433.50" - wire $1\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:1438.11-1438.47" - wire width 8 $1\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:1472.5-1472.43" - wire $1\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:1395.11-1395.48" - wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:1805.11-1805.87" - wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:1806.5-1806.84" - wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:1400.12-1400.55" - wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:1396.12-1396.59" - wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:1407.12-1407.55" - wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:1403.12-1403.59" - wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:1414.12-1414.55" - wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:1410.12-1410.59" - wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:1421.12-1421.55" - wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:1417.12-1417.59" - wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:1424.12-1424.54" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:1797.12-1797.93" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:1798.5-1798.88" - wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:1425.12-1425.54" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:1799.12-1799.93" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:1800.5-1800.88" - wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:1426.12-1426.54" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:1801.12-1801.93" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:1802.5-1802.88" - wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:1427.12-1427.54" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:1803.12-1803.93" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:1804.5-1804.88" - wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:1386.5-1386.49" - wire $1\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1393.5-1393.50" - wire $1\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:1394.11-1394.64" - wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:1391.5-1391.51" - wire $1\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:1390.5-1390.51" - wire $1\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:1382.11-1382.47" - wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:1340.11-1340.51" - wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:1483.12-1483.42" - wire width 32 $1\main_sdcore_data_count[31:0] - attribute \src "ls180.v:1815.12-1815.65" - wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:1816.5-1816.60" - wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:1484.5-1484.33" - wire $1\main_sdcore_data_done[0:0] - attribute \src "ls180.v:1811.5-1811.56" - wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:1812.5-1812.59" - wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:1485.5-1485.34" - wire $1\main_sdcore_data_error[0:0] - attribute \src "ls180.v:1821.5-1821.57" - wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:1822.5-1822.60" - wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:1486.5-1486.36" - wire $1\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:1823.5-1823.59" - wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:1824.5-1824.62" - wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:1631.11-1631.48" - wire width 2 $1\main_sdmem2block_converter_mux[1:0] - attribute \src "ls180.v:1629.11-1629.64" - wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:1605.5-1605.40" - wire $1\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:1604.12-1604.53" - wire width 64 $1\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:1603.12-1603.45" - wire width 32 $1\main_sdmem2block_dma_data[31:0] - attribute \src "ls180.v:1833.12-1833.75" - wire width 32 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - attribute \src "ls180.v:1834.5-1834.70" - wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1610.5-1610.44" - wire $1\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:1609.5-1609.42" - wire $1\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:1608.5-1608.47" - wire $1\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:1607.5-1607.42" - wire $1\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:1606.12-1606.55" - wire width 32 $1\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:1613.5-1613.40" - wire $1\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:1612.5-1612.45" - wire $1\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:1617.12-1617.47" - wire width 32 $1\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:1837.12-1837.87" - wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:1838.5-1838.82" - wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:1596.5-1596.42" - wire $1\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:1597.12-1597.61" - wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:1595.5-1595.43" - wire $1\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:1594.5-1594.43" - wire $1\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1601.5-1601.44" - wire $1\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:1602.12-1602.60" - wire width 32 $1\main_sdmem2block_dma_source_payload_data[31:0] - attribute \src "ls180.v:1598.5-1598.45" - wire $1\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:1658.11-1658.47" - wire width 5 $1\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:1655.11-1655.45" - wire width 6 $1\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:1657.11-1657.47" - wire width 5 $1\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1659.11-1659.50" - wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1039.5-1039.35" - wire $1\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:1042.5-1042.35" - wire $1\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:1043.5-1043.36" - wire $1\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:1041.11-1041.41" - wire width 9 $1\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:1037.5-1037.33" - wire $1\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:1036.11-1036.46" - wire width 9 $1\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:1145.5-1145.49" - wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:1146.5-1146.48" - wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:1147.11-1147.62" - wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1143.5-1143.49" - wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:1130.11-1130.54" - wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1126.5-1126.55" - wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:1127.5-1127.54" - wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:1128.11-1128.68" - wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1129.11-1129.81" - wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1132.5-1132.53" - wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1148.5-1148.38" - wire $1\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:1777.5-1777.66" - wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:1778.5-1778.69" - wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:1118.5-1118.36" - wire $1\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:1113.5-1113.53" - wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:1100.11-1100.39" - wire width 8 $1\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:1773.11-1773.67" - wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:1774.5-1774.64" - wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1085.5-1085.48" - wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1086.5-1086.50" - wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1087.5-1087.51" - wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1092.5-1092.37" - wire $1\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:1093.11-1093.53" - wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:1091.5-1091.38" - wire $1\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:1090.5-1090.38" - wire $1\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:1096.5-1096.39" - wire $1\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:1097.11-1097.53" - wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:1098.11-1098.55" - wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:1095.5-1095.40" - wire $1\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:1094.5-1094.40" - wire $1\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:1099.12-1099.48" - wire width 32 $1\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:1775.12-1775.71" - wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:1776.5-1776.66" - wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:1072.11-1072.39" - wire width 8 $1\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:1769.11-1769.66" - wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:1770.5-1770.63" - wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:1071.5-1071.32" - wire $1\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:1062.5-1062.48" - wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1063.5-1063.50" - wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1064.5-1064.51" - wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1069.5-1069.37" - wire $1\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:1070.11-1070.51" - wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:1068.5-1068.38" - wire $1\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:1067.5-1067.38" - wire $1\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:1256.11-1256.41" - wire width 10 $1\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:1789.11-1789.70" - wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:1790.5-1790.66" - wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:1301.5-1301.51" - wire $1\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:1302.5-1302.50" - wire $1\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:1303.11-1303.64" - wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:1299.5-1299.51" - wire $1\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:1286.5-1286.50" - wire $1\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1282.5-1282.57" - wire $1\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:1283.5-1283.56" - wire $1\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:1284.11-1284.70" - wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:1285.11-1285.83" - wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:1288.5-1288.55" - wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1304.5-1304.40" - wire $1\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:1793.5-1793.69" - wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:1794.5-1794.72" - wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:1274.5-1274.38" - wire $1\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:1269.5-1269.55" - wire $1\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1239.5-1239.49" - wire $1\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1246.5-1246.38" - wire $1\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:1247.11-1247.61" - wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:1245.5-1245.39" - wire $1\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:1244.5-1244.39" - wire $1\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1251.5-1251.40" - wire $1\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:1252.11-1252.54" - wire width 8 $1\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:1253.11-1253.56" - wire width 3 $1\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:1249.5-1249.41" - wire $1\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:1248.5-1248.41" - wire $1\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:1254.5-1254.33" - wire $1\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:1255.12-1255.49" - wire width 32 $1\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:1791.12-1791.73" - wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:1792.5-1792.68" - wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:1164.11-1164.40" - wire width 8 $1\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:1785.11-1785.61" - wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:1786.5-1786.58" - wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1223.5-1223.50" - wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:1224.5-1224.49" - wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:1225.11-1225.63" - wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1221.5-1221.50" - wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:1208.11-1208.55" - wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1204.5-1204.56" - wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:1205.5-1205.55" - wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:1206.11-1206.69" - wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1207.11-1207.82" - wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1210.5-1210.54" - wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1226.5-1226.39" - wire $1\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:1781.5-1781.66" - wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:1782.5-1782.69" - wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:1196.5-1196.37" - wire $1\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:1191.5-1191.54" - wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:1178.5-1178.34" - wire $1\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1153.5-1153.49" - wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1156.11-1156.58" - wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1157.5-1157.53" - wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1160.5-1160.39" - wire $1\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:1161.5-1161.38" - wire $1\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:1162.11-1162.52" - wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:1159.5-1159.39" - wire $1\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:1158.5-1158.39" - wire $1\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:1176.5-1176.34" - wire $1\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:1163.5-1163.33" - wire $1\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:1177.5-1177.34" - wire $1\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:1057.11-1057.39" - wire width 8 $1\main_sdphy_init_count[7:0] - attribute \src "ls180.v:1765.11-1765.66" - wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:1766.5-1766.63" - wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1052.5-1052.48" - wire $1\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1053.5-1053.50" - wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1054.5-1054.51" - wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1055.11-1055.57" - wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1056.5-1056.52" - wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1306.5-1306.35" - wire $1\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:1309.11-1309.42" - wire width 4 $1\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:307.5-307.33" - wire $1\main_sdram_address_re[0:0] - attribute \src "ls180.v:306.12-306.46" - wire width 13 $1\main_sdram_address_storage[12:0] - attribute \src "ls180.v:309.5-309.34" - wire $1\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:308.11-308.45" - wire width 2 $1\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:405.5-405.50" - wire $1\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:427.11-427.70" - wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:424.11-424.68" - wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:426.11-426.70" - wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:428.11-428.73" - wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:451.5-451.59" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:452.5-452.58" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:454.12-454.74" - wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:453.5-453.64" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:449.5-449.59" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:397.12-397.57" - wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:399.5-399.51" - wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:402.5-402.54" - wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:403.5-403.55" - wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:404.5-404.56" - wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:400.5-400.51" - wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:401.5-401.50" - wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:396.5-396.45" - wire $1\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:395.5-395.45" - wire $1\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:394.5-394.47" - wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:392.5-392.51" - wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:391.5-391.51" - wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:455.12-455.47" - wire width 13 $1\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:459.5-459.45" - wire $1\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:460.5-460.54" - wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:458.5-458.44" - wire $1\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:456.5-456.46" - wire $1\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:463.11-463.55" - wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:462.32-462.76" - wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:487.5-487.50" - wire $1\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:509.11-509.70" - wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:506.11-506.68" - wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:508.11-508.70" - wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:510.11-510.73" - wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:533.5-533.59" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:534.5-534.58" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:536.12-536.74" - wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:535.5-535.64" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:531.5-531.59" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:479.12-479.57" - wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:481.5-481.51" - wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:484.5-484.54" - wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:485.5-485.55" - wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:486.5-486.56" - wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:482.5-482.51" - wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:483.5-483.50" - wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:478.5-478.45" - wire $1\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:477.5-477.45" - wire $1\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:476.5-476.47" - wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:474.5-474.51" - wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:473.5-473.51" - wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:537.12-537.47" - wire width 13 $1\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:541.5-541.45" - wire $1\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:542.5-542.54" - wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:540.5-540.44" - wire $1\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:538.5-538.46" - wire $1\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:545.11-545.55" - wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:544.32-544.76" - wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:569.5-569.50" - wire $1\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:591.11-591.70" - wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:588.11-588.68" - wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:590.11-590.70" - wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:592.11-592.73" - wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:615.5-615.59" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:616.5-616.58" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:618.12-618.74" - wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:617.5-617.64" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:613.5-613.59" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:561.12-561.57" - wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:563.5-563.51" - wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:566.5-566.54" - wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:567.5-567.55" - wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:568.5-568.56" - wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:564.5-564.51" - wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:565.5-565.50" - wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:560.5-560.45" - wire $1\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:559.5-559.45" - wire $1\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:558.5-558.47" - wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:556.5-556.51" - wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:555.5-555.51" - wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:619.12-619.47" - wire width 13 $1\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:623.5-623.45" - wire $1\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:624.5-624.54" - wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:622.5-622.44" - wire $1\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:620.5-620.46" - wire $1\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:627.11-627.55" - wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:626.32-626.76" - wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:651.5-651.50" - wire $1\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:673.11-673.70" - wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:670.11-670.68" - wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:672.11-672.70" - wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:674.11-674.73" - wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:697.5-697.59" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:698.5-698.58" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:700.12-700.74" - wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:699.5-699.64" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:695.5-695.59" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:643.12-643.57" - wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:645.5-645.51" - wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:648.5-648.54" - wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:649.5-649.55" - wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:650.5-650.56" - wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:646.5-646.51" - wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:647.5-647.50" - wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:642.5-642.45" - wire $1\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:641.5-641.45" - wire $1\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:640.5-640.47" - wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:638.5-638.51" - wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:637.5-637.51" - wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:701.12-701.47" - wire width 13 $1\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:705.5-705.45" - wire $1\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:706.5-706.54" - wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:704.5-704.44" - wire $1\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:702.5-702.46" - wire $1\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:709.11-709.55" - wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:708.32-708.76" - wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:724.5-724.49" - wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:725.5-725.49" - wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:726.5-726.48" - wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:732.11-732.45" - wire width 2 $1\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:730.11-730.46" - wire width 4 $1\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:742.5-742.49" - wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:743.5-743.49" - wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:744.5-744.48" - wire $1\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:739.5-739.43" - wire $1\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:750.11-750.45" - wire width 2 $1\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:748.11-748.46" - wire width 4 $1\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:737.5-737.48" - wire $1\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:734.5-734.44" - wire $1\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:735.5-735.45" - wire $1\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:363.5-363.31" - wire $1\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:364.12-364.44" - wire width 13 $1\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:365.11-365.43" - wire width 2 $1\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:366.5-366.38" - wire $1\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:367.5-367.38" - wire $1\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:368.5-368.37" - wire $1\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:362.5-362.32" - wire $1\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:361.5-361.32" - wire $1\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:301.5-301.33" - wire $1\main_sdram_command_re[0:0] - attribute \src "ls180.v:300.11-300.44" - wire width 6 $1\main_sdram_command_storage[5:0] - attribute \src "ls180.v:345.12-345.45" - wire width 13 $1\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:346.11-346.40" - wire width 2 $1\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:347.5-347.35" - wire $1\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:348.5-348.34" - wire $1\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:349.5-349.35" - wire $1\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:358.5-358.39" - wire $1\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:350.5-350.34" - wire $1\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:356.5-356.39" - wire $1\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:769.5-769.26" - wire $1\main_sdram_en0[0:0] - attribute \src "ls180.v:772.5-772.26" - wire $1\main_sdram_en1[0:0] - attribute \src "ls180.v:342.12-342.46" - wire width 16 $1\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:343.11-343.47" - wire width 2 $1\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:248.5-248.36" - wire $1\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:249.5-249.35" - wire $1\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:250.5-250.36" - wire $1\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:260.12-260.45" - wire width 16 $1\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:261.5-261.43" - wire $1\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:251.5-251.35" - wire $1\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:287.5-287.38" - wire $1\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:278.12-278.48" - wire width 13 $1\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:279.11-279.43" - wire width 2 $1\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:280.5-280.38" - wire $1\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:284.5-284.36" - wire $1\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:281.5-281.37" - wire $1\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:285.5-285.36" - wire $1\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:282.5-282.38" - wire $1\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:291.5-291.42" - wire $1\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:286.5-286.40" - wire $1\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:283.5-283.37" - wire $1\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:288.12-288.47" - wire width 16 $1\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:289.5-289.42" - wire $1\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:290.11-290.50" - wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:379.5-379.38" - wire $1\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:378.5-378.38" - wire $1\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:299.5-299.25" - wire $1\main_sdram_re[0:0] - attribute \src "ls180.v:385.5-385.38" - wire $1\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:384.11-384.46" - wire width 4 $1\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:383.5-383.38" - wire $1\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:380.5-380.39" - wire $1\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:276.12-276.46" - wire width 16 $1\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:277.5-277.44" - wire $1\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:312.12-312.37" - wire width 16 $1\main_sdram_status[15:0] - attribute \src "ls180.v:754.11-754.40" - wire width 2 $1\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:298.11-298.36" - wire width 4 $1\main_sdram_storage[3:0] - attribute \src "ls180.v:763.5-763.36" - wire $1\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:762.32-762.63" - wire $1\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:771.11-771.34" - wire width 5 $1\main_sdram_time0[4:0] - attribute \src "ls180.v:774.11-774.34" - wire width 4 $1\main_sdram_time1[3:0] - attribute \src "ls180.v:376.11-376.44" - wire width 10 $1\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:766.11-766.42" - wire width 3 $1\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:765.32-765.63" - wire $1\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:311.5-311.32" - wire $1\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:310.12-310.45" - wire width 16 $1\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:998.12-998.48" - wire width 16 $1\main_spi_master_clk_divider1[15:0] - attribute \src "ls180.v:993.5-993.38" - wire $1\main_spi_master_clk_enable[0:0] - attribute \src "ls180.v:980.5-980.38" - wire $1\main_spi_master_control_re[0:0] - attribute \src "ls180.v:979.12-979.51" - wire width 16 $1\main_spi_master_control_storage[15:0] - attribute \src "ls180.v:995.11-995.39" - wire width 3 $1\main_spi_master_count[2:0] - attribute \src "ls180.v:1761.11-1761.61" - wire width 3 $1\main_spi_master_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:1762.5-1762.58" - wire $1\main_spi_master_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:994.5-994.37" - wire $1\main_spi_master_cs_enable[0:0] - attribute \src "ls180.v:990.5-990.33" - wire $1\main_spi_master_cs_re[0:0] - attribute \src "ls180.v:989.5-989.38" - wire $1\main_spi_master_cs_storage[0:0] - attribute \src "ls180.v:970.5-970.33" - wire $1\main_spi_master_done0[0:0] - attribute \src "ls180.v:971.5-971.31" - wire $1\main_spi_master_irq[0:0] - attribute \src "ls180.v:992.5-992.39" - wire $1\main_spi_master_loopback_re[0:0] - attribute \src "ls180.v:991.5-991.44" - wire $1\main_spi_master_loopback_storage[0:0] - attribute \src "ls180.v:973.11-973.38" - wire width 8 $1\main_spi_master_miso[7:0] - attribute \src "ls180.v:1003.11-1003.43" - wire width 8 $1\main_spi_master_miso_data[7:0] - attribute \src "ls180.v:997.5-997.38" - wire $1\main_spi_master_miso_latch[0:0] - attribute \src "ls180.v:1001.11-1001.43" - wire width 8 $1\main_spi_master_mosi_data[7:0] - attribute \src "ls180.v:996.5-996.38" - wire $1\main_spi_master_mosi_latch[0:0] - attribute \src "ls180.v:985.5-985.35" - wire $1\main_spi_master_mosi_re[0:0] - attribute \src "ls180.v:1002.11-1002.42" - wire width 3 $1\main_spi_master_mosi_sel[2:0] - attribute \src "ls180.v:984.11-984.46" - wire width 8 $1\main_spi_master_mosi_storage[7:0] - attribute \src "ls180.v:977.5-977.34" - wire $1\main_spi_master_start1[0:0] - attribute \src "ls180.v:867.11-867.50" - wire width 2 $1\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:869.5-869.37" - wire $1\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:863.11-863.49" - wire width 2 $1\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:868.11-868.48" - wire width 2 $1\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:835.12-835.54" - wire width 32 $1\main_uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:825.12-825.54" - wire width 32 $1\main_uart_phy_phase_accumulator_tx[31:0] - attribute \src "ls180.v:818.5-818.28" - wire $1\main_uart_phy_re[0:0] - attribute \src "ls180.v:839.11-839.43" - wire width 4 $1\main_uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:840.5-840.33" - wire $1\main_uart_phy_rx_busy[0:0] - attribute \src "ls180.v:837.5-837.30" - wire $1\main_uart_phy_rx_r[0:0] - attribute \src "ls180.v:838.11-838.38" - wire width 8 $1\main_uart_phy_rx_reg[7:0] - attribute \src "ls180.v:820.5-820.36" - wire $1\main_uart_phy_sink_ready[0:0] - attribute \src "ls180.v:833.11-833.51" - wire width 8 $1\main_uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:829.5-829.38" - wire $1\main_uart_phy_source_valid[0:0] - attribute \src "ls180.v:817.12-817.47" - wire width 32 $1\main_uart_phy_storage[31:0] - attribute \src "ls180.v:827.11-827.43" - wire width 4 $1\main_uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:828.5-828.33" - wire $1\main_uart_phy_tx_busy[0:0] - attribute \src "ls180.v:826.11-826.38" - wire width 8 $1\main_uart_phy_tx_reg[7:0] - attribute \src "ls180.v:834.5-834.39" - wire $1\main_uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:824.5-824.39" - wire $1\main_uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:858.5-858.30" - wire $1\main_uart_rx_clear[0:0] - attribute \src "ls180.v:942.11-942.43" - wire width 4 $1\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:939.11-939.42" - wire width 5 $1\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:941.11-941.43" - wire width 4 $1\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:932.5-932.38" - wire $1\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:943.11-943.46" - wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:859.5-859.36" - wire $1\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:856.5-856.32" - wire $1\main_uart_rx_pending[0:0] - attribute \src "ls180.v:853.5-853.30" - wire $1\main_uart_tx_clear[0:0] - attribute \src "ls180.v:905.11-905.43" - wire width 4 $1\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:902.11-902.42" - wire width 5 $1\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:904.11-904.43" - wire width 4 $1\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:895.5-895.38" - wire $1\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:906.11-906.46" - wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:854.5-854.36" - wire $1\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:851.5-851.32" - wire $1\main_uart_tx_pending[0:0] - attribute \src "ls180.v:795.5-795.29" - wire $1\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:813.5-813.31" - wire $1\main_wdata_consumed[0:0] - attribute \src "ls180.v:2799.68-2799.110" - wire $add$ls180.v:2799$22_Y - attribute \src "ls180.v:2859.68-2859.110" - wire $add$ls180.v:2859$33_Y - attribute \src "ls180.v:2919.68-2919.110" - wire $add$ls180.v:2919$44_Y - attribute \src "ls180.v:4052.54-4052.83" - wire $add$ls180.v:4052$537_Y - attribute \src "ls180.v:4152.36-4152.89" - wire width 5 $add$ls180.v:4152$583_Y - attribute \src "ls180.v:4182.36-4182.89" - wire width 5 $add$ls180.v:4182$594_Y - attribute \src "ls180.v:4237.53-4237.81" - wire width 3 $add$ls180.v:4237$607_Y - attribute \src "ls180.v:4341.58-4341.86" - wire width 8 $add$ls180.v:4341$635_Y - attribute \src "ls180.v:4398.58-4398.86" - wire width 8 $add$ls180.v:4398$638_Y - attribute \src "ls180.v:4415.58-4415.86" - wire width 8 $add$ls180.v:4415$640_Y - attribute \src "ls180.v:4508.59-4508.87" - wire width 8 $add$ls180.v:4508$657_Y - attribute \src "ls180.v:4533.59-4533.87" - wire width 8 $add$ls180.v:4533$660_Y - attribute \src "ls180.v:4655.53-4655.82" - wire width 8 $add$ls180.v:4655$677_Y - attribute \src "ls180.v:4766.65-4766.114" - wire width 10 $add$ls180.v:4766$691_Y - attribute \src "ls180.v:4771.62-4771.91" - wire width 10 $add$ls180.v:4771$694_Y - attribute \src "ls180.v:4797.61-4797.90" - wire width 10 $add$ls180.v:4797$697_Y - attribute \src "ls180.v:5001.80-5001.117" - wire width 3 $add$ls180.v:5001$882_Y - attribute \src "ls180.v:5195.54-5195.82" - wire width 3 $add$ls180.v:5195$957_Y - attribute \src "ls180.v:5247.55-5247.84" - wire width 32 $add$ls180.v:5247$967_Y - attribute \src "ls180.v:5273.57-5273.86" - wire width 32 $add$ls180.v:5273$975_Y - attribute \src "ls180.v:5394.51-5394.134" - wire width 32 $add$ls180.v:5394$991_Y - attribute \src "ls180.v:5397.77-5397.125" - wire width 32 $add$ls180.v:5397$993_Y - attribute \src "ls180.v:5490.50-5490.105" - wire width 32 $add$ls180.v:5490$1002_Y - attribute \src "ls180.v:5492.77-5492.111" - wire width 32 $add$ls180.v:5492$1003_Y - attribute \src "ls180.v:5604.49-5604.73" - wire width 3 $add$ls180.v:5604$1022_Y - attribute \src "ls180.v:7483.36-7483.70" - wire width 32 $add$ls180.v:7483$2415_Y - attribute \src "ls180.v:7568.37-7568.72" - wire width 4 $add$ls180.v:7568$2436_Y - attribute \src "ls180.v:7585.60-7585.119" - wire width 3 $add$ls180.v:7585$2440_Y - attribute \src "ls180.v:7588.60-7588.119" - wire width 3 $add$ls180.v:7588$2441_Y - attribute \src "ls180.v:7592.59-7592.116" - wire width 4 $add$ls180.v:7592$2446_Y - attribute \src "ls180.v:7631.60-7631.119" - wire width 3 $add$ls180.v:7631$2456_Y - attribute \src "ls180.v:7634.60-7634.119" - wire width 3 $add$ls180.v:7634$2457_Y - attribute \src "ls180.v:7638.59-7638.116" - wire width 4 $add$ls180.v:7638$2462_Y - attribute \src "ls180.v:7677.60-7677.119" - wire width 3 $add$ls180.v:7677$2472_Y - attribute \src "ls180.v:7680.60-7680.119" - wire width 3 $add$ls180.v:7680$2473_Y - attribute \src "ls180.v:7684.59-7684.116" - wire width 4 $add$ls180.v:7684$2478_Y - attribute \src "ls180.v:7723.60-7723.119" - wire width 3 $add$ls180.v:7723$2488_Y - attribute \src "ls180.v:7726.60-7726.119" - wire width 3 $add$ls180.v:7726$2489_Y - attribute \src "ls180.v:7730.59-7730.116" - wire width 4 $add$ls180.v:7730$2494_Y - attribute \src "ls180.v:7960.34-7960.66" - wire width 4 $add$ls180.v:7960$2548_Y - attribute \src "ls180.v:7976.73-7976.131" - wire width 33 $add$ls180.v:7976$2551_Y - attribute \src "ls180.v:7989.34-7989.66" - wire width 4 $add$ls180.v:7989$2555_Y - attribute \src "ls180.v:8008.73-8008.131" - wire width 33 $add$ls180.v:8008$2558_Y - attribute \src "ls180.v:8034.33-8034.65" - wire width 4 $add$ls180.v:8034$2566_Y - attribute \src "ls180.v:8037.33-8037.65" - wire width 4 $add$ls180.v:8037$2567_Y - attribute \src "ls180.v:8041.33-8041.64" - wire width 5 $add$ls180.v:8041$2572_Y - attribute \src "ls180.v:8056.33-8056.65" - wire width 4 $add$ls180.v:8056$2577_Y - attribute \src "ls180.v:8059.33-8059.65" - wire width 4 $add$ls180.v:8059$2578_Y - attribute \src "ls180.v:8063.33-8063.64" - wire width 5 $add$ls180.v:8063$2583_Y - attribute \src "ls180.v:8084.35-8084.70" - wire width 16 $add$ls180.v:8084$2585_Y - attribute \src "ls180.v:8120.25-8120.49" - wire width 32 $add$ls180.v:8120$2590_Y - attribute \src "ls180.v:8134.25-8134.49" - wire width 32 $add$ls180.v:8134$2594_Y - attribute \src "ls180.v:8148.31-8148.61" - wire width 9 $add$ls180.v:8148$2599_Y - attribute \src "ls180.v:8171.45-8171.88" - wire width 3 $add$ls180.v:8171$2603_Y - attribute \src "ls180.v:8217.71-8217.114" - wire width 4 $add$ls180.v:8217$2609_Y - attribute \src "ls180.v:8252.46-8252.90" - wire width 3 $add$ls180.v:8252$2615_Y - attribute \src "ls180.v:8298.72-8298.116" - wire width 4 $add$ls180.v:8298$2621_Y - attribute \src "ls180.v:8331.47-8331.92" - wire $add$ls180.v:8331$2627_Y - attribute \src "ls180.v:8359.73-8359.118" - wire width 2 $add$ls180.v:8359$2633_Y - attribute \src "ls180.v:8471.39-8471.75" - wire width 4 $add$ls180.v:8471$2646_Y - attribute \src "ls180.v:8532.37-8532.73" - wire width 5 $add$ls180.v:8532$2650_Y - attribute \src "ls180.v:8535.37-8535.73" - wire width 5 $add$ls180.v:8535$2651_Y - attribute \src "ls180.v:8539.36-8539.70" - wire width 6 $add$ls180.v:8539$2656_Y - attribute \src "ls180.v:8554.41-8554.80" - wire width 2 $add$ls180.v:8554$2660_Y - attribute \src "ls180.v:8588.67-8588.106" - wire width 3 $add$ls180.v:8588$2666_Y - attribute \src "ls180.v:8614.39-8614.76" - wire width 2 $add$ls180.v:8614$2668_Y - attribute \src "ls180.v:8618.37-8618.73" - wire width 5 $add$ls180.v:8618$2672_Y - attribute \src "ls180.v:8621.37-8621.73" - wire width 5 $add$ls180.v:8621$2673_Y - attribute \src "ls180.v:8625.36-8625.70" - wire width 6 $add$ls180.v:8625$2678_Y - attribute \src "ls180.v:8632.31-8632.62" - wire width 16 $add$ls180.v:8632$2680_Y - attribute \src "ls180.v:2793.9-2793.80" - wire $and$ls180.v:2793$17_Y - attribute \src "ls180.v:2811.9-2811.80" - wire $and$ls180.v:2811$24_Y - attribute \src "ls180.v:2853.9-2853.80" - wire $and$ls180.v:2853$28_Y - attribute \src "ls180.v:2871.9-2871.80" - wire $and$ls180.v:2871$35_Y - attribute \src "ls180.v:2913.9-2913.86" - wire $and$ls180.v:2913$39_Y - attribute \src "ls180.v:2931.9-2931.86" - wire $and$ls180.v:2931$46_Y - attribute \src "ls180.v:2941.31-2941.90" - wire $and$ls180.v:2941$48_Y - attribute \src "ls180.v:2941.30-2941.121" - wire $and$ls180.v:2941$49_Y - attribute \src "ls180.v:2941.29-2941.156" - wire $and$ls180.v:2941$50_Y - attribute \src "ls180.v:2942.31-2942.90" - wire $and$ls180.v:2942$51_Y - attribute \src "ls180.v:2942.30-2942.121" - wire $and$ls180.v:2942$52_Y - attribute \src "ls180.v:2942.29-2942.156" - wire $and$ls180.v:2942$53_Y - attribute \src "ls180.v:2943.31-2943.90" - wire $and$ls180.v:2943$54_Y - attribute \src "ls180.v:2943.30-2943.121" - wire $and$ls180.v:2943$55_Y - attribute \src "ls180.v:2943.29-2943.156" - wire $and$ls180.v:2943$56_Y - attribute \src "ls180.v:2944.31-2944.90" - wire $and$ls180.v:2944$57_Y - attribute \src "ls180.v:2944.30-2944.121" - wire $and$ls180.v:2944$58_Y - attribute \src "ls180.v:2944.29-2944.156" - wire $and$ls180.v:2944$59_Y - attribute \src "ls180.v:2953.7-2953.89" - wire $and$ls180.v:2953$62_Y - attribute \src "ls180.v:2958.32-2958.111" - wire $and$ls180.v:2958$63_Y - attribute \src "ls180.v:3072.40-3072.99" - wire $and$ls180.v:3072$70_Y - attribute \src "ls180.v:3073.40-3073.99" - wire $and$ls180.v:3073$71_Y - attribute \src "ls180.v:3111.38-3111.103" - wire $and$ls180.v:3111$77_Y - attribute \src "ls180.v:3165.50-3165.119" - wire $and$ls180.v:3165$85_Y - attribute \src "ls180.v:3165.49-3165.167" - wire $and$ls180.v:3165$86_Y - attribute \src "ls180.v:3166.49-3166.118" - wire $and$ls180.v:3166$87_Y - attribute \src "ls180.v:3166.48-3166.154" - wire $and$ls180.v:3166$88_Y - attribute \src "ls180.v:3167.50-3167.119" - wire $and$ls180.v:3167$89_Y - attribute \src "ls180.v:3167.49-3167.155" - wire $and$ls180.v:3167$90_Y - attribute \src "ls180.v:3170.7-3170.114" - wire $and$ls180.v:3170$92_Y - attribute \src "ls180.v:3199.66-3199.246" - wire $and$ls180.v:3199$98_Y - attribute \src "ls180.v:3200.64-3200.187" - wire $and$ls180.v:3200$99_Y - attribute \src "ls180.v:3224.9-3224.86" - wire $and$ls180.v:3224$105_Y - attribute \src "ls180.v:3236.9-3236.86" - wire $and$ls180.v:3236$106_Y - attribute \src "ls180.v:3286.13-3286.87" - wire $and$ls180.v:3286$108_Y - attribute \src "ls180.v:3322.50-3322.119" - wire $and$ls180.v:3322$115_Y - attribute \src "ls180.v:3322.49-3322.167" - wire $and$ls180.v:3322$116_Y - attribute \src "ls180.v:3323.49-3323.118" - wire $and$ls180.v:3323$117_Y - attribute \src "ls180.v:3323.48-3323.154" - wire $and$ls180.v:3323$118_Y - attribute \src "ls180.v:3324.50-3324.119" - wire $and$ls180.v:3324$119_Y - attribute \src "ls180.v:3324.49-3324.155" - wire $and$ls180.v:3324$120_Y - attribute \src "ls180.v:3327.7-3327.114" - wire $and$ls180.v:3327$122_Y - attribute \src "ls180.v:3356.66-3356.246" - wire $and$ls180.v:3356$128_Y - attribute \src "ls180.v:3357.64-3357.187" - wire $and$ls180.v:3357$129_Y - attribute \src "ls180.v:3381.9-3381.86" - wire $and$ls180.v:3381$135_Y - attribute \src "ls180.v:3393.9-3393.86" - wire $and$ls180.v:3393$136_Y - attribute \src "ls180.v:3443.13-3443.87" - wire $and$ls180.v:3443$138_Y - attribute \src "ls180.v:3479.50-3479.119" - wire $and$ls180.v:3479$145_Y - attribute \src "ls180.v:3479.49-3479.167" - wire $and$ls180.v:3479$146_Y - attribute \src "ls180.v:3480.49-3480.118" - wire $and$ls180.v:3480$147_Y - attribute \src "ls180.v:3480.48-3480.154" - wire $and$ls180.v:3480$148_Y - attribute \src "ls180.v:3481.50-3481.119" - wire $and$ls180.v:3481$149_Y - attribute \src "ls180.v:3481.49-3481.155" - wire $and$ls180.v:3481$150_Y - attribute \src "ls180.v:3484.7-3484.114" - wire $and$ls180.v:3484$152_Y - attribute \src "ls180.v:3513.66-3513.246" - wire $and$ls180.v:3513$158_Y - attribute \src "ls180.v:3514.64-3514.187" - wire $and$ls180.v:3514$159_Y - attribute \src "ls180.v:3538.9-3538.86" - wire $and$ls180.v:3538$165_Y - attribute \src "ls180.v:3550.9-3550.86" - wire $and$ls180.v:3550$166_Y - attribute \src "ls180.v:3600.13-3600.87" - wire $and$ls180.v:3600$168_Y - attribute \src "ls180.v:3636.50-3636.119" - wire $and$ls180.v:3636$175_Y - attribute \src "ls180.v:3636.49-3636.167" - wire $and$ls180.v:3636$176_Y - attribute \src "ls180.v:3637.49-3637.118" - wire $and$ls180.v:3637$177_Y - attribute \src "ls180.v:3637.48-3637.154" - wire $and$ls180.v:3637$178_Y - attribute \src "ls180.v:3638.50-3638.119" - wire $and$ls180.v:3638$179_Y - attribute \src "ls180.v:3638.49-3638.155" - wire $and$ls180.v:3638$180_Y - attribute \src "ls180.v:3641.7-3641.114" - wire $and$ls180.v:3641$182_Y - attribute \src "ls180.v:3670.66-3670.246" - wire $and$ls180.v:3670$188_Y - attribute \src "ls180.v:3671.64-3671.187" - wire $and$ls180.v:3671$189_Y - attribute \src "ls180.v:3695.9-3695.86" - wire $and$ls180.v:3695$195_Y - attribute \src "ls180.v:3707.9-3707.86" - wire $and$ls180.v:3707$196_Y - attribute \src "ls180.v:3757.13-3757.87" - wire $and$ls180.v:3757$198_Y - attribute \src "ls180.v:3772.37-3772.102" - wire $and$ls180.v:3772$199_Y - attribute \src "ls180.v:3772.108-3772.188" - wire $and$ls180.v:3772$201_Y - attribute \src "ls180.v:3772.107-3772.231" - wire $and$ls180.v:3772$203_Y - attribute \src "ls180.v:3772.36-3772.232" - wire $and$ls180.v:3772$204_Y - attribute \src "ls180.v:3773.37-3773.102" - wire $and$ls180.v:3773$205_Y - attribute \src "ls180.v:3773.108-3773.188" - wire $and$ls180.v:3773$207_Y - attribute \src "ls180.v:3773.107-3773.231" - wire $and$ls180.v:3773$209_Y - attribute \src "ls180.v:3773.36-3773.232" - wire $and$ls180.v:3773$210_Y - attribute \src "ls180.v:3774.34-3774.85" - wire $and$ls180.v:3774$211_Y - attribute \src "ls180.v:3775.37-3775.102" - wire $and$ls180.v:3775$212_Y - attribute \src "ls180.v:3775.36-3775.194" - wire $and$ls180.v:3775$214_Y - attribute \src "ls180.v:3777.37-3777.102" - wire $and$ls180.v:3777$215_Y - attribute \src "ls180.v:3777.36-3777.148" - wire $and$ls180.v:3777$216_Y - attribute \src "ls180.v:3778.40-3778.119" - wire $and$ls180.v:3778$217_Y - attribute \src "ls180.v:3778.124-3778.203" - wire $and$ls180.v:3778$218_Y - attribute \src "ls180.v:3778.209-3778.288" - wire $and$ls180.v:3778$220_Y - attribute \src "ls180.v:3778.294-3778.373" - wire $and$ls180.v:3778$222_Y - attribute \src "ls180.v:3779.41-3779.121" - wire $and$ls180.v:3779$224_Y - attribute \src "ls180.v:3779.126-3779.206" - wire $and$ls180.v:3779$225_Y - attribute \src "ls180.v:3779.212-3779.292" - wire $and$ls180.v:3779$227_Y - attribute \src "ls180.v:3779.298-3779.378" - wire $and$ls180.v:3779$229_Y - attribute \src "ls180.v:3786.38-3786.111" - wire $and$ls180.v:3786$233_Y - attribute \src "ls180.v:3786.37-3786.150" - wire $and$ls180.v:3786$234_Y - attribute \src "ls180.v:3786.36-3786.189" - wire $and$ls180.v:3786$235_Y - attribute \src "ls180.v:3792.77-3792.153" - wire $and$ls180.v:3792$238_Y - attribute \src "ls180.v:3792.162-3792.246" - wire $and$ls180.v:3792$240_Y - attribute \src "ls180.v:3792.161-3792.291" - wire $and$ls180.v:3792$242_Y - attribute \src "ls180.v:3792.76-3792.333" - wire $and$ls180.v:3792$245_Y - attribute \src "ls180.v:3792.338-3792.505" - wire $and$ls180.v:3792$248_Y - attribute \src "ls180.v:3792.38-3792.507" - wire $and$ls180.v:3792$250_Y - attribute \src "ls180.v:3793.77-3793.153" - wire $and$ls180.v:3793$251_Y - attribute \src "ls180.v:3793.162-3793.246" - wire $and$ls180.v:3793$253_Y - attribute \src "ls180.v:3793.161-3793.291" - wire $and$ls180.v:3793$255_Y - attribute \src "ls180.v:3793.76-3793.333" - wire $and$ls180.v:3793$258_Y - attribute \src "ls180.v:3793.338-3793.505" - wire $and$ls180.v:3793$261_Y - attribute \src "ls180.v:3793.38-3793.507" - wire $and$ls180.v:3793$263_Y - attribute \src "ls180.v:3794.77-3794.153" - wire $and$ls180.v:3794$264_Y - attribute \src "ls180.v:3794.162-3794.246" - wire $and$ls180.v:3794$266_Y - attribute \src "ls180.v:3794.161-3794.291" - wire $and$ls180.v:3794$268_Y - attribute \src "ls180.v:3794.76-3794.333" - wire $and$ls180.v:3794$271_Y - attribute \src "ls180.v:3794.338-3794.505" - wire $and$ls180.v:3794$274_Y - attribute \src "ls180.v:3794.38-3794.507" - wire $and$ls180.v:3794$276_Y - attribute \src "ls180.v:3795.77-3795.153" - wire $and$ls180.v:3795$277_Y - attribute \src "ls180.v:3795.162-3795.246" - wire $and$ls180.v:3795$279_Y - attribute \src "ls180.v:3795.161-3795.291" - wire $and$ls180.v:3795$281_Y - attribute \src "ls180.v:3795.76-3795.333" - wire $and$ls180.v:3795$284_Y - attribute \src "ls180.v:3795.338-3795.505" - wire $and$ls180.v:3795$287_Y - attribute \src "ls180.v:3795.38-3795.507" - wire $and$ls180.v:3795$289_Y - attribute \src "ls180.v:3825.77-3825.153" - wire $and$ls180.v:3825$296_Y - attribute \src "ls180.v:3825.162-3825.246" - wire $and$ls180.v:3825$298_Y - attribute \src "ls180.v:3825.161-3825.291" - wire $and$ls180.v:3825$300_Y - attribute \src "ls180.v:3825.76-3825.333" - wire $and$ls180.v:3825$303_Y - attribute \src "ls180.v:3825.338-3825.505" - wire $and$ls180.v:3825$306_Y - attribute \src "ls180.v:3825.38-3825.507" - wire $and$ls180.v:3825$308_Y - attribute \src "ls180.v:3826.77-3826.153" - wire $and$ls180.v:3826$309_Y - attribute \src "ls180.v:3826.162-3826.246" - wire $and$ls180.v:3826$311_Y - attribute \src "ls180.v:3826.161-3826.291" - wire $and$ls180.v:3826$313_Y - attribute \src "ls180.v:3826.76-3826.333" - wire $and$ls180.v:3826$316_Y - attribute \src "ls180.v:3826.338-3826.505" - wire $and$ls180.v:3826$319_Y - attribute \src "ls180.v:3826.38-3826.507" - wire $and$ls180.v:3826$321_Y - attribute \src "ls180.v:3827.77-3827.153" - wire $and$ls180.v:3827$322_Y - attribute \src "ls180.v:3827.162-3827.246" - wire $and$ls180.v:3827$324_Y - attribute \src "ls180.v:3827.161-3827.291" - wire $and$ls180.v:3827$326_Y - attribute \src "ls180.v:3827.76-3827.333" - wire $and$ls180.v:3827$329_Y - attribute \src "ls180.v:3827.338-3827.505" - wire $and$ls180.v:3827$332_Y - attribute \src "ls180.v:3827.38-3827.507" - wire $and$ls180.v:3827$334_Y - attribute \src "ls180.v:3828.77-3828.153" - wire $and$ls180.v:3828$335_Y - attribute \src "ls180.v:3828.162-3828.246" - wire $and$ls180.v:3828$337_Y - attribute \src "ls180.v:3828.161-3828.291" - wire $and$ls180.v:3828$339_Y - attribute \src "ls180.v:3828.76-3828.333" - wire $and$ls180.v:3828$342_Y - attribute \src "ls180.v:3828.338-3828.505" - wire $and$ls180.v:3828$345_Y - attribute \src "ls180.v:3828.38-3828.507" - wire $and$ls180.v:3828$347_Y - attribute \src "ls180.v:3857.8-3857.73" - wire $and$ls180.v:3857$352_Y - attribute \src "ls180.v:3857.7-3857.114" - wire $and$ls180.v:3857$354_Y - attribute \src "ls180.v:3860.8-3860.73" - wire $and$ls180.v:3860$355_Y - attribute \src "ls180.v:3860.7-3860.114" - wire $and$ls180.v:3860$357_Y - attribute \src "ls180.v:3866.8-3866.73" - wire $and$ls180.v:3866$359_Y - attribute \src "ls180.v:3866.7-3866.114" - wire $and$ls180.v:3866$361_Y - attribute \src "ls180.v:3869.8-3869.73" - wire $and$ls180.v:3869$362_Y - attribute \src "ls180.v:3869.7-3869.114" - wire $and$ls180.v:3869$364_Y - attribute \src "ls180.v:3875.8-3875.73" - wire $and$ls180.v:3875$366_Y - attribute \src "ls180.v:3875.7-3875.114" - wire $and$ls180.v:3875$368_Y - attribute \src "ls180.v:3878.8-3878.73" - wire $and$ls180.v:3878$369_Y - attribute \src "ls180.v:3878.7-3878.114" - wire $and$ls180.v:3878$371_Y - attribute \src "ls180.v:3884.8-3884.73" - wire $and$ls180.v:3884$373_Y - attribute \src "ls180.v:3884.7-3884.114" - wire $and$ls180.v:3884$375_Y - attribute \src "ls180.v:3887.8-3887.73" - wire $and$ls180.v:3887$376_Y - attribute \src "ls180.v:3887.7-3887.114" - wire $and$ls180.v:3887$378_Y - attribute \src "ls180.v:3912.71-3912.151" - wire $and$ls180.v:3912$383_Y - attribute \src "ls180.v:3912.70-3912.194" - wire $and$ls180.v:3912$385_Y - attribute \src "ls180.v:3912.41-3912.222" - wire $and$ls180.v:3912$388_Y - attribute \src "ls180.v:3950.71-3950.151" - wire $and$ls180.v:3950$392_Y - attribute \src "ls180.v:3950.70-3950.194" - wire $and$ls180.v:3950$394_Y - attribute \src "ls180.v:3950.41-3950.222" - wire $and$ls180.v:3950$397_Y - attribute \src "ls180.v:3968.110-3968.179" - wire $and$ls180.v:3968$402_Y - attribute \src "ls180.v:3968.185-3968.254" - wire $and$ls180.v:3968$405_Y - attribute \src "ls180.v:3968.260-3968.329" - wire $and$ls180.v:3968$408_Y - attribute \src "ls180.v:3968.41-3968.332" - wire $and$ls180.v:3968$411_Y - attribute \src "ls180.v:3968.40-3968.355" - wire $and$ls180.v:3968$412_Y - attribute \src "ls180.v:3969.34-3969.106" - wire $and$ls180.v:3969$415_Y - attribute \src "ls180.v:3973.110-3973.179" - wire $and$ls180.v:3973$418_Y - attribute \src "ls180.v:3973.185-3973.254" - wire $and$ls180.v:3973$421_Y - attribute \src "ls180.v:3973.260-3973.329" - wire $and$ls180.v:3973$424_Y - attribute \src "ls180.v:3973.41-3973.332" - wire $and$ls180.v:3973$427_Y - attribute \src "ls180.v:3973.40-3973.355" - wire $and$ls180.v:3973$428_Y - attribute \src "ls180.v:3974.34-3974.106" - wire $and$ls180.v:3974$431_Y - attribute \src "ls180.v:3978.110-3978.179" - wire $and$ls180.v:3978$434_Y - attribute \src "ls180.v:3978.185-3978.254" - wire $and$ls180.v:3978$437_Y - attribute \src "ls180.v:3978.260-3978.329" - wire $and$ls180.v:3978$440_Y - attribute \src "ls180.v:3978.41-3978.332" - wire $and$ls180.v:3978$443_Y - attribute \src "ls180.v:3978.40-3978.355" - wire $and$ls180.v:3978$444_Y - attribute \src "ls180.v:3979.34-3979.106" - wire $and$ls180.v:3979$447_Y - attribute \src "ls180.v:3983.110-3983.179" - wire $and$ls180.v:3983$450_Y - attribute \src "ls180.v:3983.185-3983.254" - wire $and$ls180.v:3983$453_Y - attribute \src "ls180.v:3983.260-3983.329" - wire $and$ls180.v:3983$456_Y - attribute \src "ls180.v:3983.41-3983.332" - wire $and$ls180.v:3983$459_Y - attribute \src "ls180.v:3983.40-3983.355" - wire $and$ls180.v:3983$460_Y - attribute \src "ls180.v:3984.34-3984.106" - wire $and$ls180.v:3984$463_Y - attribute \src "ls180.v:3988.151-3988.220" - wire $and$ls180.v:3988$467_Y - attribute \src "ls180.v:3988.226-3988.295" - wire $and$ls180.v:3988$470_Y - attribute \src "ls180.v:3988.301-3988.370" - wire $and$ls180.v:3988$473_Y - attribute \src "ls180.v:3988.82-3988.373" - wire $and$ls180.v:3988$476_Y - attribute \src "ls180.v:3988.43-3988.374" - wire $and$ls180.v:3988$477_Y - attribute \src "ls180.v:3988.42-3988.410" - wire $and$ls180.v:3988$478_Y - attribute \src "ls180.v:3988.525-3988.594" - wire $and$ls180.v:3988$483_Y - attribute \src "ls180.v:3988.600-3988.669" - wire $and$ls180.v:3988$486_Y - attribute \src "ls180.v:3988.675-3988.744" - wire $and$ls180.v:3988$489_Y - attribute \src "ls180.v:3988.456-3988.747" - wire $and$ls180.v:3988$492_Y - attribute \src "ls180.v:3988.417-3988.748" - wire $and$ls180.v:3988$493_Y - attribute \src "ls180.v:3988.416-3988.784" - wire $and$ls180.v:3988$494_Y - attribute \src "ls180.v:3988.899-3988.968" - wire $and$ls180.v:3988$499_Y - attribute \src "ls180.v:3988.974-3988.1043" - wire $and$ls180.v:3988$502_Y - attribute \src "ls180.v:3988.1049-3988.1118" - wire $and$ls180.v:3988$505_Y - attribute \src "ls180.v:3988.830-3988.1121" - wire $and$ls180.v:3988$508_Y - attribute \src "ls180.v:3988.791-3988.1122" - wire $and$ls180.v:3988$509_Y - attribute \src "ls180.v:3988.790-3988.1158" - wire $and$ls180.v:3988$510_Y - attribute \src "ls180.v:3988.1273-3988.1342" - wire $and$ls180.v:3988$515_Y - attribute \src "ls180.v:3988.1348-3988.1417" - wire $and$ls180.v:3988$518_Y - attribute \src "ls180.v:3988.1423-3988.1492" - wire $and$ls180.v:3988$521_Y - attribute \src "ls180.v:3988.1204-3988.1495" - wire $and$ls180.v:3988$524_Y - attribute \src "ls180.v:3988.1165-3988.1496" - wire $and$ls180.v:3988$525_Y - attribute \src "ls180.v:3988.1164-3988.1532" - wire $and$ls180.v:3988$526_Y - attribute \src "ls180.v:4046.9-4046.46" - wire $and$ls180.v:4046$532_Y - attribute \src "ls180.v:4064.9-4064.46" - wire $and$ls180.v:4064$539_Y - attribute \src "ls180.v:4077.32-4077.75" - wire $and$ls180.v:4077$543_Y - attribute \src "ls180.v:4077.31-4077.99" - wire $and$ls180.v:4077$545_Y - attribute \src "ls180.v:4078.34-4078.102" - wire $and$ls180.v:4078$547_Y - attribute \src "ls180.v:4078.33-4078.128" - wire $and$ls180.v:4078$549_Y - attribute \src "ls180.v:4079.33-4079.104" - wire $and$ls180.v:4079$552_Y - attribute \src "ls180.v:4080.49-4080.85" - wire $and$ls180.v:4080$553_Y - attribute \src "ls180.v:4080.90-4080.129" - wire $and$ls180.v:4080$555_Y - attribute \src "ls180.v:4080.32-4080.131" - wire $and$ls180.v:4080$557_Y - attribute \src "ls180.v:4081.25-4081.66" - wire $and$ls180.v:4081$558_Y - attribute \src "ls180.v:4082.27-4082.72" - wire $and$ls180.v:4082$560_Y - attribute \src "ls180.v:4083.26-4083.71" - wire $and$ls180.v:4083$562_Y - attribute \src "ls180.v:4112.64-4112.88" - wire $and$ls180.v:4112$568_Y - attribute \src "ls180.v:4116.7-4116.78" - wire $and$ls180.v:4116$572_Y - attribute \src "ls180.v:4127.7-4127.78" - wire $and$ls180.v:4127$575_Y - attribute \src "ls180.v:4136.26-4136.97" - wire $and$ls180.v:4136$577_Y - attribute \src "ls180.v:4136.102-4136.173" - wire $and$ls180.v:4136$578_Y - attribute \src "ls180.v:4151.41-4151.133" - wire $and$ls180.v:4151$582_Y - attribute \src "ls180.v:4162.39-4162.136" - wire $and$ls180.v:4162$587_Y - attribute \src "ls180.v:4163.37-4163.104" - wire $and$ls180.v:4163$588_Y - attribute \src "ls180.v:4181.41-4181.133" - wire $and$ls180.v:4181$593_Y - attribute \src "ls180.v:4192.39-4192.136" - wire $and$ls180.v:4192$598_Y - attribute \src "ls180.v:4193.37-4193.104" - wire $and$ls180.v:4193$599_Y - attribute \src "ls180.v:4322.33-4322.86" - wire $and$ls180.v:4322$633_Y - attribute \src "ls180.v:4426.9-4426.68" - wire $and$ls180.v:4426$642_Y - attribute \src "ls180.v:4446.53-4446.145" - wire $and$ls180.v:4446$645_Y - attribute \src "ls180.v:4465.52-4465.137" - wire $and$ls180.v:4465$648_Y - attribute \src "ls180.v:4506.9-4506.68" - wire $and$ls180.v:4506$656_Y - attribute \src "ls180.v:4544.9-4544.68" - wire $and$ls180.v:4544$662_Y - attribute \src "ls180.v:4553.10-4553.69" - wire $and$ls180.v:4553$663_Y - attribute \src "ls180.v:4553.9-4553.93" - wire $and$ls180.v:4553$664_Y - attribute \src "ls180.v:4573.54-4573.117" - wire $and$ls180.v:4573$666_Y - attribute \src "ls180.v:4592.53-4592.140" - wire $and$ls180.v:4592$669_Y - attribute \src "ls180.v:4689.9-4689.70" - wire $and$ls180.v:4689$679_Y - attribute \src "ls180.v:4707.55-4707.120" - wire $and$ls180.v:4707$681_Y - attribute \src "ls180.v:4726.54-4726.143" - wire $and$ls180.v:4726$684_Y - attribute \src "ls180.v:4808.9-4808.70" - wire $and$ls180.v:4808$699_Y - attribute \src "ls180.v:4815.9-4815.70" - wire $and$ls180.v:4815$700_Y - attribute \src "ls180.v:4896.48-4896.124" - wire $and$ls180.v:4896$823_Y - attribute \src "ls180.v:4896.47-4896.165" - wire $and$ls180.v:4896$824_Y - attribute \src "ls180.v:4897.50-4897.127" - wire $and$ls180.v:4897$825_Y - attribute \src "ls180.v:4899.48-4899.124" - wire $and$ls180.v:4899$826_Y - attribute \src "ls180.v:4899.47-4899.165" - wire $and$ls180.v:4899$827_Y - attribute \src "ls180.v:4900.50-4900.127" - wire $and$ls180.v:4900$828_Y - attribute \src "ls180.v:4902.48-4902.124" - wire $and$ls180.v:4902$829_Y - attribute \src "ls180.v:4902.47-4902.165" - wire $and$ls180.v:4902$830_Y - attribute \src "ls180.v:4903.50-4903.127" - wire $and$ls180.v:4903$831_Y - attribute \src "ls180.v:4905.48-4905.124" - wire $and$ls180.v:4905$832_Y - attribute \src "ls180.v:4905.47-4905.165" - wire $and$ls180.v:4905$833_Y - attribute \src "ls180.v:4906.50-4906.127" - wire $and$ls180.v:4906$834_Y - attribute \src "ls180.v:5019.10-5019.86" - wire $and$ls180.v:5019$883_Y - attribute \src "ls180.v:5019.9-5019.127" - wire $and$ls180.v:5019$884_Y - attribute \src "ls180.v:5029.9-5029.152" - wire $and$ls180.v:5029$888_Y - attribute \src "ls180.v:5029.8-5029.226" - wire $and$ls180.v:5029$890_Y - attribute \src "ls180.v:5029.7-5029.300" - wire $and$ls180.v:5029$892_Y - attribute \src "ls180.v:5034.49-5034.124" - wire $and$ls180.v:5034$893_Y - attribute \src "ls180.v:5044.49-5044.124" - wire $and$ls180.v:5044$896_Y - attribute \src "ls180.v:5054.49-5054.124" - wire $and$ls180.v:5054$899_Y - attribute \src "ls180.v:5064.49-5064.124" - wire $and$ls180.v:5064$902_Y - attribute \src "ls180.v:5076.7-5076.84" - wire $and$ls180.v:5076$907_Y - attribute \src "ls180.v:5194.9-5194.64" - wire $and$ls180.v:5194$956_Y - attribute \src "ls180.v:5246.10-5246.66" - wire $and$ls180.v:5246$965_Y - attribute \src "ls180.v:5246.9-5246.97" - wire $and$ls180.v:5246$966_Y - attribute \src "ls180.v:5272.11-5272.71" - wire $and$ls180.v:5272$974_Y - attribute \src "ls180.v:5356.43-5356.152" - wire $and$ls180.v:5356$982_Y - attribute \src "ls180.v:5357.41-5357.116" - wire $and$ls180.v:5357$983_Y - attribute \src "ls180.v:5369.48-5369.125" - wire $and$ls180.v:5369$988_Y - attribute \src "ls180.v:5396.9-5396.102" - wire $and$ls180.v:5396$992_Y - attribute \src "ls180.v:5469.9-5469.58" - wire $and$ls180.v:5469$998_Y - attribute \src "ls180.v:5522.51-5522.123" - wire $and$ls180.v:5522$1006_Y - attribute \src "ls180.v:5523.50-5523.120" - wire $and$ls180.v:5523$1007_Y - attribute \src "ls180.v:5524.49-5524.122" - wire $and$ls180.v:5524$1008_Y - attribute \src "ls180.v:5564.43-5564.152" - wire $and$ls180.v:5564$1013_Y - attribute \src "ls180.v:5565.41-5565.116" - wire $and$ls180.v:5565$1014_Y - attribute \src "ls180.v:5656.9-5656.76" - wire $and$ls180.v:5656$1026_Y - attribute \src "ls180.v:5659.44-5659.120" - wire $and$ls180.v:5659$1028_Y - attribute \src "ls180.v:5679.63-5679.107" - wire $and$ls180.v:5679$1030_Y - attribute \src "ls180.v:5680.63-5680.107" - wire $and$ls180.v:5680$1032_Y - attribute \src "ls180.v:5681.63-5681.107" - wire $and$ls180.v:5681$1034_Y - attribute \src "ls180.v:5682.35-5682.79" - wire $and$ls180.v:5682$1036_Y - attribute \src "ls180.v:5683.35-5683.79" - wire $and$ls180.v:5683$1038_Y - attribute \src "ls180.v:5684.63-5684.107" - wire $and$ls180.v:5684$1040_Y - attribute \src "ls180.v:5685.63-5685.107" - wire $and$ls180.v:5685$1042_Y - attribute \src "ls180.v:5686.63-5686.107" - wire $and$ls180.v:5686$1044_Y - attribute \src "ls180.v:5687.35-5687.79" - wire $and$ls180.v:5687$1046_Y - attribute \src "ls180.v:5688.35-5688.79" - wire $and$ls180.v:5688$1048_Y - attribute \src "ls180.v:5733.40-5733.81" - wire $and$ls180.v:5733$1055_Y - attribute \src "ls180.v:5734.50-5734.91" - wire $and$ls180.v:5734$1056_Y - attribute \src "ls180.v:5735.50-5735.91" - wire $and$ls180.v:5735$1057_Y - attribute \src "ls180.v:5736.29-5736.70" - wire $and$ls180.v:5736$1058_Y - attribute \src "ls180.v:5737.44-5737.85" - wire $and$ls180.v:5737$1059_Y - attribute \src "ls180.v:5739.25-5739.64" - wire $and$ls180.v:5739$1064_Y - attribute \src "ls180.v:5739.24-5739.89" - wire $and$ls180.v:5739$1066_Y - attribute \src "ls180.v:5745.31-5745.92" - wire width 32 $and$ls180.v:5745$1072_Y - attribute \src "ls180.v:5745.97-5745.168" - wire width 32 $and$ls180.v:5745$1073_Y - attribute \src "ls180.v:5745.174-5745.245" - wire width 32 $and$ls180.v:5745$1075_Y - attribute \src "ls180.v:5745.251-5745.301" - wire width 32 $and$ls180.v:5745$1077_Y - attribute \src "ls180.v:5745.307-5745.372" - wire width 32 $and$ls180.v:5745$1079_Y - attribute \src "ls180.v:5755.39-5755.92" - wire $and$ls180.v:5755$1083_Y - attribute \src "ls180.v:5755.38-5755.142" - wire $and$ls180.v:5755$1085_Y - attribute \src "ls180.v:5756.39-5756.95" - wire $and$ls180.v:5756$1087_Y - attribute \src "ls180.v:5756.38-5756.145" - wire $and$ls180.v:5756$1089_Y - attribute \src "ls180.v:5758.41-5758.94" - wire $and$ls180.v:5758$1090_Y - attribute \src "ls180.v:5758.40-5758.144" - wire $and$ls180.v:5758$1092_Y - attribute \src "ls180.v:5759.41-5759.97" - wire $and$ls180.v:5759$1094_Y - attribute \src "ls180.v:5759.40-5759.147" - wire $and$ls180.v:5759$1096_Y - attribute \src "ls180.v:5761.41-5761.94" - wire $and$ls180.v:5761$1097_Y - attribute \src "ls180.v:5761.40-5761.144" - wire $and$ls180.v:5761$1099_Y - attribute \src "ls180.v:5762.41-5762.97" - wire $and$ls180.v:5762$1101_Y - attribute \src "ls180.v:5762.40-5762.147" - wire $and$ls180.v:5762$1103_Y - attribute \src "ls180.v:5764.41-5764.94" - wire $and$ls180.v:5764$1104_Y - attribute \src "ls180.v:5764.40-5764.144" - wire $and$ls180.v:5764$1106_Y - attribute \src "ls180.v:5765.41-5765.97" - wire $and$ls180.v:5765$1108_Y - attribute \src "ls180.v:5765.40-5765.147" - wire $and$ls180.v:5765$1110_Y - attribute \src "ls180.v:5767.41-5767.94" - wire $and$ls180.v:5767$1111_Y - attribute \src "ls180.v:5767.40-5767.144" - wire $and$ls180.v:5767$1113_Y - attribute \src "ls180.v:5768.41-5768.97" - wire $and$ls180.v:5768$1115_Y - attribute \src "ls180.v:5768.40-5768.147" - wire $and$ls180.v:5768$1117_Y - attribute \src "ls180.v:5770.44-5770.97" - wire $and$ls180.v:5770$1118_Y - attribute \src "ls180.v:5770.43-5770.147" - wire $and$ls180.v:5770$1120_Y - attribute \src "ls180.v:5771.44-5771.100" - wire $and$ls180.v:5771$1122_Y - attribute \src "ls180.v:5771.43-5771.150" - wire $and$ls180.v:5771$1124_Y - attribute \src "ls180.v:5773.44-5773.97" - wire $and$ls180.v:5773$1125_Y - attribute \src "ls180.v:5773.43-5773.147" - wire $and$ls180.v:5773$1127_Y - attribute \src "ls180.v:5774.44-5774.100" - wire $and$ls180.v:5774$1129_Y - attribute \src "ls180.v:5774.43-5774.150" - wire $and$ls180.v:5774$1131_Y - attribute \src "ls180.v:5776.44-5776.97" - wire $and$ls180.v:5776$1132_Y - attribute \src "ls180.v:5776.43-5776.147" - wire $and$ls180.v:5776$1134_Y - attribute \src "ls180.v:5777.44-5777.100" - wire $and$ls180.v:5777$1136_Y - attribute \src "ls180.v:5777.43-5777.150" - wire $and$ls180.v:5777$1138_Y - attribute \src "ls180.v:5779.44-5779.97" - wire $and$ls180.v:5779$1139_Y - attribute \src "ls180.v:5779.43-5779.147" - wire $and$ls180.v:5779$1141_Y - attribute \src "ls180.v:5780.44-5780.100" - wire $and$ls180.v:5780$1143_Y - attribute \src "ls180.v:5780.43-5780.150" - wire $and$ls180.v:5780$1145_Y - attribute \src "ls180.v:5793.36-5793.89" - wire $and$ls180.v:5793$1147_Y - attribute \src "ls180.v:5793.35-5793.139" - wire $and$ls180.v:5793$1149_Y - attribute \src "ls180.v:5794.36-5794.92" - wire $and$ls180.v:5794$1151_Y - attribute \src "ls180.v:5794.35-5794.142" - wire $and$ls180.v:5794$1153_Y - attribute \src "ls180.v:5796.36-5796.89" - wire $and$ls180.v:5796$1154_Y - attribute \src "ls180.v:5796.35-5796.139" - wire $and$ls180.v:5796$1156_Y - attribute \src "ls180.v:5797.36-5797.92" - wire $and$ls180.v:5797$1158_Y - attribute \src "ls180.v:5797.35-5797.142" - wire $and$ls180.v:5797$1160_Y - attribute \src "ls180.v:5799.36-5799.89" - wire $and$ls180.v:5799$1161_Y - attribute \src "ls180.v:5799.35-5799.139" - wire $and$ls180.v:5799$1163_Y - attribute \src "ls180.v:5800.36-5800.92" - wire $and$ls180.v:5800$1165_Y - attribute \src "ls180.v:5800.35-5800.142" - wire $and$ls180.v:5800$1167_Y - attribute \src "ls180.v:5802.36-5802.89" - wire $and$ls180.v:5802$1168_Y - attribute \src "ls180.v:5802.35-5802.139" - wire $and$ls180.v:5802$1170_Y - attribute \src "ls180.v:5803.36-5803.92" - wire $and$ls180.v:5803$1172_Y - attribute \src "ls180.v:5803.35-5803.142" - wire $and$ls180.v:5803$1174_Y - attribute \src "ls180.v:5805.37-5805.90" - wire $and$ls180.v:5805$1175_Y - attribute \src "ls180.v:5805.36-5805.140" - wire $and$ls180.v:5805$1177_Y - attribute \src "ls180.v:5806.37-5806.93" - wire $and$ls180.v:5806$1179_Y - attribute \src "ls180.v:5806.36-5806.143" - wire $and$ls180.v:5806$1181_Y - attribute \src "ls180.v:5808.37-5808.90" - wire $and$ls180.v:5808$1182_Y - attribute \src "ls180.v:5808.36-5808.140" - wire $and$ls180.v:5808$1184_Y - attribute \src "ls180.v:5809.37-5809.93" - wire $and$ls180.v:5809$1186_Y - attribute \src "ls180.v:5809.36-5809.143" - wire $and$ls180.v:5809$1188_Y - attribute \src "ls180.v:5819.35-5819.88" - wire $and$ls180.v:5819$1190_Y - attribute \src "ls180.v:5819.34-5819.136" - wire $and$ls180.v:5819$1192_Y - attribute \src "ls180.v:5820.35-5820.91" - wire $and$ls180.v:5820$1194_Y - attribute \src "ls180.v:5820.34-5820.139" - wire $and$ls180.v:5820$1196_Y - attribute \src "ls180.v:5822.34-5822.87" - wire $and$ls180.v:5822$1197_Y - attribute \src "ls180.v:5822.33-5822.135" - wire $and$ls180.v:5822$1199_Y - attribute \src "ls180.v:5823.34-5823.90" - wire $and$ls180.v:5823$1201_Y - attribute \src "ls180.v:5823.33-5823.138" - wire $and$ls180.v:5823$1203_Y - attribute \src "ls180.v:5833.40-5833.93" - wire $and$ls180.v:5833$1205_Y - attribute \src "ls180.v:5833.39-5833.143" - wire $and$ls180.v:5833$1207_Y - attribute \src "ls180.v:5834.40-5834.96" - wire $and$ls180.v:5834$1209_Y - attribute \src "ls180.v:5834.39-5834.146" - wire $and$ls180.v:5834$1211_Y - attribute \src "ls180.v:5836.39-5836.92" - wire $and$ls180.v:5836$1212_Y - attribute \src "ls180.v:5836.38-5836.142" - wire $and$ls180.v:5836$1214_Y - attribute \src "ls180.v:5837.39-5837.95" - wire $and$ls180.v:5837$1216_Y - attribute \src "ls180.v:5837.38-5837.145" - wire $and$ls180.v:5837$1218_Y - attribute \src "ls180.v:5839.39-5839.92" - wire $and$ls180.v:5839$1219_Y - attribute \src "ls180.v:5839.38-5839.142" - wire $and$ls180.v:5839$1221_Y - attribute \src "ls180.v:5840.39-5840.95" - wire $and$ls180.v:5840$1223_Y - attribute \src "ls180.v:5840.38-5840.145" - wire $and$ls180.v:5840$1225_Y - attribute \src "ls180.v:5842.39-5842.92" - wire $and$ls180.v:5842$1226_Y - attribute \src "ls180.v:5842.38-5842.142" - wire $and$ls180.v:5842$1228_Y - attribute \src "ls180.v:5843.39-5843.95" - wire $and$ls180.v:5843$1230_Y - attribute \src "ls180.v:5843.38-5843.145" - wire $and$ls180.v:5843$1232_Y - attribute \src "ls180.v:5845.39-5845.92" - wire $and$ls180.v:5845$1233_Y - attribute \src "ls180.v:5845.38-5845.142" - wire $and$ls180.v:5845$1235_Y - attribute \src "ls180.v:5846.39-5846.95" - wire $and$ls180.v:5846$1237_Y - attribute \src "ls180.v:5846.38-5846.145" - wire $and$ls180.v:5846$1239_Y - attribute \src "ls180.v:5848.40-5848.93" - wire $and$ls180.v:5848$1240_Y - attribute \src "ls180.v:5848.39-5848.143" - wire $and$ls180.v:5848$1242_Y - attribute \src "ls180.v:5849.40-5849.96" - wire $and$ls180.v:5849$1244_Y - attribute \src "ls180.v:5849.39-5849.146" - wire $and$ls180.v:5849$1246_Y - attribute \src "ls180.v:5851.40-5851.93" - wire $and$ls180.v:5851$1247_Y - attribute \src "ls180.v:5851.39-5851.143" - wire $and$ls180.v:5851$1249_Y - attribute \src "ls180.v:5852.40-5852.96" - wire $and$ls180.v:5852$1251_Y - attribute \src "ls180.v:5852.39-5852.146" - wire $and$ls180.v:5852$1253_Y - attribute \src "ls180.v:5854.40-5854.93" - wire $and$ls180.v:5854$1254_Y - attribute \src "ls180.v:5854.39-5854.143" - wire $and$ls180.v:5854$1256_Y - attribute \src "ls180.v:5855.40-5855.96" - wire $and$ls180.v:5855$1258_Y - attribute \src "ls180.v:5855.39-5855.146" - wire $and$ls180.v:5855$1260_Y - attribute \src "ls180.v:5857.40-5857.93" - wire $and$ls180.v:5857$1261_Y - attribute \src "ls180.v:5857.39-5857.143" - wire $and$ls180.v:5857$1263_Y - attribute \src "ls180.v:5858.40-5858.96" - wire $and$ls180.v:5858$1265_Y - attribute \src "ls180.v:5858.39-5858.146" - wire $and$ls180.v:5858$1267_Y - attribute \src "ls180.v:5870.40-5870.93" - wire $and$ls180.v:5870$1269_Y - attribute \src "ls180.v:5870.39-5870.143" - wire $and$ls180.v:5870$1271_Y - attribute \src "ls180.v:5871.40-5871.96" - wire $and$ls180.v:5871$1273_Y - attribute \src "ls180.v:5871.39-5871.146" - wire $and$ls180.v:5871$1275_Y - attribute \src "ls180.v:5873.39-5873.92" - wire $and$ls180.v:5873$1276_Y - attribute \src "ls180.v:5873.38-5873.142" - wire $and$ls180.v:5873$1278_Y - attribute \src "ls180.v:5874.39-5874.95" - wire $and$ls180.v:5874$1280_Y - attribute \src "ls180.v:5874.38-5874.145" - wire $and$ls180.v:5874$1282_Y - attribute \src "ls180.v:5876.39-5876.92" - wire $and$ls180.v:5876$1283_Y - attribute \src "ls180.v:5876.38-5876.142" - wire $and$ls180.v:5876$1285_Y - attribute \src "ls180.v:5877.39-5877.95" - wire $and$ls180.v:5877$1287_Y - attribute \src "ls180.v:5877.38-5877.145" - wire $and$ls180.v:5877$1289_Y - attribute \src "ls180.v:5879.39-5879.92" - wire $and$ls180.v:5879$1290_Y - attribute \src "ls180.v:5879.38-5879.142" - wire $and$ls180.v:5879$1292_Y - attribute \src "ls180.v:5880.39-5880.95" - wire $and$ls180.v:5880$1294_Y - attribute \src "ls180.v:5880.38-5880.145" - wire $and$ls180.v:5880$1296_Y - attribute \src "ls180.v:5882.39-5882.92" - wire $and$ls180.v:5882$1297_Y - attribute \src "ls180.v:5882.38-5882.142" - wire $and$ls180.v:5882$1299_Y - attribute \src "ls180.v:5883.39-5883.95" - wire $and$ls180.v:5883$1301_Y - attribute \src "ls180.v:5883.38-5883.145" - wire $and$ls180.v:5883$1303_Y - attribute \src "ls180.v:5885.40-5885.93" - wire $and$ls180.v:5885$1304_Y - attribute \src "ls180.v:5885.39-5885.143" - wire $and$ls180.v:5885$1306_Y - attribute \src "ls180.v:5886.40-5886.96" - wire $and$ls180.v:5886$1308_Y - attribute \src "ls180.v:5886.39-5886.146" - wire $and$ls180.v:5886$1310_Y - attribute \src "ls180.v:5888.40-5888.93" - wire $and$ls180.v:5888$1311_Y - attribute \src "ls180.v:5888.39-5888.143" - wire $and$ls180.v:5888$1313_Y - attribute \src "ls180.v:5889.40-5889.96" - wire $and$ls180.v:5889$1315_Y - attribute \src "ls180.v:5889.39-5889.146" - wire $and$ls180.v:5889$1317_Y - attribute \src "ls180.v:5891.40-5891.93" - wire $and$ls180.v:5891$1318_Y - attribute \src "ls180.v:5891.39-5891.143" - wire $and$ls180.v:5891$1320_Y - attribute \src "ls180.v:5892.40-5892.96" - wire $and$ls180.v:5892$1322_Y - attribute \src "ls180.v:5892.39-5892.146" - wire $and$ls180.v:5892$1324_Y - attribute \src "ls180.v:5894.40-5894.93" - wire $and$ls180.v:5894$1325_Y - attribute \src "ls180.v:5894.39-5894.143" - wire $and$ls180.v:5894$1327_Y - attribute \src "ls180.v:5895.40-5895.96" - wire $and$ls180.v:5895$1329_Y - attribute \src "ls180.v:5895.39-5895.146" - wire $and$ls180.v:5895$1331_Y - attribute \src "ls180.v:5907.42-5907.95" - wire $and$ls180.v:5907$1333_Y - attribute \src "ls180.v:5907.41-5907.145" - wire $and$ls180.v:5907$1335_Y - attribute \src "ls180.v:5908.42-5908.98" - wire $and$ls180.v:5908$1337_Y - attribute \src "ls180.v:5908.41-5908.148" - wire $and$ls180.v:5908$1339_Y - attribute \src "ls180.v:5910.42-5910.95" - wire $and$ls180.v:5910$1340_Y - attribute \src "ls180.v:5910.41-5910.145" - wire $and$ls180.v:5910$1342_Y - attribute \src "ls180.v:5911.42-5911.98" - wire $and$ls180.v:5911$1344_Y - attribute \src "ls180.v:5911.41-5911.148" - wire $and$ls180.v:5911$1346_Y - attribute \src "ls180.v:5913.42-5913.95" - wire $and$ls180.v:5913$1347_Y - attribute \src "ls180.v:5913.41-5913.145" - wire $and$ls180.v:5913$1349_Y - attribute \src "ls180.v:5914.42-5914.98" - wire $and$ls180.v:5914$1351_Y - attribute \src "ls180.v:5914.41-5914.148" - wire $and$ls180.v:5914$1353_Y - attribute \src "ls180.v:5916.42-5916.95" - wire $and$ls180.v:5916$1354_Y - attribute \src "ls180.v:5916.41-5916.145" - wire $and$ls180.v:5916$1356_Y - attribute \src "ls180.v:5917.42-5917.98" - wire $and$ls180.v:5917$1358_Y - attribute \src "ls180.v:5917.41-5917.148" - wire $and$ls180.v:5917$1360_Y - attribute \src "ls180.v:5919.42-5919.95" - wire $and$ls180.v:5919$1361_Y - attribute \src "ls180.v:5919.41-5919.145" - wire $and$ls180.v:5919$1363_Y - attribute \src "ls180.v:5920.42-5920.98" - wire $and$ls180.v:5920$1365_Y - attribute \src "ls180.v:5920.41-5920.148" - wire $and$ls180.v:5920$1367_Y - attribute \src "ls180.v:5922.42-5922.95" - wire $and$ls180.v:5922$1368_Y - attribute \src "ls180.v:5922.41-5922.145" - wire $and$ls180.v:5922$1370_Y - attribute \src "ls180.v:5923.42-5923.98" - wire $and$ls180.v:5923$1372_Y - attribute \src "ls180.v:5923.41-5923.148" - wire $and$ls180.v:5923$1374_Y - attribute \src "ls180.v:5925.42-5925.95" - wire $and$ls180.v:5925$1375_Y - attribute \src "ls180.v:5925.41-5925.145" - wire $and$ls180.v:5925$1377_Y - attribute \src "ls180.v:5926.42-5926.98" - wire $and$ls180.v:5926$1379_Y - attribute \src "ls180.v:5926.41-5926.148" - wire $and$ls180.v:5926$1381_Y - attribute \src "ls180.v:5928.42-5928.95" - wire $and$ls180.v:5928$1382_Y - attribute \src "ls180.v:5928.41-5928.145" - wire $and$ls180.v:5928$1384_Y - attribute \src "ls180.v:5929.42-5929.98" - wire $and$ls180.v:5929$1386_Y - attribute \src "ls180.v:5929.41-5929.148" - wire $and$ls180.v:5929$1388_Y - attribute \src "ls180.v:5931.44-5931.97" - wire $and$ls180.v:5931$1389_Y - attribute \src "ls180.v:5931.43-5931.147" - wire $and$ls180.v:5931$1391_Y - attribute \src "ls180.v:5932.44-5932.100" - wire $and$ls180.v:5932$1393_Y - attribute \src "ls180.v:5932.43-5932.150" - wire $and$ls180.v:5932$1395_Y - attribute \src "ls180.v:5934.44-5934.97" - wire $and$ls180.v:5934$1396_Y - attribute \src "ls180.v:5934.43-5934.147" - wire $and$ls180.v:5934$1398_Y - attribute \src "ls180.v:5935.44-5935.100" - wire $and$ls180.v:5935$1400_Y - attribute \src "ls180.v:5935.43-5935.150" - wire $and$ls180.v:5935$1402_Y - attribute \src "ls180.v:5937.44-5937.97" - wire $and$ls180.v:5937$1403_Y - attribute \src "ls180.v:5937.43-5937.148" - wire $and$ls180.v:5937$1405_Y - attribute \src "ls180.v:5938.44-5938.100" - wire $and$ls180.v:5938$1407_Y - attribute \src "ls180.v:5938.43-5938.151" - wire $and$ls180.v:5938$1409_Y - attribute \src "ls180.v:5940.44-5940.97" - wire $and$ls180.v:5940$1410_Y - attribute \src "ls180.v:5940.43-5940.148" - wire $and$ls180.v:5940$1412_Y - attribute \src "ls180.v:5941.44-5941.100" - wire $and$ls180.v:5941$1414_Y - attribute \src "ls180.v:5941.43-5941.151" - wire $and$ls180.v:5941$1416_Y - attribute \src "ls180.v:5943.44-5943.97" - wire $and$ls180.v:5943$1417_Y - attribute \src "ls180.v:5943.43-5943.148" - wire $and$ls180.v:5943$1419_Y - attribute \src "ls180.v:5944.44-5944.100" - wire $and$ls180.v:5944$1421_Y - attribute \src "ls180.v:5944.43-5944.151" - wire $and$ls180.v:5944$1423_Y - attribute \src "ls180.v:5946.41-5946.94" - wire $and$ls180.v:5946$1424_Y - attribute \src "ls180.v:5946.40-5946.145" - wire $and$ls180.v:5946$1426_Y - attribute \src "ls180.v:5947.41-5947.97" - wire $and$ls180.v:5947$1428_Y - attribute \src "ls180.v:5947.40-5947.148" - wire $and$ls180.v:5947$1430_Y - attribute \src "ls180.v:5949.42-5949.95" - wire $and$ls180.v:5949$1431_Y - attribute \src "ls180.v:5949.41-5949.146" - wire $and$ls180.v:5949$1433_Y - attribute \src "ls180.v:5950.42-5950.98" - wire $and$ls180.v:5950$1435_Y - attribute \src "ls180.v:5950.41-5950.149" - wire $and$ls180.v:5950$1437_Y - attribute \src "ls180.v:5969.46-5969.99" - wire $and$ls180.v:5969$1439_Y - attribute \src "ls180.v:5969.45-5969.149" - wire $and$ls180.v:5969$1441_Y - attribute \src "ls180.v:5970.46-5970.102" - wire $and$ls180.v:5970$1443_Y - attribute \src "ls180.v:5970.45-5970.152" - wire $and$ls180.v:5970$1445_Y - attribute \src "ls180.v:5972.46-5972.99" - wire $and$ls180.v:5972$1446_Y - attribute \src "ls180.v:5972.45-5972.149" - wire $and$ls180.v:5972$1448_Y - attribute \src "ls180.v:5973.46-5973.102" - wire $and$ls180.v:5973$1450_Y - attribute \src "ls180.v:5973.45-5973.152" - wire $and$ls180.v:5973$1452_Y - attribute \src "ls180.v:5975.46-5975.99" - wire $and$ls180.v:5975$1453_Y - attribute \src "ls180.v:5975.45-5975.149" - wire $and$ls180.v:5975$1455_Y - attribute \src "ls180.v:5976.46-5976.102" - wire $and$ls180.v:5976$1457_Y - attribute \src "ls180.v:5976.45-5976.152" - wire $and$ls180.v:5976$1459_Y - attribute \src "ls180.v:5978.46-5978.99" - wire $and$ls180.v:5978$1460_Y - attribute \src "ls180.v:5978.45-5978.149" - wire $and$ls180.v:5978$1462_Y - attribute \src "ls180.v:5979.46-5979.102" - wire $and$ls180.v:5979$1464_Y - attribute \src "ls180.v:5979.45-5979.152" - wire $and$ls180.v:5979$1466_Y - attribute \src "ls180.v:5981.45-5981.98" - wire $and$ls180.v:5981$1467_Y - attribute \src "ls180.v:5981.44-5981.148" - wire $and$ls180.v:5981$1469_Y - attribute \src "ls180.v:5982.45-5982.101" - wire $and$ls180.v:5982$1471_Y - attribute \src "ls180.v:5982.44-5982.151" - wire $and$ls180.v:5982$1473_Y - attribute \src "ls180.v:5984.45-5984.98" - wire $and$ls180.v:5984$1474_Y - attribute \src "ls180.v:5984.44-5984.148" - wire $and$ls180.v:5984$1476_Y - attribute \src "ls180.v:5985.45-5985.101" - wire $and$ls180.v:5985$1478_Y - attribute \src "ls180.v:5985.44-5985.151" - wire $and$ls180.v:5985$1480_Y - attribute \src "ls180.v:5987.45-5987.98" - wire $and$ls180.v:5987$1481_Y - attribute \src "ls180.v:5987.44-5987.148" - wire $and$ls180.v:5987$1483_Y - attribute \src "ls180.v:5988.45-5988.101" - wire $and$ls180.v:5988$1485_Y - attribute \src "ls180.v:5988.44-5988.151" - wire $and$ls180.v:5988$1487_Y - attribute \src "ls180.v:5990.45-5990.98" - wire $and$ls180.v:5990$1488_Y - attribute \src "ls180.v:5990.44-5990.148" - wire $and$ls180.v:5990$1490_Y - attribute \src "ls180.v:5991.45-5991.101" - wire $and$ls180.v:5991$1492_Y - attribute \src "ls180.v:5991.44-5991.151" - wire $and$ls180.v:5991$1494_Y - attribute \src "ls180.v:5993.36-5993.89" - wire $and$ls180.v:5993$1495_Y - attribute \src "ls180.v:5993.35-5993.139" - wire $and$ls180.v:5993$1497_Y - attribute \src "ls180.v:5994.36-5994.92" - wire $and$ls180.v:5994$1499_Y - attribute \src "ls180.v:5994.35-5994.142" - wire $and$ls180.v:5994$1501_Y - attribute \src "ls180.v:5996.47-5996.100" - wire $and$ls180.v:5996$1502_Y - attribute \src "ls180.v:5996.46-5996.150" - wire $and$ls180.v:5996$1504_Y - attribute \src "ls180.v:5997.47-5997.103" - wire $and$ls180.v:5997$1506_Y - attribute \src "ls180.v:5997.46-5997.153" - wire $and$ls180.v:5997$1508_Y - attribute \src "ls180.v:5999.47-5999.100" - wire $and$ls180.v:5999$1509_Y - attribute \src "ls180.v:5999.46-5999.151" - wire $and$ls180.v:5999$1511_Y - attribute \src "ls180.v:6000.47-6000.103" - wire $and$ls180.v:6000$1513_Y - attribute \src "ls180.v:6000.46-6000.154" - wire $and$ls180.v:6000$1515_Y - attribute \src "ls180.v:6002.47-6002.100" - wire $and$ls180.v:6002$1516_Y - attribute \src "ls180.v:6002.46-6002.151" - wire $and$ls180.v:6002$1518_Y - attribute \src "ls180.v:6003.47-6003.103" - wire $and$ls180.v:6003$1520_Y - attribute \src "ls180.v:6003.46-6003.154" - wire $and$ls180.v:6003$1522_Y - attribute \src "ls180.v:6005.47-6005.100" - wire $and$ls180.v:6005$1523_Y - attribute \src "ls180.v:6005.46-6005.151" - wire $and$ls180.v:6005$1525_Y - attribute \src "ls180.v:6006.47-6006.103" - wire $and$ls180.v:6006$1527_Y - attribute \src "ls180.v:6006.46-6006.154" - wire $and$ls180.v:6006$1529_Y - attribute \src "ls180.v:6008.47-6008.100" - wire $and$ls180.v:6008$1530_Y - attribute \src "ls180.v:6008.46-6008.151" - wire $and$ls180.v:6008$1532_Y - attribute \src "ls180.v:6009.47-6009.103" - wire $and$ls180.v:6009$1534_Y - attribute \src "ls180.v:6009.46-6009.154" - wire $and$ls180.v:6009$1536_Y - attribute \src "ls180.v:6011.47-6011.100" - wire $and$ls180.v:6011$1537_Y - attribute \src "ls180.v:6011.46-6011.151" - wire $and$ls180.v:6011$1539_Y - attribute \src "ls180.v:6012.47-6012.103" - wire $and$ls180.v:6012$1541_Y - attribute \src "ls180.v:6012.46-6012.154" - wire $and$ls180.v:6012$1543_Y - attribute \src "ls180.v:6014.46-6014.99" - wire $and$ls180.v:6014$1544_Y - attribute \src "ls180.v:6014.45-6014.150" - wire $and$ls180.v:6014$1546_Y - attribute \src "ls180.v:6015.46-6015.102" - wire $and$ls180.v:6015$1548_Y - attribute \src "ls180.v:6015.45-6015.153" - wire $and$ls180.v:6015$1550_Y - attribute \src "ls180.v:6017.46-6017.99" - wire $and$ls180.v:6017$1551_Y - attribute \src "ls180.v:6017.45-6017.150" - wire $and$ls180.v:6017$1553_Y - attribute \src "ls180.v:6018.46-6018.102" - wire $and$ls180.v:6018$1555_Y - attribute \src "ls180.v:6018.45-6018.153" - wire $and$ls180.v:6018$1557_Y - attribute \src "ls180.v:6020.46-6020.99" - wire $and$ls180.v:6020$1558_Y - attribute \src "ls180.v:6020.45-6020.150" - wire $and$ls180.v:6020$1560_Y - attribute \src "ls180.v:6021.46-6021.102" - wire $and$ls180.v:6021$1562_Y - attribute \src "ls180.v:6021.45-6021.153" - wire $and$ls180.v:6021$1564_Y - attribute \src "ls180.v:6023.46-6023.99" - wire $and$ls180.v:6023$1565_Y - attribute \src "ls180.v:6023.45-6023.150" - wire $and$ls180.v:6023$1567_Y - attribute \src "ls180.v:6024.46-6024.102" - wire $and$ls180.v:6024$1569_Y - attribute \src "ls180.v:6024.45-6024.153" - wire $and$ls180.v:6024$1571_Y - attribute \src "ls180.v:6026.46-6026.99" - wire $and$ls180.v:6026$1572_Y - attribute \src "ls180.v:6026.45-6026.150" - wire $and$ls180.v:6026$1574_Y - attribute \src "ls180.v:6027.46-6027.102" - wire $and$ls180.v:6027$1576_Y - attribute \src "ls180.v:6027.45-6027.153" - wire $and$ls180.v:6027$1578_Y - attribute \src "ls180.v:6029.46-6029.99" - wire $and$ls180.v:6029$1579_Y - attribute \src "ls180.v:6029.45-6029.150" - wire $and$ls180.v:6029$1581_Y - attribute \src "ls180.v:6030.46-6030.102" - wire $and$ls180.v:6030$1583_Y - attribute \src "ls180.v:6030.45-6030.153" - wire $and$ls180.v:6030$1585_Y - attribute \src "ls180.v:6032.46-6032.99" - wire $and$ls180.v:6032$1586_Y - attribute \src "ls180.v:6032.45-6032.150" - wire $and$ls180.v:6032$1588_Y - attribute \src "ls180.v:6033.46-6033.102" - wire $and$ls180.v:6033$1590_Y - attribute \src "ls180.v:6033.45-6033.153" - wire $and$ls180.v:6033$1592_Y - attribute \src "ls180.v:6035.46-6035.99" - wire $and$ls180.v:6035$1593_Y - attribute \src "ls180.v:6035.45-6035.150" - wire $and$ls180.v:6035$1595_Y - attribute \src "ls180.v:6036.46-6036.102" - wire $and$ls180.v:6036$1597_Y - attribute \src "ls180.v:6036.45-6036.153" - wire $and$ls180.v:6036$1599_Y - attribute \src "ls180.v:6038.46-6038.99" - wire $and$ls180.v:6038$1600_Y - attribute \src "ls180.v:6038.45-6038.150" - wire $and$ls180.v:6038$1602_Y - attribute \src "ls180.v:6039.46-6039.102" - wire $and$ls180.v:6039$1604_Y - attribute \src "ls180.v:6039.45-6039.153" - wire $and$ls180.v:6039$1606_Y - attribute \src "ls180.v:6041.46-6041.99" - wire $and$ls180.v:6041$1607_Y - attribute \src "ls180.v:6041.45-6041.150" - wire $and$ls180.v:6041$1609_Y - attribute \src "ls180.v:6042.46-6042.102" - wire $and$ls180.v:6042$1611_Y - attribute \src "ls180.v:6042.45-6042.153" - wire $and$ls180.v:6042$1613_Y - attribute \src "ls180.v:6044.42-6044.95" - wire $and$ls180.v:6044$1614_Y - attribute \src "ls180.v:6044.41-6044.146" - wire $and$ls180.v:6044$1616_Y - attribute \src "ls180.v:6045.42-6045.98" - wire $and$ls180.v:6045$1618_Y - attribute \src "ls180.v:6045.41-6045.149" - wire $and$ls180.v:6045$1620_Y - attribute \src "ls180.v:6047.43-6047.96" - wire $and$ls180.v:6047$1621_Y - attribute \src "ls180.v:6047.42-6047.147" - wire $and$ls180.v:6047$1623_Y - attribute \src "ls180.v:6048.43-6048.99" - wire $and$ls180.v:6048$1625_Y - attribute \src "ls180.v:6048.42-6048.150" - wire $and$ls180.v:6048$1627_Y - attribute \src "ls180.v:6050.46-6050.99" - wire $and$ls180.v:6050$1628_Y - attribute \src "ls180.v:6050.45-6050.150" - wire $and$ls180.v:6050$1630_Y - attribute \src "ls180.v:6051.46-6051.102" - wire $and$ls180.v:6051$1632_Y - attribute \src "ls180.v:6051.45-6051.153" - wire $and$ls180.v:6051$1634_Y - attribute \src "ls180.v:6053.46-6053.99" - wire $and$ls180.v:6053$1635_Y - attribute \src "ls180.v:6053.45-6053.150" - wire $and$ls180.v:6053$1637_Y - attribute \src "ls180.v:6054.46-6054.102" - wire $and$ls180.v:6054$1639_Y - attribute \src "ls180.v:6054.45-6054.153" - wire $and$ls180.v:6054$1641_Y - attribute \src "ls180.v:6056.45-6056.98" - wire $and$ls180.v:6056$1642_Y - attribute \src "ls180.v:6056.44-6056.149" - wire $and$ls180.v:6056$1644_Y - attribute \src "ls180.v:6057.45-6057.101" - wire $and$ls180.v:6057$1646_Y - attribute \src "ls180.v:6057.44-6057.152" - wire $and$ls180.v:6057$1648_Y - attribute \src "ls180.v:6059.45-6059.98" - wire $and$ls180.v:6059$1649_Y - attribute \src "ls180.v:6059.44-6059.149" - wire $and$ls180.v:6059$1651_Y - attribute \src "ls180.v:6060.45-6060.101" - wire $and$ls180.v:6060$1653_Y - attribute \src "ls180.v:6060.44-6060.152" - wire $and$ls180.v:6060$1655_Y - attribute \src "ls180.v:6062.45-6062.98" - wire $and$ls180.v:6062$1656_Y - attribute \src "ls180.v:6062.44-6062.149" - wire $and$ls180.v:6062$1658_Y - attribute \src "ls180.v:6063.45-6063.101" - wire $and$ls180.v:6063$1660_Y - attribute \src "ls180.v:6063.44-6063.152" - wire $and$ls180.v:6063$1662_Y - attribute \src "ls180.v:6065.45-6065.98" - wire $and$ls180.v:6065$1663_Y - attribute \src "ls180.v:6065.44-6065.149" - wire $and$ls180.v:6065$1665_Y - attribute \src "ls180.v:6066.45-6066.101" - wire $and$ls180.v:6066$1667_Y - attribute \src "ls180.v:6066.44-6066.152" - wire $and$ls180.v:6066$1669_Y - attribute \src "ls180.v:6104.42-6104.95" - wire $and$ls180.v:6104$1671_Y - attribute \src "ls180.v:6104.41-6104.145" - wire $and$ls180.v:6104$1673_Y - attribute \src "ls180.v:6105.42-6105.98" - wire $and$ls180.v:6105$1675_Y - attribute \src "ls180.v:6105.41-6105.148" - wire $and$ls180.v:6105$1677_Y - attribute \src "ls180.v:6107.42-6107.95" - wire $and$ls180.v:6107$1678_Y - attribute \src "ls180.v:6107.41-6107.145" - wire $and$ls180.v:6107$1680_Y - attribute \src "ls180.v:6108.42-6108.98" - wire $and$ls180.v:6108$1682_Y - attribute \src "ls180.v:6108.41-6108.148" - wire $and$ls180.v:6108$1684_Y - attribute \src "ls180.v:6110.42-6110.95" - wire $and$ls180.v:6110$1685_Y - attribute \src "ls180.v:6110.41-6110.145" - wire $and$ls180.v:6110$1687_Y - attribute \src "ls180.v:6111.42-6111.98" - wire $and$ls180.v:6111$1689_Y - attribute \src "ls180.v:6111.41-6111.148" - wire $and$ls180.v:6111$1691_Y - attribute \src "ls180.v:6113.42-6113.95" - wire $and$ls180.v:6113$1692_Y - attribute \src "ls180.v:6113.41-6113.145" - wire $and$ls180.v:6113$1694_Y - attribute \src "ls180.v:6114.42-6114.98" - wire $and$ls180.v:6114$1696_Y - attribute \src "ls180.v:6114.41-6114.148" - wire $and$ls180.v:6114$1698_Y - attribute \src "ls180.v:6116.42-6116.95" - wire $and$ls180.v:6116$1699_Y - attribute \src "ls180.v:6116.41-6116.145" - wire $and$ls180.v:6116$1701_Y - attribute \src "ls180.v:6117.42-6117.98" - wire $and$ls180.v:6117$1703_Y - attribute \src "ls180.v:6117.41-6117.148" - wire $and$ls180.v:6117$1705_Y - attribute \src "ls180.v:6119.42-6119.95" - wire $and$ls180.v:6119$1706_Y - attribute \src "ls180.v:6119.41-6119.145" - wire $and$ls180.v:6119$1708_Y - attribute \src "ls180.v:6120.42-6120.98" - wire $and$ls180.v:6120$1710_Y - attribute \src "ls180.v:6120.41-6120.148" - wire $and$ls180.v:6120$1712_Y - attribute \src "ls180.v:6122.42-6122.95" - wire $and$ls180.v:6122$1713_Y - attribute \src "ls180.v:6122.41-6122.145" - wire $and$ls180.v:6122$1715_Y - attribute \src "ls180.v:6123.42-6123.98" - wire $and$ls180.v:6123$1717_Y - attribute \src "ls180.v:6123.41-6123.148" - wire $and$ls180.v:6123$1719_Y - attribute \src "ls180.v:6125.42-6125.95" - wire $and$ls180.v:6125$1720_Y - attribute \src "ls180.v:6125.41-6125.145" - wire $and$ls180.v:6125$1722_Y - attribute \src "ls180.v:6126.42-6126.98" - wire $and$ls180.v:6126$1724_Y - attribute \src "ls180.v:6126.41-6126.148" - wire $and$ls180.v:6126$1726_Y - attribute \src "ls180.v:6128.44-6128.97" - wire $and$ls180.v:6128$1727_Y - attribute \src "ls180.v:6128.43-6128.147" - wire $and$ls180.v:6128$1729_Y - attribute \src "ls180.v:6129.44-6129.100" - wire $and$ls180.v:6129$1731_Y - attribute \src "ls180.v:6129.43-6129.150" - wire $and$ls180.v:6129$1733_Y - attribute \src "ls180.v:6131.44-6131.97" - wire $and$ls180.v:6131$1734_Y - attribute \src "ls180.v:6131.43-6131.147" - wire $and$ls180.v:6131$1736_Y - attribute \src "ls180.v:6132.44-6132.100" - wire $and$ls180.v:6132$1738_Y - attribute \src "ls180.v:6132.43-6132.150" - wire $and$ls180.v:6132$1740_Y - attribute \src "ls180.v:6134.44-6134.97" - wire $and$ls180.v:6134$1741_Y - attribute \src "ls180.v:6134.43-6134.148" - wire $and$ls180.v:6134$1743_Y - attribute \src "ls180.v:6135.44-6135.100" - wire $and$ls180.v:6135$1745_Y - attribute \src "ls180.v:6135.43-6135.151" - wire $and$ls180.v:6135$1747_Y - attribute \src "ls180.v:6137.44-6137.97" - wire $and$ls180.v:6137$1748_Y - attribute \src "ls180.v:6137.43-6137.148" - wire $and$ls180.v:6137$1750_Y - attribute \src "ls180.v:6138.44-6138.100" - wire $and$ls180.v:6138$1752_Y - attribute \src "ls180.v:6138.43-6138.151" - wire $and$ls180.v:6138$1754_Y - attribute \src "ls180.v:6140.44-6140.97" - wire $and$ls180.v:6140$1755_Y - attribute \src "ls180.v:6140.43-6140.148" - wire $and$ls180.v:6140$1757_Y - attribute \src "ls180.v:6141.44-6141.100" - wire $and$ls180.v:6141$1759_Y - attribute \src "ls180.v:6141.43-6141.151" - wire $and$ls180.v:6141$1761_Y - attribute \src "ls180.v:6143.41-6143.94" - wire $and$ls180.v:6143$1762_Y - attribute \src "ls180.v:6143.40-6143.145" - wire $and$ls180.v:6143$1764_Y - attribute \src "ls180.v:6144.41-6144.97" - wire $and$ls180.v:6144$1766_Y - attribute \src "ls180.v:6144.40-6144.148" - wire $and$ls180.v:6144$1768_Y - attribute \src "ls180.v:6146.42-6146.95" - wire $and$ls180.v:6146$1769_Y - attribute \src "ls180.v:6146.41-6146.146" - wire $and$ls180.v:6146$1771_Y - attribute \src "ls180.v:6147.42-6147.98" - wire $and$ls180.v:6147$1773_Y - attribute \src "ls180.v:6147.41-6147.149" - wire $and$ls180.v:6147$1775_Y - attribute \src "ls180.v:6149.44-6149.97" - wire $and$ls180.v:6149$1776_Y - attribute \src "ls180.v:6149.43-6149.148" - wire $and$ls180.v:6149$1778_Y - attribute \src "ls180.v:6150.44-6150.100" - wire $and$ls180.v:6150$1780_Y - attribute \src "ls180.v:6150.43-6150.151" - wire $and$ls180.v:6150$1782_Y - attribute \src "ls180.v:6152.44-6152.97" - wire $and$ls180.v:6152$1783_Y - attribute \src "ls180.v:6152.43-6152.148" - wire $and$ls180.v:6152$1785_Y - attribute \src "ls180.v:6153.44-6153.100" - wire $and$ls180.v:6153$1787_Y - attribute \src "ls180.v:6153.43-6153.151" - wire $and$ls180.v:6153$1789_Y - attribute \src "ls180.v:6155.44-6155.97" - wire $and$ls180.v:6155$1790_Y - attribute \src "ls180.v:6155.43-6155.148" - wire $and$ls180.v:6155$1792_Y - attribute \src "ls180.v:6156.44-6156.100" - wire $and$ls180.v:6156$1794_Y - attribute \src "ls180.v:6156.43-6156.151" - wire $and$ls180.v:6156$1796_Y - attribute \src "ls180.v:6158.44-6158.97" - wire $and$ls180.v:6158$1797_Y - attribute \src "ls180.v:6158.43-6158.148" - wire $and$ls180.v:6158$1799_Y - attribute \src "ls180.v:6159.44-6159.100" - wire $and$ls180.v:6159$1801_Y - attribute \src "ls180.v:6159.43-6159.151" - wire $and$ls180.v:6159$1803_Y - attribute \src "ls180.v:6183.44-6183.97" - wire $and$ls180.v:6183$1805_Y - attribute \src "ls180.v:6183.43-6183.147" - wire $and$ls180.v:6183$1807_Y - attribute \src "ls180.v:6184.44-6184.100" - wire $and$ls180.v:6184$1809_Y - attribute \src "ls180.v:6184.43-6184.150" - wire $and$ls180.v:6184$1811_Y - attribute \src "ls180.v:6186.49-6186.102" - wire $and$ls180.v:6186$1812_Y - attribute \src "ls180.v:6186.48-6186.152" - wire $and$ls180.v:6186$1814_Y - attribute \src "ls180.v:6187.49-6187.105" - wire $and$ls180.v:6187$1816_Y - attribute \src "ls180.v:6187.48-6187.155" - wire $and$ls180.v:6187$1818_Y - attribute \src "ls180.v:6189.49-6189.102" - wire $and$ls180.v:6189$1819_Y - attribute \src "ls180.v:6189.48-6189.152" - wire $and$ls180.v:6189$1821_Y - attribute \src "ls180.v:6190.49-6190.105" - wire $and$ls180.v:6190$1823_Y - attribute \src "ls180.v:6190.48-6190.155" - wire $and$ls180.v:6190$1825_Y - attribute \src "ls180.v:6192.42-6192.95" - wire $and$ls180.v:6192$1826_Y - attribute \src "ls180.v:6192.41-6192.145" - wire $and$ls180.v:6192$1828_Y - attribute \src "ls180.v:6193.42-6193.98" - wire $and$ls180.v:6193$1830_Y - attribute \src "ls180.v:6193.41-6193.148" - wire $and$ls180.v:6193$1832_Y - attribute \src "ls180.v:6200.46-6200.99" - wire $and$ls180.v:6200$1834_Y - attribute \src "ls180.v:6200.45-6200.149" - wire $and$ls180.v:6200$1836_Y - attribute \src "ls180.v:6201.46-6201.102" - wire $and$ls180.v:6201$1838_Y - attribute \src "ls180.v:6201.45-6201.152" - wire $and$ls180.v:6201$1840_Y - attribute \src "ls180.v:6203.50-6203.103" - wire $and$ls180.v:6203$1841_Y - attribute \src "ls180.v:6203.49-6203.153" - wire $and$ls180.v:6203$1843_Y - attribute \src "ls180.v:6204.50-6204.106" - wire $and$ls180.v:6204$1845_Y - attribute \src "ls180.v:6204.49-6204.156" - wire $and$ls180.v:6204$1847_Y - attribute \src "ls180.v:6206.40-6206.93" - wire $and$ls180.v:6206$1848_Y - attribute \src "ls180.v:6206.39-6206.143" - wire $and$ls180.v:6206$1850_Y - attribute \src "ls180.v:6207.40-6207.96" - wire $and$ls180.v:6207$1852_Y - attribute \src "ls180.v:6207.39-6207.146" - wire $and$ls180.v:6207$1854_Y - attribute \src "ls180.v:6209.50-6209.103" - wire $and$ls180.v:6209$1855_Y - attribute \src "ls180.v:6209.49-6209.153" - wire $and$ls180.v:6209$1857_Y - attribute \src "ls180.v:6210.50-6210.106" - wire $and$ls180.v:6210$1859_Y - attribute \src "ls180.v:6210.49-6210.156" - wire $and$ls180.v:6210$1861_Y - attribute \src "ls180.v:6212.50-6212.103" - wire $and$ls180.v:6212$1862_Y - attribute \src "ls180.v:6212.49-6212.153" - wire $and$ls180.v:6212$1864_Y - attribute \src "ls180.v:6213.50-6213.106" - wire $and$ls180.v:6213$1866_Y - attribute \src "ls180.v:6213.49-6213.156" - wire $and$ls180.v:6213$1868_Y - attribute \src "ls180.v:6215.51-6215.104" - wire $and$ls180.v:6215$1869_Y - attribute \src "ls180.v:6215.50-6215.154" - wire $and$ls180.v:6215$1871_Y - attribute \src "ls180.v:6216.51-6216.107" - wire $and$ls180.v:6216$1873_Y - attribute \src "ls180.v:6216.50-6216.157" - wire $and$ls180.v:6216$1875_Y - attribute \src "ls180.v:6218.49-6218.102" - wire $and$ls180.v:6218$1876_Y - attribute \src "ls180.v:6218.48-6218.152" - wire $and$ls180.v:6218$1878_Y - attribute \src "ls180.v:6219.49-6219.105" - wire $and$ls180.v:6219$1880_Y - attribute \src "ls180.v:6219.48-6219.155" - wire $and$ls180.v:6219$1882_Y - attribute \src "ls180.v:6221.49-6221.102" - wire $and$ls180.v:6221$1883_Y - attribute \src "ls180.v:6221.48-6221.152" - wire $and$ls180.v:6221$1885_Y - attribute \src "ls180.v:6222.49-6222.105" - wire $and$ls180.v:6222$1887_Y - attribute \src "ls180.v:6222.48-6222.155" - wire $and$ls180.v:6222$1889_Y - attribute \src "ls180.v:6224.49-6224.102" - wire $and$ls180.v:6224$1890_Y - attribute \src "ls180.v:6224.48-6224.152" - wire $and$ls180.v:6224$1892_Y - attribute \src "ls180.v:6225.49-6225.105" - wire $and$ls180.v:6225$1894_Y - attribute \src "ls180.v:6225.48-6225.155" - wire $and$ls180.v:6225$1896_Y - attribute \src "ls180.v:6227.49-6227.102" - wire $and$ls180.v:6227$1897_Y - attribute \src "ls180.v:6227.48-6227.152" - wire $and$ls180.v:6227$1899_Y - attribute \src "ls180.v:6228.49-6228.105" - wire $and$ls180.v:6228$1901_Y - attribute \src "ls180.v:6228.48-6228.155" - wire $and$ls180.v:6228$1903_Y - attribute \src "ls180.v:6245.42-6245.97" - wire $and$ls180.v:6245$1905_Y - attribute \src "ls180.v:6245.41-6245.148" - wire $and$ls180.v:6245$1907_Y - attribute \src "ls180.v:6246.42-6246.100" - wire $and$ls180.v:6246$1909_Y - attribute \src "ls180.v:6246.41-6246.151" - wire $and$ls180.v:6246$1911_Y - attribute \src "ls180.v:6248.42-6248.97" - wire $and$ls180.v:6248$1912_Y - attribute \src "ls180.v:6248.41-6248.148" - wire $and$ls180.v:6248$1914_Y - attribute \src "ls180.v:6249.42-6249.100" - wire $and$ls180.v:6249$1916_Y - attribute \src "ls180.v:6249.41-6249.151" - wire $and$ls180.v:6249$1918_Y - attribute \src "ls180.v:6251.40-6251.95" - wire $and$ls180.v:6251$1919_Y - attribute \src "ls180.v:6251.39-6251.146" - wire $and$ls180.v:6251$1921_Y - attribute \src "ls180.v:6252.40-6252.98" - wire $and$ls180.v:6252$1923_Y - attribute \src "ls180.v:6252.39-6252.149" - wire $and$ls180.v:6252$1925_Y - attribute \src "ls180.v:6254.39-6254.94" - wire $and$ls180.v:6254$1926_Y - attribute \src "ls180.v:6254.38-6254.145" - wire $and$ls180.v:6254$1928_Y - attribute \src "ls180.v:6255.39-6255.97" - wire $and$ls180.v:6255$1930_Y - attribute \src "ls180.v:6255.38-6255.148" - wire $and$ls180.v:6255$1932_Y - attribute \src "ls180.v:6257.38-6257.93" - wire $and$ls180.v:6257$1933_Y - attribute \src "ls180.v:6257.37-6257.144" - wire $and$ls180.v:6257$1935_Y - attribute \src "ls180.v:6258.38-6258.96" - wire $and$ls180.v:6258$1937_Y - attribute \src "ls180.v:6258.37-6258.147" - wire $and$ls180.v:6258$1939_Y - attribute \src "ls180.v:6260.37-6260.92" - wire $and$ls180.v:6260$1940_Y - attribute \src "ls180.v:6260.36-6260.143" - wire $and$ls180.v:6260$1942_Y - attribute \src "ls180.v:6261.37-6261.95" - wire $and$ls180.v:6261$1944_Y - attribute \src "ls180.v:6261.36-6261.146" - wire $and$ls180.v:6261$1946_Y - attribute \src "ls180.v:6263.43-6263.98" - wire $and$ls180.v:6263$1947_Y - attribute \src "ls180.v:6263.42-6263.149" - wire $and$ls180.v:6263$1949_Y - attribute \src "ls180.v:6264.43-6264.101" - wire $and$ls180.v:6264$1951_Y - attribute \src "ls180.v:6264.42-6264.152" - wire $and$ls180.v:6264$1953_Y - attribute \src "ls180.v:6285.42-6285.97" - wire $and$ls180.v:6285$1956_Y - attribute \src "ls180.v:6285.41-6285.148" - wire $and$ls180.v:6285$1958_Y - attribute \src "ls180.v:6286.42-6286.100" - wire $and$ls180.v:6286$1960_Y - attribute \src "ls180.v:6286.41-6286.151" - wire $and$ls180.v:6286$1962_Y - attribute \src "ls180.v:6288.42-6288.97" - wire $and$ls180.v:6288$1963_Y - attribute \src "ls180.v:6288.41-6288.148" - wire $and$ls180.v:6288$1965_Y - attribute \src "ls180.v:6289.42-6289.100" - wire $and$ls180.v:6289$1967_Y - attribute \src "ls180.v:6289.41-6289.151" - wire $and$ls180.v:6289$1969_Y - attribute \src "ls180.v:6291.40-6291.95" - wire $and$ls180.v:6291$1970_Y - attribute \src "ls180.v:6291.39-6291.146" - wire $and$ls180.v:6291$1972_Y - attribute \src "ls180.v:6292.40-6292.98" - wire $and$ls180.v:6292$1974_Y - attribute \src "ls180.v:6292.39-6292.149" - wire $and$ls180.v:6292$1976_Y - attribute \src "ls180.v:6294.39-6294.94" - wire $and$ls180.v:6294$1977_Y - attribute \src "ls180.v:6294.38-6294.145" - wire $and$ls180.v:6294$1979_Y - attribute \src "ls180.v:6295.39-6295.97" - wire $and$ls180.v:6295$1981_Y - attribute \src "ls180.v:6295.38-6295.148" - wire $and$ls180.v:6295$1983_Y - attribute \src "ls180.v:6297.38-6297.93" - wire $and$ls180.v:6297$1984_Y - attribute \src "ls180.v:6297.37-6297.144" - wire $and$ls180.v:6297$1986_Y - attribute \src "ls180.v:6298.38-6298.96" - wire $and$ls180.v:6298$1988_Y - attribute \src "ls180.v:6298.37-6298.147" - wire $and$ls180.v:6298$1990_Y - attribute \src "ls180.v:6300.37-6300.92" - wire $and$ls180.v:6300$1991_Y - attribute \src "ls180.v:6300.36-6300.143" - wire $and$ls180.v:6300$1993_Y - attribute \src "ls180.v:6301.37-6301.95" - wire $and$ls180.v:6301$1995_Y - attribute \src "ls180.v:6301.36-6301.146" - wire $and$ls180.v:6301$1997_Y - attribute \src "ls180.v:6303.43-6303.98" - wire $and$ls180.v:6303$1998_Y - attribute \src "ls180.v:6303.42-6303.149" - wire $and$ls180.v:6303$2000_Y - attribute \src "ls180.v:6304.43-6304.101" - wire $and$ls180.v:6304$2002_Y - attribute \src "ls180.v:6304.42-6304.152" - wire $and$ls180.v:6304$2004_Y - attribute \src "ls180.v:6306.46-6306.101" - wire $and$ls180.v:6306$2005_Y - attribute \src "ls180.v:6306.45-6306.152" - wire $and$ls180.v:6306$2007_Y - attribute \src "ls180.v:6307.46-6307.104" - wire $and$ls180.v:6307$2009_Y - attribute \src "ls180.v:6307.45-6307.155" - wire $and$ls180.v:6307$2011_Y - attribute \src "ls180.v:6309.46-6309.101" - wire $and$ls180.v:6309$2012_Y - attribute \src "ls180.v:6309.45-6309.152" - wire $and$ls180.v:6309$2014_Y - attribute \src "ls180.v:6310.46-6310.104" - wire $and$ls180.v:6310$2016_Y - attribute \src "ls180.v:6310.45-6310.155" - wire $and$ls180.v:6310$2018_Y - attribute \src "ls180.v:6333.39-6333.94" - wire $and$ls180.v:6333$2021_Y - attribute \src "ls180.v:6333.38-6333.145" - wire $and$ls180.v:6333$2023_Y - attribute \src "ls180.v:6334.39-6334.97" - wire $and$ls180.v:6334$2025_Y - attribute \src "ls180.v:6334.38-6334.148" - wire $and$ls180.v:6334$2027_Y - attribute \src "ls180.v:6336.39-6336.94" - wire $and$ls180.v:6336$2028_Y - attribute \src "ls180.v:6336.38-6336.145" - wire $and$ls180.v:6336$2030_Y - attribute \src "ls180.v:6337.39-6337.97" - wire $and$ls180.v:6337$2032_Y - attribute \src "ls180.v:6337.38-6337.148" - wire $and$ls180.v:6337$2034_Y - attribute \src "ls180.v:6339.39-6339.94" - wire $and$ls180.v:6339$2035_Y - attribute \src "ls180.v:6339.38-6339.145" - wire $and$ls180.v:6339$2037_Y - attribute \src "ls180.v:6340.39-6340.97" - wire $and$ls180.v:6340$2039_Y - attribute \src "ls180.v:6340.38-6340.148" - wire $and$ls180.v:6340$2041_Y - attribute \src "ls180.v:6342.39-6342.94" - wire $and$ls180.v:6342$2042_Y - attribute \src "ls180.v:6342.38-6342.145" - wire $and$ls180.v:6342$2044_Y - attribute \src "ls180.v:6343.39-6343.97" - wire $and$ls180.v:6343$2046_Y - attribute \src "ls180.v:6343.38-6343.148" - wire $and$ls180.v:6343$2048_Y - attribute \src "ls180.v:6345.41-6345.96" - wire $and$ls180.v:6345$2049_Y - attribute \src "ls180.v:6345.40-6345.147" - wire $and$ls180.v:6345$2051_Y - attribute \src "ls180.v:6346.41-6346.99" - wire $and$ls180.v:6346$2053_Y - attribute \src "ls180.v:6346.40-6346.150" - wire $and$ls180.v:6346$2055_Y - attribute \src "ls180.v:6348.41-6348.96" - wire $and$ls180.v:6348$2056_Y - attribute \src "ls180.v:6348.40-6348.147" - wire $and$ls180.v:6348$2058_Y - attribute \src "ls180.v:6349.41-6349.99" - wire $and$ls180.v:6349$2060_Y - attribute \src "ls180.v:6349.40-6349.150" - wire $and$ls180.v:6349$2062_Y - attribute \src "ls180.v:6351.41-6351.96" - wire $and$ls180.v:6351$2063_Y - attribute \src "ls180.v:6351.40-6351.147" - wire $and$ls180.v:6351$2065_Y - attribute \src "ls180.v:6352.41-6352.99" - wire $and$ls180.v:6352$2067_Y - attribute \src "ls180.v:6352.40-6352.150" - wire $and$ls180.v:6352$2069_Y - attribute \src "ls180.v:6354.41-6354.96" - wire $and$ls180.v:6354$2070_Y - attribute \src "ls180.v:6354.40-6354.147" - wire $and$ls180.v:6354$2072_Y - attribute \src "ls180.v:6355.41-6355.99" - wire $and$ls180.v:6355$2074_Y - attribute \src "ls180.v:6355.40-6355.150" - wire $and$ls180.v:6355$2076_Y - attribute \src "ls180.v:6357.37-6357.92" - wire $and$ls180.v:6357$2077_Y - attribute \src "ls180.v:6357.36-6357.143" - wire $and$ls180.v:6357$2079_Y - attribute \src "ls180.v:6358.37-6358.95" - wire $and$ls180.v:6358$2081_Y - attribute \src "ls180.v:6358.36-6358.146" - wire $and$ls180.v:6358$2083_Y - attribute \src "ls180.v:6360.47-6360.102" - wire $and$ls180.v:6360$2084_Y - attribute \src "ls180.v:6360.46-6360.153" - wire $and$ls180.v:6360$2086_Y - attribute \src "ls180.v:6361.47-6361.105" - wire $and$ls180.v:6361$2088_Y - attribute \src "ls180.v:6361.46-6361.156" - wire $and$ls180.v:6361$2090_Y - attribute \src "ls180.v:6363.40-6363.95" - wire $and$ls180.v:6363$2091_Y - attribute \src "ls180.v:6363.39-6363.147" - wire $and$ls180.v:6363$2093_Y - attribute \src "ls180.v:6364.40-6364.98" - wire $and$ls180.v:6364$2095_Y - attribute \src "ls180.v:6364.39-6364.150" - wire $and$ls180.v:6364$2097_Y - attribute \src "ls180.v:6366.40-6366.95" - wire $and$ls180.v:6366$2098_Y - attribute \src "ls180.v:6366.39-6366.147" - wire $and$ls180.v:6366$2100_Y - attribute \src "ls180.v:6367.40-6367.98" - wire $and$ls180.v:6367$2102_Y - attribute \src "ls180.v:6367.39-6367.150" - wire $and$ls180.v:6367$2104_Y - attribute \src "ls180.v:6369.40-6369.95" - wire $and$ls180.v:6369$2105_Y - attribute \src "ls180.v:6369.39-6369.147" - wire $and$ls180.v:6369$2107_Y - attribute \src "ls180.v:6370.40-6370.98" - wire $and$ls180.v:6370$2109_Y - attribute \src "ls180.v:6370.39-6370.150" - wire $and$ls180.v:6370$2111_Y - attribute \src "ls180.v:6372.40-6372.95" - wire $and$ls180.v:6372$2112_Y - attribute \src "ls180.v:6372.39-6372.147" - wire $and$ls180.v:6372$2114_Y - attribute \src "ls180.v:6373.40-6373.98" - wire $and$ls180.v:6373$2116_Y - attribute \src "ls180.v:6373.39-6373.150" - wire $and$ls180.v:6373$2118_Y - attribute \src "ls180.v:6375.52-6375.107" - wire $and$ls180.v:6375$2119_Y - attribute \src "ls180.v:6375.51-6375.159" - wire $and$ls180.v:6375$2121_Y - attribute \src "ls180.v:6376.52-6376.110" - wire $and$ls180.v:6376$2123_Y - attribute \src "ls180.v:6376.51-6376.162" - wire $and$ls180.v:6376$2125_Y - attribute \src "ls180.v:6378.53-6378.108" - wire $and$ls180.v:6378$2126_Y - attribute \src "ls180.v:6378.52-6378.160" - wire $and$ls180.v:6378$2128_Y - attribute \src "ls180.v:6379.53-6379.111" - wire $and$ls180.v:6379$2130_Y - attribute \src "ls180.v:6379.52-6379.163" - wire $and$ls180.v:6379$2132_Y - attribute \src "ls180.v:6381.44-6381.99" - wire $and$ls180.v:6381$2133_Y - attribute \src "ls180.v:6381.43-6381.151" - wire $and$ls180.v:6381$2135_Y - attribute \src "ls180.v:6382.44-6382.102" - wire $and$ls180.v:6382$2137_Y - attribute \src "ls180.v:6382.43-6382.154" - wire $and$ls180.v:6382$2139_Y - attribute \src "ls180.v:6401.30-6401.85" - wire $and$ls180.v:6401$2141_Y - attribute \src "ls180.v:6401.29-6401.136" - wire $and$ls180.v:6401$2143_Y - attribute \src "ls180.v:6402.30-6402.88" - wire $and$ls180.v:6402$2145_Y - attribute \src "ls180.v:6402.29-6402.139" - wire $and$ls180.v:6402$2147_Y - attribute \src "ls180.v:6404.40-6404.95" - wire $and$ls180.v:6404$2148_Y - attribute \src "ls180.v:6404.39-6404.146" - wire $and$ls180.v:6404$2150_Y - attribute \src "ls180.v:6405.40-6405.98" - wire $and$ls180.v:6405$2152_Y - attribute \src "ls180.v:6405.39-6405.149" - wire $and$ls180.v:6405$2154_Y - attribute \src "ls180.v:6407.41-6407.96" - wire $and$ls180.v:6407$2155_Y - attribute \src "ls180.v:6407.40-6407.147" - wire $and$ls180.v:6407$2157_Y - attribute \src "ls180.v:6408.41-6408.99" - wire $and$ls180.v:6408$2159_Y - attribute \src "ls180.v:6408.40-6408.150" - wire $and$ls180.v:6408$2161_Y - attribute \src "ls180.v:6410.45-6410.100" - wire $and$ls180.v:6410$2162_Y - attribute \src "ls180.v:6410.44-6410.151" - wire $and$ls180.v:6410$2164_Y - attribute \src "ls180.v:6411.45-6411.103" - wire $and$ls180.v:6411$2166_Y - attribute \src "ls180.v:6411.44-6411.154" - wire $and$ls180.v:6411$2168_Y - attribute \src "ls180.v:6413.46-6413.101" - wire $and$ls180.v:6413$2169_Y - attribute \src "ls180.v:6413.45-6413.152" - wire $and$ls180.v:6413$2171_Y - attribute \src "ls180.v:6414.46-6414.104" - wire $and$ls180.v:6414$2173_Y - attribute \src "ls180.v:6414.45-6414.155" - wire $and$ls180.v:6414$2175_Y - attribute \src "ls180.v:6416.44-6416.99" - wire $and$ls180.v:6416$2176_Y - attribute \src "ls180.v:6416.43-6416.150" - wire $and$ls180.v:6416$2178_Y - attribute \src "ls180.v:6417.44-6417.102" - wire $and$ls180.v:6417$2180_Y - attribute \src "ls180.v:6417.43-6417.153" - wire $and$ls180.v:6417$2182_Y - attribute \src "ls180.v:6419.41-6419.96" - wire $and$ls180.v:6419$2183_Y - attribute \src "ls180.v:6419.40-6419.147" - wire $and$ls180.v:6419$2185_Y - attribute \src "ls180.v:6420.41-6420.99" - wire $and$ls180.v:6420$2187_Y - attribute \src "ls180.v:6420.40-6420.150" - wire $and$ls180.v:6420$2189_Y - attribute \src "ls180.v:6422.40-6422.95" - wire $and$ls180.v:6422$2190_Y - attribute \src "ls180.v:6422.39-6422.146" - wire $and$ls180.v:6422$2192_Y - attribute \src "ls180.v:6423.40-6423.98" - wire $and$ls180.v:6423$2194_Y - attribute \src "ls180.v:6423.39-6423.149" - wire $and$ls180.v:6423$2196_Y - attribute \src "ls180.v:6435.46-6435.101" - wire $and$ls180.v:6435$2198_Y - attribute \src "ls180.v:6435.45-6435.152" - wire $and$ls180.v:6435$2200_Y - attribute \src "ls180.v:6436.46-6436.104" - wire $and$ls180.v:6436$2202_Y - attribute \src "ls180.v:6436.45-6436.155" - wire $and$ls180.v:6436$2204_Y - attribute \src "ls180.v:6438.46-6438.101" - wire $and$ls180.v:6438$2205_Y - attribute \src "ls180.v:6438.45-6438.152" - wire $and$ls180.v:6438$2207_Y - attribute \src "ls180.v:6439.46-6439.104" - wire $and$ls180.v:6439$2209_Y - attribute \src "ls180.v:6439.45-6439.155" - wire $and$ls180.v:6439$2211_Y - attribute \src "ls180.v:6441.46-6441.101" - wire $and$ls180.v:6441$2212_Y - attribute \src "ls180.v:6441.45-6441.152" - wire $and$ls180.v:6441$2214_Y - attribute \src "ls180.v:6442.46-6442.104" - wire $and$ls180.v:6442$2216_Y - attribute \src "ls180.v:6442.45-6442.155" - wire $and$ls180.v:6442$2218_Y - attribute \src "ls180.v:6444.46-6444.101" - wire $and$ls180.v:6444$2219_Y - attribute \src "ls180.v:6444.45-6444.152" - wire $and$ls180.v:6444$2221_Y - attribute \src "ls180.v:6445.46-6445.104" - wire $and$ls180.v:6445$2223_Y - attribute \src "ls180.v:6445.45-6445.155" - wire $and$ls180.v:6445$2225_Y - attribute \src "ls180.v:6826.109-6826.178" - wire $and$ls180.v:6826$2263_Y - attribute \src "ls180.v:6826.184-6826.253" - wire $and$ls180.v:6826$2266_Y - attribute \src "ls180.v:6826.259-6826.328" - wire $and$ls180.v:6826$2269_Y - attribute \src "ls180.v:6826.40-6826.331" - wire $and$ls180.v:6826$2272_Y - attribute \src "ls180.v:6826.39-6826.354" - wire $and$ls180.v:6826$2273_Y - attribute \src "ls180.v:6850.109-6850.178" - wire $and$ls180.v:6850$2279_Y - attribute \src "ls180.v:6850.184-6850.253" - wire $and$ls180.v:6850$2282_Y - attribute \src "ls180.v:6850.259-6850.328" - wire $and$ls180.v:6850$2285_Y - attribute \src "ls180.v:6850.40-6850.331" - wire $and$ls180.v:6850$2288_Y - attribute \src "ls180.v:6850.39-6850.354" - wire $and$ls180.v:6850$2289_Y - attribute \src "ls180.v:6874.109-6874.178" - wire $and$ls180.v:6874$2295_Y - attribute \src "ls180.v:6874.184-6874.253" - wire $and$ls180.v:6874$2298_Y - attribute \src "ls180.v:6874.259-6874.328" - wire $and$ls180.v:6874$2301_Y - attribute \src "ls180.v:6874.40-6874.331" - wire $and$ls180.v:6874$2304_Y - attribute \src "ls180.v:6874.39-6874.354" - wire $and$ls180.v:6874$2305_Y - attribute \src "ls180.v:6898.109-6898.178" - wire $and$ls180.v:6898$2311_Y - attribute \src "ls180.v:6898.184-6898.253" - wire $and$ls180.v:6898$2314_Y - attribute \src "ls180.v:6898.259-6898.328" - wire $and$ls180.v:6898$2317_Y - attribute \src "ls180.v:6898.40-6898.331" - wire $and$ls180.v:6898$2320_Y - attribute \src "ls180.v:6898.39-6898.354" - wire $and$ls180.v:6898$2321_Y - attribute \src "ls180.v:7103.39-7103.104" - wire $and$ls180.v:7103$2333_Y - attribute \src "ls180.v:7103.38-7103.145" - wire $and$ls180.v:7103$2334_Y - attribute \src "ls180.v:7106.39-7106.104" - wire $and$ls180.v:7106$2335_Y - attribute \src "ls180.v:7106.38-7106.145" - wire $and$ls180.v:7106$2336_Y - attribute \src "ls180.v:7109.39-7109.82" - wire $and$ls180.v:7109$2337_Y - attribute \src "ls180.v:7109.38-7109.112" - wire $and$ls180.v:7109$2338_Y - attribute \src "ls180.v:7120.39-7120.104" - wire $and$ls180.v:7120$2340_Y - attribute \src "ls180.v:7120.38-7120.145" - wire $and$ls180.v:7120$2341_Y - attribute \src "ls180.v:7123.39-7123.104" - wire $and$ls180.v:7123$2342_Y - attribute \src "ls180.v:7123.38-7123.145" - wire $and$ls180.v:7123$2343_Y - attribute \src "ls180.v:7126.39-7126.82" - wire $and$ls180.v:7126$2344_Y - attribute \src "ls180.v:7126.38-7126.112" - wire $and$ls180.v:7126$2345_Y - attribute \src "ls180.v:7137.39-7137.104" - wire $and$ls180.v:7137$2347_Y - attribute \src "ls180.v:7137.38-7137.144" - wire $and$ls180.v:7137$2348_Y - attribute \src "ls180.v:7140.39-7140.104" - wire $and$ls180.v:7140$2349_Y - attribute \src "ls180.v:7140.38-7140.144" - wire $and$ls180.v:7140$2350_Y - attribute \src "ls180.v:7143.39-7143.82" - wire $and$ls180.v:7143$2351_Y - attribute \src "ls180.v:7143.38-7143.111" - wire $and$ls180.v:7143$2352_Y - attribute \src "ls180.v:7154.39-7154.104" - wire $and$ls180.v:7154$2354_Y - attribute \src "ls180.v:7154.38-7154.149" - wire $and$ls180.v:7154$2355_Y - attribute \src "ls180.v:7157.39-7157.104" - wire $and$ls180.v:7157$2356_Y - attribute \src "ls180.v:7157.38-7157.149" - wire $and$ls180.v:7157$2357_Y - attribute \src "ls180.v:7160.39-7160.82" - wire $and$ls180.v:7160$2358_Y - attribute \src "ls180.v:7160.38-7160.116" - wire $and$ls180.v:7160$2359_Y - attribute \src "ls180.v:7171.39-7171.104" - wire $and$ls180.v:7171$2361_Y - attribute \src "ls180.v:7171.38-7171.150" - wire $and$ls180.v:7171$2362_Y - attribute \src "ls180.v:7174.39-7174.104" - wire $and$ls180.v:7174$2363_Y - attribute \src "ls180.v:7174.38-7174.150" - wire $and$ls180.v:7174$2364_Y - attribute \src "ls180.v:7177.39-7177.82" - wire $and$ls180.v:7177$2365_Y - attribute \src "ls180.v:7177.38-7177.117" - wire $and$ls180.v:7177$2366_Y - attribute \src "ls180.v:7396.17-7396.67" - wire $and$ls180.v:7396$2373_Y - attribute \src "ls180.v:7487.8-7487.67" - wire $and$ls180.v:7487$2416_Y - attribute \src "ls180.v:7487.7-7487.102" - wire $and$ls180.v:7487$2418_Y - attribute \src "ls180.v:7506.7-7506.75" - wire $and$ls180.v:7506$2422_Y - attribute \src "ls180.v:7514.7-7514.56" - wire $and$ls180.v:7514$2424_Y - attribute \src "ls180.v:7542.7-7542.75" - wire $and$ls180.v:7542$2431_Y - attribute \src "ls180.v:7584.8-7584.131" - wire $and$ls180.v:7584$2437_Y - attribute \src "ls180.v:7584.7-7584.190" - wire $and$ls180.v:7584$2439_Y - attribute \src "ls180.v:7590.8-7590.131" - wire $and$ls180.v:7590$2442_Y - attribute \src "ls180.v:7590.7-7590.190" - wire $and$ls180.v:7590$2444_Y - attribute \src "ls180.v:7630.8-7630.131" - wire $and$ls180.v:7630$2453_Y - attribute \src "ls180.v:7630.7-7630.190" - wire $and$ls180.v:7630$2455_Y - attribute \src "ls180.v:7636.8-7636.131" - wire $and$ls180.v:7636$2458_Y - attribute \src "ls180.v:7636.7-7636.190" - wire $and$ls180.v:7636$2460_Y - attribute \src "ls180.v:7676.8-7676.131" - wire $and$ls180.v:7676$2469_Y - attribute \src "ls180.v:7676.7-7676.190" - wire $and$ls180.v:7676$2471_Y - attribute \src "ls180.v:7682.8-7682.131" - wire $and$ls180.v:7682$2474_Y - attribute \src "ls180.v:7682.7-7682.190" - wire $and$ls180.v:7682$2476_Y - attribute \src "ls180.v:7722.8-7722.131" - wire $and$ls180.v:7722$2485_Y - attribute \src "ls180.v:7722.7-7722.190" - wire $and$ls180.v:7722$2487_Y - attribute \src "ls180.v:7728.8-7728.131" - wire $and$ls180.v:7728$2490_Y - attribute \src "ls180.v:7728.7-7728.190" - wire $and$ls180.v:7728$2492_Y - attribute \src "ls180.v:7925.48-7925.124" - wire $and$ls180.v:7925$2517_Y - attribute \src "ls180.v:7925.130-7925.206" - wire $and$ls180.v:7925$2520_Y - attribute \src "ls180.v:7925.212-7925.288" - wire $and$ls180.v:7925$2523_Y - attribute \src "ls180.v:7925.294-7925.370" - wire $and$ls180.v:7925$2526_Y - attribute \src "ls180.v:7926.49-7926.125" - wire $and$ls180.v:7926$2529_Y - attribute \src "ls180.v:7926.131-7926.207" - wire $and$ls180.v:7926$2532_Y - attribute \src "ls180.v:7926.213-7926.289" - wire $and$ls180.v:7926$2535_Y - attribute \src "ls180.v:7926.295-7926.371" - wire $and$ls180.v:7926$2538_Y - attribute \src "ls180.v:7945.8-7945.49" - wire $and$ls180.v:7945$2541_Y - attribute \src "ls180.v:7948.8-7948.53" - wire $and$ls180.v:7948$2542_Y - attribute \src "ls180.v:7953.8-7953.59" - wire $and$ls180.v:7953$2544_Y - attribute \src "ls180.v:7953.7-7953.90" - wire $and$ls180.v:7953$2546_Y - attribute \src "ls180.v:7959.8-7959.59" - wire $and$ls180.v:7959$2547_Y - attribute \src "ls180.v:7983.8-7983.48" - wire $and$ls180.v:7983$2554_Y - attribute \src "ls180.v:8016.7-8016.57" - wire $and$ls180.v:8016$2560_Y - attribute \src "ls180.v:8023.7-8023.57" - wire $and$ls180.v:8023$2562_Y - attribute \src "ls180.v:8033.8-8033.75" - wire $and$ls180.v:8033$2563_Y - attribute \src "ls180.v:8033.7-8033.107" - wire $and$ls180.v:8033$2565_Y - attribute \src "ls180.v:8039.8-8039.75" - wire $and$ls180.v:8039$2568_Y - attribute \src "ls180.v:8039.7-8039.107" - wire $and$ls180.v:8039$2570_Y - attribute \src "ls180.v:8055.8-8055.75" - wire $and$ls180.v:8055$2574_Y - attribute \src "ls180.v:8055.7-8055.107" - wire $and$ls180.v:8055$2576_Y - attribute \src "ls180.v:8061.8-8061.75" - wire $and$ls180.v:8061$2579_Y - attribute \src "ls180.v:8061.7-8061.107" - wire $and$ls180.v:8061$2581_Y - attribute \src "ls180.v:8174.7-8174.96" - wire $and$ls180.v:8174$2604_Y - attribute \src "ls180.v:8175.8-8175.93" - wire $and$ls180.v:8175$2605_Y - attribute \src "ls180.v:8183.8-8183.93" - wire $and$ls180.v:8183$2606_Y - attribute \src "ls180.v:8255.7-8255.98" - wire $and$ls180.v:8255$2616_Y - attribute \src "ls180.v:8256.8-8256.95" - wire $and$ls180.v:8256$2617_Y - attribute \src "ls180.v:8264.8-8264.95" - wire $and$ls180.v:8264$2618_Y - attribute \src "ls180.v:8334.7-8334.100" - wire $and$ls180.v:8334$2628_Y - attribute \src "ls180.v:8335.8-8335.97" - wire $and$ls180.v:8335$2629_Y - attribute \src "ls180.v:8343.8-8343.97" - wire $and$ls180.v:8343$2630_Y - attribute \src "ls180.v:8434.7-8434.82" - wire $and$ls180.v:8434$2636_Y - attribute \src "ls180.v:8437.7-8437.82" - wire $and$ls180.v:8437$2637_Y - attribute \src "ls180.v:8440.7-8440.82" - wire $and$ls180.v:8440$2638_Y - attribute \src "ls180.v:8443.7-8443.82" - wire $and$ls180.v:8443$2639_Y - attribute \src "ls180.v:8446.7-8446.82" - wire $and$ls180.v:8446$2640_Y - attribute \src "ls180.v:8451.7-8451.82" - wire $and$ls180.v:8451$2641_Y - attribute \src "ls180.v:8456.7-8456.82" - wire $and$ls180.v:8456$2642_Y - attribute \src "ls180.v:8461.7-8461.82" - wire $and$ls180.v:8461$2643_Y - attribute \src "ls180.v:8466.7-8466.82" - wire $and$ls180.v:8466$2644_Y - attribute \src "ls180.v:8531.8-8531.83" - wire $and$ls180.v:8531$2647_Y - attribute \src "ls180.v:8531.7-8531.119" - wire $and$ls180.v:8531$2649_Y - attribute \src "ls180.v:8537.8-8537.83" - wire $and$ls180.v:8537$2652_Y - attribute \src "ls180.v:8537.7-8537.119" - wire $and$ls180.v:8537$2654_Y - attribute \src "ls180.v:8557.7-8557.88" - wire $and$ls180.v:8557$2661_Y - attribute \src "ls180.v:8558.8-8558.85" - wire $and$ls180.v:8558$2662_Y - attribute \src "ls180.v:8566.8-8566.85" - wire $and$ls180.v:8566$2663_Y - attribute \src "ls180.v:8610.7-8610.88" - wire $and$ls180.v:8610$2667_Y - attribute \src "ls180.v:8617.8-8617.83" - wire $and$ls180.v:8617$2669_Y - attribute \src "ls180.v:8617.7-8617.119" - wire $and$ls180.v:8617$2671_Y - attribute \src "ls180.v:8623.8-8623.83" - wire $and$ls180.v:8623$2674_Y - attribute \src "ls180.v:8623.7-8623.119" - wire $and$ls180.v:8623$2676_Y - attribute \src "ls180.v:2794.42-2794.101" - wire $eq$ls180.v:2794$18_Y - attribute \src "ls180.v:2801.11-2801.54" - wire $eq$ls180.v:2801$23_Y - attribute \src "ls180.v:2854.42-2854.101" - wire $eq$ls180.v:2854$29_Y - attribute \src "ls180.v:2861.11-2861.54" - wire $eq$ls180.v:2861$34_Y - attribute \src "ls180.v:2914.42-2914.101" - wire $eq$ls180.v:2914$40_Y - attribute \src "ls180.v:2921.11-2921.54" - wire $eq$ls180.v:2921$45_Y - attribute \src "ls180.v:3107.34-3107.65" - wire $eq$ls180.v:3107$73_Y - attribute \src "ls180.v:3111.68-3111.102" - wire $eq$ls180.v:3111$76_Y - attribute \src "ls180.v:3155.43-3155.134" - wire $eq$ls180.v:3155$81_Y - attribute \src "ls180.v:3172.47-3172.88" - wire $eq$ls180.v:3172$94_Y - attribute \src "ls180.v:3312.43-3312.134" - wire $eq$ls180.v:3312$111_Y - attribute \src "ls180.v:3329.47-3329.88" - wire $eq$ls180.v:3329$124_Y - attribute \src "ls180.v:3469.43-3469.134" - wire $eq$ls180.v:3469$141_Y - attribute \src "ls180.v:3486.47-3486.88" - wire $eq$ls180.v:3486$154_Y - attribute \src "ls180.v:3626.43-3626.134" - wire $eq$ls180.v:3626$171_Y - attribute \src "ls180.v:3643.47-3643.88" - wire $eq$ls180.v:3643$184_Y - attribute \src "ls180.v:3780.32-3780.56" - wire $eq$ls180.v:3780$231_Y - attribute \src "ls180.v:3781.32-3781.56" - wire $eq$ls180.v:3781$232_Y - attribute \src "ls180.v:3792.339-3792.418" - wire $eq$ls180.v:3792$246_Y - attribute \src "ls180.v:3792.423-3792.504" - wire $eq$ls180.v:3792$247_Y - attribute \src "ls180.v:3793.339-3793.418" - wire $eq$ls180.v:3793$259_Y - attribute \src "ls180.v:3793.423-3793.504" - wire $eq$ls180.v:3793$260_Y - attribute \src "ls180.v:3794.339-3794.418" - wire $eq$ls180.v:3794$272_Y - attribute \src "ls180.v:3794.423-3794.504" - wire $eq$ls180.v:3794$273_Y - attribute \src "ls180.v:3795.339-3795.418" - wire $eq$ls180.v:3795$285_Y - attribute \src "ls180.v:3795.423-3795.504" - wire $eq$ls180.v:3795$286_Y - attribute \src "ls180.v:3825.339-3825.418" - wire $eq$ls180.v:3825$304_Y - attribute \src "ls180.v:3825.423-3825.504" - wire $eq$ls180.v:3825$305_Y - attribute \src "ls180.v:3826.339-3826.418" - wire $eq$ls180.v:3826$317_Y - attribute \src "ls180.v:3826.423-3826.504" - wire $eq$ls180.v:3826$318_Y - attribute \src "ls180.v:3827.339-3827.418" - wire $eq$ls180.v:3827$330_Y - attribute \src "ls180.v:3827.423-3827.504" - wire $eq$ls180.v:3827$331_Y - attribute \src "ls180.v:3828.339-3828.418" - wire $eq$ls180.v:3828$343_Y - attribute \src "ls180.v:3828.423-3828.504" - wire $eq$ls180.v:3828$344_Y - attribute \src "ls180.v:3857.78-3857.113" - wire $eq$ls180.v:3857$353_Y - attribute \src "ls180.v:3860.78-3860.113" - wire $eq$ls180.v:3860$356_Y - attribute \src "ls180.v:3866.78-3866.113" - wire $eq$ls180.v:3866$360_Y - attribute \src "ls180.v:3869.78-3869.113" - wire $eq$ls180.v:3869$363_Y - attribute \src "ls180.v:3875.78-3875.113" - wire $eq$ls180.v:3875$367_Y - attribute \src "ls180.v:3878.78-3878.113" - wire $eq$ls180.v:3878$370_Y - attribute \src "ls180.v:3884.78-3884.113" - wire $eq$ls180.v:3884$374_Y - attribute \src "ls180.v:3887.78-3887.113" - wire $eq$ls180.v:3887$377_Y - attribute \src "ls180.v:3968.42-3968.82" - wire $eq$ls180.v:3968$400_Y - attribute \src "ls180.v:3968.145-3968.178" - wire $eq$ls180.v:3968$401_Y - attribute \src "ls180.v:3968.220-3968.253" - wire $eq$ls180.v:3968$404_Y - attribute \src "ls180.v:3968.295-3968.328" - wire $eq$ls180.v:3968$407_Y - attribute \src "ls180.v:3973.42-3973.82" - wire $eq$ls180.v:3973$416_Y - attribute \src "ls180.v:3973.145-3973.178" - wire $eq$ls180.v:3973$417_Y - attribute \src "ls180.v:3973.220-3973.253" - wire $eq$ls180.v:3973$420_Y - attribute \src "ls180.v:3973.295-3973.328" - wire $eq$ls180.v:3973$423_Y - attribute \src "ls180.v:3978.42-3978.82" - wire $eq$ls180.v:3978$432_Y - attribute \src "ls180.v:3978.145-3978.178" - wire $eq$ls180.v:3978$433_Y - attribute \src "ls180.v:3978.220-3978.253" - wire $eq$ls180.v:3978$436_Y - attribute \src "ls180.v:3978.295-3978.328" - wire $eq$ls180.v:3978$439_Y - attribute \src "ls180.v:3983.42-3983.82" - wire $eq$ls180.v:3983$448_Y - attribute \src "ls180.v:3983.145-3983.178" - wire $eq$ls180.v:3983$449_Y - attribute \src "ls180.v:3983.220-3983.253" - wire $eq$ls180.v:3983$452_Y - attribute \src "ls180.v:3983.295-3983.328" - wire $eq$ls180.v:3983$455_Y - attribute \src "ls180.v:3988.44-3988.77" - wire $eq$ls180.v:3988$464_Y - attribute \src "ls180.v:3988.83-3988.123" - wire $eq$ls180.v:3988$465_Y - attribute \src "ls180.v:3988.186-3988.219" - wire $eq$ls180.v:3988$466_Y - attribute \src "ls180.v:3988.261-3988.294" - wire $eq$ls180.v:3988$469_Y - attribute \src "ls180.v:3988.336-3988.369" - wire $eq$ls180.v:3988$472_Y - attribute \src "ls180.v:3988.418-3988.451" - wire $eq$ls180.v:3988$480_Y - attribute \src "ls180.v:3988.457-3988.497" - wire $eq$ls180.v:3988$481_Y - attribute \src "ls180.v:3988.560-3988.593" - wire $eq$ls180.v:3988$482_Y - attribute \src "ls180.v:3988.635-3988.668" - wire $eq$ls180.v:3988$485_Y - attribute \src "ls180.v:3988.710-3988.743" - wire $eq$ls180.v:3988$488_Y - attribute \src "ls180.v:3988.792-3988.825" - wire $eq$ls180.v:3988$496_Y - attribute \src "ls180.v:3988.831-3988.871" - wire $eq$ls180.v:3988$497_Y - attribute \src "ls180.v:3988.934-3988.967" - wire $eq$ls180.v:3988$498_Y - attribute \src "ls180.v:3988.1009-3988.1042" - wire $eq$ls180.v:3988$501_Y - attribute \src "ls180.v:3988.1084-3988.1117" - wire $eq$ls180.v:3988$504_Y - attribute \src "ls180.v:3988.1166-3988.1199" - wire $eq$ls180.v:3988$512_Y - attribute \src "ls180.v:3988.1205-3988.1245" - wire $eq$ls180.v:3988$513_Y - attribute \src "ls180.v:3988.1308-3988.1341" - wire $eq$ls180.v:3988$514_Y - attribute \src "ls180.v:3988.1383-3988.1416" - wire $eq$ls180.v:3988$517_Y - attribute \src "ls180.v:3988.1458-3988.1491" - wire $eq$ls180.v:3988$520_Y - attribute \src "ls180.v:4047.29-4047.57" - wire $eq$ls180.v:4047$533_Y - attribute \src "ls180.v:4054.11-4054.41" - wire $eq$ls180.v:4054$538_Y - attribute \src "ls180.v:4211.36-4211.111" - wire $eq$ls180.v:4211$603_Y - attribute \src "ls180.v:4212.36-4212.105" - wire $eq$ls180.v:4212$605_Y - attribute \src "ls180.v:4239.10-4239.67" - wire $eq$ls180.v:4239$609_Y - attribute \src "ls180.v:4343.10-4343.40" - wire $eq$ls180.v:4343$636_Y - attribute \src "ls180.v:4400.10-4400.39" - wire $eq$ls180.v:4400$639_Y - attribute \src "ls180.v:4417.10-4417.39" - wire $eq$ls180.v:4417$641_Y - attribute \src "ls180.v:4445.38-4445.88" - wire $eq$ls180.v:4445$643_Y - attribute \src "ls180.v:4495.9-4495.40" - wire $eq$ls180.v:4495$653_Y - attribute \src "ls180.v:4504.36-4504.105" - wire $eq$ls180.v:4504$655_Y - attribute \src "ls180.v:4523.9-4523.40" - wire $eq$ls180.v:4523$659_Y - attribute \src "ls180.v:4535.10-4535.39" - wire $eq$ls180.v:4535$661_Y - attribute \src "ls180.v:4572.39-4572.94" - wire $eq$ls180.v:4572$665_Y - attribute \src "ls180.v:4609.32-4609.89" - wire $eq$ls180.v:4609$674_Y - attribute \src "ls180.v:4657.10-4657.40" - wire $eq$ls180.v:4657$678_Y - attribute \src "ls180.v:4706.40-4706.98" - wire $eq$ls180.v:4706$680_Y - attribute \src "ls180.v:4757.9-4757.41" - wire $eq$ls180.v:4757$690_Y - attribute \src "ls180.v:4766.37-4766.123" - wire $eq$ls180.v:4766$693_Y - attribute \src "ls180.v:4789.9-4789.41" - wire $eq$ls180.v:4789$696_Y - attribute \src "ls180.v:4799.10-4799.41" - wire $eq$ls180.v:4799$698_Y - attribute \src "ls180.v:4968.9-4968.47" - wire $eq$ls180.v:4968$880_Y - attribute \src "ls180.v:4998.10-4998.48" - wire $eq$ls180.v:4998$881_Y - attribute \src "ls180.v:5029.10-5029.78" - wire $eq$ls180.v:5029$886_Y - attribute \src "ls180.v:5029.83-5029.151" - wire $eq$ls180.v:5029$887_Y - attribute \src "ls180.v:5029.157-5029.225" - wire $eq$ls180.v:5029$889_Y - attribute \src "ls180.v:5029.231-5029.299" - wire $eq$ls180.v:5029$891_Y - attribute \src "ls180.v:5037.7-5037.44" - wire $eq$ls180.v:5037$895_Y - attribute \src "ls180.v:5047.7-5047.44" - wire $eq$ls180.v:5047$898_Y - attribute \src "ls180.v:5057.7-5057.44" - wire $eq$ls180.v:5057$901_Y - attribute \src "ls180.v:5067.7-5067.44" - wire $eq$ls180.v:5067$904_Y - attribute \src "ls180.v:5191.36-5191.64" - wire $eq$ls180.v:5191$955_Y - attribute \src "ls180.v:5197.10-5197.39" - wire $eq$ls180.v:5197$958_Y - attribute \src "ls180.v:5198.11-5198.39" - wire $eq$ls180.v:5198$959_Y - attribute \src "ls180.v:5210.34-5210.63" - wire $eq$ls180.v:5210$960_Y - attribute \src "ls180.v:5211.9-5211.37" - wire $eq$ls180.v:5211$961_Y - attribute \src "ls180.v:5218.10-5218.55" - wire $eq$ls180.v:5218$962_Y - attribute \src "ls180.v:5224.12-5224.41" - wire $eq$ls180.v:5224$963_Y - attribute \src "ls180.v:5227.13-5227.42" - wire $eq$ls180.v:5227$964_Y - attribute \src "ls180.v:5249.10-5249.76" - wire $eq$ls180.v:5249$969_Y - attribute \src "ls180.v:5264.35-5264.101" - wire $eq$ls180.v:5264$972_Y - attribute \src "ls180.v:5266.10-5266.56" - wire $eq$ls180.v:5266$973_Y - attribute \src "ls180.v:5275.12-5275.78" - wire $eq$ls180.v:5275$977_Y - attribute \src "ls180.v:5282.11-5282.57" - wire $eq$ls180.v:5282$978_Y - attribute \src "ls180.v:5399.10-5399.105" - wire $eq$ls180.v:5399$995_Y - attribute \src "ls180.v:5489.39-5489.106" - wire $eq$ls180.v:5489$1001_Y - attribute \src "ls180.v:5519.44-5519.82" - wire $eq$ls180.v:5519$1004_Y - attribute \src "ls180.v:5520.43-5520.81" - wire $eq$ls180.v:5520$1005_Y - attribute \src "ls180.v:5577.32-5577.99" - wire $eq$ls180.v:5577$1018_Y - attribute \src "ls180.v:5578.32-5578.93" - wire $eq$ls180.v:5578$1020_Y - attribute \src "ls180.v:5606.10-5606.59" - wire $eq$ls180.v:5606$1024_Y - attribute \src "ls180.v:5679.85-5679.106" - wire $eq$ls180.v:5679$1029_Y - attribute \src "ls180.v:5680.85-5680.106" - wire $eq$ls180.v:5680$1031_Y - attribute \src "ls180.v:5681.85-5681.106" - wire $eq$ls180.v:5681$1033_Y - attribute \src "ls180.v:5682.57-5682.78" - wire $eq$ls180.v:5682$1035_Y - attribute \src "ls180.v:5683.57-5683.78" - wire $eq$ls180.v:5683$1037_Y - attribute \src "ls180.v:5684.85-5684.106" - wire $eq$ls180.v:5684$1039_Y - attribute \src "ls180.v:5685.85-5685.106" - wire $eq$ls180.v:5685$1041_Y - attribute \src "ls180.v:5686.85-5686.106" - wire $eq$ls180.v:5686$1043_Y - attribute \src "ls180.v:5687.57-5687.78" - wire $eq$ls180.v:5687$1045_Y - attribute \src "ls180.v:5688.57-5688.78" - wire $eq$ls180.v:5688$1047_Y - attribute \src "ls180.v:5692.27-5692.59" - wire $eq$ls180.v:5692$1050_Y - attribute \src "ls180.v:5693.27-5693.68" - wire $eq$ls180.v:5693$1051_Y - attribute \src "ls180.v:5694.27-5694.66" - wire $eq$ls180.v:5694$1052_Y - attribute \src "ls180.v:5695.27-5695.61" - wire $eq$ls180.v:5695$1053_Y - attribute \src "ls180.v:5696.27-5696.65" - wire $eq$ls180.v:5696$1054_Y - attribute \src "ls180.v:5752.24-5752.45" - wire $eq$ls180.v:5752$1081_Y - attribute \src "ls180.v:5753.32-5753.77" - wire $eq$ls180.v:5753$1082_Y - attribute \src "ls180.v:5755.97-5755.141" - wire $eq$ls180.v:5755$1084_Y - attribute \src "ls180.v:5756.100-5756.144" - wire $eq$ls180.v:5756$1088_Y - attribute \src "ls180.v:5758.99-5758.143" - wire $eq$ls180.v:5758$1091_Y - attribute \src "ls180.v:5759.102-5759.146" - wire $eq$ls180.v:5759$1095_Y - attribute \src "ls180.v:5761.99-5761.143" - wire $eq$ls180.v:5761$1098_Y - attribute \src "ls180.v:5762.102-5762.146" - wire $eq$ls180.v:5762$1102_Y - attribute \src "ls180.v:5764.99-5764.143" - wire $eq$ls180.v:5764$1105_Y - attribute \src "ls180.v:5765.102-5765.146" - wire $eq$ls180.v:5765$1109_Y - attribute \src "ls180.v:5767.99-5767.143" - wire $eq$ls180.v:5767$1112_Y - attribute \src "ls180.v:5768.102-5768.146" - wire $eq$ls180.v:5768$1116_Y - attribute \src "ls180.v:5770.102-5770.146" - wire $eq$ls180.v:5770$1119_Y - attribute \src "ls180.v:5771.105-5771.149" - wire $eq$ls180.v:5771$1123_Y - attribute \src "ls180.v:5773.102-5773.146" - wire $eq$ls180.v:5773$1126_Y - attribute \src "ls180.v:5774.105-5774.149" - wire $eq$ls180.v:5774$1130_Y - attribute \src "ls180.v:5776.102-5776.146" - wire $eq$ls180.v:5776$1133_Y - attribute \src "ls180.v:5777.105-5777.149" - wire $eq$ls180.v:5777$1137_Y - attribute \src "ls180.v:5779.102-5779.146" - wire $eq$ls180.v:5779$1140_Y - attribute \src "ls180.v:5780.105-5780.149" - wire $eq$ls180.v:5780$1144_Y - attribute \src "ls180.v:5791.32-5791.77" - wire $eq$ls180.v:5791$1146_Y - attribute \src "ls180.v:5793.94-5793.138" - wire $eq$ls180.v:5793$1148_Y - attribute \src "ls180.v:5794.97-5794.141" - wire $eq$ls180.v:5794$1152_Y - attribute \src "ls180.v:5796.94-5796.138" - wire $eq$ls180.v:5796$1155_Y - attribute \src "ls180.v:5797.97-5797.141" - wire $eq$ls180.v:5797$1159_Y - attribute \src "ls180.v:5799.94-5799.138" - wire $eq$ls180.v:5799$1162_Y - attribute \src "ls180.v:5800.97-5800.141" - wire $eq$ls180.v:5800$1166_Y - attribute \src "ls180.v:5802.94-5802.138" - wire $eq$ls180.v:5802$1169_Y - attribute \src "ls180.v:5803.97-5803.141" - wire $eq$ls180.v:5803$1173_Y - attribute \src "ls180.v:5805.95-5805.139" - wire $eq$ls180.v:5805$1176_Y - attribute \src "ls180.v:5806.98-5806.142" - wire $eq$ls180.v:5806$1180_Y - attribute \src "ls180.v:5808.95-5808.139" - wire $eq$ls180.v:5808$1183_Y - attribute \src "ls180.v:5809.98-5809.142" - wire $eq$ls180.v:5809$1187_Y - attribute \src "ls180.v:5817.32-5817.78" - wire $eq$ls180.v:5817$1189_Y - attribute \src "ls180.v:5819.93-5819.135" - wire $eq$ls180.v:5819$1191_Y - attribute \src "ls180.v:5820.96-5820.138" - wire $eq$ls180.v:5820$1195_Y - attribute \src "ls180.v:5822.92-5822.134" - wire $eq$ls180.v:5822$1198_Y - attribute \src "ls180.v:5823.95-5823.137" - wire $eq$ls180.v:5823$1202_Y - attribute \src "ls180.v:5831.32-5831.77" - wire $eq$ls180.v:5831$1204_Y - attribute \src "ls180.v:5833.98-5833.142" - wire $eq$ls180.v:5833$1206_Y - attribute \src "ls180.v:5834.101-5834.145" - wire $eq$ls180.v:5834$1210_Y - attribute \src "ls180.v:5836.97-5836.141" - wire $eq$ls180.v:5836$1213_Y - attribute \src "ls180.v:5837.100-5837.144" - wire $eq$ls180.v:5837$1217_Y - attribute \src "ls180.v:5839.97-5839.141" - wire $eq$ls180.v:5839$1220_Y - attribute \src "ls180.v:5840.100-5840.144" - wire $eq$ls180.v:5840$1224_Y - attribute \src "ls180.v:5842.97-5842.141" - wire $eq$ls180.v:5842$1227_Y - attribute \src "ls180.v:5843.100-5843.144" - wire $eq$ls180.v:5843$1231_Y - attribute \src "ls180.v:5845.97-5845.141" - wire $eq$ls180.v:5845$1234_Y - attribute \src "ls180.v:5846.100-5846.144" - wire $eq$ls180.v:5846$1238_Y - attribute \src "ls180.v:5848.98-5848.142" - wire $eq$ls180.v:5848$1241_Y - attribute \src "ls180.v:5849.101-5849.145" - wire $eq$ls180.v:5849$1245_Y - attribute \src "ls180.v:5851.98-5851.142" - wire $eq$ls180.v:5851$1248_Y - attribute \src "ls180.v:5852.101-5852.145" - wire $eq$ls180.v:5852$1252_Y - attribute \src "ls180.v:5854.98-5854.142" - wire $eq$ls180.v:5854$1255_Y - attribute \src "ls180.v:5855.101-5855.145" - wire $eq$ls180.v:5855$1259_Y - attribute \src "ls180.v:5857.98-5857.142" - wire $eq$ls180.v:5857$1262_Y - attribute \src "ls180.v:5858.101-5858.145" - wire $eq$ls180.v:5858$1266_Y - attribute \src "ls180.v:5868.32-5868.77" - wire $eq$ls180.v:5868$1268_Y - attribute \src "ls180.v:5870.98-5870.142" - wire $eq$ls180.v:5870$1270_Y - attribute \src "ls180.v:5871.101-5871.145" - wire $eq$ls180.v:5871$1274_Y - attribute \src "ls180.v:5873.97-5873.141" - wire $eq$ls180.v:5873$1277_Y - attribute \src "ls180.v:5874.100-5874.144" - wire $eq$ls180.v:5874$1281_Y - attribute \src "ls180.v:5876.97-5876.141" - wire $eq$ls180.v:5876$1284_Y - attribute \src "ls180.v:5877.100-5877.144" - wire $eq$ls180.v:5877$1288_Y - attribute \src "ls180.v:5879.97-5879.141" - wire $eq$ls180.v:5879$1291_Y - attribute \src "ls180.v:5880.100-5880.144" - wire $eq$ls180.v:5880$1295_Y - attribute \src "ls180.v:5882.97-5882.141" - wire $eq$ls180.v:5882$1298_Y - attribute \src "ls180.v:5883.100-5883.144" - wire $eq$ls180.v:5883$1302_Y - attribute \src "ls180.v:5885.98-5885.142" - wire $eq$ls180.v:5885$1305_Y - attribute \src "ls180.v:5886.101-5886.145" - wire $eq$ls180.v:5886$1309_Y - attribute \src "ls180.v:5888.98-5888.142" - wire $eq$ls180.v:5888$1312_Y - attribute \src "ls180.v:5889.101-5889.145" - wire $eq$ls180.v:5889$1316_Y - attribute \src "ls180.v:5891.98-5891.142" - wire $eq$ls180.v:5891$1319_Y - attribute \src "ls180.v:5892.101-5892.145" - wire $eq$ls180.v:5892$1323_Y - attribute \src "ls180.v:5894.98-5894.142" - wire $eq$ls180.v:5894$1326_Y - attribute \src "ls180.v:5895.101-5895.145" - wire $eq$ls180.v:5895$1330_Y - attribute \src "ls180.v:5905.32-5905.78" - wire $eq$ls180.v:5905$1332_Y - attribute \src "ls180.v:5907.100-5907.144" - wire $eq$ls180.v:5907$1334_Y - attribute \src "ls180.v:5908.103-5908.147" - wire $eq$ls180.v:5908$1338_Y - attribute \src "ls180.v:5910.100-5910.144" - wire $eq$ls180.v:5910$1341_Y - attribute \src "ls180.v:5911.103-5911.147" - wire $eq$ls180.v:5911$1345_Y - attribute \src "ls180.v:5913.100-5913.144" - wire $eq$ls180.v:5913$1348_Y - attribute \src "ls180.v:5914.103-5914.147" - wire $eq$ls180.v:5914$1352_Y - attribute \src "ls180.v:5916.100-5916.144" - wire $eq$ls180.v:5916$1355_Y - attribute \src "ls180.v:5917.103-5917.147" - wire $eq$ls180.v:5917$1359_Y - attribute \src "ls180.v:5919.100-5919.144" - wire $eq$ls180.v:5919$1362_Y - attribute \src "ls180.v:5920.103-5920.147" - wire $eq$ls180.v:5920$1366_Y - attribute \src "ls180.v:5922.100-5922.144" - wire $eq$ls180.v:5922$1369_Y - attribute \src "ls180.v:5923.103-5923.147" - wire $eq$ls180.v:5923$1373_Y - attribute \src "ls180.v:5925.100-5925.144" - wire $eq$ls180.v:5925$1376_Y - attribute \src "ls180.v:5926.103-5926.147" - wire $eq$ls180.v:5926$1380_Y - attribute \src "ls180.v:5928.100-5928.144" - wire $eq$ls180.v:5928$1383_Y - attribute \src "ls180.v:5929.103-5929.147" - wire $eq$ls180.v:5929$1387_Y - attribute \src "ls180.v:5931.102-5931.146" - wire $eq$ls180.v:5931$1390_Y - attribute \src "ls180.v:5932.105-5932.149" - wire $eq$ls180.v:5932$1394_Y - attribute \src "ls180.v:5934.102-5934.146" - wire $eq$ls180.v:5934$1397_Y - attribute \src "ls180.v:5935.105-5935.149" - wire $eq$ls180.v:5935$1401_Y - attribute \src "ls180.v:5937.102-5937.147" - wire $eq$ls180.v:5937$1404_Y - attribute \src "ls180.v:5938.105-5938.150" - wire $eq$ls180.v:5938$1408_Y - attribute \src "ls180.v:5940.102-5940.147" - wire $eq$ls180.v:5940$1411_Y - attribute \src "ls180.v:5941.105-5941.150" - wire $eq$ls180.v:5941$1415_Y - attribute \src "ls180.v:5943.102-5943.147" - wire $eq$ls180.v:5943$1418_Y - attribute \src "ls180.v:5944.105-5944.150" - wire $eq$ls180.v:5944$1422_Y - attribute \src "ls180.v:5946.99-5946.144" - wire $eq$ls180.v:5946$1425_Y - attribute \src "ls180.v:5947.102-5947.147" - wire $eq$ls180.v:5947$1429_Y - attribute \src "ls180.v:5949.100-5949.145" - wire $eq$ls180.v:5949$1432_Y - attribute \src "ls180.v:5950.103-5950.148" - wire $eq$ls180.v:5950$1436_Y - attribute \src "ls180.v:5967.32-5967.78" - wire $eq$ls180.v:5967$1438_Y - attribute \src "ls180.v:5969.104-5969.148" - wire $eq$ls180.v:5969$1440_Y - attribute \src "ls180.v:5970.107-5970.151" - wire $eq$ls180.v:5970$1444_Y - attribute \src "ls180.v:5972.104-5972.148" - wire $eq$ls180.v:5972$1447_Y - attribute \src "ls180.v:5973.107-5973.151" - wire $eq$ls180.v:5973$1451_Y - attribute \src "ls180.v:5975.104-5975.148" - wire $eq$ls180.v:5975$1454_Y - attribute \src "ls180.v:5976.107-5976.151" - wire $eq$ls180.v:5976$1458_Y - attribute \src "ls180.v:5978.104-5978.148" - wire $eq$ls180.v:5978$1461_Y - attribute \src "ls180.v:5979.107-5979.151" - wire $eq$ls180.v:5979$1465_Y - attribute \src "ls180.v:5981.103-5981.147" - wire $eq$ls180.v:5981$1468_Y - attribute \src "ls180.v:5982.106-5982.150" - wire $eq$ls180.v:5982$1472_Y - attribute \src "ls180.v:5984.103-5984.147" - wire $eq$ls180.v:5984$1475_Y - attribute \src "ls180.v:5985.106-5985.150" - wire $eq$ls180.v:5985$1479_Y - attribute \src "ls180.v:5987.103-5987.147" - wire $eq$ls180.v:5987$1482_Y - attribute \src "ls180.v:5988.106-5988.150" - wire $eq$ls180.v:5988$1486_Y - attribute \src "ls180.v:5990.103-5990.147" - wire $eq$ls180.v:5990$1489_Y - attribute \src "ls180.v:5991.106-5991.150" - wire $eq$ls180.v:5991$1493_Y - attribute \src "ls180.v:5993.94-5993.138" - wire $eq$ls180.v:5993$1496_Y - attribute \src "ls180.v:5994.97-5994.141" - wire $eq$ls180.v:5994$1500_Y - attribute \src "ls180.v:5996.105-5996.149" - wire $eq$ls180.v:5996$1503_Y - attribute \src "ls180.v:5997.108-5997.152" - wire $eq$ls180.v:5997$1507_Y - attribute \src "ls180.v:5999.105-5999.150" - wire $eq$ls180.v:5999$1510_Y - attribute \src "ls180.v:6000.108-6000.153" - wire $eq$ls180.v:6000$1514_Y - attribute \src "ls180.v:6002.105-6002.150" - wire $eq$ls180.v:6002$1517_Y - attribute \src "ls180.v:6003.108-6003.153" - wire $eq$ls180.v:6003$1521_Y - attribute \src "ls180.v:6005.105-6005.150" - wire $eq$ls180.v:6005$1524_Y - attribute \src "ls180.v:6006.108-6006.153" - wire $eq$ls180.v:6006$1528_Y - attribute \src "ls180.v:6008.105-6008.150" - wire $eq$ls180.v:6008$1531_Y - attribute \src "ls180.v:6009.108-6009.153" - wire $eq$ls180.v:6009$1535_Y - attribute \src "ls180.v:6011.105-6011.150" - wire $eq$ls180.v:6011$1538_Y - attribute \src "ls180.v:6012.108-6012.153" - wire $eq$ls180.v:6012$1542_Y - attribute \src "ls180.v:6014.104-6014.149" - wire $eq$ls180.v:6014$1545_Y - attribute \src "ls180.v:6015.107-6015.152" - wire $eq$ls180.v:6015$1549_Y - attribute \src "ls180.v:6017.104-6017.149" - wire $eq$ls180.v:6017$1552_Y - attribute \src "ls180.v:6018.107-6018.152" - wire $eq$ls180.v:6018$1556_Y - attribute \src "ls180.v:6020.104-6020.149" - wire $eq$ls180.v:6020$1559_Y - attribute \src "ls180.v:6021.107-6021.152" - wire $eq$ls180.v:6021$1563_Y - attribute \src "ls180.v:6023.104-6023.149" - wire $eq$ls180.v:6023$1566_Y - attribute \src "ls180.v:6024.107-6024.152" - wire $eq$ls180.v:6024$1570_Y - attribute \src "ls180.v:6026.104-6026.149" - wire $eq$ls180.v:6026$1573_Y - attribute \src "ls180.v:6027.107-6027.152" - wire $eq$ls180.v:6027$1577_Y - attribute \src "ls180.v:6029.104-6029.149" - wire $eq$ls180.v:6029$1580_Y - attribute \src "ls180.v:6030.107-6030.152" - wire $eq$ls180.v:6030$1584_Y - attribute \src "ls180.v:6032.104-6032.149" - wire $eq$ls180.v:6032$1587_Y - attribute \src "ls180.v:6033.107-6033.152" - wire $eq$ls180.v:6033$1591_Y - attribute \src "ls180.v:6035.104-6035.149" - wire $eq$ls180.v:6035$1594_Y - attribute \src "ls180.v:6036.107-6036.152" - wire $eq$ls180.v:6036$1598_Y - attribute \src "ls180.v:6038.104-6038.149" - wire $eq$ls180.v:6038$1601_Y - attribute \src "ls180.v:6039.107-6039.152" - wire $eq$ls180.v:6039$1605_Y - attribute \src "ls180.v:6041.104-6041.149" - wire $eq$ls180.v:6041$1608_Y - attribute \src "ls180.v:6042.107-6042.152" - wire $eq$ls180.v:6042$1612_Y - attribute \src "ls180.v:6044.100-6044.145" - wire $eq$ls180.v:6044$1615_Y - attribute \src "ls180.v:6045.103-6045.148" - wire $eq$ls180.v:6045$1619_Y - attribute \src "ls180.v:6047.101-6047.146" - wire $eq$ls180.v:6047$1622_Y - attribute \src "ls180.v:6048.104-6048.149" - wire $eq$ls180.v:6048$1626_Y - attribute \src "ls180.v:6050.104-6050.149" - wire $eq$ls180.v:6050$1629_Y - attribute \src "ls180.v:6051.107-6051.152" - wire $eq$ls180.v:6051$1633_Y - attribute \src "ls180.v:6053.104-6053.149" - wire $eq$ls180.v:6053$1636_Y - attribute \src "ls180.v:6054.107-6054.152" - wire $eq$ls180.v:6054$1640_Y - attribute \src "ls180.v:6056.103-6056.148" - wire $eq$ls180.v:6056$1643_Y - attribute \src "ls180.v:6057.106-6057.151" - wire $eq$ls180.v:6057$1647_Y - attribute \src "ls180.v:6059.103-6059.148" - wire $eq$ls180.v:6059$1650_Y - attribute \src "ls180.v:6060.106-6060.151" - wire $eq$ls180.v:6060$1654_Y - attribute \src "ls180.v:6062.103-6062.148" - wire $eq$ls180.v:6062$1657_Y - attribute \src "ls180.v:6063.106-6063.151" - wire $eq$ls180.v:6063$1661_Y - attribute \src "ls180.v:6065.103-6065.148" - wire $eq$ls180.v:6065$1664_Y - attribute \src "ls180.v:6066.106-6066.151" - wire $eq$ls180.v:6066$1668_Y - attribute \src "ls180.v:6102.32-6102.78" - wire $eq$ls180.v:6102$1670_Y - attribute \src "ls180.v:6104.100-6104.144" - wire $eq$ls180.v:6104$1672_Y - attribute \src "ls180.v:6105.103-6105.147" - wire $eq$ls180.v:6105$1676_Y - attribute \src "ls180.v:6107.100-6107.144" - wire $eq$ls180.v:6107$1679_Y - attribute \src "ls180.v:6108.103-6108.147" - wire $eq$ls180.v:6108$1683_Y - attribute \src "ls180.v:6110.100-6110.144" - wire $eq$ls180.v:6110$1686_Y - attribute \src "ls180.v:6111.103-6111.147" - wire $eq$ls180.v:6111$1690_Y - attribute \src "ls180.v:6113.100-6113.144" - wire $eq$ls180.v:6113$1693_Y - attribute \src "ls180.v:6114.103-6114.147" - wire $eq$ls180.v:6114$1697_Y - attribute \src "ls180.v:6116.100-6116.144" - wire $eq$ls180.v:6116$1700_Y - attribute \src "ls180.v:6117.103-6117.147" - wire $eq$ls180.v:6117$1704_Y - attribute \src "ls180.v:6119.100-6119.144" - wire $eq$ls180.v:6119$1707_Y - attribute \src "ls180.v:6120.103-6120.147" - wire $eq$ls180.v:6120$1711_Y - attribute \src "ls180.v:6122.100-6122.144" - wire $eq$ls180.v:6122$1714_Y - attribute \src "ls180.v:6123.103-6123.147" - wire $eq$ls180.v:6123$1718_Y - attribute \src "ls180.v:6125.100-6125.144" - wire $eq$ls180.v:6125$1721_Y - attribute \src "ls180.v:6126.103-6126.147" - wire $eq$ls180.v:6126$1725_Y - attribute \src "ls180.v:6128.102-6128.146" - wire $eq$ls180.v:6128$1728_Y - attribute \src "ls180.v:6129.105-6129.149" - wire $eq$ls180.v:6129$1732_Y - attribute \src "ls180.v:6131.102-6131.146" - wire $eq$ls180.v:6131$1735_Y - attribute \src "ls180.v:6132.105-6132.149" - wire $eq$ls180.v:6132$1739_Y - attribute \src "ls180.v:6134.102-6134.147" - wire $eq$ls180.v:6134$1742_Y - attribute \src "ls180.v:6135.105-6135.150" - wire $eq$ls180.v:6135$1746_Y - attribute \src "ls180.v:6137.102-6137.147" - wire $eq$ls180.v:6137$1749_Y - attribute \src "ls180.v:6138.105-6138.150" - wire $eq$ls180.v:6138$1753_Y - attribute \src "ls180.v:6140.102-6140.147" - wire $eq$ls180.v:6140$1756_Y - attribute \src "ls180.v:6141.105-6141.150" - wire $eq$ls180.v:6141$1760_Y - attribute \src "ls180.v:6143.99-6143.144" - wire $eq$ls180.v:6143$1763_Y - attribute \src "ls180.v:6144.102-6144.147" - wire $eq$ls180.v:6144$1767_Y - attribute \src "ls180.v:6146.100-6146.145" - wire $eq$ls180.v:6146$1770_Y - attribute \src "ls180.v:6147.103-6147.148" - wire $eq$ls180.v:6147$1774_Y - attribute \src "ls180.v:6149.102-6149.147" - wire $eq$ls180.v:6149$1777_Y - attribute \src "ls180.v:6150.105-6150.150" - wire $eq$ls180.v:6150$1781_Y - attribute \src "ls180.v:6152.102-6152.147" - wire $eq$ls180.v:6152$1784_Y - attribute \src "ls180.v:6153.105-6153.150" - wire $eq$ls180.v:6153$1788_Y - attribute \src "ls180.v:6155.102-6155.147" - wire $eq$ls180.v:6155$1791_Y - attribute \src "ls180.v:6156.105-6156.150" - wire $eq$ls180.v:6156$1795_Y - attribute \src "ls180.v:6158.102-6158.147" - wire $eq$ls180.v:6158$1798_Y - attribute \src "ls180.v:6159.105-6159.150" - wire $eq$ls180.v:6159$1802_Y - attribute \src "ls180.v:6181.32-6181.78" - wire $eq$ls180.v:6181$1804_Y - attribute \src "ls180.v:6183.102-6183.146" - wire $eq$ls180.v:6183$1806_Y - attribute \src "ls180.v:6184.105-6184.149" - wire $eq$ls180.v:6184$1810_Y - attribute \src "ls180.v:6186.107-6186.151" - wire $eq$ls180.v:6186$1813_Y - attribute \src "ls180.v:6187.110-6187.154" - wire $eq$ls180.v:6187$1817_Y - attribute \src "ls180.v:6189.107-6189.151" - wire $eq$ls180.v:6189$1820_Y - attribute \src "ls180.v:6190.110-6190.154" - wire $eq$ls180.v:6190$1824_Y - attribute \src "ls180.v:6192.100-6192.144" - wire $eq$ls180.v:6192$1827_Y - attribute \src "ls180.v:6193.103-6193.147" - wire $eq$ls180.v:6193$1831_Y - attribute \src "ls180.v:6198.32-6198.77" - wire $eq$ls180.v:6198$1833_Y - attribute \src "ls180.v:6200.104-6200.148" - wire $eq$ls180.v:6200$1835_Y - attribute \src "ls180.v:6201.107-6201.151" - wire $eq$ls180.v:6201$1839_Y - attribute \src "ls180.v:6203.108-6203.152" - wire $eq$ls180.v:6203$1842_Y - attribute \src "ls180.v:6204.111-6204.155" - wire $eq$ls180.v:6204$1846_Y - attribute \src "ls180.v:6206.98-6206.142" - wire $eq$ls180.v:6206$1849_Y - attribute \src "ls180.v:6207.101-6207.145" - wire $eq$ls180.v:6207$1853_Y - attribute \src "ls180.v:6209.108-6209.152" - wire $eq$ls180.v:6209$1856_Y - attribute \src "ls180.v:6210.111-6210.155" - wire $eq$ls180.v:6210$1860_Y - attribute \src "ls180.v:6212.108-6212.152" - wire $eq$ls180.v:6212$1863_Y - attribute \src "ls180.v:6213.111-6213.155" - wire $eq$ls180.v:6213$1867_Y - attribute \src "ls180.v:6215.109-6215.153" - wire $eq$ls180.v:6215$1870_Y - attribute \src "ls180.v:6216.112-6216.156" - wire $eq$ls180.v:6216$1874_Y - attribute \src "ls180.v:6218.107-6218.151" - wire $eq$ls180.v:6218$1877_Y - attribute \src "ls180.v:6219.110-6219.154" - wire $eq$ls180.v:6219$1881_Y - attribute \src "ls180.v:6221.107-6221.151" - wire $eq$ls180.v:6221$1884_Y - attribute \src "ls180.v:6222.110-6222.154" - wire $eq$ls180.v:6222$1888_Y - attribute \src "ls180.v:6224.107-6224.151" - wire $eq$ls180.v:6224$1891_Y - attribute \src "ls180.v:6225.110-6225.154" - wire $eq$ls180.v:6225$1895_Y - attribute \src "ls180.v:6227.107-6227.151" - wire $eq$ls180.v:6227$1898_Y - attribute \src "ls180.v:6228.110-6228.154" - wire $eq$ls180.v:6228$1902_Y - attribute \src "ls180.v:6243.33-6243.79" - wire $eq$ls180.v:6243$1904_Y - attribute \src "ls180.v:6245.102-6245.147" - wire $eq$ls180.v:6245$1906_Y - attribute \src "ls180.v:6246.105-6246.150" - wire $eq$ls180.v:6246$1910_Y - attribute \src "ls180.v:6248.102-6248.147" - wire $eq$ls180.v:6248$1913_Y - attribute \src "ls180.v:6249.105-6249.150" - wire $eq$ls180.v:6249$1917_Y - attribute \src "ls180.v:6251.100-6251.145" - wire $eq$ls180.v:6251$1920_Y - attribute \src "ls180.v:6252.103-6252.148" - wire $eq$ls180.v:6252$1924_Y - attribute \src "ls180.v:6254.99-6254.144" - wire $eq$ls180.v:6254$1927_Y - attribute \src "ls180.v:6255.102-6255.147" - wire $eq$ls180.v:6255$1931_Y - attribute \src "ls180.v:6257.98-6257.143" - wire $eq$ls180.v:6257$1934_Y - attribute \src "ls180.v:6258.101-6258.146" - wire $eq$ls180.v:6258$1938_Y - attribute \src "ls180.v:6260.97-6260.142" - wire $eq$ls180.v:6260$1941_Y - attribute \src "ls180.v:6261.100-6261.145" - wire $eq$ls180.v:6261$1945_Y - attribute \src "ls180.v:6263.103-6263.148" - wire $eq$ls180.v:6263$1948_Y - attribute \src "ls180.v:6264.106-6264.151" - wire $eq$ls180.v:6264$1952_Y - attribute \src "ls180.v:6283.33-6283.80" - wire $eq$ls180.v:6283$1955_Y - attribute \src "ls180.v:6285.102-6285.147" - wire $eq$ls180.v:6285$1957_Y - attribute \src "ls180.v:6286.105-6286.150" - wire $eq$ls180.v:6286$1961_Y - attribute \src "ls180.v:6288.102-6288.147" - wire $eq$ls180.v:6288$1964_Y - attribute \src "ls180.v:6289.105-6289.150" - wire $eq$ls180.v:6289$1968_Y - attribute \src "ls180.v:6291.100-6291.145" - wire $eq$ls180.v:6291$1971_Y - attribute \src "ls180.v:6292.103-6292.148" - wire $eq$ls180.v:6292$1975_Y - attribute \src "ls180.v:6294.99-6294.144" - wire $eq$ls180.v:6294$1978_Y - attribute \src "ls180.v:6295.102-6295.147" - wire $eq$ls180.v:6295$1982_Y - attribute \src "ls180.v:6297.98-6297.143" - wire $eq$ls180.v:6297$1985_Y - attribute \src "ls180.v:6298.101-6298.146" - wire $eq$ls180.v:6298$1989_Y - attribute \src "ls180.v:6300.97-6300.142" - wire $eq$ls180.v:6300$1992_Y - attribute \src "ls180.v:6301.100-6301.145" - wire $eq$ls180.v:6301$1996_Y - attribute \src "ls180.v:6303.103-6303.148" - wire $eq$ls180.v:6303$1999_Y - attribute \src "ls180.v:6304.106-6304.151" - wire $eq$ls180.v:6304$2003_Y - attribute \src "ls180.v:6306.106-6306.151" - wire $eq$ls180.v:6306$2006_Y - attribute \src "ls180.v:6307.109-6307.154" - wire $eq$ls180.v:6307$2010_Y - attribute \src "ls180.v:6309.106-6309.151" - wire $eq$ls180.v:6309$2013_Y - attribute \src "ls180.v:6310.109-6310.154" - wire $eq$ls180.v:6310$2017_Y - attribute \src "ls180.v:6331.33-6331.79" - wire $eq$ls180.v:6331$2020_Y - attribute \src "ls180.v:6333.99-6333.144" - wire $eq$ls180.v:6333$2022_Y - attribute \src "ls180.v:6334.102-6334.147" - wire $eq$ls180.v:6334$2026_Y - attribute \src "ls180.v:6336.99-6336.144" - wire $eq$ls180.v:6336$2029_Y - attribute \src "ls180.v:6337.102-6337.147" - wire $eq$ls180.v:6337$2033_Y - attribute \src "ls180.v:6339.99-6339.144" - wire $eq$ls180.v:6339$2036_Y - attribute \src "ls180.v:6340.102-6340.147" - wire $eq$ls180.v:6340$2040_Y - attribute \src "ls180.v:6342.99-6342.144" - wire $eq$ls180.v:6342$2043_Y - attribute \src "ls180.v:6343.102-6343.147" - wire $eq$ls180.v:6343$2047_Y - attribute \src "ls180.v:6345.101-6345.146" - wire $eq$ls180.v:6345$2050_Y - attribute \src "ls180.v:6346.104-6346.149" - wire $eq$ls180.v:6346$2054_Y - attribute \src "ls180.v:6348.101-6348.146" - wire $eq$ls180.v:6348$2057_Y - attribute \src "ls180.v:6349.104-6349.149" - wire $eq$ls180.v:6349$2061_Y - attribute \src "ls180.v:6351.101-6351.146" - wire $eq$ls180.v:6351$2064_Y - attribute \src "ls180.v:6352.104-6352.149" - wire $eq$ls180.v:6352$2068_Y - attribute \src "ls180.v:6354.101-6354.146" - wire $eq$ls180.v:6354$2071_Y - attribute \src "ls180.v:6355.104-6355.149" - wire $eq$ls180.v:6355$2075_Y - attribute \src "ls180.v:6357.97-6357.142" - wire $eq$ls180.v:6357$2078_Y - attribute \src "ls180.v:6358.100-6358.145" - wire $eq$ls180.v:6358$2082_Y - attribute \src "ls180.v:6360.107-6360.152" - wire $eq$ls180.v:6360$2085_Y - attribute \src "ls180.v:6361.110-6361.155" - wire $eq$ls180.v:6361$2089_Y - attribute \src "ls180.v:6363.100-6363.146" - wire $eq$ls180.v:6363$2092_Y - attribute \src "ls180.v:6364.103-6364.149" - wire $eq$ls180.v:6364$2096_Y - attribute \src "ls180.v:6366.100-6366.146" - wire $eq$ls180.v:6366$2099_Y - attribute \src "ls180.v:6367.103-6367.149" - wire $eq$ls180.v:6367$2103_Y - attribute \src "ls180.v:6369.100-6369.146" - wire $eq$ls180.v:6369$2106_Y - attribute \src "ls180.v:6370.103-6370.149" - wire $eq$ls180.v:6370$2110_Y - attribute \src "ls180.v:6372.100-6372.146" - wire $eq$ls180.v:6372$2113_Y - attribute \src "ls180.v:6373.103-6373.149" - wire $eq$ls180.v:6373$2117_Y - attribute \src "ls180.v:6375.112-6375.158" - wire $eq$ls180.v:6375$2120_Y - attribute \src "ls180.v:6376.115-6376.161" - wire $eq$ls180.v:6376$2124_Y - attribute \src "ls180.v:6378.113-6378.159" - wire $eq$ls180.v:6378$2127_Y - attribute \src "ls180.v:6379.116-6379.162" - wire $eq$ls180.v:6379$2131_Y - attribute \src "ls180.v:6381.104-6381.150" - wire $eq$ls180.v:6381$2134_Y - attribute \src "ls180.v:6382.107-6382.153" - wire $eq$ls180.v:6382$2138_Y - attribute \src "ls180.v:6399.33-6399.79" - wire $eq$ls180.v:6399$2140_Y - attribute \src "ls180.v:6401.90-6401.135" - wire $eq$ls180.v:6401$2142_Y - attribute \src "ls180.v:6402.93-6402.138" - wire $eq$ls180.v:6402$2146_Y - attribute \src "ls180.v:6404.100-6404.145" - wire $eq$ls180.v:6404$2149_Y - attribute \src "ls180.v:6405.103-6405.148" - wire $eq$ls180.v:6405$2153_Y - attribute \src "ls180.v:6407.101-6407.146" - wire $eq$ls180.v:6407$2156_Y - attribute \src "ls180.v:6408.104-6408.149" - wire $eq$ls180.v:6408$2160_Y - attribute \src "ls180.v:6410.105-6410.150" - wire $eq$ls180.v:6410$2163_Y - attribute \src "ls180.v:6411.108-6411.153" - wire $eq$ls180.v:6411$2167_Y - attribute \src "ls180.v:6413.106-6413.151" - wire $eq$ls180.v:6413$2170_Y - attribute \src "ls180.v:6414.109-6414.154" - wire $eq$ls180.v:6414$2174_Y - attribute \src "ls180.v:6416.104-6416.149" - wire $eq$ls180.v:6416$2177_Y - attribute \src "ls180.v:6417.107-6417.152" - wire $eq$ls180.v:6417$2181_Y - attribute \src "ls180.v:6419.101-6419.146" - wire $eq$ls180.v:6419$2184_Y - attribute \src "ls180.v:6420.104-6420.149" - wire $eq$ls180.v:6420$2188_Y - attribute \src "ls180.v:6422.100-6422.145" - wire $eq$ls180.v:6422$2191_Y - attribute \src "ls180.v:6423.103-6423.148" - wire $eq$ls180.v:6423$2195_Y - attribute \src "ls180.v:6433.33-6433.79" - wire $eq$ls180.v:6433$2197_Y - attribute \src "ls180.v:6435.106-6435.151" - wire $eq$ls180.v:6435$2199_Y - attribute \src "ls180.v:6436.109-6436.154" - wire $eq$ls180.v:6436$2203_Y - attribute \src "ls180.v:6438.106-6438.151" - wire $eq$ls180.v:6438$2206_Y - attribute \src "ls180.v:6439.109-6439.154" - wire $eq$ls180.v:6439$2210_Y - attribute \src "ls180.v:6441.106-6441.151" - wire $eq$ls180.v:6441$2213_Y - attribute \src "ls180.v:6442.109-6442.154" - wire $eq$ls180.v:6442$2217_Y - attribute \src "ls180.v:6444.106-6444.151" - wire $eq$ls180.v:6444$2220_Y - attribute \src "ls180.v:6445.109-6445.154" - wire $eq$ls180.v:6445$2224_Y - attribute \src "ls180.v:6826.41-6826.81" - wire $eq$ls180.v:6826$2261_Y - attribute \src "ls180.v:6826.144-6826.177" - wire $eq$ls180.v:6826$2262_Y - attribute \src "ls180.v:6826.219-6826.252" - wire $eq$ls180.v:6826$2265_Y - attribute \src "ls180.v:6826.294-6826.327" - wire $eq$ls180.v:6826$2268_Y - attribute \src "ls180.v:6850.41-6850.81" - wire $eq$ls180.v:6850$2277_Y - attribute \src "ls180.v:6850.144-6850.177" - wire $eq$ls180.v:6850$2278_Y - attribute \src "ls180.v:6850.219-6850.252" - wire $eq$ls180.v:6850$2281_Y - attribute \src "ls180.v:6850.294-6850.327" - wire $eq$ls180.v:6850$2284_Y - attribute \src "ls180.v:6874.41-6874.81" - wire $eq$ls180.v:6874$2293_Y - attribute \src "ls180.v:6874.144-6874.177" - wire $eq$ls180.v:6874$2294_Y - attribute \src "ls180.v:6874.219-6874.252" - wire $eq$ls180.v:6874$2297_Y - attribute \src "ls180.v:6874.294-6874.327" - wire $eq$ls180.v:6874$2300_Y - attribute \src "ls180.v:6898.41-6898.81" - wire $eq$ls180.v:6898$2309_Y - attribute \src "ls180.v:6898.144-6898.177" - wire $eq$ls180.v:6898$2310_Y - attribute \src "ls180.v:6898.219-6898.252" - wire $eq$ls180.v:6898$2313_Y - attribute \src "ls180.v:6898.294-6898.327" - wire $eq$ls180.v:6898$2316_Y - attribute \src "ls180.v:7491.8-7491.38" - wire $eq$ls180.v:7491$2419_Y - attribute \src "ls180.v:7522.8-7522.42" - wire $eq$ls180.v:7522$2427_Y - attribute \src "ls180.v:7542.38-7542.74" - wire $eq$ls180.v:7542$2430_Y - attribute \src "ls180.v:7549.7-7549.43" - wire $eq$ls180.v:7549$2432_Y - attribute \src "ls180.v:7556.7-7556.43" - wire $eq$ls180.v:7556$2433_Y - attribute \src "ls180.v:7564.7-7564.43" - wire $eq$ls180.v:7564$2434_Y - attribute \src "ls180.v:7616.9-7616.54" - wire $eq$ls180.v:7616$2452_Y - attribute \src "ls180.v:7662.9-7662.54" - wire $eq$ls180.v:7662$2468_Y - attribute \src "ls180.v:7708.9-7708.54" - wire $eq$ls180.v:7708$2484_Y - attribute \src "ls180.v:7754.9-7754.54" - wire $eq$ls180.v:7754$2500_Y - attribute \src "ls180.v:7904.9-7904.41" - wire $eq$ls180.v:7904$2512_Y - attribute \src "ls180.v:7919.9-7919.41" - wire $eq$ls180.v:7919$2515_Y - attribute \src "ls180.v:7925.49-7925.82" - wire $eq$ls180.v:7925$2516_Y - attribute \src "ls180.v:7925.131-7925.164" - wire $eq$ls180.v:7925$2519_Y - attribute \src "ls180.v:7925.213-7925.246" - wire $eq$ls180.v:7925$2522_Y - attribute \src "ls180.v:7925.295-7925.328" - wire $eq$ls180.v:7925$2525_Y - attribute \src "ls180.v:7926.50-7926.83" - wire $eq$ls180.v:7926$2528_Y - attribute \src "ls180.v:7926.132-7926.165" - wire $eq$ls180.v:7926$2531_Y - attribute \src "ls180.v:7926.214-7926.247" - wire $eq$ls180.v:7926$2534_Y - attribute \src "ls180.v:7926.296-7926.329" - wire $eq$ls180.v:7926$2537_Y - attribute \src "ls180.v:7961.9-7961.42" - wire $eq$ls180.v:7961$2549_Y - attribute \src "ls180.v:7964.10-7964.43" - wire $eq$ls180.v:7964$2550_Y - attribute \src "ls180.v:7990.9-7990.42" - wire $eq$ls180.v:7990$2556_Y - attribute \src "ls180.v:7995.10-7995.43" - wire $eq$ls180.v:7995$2557_Y - attribute \src "ls180.v:8167.9-8167.53" - wire $eq$ls180.v:8167$2601_Y - attribute \src "ls180.v:8248.9-8248.54" - wire $eq$ls180.v:8248$2613_Y - attribute \src "ls180.v:8327.9-8327.55" - wire $eq$ls180.v:8327$2625_Y - attribute \src "ls180.v:8550.9-8550.49" - wire $eq$ls180.v:8550$2658_Y - attribute \src "ls180.v:8126.8-8126.54" - wire $ge$ls180.v:8126$2593_Y - attribute \src "ls180.v:8140.8-8140.54" - wire $ge$ls180.v:8140$2597_Y - attribute \src "ls180.v:5076.47-5076.83" - wire $gt$ls180.v:5076$906_Y - attribute \src "ls180.v:5082.7-5082.43" - wire $lt$ls180.v:5082$909_Y - attribute \src "ls180.v:8121.8-8121.43" - wire $lt$ls180.v:8121$2591_Y - attribute \src "ls180.v:8135.8-8135.43" - wire $lt$ls180.v:8135$2595_Y - attribute \src "ls180.v:10052.33-10052.36" - wire width 32 $memrd$\mem$ls180.v:10052$2705_DATA - attribute \src "ls180.v:10063.12-10063.19" - wire width 25 $memrd$\storage$ls180.v:10063$2710_DATA - attribute \src "ls180.v:10070.68-10070.75" - wire width 25 $memrd$\storage$ls180.v:10070$2712_DATA - attribute \src "ls180.v:10077.14-10077.23" - wire width 25 $memrd$\storage_1$ls180.v:10077$2717_DATA - attribute \src "ls180.v:10084.68-10084.77" - wire width 25 $memrd$\storage_1$ls180.v:10084$2719_DATA - attribute \src "ls180.v:10091.14-10091.23" - wire width 25 $memrd$\storage_2$ls180.v:10091$2724_DATA - attribute \src "ls180.v:10098.68-10098.77" - wire width 25 $memrd$\storage_2$ls180.v:10098$2726_DATA - attribute \src "ls180.v:10105.14-10105.23" - wire width 25 $memrd$\storage_3$ls180.v:10105$2731_DATA - attribute \src "ls180.v:10112.68-10112.77" - wire width 25 $memrd$\storage_3$ls180.v:10112$2733_DATA - attribute \src "ls180.v:10120.14-10120.23" - wire width 10 $memrd$\storage_4$ls180.v:10120$2738_DATA - attribute \src "ls180.v:10125.15-10125.24" - wire width 10 $memrd$\storage_4$ls180.v:10125$2740_DATA - attribute \src "ls180.v:10137.14-10137.23" - wire width 10 $memrd$\storage_5$ls180.v:10137$2745_DATA - attribute \src "ls180.v:10142.15-10142.24" - wire width 10 $memrd$\storage_5$ls180.v:10142$2747_DATA - attribute \src "ls180.v:10153.14-10153.23" - wire width 10 $memrd$\storage_6$ls180.v:10153$2752_DATA - attribute \src "ls180.v:10160.45-10160.54" - wire width 10 $memrd$\storage_6$ls180.v:10160$2754_DATA - attribute \src "ls180.v:10167.14-10167.23" - wire width 10 $memrd$\storage_7$ls180.v:10167$2759_DATA - attribute \src "ls180.v:10174.45-10174.54" - wire width 10 $memrd$\storage_7$ls180.v:10174$2761_DATA - attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem$ls180.v:10042$1_ADDR - attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10042$1_DATA - attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10042$1_EN - attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem$ls180.v:10044$2_ADDR - attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10044$2_DATA - attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10044$2_EN - attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem$ls180.v:10046$3_ADDR - attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10046$3_DATA - attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10046$3_EN - attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem$ls180.v:10048$4_ADDR - attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10048$4_DATA - attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10048$4_EN - attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage$ls180.v:10062$5_ADDR - attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage$ls180.v:10062$5_DATA - attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage$ls180.v:10062$5_EN - attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage_1$ls180.v:10076$6_ADDR - attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_1$ls180.v:10076$6_DATA - attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_1$ls180.v:10076$6_EN - attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage_2$ls180.v:10090$7_ADDR - attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_2$ls180.v:10090$7_DATA - attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_2$ls180.v:10090$7_EN - attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage_3$ls180.v:10104$8_ADDR - attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_3$ls180.v:10104$8_DATA - attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_3$ls180.v:10104$8_EN - attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\storage_4$ls180.v:10119$9_ADDR - attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_4$ls180.v:10119$9_DATA - attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_4$ls180.v:10119$9_EN - attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\storage_5$ls180.v:10136$10_ADDR - attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_5$ls180.v:10136$10_DATA - attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_5$ls180.v:10136$10_EN - attribute \src "ls180.v:0.0-0.0" - wire width 5 $memwr$\storage_6$ls180.v:10152$11_ADDR - attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_6$ls180.v:10152$11_DATA - attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_6$ls180.v:10152$11_EN - attribute \src "ls180.v:0.0-0.0" - wire width 5 $memwr$\storage_7$ls180.v:10166$12_ADDR - attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_7$ls180.v:10166$12_DATA - attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_7$ls180.v:10166$12_EN - attribute \src "ls180.v:2949.41-2949.71" - wire $ne$ls180.v:2949$60_Y - attribute \src "ls180.v:3110.70-3110.104" - wire $ne$ls180.v:3110$74_Y - attribute \src "ls180.v:3171.8-3171.142" - wire $ne$ls180.v:3171$93_Y - attribute \src "ls180.v:3203.75-3203.133" - wire $ne$ls180.v:3203$100_Y - attribute \src "ls180.v:3204.75-3204.133" - wire $ne$ls180.v:3204$101_Y - attribute \src "ls180.v:3328.8-3328.142" - wire $ne$ls180.v:3328$123_Y - attribute \src "ls180.v:3360.75-3360.133" - wire $ne$ls180.v:3360$130_Y - attribute \src "ls180.v:3361.75-3361.133" - wire $ne$ls180.v:3361$131_Y - attribute \src "ls180.v:3485.8-3485.142" - wire $ne$ls180.v:3485$153_Y - attribute \src "ls180.v:3517.75-3517.133" - wire $ne$ls180.v:3517$160_Y - attribute \src "ls180.v:3518.75-3518.133" - wire $ne$ls180.v:3518$161_Y - attribute \src "ls180.v:3642.8-3642.142" - wire $ne$ls180.v:3642$183_Y - attribute \src "ls180.v:3674.75-3674.133" - wire $ne$ls180.v:3674$190_Y - attribute \src "ls180.v:3675.75-3675.133" - wire $ne$ls180.v:3675$191_Y - attribute \src "ls180.v:4167.47-4167.80" - wire $ne$ls180.v:4167$589_Y - attribute \src "ls180.v:4168.47-4168.79" - wire $ne$ls180.v:4168$590_Y - attribute \src "ls180.v:4197.47-4197.80" - wire $ne$ls180.v:4197$600_Y - attribute \src "ls180.v:4198.47-4198.79" - wire $ne$ls180.v:4198$601_Y - attribute \src "ls180.v:4608.32-4608.89" - wire $ne$ls180.v:4608$673_Y - attribute \src "ls180.v:5255.10-5255.56" - wire $ne$ls180.v:5255$970_Y - attribute \src "ls180.v:5360.51-5360.87" - wire $ne$ls180.v:5360$984_Y - attribute \src "ls180.v:5361.51-5361.86" - wire $ne$ls180.v:5361$985_Y - attribute \src "ls180.v:5568.51-5568.87" - wire $ne$ls180.v:5568$1015_Y - attribute \src "ls180.v:5569.51-5569.86" - wire $ne$ls180.v:5569$1016_Y - attribute \src "ls180.v:5659.79-5659.119" - wire $ne$ls180.v:5659$1027_Y - attribute \src "ls180.v:7481.7-7481.52" - wire $ne$ls180.v:7481$2414_Y - attribute \src "ls180.v:7531.9-7531.43" - wire $ne$ls180.v:7531$2428_Y - attribute \src "ls180.v:7567.8-7567.44" - wire $ne$ls180.v:7567$2435_Y - attribute \src "ls180.v:8470.9-8470.47" - wire $ne$ls180.v:8470$2645_Y - attribute \src "ls180.v:2757.45-2757.80" - wire $not$ls180.v:2757$14_Y - attribute \src "ls180.v:2796.61-2796.94" - wire $not$ls180.v:2796$19_Y - attribute \src "ls180.v:2797.61-2797.94" - wire $not$ls180.v:2797$20_Y - attribute \src "ls180.v:2817.45-2817.80" - wire $not$ls180.v:2817$25_Y - attribute \src "ls180.v:2856.61-2856.94" - wire $not$ls180.v:2856$30_Y - attribute \src "ls180.v:2857.61-2857.94" - wire $not$ls180.v:2857$31_Y - attribute \src "ls180.v:2877.45-2877.83" - wire $not$ls180.v:2877$36_Y - attribute \src "ls180.v:2916.61-2916.94" - wire $not$ls180.v:2916$41_Y - attribute \src "ls180.v:2917.61-2917.94" - wire $not$ls180.v:2917$42_Y - attribute \src "ls180.v:3059.34-3059.64" - wire $not$ls180.v:3059$66_Y - attribute \src "ls180.v:3060.31-3060.61" - wire $not$ls180.v:3060$67_Y - attribute \src "ls180.v:3061.32-3061.62" - wire $not$ls180.v:3061$68_Y - attribute \src "ls180.v:3062.32-3062.62" - wire $not$ls180.v:3062$69_Y - attribute \src "ls180.v:3104.33-3104.56" - wire $not$ls180.v:3104$72_Y - attribute \src "ls180.v:3205.58-3205.106" - wire $not$ls180.v:3205$102_Y - attribute \src "ls180.v:3259.9-3259.45" - wire $not$ls180.v:3259$107_Y - attribute \src "ls180.v:3362.58-3362.106" - wire $not$ls180.v:3362$132_Y - attribute \src "ls180.v:3416.9-3416.45" - wire $not$ls180.v:3416$137_Y - attribute \src "ls180.v:3519.58-3519.106" - wire $not$ls180.v:3519$162_Y - attribute \src "ls180.v:3573.9-3573.45" - wire $not$ls180.v:3573$167_Y - attribute \src "ls180.v:3676.58-3676.106" - wire $not$ls180.v:3676$192_Y - attribute \src "ls180.v:3730.9-3730.45" - wire $not$ls180.v:3730$197_Y - attribute \src "ls180.v:3772.149-3772.187" - wire $not$ls180.v:3772$200_Y - attribute \src "ls180.v:3772.193-3772.230" - wire $not$ls180.v:3772$202_Y - attribute \src "ls180.v:3773.149-3773.187" - wire $not$ls180.v:3773$206_Y - attribute \src "ls180.v:3773.193-3773.230" - wire $not$ls180.v:3773$208_Y - attribute \src "ls180.v:3789.43-3789.73" - wire width 2 $not$ls180.v:3789$236_Y - attribute \src "ls180.v:3792.205-3792.245" - wire $not$ls180.v:3792$239_Y - attribute \src "ls180.v:3792.251-3792.290" - wire $not$ls180.v:3792$241_Y - attribute \src "ls180.v:3792.159-3792.292" - wire $not$ls180.v:3792$243_Y - attribute \src "ls180.v:3793.205-3793.245" - wire $not$ls180.v:3793$252_Y - attribute \src "ls180.v:3793.251-3793.290" - wire $not$ls180.v:3793$254_Y - attribute \src "ls180.v:3793.159-3793.292" - wire $not$ls180.v:3793$256_Y - attribute \src "ls180.v:3794.205-3794.245" - wire $not$ls180.v:3794$265_Y - attribute \src "ls180.v:3794.251-3794.290" - wire $not$ls180.v:3794$267_Y - attribute \src "ls180.v:3794.159-3794.292" - wire $not$ls180.v:3794$269_Y - attribute \src "ls180.v:3795.205-3795.245" - wire $not$ls180.v:3795$278_Y - attribute \src "ls180.v:3795.251-3795.290" - wire $not$ls180.v:3795$280_Y - attribute \src "ls180.v:3795.159-3795.292" - wire $not$ls180.v:3795$282_Y - attribute \src "ls180.v:3822.71-3822.103" - wire $not$ls180.v:3822$293_Y - attribute \src "ls180.v:3825.205-3825.245" - wire $not$ls180.v:3825$297_Y - attribute \src "ls180.v:3825.251-3825.290" - wire $not$ls180.v:3825$299_Y - attribute \src "ls180.v:3825.159-3825.292" - wire $not$ls180.v:3825$301_Y - attribute \src "ls180.v:3826.205-3826.245" - wire $not$ls180.v:3826$310_Y - attribute \src "ls180.v:3826.251-3826.290" - wire $not$ls180.v:3826$312_Y - attribute \src "ls180.v:3826.159-3826.292" - wire $not$ls180.v:3826$314_Y - attribute \src "ls180.v:3827.205-3827.245" - wire $not$ls180.v:3827$323_Y - attribute \src "ls180.v:3827.251-3827.290" - wire $not$ls180.v:3827$325_Y - attribute \src "ls180.v:3827.159-3827.292" - wire $not$ls180.v:3827$327_Y - attribute \src "ls180.v:3828.205-3828.245" - wire $not$ls180.v:3828$336_Y - attribute \src "ls180.v:3828.251-3828.290" - wire $not$ls180.v:3828$338_Y - attribute \src "ls180.v:3828.159-3828.292" - wire $not$ls180.v:3828$340_Y - attribute \src "ls180.v:3891.71-3891.103" - wire $not$ls180.v:3891$379_Y - attribute \src "ls180.v:3912.112-3912.150" - wire $not$ls180.v:3912$382_Y - attribute \src "ls180.v:3912.156-3912.193" - wire $not$ls180.v:3912$384_Y - attribute \src "ls180.v:3912.68-3912.195" - wire $not$ls180.v:3912$386_Y - attribute \src "ls180.v:3920.11-3920.38" - wire $not$ls180.v:3920$389_Y - attribute \src "ls180.v:3950.112-3950.150" - wire $not$ls180.v:3950$391_Y - attribute \src "ls180.v:3950.156-3950.193" - wire $not$ls180.v:3950$393_Y - attribute \src "ls180.v:3950.68-3950.195" - wire $not$ls180.v:3950$395_Y - attribute \src "ls180.v:3958.11-3958.37" - wire $not$ls180.v:3958$398_Y - attribute \src "ls180.v:3968.87-3968.331" - wire $not$ls180.v:3968$410_Y - attribute \src "ls180.v:3969.35-3969.68" - wire $not$ls180.v:3969$413_Y - attribute \src "ls180.v:3969.73-3969.105" - wire $not$ls180.v:3969$414_Y - attribute \src "ls180.v:3973.87-3973.331" - wire $not$ls180.v:3973$426_Y - attribute \src "ls180.v:3974.35-3974.68" - wire $not$ls180.v:3974$429_Y - attribute \src "ls180.v:3974.73-3974.105" - wire $not$ls180.v:3974$430_Y - attribute \src "ls180.v:3978.87-3978.331" - wire $not$ls180.v:3978$442_Y - attribute \src "ls180.v:3979.35-3979.68" - wire $not$ls180.v:3979$445_Y - attribute \src "ls180.v:3979.73-3979.105" - wire $not$ls180.v:3979$446_Y - attribute \src "ls180.v:3983.87-3983.331" - wire $not$ls180.v:3983$458_Y - attribute \src "ls180.v:3984.35-3984.68" - wire $not$ls180.v:3984$461_Y - attribute \src "ls180.v:3984.73-3984.105" - wire $not$ls180.v:3984$462_Y - attribute \src "ls180.v:3988.128-3988.372" - wire $not$ls180.v:3988$475_Y - attribute \src "ls180.v:3988.502-3988.746" - wire $not$ls180.v:3988$491_Y - attribute \src "ls180.v:3988.876-3988.1120" - wire $not$ls180.v:3988$507_Y - attribute \src "ls180.v:3988.1250-3988.1494" - wire $not$ls180.v:3988$523_Y - attribute \src "ls180.v:4010.32-4010.50" - wire $not$ls180.v:4010$529_Y - attribute \src "ls180.v:4049.30-4049.50" - wire $not$ls180.v:4049$534_Y - attribute \src "ls180.v:4050.30-4050.50" - wire $not$ls180.v:4050$535_Y - attribute \src "ls180.v:4075.27-4075.48" - wire $not$ls180.v:4075$541_Y - attribute \src "ls180.v:4076.30-4076.50" - wire $not$ls180.v:4076$542_Y - attribute \src "ls180.v:4077.80-4077.98" - wire $not$ls180.v:4077$544_Y - attribute \src "ls180.v:4078.107-4078.127" - wire $not$ls180.v:4078$548_Y - attribute \src "ls180.v:4079.78-4079.103" - wire $not$ls180.v:4079$551_Y - attribute \src "ls180.v:4080.91-4080.111" - wire $not$ls180.v:4080$554_Y - attribute \src "ls180.v:4096.35-4096.64" - wire $not$ls180.v:4096$563_Y - attribute \src "ls180.v:4097.36-4097.67" - wire $not$ls180.v:4097$564_Y - attribute \src "ls180.v:4103.32-4103.61" - wire $not$ls180.v:4103$565_Y - attribute \src "ls180.v:4109.36-4109.67" - wire $not$ls180.v:4109$566_Y - attribute \src "ls180.v:4110.35-4110.64" - wire $not$ls180.v:4110$567_Y - attribute \src "ls180.v:4113.32-4113.63" - wire $not$ls180.v:4113$570_Y - attribute \src "ls180.v:4151.81-4151.108" - wire $not$ls180.v:4151$580_Y - attribute \src "ls180.v:4181.81-4181.108" - wire $not$ls180.v:4181$591_Y - attribute \src "ls180.v:4322.60-4322.85" - wire $not$ls180.v:4322$632_Y - attribute \src "ls180.v:4463.54-4463.96" - wire $not$ls180.v:4463$646_Y - attribute \src "ls180.v:4466.48-4466.86" - wire $not$ls180.v:4466$649_Y - attribute \src "ls180.v:4590.55-4590.98" - wire $not$ls180.v:4590$667_Y - attribute \src "ls180.v:4593.49-4593.88" - wire $not$ls180.v:4593$670_Y - attribute \src "ls180.v:4643.30-4643.58" - wire $not$ls180.v:4643$676_Y - attribute \src "ls180.v:4724.56-4724.100" - wire $not$ls180.v:4724$682_Y - attribute \src "ls180.v:4727.50-4727.90" - wire $not$ls180.v:4727$685_Y - attribute \src "ls180.v:4843.42-4843.74" - wire $not$ls180.v:4843$701_Y - attribute \src "ls180.v:5367.50-5367.88" - wire $not$ls180.v:5367$986_Y - attribute \src "ls180.v:5379.52-5379.102" - wire $not$ls180.v:5379$989_Y - attribute \src "ls180.v:5438.38-5438.74" - wire $not$ls180.v:5438$996_Y - attribute \src "ls180.v:5739.69-5739.88" - wire $not$ls180.v:5739$1065_Y - attribute \src "ls180.v:5756.63-5756.94" - wire $not$ls180.v:5756$1086_Y - attribute \src "ls180.v:5759.65-5759.96" - wire $not$ls180.v:5759$1093_Y - attribute \src "ls180.v:5762.65-5762.96" - wire $not$ls180.v:5762$1100_Y - attribute \src "ls180.v:5765.65-5765.96" - wire $not$ls180.v:5765$1107_Y - attribute \src "ls180.v:5768.65-5768.96" - wire $not$ls180.v:5768$1114_Y - attribute \src "ls180.v:5771.68-5771.99" - wire $not$ls180.v:5771$1121_Y - attribute \src "ls180.v:5774.68-5774.99" - wire $not$ls180.v:5774$1128_Y - attribute \src "ls180.v:5777.68-5777.99" - wire $not$ls180.v:5777$1135_Y - attribute \src "ls180.v:5780.68-5780.99" - wire $not$ls180.v:5780$1142_Y - attribute \src "ls180.v:5794.60-5794.91" - wire $not$ls180.v:5794$1150_Y - attribute \src "ls180.v:5797.60-5797.91" - wire $not$ls180.v:5797$1157_Y - attribute \src "ls180.v:5800.60-5800.91" - wire $not$ls180.v:5800$1164_Y - attribute \src "ls180.v:5803.60-5803.91" - wire $not$ls180.v:5803$1171_Y - attribute \src "ls180.v:5806.61-5806.92" - wire $not$ls180.v:5806$1178_Y - attribute \src "ls180.v:5809.61-5809.92" - wire $not$ls180.v:5809$1185_Y - attribute \src "ls180.v:5820.59-5820.90" - wire $not$ls180.v:5820$1193_Y - attribute \src "ls180.v:5823.58-5823.89" - wire $not$ls180.v:5823$1200_Y - attribute \src "ls180.v:5834.64-5834.95" - wire $not$ls180.v:5834$1208_Y - attribute \src "ls180.v:5837.63-5837.94" - wire $not$ls180.v:5837$1215_Y - attribute \src "ls180.v:5840.63-5840.94" - wire $not$ls180.v:5840$1222_Y - attribute \src "ls180.v:5843.63-5843.94" - wire $not$ls180.v:5843$1229_Y - attribute \src "ls180.v:5846.63-5846.94" - wire $not$ls180.v:5846$1236_Y - attribute \src "ls180.v:5849.64-5849.95" - wire $not$ls180.v:5849$1243_Y - attribute \src "ls180.v:5852.64-5852.95" - wire $not$ls180.v:5852$1250_Y - attribute \src "ls180.v:5855.64-5855.95" - wire $not$ls180.v:5855$1257_Y - attribute \src "ls180.v:5858.64-5858.95" - wire $not$ls180.v:5858$1264_Y - attribute \src "ls180.v:5871.64-5871.95" - wire $not$ls180.v:5871$1272_Y - attribute \src "ls180.v:5874.63-5874.94" - wire $not$ls180.v:5874$1279_Y - attribute \src "ls180.v:5877.63-5877.94" - wire $not$ls180.v:5877$1286_Y - attribute \src "ls180.v:5880.63-5880.94" - wire $not$ls180.v:5880$1293_Y - attribute \src "ls180.v:5883.63-5883.94" - wire $not$ls180.v:5883$1300_Y - attribute \src "ls180.v:5886.64-5886.95" - wire $not$ls180.v:5886$1307_Y - attribute \src "ls180.v:5889.64-5889.95" - wire $not$ls180.v:5889$1314_Y - attribute \src "ls180.v:5892.64-5892.95" - wire $not$ls180.v:5892$1321_Y - attribute \src "ls180.v:5895.64-5895.95" - wire $not$ls180.v:5895$1328_Y - attribute \src "ls180.v:5908.66-5908.97" - wire $not$ls180.v:5908$1336_Y - attribute \src "ls180.v:5911.66-5911.97" - wire $not$ls180.v:5911$1343_Y - attribute \src "ls180.v:5914.66-5914.97" - wire $not$ls180.v:5914$1350_Y - attribute \src "ls180.v:5917.66-5917.97" - wire $not$ls180.v:5917$1357_Y - attribute \src "ls180.v:5920.66-5920.97" - wire $not$ls180.v:5920$1364_Y - attribute \src "ls180.v:5923.66-5923.97" - wire $not$ls180.v:5923$1371_Y - attribute \src "ls180.v:5926.66-5926.97" - wire $not$ls180.v:5926$1378_Y - attribute \src "ls180.v:5929.66-5929.97" - wire $not$ls180.v:5929$1385_Y - attribute \src "ls180.v:5932.68-5932.99" - wire $not$ls180.v:5932$1392_Y - attribute \src "ls180.v:5935.68-5935.99" - wire $not$ls180.v:5935$1399_Y - attribute \src "ls180.v:5938.68-5938.99" - wire $not$ls180.v:5938$1406_Y - attribute \src "ls180.v:5941.68-5941.99" - wire $not$ls180.v:5941$1413_Y - attribute \src "ls180.v:5944.68-5944.99" - wire $not$ls180.v:5944$1420_Y - attribute \src "ls180.v:5947.65-5947.96" - wire $not$ls180.v:5947$1427_Y - attribute \src "ls180.v:5950.66-5950.97" - wire $not$ls180.v:5950$1434_Y - attribute \src "ls180.v:5970.70-5970.101" - wire $not$ls180.v:5970$1442_Y - attribute \src "ls180.v:5973.70-5973.101" - wire $not$ls180.v:5973$1449_Y - attribute \src "ls180.v:5976.70-5976.101" - wire $not$ls180.v:5976$1456_Y - attribute \src "ls180.v:5979.70-5979.101" - wire $not$ls180.v:5979$1463_Y - attribute \src "ls180.v:5982.69-5982.100" - wire $not$ls180.v:5982$1470_Y - attribute \src "ls180.v:5985.69-5985.100" - wire $not$ls180.v:5985$1477_Y - attribute \src "ls180.v:5988.69-5988.100" - wire $not$ls180.v:5988$1484_Y - attribute \src "ls180.v:5991.69-5991.100" - wire $not$ls180.v:5991$1491_Y - attribute \src "ls180.v:5994.60-5994.91" - wire $not$ls180.v:5994$1498_Y - attribute \src "ls180.v:5997.71-5997.102" - wire $not$ls180.v:5997$1505_Y - attribute \src "ls180.v:6000.71-6000.102" - wire $not$ls180.v:6000$1512_Y - attribute \src "ls180.v:6003.71-6003.102" - wire $not$ls180.v:6003$1519_Y - attribute \src "ls180.v:6006.71-6006.102" - wire $not$ls180.v:6006$1526_Y - attribute \src "ls180.v:6009.71-6009.102" - wire $not$ls180.v:6009$1533_Y - attribute \src "ls180.v:6012.71-6012.102" - wire $not$ls180.v:6012$1540_Y - attribute \src "ls180.v:6015.70-6015.101" - wire $not$ls180.v:6015$1547_Y - attribute \src "ls180.v:6018.70-6018.101" - wire $not$ls180.v:6018$1554_Y - attribute \src "ls180.v:6021.70-6021.101" - wire $not$ls180.v:6021$1561_Y - attribute \src "ls180.v:6024.70-6024.101" - wire $not$ls180.v:6024$1568_Y - attribute \src "ls180.v:6027.70-6027.101" - wire $not$ls180.v:6027$1575_Y - attribute \src "ls180.v:6030.70-6030.101" - wire $not$ls180.v:6030$1582_Y - attribute \src "ls180.v:6033.70-6033.101" - wire $not$ls180.v:6033$1589_Y - attribute \src "ls180.v:6036.70-6036.101" - wire $not$ls180.v:6036$1596_Y - attribute \src "ls180.v:6039.70-6039.101" - wire $not$ls180.v:6039$1603_Y - attribute \src "ls180.v:6042.70-6042.101" - wire $not$ls180.v:6042$1610_Y - attribute \src "ls180.v:6045.66-6045.97" - wire $not$ls180.v:6045$1617_Y - attribute \src "ls180.v:6048.67-6048.98" - wire $not$ls180.v:6048$1624_Y - attribute \src "ls180.v:6051.70-6051.101" - wire $not$ls180.v:6051$1631_Y - attribute \src "ls180.v:6054.70-6054.101" - wire $not$ls180.v:6054$1638_Y - attribute \src "ls180.v:6057.69-6057.100" - wire $not$ls180.v:6057$1645_Y - attribute \src "ls180.v:6060.69-6060.100" - wire $not$ls180.v:6060$1652_Y - attribute \src "ls180.v:6063.69-6063.100" - wire $not$ls180.v:6063$1659_Y - attribute \src "ls180.v:6066.69-6066.100" - wire $not$ls180.v:6066$1666_Y - attribute \src "ls180.v:6105.66-6105.97" - wire $not$ls180.v:6105$1674_Y - attribute \src "ls180.v:6108.66-6108.97" - wire $not$ls180.v:6108$1681_Y - attribute \src "ls180.v:6111.66-6111.97" - wire $not$ls180.v:6111$1688_Y - attribute \src "ls180.v:6114.66-6114.97" - wire $not$ls180.v:6114$1695_Y - attribute \src "ls180.v:6117.66-6117.97" - wire $not$ls180.v:6117$1702_Y - attribute \src "ls180.v:6120.66-6120.97" - wire $not$ls180.v:6120$1709_Y - attribute \src "ls180.v:6123.66-6123.97" - wire $not$ls180.v:6123$1716_Y - attribute \src "ls180.v:6126.66-6126.97" - wire $not$ls180.v:6126$1723_Y - attribute \src "ls180.v:6129.68-6129.99" - wire $not$ls180.v:6129$1730_Y - attribute \src "ls180.v:6132.68-6132.99" - wire $not$ls180.v:6132$1737_Y - attribute \src "ls180.v:6135.68-6135.99" - wire $not$ls180.v:6135$1744_Y - attribute \src "ls180.v:6138.68-6138.99" - wire $not$ls180.v:6138$1751_Y - attribute \src "ls180.v:6141.68-6141.99" - wire $not$ls180.v:6141$1758_Y - attribute \src "ls180.v:6144.65-6144.96" - wire $not$ls180.v:6144$1765_Y - attribute \src "ls180.v:6147.66-6147.97" - wire $not$ls180.v:6147$1772_Y - attribute \src "ls180.v:6150.68-6150.99" - wire $not$ls180.v:6150$1779_Y - attribute \src "ls180.v:6153.68-6153.99" - wire $not$ls180.v:6153$1786_Y - attribute \src "ls180.v:6156.68-6156.99" - wire $not$ls180.v:6156$1793_Y - attribute \src "ls180.v:6159.68-6159.99" - wire $not$ls180.v:6159$1800_Y - attribute \src "ls180.v:6184.68-6184.99" - wire $not$ls180.v:6184$1808_Y - attribute \src "ls180.v:6187.73-6187.104" - wire $not$ls180.v:6187$1815_Y - attribute \src "ls180.v:6190.73-6190.104" - wire $not$ls180.v:6190$1822_Y - attribute \src "ls180.v:6193.66-6193.97" - wire $not$ls180.v:6193$1829_Y - attribute \src "ls180.v:6201.70-6201.101" - wire $not$ls180.v:6201$1837_Y - attribute \src "ls180.v:6204.74-6204.105" - wire $not$ls180.v:6204$1844_Y - attribute \src "ls180.v:6207.64-6207.95" - wire $not$ls180.v:6207$1851_Y - attribute \src "ls180.v:6210.74-6210.105" - wire $not$ls180.v:6210$1858_Y - attribute \src "ls180.v:6213.74-6213.105" - wire $not$ls180.v:6213$1865_Y - attribute \src "ls180.v:6216.75-6216.106" - wire $not$ls180.v:6216$1872_Y - attribute \src "ls180.v:6219.73-6219.104" - wire $not$ls180.v:6219$1879_Y - attribute \src "ls180.v:6222.73-6222.104" - wire $not$ls180.v:6222$1886_Y - attribute \src "ls180.v:6225.73-6225.104" - wire $not$ls180.v:6225$1893_Y - attribute \src "ls180.v:6228.73-6228.104" - wire $not$ls180.v:6228$1900_Y - attribute \src "ls180.v:6246.67-6246.99" - wire $not$ls180.v:6246$1908_Y - attribute \src "ls180.v:6249.67-6249.99" - wire $not$ls180.v:6249$1915_Y - attribute \src "ls180.v:6252.65-6252.97" - wire $not$ls180.v:6252$1922_Y - attribute \src "ls180.v:6255.64-6255.96" - wire $not$ls180.v:6255$1929_Y - attribute \src "ls180.v:6258.63-6258.95" - wire $not$ls180.v:6258$1936_Y - attribute \src "ls180.v:6261.62-6261.94" - wire $not$ls180.v:6261$1943_Y - attribute \src "ls180.v:6264.68-6264.100" - wire $not$ls180.v:6264$1950_Y - attribute \src "ls180.v:6286.67-6286.99" - wire $not$ls180.v:6286$1959_Y - attribute \src "ls180.v:6289.67-6289.99" - wire $not$ls180.v:6289$1966_Y - attribute \src "ls180.v:6292.65-6292.97" - wire $not$ls180.v:6292$1973_Y - attribute \src "ls180.v:6295.64-6295.96" - wire $not$ls180.v:6295$1980_Y - attribute \src "ls180.v:6298.63-6298.95" - wire $not$ls180.v:6298$1987_Y - attribute \src "ls180.v:6301.62-6301.94" - wire $not$ls180.v:6301$1994_Y - attribute \src "ls180.v:6304.68-6304.100" - wire $not$ls180.v:6304$2001_Y - attribute \src "ls180.v:6307.71-6307.103" - wire $not$ls180.v:6307$2008_Y - attribute \src "ls180.v:6310.71-6310.103" - wire $not$ls180.v:6310$2015_Y - attribute \src "ls180.v:6334.64-6334.96" - wire $not$ls180.v:6334$2024_Y - attribute \src "ls180.v:6337.64-6337.96" - wire $not$ls180.v:6337$2031_Y - attribute \src "ls180.v:6340.64-6340.96" - wire $not$ls180.v:6340$2038_Y - attribute \src "ls180.v:6343.64-6343.96" - wire $not$ls180.v:6343$2045_Y - attribute \src "ls180.v:6346.66-6346.98" - wire $not$ls180.v:6346$2052_Y - attribute \src "ls180.v:6349.66-6349.98" - wire $not$ls180.v:6349$2059_Y - attribute \src "ls180.v:6352.66-6352.98" - wire $not$ls180.v:6352$2066_Y - attribute \src "ls180.v:6355.66-6355.98" - wire $not$ls180.v:6355$2073_Y - attribute \src "ls180.v:6358.62-6358.94" - wire $not$ls180.v:6358$2080_Y - attribute \src "ls180.v:6361.72-6361.104" - wire $not$ls180.v:6361$2087_Y - attribute \src "ls180.v:6364.65-6364.97" - wire $not$ls180.v:6364$2094_Y - attribute \src "ls180.v:6367.65-6367.97" - wire $not$ls180.v:6367$2101_Y - attribute \src "ls180.v:6370.65-6370.97" - wire $not$ls180.v:6370$2108_Y - attribute \src "ls180.v:6373.65-6373.97" - wire $not$ls180.v:6373$2115_Y - attribute \src "ls180.v:6376.77-6376.109" - wire $not$ls180.v:6376$2122_Y - attribute \src "ls180.v:6379.78-6379.110" - wire $not$ls180.v:6379$2129_Y - attribute \src "ls180.v:6382.69-6382.101" - wire $not$ls180.v:6382$2136_Y - attribute \src "ls180.v:6402.55-6402.87" - wire $not$ls180.v:6402$2144_Y - attribute \src "ls180.v:6405.65-6405.97" - wire $not$ls180.v:6405$2151_Y - attribute \src "ls180.v:6408.66-6408.98" - wire $not$ls180.v:6408$2158_Y - attribute \src "ls180.v:6411.70-6411.102" - wire $not$ls180.v:6411$2165_Y - attribute \src "ls180.v:6414.71-6414.103" - wire $not$ls180.v:6414$2172_Y - attribute \src "ls180.v:6417.69-6417.101" - wire $not$ls180.v:6417$2179_Y - attribute \src "ls180.v:6420.66-6420.98" - wire $not$ls180.v:6420$2186_Y - attribute \src "ls180.v:6423.65-6423.97" - wire $not$ls180.v:6423$2193_Y - attribute \src "ls180.v:6436.71-6436.103" - wire $not$ls180.v:6436$2201_Y - attribute \src "ls180.v:6439.71-6439.103" - wire $not$ls180.v:6439$2208_Y - attribute \src "ls180.v:6442.71-6442.103" - wire $not$ls180.v:6442$2215_Y - attribute \src "ls180.v:6445.71-6445.103" - wire $not$ls180.v:6445$2222_Y - attribute \src "ls180.v:6826.86-6826.330" - wire $not$ls180.v:6826$2271_Y - attribute \src "ls180.v:6850.86-6850.330" - wire $not$ls180.v:6850$2287_Y - attribute \src "ls180.v:6874.86-6874.330" - wire $not$ls180.v:6874$2303_Y - attribute \src "ls180.v:6898.86-6898.330" - wire $not$ls180.v:6898$2319_Y - attribute \src "ls180.v:7396.18-7396.42" - wire $not$ls180.v:7396$2372_Y - attribute \src "ls180.v:7487.72-7487.101" - wire $not$ls180.v:7487$2417_Y - attribute \src "ls180.v:7506.8-7506.38" - wire $not$ls180.v:7506$2421_Y - attribute \src "ls180.v:7514.32-7514.55" - wire $not$ls180.v:7514$2423_Y - attribute \src "ls180.v:7584.136-7584.189" - wire $not$ls180.v:7584$2438_Y - attribute \src "ls180.v:7590.136-7590.189" - wire $not$ls180.v:7590$2443_Y - attribute \src "ls180.v:7591.8-7591.61" - wire $not$ls180.v:7591$2445_Y - attribute \src "ls180.v:7599.8-7599.56" - wire $not$ls180.v:7599$2448_Y - attribute \src "ls180.v:7614.8-7614.46" - wire $not$ls180.v:7614$2450_Y - attribute \src "ls180.v:7630.136-7630.189" - wire $not$ls180.v:7630$2454_Y - attribute \src "ls180.v:7636.136-7636.189" - wire $not$ls180.v:7636$2459_Y - attribute \src "ls180.v:7637.8-7637.61" - wire $not$ls180.v:7637$2461_Y - attribute \src "ls180.v:7645.8-7645.56" - wire $not$ls180.v:7645$2464_Y - attribute \src "ls180.v:7660.8-7660.46" - wire $not$ls180.v:7660$2466_Y - attribute \src "ls180.v:7676.136-7676.189" - wire $not$ls180.v:7676$2470_Y - attribute \src "ls180.v:7682.136-7682.189" - wire $not$ls180.v:7682$2475_Y - attribute \src "ls180.v:7683.8-7683.61" - wire $not$ls180.v:7683$2477_Y - attribute \src "ls180.v:7691.8-7691.56" - wire $not$ls180.v:7691$2480_Y - attribute \src "ls180.v:7706.8-7706.46" - wire $not$ls180.v:7706$2482_Y - attribute \src "ls180.v:7722.136-7722.189" - wire $not$ls180.v:7722$2486_Y - attribute \src "ls180.v:7728.136-7728.189" - wire $not$ls180.v:7728$2491_Y - attribute \src "ls180.v:7729.8-7729.61" - wire $not$ls180.v:7729$2493_Y - attribute \src "ls180.v:7737.8-7737.56" - wire $not$ls180.v:7737$2496_Y - attribute \src "ls180.v:7752.8-7752.46" - wire $not$ls180.v:7752$2498_Y - attribute \src "ls180.v:7760.7-7760.22" - wire $not$ls180.v:7760$2501_Y - attribute \src "ls180.v:7763.8-7763.29" - wire $not$ls180.v:7763$2502_Y - attribute \src "ls180.v:7767.7-7767.22" - wire $not$ls180.v:7767$2504_Y - attribute \src "ls180.v:7770.8-7770.29" - wire $not$ls180.v:7770$2505_Y - attribute \src "ls180.v:7889.30-7889.60" - wire $not$ls180.v:7889$2507_Y - attribute \src "ls180.v:7890.30-7890.60" - wire $not$ls180.v:7890$2508_Y - attribute \src "ls180.v:7891.29-7891.59" - wire $not$ls180.v:7891$2509_Y - attribute \src "ls180.v:7902.8-7902.33" - wire $not$ls180.v:7902$2510_Y - attribute \src "ls180.v:7917.8-7917.33" - wire $not$ls180.v:7917$2513_Y - attribute \src "ls180.v:7953.36-7953.58" - wire $not$ls180.v:7953$2543_Y - attribute \src "ls180.v:7953.64-7953.89" - wire $not$ls180.v:7953$2545_Y - attribute \src "ls180.v:7982.7-7982.29" - wire $not$ls180.v:7982$2552_Y - attribute \src "ls180.v:7983.9-7983.26" - wire $not$ls180.v:7983$2553_Y - attribute \src "ls180.v:8016.8-8016.29" - wire $not$ls180.v:8016$2559_Y - attribute \src "ls180.v:8023.8-8023.29" - wire $not$ls180.v:8023$2561_Y - attribute \src "ls180.v:8033.80-8033.106" - wire $not$ls180.v:8033$2564_Y - attribute \src "ls180.v:8039.80-8039.106" - wire $not$ls180.v:8039$2569_Y - attribute \src "ls180.v:8040.8-8040.34" - wire $not$ls180.v:8040$2571_Y - attribute \src "ls180.v:8055.80-8055.106" - wire $not$ls180.v:8055$2575_Y - attribute \src "ls180.v:8061.80-8061.106" - wire $not$ls180.v:8061$2580_Y - attribute \src "ls180.v:8062.8-8062.34" - wire $not$ls180.v:8062$2582_Y - attribute \src "ls180.v:8093.23-8093.42" - wire $not$ls180.v:8093$2586_Y - attribute \src "ls180.v:8093.47-8093.73" - wire $not$ls180.v:8093$2587_Y - attribute \src "ls180.v:8147.7-8147.31" - wire $not$ls180.v:8147$2598_Y - attribute \src "ls180.v:8219.8-8219.46" - wire $not$ls180.v:8219$2610_Y - attribute \src "ls180.v:8300.8-8300.47" - wire $not$ls180.v:8300$2622_Y - attribute \src "ls180.v:8361.8-8361.48" - wire $not$ls180.v:8361$2634_Y - attribute \src "ls180.v:8531.88-8531.118" - wire $not$ls180.v:8531$2648_Y - attribute \src "ls180.v:8537.88-8537.118" - wire $not$ls180.v:8537$2653_Y - attribute \src "ls180.v:8538.8-8538.38" - wire $not$ls180.v:8538$2655_Y - attribute \src "ls180.v:8617.88-8617.118" - wire $not$ls180.v:8617$2670_Y - attribute \src "ls180.v:8623.88-8623.118" - wire $not$ls180.v:8623$2675_Y - attribute \src "ls180.v:8624.8-8624.38" - wire $not$ls180.v:8624$2677_Y - attribute \src "ls180.v:8641.22-8641.37" - wire $not$ls180.v:8641$2681_Y - attribute \src "ls180.v:8641.42-8641.64" - wire $not$ls180.v:8641$2682_Y - attribute \src "ls180.v:8679.9-8679.28" - wire $not$ls180.v:8679$2685_Y - attribute \src "ls180.v:8698.9-8698.28" - wire $not$ls180.v:8698$2686_Y - attribute \src "ls180.v:8717.9-8717.28" - wire $not$ls180.v:8717$2687_Y - attribute \src "ls180.v:8736.9-8736.28" - wire $not$ls180.v:8736$2688_Y - attribute \src "ls180.v:8755.9-8755.28" - wire $not$ls180.v:8755$2689_Y - attribute \src "ls180.v:8776.8-8776.21" - wire $not$ls180.v:8776$2690_Y - attribute \src "ls180.v:10259.8-10259.51" - wire $or$ls180.v:10259$2762_Y - attribute \src "ls180.v:2798.10-2798.96" - wire $or$ls180.v:2798$21_Y - attribute \src "ls180.v:2858.10-2858.96" - wire $or$ls180.v:2858$32_Y - attribute \src "ls180.v:2918.10-2918.96" - wire $or$ls180.v:2918$43_Y - attribute \src "ls180.v:3110.39-3110.105" - wire $or$ls180.v:3110$75_Y - attribute \src "ls180.v:3153.59-3153.140" - wire $or$ls180.v:3153$79_Y - attribute \src "ls180.v:3154.44-3154.151" - wire $or$ls180.v:3154$80_Y - attribute \src "ls180.v:3162.45-3162.170" - wire width 13 $or$ls180.v:3162$84_Y - attribute \src "ls180.v:3199.127-3199.245" - wire $or$ls180.v:3199$97_Y - attribute \src "ls180.v:3205.57-3205.157" - wire $or$ls180.v:3205$103_Y - attribute \src "ls180.v:3310.59-3310.140" - wire $or$ls180.v:3310$109_Y - attribute \src "ls180.v:3311.44-3311.151" - wire $or$ls180.v:3311$110_Y - attribute \src "ls180.v:3319.45-3319.170" - wire width 13 $or$ls180.v:3319$114_Y - attribute \src "ls180.v:3356.127-3356.245" - wire $or$ls180.v:3356$127_Y - attribute \src "ls180.v:3362.57-3362.157" - wire $or$ls180.v:3362$133_Y - attribute \src "ls180.v:3467.59-3467.140" - wire $or$ls180.v:3467$139_Y - attribute \src "ls180.v:3468.44-3468.151" - wire $or$ls180.v:3468$140_Y - attribute \src "ls180.v:3476.45-3476.170" - wire width 13 $or$ls180.v:3476$144_Y - attribute \src "ls180.v:3513.127-3513.245" - wire $or$ls180.v:3513$157_Y - attribute \src "ls180.v:3519.57-3519.157" - wire $or$ls180.v:3519$163_Y - attribute \src "ls180.v:3624.59-3624.140" - wire $or$ls180.v:3624$169_Y - attribute \src "ls180.v:3625.44-3625.151" - wire $or$ls180.v:3625$170_Y - attribute \src "ls180.v:3633.45-3633.170" - wire width 13 $or$ls180.v:3633$174_Y - attribute \src "ls180.v:3670.127-3670.245" - wire $or$ls180.v:3670$187_Y - attribute \src "ls180.v:3676.57-3676.157" - wire $or$ls180.v:3676$193_Y - attribute \src "ls180.v:3775.107-3775.193" - wire $or$ls180.v:3775$213_Y - attribute \src "ls180.v:3778.39-3778.204" - wire $or$ls180.v:3778$219_Y - attribute \src "ls180.v:3778.38-3778.289" - wire $or$ls180.v:3778$221_Y - attribute \src "ls180.v:3778.37-3778.374" - wire $or$ls180.v:3778$223_Y - attribute \src "ls180.v:3779.40-3779.207" - wire $or$ls180.v:3779$226_Y - attribute \src "ls180.v:3779.39-3779.293" - wire $or$ls180.v:3779$228_Y - attribute \src "ls180.v:3779.38-3779.379" - wire $or$ls180.v:3779$230_Y - attribute \src "ls180.v:3792.158-3792.332" - wire $or$ls180.v:3792$244_Y - attribute \src "ls180.v:3792.75-3792.506" - wire $or$ls180.v:3792$249_Y - attribute \src "ls180.v:3793.158-3793.332" - wire $or$ls180.v:3793$257_Y - attribute \src "ls180.v:3793.75-3793.506" - wire $or$ls180.v:3793$262_Y - attribute \src "ls180.v:3794.158-3794.332" - wire $or$ls180.v:3794$270_Y - attribute \src "ls180.v:3794.75-3794.506" - wire $or$ls180.v:3794$275_Y - attribute \src "ls180.v:3795.158-3795.332" - wire $or$ls180.v:3795$283_Y - attribute \src "ls180.v:3795.75-3795.506" - wire $or$ls180.v:3795$288_Y - attribute \src "ls180.v:3822.36-3822.104" - wire $or$ls180.v:3822$294_Y - attribute \src "ls180.v:3825.158-3825.332" - wire $or$ls180.v:3825$302_Y - attribute \src "ls180.v:3825.75-3825.506" - wire $or$ls180.v:3825$307_Y - attribute \src "ls180.v:3826.158-3826.332" - wire $or$ls180.v:3826$315_Y - attribute \src "ls180.v:3826.75-3826.506" - wire $or$ls180.v:3826$320_Y - attribute \src "ls180.v:3827.158-3827.332" - wire $or$ls180.v:3827$328_Y - attribute \src "ls180.v:3827.75-3827.506" - wire $or$ls180.v:3827$333_Y - attribute \src "ls180.v:3828.158-3828.332" - wire $or$ls180.v:3828$341_Y - attribute \src "ls180.v:3828.75-3828.506" - wire $or$ls180.v:3828$346_Y - attribute \src "ls180.v:3891.36-3891.104" - wire $or$ls180.v:3891$380_Y - attribute \src "ls180.v:3912.67-3912.221" - wire $or$ls180.v:3912$387_Y - attribute \src "ls180.v:3920.10-3920.62" - wire $or$ls180.v:3920$390_Y - attribute \src "ls180.v:3950.67-3950.221" - wire $or$ls180.v:3950$396_Y - attribute \src "ls180.v:3958.10-3958.61" - wire $or$ls180.v:3958$399_Y - attribute \src "ls180.v:3968.91-3968.180" - wire $or$ls180.v:3968$403_Y - attribute \src "ls180.v:3968.90-3968.255" - wire $or$ls180.v:3968$406_Y - attribute \src "ls180.v:3968.89-3968.330" - wire $or$ls180.v:3968$409_Y - attribute \src "ls180.v:3973.91-3973.180" - wire $or$ls180.v:3973$419_Y - attribute \src "ls180.v:3973.90-3973.255" - wire $or$ls180.v:3973$422_Y - attribute \src "ls180.v:3973.89-3973.330" - wire $or$ls180.v:3973$425_Y - attribute \src "ls180.v:3978.91-3978.180" - wire $or$ls180.v:3978$435_Y - attribute \src "ls180.v:3978.90-3978.255" - wire $or$ls180.v:3978$438_Y - attribute \src "ls180.v:3978.89-3978.330" - wire $or$ls180.v:3978$441_Y - attribute \src "ls180.v:3983.91-3983.180" - wire $or$ls180.v:3983$451_Y - attribute \src "ls180.v:3983.90-3983.255" - wire $or$ls180.v:3983$454_Y - attribute \src "ls180.v:3983.89-3983.330" - wire $or$ls180.v:3983$457_Y - attribute \src "ls180.v:3988.132-3988.221" - wire $or$ls180.v:3988$468_Y - attribute \src "ls180.v:3988.131-3988.296" - wire $or$ls180.v:3988$471_Y - attribute \src "ls180.v:3988.130-3988.371" - wire $or$ls180.v:3988$474_Y - attribute \src "ls180.v:3988.34-3988.411" - wire $or$ls180.v:3988$479_Y - attribute \src "ls180.v:3988.506-3988.595" - wire $or$ls180.v:3988$484_Y - attribute \src "ls180.v:3988.505-3988.670" - wire $or$ls180.v:3988$487_Y - attribute \src "ls180.v:3988.504-3988.745" - wire $or$ls180.v:3988$490_Y - attribute \src "ls180.v:3988.33-3988.785" - wire $or$ls180.v:3988$495_Y - attribute \src "ls180.v:3988.880-3988.969" - wire $or$ls180.v:3988$500_Y - attribute \src "ls180.v:3988.879-3988.1044" - wire $or$ls180.v:3988$503_Y - attribute \src "ls180.v:3988.878-3988.1119" - wire $or$ls180.v:3988$506_Y - attribute \src "ls180.v:3988.32-3988.1159" - wire $or$ls180.v:3988$511_Y - attribute \src "ls180.v:3988.1254-3988.1343" - wire $or$ls180.v:3988$516_Y - attribute \src "ls180.v:3988.1253-3988.1418" - wire $or$ls180.v:3988$519_Y - attribute \src "ls180.v:3988.1252-3988.1493" - wire $or$ls180.v:3988$522_Y - attribute \src "ls180.v:3988.31-3988.1533" - wire $or$ls180.v:3988$527_Y - attribute \src "ls180.v:4051.10-4051.52" - wire $or$ls180.v:4051$536_Y - attribute \src "ls180.v:4078.35-4078.74" - wire $or$ls180.v:4078$546_Y - attribute \src "ls180.v:4079.34-4079.73" - wire $or$ls180.v:4079$550_Y - attribute \src "ls180.v:4080.48-4080.130" - wire $or$ls180.v:4080$556_Y - attribute \src "ls180.v:4081.24-4081.87" - wire $or$ls180.v:4081$559_Y - attribute \src "ls180.v:4082.26-4082.95" - wire $or$ls180.v:4082$561_Y - attribute \src "ls180.v:4112.42-4112.89" - wire $or$ls180.v:4112$569_Y - attribute \src "ls180.v:4136.25-4136.174" - wire $or$ls180.v:4136$579_Y - attribute \src "ls180.v:4151.80-4151.132" - wire $or$ls180.v:4151$581_Y - attribute \src "ls180.v:4162.72-4162.135" - wire $or$ls180.v:4162$586_Y - attribute \src "ls180.v:4181.80-4181.132" - wire $or$ls180.v:4181$592_Y - attribute \src "ls180.v:4192.72-4192.135" - wire $or$ls180.v:4192$597_Y - attribute \src "ls180.v:4267.36-4267.111" - wire $or$ls180.v:4267$610_Y - attribute \src "ls180.v:4267.35-4267.151" - wire $or$ls180.v:4267$611_Y - attribute \src "ls180.v:4267.34-4267.192" - wire $or$ls180.v:4267$612_Y - attribute \src "ls180.v:4267.33-4267.233" - wire $or$ls180.v:4267$613_Y - attribute \src "ls180.v:4268.39-4268.120" - wire $or$ls180.v:4268$614_Y - attribute \src "ls180.v:4268.38-4268.163" - wire $or$ls180.v:4268$615_Y - attribute \src "ls180.v:4268.37-4268.207" - wire $or$ls180.v:4268$616_Y - attribute \src "ls180.v:4268.36-4268.251" - wire $or$ls180.v:4268$617_Y - attribute \src "ls180.v:4269.38-4269.117" - wire $or$ls180.v:4269$618_Y - attribute \src "ls180.v:4269.37-4269.159" - wire $or$ls180.v:4269$619_Y - attribute \src "ls180.v:4269.36-4269.202" - wire $or$ls180.v:4269$620_Y - attribute \src "ls180.v:4269.35-4269.245" - wire $or$ls180.v:4269$621_Y - attribute \src "ls180.v:4270.40-4270.123" - wire $or$ls180.v:4270$622_Y - attribute \src "ls180.v:4270.39-4270.167" - wire $or$ls180.v:4270$623_Y - attribute \src "ls180.v:4270.38-4270.212" - wire $or$ls180.v:4270$624_Y - attribute \src "ls180.v:4270.37-4270.257" - wire $or$ls180.v:4270$625_Y - attribute \src "ls180.v:4271.39-4271.120" - wire width 4 $or$ls180.v:4271$626_Y - attribute \src "ls180.v:4271.38-4271.163" - wire width 4 $or$ls180.v:4271$627_Y - attribute \src "ls180.v:4271.37-4271.207" - wire width 4 $or$ls180.v:4271$628_Y - attribute \src "ls180.v:4271.36-4271.251" - wire width 4 $or$ls180.v:4271$629_Y - attribute \src "ls180.v:4292.35-4292.80" - wire $or$ls180.v:4292$630_Y - attribute \src "ls180.v:4446.91-4446.144" - wire $or$ls180.v:4446$644_Y - attribute \src "ls180.v:4463.53-4463.143" - wire $or$ls180.v:4463$647_Y - attribute \src "ls180.v:4466.47-4466.127" - wire $or$ls180.v:4466$650_Y - attribute \src "ls180.v:4590.54-4590.146" - wire $or$ls180.v:4590$668_Y - attribute \src "ls180.v:4593.48-4593.130" - wire $or$ls180.v:4593$671_Y - attribute \src "ls180.v:4724.55-4724.149" - wire $or$ls180.v:4724$683_Y - attribute \src "ls180.v:4727.49-4727.133" - wire $or$ls180.v:4727$686_Y - attribute \src "ls180.v:5356.80-5356.151" - wire $or$ls180.v:5356$981_Y - attribute \src "ls180.v:5367.49-5367.131" - wire $or$ls180.v:5367$987_Y - attribute \src "ls180.v:5564.80-5564.151" - wire $or$ls180.v:5564$1012_Y - attribute \src "ls180.v:5738.33-5738.102" - wire $or$ls180.v:5738$1060_Y - attribute \src "ls180.v:5738.32-5738.144" - wire $or$ls180.v:5738$1061_Y - attribute \src "ls180.v:5738.31-5738.165" - wire $or$ls180.v:5738$1062_Y - attribute \src "ls180.v:5738.30-5738.201" - wire $or$ls180.v:5738$1063_Y - attribute \src "ls180.v:5744.28-5744.97" - wire $or$ls180.v:5744$1068_Y - attribute \src "ls180.v:5744.27-5744.139" - wire $or$ls180.v:5744$1069_Y - attribute \src "ls180.v:5744.26-5744.160" - wire $or$ls180.v:5744$1070_Y - attribute \src "ls180.v:5744.25-5744.196" - wire $or$ls180.v:5744$1071_Y - attribute \src "ls180.v:5745.30-5745.169" - wire width 32 $or$ls180.v:5745$1074_Y - attribute \src "ls180.v:5745.29-5745.246" - wire width 32 $or$ls180.v:5745$1076_Y - attribute \src "ls180.v:5745.28-5745.302" - wire width 32 $or$ls180.v:5745$1078_Y - attribute \src "ls180.v:5745.27-5745.373" - wire width 32 $or$ls180.v:5745$1080_Y - attribute \src "ls180.v:6499.55-6499.124" - wire width 8 $or$ls180.v:6499$2226_Y - attribute \src "ls180.v:6499.54-6499.161" - wire width 8 $or$ls180.v:6499$2227_Y - attribute \src "ls180.v:6499.53-6499.198" - wire width 8 $or$ls180.v:6499$2228_Y - attribute \src "ls180.v:6499.52-6499.235" - wire width 8 $or$ls180.v:6499$2229_Y - attribute \src "ls180.v:6499.51-6499.272" - wire width 8 $or$ls180.v:6499$2230_Y - attribute \src "ls180.v:6499.50-6499.309" - wire width 8 $or$ls180.v:6499$2231_Y - attribute \src "ls180.v:6499.49-6499.346" - wire width 8 $or$ls180.v:6499$2232_Y - attribute \src "ls180.v:6499.48-6499.383" - wire width 8 $or$ls180.v:6499$2233_Y - attribute \src "ls180.v:6499.47-6499.420" - wire width 8 $or$ls180.v:6499$2234_Y - attribute \src "ls180.v:6499.46-6499.458" - wire width 8 $or$ls180.v:6499$2235_Y - attribute \src "ls180.v:6499.45-6499.496" - wire width 8 $or$ls180.v:6499$2236_Y - attribute \src "ls180.v:6499.44-6499.534" - wire width 8 $or$ls180.v:6499$2237_Y - attribute \src "ls180.v:6499.43-6499.572" - wire width 8 $or$ls180.v:6499$2238_Y - attribute \src "ls180.v:6499.42-6499.610" - wire width 8 $or$ls180.v:6499$2239_Y - attribute \src "ls180.v:6826.90-6826.179" - wire $or$ls180.v:6826$2264_Y - attribute \src "ls180.v:6826.89-6826.254" - wire $or$ls180.v:6826$2267_Y - attribute \src "ls180.v:6826.88-6826.329" - wire $or$ls180.v:6826$2270_Y - attribute \src "ls180.v:6850.90-6850.179" - wire $or$ls180.v:6850$2280_Y - attribute \src "ls180.v:6850.89-6850.254" - wire $or$ls180.v:6850$2283_Y - attribute \src "ls180.v:6850.88-6850.329" - wire $or$ls180.v:6850$2286_Y - attribute \src "ls180.v:6874.90-6874.179" - wire $or$ls180.v:6874$2296_Y - attribute \src "ls180.v:6874.89-6874.254" - wire $or$ls180.v:6874$2299_Y - attribute \src "ls180.v:6874.88-6874.329" - wire $or$ls180.v:6874$2302_Y - attribute \src "ls180.v:6898.90-6898.179" - wire $or$ls180.v:6898$2312_Y - attribute \src "ls180.v:6898.89-6898.254" - wire $or$ls180.v:6898$2315_Y - attribute \src "ls180.v:6898.88-6898.329" - wire $or$ls180.v:6898$2318_Y - attribute \src "ls180.v:7412.20-7412.71" - wire $or$ls180.v:7412$2375_Y - attribute \src "ls180.v:7413.20-7413.71" - wire $or$ls180.v:7413$2376_Y - attribute \src "ls180.v:7414.20-7414.71" - wire $or$ls180.v:7414$2377_Y - attribute \src "ls180.v:7415.20-7415.71" - wire $or$ls180.v:7415$2378_Y - attribute \src "ls180.v:7416.20-7416.71" - wire $or$ls180.v:7416$2379_Y - attribute \src "ls180.v:7417.20-7417.71" - wire $or$ls180.v:7417$2380_Y - attribute \src "ls180.v:7418.20-7418.71" - wire $or$ls180.v:7418$2381_Y - attribute \src "ls180.v:7419.20-7419.71" - wire $or$ls180.v:7419$2382_Y - attribute \src "ls180.v:7420.20-7420.71" - wire $or$ls180.v:7420$2383_Y - attribute \src "ls180.v:7421.20-7421.71" - wire $or$ls180.v:7421$2384_Y - attribute \src "ls180.v:7422.21-7422.73" - wire $or$ls180.v:7422$2385_Y - attribute \src "ls180.v:7423.21-7423.73" - wire $or$ls180.v:7423$2386_Y - attribute \src "ls180.v:7424.21-7424.73" - wire $or$ls180.v:7424$2387_Y - attribute \src "ls180.v:7425.21-7425.73" - wire $or$ls180.v:7425$2388_Y - attribute \src "ls180.v:7426.21-7426.73" - wire $or$ls180.v:7426$2389_Y - attribute \src "ls180.v:7427.21-7427.73" - wire $or$ls180.v:7427$2390_Y - attribute \src "ls180.v:7428.21-7428.73" - wire $or$ls180.v:7428$2391_Y - attribute \src "ls180.v:7429.21-7429.73" - wire $or$ls180.v:7429$2392_Y - attribute \src "ls180.v:7430.21-7430.73" - wire $or$ls180.v:7430$2393_Y - attribute \src "ls180.v:7431.21-7431.73" - wire $or$ls180.v:7431$2394_Y - attribute \src "ls180.v:7432.21-7432.73" - wire $or$ls180.v:7432$2395_Y - attribute \src "ls180.v:7433.21-7433.73" - wire $or$ls180.v:7433$2396_Y - attribute \src "ls180.v:7434.21-7434.73" - wire $or$ls180.v:7434$2397_Y - attribute \src "ls180.v:7435.21-7435.73" - wire $or$ls180.v:7435$2398_Y - attribute \src "ls180.v:7436.21-7436.73" - wire $or$ls180.v:7436$2399_Y - attribute \src "ls180.v:7437.21-7437.73" - wire $or$ls180.v:7437$2400_Y - attribute \src "ls180.v:7438.21-7438.73" - wire $or$ls180.v:7438$2401_Y - attribute \src "ls180.v:7439.21-7439.73" - wire $or$ls180.v:7439$2402_Y - attribute \src "ls180.v:7440.21-7440.73" - wire $or$ls180.v:7440$2403_Y - attribute \src "ls180.v:7441.21-7441.73" - wire $or$ls180.v:7441$2404_Y - attribute \src "ls180.v:7442.21-7442.73" - wire $or$ls180.v:7442$2405_Y - attribute \src "ls180.v:7443.21-7443.73" - wire $or$ls180.v:7443$2406_Y - attribute \src "ls180.v:7444.21-7444.73" - wire $or$ls180.v:7444$2407_Y - attribute \src "ls180.v:7445.21-7445.73" - wire $or$ls180.v:7445$2408_Y - attribute \src "ls180.v:7446.21-7446.73" - wire $or$ls180.v:7446$2409_Y - attribute \src "ls180.v:7447.21-7447.73" - wire $or$ls180.v:7447$2410_Y - attribute \src "ls180.v:7448.7-7448.93" - wire $or$ls180.v:7448$2411_Y - attribute \src "ls180.v:7459.7-7459.93" - wire $or$ls180.v:7459$2412_Y - attribute \src "ls180.v:7470.7-7470.93" - wire $or$ls180.v:7470$2413_Y - attribute \src "ls180.v:7599.7-7599.107" - wire $or$ls180.v:7599$2449_Y - attribute \src "ls180.v:7645.7-7645.107" - wire $or$ls180.v:7645$2465_Y - attribute \src "ls180.v:7691.7-7691.107" - wire $or$ls180.v:7691$2481_Y - attribute \src "ls180.v:7737.7-7737.107" - wire $or$ls180.v:7737$2497_Y - attribute \src "ls180.v:7925.40-7925.125" - wire $or$ls180.v:7925$2518_Y - attribute \src "ls180.v:7925.39-7925.207" - wire $or$ls180.v:7925$2521_Y - attribute \src "ls180.v:7925.38-7925.289" - wire $or$ls180.v:7925$2524_Y - attribute \src "ls180.v:7925.37-7925.371" - wire $or$ls180.v:7925$2527_Y - attribute \src "ls180.v:7926.41-7926.126" - wire $or$ls180.v:7926$2530_Y - attribute \src "ls180.v:7926.40-7926.208" - wire $or$ls180.v:7926$2533_Y - attribute \src "ls180.v:7926.39-7926.290" - wire $or$ls180.v:7926$2536_Y - attribute \src "ls180.v:7926.38-7926.372" - wire $or$ls180.v:7926$2539_Y - attribute \src "ls180.v:7930.7-7930.49" - wire $or$ls180.v:7930$2540_Y - attribute \src "ls180.v:8093.22-8093.74" - wire $or$ls180.v:8093$2588_Y - attribute \src "ls180.v:8161.32-8161.85" - wire $or$ls180.v:8161$2600_Y - attribute \src "ls180.v:8167.8-8167.97" - wire $or$ls180.v:8167$2602_Y - attribute \src "ls180.v:8184.52-8184.139" - wire $or$ls180.v:8184$2607_Y - attribute \src "ls180.v:8185.51-8185.136" - wire $or$ls180.v:8185$2608_Y - attribute \src "ls180.v:8219.7-8219.87" - wire $or$ls180.v:8219$2611_Y - attribute \src "ls180.v:8242.33-8242.88" - wire $or$ls180.v:8242$2612_Y - attribute \src "ls180.v:8248.8-8248.99" - wire $or$ls180.v:8248$2614_Y - attribute \src "ls180.v:8265.53-8265.142" - wire $or$ls180.v:8265$2619_Y - attribute \src "ls180.v:8266.52-8266.139" - wire $or$ls180.v:8266$2620_Y - attribute \src "ls180.v:8300.7-8300.89" - wire $or$ls180.v:8300$2623_Y - attribute \src "ls180.v:8321.34-8321.91" - wire $or$ls180.v:8321$2624_Y - attribute \src "ls180.v:8327.8-8327.101" - wire $or$ls180.v:8327$2626_Y - attribute \src "ls180.v:8344.54-8344.145" - wire $or$ls180.v:8344$2631_Y - attribute \src "ls180.v:8345.53-8345.142" - wire $or$ls180.v:8345$2632_Y - attribute \src "ls180.v:8361.7-8361.91" - wire $or$ls180.v:8361$2635_Y - attribute \src "ls180.v:8550.8-8550.89" - wire $or$ls180.v:8550$2659_Y - attribute \src "ls180.v:8567.48-8567.127" - wire $or$ls180.v:8567$2664_Y - attribute \src "ls180.v:8568.47-8568.124" - wire $or$ls180.v:8568$2665_Y - attribute \src "ls180.v:8641.21-8641.65" - wire $or$ls180.v:8641$2683_Y - attribute \src "ls180.v:3162.46-3162.94" - wire width 13 $sshl$ls180.v:3162$83_Y - attribute \src "ls180.v:3319.46-3319.94" - wire width 13 $sshl$ls180.v:3319$113_Y - attribute \src "ls180.v:3476.46-3476.94" - wire width 13 $sshl$ls180.v:3476$143_Y - attribute \src "ls180.v:3633.46-3633.94" - wire width 13 $sshl$ls180.v:3633$173_Y - attribute \src "ls180.v:3193.63-3193.122" - wire width 3 $sub$ls180.v:3193$96_Y - attribute \src "ls180.v:3350.63-3350.122" - wire width 3 $sub$ls180.v:3350$126_Y - attribute \src "ls180.v:3507.63-3507.122" - wire width 3 $sub$ls180.v:3507$156_Y - attribute \src "ls180.v:3664.63-3664.122" - wire width 3 $sub$ls180.v:3664$186_Y - attribute \src "ls180.v:4070.38-4070.75" - wire width 31 $sub$ls180.v:4070$540_Y - attribute \src "ls180.v:4156.36-4156.68" - wire width 4 $sub$ls180.v:4156$585_Y - attribute \src "ls180.v:4186.36-4186.68" - wire width 4 $sub$ls180.v:4186$596_Y - attribute \src "ls180.v:4211.69-4211.110" - wire width 16 $sub$ls180.v:4211$602_Y - attribute \src "ls180.v:4212.69-4212.104" - wire width 16 $sub$ls180.v:4212$604_Y - attribute \src "ls180.v:4239.36-4239.66" - wire width 8 $sub$ls180.v:4239$608_Y - attribute \src "ls180.v:4493.60-4493.90" - wire width 32 $sub$ls180.v:4493$652_Y - attribute \src "ls180.v:4504.62-4504.104" - wire width 8 $sub$ls180.v:4504$654_Y - attribute \src "ls180.v:4521.60-4521.90" - wire width 32 $sub$ls180.v:4521$658_Y - attribute \src "ls180.v:4750.62-4750.93" - wire width 32 $sub$ls180.v:4750$688_Y - attribute \src "ls180.v:4755.62-4755.93" - wire width 32 $sub$ls180.v:4755$689_Y - attribute \src "ls180.v:4766.64-4766.122" - wire width 10 $sub$ls180.v:4766$692_Y - attribute \src "ls180.v:4787.62-4787.93" - wire width 32 $sub$ls180.v:4787$695_Y - attribute \src "ls180.v:5249.37-5249.75" - wire width 32 $sub$ls180.v:5249$968_Y - attribute \src "ls180.v:5264.62-5264.100" - wire width 32 $sub$ls180.v:5264$971_Y - attribute \src "ls180.v:5275.39-5275.77" - wire width 32 $sub$ls180.v:5275$976_Y - attribute \src "ls180.v:5350.40-5350.76" - wire width 5 $sub$ls180.v:5350$980_Y - attribute \src "ls180.v:5399.56-5399.104" - wire width 32 $sub$ls180.v:5399$994_Y - attribute \src "ls180.v:5489.71-5489.105" - wire width 32 $sub$ls180.v:5489$1000_Y - attribute \src "ls180.v:5558.40-5558.76" - wire width 5 $sub$ls180.v:5558$1011_Y - attribute \src "ls180.v:5577.61-5577.98" - wire width 16 $sub$ls180.v:5577$1017_Y - attribute \src "ls180.v:5578.61-5578.92" - wire width 16 $sub$ls180.v:5578$1019_Y - attribute \src "ls180.v:5606.32-5606.58" - wire width 8 $sub$ls180.v:5606$1023_Y - attribute \src "ls180.v:7494.31-7494.60" - wire width 32 $sub$ls180.v:7494$2420_Y - attribute \src "ls180.v:7515.31-7515.61" - wire width 10 $sub$ls180.v:7515$2425_Y - attribute \src "ls180.v:7521.34-7521.67" - wire $sub$ls180.v:7521$2426_Y - attribute \src "ls180.v:7532.36-7532.69" - wire $sub$ls180.v:7532$2429_Y - attribute \src "ls180.v:7596.59-7596.116" - wire width 4 $sub$ls180.v:7596$2447_Y - attribute \src "ls180.v:7615.46-7615.90" - wire width 3 $sub$ls180.v:7615$2451_Y - attribute \src "ls180.v:7642.59-7642.116" - wire width 4 $sub$ls180.v:7642$2463_Y - attribute \src "ls180.v:7661.46-7661.90" - wire width 3 $sub$ls180.v:7661$2467_Y - attribute \src "ls180.v:7688.59-7688.116" - wire width 4 $sub$ls180.v:7688$2479_Y - attribute \src "ls180.v:7707.46-7707.90" - wire width 3 $sub$ls180.v:7707$2483_Y - attribute \src "ls180.v:7734.59-7734.116" - wire width 4 $sub$ls180.v:7734$2495_Y - attribute \src "ls180.v:7753.46-7753.90" - wire width 3 $sub$ls180.v:7753$2499_Y - attribute \src "ls180.v:7764.25-7764.48" - wire width 5 $sub$ls180.v:7764$2503_Y - attribute \src "ls180.v:7771.25-7771.48" - wire width 4 $sub$ls180.v:7771$2506_Y - attribute \src "ls180.v:7903.33-7903.64" - wire $sub$ls180.v:7903$2511_Y - attribute \src "ls180.v:7918.33-7918.64" - wire width 3 $sub$ls180.v:7918$2514_Y - attribute \src "ls180.v:8045.33-8045.64" - wire width 5 $sub$ls180.v:8045$2573_Y - attribute \src "ls180.v:8067.33-8067.64" - wire width 5 $sub$ls180.v:8067$2584_Y - attribute \src "ls180.v:8102.33-8102.64" - wire width 3 $sub$ls180.v:8102$2589_Y - attribute \src "ls180.v:8126.30-8126.53" - wire width 32 $sub$ls180.v:8126$2592_Y - attribute \src "ls180.v:8140.30-8140.53" - wire width 32 $sub$ls180.v:8140$2596_Y - attribute \src "ls180.v:8543.36-8543.70" - wire width 6 $sub$ls180.v:8543$2657_Y - attribute \src "ls180.v:8629.36-8629.70" - wire width 6 $sub$ls180.v:8629$2679_Y - attribute \src "ls180.v:8650.29-8650.56" - wire width 3 $sub$ls180.v:8650$2684_Y - attribute \src "ls180.v:8777.22-8777.42" - wire width 20 $sub$ls180.v:8777$2691_Y - attribute \src "ls180.v:4847.353-4847.425" - wire $xor$ls180.v:4847$702_Y - attribute \src "ls180.v:4847.200-4847.272" - wire $xor$ls180.v:4847$703_Y - attribute \src "ls180.v:4847.160-4847.273" - wire $xor$ls180.v:4847$704_Y - attribute \src "ls180.v:4848.353-4848.425" - wire $xor$ls180.v:4848$705_Y - attribute \src "ls180.v:4848.200-4848.272" - wire $xor$ls180.v:4848$706_Y - attribute \src "ls180.v:4848.160-4848.273" - wire $xor$ls180.v:4848$707_Y - attribute \src "ls180.v:4849.353-4849.425" - wire $xor$ls180.v:4849$708_Y - attribute \src "ls180.v:4849.200-4849.272" - wire $xor$ls180.v:4849$709_Y - attribute \src "ls180.v:4849.160-4849.273" - wire $xor$ls180.v:4849$710_Y - attribute \src "ls180.v:4850.353-4850.425" - wire $xor$ls180.v:4850$711_Y - attribute \src "ls180.v:4850.200-4850.272" - wire $xor$ls180.v:4850$712_Y - attribute \src "ls180.v:4850.160-4850.273" - wire $xor$ls180.v:4850$713_Y - attribute \src "ls180.v:4851.353-4851.425" - wire $xor$ls180.v:4851$714_Y - attribute \src "ls180.v:4851.200-4851.272" - wire $xor$ls180.v:4851$715_Y - attribute \src "ls180.v:4851.160-4851.273" - wire $xor$ls180.v:4851$716_Y - attribute \src "ls180.v:4852.353-4852.425" - wire $xor$ls180.v:4852$717_Y - attribute \src "ls180.v:4852.200-4852.272" - wire $xor$ls180.v:4852$718_Y - attribute \src "ls180.v:4852.160-4852.273" - wire $xor$ls180.v:4852$719_Y - attribute \src "ls180.v:4853.353-4853.425" - wire $xor$ls180.v:4853$720_Y - attribute \src "ls180.v:4853.200-4853.272" - wire $xor$ls180.v:4853$721_Y - attribute \src "ls180.v:4853.160-4853.273" - wire $xor$ls180.v:4853$722_Y - attribute \src "ls180.v:4854.353-4854.425" - wire $xor$ls180.v:4854$723_Y - attribute \src "ls180.v:4854.200-4854.272" - wire $xor$ls180.v:4854$724_Y - attribute \src "ls180.v:4854.160-4854.273" - wire $xor$ls180.v:4854$725_Y - attribute \src "ls180.v:4855.353-4855.425" - wire $xor$ls180.v:4855$726_Y - attribute \src "ls180.v:4855.200-4855.272" - wire $xor$ls180.v:4855$727_Y - attribute \src "ls180.v:4855.160-4855.273" - wire $xor$ls180.v:4855$728_Y - attribute \src "ls180.v:4856.354-4856.426" - wire $xor$ls180.v:4856$729_Y - attribute \src "ls180.v:4856.201-4856.273" - wire $xor$ls180.v:4856$730_Y - attribute \src "ls180.v:4856.161-4856.274" - wire $xor$ls180.v:4856$731_Y - attribute \src "ls180.v:4857.361-4857.434" - wire $xor$ls180.v:4857$732_Y - attribute \src "ls180.v:4857.205-4857.278" - wire $xor$ls180.v:4857$733_Y - attribute \src "ls180.v:4857.164-4857.279" - wire $xor$ls180.v:4857$734_Y - attribute \src "ls180.v:4858.361-4858.434" - wire $xor$ls180.v:4858$735_Y - attribute \src "ls180.v:4858.205-4858.278" - wire $xor$ls180.v:4858$736_Y - attribute \src "ls180.v:4858.164-4858.279" - wire $xor$ls180.v:4858$737_Y - attribute \src "ls180.v:4859.361-4859.434" - wire $xor$ls180.v:4859$738_Y - attribute \src "ls180.v:4859.205-4859.278" - wire $xor$ls180.v:4859$739_Y - attribute \src "ls180.v:4859.164-4859.279" - wire $xor$ls180.v:4859$740_Y - attribute \src "ls180.v:4860.361-4860.434" - wire $xor$ls180.v:4860$741_Y - attribute \src "ls180.v:4860.205-4860.278" - wire $xor$ls180.v:4860$742_Y - attribute \src "ls180.v:4860.164-4860.279" - wire $xor$ls180.v:4860$743_Y - attribute \src "ls180.v:4861.361-4861.434" - wire $xor$ls180.v:4861$744_Y - attribute \src "ls180.v:4861.205-4861.278" - wire $xor$ls180.v:4861$745_Y - attribute \src "ls180.v:4861.164-4861.279" - wire $xor$ls180.v:4861$746_Y - attribute \src "ls180.v:4862.361-4862.434" - wire $xor$ls180.v:4862$747_Y - attribute \src "ls180.v:4862.205-4862.278" - wire $xor$ls180.v:4862$748_Y - attribute \src "ls180.v:4862.164-4862.279" - wire $xor$ls180.v:4862$749_Y - attribute \src "ls180.v:4863.361-4863.434" - wire $xor$ls180.v:4863$750_Y - attribute \src "ls180.v:4863.205-4863.278" - wire $xor$ls180.v:4863$751_Y - attribute \src "ls180.v:4863.164-4863.279" - wire $xor$ls180.v:4863$752_Y - attribute \src "ls180.v:4864.361-4864.434" - wire $xor$ls180.v:4864$753_Y - attribute \src "ls180.v:4864.205-4864.278" - wire $xor$ls180.v:4864$754_Y - attribute \src "ls180.v:4864.164-4864.279" - wire $xor$ls180.v:4864$755_Y - attribute \src "ls180.v:4865.361-4865.434" - wire $xor$ls180.v:4865$756_Y - attribute \src "ls180.v:4865.205-4865.278" - wire $xor$ls180.v:4865$757_Y - attribute \src "ls180.v:4865.164-4865.279" - wire $xor$ls180.v:4865$758_Y - attribute \src "ls180.v:4866.361-4866.434" - wire $xor$ls180.v:4866$759_Y - attribute \src "ls180.v:4866.205-4866.278" - wire $xor$ls180.v:4866$760_Y - attribute \src "ls180.v:4866.164-4866.279" - wire $xor$ls180.v:4866$761_Y - attribute \src "ls180.v:4867.361-4867.434" - wire $xor$ls180.v:4867$762_Y - attribute \src "ls180.v:4867.205-4867.278" - wire $xor$ls180.v:4867$763_Y - attribute \src "ls180.v:4867.164-4867.279" - wire $xor$ls180.v:4867$764_Y - attribute \src "ls180.v:4868.361-4868.434" - wire $xor$ls180.v:4868$765_Y - attribute \src "ls180.v:4868.205-4868.278" - wire $xor$ls180.v:4868$766_Y - attribute \src "ls180.v:4868.164-4868.279" - wire $xor$ls180.v:4868$767_Y - attribute \src "ls180.v:4869.361-4869.434" - wire $xor$ls180.v:4869$768_Y - attribute \src "ls180.v:4869.205-4869.278" - wire $xor$ls180.v:4869$769_Y - attribute \src "ls180.v:4869.164-4869.279" - wire $xor$ls180.v:4869$770_Y - attribute \src "ls180.v:4870.361-4870.434" - wire $xor$ls180.v:4870$771_Y - attribute \src "ls180.v:4870.205-4870.278" - wire $xor$ls180.v:4870$772_Y - attribute \src "ls180.v:4870.164-4870.279" - wire $xor$ls180.v:4870$773_Y - attribute \src "ls180.v:4871.361-4871.434" - wire $xor$ls180.v:4871$774_Y - attribute \src "ls180.v:4871.205-4871.278" - wire $xor$ls180.v:4871$775_Y - attribute \src "ls180.v:4871.164-4871.279" - wire $xor$ls180.v:4871$776_Y - attribute \src "ls180.v:4872.361-4872.434" - wire $xor$ls180.v:4872$777_Y - attribute \src "ls180.v:4872.205-4872.278" - wire $xor$ls180.v:4872$778_Y - attribute \src "ls180.v:4872.164-4872.279" - wire $xor$ls180.v:4872$779_Y - attribute \src "ls180.v:4873.361-4873.434" - wire $xor$ls180.v:4873$780_Y - attribute \src "ls180.v:4873.205-4873.278" - wire $xor$ls180.v:4873$781_Y - attribute \src "ls180.v:4873.164-4873.279" - wire $xor$ls180.v:4873$782_Y - attribute \src "ls180.v:4874.361-4874.434" - wire $xor$ls180.v:4874$783_Y - attribute \src "ls180.v:4874.205-4874.278" - wire $xor$ls180.v:4874$784_Y - attribute \src "ls180.v:4874.164-4874.279" - wire $xor$ls180.v:4874$785_Y - attribute \src "ls180.v:4875.361-4875.434" - wire $xor$ls180.v:4875$786_Y - attribute \src "ls180.v:4875.205-4875.278" - wire $xor$ls180.v:4875$787_Y - attribute \src "ls180.v:4875.164-4875.279" - wire $xor$ls180.v:4875$788_Y - attribute \src "ls180.v:4876.361-4876.434" - wire $xor$ls180.v:4876$789_Y - attribute \src "ls180.v:4876.205-4876.278" - wire $xor$ls180.v:4876$790_Y - attribute \src "ls180.v:4876.164-4876.279" - wire $xor$ls180.v:4876$791_Y - attribute \src "ls180.v:4877.360-4877.432" - wire $xor$ls180.v:4877$792_Y - attribute \src "ls180.v:4877.205-4877.277" - wire $xor$ls180.v:4877$793_Y - attribute \src "ls180.v:4877.164-4877.278" - wire $xor$ls180.v:4877$794_Y - attribute \src "ls180.v:4878.360-4878.432" - wire $xor$ls180.v:4878$795_Y - attribute \src "ls180.v:4878.205-4878.277" - wire $xor$ls180.v:4878$796_Y - attribute \src "ls180.v:4878.164-4878.278" - wire $xor$ls180.v:4878$797_Y - attribute \src "ls180.v:4879.360-4879.432" - wire $xor$ls180.v:4879$798_Y - attribute \src "ls180.v:4879.205-4879.277" - wire $xor$ls180.v:4879$799_Y - attribute \src "ls180.v:4879.164-4879.278" - wire $xor$ls180.v:4879$800_Y - attribute \src "ls180.v:4880.360-4880.432" - wire $xor$ls180.v:4880$801_Y - attribute \src "ls180.v:4880.205-4880.277" - wire $xor$ls180.v:4880$802_Y - attribute \src "ls180.v:4880.164-4880.278" - wire $xor$ls180.v:4880$803_Y - attribute \src "ls180.v:4881.360-4881.432" - wire $xor$ls180.v:4881$804_Y - attribute \src "ls180.v:4881.205-4881.277" - wire $xor$ls180.v:4881$805_Y - attribute \src "ls180.v:4881.164-4881.278" - wire $xor$ls180.v:4881$806_Y - attribute \src "ls180.v:4882.360-4882.432" - wire $xor$ls180.v:4882$807_Y - attribute \src "ls180.v:4882.205-4882.277" - wire $xor$ls180.v:4882$808_Y - attribute \src "ls180.v:4882.164-4882.278" - wire $xor$ls180.v:4882$809_Y - attribute \src "ls180.v:4883.360-4883.432" - wire $xor$ls180.v:4883$810_Y - attribute \src "ls180.v:4883.205-4883.277" - wire $xor$ls180.v:4883$811_Y - attribute \src "ls180.v:4883.164-4883.278" - wire $xor$ls180.v:4883$812_Y - attribute \src "ls180.v:4884.360-4884.432" - wire $xor$ls180.v:4884$813_Y - attribute \src "ls180.v:4884.205-4884.277" - wire $xor$ls180.v:4884$814_Y - attribute \src "ls180.v:4884.164-4884.278" - wire $xor$ls180.v:4884$815_Y - attribute \src "ls180.v:4885.360-4885.432" - wire $xor$ls180.v:4885$816_Y - attribute \src "ls180.v:4885.205-4885.277" - wire $xor$ls180.v:4885$817_Y - attribute \src "ls180.v:4885.164-4885.278" - wire $xor$ls180.v:4885$818_Y - attribute \src "ls180.v:4886.360-4886.432" - wire $xor$ls180.v:4886$819_Y - attribute \src "ls180.v:4886.205-4886.277" - wire $xor$ls180.v:4886$820_Y - attribute \src "ls180.v:4886.164-4886.278" - wire $xor$ls180.v:4886$821_Y - attribute \src "ls180.v:4907.899-4907.983" - wire $xor$ls180.v:4907$835_Y - attribute \src "ls180.v:4907.634-4907.718" - wire $xor$ls180.v:4907$836_Y - attribute \src "ls180.v:4907.588-4907.719" - wire $xor$ls180.v:4907$837_Y - attribute \src "ls180.v:4907.234-4907.318" - wire $xor$ls180.v:4907$838_Y - attribute \src "ls180.v:4907.187-4907.319" - wire $xor$ls180.v:4907$839_Y - attribute \src "ls180.v:4908.899-4908.983" - wire $xor$ls180.v:4908$840_Y - attribute \src "ls180.v:4908.634-4908.718" - wire $xor$ls180.v:4908$841_Y - attribute \src "ls180.v:4908.588-4908.719" - wire $xor$ls180.v:4908$842_Y - attribute \src "ls180.v:4908.234-4908.318" - wire $xor$ls180.v:4908$843_Y - attribute \src "ls180.v:4908.187-4908.319" - wire $xor$ls180.v:4908$844_Y - attribute \src "ls180.v:4917.899-4917.983" - wire $xor$ls180.v:4917$846_Y - attribute \src "ls180.v:4917.634-4917.718" - wire $xor$ls180.v:4917$847_Y - attribute \src "ls180.v:4917.588-4917.719" - wire $xor$ls180.v:4917$848_Y - attribute \src "ls180.v:4917.234-4917.318" - wire $xor$ls180.v:4917$849_Y - attribute \src "ls180.v:4917.187-4917.319" - wire $xor$ls180.v:4917$850_Y - attribute \src "ls180.v:4918.899-4918.983" - wire $xor$ls180.v:4918$851_Y - attribute \src "ls180.v:4918.634-4918.718" - wire $xor$ls180.v:4918$852_Y - attribute \src "ls180.v:4918.588-4918.719" - wire $xor$ls180.v:4918$853_Y - attribute \src "ls180.v:4918.234-4918.318" - wire $xor$ls180.v:4918$854_Y - attribute \src "ls180.v:4918.187-4918.319" - wire $xor$ls180.v:4918$855_Y - attribute \src "ls180.v:4927.899-4927.983" - wire $xor$ls180.v:4927$857_Y - attribute \src "ls180.v:4927.634-4927.718" - wire $xor$ls180.v:4927$858_Y - attribute \src "ls180.v:4927.588-4927.719" - wire $xor$ls180.v:4927$859_Y - attribute \src "ls180.v:4927.234-4927.318" - wire $xor$ls180.v:4927$860_Y - attribute \src "ls180.v:4927.187-4927.319" - wire $xor$ls180.v:4927$861_Y - attribute \src "ls180.v:4928.899-4928.983" - wire $xor$ls180.v:4928$862_Y - attribute \src "ls180.v:4928.634-4928.718" - wire $xor$ls180.v:4928$863_Y - attribute \src "ls180.v:4928.588-4928.719" - wire $xor$ls180.v:4928$864_Y - attribute \src "ls180.v:4928.234-4928.318" - wire $xor$ls180.v:4928$865_Y - attribute \src "ls180.v:4928.187-4928.319" - wire $xor$ls180.v:4928$866_Y - attribute \src "ls180.v:4937.899-4937.983" - wire $xor$ls180.v:4937$868_Y - attribute \src "ls180.v:4937.634-4937.718" - wire $xor$ls180.v:4937$869_Y - attribute \src "ls180.v:4937.588-4937.719" - wire $xor$ls180.v:4937$870_Y - attribute \src "ls180.v:4937.234-4937.318" - wire $xor$ls180.v:4937$871_Y - attribute \src "ls180.v:4937.187-4937.319" - wire $xor$ls180.v:4937$872_Y - attribute \src "ls180.v:4938.899-4938.983" - wire $xor$ls180.v:4938$873_Y - attribute \src "ls180.v:4938.634-4938.718" - wire $xor$ls180.v:4938$874_Y - attribute \src "ls180.v:4938.588-4938.719" - wire $xor$ls180.v:4938$875_Y - attribute \src "ls180.v:4938.234-4938.318" - wire $xor$ls180.v:4938$876_Y - attribute \src "ls180.v:4938.187-4938.319" - wire $xor$ls180.v:4938$877_Y - attribute \src "ls180.v:5089.879-5089.961" - wire $xor$ls180.v:5089$910_Y - attribute \src "ls180.v:5089.620-5089.702" - wire $xor$ls180.v:5089$911_Y - attribute \src "ls180.v:5089.575-5089.703" - wire $xor$ls180.v:5089$912_Y - attribute \src "ls180.v:5089.229-5089.311" - wire $xor$ls180.v:5089$913_Y - attribute \src "ls180.v:5089.183-5089.312" - wire $xor$ls180.v:5089$914_Y - attribute \src "ls180.v:5090.879-5090.961" - wire $xor$ls180.v:5090$915_Y - attribute \src "ls180.v:5090.620-5090.702" - wire $xor$ls180.v:5090$916_Y - attribute \src "ls180.v:5090.575-5090.703" - wire $xor$ls180.v:5090$917_Y - attribute \src "ls180.v:5090.229-5090.311" - wire $xor$ls180.v:5090$918_Y - attribute \src "ls180.v:5090.183-5090.312" - wire $xor$ls180.v:5090$919_Y - attribute \src "ls180.v:5099.879-5099.961" - wire $xor$ls180.v:5099$921_Y - attribute \src "ls180.v:5099.620-5099.702" - wire $xor$ls180.v:5099$922_Y - attribute \src "ls180.v:5099.575-5099.703" - wire $xor$ls180.v:5099$923_Y - attribute \src "ls180.v:5099.229-5099.311" - wire $xor$ls180.v:5099$924_Y - attribute \src "ls180.v:5099.183-5099.312" - wire $xor$ls180.v:5099$925_Y - attribute \src "ls180.v:5100.879-5100.961" - wire $xor$ls180.v:5100$926_Y - attribute \src "ls180.v:5100.620-5100.702" - wire $xor$ls180.v:5100$927_Y - attribute \src "ls180.v:5100.575-5100.703" - wire $xor$ls180.v:5100$928_Y - attribute \src "ls180.v:5100.229-5100.311" - wire $xor$ls180.v:5100$929_Y - attribute \src "ls180.v:5100.183-5100.312" - wire $xor$ls180.v:5100$930_Y - attribute \src "ls180.v:5109.879-5109.961" - wire $xor$ls180.v:5109$932_Y - attribute \src "ls180.v:5109.620-5109.702" - wire $xor$ls180.v:5109$933_Y - attribute \src "ls180.v:5109.575-5109.703" - wire $xor$ls180.v:5109$934_Y - attribute \src "ls180.v:5109.229-5109.311" - wire $xor$ls180.v:5109$935_Y - attribute \src "ls180.v:5109.183-5109.312" - wire $xor$ls180.v:5109$936_Y - attribute \src "ls180.v:5110.879-5110.961" - wire $xor$ls180.v:5110$937_Y - attribute \src "ls180.v:5110.620-5110.702" - wire $xor$ls180.v:5110$938_Y - attribute \src "ls180.v:5110.575-5110.703" - wire $xor$ls180.v:5110$939_Y - attribute \src "ls180.v:5110.229-5110.311" - wire $xor$ls180.v:5110$940_Y - attribute \src "ls180.v:5110.183-5110.312" - wire $xor$ls180.v:5110$941_Y - attribute \src "ls180.v:5119.879-5119.961" - wire $xor$ls180.v:5119$943_Y - attribute \src "ls180.v:5119.620-5119.702" - wire $xor$ls180.v:5119$944_Y - attribute \src "ls180.v:5119.575-5119.703" - wire $xor$ls180.v:5119$945_Y - attribute \src "ls180.v:5119.229-5119.311" - wire $xor$ls180.v:5119$946_Y - attribute \src "ls180.v:5119.183-5119.312" - wire $xor$ls180.v:5119$947_Y - attribute \src "ls180.v:5120.879-5120.961" - wire $xor$ls180.v:5120$948_Y - attribute \src "ls180.v:5120.620-5120.702" - wire $xor$ls180.v:5120$949_Y - attribute \src "ls180.v:5120.575-5120.703" - wire $xor$ls180.v:5120$950_Y - attribute \src "ls180.v:5120.229-5120.311" - wire $xor$ls180.v:5120$951_Y - attribute \src "ls180.v:5120.183-5120.312" - wire $xor$ls180.v:5120$952_Y - attribute \src "ls180.v:1725.11-1725.42" - wire width 3 \builder_bankmachine0_next_state - attribute \src "ls180.v:1724.11-1724.37" - wire width 3 \builder_bankmachine0_state - attribute \src "ls180.v:1727.11-1727.42" - wire width 3 \builder_bankmachine1_next_state - attribute \src "ls180.v:1726.11-1726.37" - wire width 3 \builder_bankmachine1_state - attribute \src "ls180.v:1729.11-1729.42" - wire width 3 \builder_bankmachine2_next_state - attribute \src "ls180.v:1728.11-1728.37" - wire width 3 \builder_bankmachine2_state - attribute \src "ls180.v:1731.11-1731.42" - wire width 3 \builder_bankmachine3_next_state - attribute \src "ls180.v:1730.11-1730.37" - wire width 3 \builder_bankmachine3_state - attribute \src "ls180.v:2576.5-2576.34" - wire \builder_comb_rhs_array_muxed0 - attribute \src "ls180.v:2577.12-2577.41" - wire width 13 \builder_comb_rhs_array_muxed1 - attribute \src "ls180.v:2589.5-2589.35" - wire \builder_comb_rhs_array_muxed10 - attribute \src "ls180.v:2590.5-2590.35" - wire \builder_comb_rhs_array_muxed11 - attribute \src "ls180.v:2594.12-2594.42" - wire width 22 \builder_comb_rhs_array_muxed12 - attribute \src "ls180.v:2595.5-2595.35" - wire \builder_comb_rhs_array_muxed13 - attribute \src "ls180.v:2596.5-2596.35" - wire \builder_comb_rhs_array_muxed14 - attribute \src "ls180.v:2597.12-2597.42" - wire width 22 \builder_comb_rhs_array_muxed15 - attribute \src "ls180.v:2598.5-2598.35" - wire \builder_comb_rhs_array_muxed16 - attribute \src "ls180.v:2599.5-2599.35" - wire \builder_comb_rhs_array_muxed17 - attribute \src "ls180.v:2600.12-2600.42" - wire width 22 \builder_comb_rhs_array_muxed18 - attribute \src "ls180.v:2601.5-2601.35" - wire \builder_comb_rhs_array_muxed19 - attribute \src "ls180.v:2578.11-2578.40" - wire width 2 \builder_comb_rhs_array_muxed2 - attribute \src "ls180.v:2602.5-2602.35" - wire \builder_comb_rhs_array_muxed20 - attribute \src "ls180.v:2603.12-2603.42" - wire width 22 \builder_comb_rhs_array_muxed21 - attribute \src "ls180.v:2604.5-2604.35" - wire \builder_comb_rhs_array_muxed22 - attribute \src "ls180.v:2605.5-2605.35" - wire \builder_comb_rhs_array_muxed23 - attribute \src "ls180.v:2606.12-2606.42" - wire width 32 \builder_comb_rhs_array_muxed24 - attribute \src "ls180.v:2607.12-2607.42" - wire width 32 \builder_comb_rhs_array_muxed25 - attribute \src "ls180.v:2608.11-2608.41" - wire width 4 \builder_comb_rhs_array_muxed26 - attribute \src "ls180.v:2609.5-2609.35" - wire \builder_comb_rhs_array_muxed27 - attribute \src "ls180.v:2610.5-2610.35" - wire \builder_comb_rhs_array_muxed28 - attribute \src "ls180.v:2611.5-2611.35" - wire \builder_comb_rhs_array_muxed29 - attribute \src "ls180.v:2579.5-2579.34" - wire \builder_comb_rhs_array_muxed3 - attribute \src "ls180.v:2612.11-2612.41" - wire width 3 \builder_comb_rhs_array_muxed30 - attribute \src "ls180.v:2613.11-2613.41" - wire width 2 \builder_comb_rhs_array_muxed31 - attribute \src "ls180.v:2580.5-2580.34" - wire \builder_comb_rhs_array_muxed4 - attribute \src "ls180.v:2581.5-2581.34" - wire \builder_comb_rhs_array_muxed5 - attribute \src "ls180.v:2585.5-2585.34" - wire \builder_comb_rhs_array_muxed6 - attribute \src "ls180.v:2586.12-2586.41" - wire width 13 \builder_comb_rhs_array_muxed7 - attribute \src "ls180.v:2587.11-2587.40" - wire width 2 \builder_comb_rhs_array_muxed8 - attribute \src "ls180.v:2588.5-2588.34" - wire \builder_comb_rhs_array_muxed9 - attribute \src "ls180.v:2582.5-2582.32" - wire \builder_comb_t_array_muxed0 - attribute \src "ls180.v:2583.5-2583.32" - wire \builder_comb_t_array_muxed1 - attribute \src "ls180.v:2584.5-2584.32" - wire \builder_comb_t_array_muxed2 - attribute \src "ls180.v:2591.5-2591.32" - wire \builder_comb_t_array_muxed3 - attribute \src "ls180.v:2592.5-2592.32" - wire \builder_comb_t_array_muxed4 - attribute \src "ls180.v:2593.5-2593.32" - wire \builder_comb_t_array_muxed5 - attribute \src "ls180.v:1711.5-1711.34" - wire \builder_converter0_next_state - attribute \src "ls180.v:1710.5-1710.29" - wire \builder_converter0_state - attribute \src "ls180.v:1715.5-1715.34" - wire \builder_converter1_next_state - attribute \src "ls180.v:1714.5-1714.29" - wire \builder_converter1_state - attribute \src "ls180.v:1719.5-1719.34" - wire \builder_converter2_next_state - attribute \src "ls180.v:1718.5-1718.29" - wire \builder_converter2_state - attribute \src "ls180.v:1756.5-1756.33" - wire \builder_converter_next_state - attribute \src "ls180.v:1755.5-1755.28" - wire \builder_converter_state - attribute \src "ls180.v:1876.12-1876.25" - wire width 20 \builder_count - attribute \src "ls180.v:2564.13-2564.41" - wire width 14 \builder_csr_interconnect_adr - attribute \src "ls180.v:2567.12-2567.42" - wire width 8 \builder_csr_interconnect_dat_r - attribute \src "ls180.v:2566.12-2566.42" - wire width 8 \builder_csr_interconnect_dat_w - attribute \src "ls180.v:2565.6-2565.33" - wire \builder_csr_interconnect_we - attribute \src "ls180.v:1914.12-1914.42" - wire width 8 \builder_csrbank0_bus_errors0_r - attribute \src "ls180.v:1913.6-1913.37" - wire \builder_csrbank0_bus_errors0_re - attribute \src "ls180.v:1916.12-1916.42" - wire width 8 \builder_csrbank0_bus_errors0_w - attribute \src "ls180.v:1915.6-1915.37" - wire \builder_csrbank0_bus_errors0_we - attribute \src "ls180.v:1910.12-1910.42" - wire width 8 \builder_csrbank0_bus_errors1_r - attribute \src "ls180.v:1909.6-1909.37" - wire \builder_csrbank0_bus_errors1_re - attribute \src "ls180.v:1912.12-1912.42" - wire width 8 \builder_csrbank0_bus_errors1_w - attribute \src "ls180.v:1911.6-1911.37" - wire \builder_csrbank0_bus_errors1_we - attribute \src "ls180.v:1906.12-1906.42" - wire width 8 \builder_csrbank0_bus_errors2_r - attribute \src "ls180.v:1905.6-1905.37" - wire \builder_csrbank0_bus_errors2_re - attribute \src "ls180.v:1908.12-1908.42" - wire width 8 \builder_csrbank0_bus_errors2_w - attribute \src "ls180.v:1907.6-1907.37" - wire \builder_csrbank0_bus_errors2_we - attribute \src "ls180.v:1902.12-1902.42" - wire width 8 \builder_csrbank0_bus_errors3_r - attribute \src "ls180.v:1901.6-1901.37" - wire \builder_csrbank0_bus_errors3_re - attribute \src "ls180.v:1904.12-1904.42" - wire width 8 \builder_csrbank0_bus_errors3_w - attribute \src "ls180.v:1903.6-1903.37" - wire \builder_csrbank0_bus_errors3_we - attribute \src "ls180.v:1882.6-1882.31" - wire \builder_csrbank0_reset0_r - attribute \src "ls180.v:1881.6-1881.32" - wire \builder_csrbank0_reset0_re - attribute \src "ls180.v:1884.6-1884.31" - wire \builder_csrbank0_reset0_w - attribute \src "ls180.v:1883.6-1883.32" - wire \builder_csrbank0_reset0_we - attribute \src "ls180.v:1898.12-1898.39" - wire width 8 \builder_csrbank0_scratch0_r - attribute \src "ls180.v:1897.6-1897.34" - wire \builder_csrbank0_scratch0_re - attribute \src "ls180.v:1900.12-1900.39" - wire width 8 \builder_csrbank0_scratch0_w - attribute \src "ls180.v:1899.6-1899.34" - wire \builder_csrbank0_scratch0_we - attribute \src "ls180.v:1894.12-1894.39" - wire width 8 \builder_csrbank0_scratch1_r - attribute \src "ls180.v:1893.6-1893.34" - wire \builder_csrbank0_scratch1_re - attribute \src "ls180.v:1896.12-1896.39" - wire width 8 \builder_csrbank0_scratch1_w - attribute \src "ls180.v:1895.6-1895.34" - wire \builder_csrbank0_scratch1_we - attribute \src "ls180.v:1890.12-1890.39" - wire width 8 \builder_csrbank0_scratch2_r - attribute \src "ls180.v:1889.6-1889.34" - wire \builder_csrbank0_scratch2_re - attribute \src "ls180.v:1892.12-1892.39" - wire width 8 \builder_csrbank0_scratch2_w - attribute \src "ls180.v:1891.6-1891.34" - wire \builder_csrbank0_scratch2_we - attribute \src "ls180.v:1886.12-1886.39" - wire width 8 \builder_csrbank0_scratch3_r - attribute \src "ls180.v:1885.6-1885.34" - wire \builder_csrbank0_scratch3_re - attribute \src "ls180.v:1888.12-1888.39" - wire width 8 \builder_csrbank0_scratch3_w - attribute \src "ls180.v:1887.6-1887.34" - wire \builder_csrbank0_scratch3_we - attribute \src "ls180.v:1917.6-1917.26" - wire \builder_csrbank0_sel - attribute \src "ls180.v:2388.12-2388.40" - wire width 8 \builder_csrbank10_control0_r - attribute \src "ls180.v:2387.6-2387.35" - wire \builder_csrbank10_control0_re - attribute \src "ls180.v:2390.12-2390.40" - wire width 8 \builder_csrbank10_control0_w - attribute \src "ls180.v:2389.6-2389.35" - wire \builder_csrbank10_control0_we - attribute \src "ls180.v:2384.12-2384.40" - wire width 8 \builder_csrbank10_control1_r - attribute \src "ls180.v:2383.6-2383.35" - wire \builder_csrbank10_control1_re - attribute \src "ls180.v:2386.12-2386.40" - wire width 8 \builder_csrbank10_control1_w - attribute \src "ls180.v:2385.6-2385.35" - wire \builder_csrbank10_control1_we - attribute \src "ls180.v:2404.6-2404.29" - wire \builder_csrbank10_cs0_r - attribute \src "ls180.v:2403.6-2403.30" - wire \builder_csrbank10_cs0_re - attribute \src "ls180.v:2406.6-2406.29" - wire \builder_csrbank10_cs0_w - attribute \src "ls180.v:2405.6-2405.30" - wire \builder_csrbank10_cs0_we - attribute \src "ls180.v:2408.6-2408.35" - wire \builder_csrbank10_loopback0_r - attribute \src "ls180.v:2407.6-2407.36" - wire \builder_csrbank10_loopback0_re - attribute \src "ls180.v:2410.6-2410.35" - wire \builder_csrbank10_loopback0_w - attribute \src "ls180.v:2409.6-2409.36" - wire \builder_csrbank10_loopback0_we - attribute \src "ls180.v:2400.12-2400.36" - wire width 8 \builder_csrbank10_miso_r - attribute \src "ls180.v:2399.6-2399.31" - wire \builder_csrbank10_miso_re - attribute \src "ls180.v:2402.12-2402.36" - wire width 8 \builder_csrbank10_miso_w - attribute \src "ls180.v:2401.6-2401.31" - wire \builder_csrbank10_miso_we - attribute \src "ls180.v:2396.12-2396.37" - wire width 8 \builder_csrbank10_mosi0_r - attribute \src "ls180.v:2395.6-2395.32" - wire \builder_csrbank10_mosi0_re - attribute \src "ls180.v:2398.12-2398.37" - wire width 8 \builder_csrbank10_mosi0_w - attribute \src "ls180.v:2397.6-2397.32" - wire \builder_csrbank10_mosi0_we - attribute \src "ls180.v:2411.6-2411.27" - wire \builder_csrbank10_sel - attribute \src "ls180.v:2392.6-2392.32" - wire \builder_csrbank10_status_r - attribute \src "ls180.v:2391.6-2391.33" - wire \builder_csrbank10_status_re - attribute \src "ls180.v:2394.6-2394.32" - wire \builder_csrbank10_status_w - attribute \src "ls180.v:2393.6-2393.33" - wire \builder_csrbank10_status_we - attribute \src "ls180.v:2449.12-2449.44" - wire width 8 \builder_csrbank11_clk_divider0_r - attribute \src "ls180.v:2448.6-2448.39" - wire \builder_csrbank11_clk_divider0_re - attribute \src "ls180.v:2451.12-2451.44" - wire width 8 \builder_csrbank11_clk_divider0_w - attribute \src "ls180.v:2450.6-2450.39" - wire \builder_csrbank11_clk_divider0_we - attribute \src "ls180.v:2445.12-2445.44" - wire width 8 \builder_csrbank11_clk_divider1_r - attribute \src "ls180.v:2444.6-2444.39" - wire \builder_csrbank11_clk_divider1_re - attribute \src "ls180.v:2447.12-2447.44" - wire width 8 \builder_csrbank11_clk_divider1_w - attribute \src "ls180.v:2446.6-2446.39" - wire \builder_csrbank11_clk_divider1_we - attribute \src "ls180.v:2421.12-2421.40" - wire width 8 \builder_csrbank11_control0_r - attribute \src "ls180.v:2420.6-2420.35" - wire \builder_csrbank11_control0_re - attribute \src "ls180.v:2423.12-2423.40" - wire width 8 \builder_csrbank11_control0_w - attribute \src "ls180.v:2422.6-2422.35" - wire \builder_csrbank11_control0_we - attribute \src "ls180.v:2417.12-2417.40" - wire width 8 \builder_csrbank11_control1_r - attribute \src "ls180.v:2416.6-2416.35" - wire \builder_csrbank11_control1_re - attribute \src "ls180.v:2419.12-2419.40" - wire width 8 \builder_csrbank11_control1_w - attribute \src "ls180.v:2418.6-2418.35" - wire \builder_csrbank11_control1_we - attribute \src "ls180.v:2437.6-2437.29" - wire \builder_csrbank11_cs0_r - attribute \src "ls180.v:2436.6-2436.30" - wire \builder_csrbank11_cs0_re - attribute \src "ls180.v:2439.6-2439.29" - wire \builder_csrbank11_cs0_w - attribute \src "ls180.v:2438.6-2438.30" - wire \builder_csrbank11_cs0_we - attribute \src "ls180.v:2441.6-2441.35" - wire \builder_csrbank11_loopback0_r - attribute \src "ls180.v:2440.6-2440.36" - wire \builder_csrbank11_loopback0_re - attribute \src "ls180.v:2443.6-2443.35" - wire \builder_csrbank11_loopback0_w - attribute \src "ls180.v:2442.6-2442.36" - wire \builder_csrbank11_loopback0_we - attribute \src "ls180.v:2433.12-2433.36" - wire width 8 \builder_csrbank11_miso_r - attribute \src "ls180.v:2432.6-2432.31" - wire \builder_csrbank11_miso_re - attribute \src "ls180.v:2435.12-2435.36" - wire width 8 \builder_csrbank11_miso_w - attribute \src "ls180.v:2434.6-2434.31" - wire \builder_csrbank11_miso_we - attribute \src "ls180.v:2429.12-2429.37" - wire width 8 \builder_csrbank11_mosi0_r - attribute \src "ls180.v:2428.6-2428.32" - wire \builder_csrbank11_mosi0_re - attribute \src "ls180.v:2431.12-2431.37" - wire width 8 \builder_csrbank11_mosi0_w - attribute \src "ls180.v:2430.6-2430.32" - wire \builder_csrbank11_mosi0_we - attribute \src "ls180.v:2452.6-2452.27" - wire \builder_csrbank11_sel - attribute \src "ls180.v:2425.6-2425.32" - wire \builder_csrbank11_status_r - attribute \src "ls180.v:2424.6-2424.33" - wire \builder_csrbank11_status_re - attribute \src "ls180.v:2427.6-2427.32" - wire \builder_csrbank11_status_w - attribute \src "ls180.v:2426.6-2426.33" - wire \builder_csrbank11_status_we - attribute \src "ls180.v:2490.6-2490.29" - wire \builder_csrbank12_en0_r - attribute \src "ls180.v:2489.6-2489.30" - wire \builder_csrbank12_en0_re - attribute \src "ls180.v:2492.6-2492.29" - wire \builder_csrbank12_en0_w - attribute \src "ls180.v:2491.6-2491.30" - wire \builder_csrbank12_en0_we - attribute \src "ls180.v:2514.6-2514.36" - wire \builder_csrbank12_ev_enable0_r - attribute \src "ls180.v:2513.6-2513.37" - wire \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:2516.6-2516.36" - wire \builder_csrbank12_ev_enable0_w - attribute \src "ls180.v:2515.6-2515.37" - wire \builder_csrbank12_ev_enable0_we - attribute \src "ls180.v:2470.12-2470.37" - wire width 8 \builder_csrbank12_load0_r - attribute \src "ls180.v:2469.6-2469.32" - wire \builder_csrbank12_load0_re - attribute \src "ls180.v:2472.12-2472.37" - wire width 8 \builder_csrbank12_load0_w - attribute \src "ls180.v:2471.6-2471.32" - wire \builder_csrbank12_load0_we - attribute \src "ls180.v:2466.12-2466.37" - wire width 8 \builder_csrbank12_load1_r - attribute \src "ls180.v:2465.6-2465.32" - wire \builder_csrbank12_load1_re - attribute \src "ls180.v:2468.12-2468.37" - wire width 8 \builder_csrbank12_load1_w - attribute \src "ls180.v:2467.6-2467.32" - wire \builder_csrbank12_load1_we - attribute \src "ls180.v:2462.12-2462.37" - wire width 8 \builder_csrbank12_load2_r - attribute \src "ls180.v:2461.6-2461.32" - wire \builder_csrbank12_load2_re - attribute \src "ls180.v:2464.12-2464.37" - wire width 8 \builder_csrbank12_load2_w - attribute \src "ls180.v:2463.6-2463.32" - wire \builder_csrbank12_load2_we - attribute \src "ls180.v:2458.12-2458.37" - wire width 8 \builder_csrbank12_load3_r - attribute \src "ls180.v:2457.6-2457.32" - wire \builder_csrbank12_load3_re - attribute \src "ls180.v:2460.12-2460.37" - wire width 8 \builder_csrbank12_load3_w - attribute \src "ls180.v:2459.6-2459.32" - wire \builder_csrbank12_load3_we - attribute \src "ls180.v:2486.12-2486.39" - wire width 8 \builder_csrbank12_reload0_r - attribute \src "ls180.v:2485.6-2485.34" - wire \builder_csrbank12_reload0_re - attribute \src "ls180.v:2488.12-2488.39" - wire width 8 \builder_csrbank12_reload0_w - attribute \src "ls180.v:2487.6-2487.34" - wire \builder_csrbank12_reload0_we - attribute \src "ls180.v:2482.12-2482.39" - wire width 8 \builder_csrbank12_reload1_r - attribute \src "ls180.v:2481.6-2481.34" - wire \builder_csrbank12_reload1_re - attribute \src "ls180.v:2484.12-2484.39" - wire width 8 \builder_csrbank12_reload1_w - attribute \src "ls180.v:2483.6-2483.34" - wire \builder_csrbank12_reload1_we - attribute \src "ls180.v:2478.12-2478.39" - wire width 8 \builder_csrbank12_reload2_r - attribute \src "ls180.v:2477.6-2477.34" - wire \builder_csrbank12_reload2_re - attribute \src "ls180.v:2480.12-2480.39" - wire width 8 \builder_csrbank12_reload2_w - attribute \src "ls180.v:2479.6-2479.34" - wire \builder_csrbank12_reload2_we - attribute \src "ls180.v:2474.12-2474.39" - wire width 8 \builder_csrbank12_reload3_r - attribute \src "ls180.v:2473.6-2473.34" - wire \builder_csrbank12_reload3_re - attribute \src "ls180.v:2476.12-2476.39" - wire width 8 \builder_csrbank12_reload3_w - attribute \src "ls180.v:2475.6-2475.34" - wire \builder_csrbank12_reload3_we - attribute \src "ls180.v:2517.6-2517.27" - wire \builder_csrbank12_sel - attribute \src "ls180.v:2494.6-2494.39" - wire \builder_csrbank12_update_value0_r - attribute \src "ls180.v:2493.6-2493.40" - wire \builder_csrbank12_update_value0_re - attribute \src "ls180.v:2496.6-2496.39" - wire \builder_csrbank12_update_value0_w - attribute \src "ls180.v:2495.6-2495.40" - wire \builder_csrbank12_update_value0_we - attribute \src "ls180.v:2510.12-2510.38" - wire width 8 \builder_csrbank12_value0_r - attribute \src "ls180.v:2509.6-2509.33" - wire \builder_csrbank12_value0_re - attribute \src "ls180.v:2512.12-2512.38" - wire width 8 \builder_csrbank12_value0_w - attribute \src "ls180.v:2511.6-2511.33" - wire \builder_csrbank12_value0_we - attribute \src "ls180.v:2506.12-2506.38" - wire width 8 \builder_csrbank12_value1_r - attribute \src "ls180.v:2505.6-2505.33" - wire \builder_csrbank12_value1_re - attribute \src "ls180.v:2508.12-2508.38" - wire width 8 \builder_csrbank12_value1_w - attribute \src "ls180.v:2507.6-2507.33" - wire \builder_csrbank12_value1_we - attribute \src "ls180.v:2502.12-2502.38" - wire width 8 \builder_csrbank12_value2_r - attribute \src "ls180.v:2501.6-2501.33" - wire \builder_csrbank12_value2_re - attribute \src "ls180.v:2504.12-2504.38" - wire width 8 \builder_csrbank12_value2_w - attribute \src "ls180.v:2503.6-2503.33" - wire \builder_csrbank12_value2_we - attribute \src "ls180.v:2498.12-2498.38" - wire width 8 \builder_csrbank12_value3_r - attribute \src "ls180.v:2497.6-2497.33" - wire \builder_csrbank12_value3_re - attribute \src "ls180.v:2500.12-2500.38" - wire width 8 \builder_csrbank12_value3_w - attribute \src "ls180.v:2499.6-2499.33" - wire \builder_csrbank12_value3_we - attribute \src "ls180.v:2531.12-2531.42" - wire width 2 \builder_csrbank13_ev_enable0_r - attribute \src "ls180.v:2530.6-2530.37" - wire \builder_csrbank13_ev_enable0_re - attribute \src "ls180.v:2533.12-2533.42" - wire width 2 \builder_csrbank13_ev_enable0_w - attribute \src "ls180.v:2532.6-2532.37" - wire \builder_csrbank13_ev_enable0_we - attribute \src "ls180.v:2527.6-2527.33" - wire \builder_csrbank13_rxempty_r - attribute \src "ls180.v:2526.6-2526.34" - wire \builder_csrbank13_rxempty_re - attribute \src "ls180.v:2529.6-2529.33" - wire \builder_csrbank13_rxempty_w - attribute \src "ls180.v:2528.6-2528.34" - wire \builder_csrbank13_rxempty_we - attribute \src "ls180.v:2539.6-2539.32" - wire \builder_csrbank13_rxfull_r - attribute \src "ls180.v:2538.6-2538.33" - wire \builder_csrbank13_rxfull_re - attribute \src "ls180.v:2541.6-2541.32" - wire \builder_csrbank13_rxfull_w - attribute \src "ls180.v:2540.6-2540.33" - wire \builder_csrbank13_rxfull_we - attribute \src "ls180.v:2542.6-2542.27" - wire \builder_csrbank13_sel - attribute \src "ls180.v:2535.6-2535.33" - wire \builder_csrbank13_txempty_r - attribute \src "ls180.v:2534.6-2534.34" - wire \builder_csrbank13_txempty_re - attribute \src "ls180.v:2537.6-2537.33" - wire \builder_csrbank13_txempty_w - attribute \src "ls180.v:2536.6-2536.34" - wire \builder_csrbank13_txempty_we - attribute \src "ls180.v:2523.6-2523.32" - wire \builder_csrbank13_txfull_r - attribute \src "ls180.v:2522.6-2522.33" - wire \builder_csrbank13_txfull_re - attribute \src "ls180.v:2525.6-2525.32" - wire \builder_csrbank13_txfull_w - attribute \src "ls180.v:2524.6-2524.33" - wire \builder_csrbank13_txfull_we - attribute \src "ls180.v:2563.6-2563.27" - wire \builder_csrbank14_sel - attribute \src "ls180.v:2560.12-2560.44" - wire width 8 \builder_csrbank14_tuning_word0_r - attribute \src "ls180.v:2559.6-2559.39" - wire \builder_csrbank14_tuning_word0_re - attribute \src "ls180.v:2562.12-2562.44" - wire width 8 \builder_csrbank14_tuning_word0_w - attribute \src "ls180.v:2561.6-2561.39" - wire \builder_csrbank14_tuning_word0_we - attribute \src "ls180.v:2556.12-2556.44" - wire width 8 \builder_csrbank14_tuning_word1_r - attribute \src "ls180.v:2555.6-2555.39" - wire \builder_csrbank14_tuning_word1_re - attribute \src "ls180.v:2558.12-2558.44" - wire width 8 \builder_csrbank14_tuning_word1_w - attribute \src "ls180.v:2557.6-2557.39" - wire \builder_csrbank14_tuning_word1_we - attribute \src "ls180.v:2552.12-2552.44" - wire width 8 \builder_csrbank14_tuning_word2_r - attribute \src "ls180.v:2551.6-2551.39" - wire \builder_csrbank14_tuning_word2_re - attribute \src "ls180.v:2554.12-2554.44" - wire width 8 \builder_csrbank14_tuning_word2_w - attribute \src "ls180.v:2553.6-2553.39" - wire \builder_csrbank14_tuning_word2_we - attribute \src "ls180.v:2548.12-2548.44" - wire width 8 \builder_csrbank14_tuning_word3_r - attribute \src "ls180.v:2547.6-2547.39" - wire \builder_csrbank14_tuning_word3_re - attribute \src "ls180.v:2550.12-2550.44" - wire width 8 \builder_csrbank14_tuning_word3_w - attribute \src "ls180.v:2549.6-2549.39" - wire \builder_csrbank14_tuning_word3_we - attribute \src "ls180.v:1935.12-1935.34" - wire width 8 \builder_csrbank1_in0_r - attribute \src "ls180.v:1934.6-1934.29" - wire \builder_csrbank1_in0_re - attribute \src "ls180.v:1937.12-1937.34" - wire width 8 \builder_csrbank1_in0_w - attribute \src "ls180.v:1936.6-1936.29" - wire \builder_csrbank1_in0_we - attribute \src "ls180.v:1931.12-1931.34" - wire width 8 \builder_csrbank1_in1_r - attribute \src "ls180.v:1930.6-1930.29" - wire \builder_csrbank1_in1_re - attribute \src "ls180.v:1933.12-1933.34" - wire width 8 \builder_csrbank1_in1_w - attribute \src "ls180.v:1932.6-1932.29" - wire \builder_csrbank1_in1_we - attribute \src "ls180.v:1927.12-1927.34" - wire width 8 \builder_csrbank1_oe0_r - attribute \src "ls180.v:1926.6-1926.29" - wire \builder_csrbank1_oe0_re - attribute \src "ls180.v:1929.12-1929.34" - wire width 8 \builder_csrbank1_oe0_w - attribute \src "ls180.v:1928.6-1928.29" - wire \builder_csrbank1_oe0_we - attribute \src "ls180.v:1923.12-1923.34" - wire width 8 \builder_csrbank1_oe1_r - attribute \src "ls180.v:1922.6-1922.29" - wire \builder_csrbank1_oe1_re - attribute \src "ls180.v:1925.12-1925.34" - wire width 8 \builder_csrbank1_oe1_w - attribute \src "ls180.v:1924.6-1924.29" - wire \builder_csrbank1_oe1_we - attribute \src "ls180.v:1943.12-1943.35" - wire width 8 \builder_csrbank1_out0_r - attribute \src "ls180.v:1942.6-1942.30" - wire \builder_csrbank1_out0_re - attribute \src "ls180.v:1945.12-1945.35" - wire width 8 \builder_csrbank1_out0_w - attribute \src "ls180.v:1944.6-1944.30" - wire \builder_csrbank1_out0_we - attribute \src "ls180.v:1939.12-1939.35" - wire width 8 \builder_csrbank1_out1_r - attribute \src "ls180.v:1938.6-1938.30" - wire \builder_csrbank1_out1_re - attribute \src "ls180.v:1941.12-1941.35" - wire width 8 \builder_csrbank1_out1_w - attribute \src "ls180.v:1940.6-1940.30" - wire \builder_csrbank1_out1_we - attribute \src "ls180.v:1946.6-1946.26" - wire \builder_csrbank1_sel - attribute \src "ls180.v:1956.6-1956.26" - wire \builder_csrbank2_r_r - attribute \src "ls180.v:1955.6-1955.27" - wire \builder_csrbank2_r_re - attribute \src "ls180.v:1958.6-1958.26" - wire \builder_csrbank2_r_w - attribute \src "ls180.v:1957.6-1957.27" - wire \builder_csrbank2_r_we - attribute \src "ls180.v:1959.6-1959.26" - wire \builder_csrbank2_sel - attribute \src "ls180.v:1952.12-1952.33" - wire width 3 \builder_csrbank2_w0_r - attribute \src "ls180.v:1951.6-1951.28" - wire \builder_csrbank2_w0_re - attribute \src "ls180.v:1954.12-1954.33" - wire width 3 \builder_csrbank2_w0_w - attribute \src "ls180.v:1953.6-1953.28" - wire \builder_csrbank2_w0_we - attribute \src "ls180.v:1965.6-1965.32" - wire \builder_csrbank3_enable0_r - attribute \src "ls180.v:1964.6-1964.33" - wire \builder_csrbank3_enable0_re - attribute \src "ls180.v:1967.6-1967.32" - wire \builder_csrbank3_enable0_w - attribute \src "ls180.v:1966.6-1966.33" - wire \builder_csrbank3_enable0_we - attribute \src "ls180.v:1997.12-1997.38" - wire width 8 \builder_csrbank3_period0_r - attribute \src "ls180.v:1996.6-1996.33" - wire \builder_csrbank3_period0_re - attribute \src "ls180.v:1999.12-1999.38" - wire width 8 \builder_csrbank3_period0_w - attribute \src "ls180.v:1998.6-1998.33" - wire \builder_csrbank3_period0_we - attribute \src "ls180.v:1993.12-1993.38" - wire width 8 \builder_csrbank3_period1_r - attribute \src "ls180.v:1992.6-1992.33" - wire \builder_csrbank3_period1_re - attribute \src "ls180.v:1995.12-1995.38" - wire width 8 \builder_csrbank3_period1_w - attribute \src "ls180.v:1994.6-1994.33" - wire \builder_csrbank3_period1_we - attribute \src "ls180.v:1989.12-1989.38" - wire width 8 \builder_csrbank3_period2_r - attribute \src "ls180.v:1988.6-1988.33" - wire \builder_csrbank3_period2_re - attribute \src "ls180.v:1991.12-1991.38" - wire width 8 \builder_csrbank3_period2_w - attribute \src "ls180.v:1990.6-1990.33" - wire \builder_csrbank3_period2_we - attribute \src "ls180.v:1985.12-1985.38" - wire width 8 \builder_csrbank3_period3_r - attribute \src "ls180.v:1984.6-1984.33" - wire \builder_csrbank3_period3_re - attribute \src "ls180.v:1987.12-1987.38" - wire width 8 \builder_csrbank3_period3_w - attribute \src "ls180.v:1986.6-1986.33" - wire \builder_csrbank3_period3_we - attribute \src "ls180.v:2000.6-2000.26" - wire \builder_csrbank3_sel - attribute \src "ls180.v:1981.12-1981.37" - wire width 8 \builder_csrbank3_width0_r - attribute \src "ls180.v:1980.6-1980.32" - wire \builder_csrbank3_width0_re - attribute \src "ls180.v:1983.12-1983.37" - wire width 8 \builder_csrbank3_width0_w - attribute \src "ls180.v:1982.6-1982.32" - wire \builder_csrbank3_width0_we - attribute \src "ls180.v:1977.12-1977.37" - wire width 8 \builder_csrbank3_width1_r - attribute \src "ls180.v:1976.6-1976.32" - wire \builder_csrbank3_width1_re - attribute \src "ls180.v:1979.12-1979.37" - wire width 8 \builder_csrbank3_width1_w - attribute \src "ls180.v:1978.6-1978.32" - wire \builder_csrbank3_width1_we - attribute \src "ls180.v:1973.12-1973.37" - wire width 8 \builder_csrbank3_width2_r - attribute \src "ls180.v:1972.6-1972.32" - wire \builder_csrbank3_width2_re - attribute \src "ls180.v:1975.12-1975.37" - wire width 8 \builder_csrbank3_width2_w - attribute \src "ls180.v:1974.6-1974.32" - wire \builder_csrbank3_width2_we - attribute \src "ls180.v:1969.12-1969.37" - wire width 8 \builder_csrbank3_width3_r - attribute \src "ls180.v:1968.6-1968.32" - wire \builder_csrbank3_width3_re - attribute \src "ls180.v:1971.12-1971.37" - wire width 8 \builder_csrbank3_width3_w - attribute \src "ls180.v:1970.6-1970.32" - wire \builder_csrbank3_width3_we - attribute \src "ls180.v:2006.6-2006.32" - wire \builder_csrbank4_enable0_r - attribute \src "ls180.v:2005.6-2005.33" - wire \builder_csrbank4_enable0_re - attribute \src "ls180.v:2008.6-2008.32" - wire \builder_csrbank4_enable0_w - attribute \src "ls180.v:2007.6-2007.33" - wire \builder_csrbank4_enable0_we - attribute \src "ls180.v:2038.12-2038.38" - wire width 8 \builder_csrbank4_period0_r - attribute \src "ls180.v:2037.6-2037.33" - wire \builder_csrbank4_period0_re - attribute \src "ls180.v:2040.12-2040.38" - wire width 8 \builder_csrbank4_period0_w - attribute \src "ls180.v:2039.6-2039.33" - wire \builder_csrbank4_period0_we - attribute \src "ls180.v:2034.12-2034.38" - wire width 8 \builder_csrbank4_period1_r - attribute \src "ls180.v:2033.6-2033.33" - wire \builder_csrbank4_period1_re - attribute \src "ls180.v:2036.12-2036.38" - wire width 8 \builder_csrbank4_period1_w - attribute \src "ls180.v:2035.6-2035.33" - wire \builder_csrbank4_period1_we - attribute \src "ls180.v:2030.12-2030.38" - wire width 8 \builder_csrbank4_period2_r - attribute \src "ls180.v:2029.6-2029.33" - wire \builder_csrbank4_period2_re - attribute \src "ls180.v:2032.12-2032.38" - wire width 8 \builder_csrbank4_period2_w - attribute \src "ls180.v:2031.6-2031.33" - wire \builder_csrbank4_period2_we - attribute \src "ls180.v:2026.12-2026.38" - wire width 8 \builder_csrbank4_period3_r - attribute \src "ls180.v:2025.6-2025.33" - wire \builder_csrbank4_period3_re - attribute \src "ls180.v:2028.12-2028.38" - wire width 8 \builder_csrbank4_period3_w - attribute \src "ls180.v:2027.6-2027.33" - wire \builder_csrbank4_period3_we - attribute \src "ls180.v:2041.6-2041.26" - wire \builder_csrbank4_sel - attribute \src "ls180.v:2022.12-2022.37" - wire width 8 \builder_csrbank4_width0_r - attribute \src "ls180.v:2021.6-2021.32" - wire \builder_csrbank4_width0_re - attribute \src "ls180.v:2024.12-2024.37" - wire width 8 \builder_csrbank4_width0_w - attribute \src "ls180.v:2023.6-2023.32" - wire \builder_csrbank4_width0_we - attribute \src "ls180.v:2018.12-2018.37" - wire width 8 \builder_csrbank4_width1_r - attribute \src "ls180.v:2017.6-2017.32" - wire \builder_csrbank4_width1_re - attribute \src "ls180.v:2020.12-2020.37" - wire width 8 \builder_csrbank4_width1_w - attribute \src "ls180.v:2019.6-2019.32" - wire \builder_csrbank4_width1_we - attribute \src "ls180.v:2014.12-2014.37" - wire width 8 \builder_csrbank4_width2_r - attribute \src "ls180.v:2013.6-2013.32" - wire \builder_csrbank4_width2_re - attribute \src "ls180.v:2016.12-2016.37" - wire width 8 \builder_csrbank4_width2_w - attribute \src "ls180.v:2015.6-2015.32" - wire \builder_csrbank4_width2_we - attribute \src "ls180.v:2010.12-2010.37" - wire width 8 \builder_csrbank4_width3_r - attribute \src "ls180.v:2009.6-2009.32" - wire \builder_csrbank4_width3_re - attribute \src "ls180.v:2012.12-2012.37" - wire width 8 \builder_csrbank4_width3_w - attribute \src "ls180.v:2011.6-2011.32" - wire \builder_csrbank4_width3_we - attribute \src "ls180.v:2075.12-2075.40" - wire width 8 \builder_csrbank5_dma_base0_r - attribute \src "ls180.v:2074.6-2074.35" - wire \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:2077.12-2077.40" - wire width 8 \builder_csrbank5_dma_base0_w - attribute \src "ls180.v:2076.6-2076.35" - wire \builder_csrbank5_dma_base0_we - attribute \src "ls180.v:2071.12-2071.40" - wire width 8 \builder_csrbank5_dma_base1_r - attribute \src "ls180.v:2070.6-2070.35" - wire \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:2073.12-2073.40" - wire width 8 \builder_csrbank5_dma_base1_w - attribute \src "ls180.v:2072.6-2072.35" - wire \builder_csrbank5_dma_base1_we - attribute \src "ls180.v:2067.12-2067.40" - wire width 8 \builder_csrbank5_dma_base2_r - attribute \src "ls180.v:2066.6-2066.35" - wire \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:2069.12-2069.40" - wire width 8 \builder_csrbank5_dma_base2_w - attribute \src "ls180.v:2068.6-2068.35" - wire \builder_csrbank5_dma_base2_we - attribute \src "ls180.v:2063.12-2063.40" - wire width 8 \builder_csrbank5_dma_base3_r - attribute \src "ls180.v:2062.6-2062.35" - wire \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:2065.12-2065.40" - wire width 8 \builder_csrbank5_dma_base3_w - attribute \src "ls180.v:2064.6-2064.35" - wire \builder_csrbank5_dma_base3_we - attribute \src "ls180.v:2059.12-2059.40" - wire width 8 \builder_csrbank5_dma_base4_r - attribute \src "ls180.v:2058.6-2058.35" - wire \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:2061.12-2061.40" - wire width 8 \builder_csrbank5_dma_base4_w - attribute \src "ls180.v:2060.6-2060.35" - wire \builder_csrbank5_dma_base4_we - attribute \src "ls180.v:2055.12-2055.40" - wire width 8 \builder_csrbank5_dma_base5_r - attribute \src "ls180.v:2054.6-2054.35" - wire \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:2057.12-2057.40" - wire width 8 \builder_csrbank5_dma_base5_w - attribute \src "ls180.v:2056.6-2056.35" - wire \builder_csrbank5_dma_base5_we - attribute \src "ls180.v:2051.12-2051.40" - wire width 8 \builder_csrbank5_dma_base6_r - attribute \src "ls180.v:2050.6-2050.35" - wire \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:2053.12-2053.40" - wire width 8 \builder_csrbank5_dma_base6_w - attribute \src "ls180.v:2052.6-2052.35" - wire \builder_csrbank5_dma_base6_we - attribute \src "ls180.v:2047.12-2047.40" - wire width 8 \builder_csrbank5_dma_base7_r - attribute \src "ls180.v:2046.6-2046.35" - wire \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:2049.12-2049.40" - wire width 8 \builder_csrbank5_dma_base7_w - attribute \src "ls180.v:2048.6-2048.35" - wire \builder_csrbank5_dma_base7_we - attribute \src "ls180.v:2099.6-2099.33" - wire \builder_csrbank5_dma_done_r - attribute \src "ls180.v:2098.6-2098.34" - wire \builder_csrbank5_dma_done_re - attribute \src "ls180.v:2101.6-2101.33" - wire \builder_csrbank5_dma_done_w - attribute \src "ls180.v:2100.6-2100.34" - wire \builder_csrbank5_dma_done_we - attribute \src "ls180.v:2095.6-2095.36" - wire \builder_csrbank5_dma_enable0_r - attribute \src "ls180.v:2094.6-2094.37" - wire \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:2097.6-2097.36" - wire \builder_csrbank5_dma_enable0_w - attribute \src "ls180.v:2096.6-2096.37" - wire \builder_csrbank5_dma_enable0_we - attribute \src "ls180.v:2091.12-2091.42" - wire width 8 \builder_csrbank5_dma_length0_r - attribute \src "ls180.v:2090.6-2090.37" - wire \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:2093.12-2093.42" - wire width 8 \builder_csrbank5_dma_length0_w - attribute \src "ls180.v:2092.6-2092.37" - wire \builder_csrbank5_dma_length0_we - attribute \src "ls180.v:2087.12-2087.42" - wire width 8 \builder_csrbank5_dma_length1_r - attribute \src "ls180.v:2086.6-2086.37" - wire \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:2089.12-2089.42" - wire width 8 \builder_csrbank5_dma_length1_w - attribute \src "ls180.v:2088.6-2088.37" - wire \builder_csrbank5_dma_length1_we - attribute \src "ls180.v:2083.12-2083.42" - wire width 8 \builder_csrbank5_dma_length2_r - attribute \src "ls180.v:2082.6-2082.37" - wire \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:2085.12-2085.42" - wire width 8 \builder_csrbank5_dma_length2_w - attribute \src "ls180.v:2084.6-2084.37" - wire \builder_csrbank5_dma_length2_we - attribute \src "ls180.v:2079.12-2079.42" - wire width 8 \builder_csrbank5_dma_length3_r - attribute \src "ls180.v:2078.6-2078.37" - wire \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:2081.12-2081.42" - wire width 8 \builder_csrbank5_dma_length3_w - attribute \src "ls180.v:2080.6-2080.37" - wire \builder_csrbank5_dma_length3_we - attribute \src "ls180.v:2103.6-2103.34" - wire \builder_csrbank5_dma_loop0_r - attribute \src "ls180.v:2102.6-2102.35" - wire \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:2105.6-2105.34" - wire \builder_csrbank5_dma_loop0_w - attribute \src "ls180.v:2104.6-2104.35" - wire \builder_csrbank5_dma_loop0_we - attribute \src "ls180.v:2106.6-2106.26" - wire \builder_csrbank5_sel - attribute \src "ls180.v:2236.12-2236.43" - wire width 8 \builder_csrbank6_block_count0_r - attribute \src "ls180.v:2235.6-2235.38" - wire \builder_csrbank6_block_count0_re - attribute \src "ls180.v:2238.12-2238.43" - wire width 8 \builder_csrbank6_block_count0_w - attribute \src "ls180.v:2237.6-2237.38" - wire \builder_csrbank6_block_count0_we - attribute \src "ls180.v:2232.12-2232.43" - wire width 8 \builder_csrbank6_block_count1_r - attribute \src "ls180.v:2231.6-2231.38" - wire \builder_csrbank6_block_count1_re - attribute \src "ls180.v:2234.12-2234.43" - wire width 8 \builder_csrbank6_block_count1_w - attribute \src "ls180.v:2233.6-2233.38" - wire \builder_csrbank6_block_count1_we - attribute \src "ls180.v:2228.12-2228.43" - wire width 8 \builder_csrbank6_block_count2_r - attribute \src "ls180.v:2227.6-2227.38" - wire \builder_csrbank6_block_count2_re - attribute \src "ls180.v:2230.12-2230.43" - wire width 8 \builder_csrbank6_block_count2_w - attribute \src "ls180.v:2229.6-2229.38" - wire \builder_csrbank6_block_count2_we - attribute \src "ls180.v:2224.12-2224.43" - wire width 8 \builder_csrbank6_block_count3_r - attribute \src "ls180.v:2223.6-2223.38" - wire \builder_csrbank6_block_count3_re - attribute \src "ls180.v:2226.12-2226.43" - wire width 8 \builder_csrbank6_block_count3_w - attribute \src "ls180.v:2225.6-2225.38" - wire \builder_csrbank6_block_count3_we - attribute \src "ls180.v:2220.12-2220.44" - wire width 8 \builder_csrbank6_block_length0_r - attribute \src "ls180.v:2219.6-2219.39" - wire \builder_csrbank6_block_length0_re - attribute \src "ls180.v:2222.12-2222.44" - wire width 8 \builder_csrbank6_block_length0_w - attribute \src "ls180.v:2221.6-2221.39" - wire \builder_csrbank6_block_length0_we - attribute \src "ls180.v:2216.12-2216.44" - wire width 2 \builder_csrbank6_block_length1_r - attribute \src "ls180.v:2215.6-2215.39" - wire \builder_csrbank6_block_length1_re - attribute \src "ls180.v:2218.12-2218.44" - wire width 2 \builder_csrbank6_block_length1_w - attribute \src "ls180.v:2217.6-2217.39" - wire \builder_csrbank6_block_length1_we - attribute \src "ls180.v:2124.12-2124.44" - wire width 8 \builder_csrbank6_cmd_argument0_r - attribute \src "ls180.v:2123.6-2123.39" - wire \builder_csrbank6_cmd_argument0_re - attribute \src "ls180.v:2126.12-2126.44" - wire width 8 \builder_csrbank6_cmd_argument0_w - attribute \src "ls180.v:2125.6-2125.39" - wire \builder_csrbank6_cmd_argument0_we - attribute \src "ls180.v:2120.12-2120.44" - wire width 8 \builder_csrbank6_cmd_argument1_r - attribute \src "ls180.v:2119.6-2119.39" - wire \builder_csrbank6_cmd_argument1_re - attribute \src "ls180.v:2122.12-2122.44" - wire width 8 \builder_csrbank6_cmd_argument1_w - attribute \src "ls180.v:2121.6-2121.39" - wire \builder_csrbank6_cmd_argument1_we - attribute \src "ls180.v:2116.12-2116.44" - wire width 8 \builder_csrbank6_cmd_argument2_r - attribute \src "ls180.v:2115.6-2115.39" - wire \builder_csrbank6_cmd_argument2_re - attribute \src "ls180.v:2118.12-2118.44" - wire width 8 \builder_csrbank6_cmd_argument2_w - attribute \src "ls180.v:2117.6-2117.39" - wire \builder_csrbank6_cmd_argument2_we - attribute \src "ls180.v:2112.12-2112.44" - wire width 8 \builder_csrbank6_cmd_argument3_r - attribute \src "ls180.v:2111.6-2111.39" - wire \builder_csrbank6_cmd_argument3_re - attribute \src "ls180.v:2114.12-2114.44" - wire width 8 \builder_csrbank6_cmd_argument3_w - attribute \src "ls180.v:2113.6-2113.39" - wire \builder_csrbank6_cmd_argument3_we - attribute \src "ls180.v:2140.12-2140.43" - wire width 8 \builder_csrbank6_cmd_command0_r - attribute \src "ls180.v:2139.6-2139.38" - wire \builder_csrbank6_cmd_command0_re - attribute \src "ls180.v:2142.12-2142.43" - wire width 8 \builder_csrbank6_cmd_command0_w - attribute \src "ls180.v:2141.6-2141.38" - wire \builder_csrbank6_cmd_command0_we - attribute \src "ls180.v:2136.12-2136.43" - wire width 8 \builder_csrbank6_cmd_command1_r - attribute \src "ls180.v:2135.6-2135.38" - wire \builder_csrbank6_cmd_command1_re - attribute \src "ls180.v:2138.12-2138.43" - wire width 8 \builder_csrbank6_cmd_command1_w - attribute \src "ls180.v:2137.6-2137.38" - wire \builder_csrbank6_cmd_command1_we - attribute \src "ls180.v:2132.12-2132.43" - wire width 8 \builder_csrbank6_cmd_command2_r - attribute \src "ls180.v:2131.6-2131.38" - wire \builder_csrbank6_cmd_command2_re - attribute \src "ls180.v:2134.12-2134.43" - wire width 8 \builder_csrbank6_cmd_command2_w - attribute \src "ls180.v:2133.6-2133.38" - wire \builder_csrbank6_cmd_command2_we - attribute \src "ls180.v:2128.12-2128.43" - wire width 8 \builder_csrbank6_cmd_command3_r - attribute \src "ls180.v:2127.6-2127.38" - wire \builder_csrbank6_cmd_command3_re - attribute \src "ls180.v:2130.12-2130.43" - wire width 8 \builder_csrbank6_cmd_command3_w - attribute \src "ls180.v:2129.6-2129.38" - wire \builder_csrbank6_cmd_command3_we - attribute \src "ls180.v:2208.12-2208.40" - wire width 4 \builder_csrbank6_cmd_event_r - attribute \src "ls180.v:2207.6-2207.35" - wire \builder_csrbank6_cmd_event_re - attribute \src "ls180.v:2210.12-2210.40" - wire width 4 \builder_csrbank6_cmd_event_w - attribute \src "ls180.v:2209.6-2209.35" - wire \builder_csrbank6_cmd_event_we - attribute \src "ls180.v:2204.12-2204.44" - wire width 8 \builder_csrbank6_cmd_response0_r - attribute \src "ls180.v:2203.6-2203.39" - wire \builder_csrbank6_cmd_response0_re - attribute \src "ls180.v:2206.12-2206.44" - wire width 8 \builder_csrbank6_cmd_response0_w - attribute \src "ls180.v:2205.6-2205.39" - wire \builder_csrbank6_cmd_response0_we - attribute \src "ls180.v:2164.12-2164.45" - wire width 8 \builder_csrbank6_cmd_response10_r - attribute \src "ls180.v:2163.6-2163.40" - wire \builder_csrbank6_cmd_response10_re - attribute \src "ls180.v:2166.12-2166.45" - wire width 8 \builder_csrbank6_cmd_response10_w - attribute \src "ls180.v:2165.6-2165.40" - wire \builder_csrbank6_cmd_response10_we - attribute \src "ls180.v:2160.12-2160.45" - wire width 8 \builder_csrbank6_cmd_response11_r - attribute \src "ls180.v:2159.6-2159.40" - wire \builder_csrbank6_cmd_response11_re - attribute \src "ls180.v:2162.12-2162.45" - wire width 8 \builder_csrbank6_cmd_response11_w - attribute \src "ls180.v:2161.6-2161.40" - wire \builder_csrbank6_cmd_response11_we - attribute \src "ls180.v:2156.12-2156.45" - wire width 8 \builder_csrbank6_cmd_response12_r - attribute \src "ls180.v:2155.6-2155.40" - wire \builder_csrbank6_cmd_response12_re - attribute \src "ls180.v:2158.12-2158.45" - wire width 8 \builder_csrbank6_cmd_response12_w - attribute \src "ls180.v:2157.6-2157.40" - wire \builder_csrbank6_cmd_response12_we - attribute \src "ls180.v:2152.12-2152.45" - wire width 8 \builder_csrbank6_cmd_response13_r - attribute \src "ls180.v:2151.6-2151.40" - wire \builder_csrbank6_cmd_response13_re - attribute \src "ls180.v:2154.12-2154.45" - wire width 8 \builder_csrbank6_cmd_response13_w - attribute \src "ls180.v:2153.6-2153.40" - wire \builder_csrbank6_cmd_response13_we - attribute \src "ls180.v:2148.12-2148.45" - wire width 8 \builder_csrbank6_cmd_response14_r - attribute \src "ls180.v:2147.6-2147.40" - wire \builder_csrbank6_cmd_response14_re - attribute \src "ls180.v:2150.12-2150.45" - wire width 8 \builder_csrbank6_cmd_response14_w - attribute \src "ls180.v:2149.6-2149.40" - wire \builder_csrbank6_cmd_response14_we - attribute \src "ls180.v:2144.12-2144.45" - wire width 8 \builder_csrbank6_cmd_response15_r - attribute \src "ls180.v:2143.6-2143.40" - wire \builder_csrbank6_cmd_response15_re - attribute \src "ls180.v:2146.12-2146.45" - wire width 8 \builder_csrbank6_cmd_response15_w - attribute \src "ls180.v:2145.6-2145.40" - wire \builder_csrbank6_cmd_response15_we - attribute \src "ls180.v:2200.12-2200.44" - wire width 8 \builder_csrbank6_cmd_response1_r - attribute \src "ls180.v:2199.6-2199.39" - wire \builder_csrbank6_cmd_response1_re - attribute \src "ls180.v:2202.12-2202.44" - wire width 8 \builder_csrbank6_cmd_response1_w - attribute \src "ls180.v:2201.6-2201.39" - wire \builder_csrbank6_cmd_response1_we - attribute \src "ls180.v:2196.12-2196.44" - wire width 8 \builder_csrbank6_cmd_response2_r - attribute \src "ls180.v:2195.6-2195.39" - wire \builder_csrbank6_cmd_response2_re - attribute \src "ls180.v:2198.12-2198.44" - wire width 8 \builder_csrbank6_cmd_response2_w - attribute \src "ls180.v:2197.6-2197.39" - wire \builder_csrbank6_cmd_response2_we - attribute \src "ls180.v:2192.12-2192.44" - wire width 8 \builder_csrbank6_cmd_response3_r - attribute \src "ls180.v:2191.6-2191.39" - wire \builder_csrbank6_cmd_response3_re - attribute \src "ls180.v:2194.12-2194.44" - wire width 8 \builder_csrbank6_cmd_response3_w - attribute \src "ls180.v:2193.6-2193.39" - wire \builder_csrbank6_cmd_response3_we - attribute \src "ls180.v:2188.12-2188.44" - wire width 8 \builder_csrbank6_cmd_response4_r - attribute \src "ls180.v:2187.6-2187.39" - wire \builder_csrbank6_cmd_response4_re - attribute \src "ls180.v:2190.12-2190.44" - wire width 8 \builder_csrbank6_cmd_response4_w - attribute \src "ls180.v:2189.6-2189.39" - wire \builder_csrbank6_cmd_response4_we - attribute \src "ls180.v:2184.12-2184.44" - wire width 8 \builder_csrbank6_cmd_response5_r - attribute \src "ls180.v:2183.6-2183.39" - wire \builder_csrbank6_cmd_response5_re - attribute \src "ls180.v:2186.12-2186.44" - wire width 8 \builder_csrbank6_cmd_response5_w - attribute \src "ls180.v:2185.6-2185.39" - wire \builder_csrbank6_cmd_response5_we - attribute \src "ls180.v:2180.12-2180.44" - wire width 8 \builder_csrbank6_cmd_response6_r - attribute \src "ls180.v:2179.6-2179.39" - wire \builder_csrbank6_cmd_response6_re - attribute \src "ls180.v:2182.12-2182.44" - wire width 8 \builder_csrbank6_cmd_response6_w - attribute \src "ls180.v:2181.6-2181.39" - wire \builder_csrbank6_cmd_response6_we - attribute \src "ls180.v:2176.12-2176.44" - wire width 8 \builder_csrbank6_cmd_response7_r - attribute \src "ls180.v:2175.6-2175.39" - wire \builder_csrbank6_cmd_response7_re - attribute \src "ls180.v:2178.12-2178.44" - wire width 8 \builder_csrbank6_cmd_response7_w - attribute \src "ls180.v:2177.6-2177.39" - wire \builder_csrbank6_cmd_response7_we - attribute \src "ls180.v:2172.12-2172.44" - wire width 8 \builder_csrbank6_cmd_response8_r - attribute \src "ls180.v:2171.6-2171.39" - wire \builder_csrbank6_cmd_response8_re - attribute \src "ls180.v:2174.12-2174.44" - wire width 8 \builder_csrbank6_cmd_response8_w - attribute \src "ls180.v:2173.6-2173.39" - wire \builder_csrbank6_cmd_response8_we - attribute \src "ls180.v:2168.12-2168.44" - wire width 8 \builder_csrbank6_cmd_response9_r - attribute \src "ls180.v:2167.6-2167.39" - wire \builder_csrbank6_cmd_response9_re - attribute \src "ls180.v:2170.12-2170.44" - wire width 8 \builder_csrbank6_cmd_response9_w - attribute \src "ls180.v:2169.6-2169.39" - wire \builder_csrbank6_cmd_response9_we - attribute \src "ls180.v:2212.12-2212.41" - wire width 4 \builder_csrbank6_data_event_r - attribute \src "ls180.v:2211.6-2211.36" - wire \builder_csrbank6_data_event_re - attribute \src "ls180.v:2214.12-2214.41" - wire width 4 \builder_csrbank6_data_event_w - attribute \src "ls180.v:2213.6-2213.36" - wire \builder_csrbank6_data_event_we - attribute \src "ls180.v:2239.6-2239.26" - wire \builder_csrbank6_sel - attribute \src "ls180.v:2273.12-2273.40" - wire width 8 \builder_csrbank7_dma_base0_r - attribute \src "ls180.v:2272.6-2272.35" - wire \builder_csrbank7_dma_base0_re - attribute \src "ls180.v:2275.12-2275.40" - wire width 8 \builder_csrbank7_dma_base0_w - attribute \src "ls180.v:2274.6-2274.35" - wire \builder_csrbank7_dma_base0_we - attribute \src "ls180.v:2269.12-2269.40" - wire width 8 \builder_csrbank7_dma_base1_r - attribute \src "ls180.v:2268.6-2268.35" - wire \builder_csrbank7_dma_base1_re - attribute \src "ls180.v:2271.12-2271.40" - wire width 8 \builder_csrbank7_dma_base1_w - attribute \src "ls180.v:2270.6-2270.35" - wire \builder_csrbank7_dma_base1_we - attribute \src "ls180.v:2265.12-2265.40" - wire width 8 \builder_csrbank7_dma_base2_r - attribute \src "ls180.v:2264.6-2264.35" - wire \builder_csrbank7_dma_base2_re - attribute \src "ls180.v:2267.12-2267.40" - wire width 8 \builder_csrbank7_dma_base2_w - attribute \src "ls180.v:2266.6-2266.35" - wire \builder_csrbank7_dma_base2_we - attribute \src "ls180.v:2261.12-2261.40" - wire width 8 \builder_csrbank7_dma_base3_r - attribute \src "ls180.v:2260.6-2260.35" - wire \builder_csrbank7_dma_base3_re - attribute \src "ls180.v:2263.12-2263.40" - wire width 8 \builder_csrbank7_dma_base3_w - attribute \src "ls180.v:2262.6-2262.35" - wire \builder_csrbank7_dma_base3_we - attribute \src "ls180.v:2257.12-2257.40" - wire width 8 \builder_csrbank7_dma_base4_r - attribute \src "ls180.v:2256.6-2256.35" - wire \builder_csrbank7_dma_base4_re - attribute \src "ls180.v:2259.12-2259.40" - wire width 8 \builder_csrbank7_dma_base4_w - attribute \src "ls180.v:2258.6-2258.35" - wire \builder_csrbank7_dma_base4_we - attribute \src "ls180.v:2253.12-2253.40" - wire width 8 \builder_csrbank7_dma_base5_r - attribute \src "ls180.v:2252.6-2252.35" - wire \builder_csrbank7_dma_base5_re - attribute \src "ls180.v:2255.12-2255.40" - wire width 8 \builder_csrbank7_dma_base5_w - attribute \src "ls180.v:2254.6-2254.35" - wire \builder_csrbank7_dma_base5_we - attribute \src "ls180.v:2249.12-2249.40" - wire width 8 \builder_csrbank7_dma_base6_r - attribute \src "ls180.v:2248.6-2248.35" - wire \builder_csrbank7_dma_base6_re - attribute \src "ls180.v:2251.12-2251.40" - wire width 8 \builder_csrbank7_dma_base6_w - attribute \src "ls180.v:2250.6-2250.35" - wire \builder_csrbank7_dma_base6_we - attribute \src "ls180.v:2245.12-2245.40" - wire width 8 \builder_csrbank7_dma_base7_r - attribute \src "ls180.v:2244.6-2244.35" - wire \builder_csrbank7_dma_base7_re - attribute \src "ls180.v:2247.12-2247.40" - wire width 8 \builder_csrbank7_dma_base7_w - attribute \src "ls180.v:2246.6-2246.35" - wire \builder_csrbank7_dma_base7_we - attribute \src "ls180.v:2297.6-2297.33" - wire \builder_csrbank7_dma_done_r - attribute \src "ls180.v:2296.6-2296.34" - wire \builder_csrbank7_dma_done_re - attribute \src "ls180.v:2299.6-2299.33" - wire \builder_csrbank7_dma_done_w - attribute \src "ls180.v:2298.6-2298.34" - wire \builder_csrbank7_dma_done_we - attribute \src "ls180.v:2293.6-2293.36" - wire \builder_csrbank7_dma_enable0_r - attribute \src "ls180.v:2292.6-2292.37" - wire \builder_csrbank7_dma_enable0_re - attribute \src "ls180.v:2295.6-2295.36" - wire \builder_csrbank7_dma_enable0_w - attribute \src "ls180.v:2294.6-2294.37" - wire \builder_csrbank7_dma_enable0_we - attribute \src "ls180.v:2289.12-2289.42" - wire width 8 \builder_csrbank7_dma_length0_r - attribute \src "ls180.v:2288.6-2288.37" - wire \builder_csrbank7_dma_length0_re - attribute \src "ls180.v:2291.12-2291.42" - wire width 8 \builder_csrbank7_dma_length0_w - attribute \src "ls180.v:2290.6-2290.37" - wire \builder_csrbank7_dma_length0_we - attribute \src "ls180.v:2285.12-2285.42" - wire width 8 \builder_csrbank7_dma_length1_r - attribute \src "ls180.v:2284.6-2284.37" - wire \builder_csrbank7_dma_length1_re - attribute \src "ls180.v:2287.12-2287.42" - wire width 8 \builder_csrbank7_dma_length1_w - attribute \src "ls180.v:2286.6-2286.37" - wire \builder_csrbank7_dma_length1_we - attribute \src "ls180.v:2281.12-2281.42" - wire width 8 \builder_csrbank7_dma_length2_r - attribute \src "ls180.v:2280.6-2280.37" - wire \builder_csrbank7_dma_length2_re - attribute \src "ls180.v:2283.12-2283.42" - wire width 8 \builder_csrbank7_dma_length2_w - attribute \src "ls180.v:2282.6-2282.37" - wire \builder_csrbank7_dma_length2_we - attribute \src "ls180.v:2277.12-2277.42" - wire width 8 \builder_csrbank7_dma_length3_r - attribute \src "ls180.v:2276.6-2276.37" - wire \builder_csrbank7_dma_length3_re - attribute \src "ls180.v:2279.12-2279.42" - wire width 8 \builder_csrbank7_dma_length3_w - attribute \src "ls180.v:2278.6-2278.37" - wire \builder_csrbank7_dma_length3_we - attribute \src "ls180.v:2301.6-2301.34" - wire \builder_csrbank7_dma_loop0_r - attribute \src "ls180.v:2300.6-2300.35" - wire \builder_csrbank7_dma_loop0_re - attribute \src "ls180.v:2303.6-2303.34" - wire \builder_csrbank7_dma_loop0_w - attribute \src "ls180.v:2302.6-2302.35" - wire \builder_csrbank7_dma_loop0_we - attribute \src "ls180.v:2317.12-2317.42" - wire width 8 \builder_csrbank7_dma_offset0_r - attribute \src "ls180.v:2316.6-2316.37" - wire \builder_csrbank7_dma_offset0_re - attribute \src "ls180.v:2319.12-2319.42" - wire width 8 \builder_csrbank7_dma_offset0_w - attribute \src "ls180.v:2318.6-2318.37" - wire \builder_csrbank7_dma_offset0_we - attribute \src "ls180.v:2313.12-2313.42" - wire width 8 \builder_csrbank7_dma_offset1_r - attribute \src "ls180.v:2312.6-2312.37" - wire \builder_csrbank7_dma_offset1_re - attribute \src "ls180.v:2315.12-2315.42" - wire width 8 \builder_csrbank7_dma_offset1_w - attribute \src "ls180.v:2314.6-2314.37" - wire \builder_csrbank7_dma_offset1_we - attribute \src "ls180.v:2309.12-2309.42" - wire width 8 \builder_csrbank7_dma_offset2_r - attribute \src "ls180.v:2308.6-2308.37" - wire \builder_csrbank7_dma_offset2_re - attribute \src "ls180.v:2311.12-2311.42" - wire width 8 \builder_csrbank7_dma_offset2_w - attribute \src "ls180.v:2310.6-2310.37" - wire \builder_csrbank7_dma_offset2_we - attribute \src "ls180.v:2305.12-2305.42" - wire width 8 \builder_csrbank7_dma_offset3_r - attribute \src "ls180.v:2304.6-2304.37" - wire \builder_csrbank7_dma_offset3_re - attribute \src "ls180.v:2307.12-2307.42" - wire width 8 \builder_csrbank7_dma_offset3_w - attribute \src "ls180.v:2306.6-2306.37" - wire \builder_csrbank7_dma_offset3_we - attribute \src "ls180.v:2320.6-2320.26" - wire \builder_csrbank7_sel - attribute \src "ls180.v:2326.6-2326.36" - wire \builder_csrbank8_card_detect_r - attribute \src "ls180.v:2325.6-2325.37" - wire \builder_csrbank8_card_detect_re - attribute \src "ls180.v:2328.6-2328.36" - wire \builder_csrbank8_card_detect_w - attribute \src "ls180.v:2327.6-2327.37" - wire \builder_csrbank8_card_detect_we - attribute \src "ls180.v:2334.12-2334.47" - wire width 8 \builder_csrbank8_clocker_divider0_r - attribute \src "ls180.v:2333.6-2333.42" - wire \builder_csrbank8_clocker_divider0_re - attribute \src "ls180.v:2336.12-2336.47" - wire width 8 \builder_csrbank8_clocker_divider0_w - attribute \src "ls180.v:2335.6-2335.42" - wire \builder_csrbank8_clocker_divider0_we - attribute \src "ls180.v:2330.6-2330.41" - wire \builder_csrbank8_clocker_divider1_r - attribute \src "ls180.v:2329.6-2329.42" - wire \builder_csrbank8_clocker_divider1_re - attribute \src "ls180.v:2332.6-2332.41" - wire \builder_csrbank8_clocker_divider1_w - attribute \src "ls180.v:2331.6-2331.42" - wire \builder_csrbank8_clocker_divider1_we - attribute \src "ls180.v:2337.6-2337.26" - wire \builder_csrbank8_sel - attribute \src "ls180.v:2343.12-2343.44" - wire width 4 \builder_csrbank9_dfii_control0_r - attribute \src "ls180.v:2342.6-2342.39" - wire \builder_csrbank9_dfii_control0_re - attribute \src "ls180.v:2345.12-2345.44" - wire width 4 \builder_csrbank9_dfii_control0_w - attribute \src "ls180.v:2344.6-2344.39" - wire \builder_csrbank9_dfii_control0_we - attribute \src "ls180.v:2355.12-2355.48" - wire width 8 \builder_csrbank9_dfii_pi0_address0_r - attribute \src "ls180.v:2354.6-2354.43" - wire \builder_csrbank9_dfii_pi0_address0_re - attribute \src "ls180.v:2357.12-2357.48" - wire width 8 \builder_csrbank9_dfii_pi0_address0_w - attribute \src "ls180.v:2356.6-2356.43" - wire \builder_csrbank9_dfii_pi0_address0_we - attribute \src "ls180.v:2351.12-2351.48" - wire width 5 \builder_csrbank9_dfii_pi0_address1_r - attribute \src "ls180.v:2350.6-2350.43" - wire \builder_csrbank9_dfii_pi0_address1_re - attribute \src "ls180.v:2353.12-2353.48" - wire width 5 \builder_csrbank9_dfii_pi0_address1_w - attribute \src "ls180.v:2352.6-2352.43" - wire \builder_csrbank9_dfii_pi0_address1_we - attribute \src "ls180.v:2359.12-2359.49" - wire width 2 \builder_csrbank9_dfii_pi0_baddress0_r - attribute \src "ls180.v:2358.6-2358.44" - wire \builder_csrbank9_dfii_pi0_baddress0_re - attribute \src "ls180.v:2361.12-2361.49" - wire width 2 \builder_csrbank9_dfii_pi0_baddress0_w - attribute \src "ls180.v:2360.6-2360.44" - wire \builder_csrbank9_dfii_pi0_baddress0_we - attribute \src "ls180.v:2347.12-2347.48" - wire width 6 \builder_csrbank9_dfii_pi0_command0_r - attribute \src "ls180.v:2346.6-2346.43" - wire \builder_csrbank9_dfii_pi0_command0_re - attribute \src "ls180.v:2349.12-2349.48" - wire width 6 \builder_csrbank9_dfii_pi0_command0_w - attribute \src "ls180.v:2348.6-2348.43" - wire \builder_csrbank9_dfii_pi0_command0_we - attribute \src "ls180.v:2375.12-2375.47" - wire width 8 \builder_csrbank9_dfii_pi0_rddata0_r - attribute \src "ls180.v:2374.6-2374.42" - wire \builder_csrbank9_dfii_pi0_rddata0_re - attribute \src "ls180.v:2377.12-2377.47" - wire width 8 \builder_csrbank9_dfii_pi0_rddata0_w - attribute \src "ls180.v:2376.6-2376.42" - wire \builder_csrbank9_dfii_pi0_rddata0_we - attribute \src "ls180.v:2371.12-2371.47" - wire width 8 \builder_csrbank9_dfii_pi0_rddata1_r - attribute \src "ls180.v:2370.6-2370.42" - wire \builder_csrbank9_dfii_pi0_rddata1_re - attribute \src "ls180.v:2373.12-2373.47" - wire width 8 \builder_csrbank9_dfii_pi0_rddata1_w - attribute \src "ls180.v:2372.6-2372.42" - wire \builder_csrbank9_dfii_pi0_rddata1_we - attribute \src "ls180.v:2367.12-2367.47" - wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_r - attribute \src "ls180.v:2366.6-2366.42" - wire \builder_csrbank9_dfii_pi0_wrdata0_re - attribute \src "ls180.v:2369.12-2369.47" - wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_w - attribute \src "ls180.v:2368.6-2368.42" - wire \builder_csrbank9_dfii_pi0_wrdata0_we - attribute \src "ls180.v:2363.12-2363.47" - wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_r - attribute \src "ls180.v:2362.6-2362.42" - wire \builder_csrbank9_dfii_pi0_wrdata1_re - attribute \src "ls180.v:2365.12-2365.47" - wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_w - attribute \src "ls180.v:2364.6-2364.42" - wire \builder_csrbank9_dfii_pi0_wrdata1_we - attribute \src "ls180.v:2378.6-2378.26" - wire \builder_csrbank9_sel - attribute \src "ls180.v:1875.6-1875.18" - wire \builder_done - attribute \src "ls180.v:1873.5-1873.18" - wire \builder_error - attribute \src "ls180.v:1870.11-1870.24" - wire width 3 \builder_grant - attribute \src "ls180.v:1877.13-1877.44" - wire width 14 \builder_interface0_bank_bus_adr - attribute \src "ls180.v:1880.11-1880.44" - wire width 8 \builder_interface0_bank_bus_dat_r - attribute \src "ls180.v:1879.12-1879.45" - wire width 8 \builder_interface0_bank_bus_dat_w - attribute \src "ls180.v:1878.6-1878.36" - wire \builder_interface0_bank_bus_we - attribute \src "ls180.v:2379.13-2379.45" - wire width 14 \builder_interface10_bank_bus_adr - attribute \src "ls180.v:2382.11-2382.45" - wire width 8 \builder_interface10_bank_bus_dat_r - attribute \src "ls180.v:2381.12-2381.46" - wire width 8 \builder_interface10_bank_bus_dat_w - attribute \src "ls180.v:2380.6-2380.37" - wire \builder_interface10_bank_bus_we - attribute \src "ls180.v:2412.13-2412.45" - wire width 14 \builder_interface11_bank_bus_adr - attribute \src "ls180.v:2415.11-2415.45" - wire width 8 \builder_interface11_bank_bus_dat_r - attribute \src "ls180.v:2414.12-2414.46" - wire width 8 \builder_interface11_bank_bus_dat_w - attribute \src "ls180.v:2413.6-2413.37" - wire \builder_interface11_bank_bus_we - attribute \src "ls180.v:2453.13-2453.45" - wire width 14 \builder_interface12_bank_bus_adr - attribute \src "ls180.v:2456.11-2456.45" - wire width 8 \builder_interface12_bank_bus_dat_r - attribute \src "ls180.v:2455.12-2455.46" - wire width 8 \builder_interface12_bank_bus_dat_w - attribute \src "ls180.v:2454.6-2454.37" - wire \builder_interface12_bank_bus_we - attribute \src "ls180.v:2518.13-2518.45" - wire width 14 \builder_interface13_bank_bus_adr - attribute \src "ls180.v:2521.11-2521.45" - wire width 8 \builder_interface13_bank_bus_dat_r - attribute \src "ls180.v:2520.12-2520.46" - wire width 8 \builder_interface13_bank_bus_dat_w - attribute \src "ls180.v:2519.6-2519.37" - wire \builder_interface13_bank_bus_we - attribute \src "ls180.v:2543.13-2543.45" - wire width 14 \builder_interface14_bank_bus_adr - attribute \src "ls180.v:2546.11-2546.45" - wire width 8 \builder_interface14_bank_bus_dat_r - attribute \src "ls180.v:2545.12-2545.46" - wire width 8 \builder_interface14_bank_bus_dat_w - attribute \src "ls180.v:2544.6-2544.37" - wire \builder_interface14_bank_bus_we - attribute \src "ls180.v:1918.13-1918.44" - wire width 14 \builder_interface1_bank_bus_adr - attribute \src "ls180.v:1921.11-1921.44" - wire width 8 \builder_interface1_bank_bus_dat_r - attribute \src "ls180.v:1920.12-1920.45" - wire width 8 \builder_interface1_bank_bus_dat_w - attribute \src "ls180.v:1919.6-1919.36" - wire \builder_interface1_bank_bus_we - attribute \src "ls180.v:1947.13-1947.44" - wire width 14 \builder_interface2_bank_bus_adr - attribute \src "ls180.v:1950.11-1950.44" - wire width 8 \builder_interface2_bank_bus_dat_r - attribute \src "ls180.v:1949.12-1949.45" - wire width 8 \builder_interface2_bank_bus_dat_w - attribute \src "ls180.v:1948.6-1948.36" - wire \builder_interface2_bank_bus_we - attribute \src "ls180.v:1960.13-1960.44" - wire width 14 \builder_interface3_bank_bus_adr - attribute \src "ls180.v:1963.11-1963.44" - wire width 8 \builder_interface3_bank_bus_dat_r - attribute \src "ls180.v:1962.12-1962.45" - wire width 8 \builder_interface3_bank_bus_dat_w - attribute \src "ls180.v:1961.6-1961.36" - wire \builder_interface3_bank_bus_we - attribute \src "ls180.v:2001.13-2001.44" - wire width 14 \builder_interface4_bank_bus_adr - attribute \src "ls180.v:2004.11-2004.44" - wire width 8 \builder_interface4_bank_bus_dat_r - attribute \src "ls180.v:2003.12-2003.45" - wire width 8 \builder_interface4_bank_bus_dat_w - attribute \src "ls180.v:2002.6-2002.36" - wire \builder_interface4_bank_bus_we - attribute \src "ls180.v:2042.13-2042.44" - wire width 14 \builder_interface5_bank_bus_adr - attribute \src "ls180.v:2045.11-2045.44" - wire width 8 \builder_interface5_bank_bus_dat_r - attribute \src "ls180.v:2044.12-2044.45" - wire width 8 \builder_interface5_bank_bus_dat_w - attribute \src "ls180.v:2043.6-2043.36" - wire \builder_interface5_bank_bus_we - attribute \src "ls180.v:2107.13-2107.44" - wire width 14 \builder_interface6_bank_bus_adr - attribute \src "ls180.v:2110.11-2110.44" - wire width 8 \builder_interface6_bank_bus_dat_r - attribute \src "ls180.v:2109.12-2109.45" - wire width 8 \builder_interface6_bank_bus_dat_w - attribute \src "ls180.v:2108.6-2108.36" - wire \builder_interface6_bank_bus_we - attribute \src "ls180.v:2240.13-2240.44" - wire width 14 \builder_interface7_bank_bus_adr - attribute \src "ls180.v:2243.11-2243.44" - wire width 8 \builder_interface7_bank_bus_dat_r - attribute \src "ls180.v:2242.12-2242.45" - wire width 8 \builder_interface7_bank_bus_dat_w - attribute \src "ls180.v:2241.6-2241.36" - wire \builder_interface7_bank_bus_we - attribute \src "ls180.v:2321.13-2321.44" - wire width 14 \builder_interface8_bank_bus_adr - attribute \src "ls180.v:2324.11-2324.44" - wire width 8 \builder_interface8_bank_bus_dat_r - attribute \src "ls180.v:2323.12-2323.45" - wire width 8 \builder_interface8_bank_bus_dat_w - attribute \src "ls180.v:2322.6-2322.36" - wire \builder_interface8_bank_bus_we - attribute \src "ls180.v:2338.13-2338.44" - wire width 14 \builder_interface9_bank_bus_adr - attribute \src "ls180.v:2341.11-2341.44" - wire width 8 \builder_interface9_bank_bus_dat_r - attribute \src "ls180.v:2340.12-2340.45" - wire width 8 \builder_interface9_bank_bus_dat_w - attribute \src "ls180.v:2339.6-2339.36" - wire \builder_interface9_bank_bus_we - attribute \src "ls180.v:1843.12-1843.35" - wire width 14 \builder_libresocsim_adr - attribute \src "ls180.v:2572.12-2572.47" - wire width 14 \builder_libresocsim_adr_next_value1 - attribute \src "ls180.v:2573.5-2573.43" - wire \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:1846.12-1846.37" - wire width 8 \builder_libresocsim_dat_r - attribute \src "ls180.v:1845.11-1845.36" - wire width 8 \builder_libresocsim_dat_w - attribute \src "ls180.v:2570.11-2570.48" - wire width 8 \builder_libresocsim_dat_w_next_value0 - attribute \src "ls180.v:2571.5-2571.45" - wire \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:1844.5-1844.27" - wire \builder_libresocsim_we - attribute \src "ls180.v:2574.5-2574.39" - wire \builder_libresocsim_we_next_value2 - attribute \src "ls180.v:2575.5-2575.42" - wire \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:1853.5-1853.37" - wire \builder_libresocsim_wishbone_ack - attribute \src "ls180.v:1847.13-1847.45" - wire width 30 \builder_libresocsim_wishbone_adr - attribute \src "ls180.v:1856.12-1856.44" - wire width 2 \builder_libresocsim_wishbone_bte - attribute \src "ls180.v:1855.12-1855.44" - wire width 3 \builder_libresocsim_wishbone_cti - attribute \src "ls180.v:1851.6-1851.38" - wire \builder_libresocsim_wishbone_cyc - attribute \src "ls180.v:1849.12-1849.46" - wire width 32 \builder_libresocsim_wishbone_dat_r - attribute \src "ls180.v:1848.13-1848.47" - wire width 32 \builder_libresocsim_wishbone_dat_w - attribute \src "ls180.v:1857.5-1857.37" - wire \builder_libresocsim_wishbone_err - attribute \src "ls180.v:1850.12-1850.44" - wire width 4 \builder_libresocsim_wishbone_sel - attribute \src "ls180.v:1852.6-1852.38" - wire \builder_libresocsim_wishbone_stb - attribute \src "ls180.v:1854.6-1854.37" - wire \builder_libresocsim_wishbone_we - attribute \src "ls180.v:1746.5-1746.20" - wire \builder_locked0 - attribute \src "ls180.v:1747.5-1747.20" - wire \builder_locked1 - attribute \src "ls180.v:1748.5-1748.20" - wire \builder_locked2 - attribute \src "ls180.v:1749.5-1749.20" - wire \builder_locked3 - attribute \src "ls180.v:1733.11-1733.41" - wire width 3 \builder_multiplexer_next_state - attribute \src "ls180.v:1732.11-1732.36" - wire width 3 \builder_multiplexer_state - attribute \no_retiming "true" - attribute \src "ls180.v:2679.32-2679.59" - wire \builder_multiregimpl0_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2680.32-2680.59" - wire \builder_multiregimpl0_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2699.32-2699.60" - wire \builder_multiregimpl10_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2700.32-2700.60" - wire \builder_multiregimpl10_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2701.32-2701.60" - wire \builder_multiregimpl11_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2702.32-2702.60" - wire \builder_multiregimpl11_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2703.32-2703.60" - wire \builder_multiregimpl12_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2704.32-2704.60" - wire \builder_multiregimpl12_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2705.32-2705.60" - wire \builder_multiregimpl13_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2706.32-2706.60" - wire \builder_multiregimpl13_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2707.32-2707.60" - wire \builder_multiregimpl14_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2708.32-2708.60" - wire \builder_multiregimpl14_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2709.32-2709.60" - wire \builder_multiregimpl15_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2710.32-2710.60" - wire \builder_multiregimpl15_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2711.32-2711.60" - wire \builder_multiregimpl16_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2712.32-2712.60" - wire \builder_multiregimpl16_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2681.32-2681.59" - wire \builder_multiregimpl1_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2682.32-2682.59" - wire \builder_multiregimpl1_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2683.32-2683.59" - wire \builder_multiregimpl2_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2684.32-2684.59" - wire \builder_multiregimpl2_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2685.32-2685.59" - wire \builder_multiregimpl3_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2686.32-2686.59" - wire \builder_multiregimpl3_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2687.32-2687.59" - wire \builder_multiregimpl4_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2688.32-2688.59" - wire \builder_multiregimpl4_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2689.32-2689.59" - wire \builder_multiregimpl5_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2690.32-2690.59" - wire \builder_multiregimpl5_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2691.32-2691.59" - wire \builder_multiregimpl6_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2692.32-2692.59" - wire \builder_multiregimpl6_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2693.32-2693.59" - wire \builder_multiregimpl7_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2694.32-2694.59" - wire \builder_multiregimpl7_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2695.32-2695.59" - wire \builder_multiregimpl8_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2696.32-2696.59" - wire \builder_multiregimpl8_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2697.32-2697.59" - wire \builder_multiregimpl9_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2698.32-2698.59" - wire \builder_multiregimpl9_regs1 - attribute \src "ls180.v:1751.5-1751.36" - wire \builder_new_master_rdata_valid0 - attribute \src "ls180.v:1752.5-1752.36" - wire \builder_new_master_rdata_valid1 - attribute \src "ls180.v:1753.5-1753.36" - wire \builder_new_master_rdata_valid2 - attribute \src "ls180.v:1754.5-1754.36" - wire \builder_new_master_rdata_valid3 - attribute \src "ls180.v:1750.5-1750.35" - wire \builder_new_master_wdata_ready - attribute \src "ls180.v:2569.11-2569.29" - wire width 2 \builder_next_state - attribute \src "ls180.v:1723.11-1723.39" - wire width 2 \builder_refresher_next_state - attribute \src "ls180.v:1722.11-1722.34" - wire width 2 \builder_refresher_state - attribute \src "ls180.v:1869.12-1869.27" - wire width 5 \builder_request - attribute \src "ls180.v:1736.6-1736.28" - wire \builder_roundrobin0_ce - attribute \src "ls180.v:1735.6-1735.31" - wire \builder_roundrobin0_grant - attribute \src "ls180.v:1734.6-1734.33" - wire \builder_roundrobin0_request - attribute \src "ls180.v:1739.6-1739.28" - wire \builder_roundrobin1_ce - attribute \src "ls180.v:1738.6-1738.31" - wire \builder_roundrobin1_grant - attribute \src "ls180.v:1737.6-1737.33" - wire \builder_roundrobin1_request - attribute \src "ls180.v:1742.6-1742.28" - wire \builder_roundrobin2_ce - attribute \src "ls180.v:1741.6-1741.31" - wire \builder_roundrobin2_grant - attribute \src "ls180.v:1740.6-1740.33" - wire \builder_roundrobin2_request - attribute \src "ls180.v:1745.6-1745.28" - wire \builder_roundrobin3_ce - attribute \src "ls180.v:1744.6-1744.31" - wire \builder_roundrobin3_grant - attribute \src "ls180.v:1743.6-1743.33" - wire \builder_roundrobin3_request - attribute \src "ls180.v:1828.11-1828.44" - wire width 2 \builder_sdblock2memdma_next_state - attribute \src "ls180.v:1827.11-1827.39" - wire width 2 \builder_sdblock2memdma_state - attribute \src "ls180.v:1796.5-1796.50" - wire \builder_sdcore_crcupstreaminserter_next_state - attribute \src "ls180.v:1795.5-1795.45" - wire \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:1808.11-1808.40" - wire width 3 \builder_sdcore_fsm_next_state - attribute \src "ls180.v:1807.11-1807.35" - wire width 3 \builder_sdcore_fsm_state - attribute \src "ls180.v:1832.5-1832.42" - wire \builder_sdmem2blockdma_fsm_next_state - attribute \src "ls180.v:1831.5-1831.37" - wire \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:1836.11-1836.58" - wire width 2 \builder_sdmem2blockdma_resetinserter_next_state - attribute \src "ls180.v:1835.11-1835.53" - wire width 2 \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:1784.11-1784.39" - wire width 3 \builder_sdphy_fsm_next_state - attribute \src "ls180.v:1783.11-1783.34" - wire width 3 \builder_sdphy_fsm_state - attribute \src "ls180.v:1772.11-1772.45" - wire width 3 \builder_sdphy_sdphycmdr_next_state - attribute \src "ls180.v:1771.11-1771.40" - wire width 3 \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:1768.11-1768.45" - wire width 2 \builder_sdphy_sdphycmdw_next_state - attribute \src "ls180.v:1767.11-1767.40" - wire width 2 \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:1780.5-1780.39" - wire \builder_sdphy_sdphycrcr_next_state - attribute \src "ls180.v:1779.5-1779.34" - wire \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:1788.11-1788.46" - wire width 3 \builder_sdphy_sdphydatar_next_state - attribute \src "ls180.v:1787.11-1787.41" - wire width 3 \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:1764.5-1764.39" - wire \builder_sdphy_sdphyinit_next_state - attribute \src "ls180.v:1763.5-1763.34" - wire \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:1864.5-1864.23" - wire \builder_shared_ack - attribute \src "ls180.v:1858.13-1858.31" - wire width 30 \builder_shared_adr - attribute \src "ls180.v:1867.12-1867.30" - wire width 2 \builder_shared_bte - attribute \src "ls180.v:1866.12-1866.30" - wire width 3 \builder_shared_cti - attribute \src "ls180.v:1862.6-1862.24" - wire \builder_shared_cyc - attribute \src "ls180.v:1860.12-1860.32" - wire width 32 \builder_shared_dat_r - attribute \src "ls180.v:1859.13-1859.33" - wire width 32 \builder_shared_dat_w - attribute \src "ls180.v:1868.6-1868.24" - wire \builder_shared_err - attribute \src "ls180.v:1861.12-1861.30" - wire width 4 \builder_shared_sel - attribute \src "ls180.v:1863.6-1863.24" - wire \builder_shared_stb - attribute \src "ls180.v:1865.6-1865.23" - wire \builder_shared_we - attribute \src "ls180.v:1871.11-1871.28" - wire width 5 \builder_slave_sel - attribute \src "ls180.v:1872.11-1872.30" - wire width 5 \builder_slave_sel_r - attribute \src "ls180.v:1760.11-1760.40" - wire width 2 \builder_spimaster0_next_state - attribute \src "ls180.v:1759.11-1759.35" - wire width 2 \builder_spimaster0_state - attribute \src "ls180.v:1840.11-1840.40" - wire width 2 \builder_spimaster1_next_state - attribute \src "ls180.v:1839.11-1839.35" - wire width 2 \builder_spimaster1_state - attribute \src "ls180.v:2568.11-2568.24" - wire width 2 \builder_state - attribute \src "ls180.v:2621.5-2621.32" - wire \builder_sync_f_array_muxed0 - attribute \src "ls180.v:2622.5-2622.32" - wire \builder_sync_f_array_muxed1 - attribute \src "ls180.v:2614.11-2614.40" - wire width 2 \builder_sync_rhs_array_muxed0 - attribute \src "ls180.v:2615.12-2615.41" - wire width 13 \builder_sync_rhs_array_muxed1 - attribute \src "ls180.v:2616.5-2616.34" - wire \builder_sync_rhs_array_muxed2 - attribute \src "ls180.v:2617.5-2617.34" - wire \builder_sync_rhs_array_muxed3 - attribute \src "ls180.v:2618.5-2618.34" - wire \builder_sync_rhs_array_muxed4 - attribute \src "ls180.v:2619.5-2619.34" - wire \builder_sync_rhs_array_muxed5 - attribute \src "ls180.v:2620.5-2620.34" - wire \builder_sync_rhs_array_muxed6 - attribute \src "ls180.v:1874.6-1874.18" - wire \builder_wait - attribute \src "ls180.v:30.19-30.23" - wire width 3 input 26 \eint - attribute \src "ls180.v:23.20-23.26" - wire width 16 input 19 \gpio_i - attribute \src "ls180.v:24.21-24.27" - wire width 16 output 20 \gpio_o - attribute \src "ls180.v:25.21-25.28" - wire width 16 output 21 \gpio_oe - attribute \src "ls180.v:38.14-38.21" - wire output 34 \i2c_scl - attribute \src "ls180.v:39.13-39.22" - wire input 35 \i2c_sda_i - attribute \src "ls180.v:40.14-40.23" - wire output 36 \i2c_sda_o - attribute \src "ls180.v:41.14-41.24" - wire output 37 \i2c_sda_oe - attribute \src "ls180.v:32.13-32.21" - wire input 28 \jtag_tck - attribute \src "ls180.v:33.13-33.21" - wire input 29 \jtag_tdi - attribute \src "ls180.v:34.14-34.22" - wire output 30 \jtag_tdo - attribute \src "ls180.v:31.13-31.21" - wire input 27 \jtag_tms - attribute \src "ls180.v:1680.13-1680.37" - wire width 16 \libresocsim_clk_divider0 - attribute \src "ls180.v:1702.12-1702.36" - wire width 16 \libresocsim_clk_divider1 - attribute \src "ls180.v:1697.5-1697.27" - wire \libresocsim_clk_enable - attribute \src "ls180.v:1704.6-1704.26" - wire \libresocsim_clk_fall - attribute \src "ls180.v:1703.6-1703.26" - wire \libresocsim_clk_rise - attribute \src "ls180.v:1684.5-1684.27" - wire \libresocsim_control_re - attribute \src "ls180.v:1683.12-1683.39" - wire width 16 \libresocsim_control_storage - attribute \src "ls180.v:1699.11-1699.28" - wire width 3 \libresocsim_count - attribute \src "ls180.v:1841.11-1841.50" - wire width 3 \libresocsim_count_spimaster1_next_value - attribute \src "ls180.v:1842.5-1842.47" - wire \libresocsim_count_spimaster1_next_value_ce - attribute \src "ls180.v:1678.6-1678.20" - wire \libresocsim_cs - attribute \src "ls180.v:1698.5-1698.26" - wire \libresocsim_cs_enable - attribute \src "ls180.v:1694.5-1694.22" - wire \libresocsim_cs_re - attribute \src "ls180.v:1693.5-1693.27" - wire \libresocsim_cs_storage - attribute \src "ls180.v:1674.5-1674.22" - wire \libresocsim_done0 - attribute \src "ls180.v:1685.6-1685.23" - wire \libresocsim_done1 - attribute \src "ls180.v:1675.5-1675.20" - wire \libresocsim_irq - attribute \src "ls180.v:1673.12-1673.31" - wire width 8 \libresocsim_length0 - attribute \src "ls180.v:1682.12-1682.31" - wire width 8 \libresocsim_length1 - attribute \src "ls180.v:1679.6-1679.26" - wire \libresocsim_loopback - attribute \src "ls180.v:1696.5-1696.28" - wire \libresocsim_loopback_re - attribute \src "ls180.v:1695.5-1695.33" - wire \libresocsim_loopback_storage - attribute \src "ls180.v:1677.11-1677.27" - wire width 8 \libresocsim_miso - attribute \src "ls180.v:1707.11-1707.32" - wire width 8 \libresocsim_miso_data - attribute \src "ls180.v:1701.5-1701.27" - wire \libresocsim_miso_latch - attribute \src "ls180.v:1690.12-1690.35" - wire width 8 \libresocsim_miso_status - attribute \src "ls180.v:1691.6-1691.25" - wire \libresocsim_miso_we - attribute \src "ls180.v:1676.12-1676.28" - wire width 8 \libresocsim_mosi - attribute \src "ls180.v:1705.11-1705.32" - wire width 8 \libresocsim_mosi_data - attribute \src "ls180.v:1700.5-1700.27" - wire \libresocsim_mosi_latch - attribute \src "ls180.v:1689.5-1689.24" - wire \libresocsim_mosi_re - attribute \src "ls180.v:1706.11-1706.31" - wire width 3 \libresocsim_mosi_sel - attribute \src "ls180.v:1688.11-1688.35" - wire width 8 \libresocsim_mosi_storage - attribute \src "ls180.v:1709.5-1709.19" - wire \libresocsim_re - attribute \src "ls180.v:1692.6-1692.21" - wire \libresocsim_sel - attribute \src "ls180.v:1672.6-1672.24" - wire \libresocsim_start0 - attribute \src "ls180.v:1681.5-1681.23" - wire \libresocsim_start1 - attribute \src "ls180.v:1686.6-1686.31" - wire \libresocsim_status_status - attribute \src "ls180.v:1687.6-1687.27" - wire \libresocsim_status_we - attribute \src "ls180.v:1708.12-1708.31" - wire width 16 \libresocsim_storage - attribute \src "ls180.v:814.6-814.18" - wire \main_ack_cmd - attribute \src "ls180.v:816.6-816.20" - wire \main_ack_rdata - attribute \src "ls180.v:815.6-815.20" - wire \main_ack_wdata - attribute \src "ls180.v:812.5-812.22" - wire \main_cmd_consumed - attribute \src "ls180.v:809.5-809.27" - wire \main_converter_counter - attribute \src "ls180.v:1757.5-1757.48" - wire \main_converter_counter_converter_next_value - attribute \src "ls180.v:1758.5-1758.51" - wire \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:811.12-811.32" - wire width 32 \main_converter_dat_r - attribute \src "ls180.v:810.6-810.26" - wire \main_converter_reset - attribute \src "ls180.v:808.5-808.24" - wire \main_converter_skip - attribute \src "ls180.v:238.6-238.23" - wire \main_dfi_p0_act_n - attribute \src "ls180.v:229.13-229.32" - wire width 13 \main_dfi_p0_address - attribute \src "ls180.v:230.12-230.28" - wire width 2 \main_dfi_p0_bank - attribute \src "ls180.v:231.6-231.23" - wire \main_dfi_p0_cas_n - attribute \src "ls180.v:235.6-235.21" - wire \main_dfi_p0_cke - attribute \src "ls180.v:232.6-232.22" - wire \main_dfi_p0_cs_n - attribute \src "ls180.v:236.6-236.21" - wire \main_dfi_p0_odt - attribute \src "ls180.v:233.6-233.23" - wire \main_dfi_p0_ras_n - attribute \src "ls180.v:243.12-243.30" - wire width 16 \main_dfi_p0_rddata - attribute \src "ls180.v:242.6-242.27" - wire \main_dfi_p0_rddata_en - attribute \src "ls180.v:244.5-244.29" - wire \main_dfi_p0_rddata_valid - attribute \src "ls180.v:237.6-237.25" - wire \main_dfi_p0_reset_n - attribute \src "ls180.v:234.6-234.22" - wire \main_dfi_p0_we_n - attribute \src "ls180.v:239.13-239.31" - wire width 16 \main_dfi_p0_wrdata - attribute \src "ls180.v:240.6-240.27" - wire \main_dfi_p0_wrdata_en - attribute \src "ls180.v:241.12-241.35" - wire width 2 \main_dfi_p0_wrdata_mask - attribute \src "ls180.v:1005.12-1005.22" - wire width 36 \main_dummy - attribute \src "ls180.v:960.5-960.20" - wire \main_gpio_oe_re - attribute \src "ls180.v:959.12-959.32" - wire width 16 \main_gpio_oe_storage - attribute \src "ls180.v:964.5-964.21" - wire \main_gpio_out_re - attribute \src "ls180.v:963.12-963.33" - wire width 16 \main_gpio_out_storage - attribute \src "ls180.v:965.13-965.29" - wire width 16 \main_gpio_pads_i - attribute \src "ls180.v:966.13-966.29" - wire width 16 \main_gpio_pads_o - attribute \src "ls180.v:967.13-967.30" - wire width 16 \main_gpio_pads_oe - attribute \src "ls180.v:961.12-961.28" - wire width 16 \main_gpio_status - attribute \src "ls180.v:962.6-962.18" - wire \main_gpio_we - attribute \src "ls180.v:1027.6-1027.17" - wire \main_i2c_oe - attribute \src "ls180.v:1030.5-1030.16" - wire \main_i2c_re - attribute \src "ls180.v:1026.6-1026.18" - wire \main_i2c_scl - attribute \src "ls180.v:1028.6-1028.19" - wire \main_i2c_sda0 - attribute \src "ls180.v:1031.6-1031.19" - wire \main_i2c_sda1 - attribute \src "ls180.v:1032.6-1032.21" - wire \main_i2c_status - attribute \src "ls180.v:1029.11-1029.27" - wire width 3 \main_i2c_storage - attribute \src "ls180.v:1033.6-1033.17" - wire \main_i2c_we - attribute \src "ls180.v:228.5-228.17" - wire \main_int_rst - attribute \src "ls180.v:1493.6-1493.29" - wire \main_interface0_bus_ack - attribute \src "ls180.v:1487.13-1487.36" - wire width 32 \main_interface0_bus_adr - attribute \src "ls180.v:1496.11-1496.34" - wire width 2 \main_interface0_bus_bte - attribute \src "ls180.v:1495.11-1495.34" - wire width 3 \main_interface0_bus_cti - attribute \src "ls180.v:1491.6-1491.29" - wire \main_interface0_bus_cyc - attribute \src "ls180.v:1489.13-1489.38" - wire width 32 \main_interface0_bus_dat_r - attribute \src "ls180.v:1488.13-1488.38" - wire width 32 \main_interface0_bus_dat_w - attribute \src "ls180.v:1497.6-1497.29" - wire \main_interface0_bus_err - attribute \src "ls180.v:1490.12-1490.35" - wire width 4 \main_interface0_bus_sel - attribute \src "ls180.v:1492.6-1492.29" - wire \main_interface0_bus_stb - attribute \src "ls180.v:1494.6-1494.28" - wire \main_interface0_bus_we - attribute \src "ls180.v:1584.6-1584.29" - wire \main_interface1_bus_ack - attribute \src "ls180.v:1578.12-1578.35" - wire width 32 \main_interface1_bus_adr - attribute \src "ls180.v:1587.11-1587.34" - wire width 2 \main_interface1_bus_bte - attribute \src "ls180.v:1586.11-1586.34" - wire width 3 \main_interface1_bus_cti - attribute \src "ls180.v:1582.5-1582.28" - wire \main_interface1_bus_cyc - attribute \src "ls180.v:1580.13-1580.38" - wire width 32 \main_interface1_bus_dat_r - attribute \src "ls180.v:1579.12-1579.37" - wire width 32 \main_interface1_bus_dat_w - attribute \src "ls180.v:1588.6-1588.29" - wire \main_interface1_bus_err - attribute \src "ls180.v:1581.11-1581.34" - wire width 4 \main_interface1_bus_sel - attribute \src "ls180.v:1583.5-1583.28" - wire \main_interface1_bus_stb - attribute \src "ls180.v:1585.5-1585.27" - wire \main_interface1_bus_we - attribute \src "ls180.v:194.12-194.32" - wire width 7 \main_libresocsim_adr - attribute \src "ls180.v:62.6-62.32" - wire \main_libresocsim_bus_error - attribute \src "ls180.v:63.12-63.39" - wire width 32 \main_libresocsim_bus_errors - attribute \src "ls180.v:59.13-59.47" - wire width 32 \main_libresocsim_bus_errors_status - attribute \src "ls180.v:60.6-60.36" - wire \main_libresocsim_bus_errors_we - attribute \src "ls180.v:150.5-150.40" - wire \main_libresocsim_converter0_counter - attribute \src "ls180.v:1712.5-1712.62" - wire \main_libresocsim_converter0_counter_converter0_next_value - attribute \src "ls180.v:1713.5-1713.65" - wire \main_libresocsim_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:152.12-152.45" - wire width 64 \main_libresocsim_converter0_dat_r - attribute \src "ls180.v:151.6-151.39" - wire \main_libresocsim_converter0_reset - attribute \src "ls180.v:149.5-149.37" - wire \main_libresocsim_converter0_skip - attribute \src "ls180.v:165.5-165.40" - wire \main_libresocsim_converter1_counter - attribute \src "ls180.v:1716.5-1716.62" - wire \main_libresocsim_converter1_counter_converter1_next_value - attribute \src "ls180.v:1717.5-1717.65" - wire \main_libresocsim_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:167.12-167.45" - wire width 64 \main_libresocsim_converter1_dat_r - attribute \src "ls180.v:166.6-166.39" - wire \main_libresocsim_converter1_reset - attribute \src "ls180.v:164.5-164.37" - wire \main_libresocsim_converter1_skip - attribute \src "ls180.v:180.5-180.40" - wire \main_libresocsim_converter2_counter - attribute \src "ls180.v:1720.5-1720.62" - wire \main_libresocsim_converter2_counter_converter2_next_value - attribute \src "ls180.v:1721.5-1721.65" - wire \main_libresocsim_converter2_counter_converter2_next_value_ce - attribute \src "ls180.v:182.12-182.45" - wire width 64 \main_libresocsim_converter2_dat_r - attribute \src "ls180.v:181.6-181.39" - wire \main_libresocsim_converter2_reset - attribute \src "ls180.v:179.5-179.37" - wire \main_libresocsim_converter2_skip - attribute \src "ls180.v:195.13-195.35" - wire width 32 \main_libresocsim_dat_r - attribute \src "ls180.v:197.13-197.35" - wire width 32 \main_libresocsim_dat_w - attribute \src "ls180.v:203.5-203.27" - wire \main_libresocsim_en_re - attribute \src "ls180.v:202.5-202.32" - wire \main_libresocsim_en_storage - attribute \src "ls180.v:219.6-219.45" - wire \main_libresocsim_eventmanager_pending_r - attribute \src "ls180.v:218.6-218.46" - wire \main_libresocsim_eventmanager_pending_re - attribute \src "ls180.v:221.6-221.45" - wire \main_libresocsim_eventmanager_pending_w - attribute \src "ls180.v:220.6-220.46" - wire \main_libresocsim_eventmanager_pending_we - attribute \src "ls180.v:223.5-223.37" - wire \main_libresocsim_eventmanager_re - attribute \src "ls180.v:215.6-215.44" - wire \main_libresocsim_eventmanager_status_r - attribute \src "ls180.v:214.6-214.45" - wire \main_libresocsim_eventmanager_status_re - attribute \src "ls180.v:217.6-217.44" - wire \main_libresocsim_eventmanager_status_w - attribute \src "ls180.v:216.6-216.45" - wire \main_libresocsim_eventmanager_status_we - attribute \src "ls180.v:222.5-222.42" - wire \main_libresocsim_eventmanager_storage - attribute \src "ls180.v:144.6-144.57" - wire \main_libresocsim_interface0_converted_interface_ack - attribute \src "ls180.v:138.12-138.63" - wire width 30 \main_libresocsim_interface0_converted_interface_adr - attribute \src "ls180.v:147.11-147.62" - wire width 2 \main_libresocsim_interface0_converted_interface_bte - attribute \src "ls180.v:146.11-146.62" - wire width 3 \main_libresocsim_interface0_converted_interface_cti - attribute \src "ls180.v:142.5-142.56" - wire \main_libresocsim_interface0_converted_interface_cyc - attribute \src "ls180.v:140.13-140.66" - wire width 32 \main_libresocsim_interface0_converted_interface_dat_r - attribute \src "ls180.v:139.12-139.65" - wire width 32 \main_libresocsim_interface0_converted_interface_dat_w - attribute \src "ls180.v:148.6-148.57" - wire \main_libresocsim_interface0_converted_interface_err - attribute \src "ls180.v:141.11-141.62" - wire width 4 \main_libresocsim_interface0_converted_interface_sel - attribute \src "ls180.v:143.5-143.56" - wire \main_libresocsim_interface0_converted_interface_stb - attribute \src "ls180.v:145.5-145.55" - wire \main_libresocsim_interface0_converted_interface_we - attribute \src "ls180.v:159.6-159.57" - wire \main_libresocsim_interface1_converted_interface_ack - attribute \src "ls180.v:153.12-153.63" - wire width 30 \main_libresocsim_interface1_converted_interface_adr - attribute \src "ls180.v:162.11-162.62" - wire width 2 \main_libresocsim_interface1_converted_interface_bte - attribute \src "ls180.v:161.11-161.62" - wire width 3 \main_libresocsim_interface1_converted_interface_cti - attribute \src "ls180.v:157.5-157.56" - wire \main_libresocsim_interface1_converted_interface_cyc - attribute \src "ls180.v:155.13-155.66" - wire width 32 \main_libresocsim_interface1_converted_interface_dat_r - attribute \src "ls180.v:154.12-154.65" - wire width 32 \main_libresocsim_interface1_converted_interface_dat_w - attribute \src "ls180.v:163.6-163.57" - wire \main_libresocsim_interface1_converted_interface_err - attribute \src "ls180.v:156.11-156.62" - wire width 4 \main_libresocsim_interface1_converted_interface_sel - attribute \src "ls180.v:158.5-158.56" - wire \main_libresocsim_interface1_converted_interface_stb - attribute \src "ls180.v:160.5-160.55" - wire \main_libresocsim_interface1_converted_interface_we - attribute \src "ls180.v:174.6-174.57" - wire \main_libresocsim_interface2_converted_interface_ack - attribute \src "ls180.v:168.12-168.63" - wire width 30 \main_libresocsim_interface2_converted_interface_adr - attribute \src "ls180.v:177.11-177.62" - wire width 2 \main_libresocsim_interface2_converted_interface_bte - attribute \src "ls180.v:176.11-176.62" - wire width 3 \main_libresocsim_interface2_converted_interface_cti - attribute \src "ls180.v:172.5-172.56" - wire \main_libresocsim_interface2_converted_interface_cyc - attribute \src "ls180.v:170.13-170.66" - wire width 32 \main_libresocsim_interface2_converted_interface_dat_r - attribute \src "ls180.v:169.12-169.65" - wire width 32 \main_libresocsim_interface2_converted_interface_dat_w - attribute \src "ls180.v:178.6-178.57" - wire \main_libresocsim_interface2_converted_interface_err - attribute \src "ls180.v:171.11-171.62" - wire width 4 \main_libresocsim_interface2_converted_interface_sel - attribute \src "ls180.v:173.5-173.56" - wire \main_libresocsim_interface2_converted_interface_stb - attribute \src "ls180.v:175.5-175.55" - wire \main_libresocsim_interface2_converted_interface_we - attribute \src "ls180.v:208.6-208.26" - wire \main_libresocsim_irq - attribute \src "ls180.v:123.6-123.32" - wire \main_libresocsim_libresoc0 - attribute \src "ls180.v:124.6-124.32" - wire \main_libresocsim_libresoc1 - attribute \src "ls180.v:125.13-125.39" - wire width 64 \main_libresocsim_libresoc2 - attribute \src "ls180.v:127.12-127.45" - wire width 3 \main_libresocsim_libresoc_clk_sel - attribute \src "ls180.v:130.13-130.65" - wire width 16 \main_libresocsim_libresoc_constraintmanager0_gpio0_i - attribute \src "ls180.v:131.13-131.65" - wire width 16 \main_libresocsim_libresoc_constraintmanager0_gpio0_o - attribute \src "ls180.v:132.13-132.66" - wire width 16 \main_libresocsim_libresoc_constraintmanager0_gpio0_oe - attribute \src "ls180.v:129.6-129.59" - wire \main_libresocsim_libresoc_constraintmanager0_uart0_rx - attribute \src "ls180.v:128.5-128.58" - wire \main_libresocsim_libresoc_constraintmanager0_uart0_tx - attribute \src "ls180.v:135.13-135.65" - wire width 16 \main_libresocsim_libresoc_constraintmanager1_gpio0_i - attribute \src "ls180.v:136.13-136.65" - wire width 16 \main_libresocsim_libresoc_constraintmanager1_gpio0_o - attribute \src "ls180.v:137.13-137.66" - wire width 16 \main_libresocsim_libresoc_constraintmanager1_gpio0_oe - attribute \src "ls180.v:134.6-134.59" - wire \main_libresocsim_libresoc_constraintmanager1_uart0_rx - attribute \src "ls180.v:133.6-133.59" - wire \main_libresocsim_libresoc_constraintmanager1_uart0_tx - attribute \src "ls180.v:72.5-72.39" - wire \main_libresocsim_libresoc_dbus_ack - attribute \src "ls180.v:66.13-66.47" - wire width 29 \main_libresocsim_libresoc_dbus_adr - attribute \src "ls180.v:75.12-75.46" - wire width 2 \main_libresocsim_libresoc_dbus_bte - attribute \src "ls180.v:74.12-74.46" - wire width 3 \main_libresocsim_libresoc_dbus_cti - attribute \src "ls180.v:70.6-70.40" - wire \main_libresocsim_libresoc_dbus_cyc - attribute \src "ls180.v:68.13-68.49" - wire width 64 \main_libresocsim_libresoc_dbus_dat_r - attribute \src "ls180.v:67.13-67.49" - wire width 64 \main_libresocsim_libresoc_dbus_dat_w - attribute \src "ls180.v:76.5-76.39" - wire \main_libresocsim_libresoc_dbus_err - attribute \src "ls180.v:69.12-69.46" - wire width 8 \main_libresocsim_libresoc_dbus_sel - attribute \src "ls180.v:71.6-71.40" - wire \main_libresocsim_libresoc_dbus_stb - attribute \src "ls180.v:73.6-73.39" - wire \main_libresocsim_libresoc_dbus_we - attribute \src "ls180.v:83.5-83.39" - wire \main_libresocsim_libresoc_ibus_ack - attribute \src "ls180.v:77.13-77.47" - wire width 29 \main_libresocsim_libresoc_ibus_adr - attribute \src "ls180.v:86.12-86.46" - wire width 2 \main_libresocsim_libresoc_ibus_bte - attribute \src "ls180.v:85.12-85.46" - wire width 3 \main_libresocsim_libresoc_ibus_cti - attribute \src "ls180.v:81.6-81.40" - wire \main_libresocsim_libresoc_ibus_cyc - attribute \src "ls180.v:79.13-79.49" - wire width 64 \main_libresocsim_libresoc_ibus_dat_r - attribute \src "ls180.v:78.13-78.49" - wire width 64 \main_libresocsim_libresoc_ibus_dat_w - attribute \src "ls180.v:87.5-87.39" - wire \main_libresocsim_libresoc_ibus_err - attribute \src "ls180.v:80.12-80.46" - wire width 8 \main_libresocsim_libresoc_ibus_sel - attribute \src "ls180.v:82.6-82.40" - wire \main_libresocsim_libresoc_ibus_stb - attribute \src "ls180.v:84.6-84.39" - wire \main_libresocsim_libresoc_ibus_we - attribute \src "ls180.v:65.12-65.47" - wire width 16 \main_libresocsim_libresoc_interrupt - attribute \src "ls180.v:119.6-119.40" - wire \main_libresocsim_libresoc_jtag_tck - attribute \src "ls180.v:121.6-121.40" - wire \main_libresocsim_libresoc_jtag_tdi - attribute \src "ls180.v:122.6-122.40" - wire \main_libresocsim_libresoc_jtag_tdo - attribute \src "ls180.v:120.6-120.40" - wire \main_libresocsim_libresoc_jtag_tms - attribute \src "ls180.v:116.5-116.42" - wire \main_libresocsim_libresoc_jtag_wb_ack - attribute \src "ls180.v:110.13-110.50" - wire width 29 \main_libresocsim_libresoc_jtag_wb_adr - attribute \src "ls180.v:114.6-114.43" - wire \main_libresocsim_libresoc_jtag_wb_cyc - attribute \src "ls180.v:112.13-112.52" - wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_r - attribute \src "ls180.v:111.13-111.52" - wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_w - attribute \src "ls180.v:118.5-118.42" - wire \main_libresocsim_libresoc_jtag_wb_err - attribute \src "ls180.v:113.12-113.49" - wire width 8 \main_libresocsim_libresoc_jtag_wb_sel - attribute \src "ls180.v:115.6-115.43" - wire \main_libresocsim_libresoc_jtag_wb_stb - attribute \src "ls180.v:117.6-117.42" - wire \main_libresocsim_libresoc_jtag_wb_we - attribute \src "ls180.v:126.6-126.40" - wire \main_libresocsim_libresoc_pll_48_o - attribute \src "ls180.v:64.6-64.37" - wire \main_libresocsim_libresoc_reset - attribute \src "ls180.v:94.6-94.44" - wire \main_libresocsim_libresoc_xics_icp_ack - attribute \src "ls180.v:88.13-88.51" - wire width 30 \main_libresocsim_libresoc_xics_icp_adr - attribute \src "ls180.v:97.12-97.50" - wire width 2 \main_libresocsim_libresoc_xics_icp_bte - attribute \src "ls180.v:96.12-96.50" - wire width 3 \main_libresocsim_libresoc_xics_icp_cti - attribute \src "ls180.v:92.6-92.44" - wire \main_libresocsim_libresoc_xics_icp_cyc - attribute \src "ls180.v:90.13-90.53" - wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r - attribute \src "ls180.v:89.13-89.53" - wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w - attribute \src "ls180.v:98.6-98.44" - wire \main_libresocsim_libresoc_xics_icp_err - attribute \src "ls180.v:91.12-91.50" - wire width 4 \main_libresocsim_libresoc_xics_icp_sel - attribute \src "ls180.v:93.6-93.44" - wire \main_libresocsim_libresoc_xics_icp_stb - attribute \src "ls180.v:95.6-95.43" - wire \main_libresocsim_libresoc_xics_icp_we - attribute \src "ls180.v:105.6-105.44" - wire \main_libresocsim_libresoc_xics_ics_ack - attribute \src "ls180.v:99.13-99.51" - wire width 30 \main_libresocsim_libresoc_xics_ics_adr - attribute \src "ls180.v:108.12-108.50" - wire width 2 \main_libresocsim_libresoc_xics_ics_bte - attribute \src "ls180.v:107.12-107.50" - wire width 3 \main_libresocsim_libresoc_xics_ics_cti - attribute \src "ls180.v:103.6-103.44" - wire \main_libresocsim_libresoc_xics_ics_cyc - attribute \src "ls180.v:101.13-101.53" - wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r - attribute \src "ls180.v:100.13-100.53" - wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w - attribute \src "ls180.v:109.6-109.44" - wire \main_libresocsim_libresoc_xics_ics_err - attribute \src "ls180.v:102.12-102.50" - wire width 4 \main_libresocsim_libresoc_xics_ics_sel - attribute \src "ls180.v:104.6-104.44" - wire \main_libresocsim_libresoc_xics_ics_stb - attribute \src "ls180.v:106.6-106.43" - wire \main_libresocsim_libresoc_xics_ics_we - attribute \src "ls180.v:199.5-199.29" - wire \main_libresocsim_load_re - attribute \src "ls180.v:198.12-198.41" - wire width 32 \main_libresocsim_load_storage - attribute \src "ls180.v:189.5-189.33" - wire \main_libresocsim_ram_bus_ack - attribute \src "ls180.v:183.13-183.41" - wire width 30 \main_libresocsim_ram_bus_adr - attribute \src "ls180.v:192.12-192.40" - wire width 2 \main_libresocsim_ram_bus_bte - attribute \src "ls180.v:191.12-191.40" - wire width 3 \main_libresocsim_ram_bus_cti - attribute \src "ls180.v:187.6-187.34" - wire \main_libresocsim_ram_bus_cyc - attribute \src "ls180.v:185.13-185.43" - wire width 32 \main_libresocsim_ram_bus_dat_r - attribute \src "ls180.v:184.13-184.43" - wire width 32 \main_libresocsim_ram_bus_dat_w - attribute \src "ls180.v:193.5-193.33" - wire \main_libresocsim_ram_bus_err - attribute \src "ls180.v:186.12-186.40" - wire width 4 \main_libresocsim_ram_bus_sel - attribute \src "ls180.v:188.6-188.34" - wire \main_libresocsim_ram_bus_stb - attribute \src "ls180.v:190.6-190.33" - wire \main_libresocsim_ram_bus_we - attribute \src "ls180.v:201.5-201.31" - wire \main_libresocsim_reload_re - attribute \src "ls180.v:200.12-200.43" - wire width 32 \main_libresocsim_reload_storage - attribute \src "ls180.v:61.6-61.28" - wire \main_libresocsim_reset - attribute \src "ls180.v:56.5-56.30" - wire \main_libresocsim_reset_re - attribute \src "ls180.v:55.5-55.35" - wire \main_libresocsim_reset_storage - attribute \src "ls180.v:58.5-58.32" - wire \main_libresocsim_scratch_re - attribute \src "ls180.v:57.12-57.44" - wire width 32 \main_libresocsim_scratch_storage - attribute \src "ls180.v:205.5-205.37" - wire \main_libresocsim_update_value_re - attribute \src "ls180.v:204.5-204.42" - wire \main_libresocsim_update_value_storage - attribute \src "ls180.v:224.12-224.34" - wire width 32 \main_libresocsim_value - attribute \src "ls180.v:206.12-206.41" - wire width 32 \main_libresocsim_value_status - attribute \src "ls180.v:207.6-207.31" - wire \main_libresocsim_value_we - attribute \src "ls180.v:196.11-196.30" - wire width 4 \main_libresocsim_we - attribute \src "ls180.v:212.5-212.32" - wire \main_libresocsim_zero_clear - attribute \src "ls180.v:213.5-213.38" - wire \main_libresocsim_zero_old_trigger - attribute \src "ls180.v:210.5-210.34" - wire \main_libresocsim_zero_pending - attribute \src "ls180.v:209.6-209.34" - wire \main_libresocsim_zero_status - attribute \src "ls180.v:211.6-211.35" - wire \main_libresocsim_zero_trigger - attribute \src "ls180.v:806.6-806.26" - wire \main_litedram_wb_ack - attribute \src "ls180.v:800.12-800.32" - wire width 30 \main_litedram_wb_adr - attribute \src "ls180.v:804.5-804.25" - wire \main_litedram_wb_cyc - attribute \src "ls180.v:802.13-802.35" - wire width 16 \main_litedram_wb_dat_r - attribute \src "ls180.v:801.12-801.34" - wire width 16 \main_litedram_wb_dat_w - attribute \src "ls180.v:803.11-803.31" - wire width 2 \main_litedram_wb_sel - attribute \src "ls180.v:805.5-805.25" - wire \main_litedram_wb_stb - attribute \src "ls180.v:807.5-807.24" - wire \main_litedram_wb_we - attribute \src "ls180.v:1004.13-1004.20" - wire width 36 \main_nc - attribute \src "ls180.v:779.6-779.24" - wire \main_port_cmd_last - attribute \src "ls180.v:781.13-781.39" - wire width 24 \main_port_cmd_payload_addr - attribute \src "ls180.v:780.6-780.30" - wire \main_port_cmd_payload_we - attribute \src "ls180.v:778.6-778.25" - wire \main_port_cmd_ready - attribute \src "ls180.v:777.6-777.25" - wire \main_port_cmd_valid - attribute \src "ls180.v:776.6-776.21" - wire \main_port_flush - attribute \src "ls180.v:788.13-788.41" - wire width 16 \main_port_rdata_payload_data - attribute \src "ls180.v:787.6-787.27" - wire \main_port_rdata_ready - attribute \src "ls180.v:786.6-786.27" - wire \main_port_rdata_valid - attribute \src "ls180.v:784.13-784.41" - wire width 16 \main_port_wdata_payload_data - attribute \src "ls180.v:785.12-785.38" - wire width 2 \main_port_wdata_payload_we - attribute \src "ls180.v:783.6-783.27" - wire \main_port_wdata_ready - attribute \src "ls180.v:782.6-782.27" - wire \main_port_wdata_valid - attribute \src "ls180.v:1009.12-1009.29" - wire width 32 \main_pwm0_counter - attribute \src "ls180.v:1006.6-1006.22" - wire \main_pwm0_enable - attribute \src "ls180.v:1011.5-1011.24" - wire \main_pwm0_enable_re - attribute \src "ls180.v:1010.5-1010.29" - wire \main_pwm0_enable_storage - attribute \src "ls180.v:1008.13-1008.29" - wire width 32 \main_pwm0_period - attribute \src "ls180.v:1015.5-1015.24" - wire \main_pwm0_period_re - attribute \src "ls180.v:1014.12-1014.36" - wire width 32 \main_pwm0_period_storage - attribute \src "ls180.v:1007.13-1007.28" - wire width 32 \main_pwm0_width - attribute \src "ls180.v:1013.5-1013.23" - wire \main_pwm0_width_re - attribute \src "ls180.v:1012.12-1012.35" - wire width 32 \main_pwm0_width_storage - attribute \src "ls180.v:1019.12-1019.29" - wire width 32 \main_pwm1_counter - attribute \src "ls180.v:1016.6-1016.22" - wire \main_pwm1_enable - attribute \src "ls180.v:1021.5-1021.24" - wire \main_pwm1_enable_re - attribute \src "ls180.v:1020.5-1020.29" - wire \main_pwm1_enable_storage - attribute \src "ls180.v:1018.13-1018.29" - wire width 32 \main_pwm1_period - attribute \src "ls180.v:1025.5-1025.24" - wire \main_pwm1_period_re - attribute \src "ls180.v:1024.12-1024.36" - wire width 32 \main_pwm1_period_storage - attribute \src "ls180.v:1017.13-1017.28" - wire width 32 \main_pwm1_width - attribute \src "ls180.v:1023.5-1023.23" - wire \main_pwm1_width_re - attribute \src "ls180.v:1022.12-1022.35" - wire width 32 \main_pwm1_width_storage - attribute \src "ls180.v:245.11-245.25" - wire width 3 \main_rddata_en - attribute \src "ls180.v:1547.11-1547.43" - wire width 2 \main_sdblock2mem_converter_demux - attribute \src "ls180.v:1548.6-1548.42" - wire \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:1538.6-1538.43" - wire \main_sdblock2mem_converter_sink_first - attribute \src "ls180.v:1539.6-1539.42" - wire \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:1540.12-1540.56" - wire width 8 \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:1537.6-1537.43" - wire \main_sdblock2mem_converter_sink_ready - attribute \src "ls180.v:1536.6-1536.43" - wire \main_sdblock2mem_converter_sink_valid - attribute \src "ls180.v:1543.5-1543.44" - wire \main_sdblock2mem_converter_source_first - attribute \src "ls180.v:1544.5-1544.43" - wire \main_sdblock2mem_converter_source_last - attribute \src "ls180.v:1545.12-1545.58" - wire width 32 \main_sdblock2mem_converter_source_payload_data - attribute \src "ls180.v:1546.11-1546.70" - wire width 3 \main_sdblock2mem_converter_source_payload_valid_token_count - attribute \src "ls180.v:1542.6-1542.45" - wire \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:1541.6-1541.45" - wire \main_sdblock2mem_converter_source_valid - attribute \src "ls180.v:1549.5-1549.42" - wire \main_sdblock2mem_converter_strobe_all - attribute \src "ls180.v:1522.11-1522.40" - wire width 5 \main_sdblock2mem_fifo_consume - attribute \src "ls180.v:1527.6-1527.35" - wire \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:1531.6-1531.41" - wire \main_sdblock2mem_fifo_fifo_in_first - attribute \src "ls180.v:1532.6-1532.40" - wire \main_sdblock2mem_fifo_fifo_in_last - attribute \src "ls180.v:1530.12-1530.54" - wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data - attribute \src "ls180.v:1534.6-1534.42" - wire \main_sdblock2mem_fifo_fifo_out_first - attribute \src "ls180.v:1535.6-1535.41" - wire \main_sdblock2mem_fifo_fifo_out_last - attribute \src "ls180.v:1533.12-1533.55" - wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data - attribute \src "ls180.v:1519.11-1519.38" - wire width 6 \main_sdblock2mem_fifo_level - attribute \src "ls180.v:1521.11-1521.40" - wire width 5 \main_sdblock2mem_fifo_produce - attribute \src "ls180.v:1528.12-1528.44" - wire width 5 \main_sdblock2mem_fifo_rdport_adr - attribute \src "ls180.v:1529.12-1529.46" - wire width 10 \main_sdblock2mem_fifo_rdport_dat_r - attribute \src "ls180.v:1520.5-1520.34" - wire \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:1505.6-1505.38" - wire \main_sdblock2mem_fifo_sink_first - attribute \src "ls180.v:1506.6-1506.37" - wire \main_sdblock2mem_fifo_sink_last - attribute \src "ls180.v:1507.12-1507.51" - wire width 8 \main_sdblock2mem_fifo_sink_payload_data - attribute \src "ls180.v:1504.6-1504.38" - wire \main_sdblock2mem_fifo_sink_ready - attribute \src "ls180.v:1503.6-1503.38" - wire \main_sdblock2mem_fifo_sink_valid - attribute \src "ls180.v:1510.6-1510.40" - wire \main_sdblock2mem_fifo_source_first - attribute \src "ls180.v:1511.6-1511.39" - wire \main_sdblock2mem_fifo_source_last - attribute \src "ls180.v:1512.12-1512.53" - wire width 8 \main_sdblock2mem_fifo_source_payload_data - attribute \src "ls180.v:1509.6-1509.40" - wire \main_sdblock2mem_fifo_source_ready - attribute \src "ls180.v:1508.6-1508.40" - wire \main_sdblock2mem_fifo_source_valid - attribute \src "ls180.v:1517.12-1517.46" - wire width 10 \main_sdblock2mem_fifo_syncfifo_din - attribute \src "ls180.v:1518.12-1518.47" - wire width 10 \main_sdblock2mem_fifo_syncfifo_dout - attribute \src "ls180.v:1515.6-1515.39" - wire \main_sdblock2mem_fifo_syncfifo_re - attribute \src "ls180.v:1516.6-1516.45" - wire \main_sdblock2mem_fifo_syncfifo_readable - attribute \src "ls180.v:1513.6-1513.39" - wire \main_sdblock2mem_fifo_syncfifo_we - attribute \src "ls180.v:1514.6-1514.45" - wire \main_sdblock2mem_fifo_syncfifo_writable - attribute \src "ls180.v:1523.11-1523.43" - wire width 5 \main_sdblock2mem_fifo_wrport_adr - attribute \src "ls180.v:1524.12-1524.46" - wire width 10 \main_sdblock2mem_fifo_wrport_dat_r - attribute \src "ls180.v:1526.12-1526.46" - wire width 10 \main_sdblock2mem_fifo_wrport_dat_w - attribute \src "ls180.v:1525.6-1525.37" - wire \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:1500.6-1500.38" - wire \main_sdblock2mem_sink_sink_first - attribute \src "ls180.v:1501.6-1501.37" - wire \main_sdblock2mem_sink_sink_last - attribute \src "ls180.v:1557.12-1557.54" - wire width 32 \main_sdblock2mem_sink_sink_payload_address - attribute \src "ls180.v:1502.12-1502.52" - wire width 8 \main_sdblock2mem_sink_sink_payload_data0 - attribute \src "ls180.v:1558.12-1558.52" - wire width 32 \main_sdblock2mem_sink_sink_payload_data1 - attribute \src "ls180.v:1499.6-1499.39" - wire \main_sdblock2mem_sink_sink_ready0 - attribute \src "ls180.v:1556.6-1556.39" - wire \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:1498.6-1498.39" - wire \main_sdblock2mem_sink_sink_valid0 - attribute \src "ls180.v:1555.5-1555.38" - wire \main_sdblock2mem_sink_sink_valid1 - attribute \src "ls180.v:1552.6-1552.42" - wire \main_sdblock2mem_source_source_first - attribute \src "ls180.v:1553.6-1553.41" - wire \main_sdblock2mem_source_source_last - attribute \src "ls180.v:1554.13-1554.56" - wire width 32 \main_sdblock2mem_source_source_payload_data - attribute \src "ls180.v:1551.6-1551.42" - wire \main_sdblock2mem_source_source_ready - attribute \src "ls180.v:1550.6-1550.42" - wire \main_sdblock2mem_source_source_valid - attribute \src "ls180.v:1574.13-1574.52" - wire width 32 \main_sdblock2mem_wishbonedmawriter_base - attribute \src "ls180.v:1565.5-1565.47" - wire \main_sdblock2mem_wishbonedmawriter_base_re - attribute \src "ls180.v:1564.12-1564.59" - wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage - attribute \src "ls180.v:1569.5-1569.49" - wire \main_sdblock2mem_wishbonedmawriter_enable_re - attribute \src "ls180.v:1568.5-1568.54" - wire \main_sdblock2mem_wishbonedmawriter_enable_storage - attribute \src "ls180.v:1576.13-1576.54" - wire width 32 \main_sdblock2mem_wishbonedmawriter_length - attribute \src "ls180.v:1567.5-1567.49" - wire \main_sdblock2mem_wishbonedmawriter_length_re - attribute \src "ls180.v:1566.12-1566.61" - wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage - attribute \src "ls180.v:1573.5-1573.47" - wire \main_sdblock2mem_wishbonedmawriter_loop_re - attribute \src "ls180.v:1572.5-1572.52" - wire \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:1575.12-1575.53" - wire width 32 \main_sdblock2mem_wishbonedmawriter_offset - attribute \src "ls180.v:1829.12-1829.79" - wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value - attribute \src "ls180.v:1830.5-1830.75" - wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:1577.6-1577.46" - wire \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:1561.6-1561.51" - wire \main_sdblock2mem_wishbonedmawriter_sink_first - attribute \src "ls180.v:1562.6-1562.50" - wire \main_sdblock2mem_wishbonedmawriter_sink_last - attribute \src "ls180.v:1563.13-1563.65" - wire width 32 \main_sdblock2mem_wishbonedmawriter_sink_payload_data - attribute \src "ls180.v:1560.5-1560.50" - wire \main_sdblock2mem_wishbonedmawriter_sink_ready - attribute \src "ls180.v:1559.6-1559.51" - wire \main_sdblock2mem_wishbonedmawriter_sink_valid - attribute \src "ls180.v:1570.5-1570.46" - wire \main_sdblock2mem_wishbonedmawriter_status - attribute \src "ls180.v:1571.6-1571.43" - wire \main_sdblock2mem_wishbonedmawriter_we - attribute \src "ls180.v:1339.5-1339.31" - wire \main_sdcore_block_count_re - attribute \src "ls180.v:1338.12-1338.43" - wire width 32 \main_sdcore_block_count_storage - attribute \src "ls180.v:1337.5-1337.32" - wire \main_sdcore_block_length_re - attribute \src "ls180.v:1336.11-1336.43" - wire width 10 \main_sdcore_block_length_storage - attribute \src "ls180.v:1323.5-1323.32" - wire \main_sdcore_cmd_argument_re - attribute \src "ls180.v:1322.12-1322.44" - wire width 32 \main_sdcore_cmd_argument_storage - attribute \src "ls180.v:1325.5-1325.31" - wire \main_sdcore_cmd_command_re - attribute \src "ls180.v:1324.12-1324.43" - wire width 32 \main_sdcore_cmd_command_storage - attribute \src "ls180.v:1478.11-1478.32" - wire width 3 \main_sdcore_cmd_count - attribute \src "ls180.v:1813.11-1813.55" - wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2 - attribute \src "ls180.v:1814.5-1814.52" - wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:1479.5-1479.25" - wire \main_sdcore_cmd_done - attribute \src "ls180.v:1809.5-1809.48" - wire \main_sdcore_cmd_done_sdcore_fsm_next_value0 - attribute \src "ls180.v:1810.5-1810.51" - wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:1480.5-1480.26" - wire \main_sdcore_cmd_error - attribute \src "ls180.v:1817.5-1817.49" - wire \main_sdcore_cmd_error_sdcore_fsm_next_value4 - attribute \src "ls180.v:1818.5-1818.52" - wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:1332.12-1332.40" - wire width 4 \main_sdcore_cmd_event_status - attribute \src "ls180.v:1333.6-1333.30" - wire \main_sdcore_cmd_event_we - attribute \src "ls180.v:1330.13-1330.44" - wire width 128 \main_sdcore_cmd_response_status - attribute \src "ls180.v:1825.13-1825.67" - wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 - attribute \src "ls180.v:1826.5-1826.62" - wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:1331.6-1331.33" - wire \main_sdcore_cmd_response_we - attribute \src "ls180.v:1327.6-1327.28" - wire \main_sdcore_cmd_send_r - attribute \src "ls180.v:1326.6-1326.29" - wire \main_sdcore_cmd_send_re - attribute \src "ls180.v:1329.5-1329.27" - wire \main_sdcore_cmd_send_w - attribute \src "ls180.v:1328.6-1328.29" - wire \main_sdcore_cmd_send_we - attribute \src "ls180.v:1481.5-1481.28" - wire \main_sdcore_cmd_timeout - attribute \src "ls180.v:1819.5-1819.51" - wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 - attribute \src "ls180.v:1820.5-1820.54" - wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:1477.12-1477.32" - wire width 2 \main_sdcore_cmd_type - attribute \src "ls180.v:1439.11-1439.40" - wire width 4 \main_sdcore_crc16_checker_cnt - attribute \src "ls180.v:1445.5-1445.39" - wire \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:1444.12-1444.46" - wire width 16 \main_sdcore_crc16_checker_crc0_crc - attribute \src "ls180.v:1440.12-1440.50" - wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0 - attribute \src "ls180.v:1441.13-1441.51" - wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1 - attribute \src "ls180.v:1442.13-1442.51" - wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:1446.6-1446.43" - wire \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:1443.12-1443.46" - wire width 2 \main_sdcore_crc16_checker_crc0_val - attribute \src "ls180.v:1452.5-1452.39" - wire \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:1451.12-1451.46" - wire width 16 \main_sdcore_crc16_checker_crc1_crc - attribute \src "ls180.v:1447.12-1447.50" - wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0 - attribute \src "ls180.v:1448.13-1448.51" - wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1 - attribute \src "ls180.v:1449.13-1449.51" - wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:1453.6-1453.43" - wire \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:1450.12-1450.46" - wire width 2 \main_sdcore_crc16_checker_crc1_val - attribute \src "ls180.v:1459.5-1459.39" - wire \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:1458.12-1458.46" - wire width 16 \main_sdcore_crc16_checker_crc2_crc - attribute \src "ls180.v:1454.12-1454.50" - wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0 - attribute \src "ls180.v:1455.13-1455.51" - wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1 - attribute \src "ls180.v:1456.13-1456.51" - wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:1460.6-1460.43" - wire \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:1457.12-1457.46" - wire width 2 \main_sdcore_crc16_checker_crc2_val - attribute \src "ls180.v:1466.5-1466.39" - wire \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:1465.12-1465.46" - wire width 16 \main_sdcore_crc16_checker_crc3_crc - attribute \src "ls180.v:1461.12-1461.50" - wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0 - attribute \src "ls180.v:1462.13-1462.51" - wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1 - attribute \src "ls180.v:1463.13-1463.51" - wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:1467.6-1467.43" - wire \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:1464.12-1464.46" - wire width 2 \main_sdcore_crc16_checker_crc3_val - attribute \src "ls180.v:1468.12-1468.45" - wire width 16 \main_sdcore_crc16_checker_crctmp0 - attribute \src "ls180.v:1469.12-1469.45" - wire width 16 \main_sdcore_crc16_checker_crctmp1 - attribute \src "ls180.v:1470.12-1470.45" - wire width 16 \main_sdcore_crc16_checker_crctmp2 - attribute \src "ls180.v:1471.12-1471.45" - wire width 16 \main_sdcore_crc16_checker_crctmp3 - attribute \src "ls180.v:1473.12-1473.43" - wire width 16 \main_sdcore_crc16_checker_fifo0 - attribute \src "ls180.v:1474.12-1474.43" - wire width 16 \main_sdcore_crc16_checker_fifo1 - attribute \src "ls180.v:1475.12-1475.43" - wire width 16 \main_sdcore_crc16_checker_fifo2 - attribute \src "ls180.v:1476.12-1476.43" - wire width 16 \main_sdcore_crc16_checker_fifo3 - attribute \src "ls180.v:1430.5-1430.41" - wire \main_sdcore_crc16_checker_sink_first - attribute \src "ls180.v:1431.5-1431.40" - wire \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:1432.11-1432.54" - wire width 8 \main_sdcore_crc16_checker_sink_payload_data - attribute \src "ls180.v:1429.5-1429.41" - wire \main_sdcore_crc16_checker_sink_ready - attribute \src "ls180.v:1428.5-1428.41" - wire \main_sdcore_crc16_checker_sink_valid - attribute \src "ls180.v:1435.5-1435.43" - wire \main_sdcore_crc16_checker_source_first - attribute \src "ls180.v:1436.6-1436.43" - wire \main_sdcore_crc16_checker_source_last - attribute \src "ls180.v:1437.12-1437.57" - wire width 8 \main_sdcore_crc16_checker_source_payload_data - attribute \src "ls180.v:1434.6-1434.44" - wire \main_sdcore_crc16_checker_source_ready - attribute \src "ls180.v:1433.5-1433.43" - wire \main_sdcore_crc16_checker_source_valid - attribute \src "ls180.v:1438.11-1438.40" - wire width 8 \main_sdcore_crc16_checker_val - attribute \src "ls180.v:1472.5-1472.36" - wire \main_sdcore_crc16_checker_valid - attribute \src "ls180.v:1395.11-1395.41" - wire width 3 \main_sdcore_crc16_inserter_cnt - attribute \src "ls180.v:1805.11-1805.80" - wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 - attribute \src "ls180.v:1806.5-1806.77" - wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:1401.6-1401.41" - wire \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:1400.12-1400.47" - wire width 16 \main_sdcore_crc16_inserter_crc0_crc - attribute \src "ls180.v:1396.12-1396.51" - wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0 - attribute \src "ls180.v:1397.13-1397.52" - wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1 - attribute \src "ls180.v:1398.13-1398.52" - wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:1402.6-1402.44" - wire \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:1399.12-1399.47" - wire width 2 \main_sdcore_crc16_inserter_crc0_val - attribute \src "ls180.v:1408.6-1408.41" - wire \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:1407.12-1407.47" - wire width 16 \main_sdcore_crc16_inserter_crc1_crc - attribute \src "ls180.v:1403.12-1403.51" - wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0 - attribute \src "ls180.v:1404.13-1404.52" - wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1 - attribute \src "ls180.v:1405.13-1405.52" - wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:1409.6-1409.44" - wire \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:1406.12-1406.47" - wire width 2 \main_sdcore_crc16_inserter_crc1_val - attribute \src "ls180.v:1415.6-1415.41" - wire \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:1414.12-1414.47" - wire width 16 \main_sdcore_crc16_inserter_crc2_crc - attribute \src "ls180.v:1410.12-1410.51" - wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0 - attribute \src "ls180.v:1411.13-1411.52" - wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1 - attribute \src "ls180.v:1412.13-1412.52" - wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:1416.6-1416.44" - wire \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:1413.12-1413.47" - wire width 2 \main_sdcore_crc16_inserter_crc2_val - attribute \src "ls180.v:1422.6-1422.41" - wire \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:1421.12-1421.47" - wire width 16 \main_sdcore_crc16_inserter_crc3_crc - attribute \src "ls180.v:1417.12-1417.51" - wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0 - attribute \src "ls180.v:1418.13-1418.52" - wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1 - attribute \src "ls180.v:1419.13-1419.52" - wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:1423.6-1423.44" - wire \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:1420.12-1420.47" - wire width 2 \main_sdcore_crc16_inserter_crc3_val - attribute \src "ls180.v:1424.12-1424.46" - wire width 16 \main_sdcore_crc16_inserter_crctmp0 - attribute \src "ls180.v:1797.12-1797.85" - wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 - attribute \src "ls180.v:1798.5-1798.81" - wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:1425.12-1425.46" - wire width 16 \main_sdcore_crc16_inserter_crctmp1 - attribute \src "ls180.v:1799.12-1799.85" - wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 - attribute \src "ls180.v:1800.5-1800.81" - wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:1426.12-1426.46" - wire width 16 \main_sdcore_crc16_inserter_crctmp2 - attribute \src "ls180.v:1801.12-1801.85" - wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 - attribute \src "ls180.v:1802.5-1802.81" - wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:1427.12-1427.46" - wire width 16 \main_sdcore_crc16_inserter_crctmp3 - attribute \src "ls180.v:1803.12-1803.85" - wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 - attribute \src "ls180.v:1804.5-1804.81" - wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:1387.6-1387.43" - wire \main_sdcore_crc16_inserter_sink_first - attribute \src "ls180.v:1388.6-1388.42" - wire \main_sdcore_crc16_inserter_sink_last - attribute \src "ls180.v:1389.12-1389.56" - wire width 8 \main_sdcore_crc16_inserter_sink_payload_data - attribute \src "ls180.v:1386.5-1386.42" - wire \main_sdcore_crc16_inserter_sink_ready - attribute \src "ls180.v:1385.6-1385.43" - wire \main_sdcore_crc16_inserter_sink_valid - attribute \src "ls180.v:1392.5-1392.44" - wire \main_sdcore_crc16_inserter_source_first - attribute \src "ls180.v:1393.5-1393.43" - wire \main_sdcore_crc16_inserter_source_last - attribute \src "ls180.v:1394.11-1394.57" - wire width 8 \main_sdcore_crc16_inserter_source_payload_data - attribute \src "ls180.v:1391.5-1391.44" - wire \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:1390.5-1390.44" - wire \main_sdcore_crc16_inserter_source_valid - attribute \src "ls180.v:1383.6-1383.35" - wire \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:1382.11-1382.40" - wire width 7 \main_sdcore_crc7_inserter_crc - attribute \src "ls180.v:1340.11-1340.44" - wire width 7 \main_sdcore_crc7_inserter_crcreg0 - attribute \src "ls180.v:1341.12-1341.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg1 - attribute \src "ls180.v:1350.12-1350.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg10 - attribute \src "ls180.v:1351.12-1351.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg11 - attribute \src "ls180.v:1352.12-1352.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg12 - attribute \src "ls180.v:1353.12-1353.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg13 - attribute \src "ls180.v:1354.12-1354.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg14 - attribute \src "ls180.v:1355.12-1355.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg15 - attribute \src "ls180.v:1356.12-1356.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg16 - attribute \src "ls180.v:1357.12-1357.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg17 - attribute \src "ls180.v:1358.12-1358.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg18 - attribute \src "ls180.v:1359.12-1359.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg19 - attribute \src "ls180.v:1342.12-1342.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg2 - attribute \src "ls180.v:1360.12-1360.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg20 - attribute \src "ls180.v:1361.12-1361.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg21 - attribute \src "ls180.v:1362.12-1362.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg22 - attribute \src "ls180.v:1363.12-1363.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg23 - attribute \src "ls180.v:1364.12-1364.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg24 - attribute \src "ls180.v:1365.12-1365.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg25 - attribute \src "ls180.v:1366.12-1366.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg26 - attribute \src "ls180.v:1367.12-1367.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg27 - attribute \src "ls180.v:1368.12-1368.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg28 - attribute \src "ls180.v:1369.12-1369.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg29 - attribute \src "ls180.v:1343.12-1343.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg3 - attribute \src "ls180.v:1370.12-1370.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg30 - attribute \src "ls180.v:1371.12-1371.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg31 - attribute \src "ls180.v:1372.12-1372.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg32 - attribute \src "ls180.v:1373.12-1373.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg33 - attribute \src "ls180.v:1374.12-1374.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg34 - attribute \src "ls180.v:1375.12-1375.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg35 - attribute \src "ls180.v:1376.12-1376.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg36 - attribute \src "ls180.v:1377.12-1377.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg37 - attribute \src "ls180.v:1378.12-1378.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg38 - attribute \src "ls180.v:1379.12-1379.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg39 - attribute \src "ls180.v:1344.12-1344.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg4 - attribute \src "ls180.v:1380.12-1380.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:1345.12-1345.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg5 - attribute \src "ls180.v:1346.12-1346.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg6 - attribute \src "ls180.v:1347.12-1347.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg7 - attribute \src "ls180.v:1348.12-1348.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg8 - attribute \src "ls180.v:1349.12-1349.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg9 - attribute \src "ls180.v:1384.6-1384.38" - wire \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:1381.13-1381.42" - wire width 40 \main_sdcore_crc7_inserter_val - attribute \src "ls180.v:1483.12-1483.34" - wire width 32 \main_sdcore_data_count - attribute \src "ls180.v:1815.12-1815.57" - wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3 - attribute \src "ls180.v:1816.5-1816.53" - wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:1484.5-1484.26" - wire \main_sdcore_data_done - attribute \src "ls180.v:1811.5-1811.49" - wire \main_sdcore_data_done_sdcore_fsm_next_value1 - attribute \src "ls180.v:1812.5-1812.52" - wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:1485.5-1485.27" - wire \main_sdcore_data_error - attribute \src "ls180.v:1821.5-1821.50" - wire \main_sdcore_data_error_sdcore_fsm_next_value6 - attribute \src "ls180.v:1822.5-1822.53" - wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:1334.12-1334.41" - wire width 4 \main_sdcore_data_event_status - attribute \src "ls180.v:1335.6-1335.31" - wire \main_sdcore_data_event_we - attribute \src "ls180.v:1486.5-1486.29" - wire \main_sdcore_data_timeout - attribute \src "ls180.v:1823.5-1823.52" - wire \main_sdcore_data_timeout_sdcore_fsm_next_value7 - attribute \src "ls180.v:1824.5-1824.55" - wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:1482.12-1482.33" - wire width 2 \main_sdcore_data_type - attribute \src "ls180.v:1314.6-1314.33" - wire \main_sdcore_sink_sink_first - attribute \src "ls180.v:1315.6-1315.32" - wire \main_sdcore_sink_sink_last - attribute \src "ls180.v:1316.12-1316.46" - wire width 8 \main_sdcore_sink_sink_payload_data - attribute \src "ls180.v:1313.6-1313.33" - wire \main_sdcore_sink_sink_ready - attribute \src "ls180.v:1312.6-1312.33" - wire \main_sdcore_sink_sink_valid - attribute \src "ls180.v:1319.6-1319.37" - wire \main_sdcore_source_source_first - attribute \src "ls180.v:1320.6-1320.36" - wire \main_sdcore_source_source_last - attribute \src "ls180.v:1321.12-1321.50" - wire width 8 \main_sdcore_source_source_payload_data - attribute \src "ls180.v:1318.6-1318.37" - wire \main_sdcore_source_source_ready - attribute \src "ls180.v:1317.6-1317.37" - wire \main_sdcore_source_source_valid - attribute \src "ls180.v:1632.6-1632.38" - wire \main_sdmem2block_converter_first - attribute \src "ls180.v:1633.6-1633.37" - wire \main_sdmem2block_converter_last - attribute \src "ls180.v:1631.11-1631.41" - wire width 2 \main_sdmem2block_converter_mux - attribute \src "ls180.v:1622.6-1622.43" - wire \main_sdmem2block_converter_sink_first - attribute \src "ls180.v:1623.6-1623.42" - wire \main_sdmem2block_converter_sink_last - attribute \src "ls180.v:1624.13-1624.57" - wire width 32 \main_sdmem2block_converter_sink_payload_data - attribute \src "ls180.v:1621.6-1621.43" - wire \main_sdmem2block_converter_sink_ready - attribute \src "ls180.v:1620.6-1620.43" - wire \main_sdmem2block_converter_sink_valid - attribute \src "ls180.v:1627.6-1627.45" - wire \main_sdmem2block_converter_source_first - attribute \src "ls180.v:1628.6-1628.44" - wire \main_sdmem2block_converter_source_last - attribute \src "ls180.v:1629.11-1629.57" - wire width 8 \main_sdmem2block_converter_source_payload_data - attribute \src "ls180.v:1630.6-1630.65" - wire \main_sdmem2block_converter_source_payload_valid_token_count - attribute \src "ls180.v:1626.6-1626.45" - wire \main_sdmem2block_converter_source_ready - attribute \src "ls180.v:1625.6-1625.45" - wire \main_sdmem2block_converter_source_valid - attribute \src "ls180.v:1616.13-1616.38" - wire width 32 \main_sdmem2block_dma_base - attribute \src "ls180.v:1605.5-1605.33" - wire \main_sdmem2block_dma_base_re - attribute \src "ls180.v:1604.12-1604.45" - wire width 64 \main_sdmem2block_dma_base_storage - attribute \src "ls180.v:1603.12-1603.37" - wire width 32 \main_sdmem2block_dma_data - attribute \src "ls180.v:1833.12-1833.67" - wire width 32 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value - attribute \src "ls180.v:1834.5-1834.63" - wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:1610.5-1610.37" - wire \main_sdmem2block_dma_done_status - attribute \src "ls180.v:1611.6-1611.34" - wire \main_sdmem2block_dma_done_we - attribute \src "ls180.v:1609.5-1609.35" - wire \main_sdmem2block_dma_enable_re - attribute \src "ls180.v:1608.5-1608.40" - wire \main_sdmem2block_dma_enable_storage - attribute \src "ls180.v:1618.13-1618.40" - wire width 32 \main_sdmem2block_dma_length - attribute \src "ls180.v:1607.5-1607.35" - wire \main_sdmem2block_dma_length_re - attribute \src "ls180.v:1606.12-1606.47" - wire width 32 \main_sdmem2block_dma_length_storage - attribute \src "ls180.v:1613.5-1613.33" - wire \main_sdmem2block_dma_loop_re - attribute \src "ls180.v:1612.5-1612.38" - wire \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:1617.12-1617.39" - wire width 32 \main_sdmem2block_dma_offset - attribute \src "ls180.v:1837.12-1837.79" - wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value - attribute \src "ls180.v:1838.5-1838.75" - wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:1614.13-1614.47" - wire width 32 \main_sdmem2block_dma_offset_status - attribute \src "ls180.v:1615.6-1615.36" - wire \main_sdmem2block_dma_offset_we - attribute \src "ls180.v:1619.6-1619.32" - wire \main_sdmem2block_dma_reset - attribute \src "ls180.v:1596.5-1596.35" - wire \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:1597.12-1597.53" - wire width 32 \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:1595.5-1595.36" - wire \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:1594.5-1594.36" - wire \main_sdmem2block_dma_sink_valid - attribute \src "ls180.v:1600.5-1600.38" - wire \main_sdmem2block_dma_source_first - attribute \src "ls180.v:1601.5-1601.37" - wire \main_sdmem2block_dma_source_last - attribute \src "ls180.v:1602.12-1602.52" - wire width 32 \main_sdmem2block_dma_source_payload_data - attribute \src "ls180.v:1599.6-1599.39" - wire \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:1598.5-1598.38" - wire \main_sdmem2block_dma_source_valid - attribute \src "ls180.v:1658.11-1658.40" - wire width 5 \main_sdmem2block_fifo_consume - attribute \src "ls180.v:1663.6-1663.35" - wire \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:1667.6-1667.41" - wire \main_sdmem2block_fifo_fifo_in_first - attribute \src "ls180.v:1668.6-1668.40" - wire \main_sdmem2block_fifo_fifo_in_last - attribute \src "ls180.v:1666.12-1666.54" - wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data - attribute \src "ls180.v:1670.6-1670.42" - wire \main_sdmem2block_fifo_fifo_out_first - attribute \src "ls180.v:1671.6-1671.41" - wire \main_sdmem2block_fifo_fifo_out_last - attribute \src "ls180.v:1669.12-1669.55" - wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data - attribute \src "ls180.v:1655.11-1655.38" - wire width 6 \main_sdmem2block_fifo_level - attribute \src "ls180.v:1657.11-1657.40" - wire width 5 \main_sdmem2block_fifo_produce - attribute \src "ls180.v:1664.12-1664.44" - wire width 5 \main_sdmem2block_fifo_rdport_adr - attribute \src "ls180.v:1665.12-1665.46" - wire width 10 \main_sdmem2block_fifo_rdport_dat_r - attribute \src "ls180.v:1656.5-1656.34" - wire \main_sdmem2block_fifo_replace - attribute \src "ls180.v:1641.6-1641.38" - wire \main_sdmem2block_fifo_sink_first - attribute \src "ls180.v:1642.6-1642.37" - wire \main_sdmem2block_fifo_sink_last - attribute \src "ls180.v:1643.12-1643.51" - wire width 8 \main_sdmem2block_fifo_sink_payload_data - attribute \src "ls180.v:1640.6-1640.38" - wire \main_sdmem2block_fifo_sink_ready - attribute \src "ls180.v:1639.6-1639.38" - wire \main_sdmem2block_fifo_sink_valid - attribute \src "ls180.v:1646.6-1646.40" - wire \main_sdmem2block_fifo_source_first - attribute \src "ls180.v:1647.6-1647.39" - wire \main_sdmem2block_fifo_source_last - attribute \src "ls180.v:1648.12-1648.53" - wire width 8 \main_sdmem2block_fifo_source_payload_data - attribute \src "ls180.v:1645.6-1645.40" - wire \main_sdmem2block_fifo_source_ready - attribute \src "ls180.v:1644.6-1644.40" - wire \main_sdmem2block_fifo_source_valid - attribute \src "ls180.v:1653.12-1653.46" - wire width 10 \main_sdmem2block_fifo_syncfifo_din - attribute \src "ls180.v:1654.12-1654.47" - wire width 10 \main_sdmem2block_fifo_syncfifo_dout - attribute \src "ls180.v:1651.6-1651.39" - wire \main_sdmem2block_fifo_syncfifo_re - attribute \src "ls180.v:1652.6-1652.45" - wire \main_sdmem2block_fifo_syncfifo_readable - attribute \src "ls180.v:1649.6-1649.39" - wire \main_sdmem2block_fifo_syncfifo_we - attribute \src "ls180.v:1650.6-1650.45" - wire \main_sdmem2block_fifo_syncfifo_writable - attribute \src "ls180.v:1659.11-1659.43" - wire width 5 \main_sdmem2block_fifo_wrport_adr - attribute \src "ls180.v:1660.12-1660.46" - wire width 10 \main_sdmem2block_fifo_wrport_dat_r - attribute \src "ls180.v:1662.12-1662.46" - wire width 10 \main_sdmem2block_fifo_wrport_dat_w - attribute \src "ls180.v:1661.6-1661.37" - wire \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:1591.6-1591.43" - wire \main_sdmem2block_source_source_first0 - attribute \src "ls180.v:1636.6-1636.43" - wire \main_sdmem2block_source_source_first1 - attribute \src "ls180.v:1592.6-1592.42" - wire \main_sdmem2block_source_source_last0 - attribute \src "ls180.v:1637.6-1637.42" - wire \main_sdmem2block_source_source_last1 - attribute \src "ls180.v:1593.12-1593.56" - wire width 8 \main_sdmem2block_source_source_payload_data0 - attribute \src "ls180.v:1638.12-1638.56" - wire width 8 \main_sdmem2block_source_source_payload_data1 - attribute \src "ls180.v:1590.6-1590.43" - wire \main_sdmem2block_source_source_ready0 - attribute \src "ls180.v:1635.6-1635.43" - wire \main_sdmem2block_source_source_ready1 - attribute \src "ls180.v:1589.6-1589.43" - wire \main_sdmem2block_source_source_valid0 - attribute \src "ls180.v:1634.6-1634.43" - wire \main_sdmem2block_source_source_valid1 - attribute \src "ls180.v:1040.6-1040.27" - wire \main_sdphy_clocker_ce - attribute \src "ls180.v:1039.5-1039.28" - wire \main_sdphy_clocker_clk0 - attribute \src "ls180.v:1042.5-1042.28" - wire \main_sdphy_clocker_clk1 - attribute \src "ls180.v:1043.5-1043.29" - wire \main_sdphy_clocker_clk_d - attribute \src "ls180.v:1041.11-1041.34" - wire width 9 \main_sdphy_clocker_clks - attribute \src "ls180.v:1037.5-1037.26" - wire \main_sdphy_clocker_re - attribute \src "ls180.v:1038.6-1038.29" - wire \main_sdphy_clocker_stop - attribute \src "ls180.v:1036.11-1036.37" - wire width 9 \main_sdphy_clocker_storage - attribute \src "ls180.v:1140.6-1140.41" - wire \main_sdphy_cmdr_cmdr_buf_sink_first - attribute \src "ls180.v:1141.6-1141.40" - wire \main_sdphy_cmdr_cmdr_buf_sink_last - attribute \src "ls180.v:1142.12-1142.54" - wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data - attribute \src "ls180.v:1139.6-1139.41" - wire \main_sdphy_cmdr_cmdr_buf_sink_ready - attribute \src "ls180.v:1138.6-1138.41" - wire \main_sdphy_cmdr_cmdr_buf_sink_valid - attribute \src "ls180.v:1145.5-1145.42" - wire \main_sdphy_cmdr_cmdr_buf_source_first - attribute \src "ls180.v:1146.5-1146.41" - wire \main_sdphy_cmdr_cmdr_buf_source_last - attribute \src "ls180.v:1147.11-1147.55" - wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data - attribute \src "ls180.v:1144.6-1144.43" - wire \main_sdphy_cmdr_cmdr_buf_source_ready - attribute \src "ls180.v:1143.5-1143.42" - wire \main_sdphy_cmdr_cmdr_buf_source_valid - attribute \src "ls180.v:1130.11-1130.47" - wire width 3 \main_sdphy_cmdr_cmdr_converter_demux - attribute \src "ls180.v:1131.6-1131.46" - wire \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:1121.5-1121.46" - wire \main_sdphy_cmdr_cmdr_converter_sink_first - attribute \src "ls180.v:1122.5-1122.45" - wire \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:1123.6-1123.54" - wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:1120.6-1120.47" - wire \main_sdphy_cmdr_cmdr_converter_sink_ready - attribute \src "ls180.v:1119.6-1119.47" - wire \main_sdphy_cmdr_cmdr_converter_sink_valid - attribute \src "ls180.v:1126.5-1126.48" - wire \main_sdphy_cmdr_cmdr_converter_source_first - attribute \src "ls180.v:1127.5-1127.47" - wire \main_sdphy_cmdr_cmdr_converter_source_last - attribute \src "ls180.v:1128.11-1128.61" - wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data - attribute \src "ls180.v:1129.11-1129.74" - wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1125.6-1125.49" - wire \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:1124.6-1124.49" - wire \main_sdphy_cmdr_cmdr_converter_source_valid - attribute \src "ls180.v:1132.5-1132.46" - wire \main_sdphy_cmdr_cmdr_converter_strobe_all - attribute \src "ls180.v:1103.6-1103.40" - wire \main_sdphy_cmdr_cmdr_pads_in_first - attribute \src "ls180.v:1104.6-1104.39" - wire \main_sdphy_cmdr_cmdr_pads_in_last - attribute \src "ls180.v:1105.6-1105.46" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk - attribute \src "ls180.v:1106.6-1106.48" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - attribute \src "ls180.v:1107.6-1107.48" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o - attribute \src "ls180.v:1108.6-1108.49" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1109.12-1109.55" - wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i - attribute \src "ls180.v:1110.12-1110.55" - wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o - attribute \src "ls180.v:1111.6-1111.50" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe - attribute \src "ls180.v:1102.5-1102.39" - wire \main_sdphy_cmdr_cmdr_pads_in_ready - attribute \src "ls180.v:1101.6-1101.40" - wire \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:1148.5-1148.31" - wire \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:1777.5-1777.59" - wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 - attribute \src "ls180.v:1778.5-1778.62" - wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:1118.5-1118.29" - wire \main_sdphy_cmdr_cmdr_run - attribute \src "ls180.v:1114.6-1114.47" - wire \main_sdphy_cmdr_cmdr_source_source_first0 - attribute \src "ls180.v:1135.6-1135.47" - wire \main_sdphy_cmdr_cmdr_source_source_first1 - attribute \src "ls180.v:1115.6-1115.46" - wire \main_sdphy_cmdr_cmdr_source_source_last0 - attribute \src "ls180.v:1136.6-1136.46" - wire \main_sdphy_cmdr_cmdr_source_source_last1 - attribute \src "ls180.v:1116.12-1116.60" - wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0 - attribute \src "ls180.v:1137.12-1137.60" - wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1 - attribute \src "ls180.v:1113.5-1113.46" - wire \main_sdphy_cmdr_cmdr_source_source_ready0 - attribute \src "ls180.v:1134.6-1134.47" - wire \main_sdphy_cmdr_cmdr_source_source_ready1 - attribute \src "ls180.v:1112.6-1112.47" - wire \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:1133.6-1133.47" - wire \main_sdphy_cmdr_cmdr_source_source_valid1 - attribute \src "ls180.v:1117.6-1117.32" - wire \main_sdphy_cmdr_cmdr_start - attribute \src "ls180.v:1100.11-1100.32" - wire width 8 \main_sdphy_cmdr_count - attribute \src "ls180.v:1773.11-1773.60" - wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 - attribute \src "ls180.v:1774.5-1774.57" - wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:1075.5-1075.42" - wire \main_sdphy_cmdr_pads_in_pads_in_first - attribute \src "ls180.v:1076.5-1076.41" - wire \main_sdphy_cmdr_pads_in_pads_in_last - attribute \src "ls180.v:1077.5-1077.48" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1078.6-1078.51" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1079.5-1079.50" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1080.5-1080.51" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1081.12-1081.58" - wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1082.11-1082.57" - wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1083.5-1083.52" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1074.6-1074.43" - wire \main_sdphy_cmdr_pads_in_pads_in_ready - attribute \src "ls180.v:1073.6-1073.43" - wire \main_sdphy_cmdr_pads_in_pads_in_valid - attribute \src "ls180.v:1085.5-1085.41" - wire \main_sdphy_cmdr_pads_out_payload_clk - attribute \src "ls180.v:1086.5-1086.43" - wire \main_sdphy_cmdr_pads_out_payload_cmd_o - attribute \src "ls180.v:1087.5-1087.44" - wire \main_sdphy_cmdr_pads_out_payload_cmd_oe - attribute \src "ls180.v:1088.11-1088.50" - wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o - attribute \src "ls180.v:1089.5-1089.45" - wire \main_sdphy_cmdr_pads_out_payload_data_oe - attribute \src "ls180.v:1084.6-1084.36" - wire \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:1092.5-1092.30" - wire \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:1093.11-1093.46" - wire width 8 \main_sdphy_cmdr_sink_payload_length - attribute \src "ls180.v:1091.5-1091.31" - wire \main_sdphy_cmdr_sink_ready - attribute \src "ls180.v:1090.5-1090.31" - wire \main_sdphy_cmdr_sink_valid - attribute \src "ls180.v:1096.5-1096.32" - wire \main_sdphy_cmdr_source_last - attribute \src "ls180.v:1097.11-1097.46" - wire width 8 \main_sdphy_cmdr_source_payload_data - attribute \src "ls180.v:1098.11-1098.48" - wire width 3 \main_sdphy_cmdr_source_payload_status - attribute \src "ls180.v:1095.5-1095.33" - wire \main_sdphy_cmdr_source_ready - attribute \src "ls180.v:1094.5-1094.33" - wire \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:1099.12-1099.35" - wire width 32 \main_sdphy_cmdr_timeout - attribute \src "ls180.v:1775.12-1775.63" - wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 - attribute \src "ls180.v:1776.5-1776.59" - wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:1072.11-1072.32" - wire width 8 \main_sdphy_cmdw_count - attribute \src "ls180.v:1769.11-1769.59" - wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value - attribute \src "ls180.v:1770.5-1770.56" - wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:1071.5-1071.25" - wire \main_sdphy_cmdw_done - attribute \src "ls180.v:1059.6-1059.43" - wire \main_sdphy_cmdw_pads_in_payload_cmd_i - attribute \src "ls180.v:1060.12-1060.50" - wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i - attribute \src "ls180.v:1058.6-1058.35" - wire \main_sdphy_cmdw_pads_in_valid - attribute \src "ls180.v:1062.5-1062.41" - wire \main_sdphy_cmdw_pads_out_payload_clk - attribute \src "ls180.v:1063.5-1063.43" - wire \main_sdphy_cmdw_pads_out_payload_cmd_o - attribute \src "ls180.v:1064.5-1064.44" - wire \main_sdphy_cmdw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1065.11-1065.50" - wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o - attribute \src "ls180.v:1066.5-1066.45" - wire \main_sdphy_cmdw_pads_out_payload_data_oe - attribute \src "ls180.v:1061.6-1061.36" - wire \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:1069.5-1069.30" - wire \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:1070.11-1070.44" - wire width 8 \main_sdphy_cmdw_sink_payload_data - attribute \src "ls180.v:1068.5-1068.31" - wire \main_sdphy_cmdw_sink_ready - attribute \src "ls180.v:1067.5-1067.31" - wire \main_sdphy_cmdw_sink_valid - attribute \src "ls180.v:1256.11-1256.33" - wire width 10 \main_sdphy_datar_count - attribute \src "ls180.v:1789.11-1789.62" - wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 - attribute \src "ls180.v:1790.5-1790.59" - wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:1296.6-1296.43" - wire \main_sdphy_datar_datar_buf_sink_first - attribute \src "ls180.v:1297.6-1297.42" - wire \main_sdphy_datar_datar_buf_sink_last - attribute \src "ls180.v:1298.12-1298.56" - wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data - attribute \src "ls180.v:1295.6-1295.43" - wire \main_sdphy_datar_datar_buf_sink_ready - attribute \src "ls180.v:1294.6-1294.43" - wire \main_sdphy_datar_datar_buf_sink_valid - attribute \src "ls180.v:1301.5-1301.44" - wire \main_sdphy_datar_datar_buf_source_first - attribute \src "ls180.v:1302.5-1302.43" - wire \main_sdphy_datar_datar_buf_source_last - attribute \src "ls180.v:1303.11-1303.57" - wire width 8 \main_sdphy_datar_datar_buf_source_payload_data - attribute \src "ls180.v:1300.6-1300.45" - wire \main_sdphy_datar_datar_buf_source_ready - attribute \src "ls180.v:1299.5-1299.44" - wire \main_sdphy_datar_datar_buf_source_valid - attribute \src "ls180.v:1286.5-1286.43" - wire \main_sdphy_datar_datar_converter_demux - attribute \src "ls180.v:1287.6-1287.48" - wire \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:1277.5-1277.48" - wire \main_sdphy_datar_datar_converter_sink_first - attribute \src "ls180.v:1278.5-1278.47" - wire \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:1279.12-1279.62" - wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data - attribute \src "ls180.v:1276.6-1276.49" - wire \main_sdphy_datar_datar_converter_sink_ready - attribute \src "ls180.v:1275.6-1275.49" - wire \main_sdphy_datar_datar_converter_sink_valid - attribute \src "ls180.v:1282.5-1282.50" - wire \main_sdphy_datar_datar_converter_source_first - attribute \src "ls180.v:1283.5-1283.49" - wire \main_sdphy_datar_datar_converter_source_last - attribute \src "ls180.v:1284.11-1284.63" - wire width 8 \main_sdphy_datar_datar_converter_source_payload_data - attribute \src "ls180.v:1285.11-1285.76" - wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count - attribute \src "ls180.v:1281.6-1281.51" - wire \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:1280.6-1280.51" - wire \main_sdphy_datar_datar_converter_source_valid - attribute \src "ls180.v:1288.5-1288.48" - wire \main_sdphy_datar_datar_converter_strobe_all - attribute \src "ls180.v:1259.6-1259.42" - wire \main_sdphy_datar_datar_pads_in_first - attribute \src "ls180.v:1260.6-1260.41" - wire \main_sdphy_datar_datar_pads_in_last - attribute \src "ls180.v:1261.6-1261.48" - wire \main_sdphy_datar_datar_pads_in_payload_clk - attribute \src "ls180.v:1262.6-1262.50" - wire \main_sdphy_datar_datar_pads_in_payload_cmd_i - attribute \src "ls180.v:1263.6-1263.50" - wire \main_sdphy_datar_datar_pads_in_payload_cmd_o - attribute \src "ls180.v:1264.6-1264.51" - wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe - attribute \src "ls180.v:1265.12-1265.57" - wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i - attribute \src "ls180.v:1266.12-1266.57" - wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o - attribute \src "ls180.v:1267.6-1267.52" - wire \main_sdphy_datar_datar_pads_in_payload_data_oe - attribute \src "ls180.v:1258.5-1258.41" - wire \main_sdphy_datar_datar_pads_in_ready - attribute \src "ls180.v:1257.6-1257.42" - wire \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:1304.5-1304.33" - wire \main_sdphy_datar_datar_reset - attribute \src "ls180.v:1793.5-1793.62" - wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 - attribute \src "ls180.v:1794.5-1794.65" - wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:1274.5-1274.31" - wire \main_sdphy_datar_datar_run - attribute \src "ls180.v:1270.6-1270.49" - wire \main_sdphy_datar_datar_source_source_first0 - attribute \src "ls180.v:1291.6-1291.49" - wire \main_sdphy_datar_datar_source_source_first1 - attribute \src "ls180.v:1271.6-1271.48" - wire \main_sdphy_datar_datar_source_source_last0 - attribute \src "ls180.v:1292.6-1292.48" - wire \main_sdphy_datar_datar_source_source_last1 - attribute \src "ls180.v:1272.12-1272.62" - wire width 8 \main_sdphy_datar_datar_source_source_payload_data0 - attribute \src "ls180.v:1293.12-1293.62" - wire width 8 \main_sdphy_datar_datar_source_source_payload_data1 - attribute \src "ls180.v:1269.5-1269.48" - wire \main_sdphy_datar_datar_source_source_ready0 - attribute \src "ls180.v:1290.6-1290.49" - wire \main_sdphy_datar_datar_source_source_ready1 - attribute \src "ls180.v:1268.6-1268.49" - wire \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:1289.6-1289.49" - wire \main_sdphy_datar_datar_source_source_valid1 - attribute \src "ls180.v:1273.6-1273.34" - wire \main_sdphy_datar_datar_start - attribute \src "ls180.v:1229.5-1229.43" - wire \main_sdphy_datar_pads_in_pads_in_first - attribute \src "ls180.v:1230.5-1230.42" - wire \main_sdphy_datar_pads_in_pads_in_last - attribute \src "ls180.v:1231.5-1231.49" - wire \main_sdphy_datar_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1232.6-1232.52" - wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1233.5-1233.51" - wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1234.5-1234.52" - wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1235.12-1235.59" - wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1236.11-1236.58" - wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1237.5-1237.53" - wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1228.6-1228.44" - wire \main_sdphy_datar_pads_in_pads_in_ready - attribute \src "ls180.v:1227.6-1227.44" - wire \main_sdphy_datar_pads_in_pads_in_valid - attribute \src "ls180.v:1239.5-1239.42" - wire \main_sdphy_datar_pads_out_payload_clk - attribute \src "ls180.v:1240.5-1240.44" - wire \main_sdphy_datar_pads_out_payload_cmd_o - attribute \src "ls180.v:1241.5-1241.45" - wire \main_sdphy_datar_pads_out_payload_cmd_oe - attribute \src "ls180.v:1242.11-1242.51" - wire width 4 \main_sdphy_datar_pads_out_payload_data_o - attribute \src "ls180.v:1243.5-1243.46" - wire \main_sdphy_datar_pads_out_payload_data_oe - attribute \src "ls180.v:1238.6-1238.37" - wire \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:1246.5-1246.31" - wire \main_sdphy_datar_sink_last - attribute \src "ls180.v:1247.11-1247.53" - wire width 10 \main_sdphy_datar_sink_payload_block_length - attribute \src "ls180.v:1245.5-1245.32" - wire \main_sdphy_datar_sink_ready - attribute \src "ls180.v:1244.5-1244.32" - wire \main_sdphy_datar_sink_valid - attribute \src "ls180.v:1250.5-1250.34" - wire \main_sdphy_datar_source_first - attribute \src "ls180.v:1251.5-1251.33" - wire \main_sdphy_datar_source_last - attribute \src "ls180.v:1252.11-1252.47" - wire width 8 \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:1253.11-1253.49" - wire width 3 \main_sdphy_datar_source_payload_status - attribute \src "ls180.v:1249.5-1249.34" - wire \main_sdphy_datar_source_ready - attribute \src "ls180.v:1248.5-1248.34" - wire \main_sdphy_datar_source_valid - attribute \src "ls180.v:1254.5-1254.26" - wire \main_sdphy_datar_stop - attribute \src "ls180.v:1255.12-1255.36" - wire width 32 \main_sdphy_datar_timeout - attribute \src "ls180.v:1791.12-1791.65" - wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 - attribute \src "ls180.v:1792.5-1792.61" - wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:1164.11-1164.33" - wire width 8 \main_sdphy_dataw_count - attribute \src "ls180.v:1785.11-1785.54" - wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value - attribute \src "ls180.v:1786.5-1786.51" - wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:1218.6-1218.42" - wire \main_sdphy_dataw_crcr_buf_sink_first - attribute \src "ls180.v:1219.6-1219.41" - wire \main_sdphy_dataw_crcr_buf_sink_last - attribute \src "ls180.v:1220.12-1220.55" - wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data - attribute \src "ls180.v:1217.6-1217.42" - wire \main_sdphy_dataw_crcr_buf_sink_ready - attribute \src "ls180.v:1216.6-1216.42" - wire \main_sdphy_dataw_crcr_buf_sink_valid - attribute \src "ls180.v:1223.5-1223.43" - wire \main_sdphy_dataw_crcr_buf_source_first - attribute \src "ls180.v:1224.5-1224.42" - wire \main_sdphy_dataw_crcr_buf_source_last - attribute \src "ls180.v:1225.11-1225.56" - wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data - attribute \src "ls180.v:1222.6-1222.44" - wire \main_sdphy_dataw_crcr_buf_source_ready - attribute \src "ls180.v:1221.5-1221.43" - wire \main_sdphy_dataw_crcr_buf_source_valid - attribute \src "ls180.v:1208.11-1208.48" - wire width 3 \main_sdphy_dataw_crcr_converter_demux - attribute \src "ls180.v:1209.6-1209.47" - wire \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:1199.5-1199.47" - wire \main_sdphy_dataw_crcr_converter_sink_first - attribute \src "ls180.v:1200.5-1200.46" - wire \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:1201.6-1201.55" - wire \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:1198.6-1198.48" - wire \main_sdphy_dataw_crcr_converter_sink_ready - attribute \src "ls180.v:1197.6-1197.48" - wire \main_sdphy_dataw_crcr_converter_sink_valid - attribute \src "ls180.v:1204.5-1204.49" - wire \main_sdphy_dataw_crcr_converter_source_first - attribute \src "ls180.v:1205.5-1205.48" - wire \main_sdphy_dataw_crcr_converter_source_last - attribute \src "ls180.v:1206.11-1206.62" - wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data - attribute \src "ls180.v:1207.11-1207.75" - wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1203.6-1203.50" - wire \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:1202.6-1202.50" - wire \main_sdphy_dataw_crcr_converter_source_valid - attribute \src "ls180.v:1210.5-1210.47" - wire \main_sdphy_dataw_crcr_converter_strobe_all - attribute \src "ls180.v:1181.6-1181.41" - wire \main_sdphy_dataw_crcr_pads_in_first - attribute \src "ls180.v:1182.6-1182.40" - wire \main_sdphy_dataw_crcr_pads_in_last - attribute \src "ls180.v:1183.6-1183.47" - wire \main_sdphy_dataw_crcr_pads_in_payload_clk - attribute \src "ls180.v:1184.6-1184.49" - wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i - attribute \src "ls180.v:1185.6-1185.49" - wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o - attribute \src "ls180.v:1186.6-1186.50" - wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1187.12-1187.56" - wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i - attribute \src "ls180.v:1188.12-1188.56" - wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o - attribute \src "ls180.v:1189.6-1189.51" - wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe - attribute \src "ls180.v:1180.5-1180.40" - wire \main_sdphy_dataw_crcr_pads_in_ready - attribute \src "ls180.v:1179.6-1179.41" - wire \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:1226.5-1226.32" - wire \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:1781.5-1781.59" - wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value - attribute \src "ls180.v:1782.5-1782.62" - wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:1196.5-1196.30" - wire \main_sdphy_dataw_crcr_run - attribute \src "ls180.v:1192.6-1192.48" - wire \main_sdphy_dataw_crcr_source_source_first0 - attribute \src "ls180.v:1213.6-1213.48" - wire \main_sdphy_dataw_crcr_source_source_first1 - attribute \src "ls180.v:1193.6-1193.47" - wire \main_sdphy_dataw_crcr_source_source_last0 - attribute \src "ls180.v:1214.6-1214.47" - wire \main_sdphy_dataw_crcr_source_source_last1 - attribute \src "ls180.v:1194.12-1194.61" - wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0 - attribute \src "ls180.v:1215.12-1215.61" - wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1 - attribute \src "ls180.v:1191.5-1191.47" - wire \main_sdphy_dataw_crcr_source_source_ready0 - attribute \src "ls180.v:1212.6-1212.48" - wire \main_sdphy_dataw_crcr_source_source_ready1 - attribute \src "ls180.v:1190.6-1190.48" - wire \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:1211.6-1211.48" - wire \main_sdphy_dataw_crcr_source_source_valid1 - attribute \src "ls180.v:1195.6-1195.33" - wire \main_sdphy_dataw_crcr_start - attribute \src "ls180.v:1178.5-1178.27" - wire \main_sdphy_dataw_error - attribute \src "ls180.v:1167.5-1167.43" - wire \main_sdphy_dataw_pads_in_pads_in_first - attribute \src "ls180.v:1168.5-1168.42" - wire \main_sdphy_dataw_pads_in_pads_in_last - attribute \src "ls180.v:1169.5-1169.49" - wire \main_sdphy_dataw_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1170.5-1170.51" - wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1171.5-1171.51" - wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1172.5-1172.52" - wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1173.11-1173.58" - wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1174.11-1174.58" - wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1175.5-1175.53" - wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1166.6-1166.44" - wire \main_sdphy_dataw_pads_in_pads_in_ready - attribute \src "ls180.v:1165.5-1165.43" - wire \main_sdphy_dataw_pads_in_pads_in_valid - attribute \src "ls180.v:1150.6-1150.44" - wire \main_sdphy_dataw_pads_in_payload_cmd_i - attribute \src "ls180.v:1151.12-1151.51" - wire width 4 \main_sdphy_dataw_pads_in_payload_data_i - attribute \src "ls180.v:1149.6-1149.36" - wire \main_sdphy_dataw_pads_in_valid - attribute \src "ls180.v:1153.5-1153.42" - wire \main_sdphy_dataw_pads_out_payload_clk - attribute \src "ls180.v:1154.5-1154.44" - wire \main_sdphy_dataw_pads_out_payload_cmd_o - attribute \src "ls180.v:1155.5-1155.45" - wire \main_sdphy_dataw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1156.11-1156.51" - wire width 4 \main_sdphy_dataw_pads_out_payload_data_o - attribute \src "ls180.v:1157.5-1157.46" - wire \main_sdphy_dataw_pads_out_payload_data_oe - attribute \src "ls180.v:1152.6-1152.37" - wire \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:1160.5-1160.32" - wire \main_sdphy_dataw_sink_first - attribute \src "ls180.v:1161.5-1161.31" - wire \main_sdphy_dataw_sink_last - attribute \src "ls180.v:1162.11-1162.45" - wire width 8 \main_sdphy_dataw_sink_payload_data - attribute \src "ls180.v:1159.5-1159.32" - wire \main_sdphy_dataw_sink_ready - attribute \src "ls180.v:1158.5-1158.32" - wire \main_sdphy_dataw_sink_valid - attribute \src "ls180.v:1176.5-1176.27" - wire \main_sdphy_dataw_start - attribute \src "ls180.v:1163.5-1163.26" - wire \main_sdphy_dataw_stop - attribute \src "ls180.v:1177.5-1177.27" - wire \main_sdphy_dataw_valid - attribute \src "ls180.v:1057.11-1057.32" - wire width 8 \main_sdphy_init_count - attribute \src "ls180.v:1765.11-1765.59" - wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value - attribute \src "ls180.v:1766.5-1766.56" - wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:1045.6-1045.34" - wire \main_sdphy_init_initialize_r - attribute \src "ls180.v:1044.6-1044.35" - wire \main_sdphy_init_initialize_re - attribute \src "ls180.v:1047.5-1047.33" - wire \main_sdphy_init_initialize_w - attribute \src "ls180.v:1046.6-1046.35" - wire \main_sdphy_init_initialize_we - attribute \src "ls180.v:1049.6-1049.43" - wire \main_sdphy_init_pads_in_payload_cmd_i - attribute \src "ls180.v:1050.12-1050.50" - wire width 4 \main_sdphy_init_pads_in_payload_data_i - attribute \src "ls180.v:1048.6-1048.35" - wire \main_sdphy_init_pads_in_valid - attribute \src "ls180.v:1052.5-1052.41" - wire \main_sdphy_init_pads_out_payload_clk - attribute \src "ls180.v:1053.5-1053.43" - wire \main_sdphy_init_pads_out_payload_cmd_o - attribute \src "ls180.v:1054.5-1054.44" - wire \main_sdphy_init_pads_out_payload_cmd_oe - attribute \src "ls180.v:1055.11-1055.50" - wire width 4 \main_sdphy_init_pads_out_payload_data_o - attribute \src "ls180.v:1056.5-1056.45" - wire \main_sdphy_init_pads_out_payload_data_oe - attribute \src "ls180.v:1051.6-1051.36" - wire \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:1305.6-1305.27" - wire \main_sdphy_sdpads_clk - attribute \src "ls180.v:1306.5-1306.28" - wire \main_sdphy_sdpads_cmd_i - attribute \src "ls180.v:1307.6-1307.29" - wire \main_sdphy_sdpads_cmd_o - attribute \src "ls180.v:1308.6-1308.30" - wire \main_sdphy_sdpads_cmd_oe - attribute \src "ls180.v:1309.11-1309.35" - wire width 4 \main_sdphy_sdpads_data_i - attribute \src "ls180.v:1310.12-1310.36" - wire width 4 \main_sdphy_sdpads_data_o - attribute \src "ls180.v:1311.6-1311.31" - wire \main_sdphy_sdpads_data_oe - attribute \src "ls180.v:1034.6-1034.23" - wire \main_sdphy_status - attribute \src "ls180.v:1035.6-1035.19" - wire \main_sdphy_we - attribute \src "ls180.v:307.5-307.26" - wire \main_sdram_address_re - attribute \src "ls180.v:306.12-306.38" - wire width 13 \main_sdram_address_storage - attribute \src "ls180.v:309.5-309.27" - wire \main_sdram_baddress_re - attribute \src "ls180.v:308.11-308.38" - wire width 2 \main_sdram_baddress_storage - attribute \src "ls180.v:405.5-405.43" - wire \main_sdram_bankmachine0_auto_precharge - attribute \src "ls180.v:427.11-427.63" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - attribute \src "ls180.v:432.6-432.58" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:437.6-437.64" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:438.6-438.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:436.13-436.78" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:435.6-435.69" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:441.6-441.65" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:442.6-442.64" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:440.13-440.79" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:439.6-439.70" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:424.11-424.61" - wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level - attribute \src "ls180.v:426.11-426.63" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - attribute \src "ls180.v:433.12-433.67" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:434.13-434.70" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:425.5-425.57" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:408.5-408.60" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:409.5-409.59" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:411.13-411.75" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:410.6-410.66" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:407.6-407.61" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:406.6-406.61" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:414.6-414.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:415.6-415.62" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:417.13-417.77" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:416.6-416.68" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:413.6-413.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:412.6-412.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:422.13-422.71" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - attribute \src "ls180.v:423.13-423.72" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout - attribute \src "ls180.v:420.6-420.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - attribute \src "ls180.v:421.6-421.69" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - attribute \src "ls180.v:418.6-418.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - attribute \src "ls180.v:419.6-419.69" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - attribute \src "ls180.v:428.11-428.66" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:429.13-429.70" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:431.13-431.70" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:430.6-430.60" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:445.6-445.51" - wire \main_sdram_bankmachine0_cmd_buffer_sink_first - attribute \src "ls180.v:446.6-446.50" - wire \main_sdram_bankmachine0_cmd_buffer_sink_last - attribute \src "ls180.v:448.13-448.65" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:447.6-447.56" - wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we - attribute \src "ls180.v:444.6-444.51" - wire \main_sdram_bankmachine0_cmd_buffer_sink_ready - attribute \src "ls180.v:443.6-443.51" - wire \main_sdram_bankmachine0_cmd_buffer_sink_valid - attribute \src "ls180.v:451.5-451.52" - wire \main_sdram_bankmachine0_cmd_buffer_source_first - attribute \src "ls180.v:452.5-452.51" - wire \main_sdram_bankmachine0_cmd_buffer_source_last - attribute \src "ls180.v:454.12-454.66" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr - attribute \src "ls180.v:453.5-453.57" - wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:450.6-450.53" - wire \main_sdram_bankmachine0_cmd_buffer_source_ready - attribute \src "ls180.v:449.5-449.52" - wire \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:397.12-397.49" - wire width 13 \main_sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:398.12-398.50" - wire width 2 \main_sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:399.5-399.44" - wire \main_sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:402.5-402.47" - wire \main_sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:403.5-403.48" - wire \main_sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:404.5-404.49" - wire \main_sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:400.5-400.44" - wire \main_sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:401.5-401.43" - wire \main_sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:396.5-396.38" - wire \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:395.5-395.38" - wire \main_sdram_bankmachine0_cmd_valid - attribute \src "ls180.v:394.5-394.40" - wire \main_sdram_bankmachine0_refresh_gnt - attribute \src "ls180.v:393.6-393.41" - wire \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:389.13-389.45" - wire width 22 \main_sdram_bankmachine0_req_addr - attribute \src "ls180.v:390.6-390.38" - wire \main_sdram_bankmachine0_req_lock - attribute \src "ls180.v:392.5-392.44" - wire \main_sdram_bankmachine0_req_rdata_valid - attribute \src "ls180.v:387.6-387.39" - wire \main_sdram_bankmachine0_req_ready - attribute \src "ls180.v:386.6-386.39" - wire \main_sdram_bankmachine0_req_valid - attribute \src "ls180.v:391.5-391.44" - wire \main_sdram_bankmachine0_req_wdata_ready - attribute \src "ls180.v:388.6-388.36" - wire \main_sdram_bankmachine0_req_we - attribute \src "ls180.v:455.12-455.39" - wire width 13 \main_sdram_bankmachine0_row - attribute \src "ls180.v:459.5-459.38" - wire \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:460.5-460.47" - wire \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:457.6-457.37" - wire \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:458.5-458.37" - wire \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:456.5-456.39" - wire \main_sdram_bankmachine0_row_opened - attribute \no_retiming "true" - attribute \src "ls180.v:467.32-467.69" - wire \main_sdram_bankmachine0_trascon_ready - attribute \src "ls180.v:466.6-466.43" - wire \main_sdram_bankmachine0_trascon_valid - attribute \no_retiming "true" - attribute \src "ls180.v:465.32-465.68" - wire \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:464.6-464.42" - wire \main_sdram_bankmachine0_trccon_valid - attribute \src "ls180.v:463.11-463.48" - wire width 3 \main_sdram_bankmachine0_twtpcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:462.32-462.69" - wire \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:461.6-461.43" - wire \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:487.5-487.43" - wire \main_sdram_bankmachine1_auto_precharge - attribute \src "ls180.v:509.11-509.63" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - attribute \src "ls180.v:514.6-514.58" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:519.6-519.64" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:520.6-520.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:518.13-518.78" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:517.6-517.69" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:523.6-523.65" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:524.6-524.64" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:522.13-522.79" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:521.6-521.70" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:506.11-506.61" - wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level - attribute \src "ls180.v:508.11-508.63" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - attribute \src "ls180.v:515.12-515.67" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:516.13-516.70" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:507.5-507.57" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:490.5-490.60" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:491.5-491.59" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:493.13-493.75" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:492.6-492.66" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:489.6-489.61" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:488.6-488.61" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:496.6-496.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:497.6-497.62" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:499.13-499.77" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:498.6-498.68" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:495.6-495.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:494.6-494.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:504.13-504.71" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - attribute \src "ls180.v:505.13-505.72" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout - attribute \src "ls180.v:502.6-502.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - attribute \src "ls180.v:503.6-503.69" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - attribute \src "ls180.v:500.6-500.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - attribute \src "ls180.v:501.6-501.69" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - attribute \src "ls180.v:510.11-510.66" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:511.13-511.70" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:513.13-513.70" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:512.6-512.60" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:527.6-527.51" - wire \main_sdram_bankmachine1_cmd_buffer_sink_first - attribute \src "ls180.v:528.6-528.50" - wire \main_sdram_bankmachine1_cmd_buffer_sink_last - attribute \src "ls180.v:530.13-530.65" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:529.6-529.56" - wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we - attribute \src "ls180.v:526.6-526.51" - wire \main_sdram_bankmachine1_cmd_buffer_sink_ready - attribute \src "ls180.v:525.6-525.51" - wire \main_sdram_bankmachine1_cmd_buffer_sink_valid - attribute \src "ls180.v:533.5-533.52" - wire \main_sdram_bankmachine1_cmd_buffer_source_first - attribute \src "ls180.v:534.5-534.51" - wire \main_sdram_bankmachine1_cmd_buffer_source_last - attribute \src "ls180.v:536.12-536.66" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr - attribute \src "ls180.v:535.5-535.57" - wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:532.6-532.53" - wire \main_sdram_bankmachine1_cmd_buffer_source_ready - attribute \src "ls180.v:531.5-531.52" - wire \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:479.12-479.49" - wire width 13 \main_sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:480.12-480.50" - wire width 2 \main_sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:481.5-481.44" - wire \main_sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:484.5-484.47" - wire \main_sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:485.5-485.48" - wire \main_sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:486.5-486.49" - wire \main_sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:482.5-482.44" - wire \main_sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:483.5-483.43" - wire \main_sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:478.5-478.38" - wire \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:477.5-477.38" - wire \main_sdram_bankmachine1_cmd_valid - attribute \src "ls180.v:476.5-476.40" - wire \main_sdram_bankmachine1_refresh_gnt - attribute \src "ls180.v:475.6-475.41" - wire \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:471.13-471.45" - wire width 22 \main_sdram_bankmachine1_req_addr - attribute \src "ls180.v:472.6-472.38" - wire \main_sdram_bankmachine1_req_lock - attribute \src "ls180.v:474.5-474.44" - wire \main_sdram_bankmachine1_req_rdata_valid - attribute \src "ls180.v:469.6-469.39" - wire \main_sdram_bankmachine1_req_ready - attribute \src "ls180.v:468.6-468.39" - wire \main_sdram_bankmachine1_req_valid - attribute \src "ls180.v:473.5-473.44" - wire \main_sdram_bankmachine1_req_wdata_ready - attribute \src "ls180.v:470.6-470.36" - wire \main_sdram_bankmachine1_req_we - attribute \src "ls180.v:537.12-537.39" - wire width 13 \main_sdram_bankmachine1_row - attribute \src "ls180.v:541.5-541.38" - wire \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:542.5-542.47" - wire \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:539.6-539.37" - wire \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:540.5-540.37" - wire \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:538.5-538.39" - wire \main_sdram_bankmachine1_row_opened - attribute \no_retiming "true" - attribute \src "ls180.v:549.32-549.69" - wire \main_sdram_bankmachine1_trascon_ready - attribute \src "ls180.v:548.6-548.43" - wire \main_sdram_bankmachine1_trascon_valid - attribute \no_retiming "true" - attribute \src "ls180.v:547.32-547.68" - wire \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:546.6-546.42" - wire \main_sdram_bankmachine1_trccon_valid - attribute \src "ls180.v:545.11-545.48" - wire width 3 \main_sdram_bankmachine1_twtpcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:544.32-544.69" - wire \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:543.6-543.43" - wire \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:569.5-569.43" - wire \main_sdram_bankmachine2_auto_precharge - attribute \src "ls180.v:591.11-591.63" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - attribute \src "ls180.v:596.6-596.58" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:601.6-601.64" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:602.6-602.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:600.13-600.78" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:599.6-599.69" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:605.6-605.65" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:606.6-606.64" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:604.13-604.79" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:603.6-603.70" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:588.11-588.61" - wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level - attribute \src "ls180.v:590.11-590.63" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - attribute \src "ls180.v:597.12-597.67" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:598.13-598.70" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:589.5-589.57" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:572.5-572.60" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:573.5-573.59" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:575.13-575.75" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:574.6-574.66" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:571.6-571.61" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:570.6-570.61" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:578.6-578.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:579.6-579.62" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:581.13-581.77" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:580.6-580.68" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:577.6-577.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:576.6-576.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:586.13-586.71" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - attribute \src "ls180.v:587.13-587.72" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout - attribute \src "ls180.v:584.6-584.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - attribute \src "ls180.v:585.6-585.69" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - attribute \src "ls180.v:582.6-582.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - attribute \src "ls180.v:583.6-583.69" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - attribute \src "ls180.v:592.11-592.66" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:593.13-593.70" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:595.13-595.70" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:594.6-594.60" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:609.6-609.51" - wire \main_sdram_bankmachine2_cmd_buffer_sink_first - attribute \src "ls180.v:610.6-610.50" - wire \main_sdram_bankmachine2_cmd_buffer_sink_last - attribute \src "ls180.v:612.13-612.65" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:611.6-611.56" - wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we - attribute \src "ls180.v:608.6-608.51" - wire \main_sdram_bankmachine2_cmd_buffer_sink_ready - attribute \src "ls180.v:607.6-607.51" - wire \main_sdram_bankmachine2_cmd_buffer_sink_valid - attribute \src "ls180.v:615.5-615.52" - wire \main_sdram_bankmachine2_cmd_buffer_source_first - attribute \src "ls180.v:616.5-616.51" - wire \main_sdram_bankmachine2_cmd_buffer_source_last - attribute \src "ls180.v:618.12-618.66" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr - attribute \src "ls180.v:617.5-617.57" - wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:614.6-614.53" - wire \main_sdram_bankmachine2_cmd_buffer_source_ready - attribute \src "ls180.v:613.5-613.52" - wire \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:561.12-561.49" - wire width 13 \main_sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:562.12-562.50" - wire width 2 \main_sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:563.5-563.44" - wire \main_sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:566.5-566.47" - wire \main_sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:567.5-567.48" - wire \main_sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:568.5-568.49" - wire \main_sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:564.5-564.44" - wire \main_sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:565.5-565.43" - wire \main_sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:560.5-560.38" - wire \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:559.5-559.38" - wire \main_sdram_bankmachine2_cmd_valid - attribute \src "ls180.v:558.5-558.40" - wire \main_sdram_bankmachine2_refresh_gnt - attribute \src "ls180.v:557.6-557.41" - wire \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:553.13-553.45" - wire width 22 \main_sdram_bankmachine2_req_addr - attribute \src "ls180.v:554.6-554.38" - wire \main_sdram_bankmachine2_req_lock - attribute \src "ls180.v:556.5-556.44" - wire \main_sdram_bankmachine2_req_rdata_valid - attribute \src "ls180.v:551.6-551.39" - wire \main_sdram_bankmachine2_req_ready - attribute \src "ls180.v:550.6-550.39" - wire \main_sdram_bankmachine2_req_valid - attribute \src "ls180.v:555.5-555.44" - wire \main_sdram_bankmachine2_req_wdata_ready - attribute \src "ls180.v:552.6-552.36" - wire \main_sdram_bankmachine2_req_we - attribute \src "ls180.v:619.12-619.39" - wire width 13 \main_sdram_bankmachine2_row - attribute \src "ls180.v:623.5-623.38" - wire \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:624.5-624.47" - wire \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:621.6-621.37" - wire \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:622.5-622.37" - wire \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:620.5-620.39" - wire \main_sdram_bankmachine2_row_opened - attribute \no_retiming "true" - attribute \src "ls180.v:631.32-631.69" - wire \main_sdram_bankmachine2_trascon_ready - attribute \src "ls180.v:630.6-630.43" - wire \main_sdram_bankmachine2_trascon_valid - attribute \no_retiming "true" - attribute \src "ls180.v:629.32-629.68" - wire \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:628.6-628.42" - wire \main_sdram_bankmachine2_trccon_valid - attribute \src "ls180.v:627.11-627.48" - wire width 3 \main_sdram_bankmachine2_twtpcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:626.32-626.69" - wire \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:625.6-625.43" - wire \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:651.5-651.43" - wire \main_sdram_bankmachine3_auto_precharge - attribute \src "ls180.v:673.11-673.63" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - attribute \src "ls180.v:678.6-678.58" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:683.6-683.64" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:684.6-684.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:682.13-682.78" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:681.6-681.69" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:687.6-687.65" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:688.6-688.64" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:686.13-686.79" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:685.6-685.70" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:670.11-670.61" - wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level - attribute \src "ls180.v:672.11-672.63" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - attribute \src "ls180.v:679.12-679.67" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:680.13-680.70" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:671.5-671.57" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:654.5-654.60" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:655.5-655.59" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:657.13-657.75" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:656.6-656.66" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:653.6-653.61" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:652.6-652.61" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:660.6-660.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:661.6-661.62" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:663.13-663.77" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:662.6-662.68" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:659.6-659.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:658.6-658.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:668.13-668.71" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - attribute \src "ls180.v:669.13-669.72" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout - attribute \src "ls180.v:666.6-666.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - attribute \src "ls180.v:667.6-667.69" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - attribute \src "ls180.v:664.6-664.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - attribute \src "ls180.v:665.6-665.69" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - attribute \src "ls180.v:674.11-674.66" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:675.13-675.70" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:677.13-677.70" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:676.6-676.60" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:691.6-691.51" - wire \main_sdram_bankmachine3_cmd_buffer_sink_first - attribute \src "ls180.v:692.6-692.50" - wire \main_sdram_bankmachine3_cmd_buffer_sink_last - attribute \src "ls180.v:694.13-694.65" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:693.6-693.56" - wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we - attribute \src "ls180.v:690.6-690.51" - wire \main_sdram_bankmachine3_cmd_buffer_sink_ready - attribute \src "ls180.v:689.6-689.51" - wire \main_sdram_bankmachine3_cmd_buffer_sink_valid - attribute \src "ls180.v:697.5-697.52" - wire \main_sdram_bankmachine3_cmd_buffer_source_first - attribute \src "ls180.v:698.5-698.51" - wire \main_sdram_bankmachine3_cmd_buffer_source_last - attribute \src "ls180.v:700.12-700.66" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr - attribute \src "ls180.v:699.5-699.57" - wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:696.6-696.53" - wire \main_sdram_bankmachine3_cmd_buffer_source_ready - attribute \src "ls180.v:695.5-695.52" - wire \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:643.12-643.49" - wire width 13 \main_sdram_bankmachine3_cmd_payload_a - attribute \src "ls180.v:644.12-644.50" - wire width 2 \main_sdram_bankmachine3_cmd_payload_ba - attribute \src "ls180.v:645.5-645.44" - wire \main_sdram_bankmachine3_cmd_payload_cas - attribute \src "ls180.v:648.5-648.47" - wire \main_sdram_bankmachine3_cmd_payload_is_cmd - attribute \src "ls180.v:649.5-649.48" - wire \main_sdram_bankmachine3_cmd_payload_is_read - attribute \src "ls180.v:650.5-650.49" - wire \main_sdram_bankmachine3_cmd_payload_is_write - attribute \src "ls180.v:646.5-646.44" - wire \main_sdram_bankmachine3_cmd_payload_ras - attribute \src "ls180.v:647.5-647.43" - wire \main_sdram_bankmachine3_cmd_payload_we - attribute \src "ls180.v:642.5-642.38" - wire \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:641.5-641.38" - wire \main_sdram_bankmachine3_cmd_valid - attribute \src "ls180.v:640.5-640.40" - wire \main_sdram_bankmachine3_refresh_gnt - attribute \src "ls180.v:639.6-639.41" - wire \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:635.13-635.45" - wire width 22 \main_sdram_bankmachine3_req_addr - attribute \src "ls180.v:636.6-636.38" - wire \main_sdram_bankmachine3_req_lock - attribute \src "ls180.v:638.5-638.44" - wire \main_sdram_bankmachine3_req_rdata_valid - attribute \src "ls180.v:633.6-633.39" - wire \main_sdram_bankmachine3_req_ready - attribute \src "ls180.v:632.6-632.39" - wire \main_sdram_bankmachine3_req_valid - attribute \src "ls180.v:637.5-637.44" - wire \main_sdram_bankmachine3_req_wdata_ready - attribute \src "ls180.v:634.6-634.36" - wire \main_sdram_bankmachine3_req_we - attribute \src "ls180.v:701.12-701.39" - wire width 13 \main_sdram_bankmachine3_row - attribute \src "ls180.v:705.5-705.38" - wire \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:706.5-706.47" - wire \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:703.6-703.37" - wire \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:704.5-704.37" - wire \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:702.5-702.39" - wire \main_sdram_bankmachine3_row_opened - attribute \no_retiming "true" - attribute \src "ls180.v:713.32-713.69" - wire \main_sdram_bankmachine3_trascon_ready - attribute \src "ls180.v:712.6-712.43" - wire \main_sdram_bankmachine3_trascon_valid - attribute \no_retiming "true" - attribute \src "ls180.v:711.32-711.68" - wire \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:710.6-710.42" - wire \main_sdram_bankmachine3_trccon_valid - attribute \src "ls180.v:709.11-709.48" - wire width 3 \main_sdram_bankmachine3_twtpcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:708.32-708.69" - wire \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:707.6-707.43" - wire \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:715.6-715.28" - wire \main_sdram_cas_allowed - attribute \src "ls180.v:733.6-733.30" - wire \main_sdram_choose_cmd_ce - attribute \src "ls180.v:722.13-722.48" - wire width 13 \main_sdram_choose_cmd_cmd_payload_a - attribute \src "ls180.v:723.12-723.48" - wire width 2 \main_sdram_choose_cmd_cmd_payload_ba - attribute \src "ls180.v:724.5-724.42" - wire \main_sdram_choose_cmd_cmd_payload_cas - attribute \src "ls180.v:727.6-727.46" - wire \main_sdram_choose_cmd_cmd_payload_is_cmd - attribute \src "ls180.v:728.6-728.47" - wire \main_sdram_choose_cmd_cmd_payload_is_read - attribute \src "ls180.v:729.6-729.48" - wire \main_sdram_choose_cmd_cmd_payload_is_write - attribute \src "ls180.v:725.5-725.42" - wire \main_sdram_choose_cmd_cmd_payload_ras - attribute \src "ls180.v:726.5-726.41" - wire \main_sdram_choose_cmd_cmd_payload_we - attribute \src "ls180.v:721.5-721.36" - wire \main_sdram_choose_cmd_cmd_ready - attribute \src "ls180.v:720.6-720.37" - wire \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:732.11-732.38" - wire width 2 \main_sdram_choose_cmd_grant - attribute \src "ls180.v:731.12-731.41" - wire width 4 \main_sdram_choose_cmd_request - attribute \src "ls180.v:730.11-730.39" - wire width 4 \main_sdram_choose_cmd_valids - attribute \src "ls180.v:719.5-719.41" - wire \main_sdram_choose_cmd_want_activates - attribute \src "ls180.v:718.5-718.36" - wire \main_sdram_choose_cmd_want_cmds - attribute \src "ls180.v:716.5-716.37" - wire \main_sdram_choose_cmd_want_reads - attribute \src "ls180.v:717.5-717.38" - wire \main_sdram_choose_cmd_want_writes - attribute \src "ls180.v:751.6-751.30" - wire \main_sdram_choose_req_ce - attribute \src "ls180.v:740.13-740.48" - wire width 13 \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:741.12-741.48" - wire width 2 \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:742.5-742.42" - wire \main_sdram_choose_req_cmd_payload_cas - attribute \src "ls180.v:745.6-745.46" - wire \main_sdram_choose_req_cmd_payload_is_cmd - attribute \src "ls180.v:746.6-746.47" - wire \main_sdram_choose_req_cmd_payload_is_read - attribute \src "ls180.v:747.6-747.48" - wire \main_sdram_choose_req_cmd_payload_is_write - attribute \src "ls180.v:743.5-743.42" - wire \main_sdram_choose_req_cmd_payload_ras - attribute \src "ls180.v:744.5-744.41" - wire \main_sdram_choose_req_cmd_payload_we - attribute \src "ls180.v:739.5-739.36" - wire \main_sdram_choose_req_cmd_ready - attribute \src "ls180.v:738.6-738.37" - wire \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:750.11-750.38" - wire width 2 \main_sdram_choose_req_grant - attribute \src "ls180.v:749.12-749.41" - wire width 4 \main_sdram_choose_req_request - attribute \src "ls180.v:748.11-748.39" - wire width 4 \main_sdram_choose_req_valids - attribute \src "ls180.v:737.5-737.41" - wire \main_sdram_choose_req_want_activates - attribute \src "ls180.v:736.6-736.37" - wire \main_sdram_choose_req_want_cmds - attribute \src "ls180.v:734.5-734.37" - wire \main_sdram_choose_req_want_reads - attribute \src "ls180.v:735.5-735.38" - wire \main_sdram_choose_req_want_writes - attribute \src "ls180.v:295.6-295.20" - wire \main_sdram_cke - attribute \src "ls180.v:363.5-363.24" - wire \main_sdram_cmd_last - attribute \src "ls180.v:364.12-364.36" - wire width 13 \main_sdram_cmd_payload_a - attribute \src "ls180.v:365.11-365.36" - wire width 2 \main_sdram_cmd_payload_ba - attribute \src "ls180.v:366.5-366.31" - wire \main_sdram_cmd_payload_cas - attribute \src "ls180.v:369.5-369.35" - wire \main_sdram_cmd_payload_is_read - attribute \src "ls180.v:370.5-370.36" - wire \main_sdram_cmd_payload_is_write - attribute \src "ls180.v:367.5-367.31" - wire \main_sdram_cmd_payload_ras - attribute \src "ls180.v:368.5-368.30" - wire \main_sdram_cmd_payload_we - attribute \src "ls180.v:362.5-362.25" - wire \main_sdram_cmd_ready - attribute \src "ls180.v:361.5-361.25" - wire \main_sdram_cmd_valid - attribute \src "ls180.v:303.6-303.32" - wire \main_sdram_command_issue_r - attribute \src "ls180.v:302.6-302.33" - wire \main_sdram_command_issue_re - attribute \src "ls180.v:305.5-305.31" - wire \main_sdram_command_issue_w - attribute \src "ls180.v:304.6-304.33" - wire \main_sdram_command_issue_we - attribute \src "ls180.v:301.5-301.26" - wire \main_sdram_command_re - attribute \src "ls180.v:300.11-300.37" - wire width 6 \main_sdram_command_storage - attribute \src "ls180.v:354.5-354.28" - wire \main_sdram_dfi_p0_act_n - attribute \src "ls180.v:345.12-345.37" - wire width 13 \main_sdram_dfi_p0_address - attribute \src "ls180.v:346.11-346.33" - wire width 2 \main_sdram_dfi_p0_bank - attribute \src "ls180.v:347.5-347.28" - wire \main_sdram_dfi_p0_cas_n - attribute \src "ls180.v:351.6-351.27" - wire \main_sdram_dfi_p0_cke - attribute \src "ls180.v:348.5-348.27" - wire \main_sdram_dfi_p0_cs_n - attribute \src "ls180.v:352.6-352.27" - wire \main_sdram_dfi_p0_odt - attribute \src "ls180.v:349.5-349.28" - wire \main_sdram_dfi_p0_ras_n - attribute \src "ls180.v:359.13-359.37" - wire width 16 \main_sdram_dfi_p0_rddata - attribute \src "ls180.v:358.5-358.32" - wire \main_sdram_dfi_p0_rddata_en - attribute \src "ls180.v:360.6-360.36" - wire \main_sdram_dfi_p0_rddata_valid - attribute \src "ls180.v:353.6-353.31" - wire \main_sdram_dfi_p0_reset_n - attribute \src "ls180.v:350.5-350.27" - wire \main_sdram_dfi_p0_we_n - attribute \src "ls180.v:355.13-355.37" - wire width 16 \main_sdram_dfi_p0_wrdata - attribute \src "ls180.v:356.5-356.32" - wire \main_sdram_dfi_p0_wrdata_en - attribute \src "ls180.v:357.12-357.41" - wire width 2 \main_sdram_dfi_p0_wrdata_mask - attribute \src "ls180.v:769.5-769.19" - wire \main_sdram_en0 - attribute \src "ls180.v:772.5-772.19" - wire \main_sdram_en1 - attribute \src "ls180.v:775.6-775.30" - wire \main_sdram_go_to_refresh - attribute \src "ls180.v:317.13-317.44" - wire width 22 \main_sdram_interface_bank0_addr - attribute \src "ls180.v:318.6-318.37" - wire \main_sdram_interface_bank0_lock - attribute \src "ls180.v:320.6-320.44" - wire \main_sdram_interface_bank0_rdata_valid - attribute \src "ls180.v:315.6-315.38" - wire \main_sdram_interface_bank0_ready - attribute \src "ls180.v:314.6-314.38" - wire \main_sdram_interface_bank0_valid - attribute \src "ls180.v:319.6-319.44" - wire \main_sdram_interface_bank0_wdata_ready - attribute \src "ls180.v:316.6-316.35" - wire \main_sdram_interface_bank0_we - attribute \src "ls180.v:324.13-324.44" - wire width 22 \main_sdram_interface_bank1_addr - attribute \src "ls180.v:325.6-325.37" - wire \main_sdram_interface_bank1_lock - attribute \src "ls180.v:327.6-327.44" - wire \main_sdram_interface_bank1_rdata_valid - attribute \src "ls180.v:322.6-322.38" - wire \main_sdram_interface_bank1_ready - attribute \src "ls180.v:321.6-321.38" - wire \main_sdram_interface_bank1_valid - attribute \src "ls180.v:326.6-326.44" - wire \main_sdram_interface_bank1_wdata_ready - attribute \src "ls180.v:323.6-323.35" - wire \main_sdram_interface_bank1_we - attribute \src "ls180.v:331.13-331.44" - wire width 22 \main_sdram_interface_bank2_addr - attribute \src "ls180.v:332.6-332.37" - wire \main_sdram_interface_bank2_lock - attribute \src "ls180.v:334.6-334.44" - wire \main_sdram_interface_bank2_rdata_valid - attribute \src "ls180.v:329.6-329.38" - wire \main_sdram_interface_bank2_ready - attribute \src "ls180.v:328.6-328.38" - wire \main_sdram_interface_bank2_valid - attribute \src "ls180.v:333.6-333.44" - wire \main_sdram_interface_bank2_wdata_ready - attribute \src "ls180.v:330.6-330.35" - wire \main_sdram_interface_bank2_we - attribute \src "ls180.v:338.13-338.44" - wire width 22 \main_sdram_interface_bank3_addr - attribute \src "ls180.v:339.6-339.37" - wire \main_sdram_interface_bank3_lock - attribute \src "ls180.v:341.6-341.44" - wire \main_sdram_interface_bank3_rdata_valid - attribute \src "ls180.v:336.6-336.38" - wire \main_sdram_interface_bank3_ready - attribute \src "ls180.v:335.6-335.38" - wire \main_sdram_interface_bank3_valid - attribute \src "ls180.v:340.6-340.44" - wire \main_sdram_interface_bank3_wdata_ready - attribute \src "ls180.v:337.6-337.35" - wire \main_sdram_interface_bank3_we - attribute \src "ls180.v:344.13-344.39" - wire width 16 \main_sdram_interface_rdata - attribute \src "ls180.v:342.12-342.38" - wire width 16 \main_sdram_interface_wdata - attribute \src "ls180.v:343.11-343.40" - wire width 2 \main_sdram_interface_wdata_we - attribute \src "ls180.v:255.5-255.29" - wire \main_sdram_inti_p0_act_n - attribute \src "ls180.v:246.13-246.39" - wire width 13 \main_sdram_inti_p0_address - attribute \src "ls180.v:247.12-247.35" - wire width 2 \main_sdram_inti_p0_bank - attribute \src "ls180.v:248.5-248.29" - wire \main_sdram_inti_p0_cas_n - attribute \src "ls180.v:252.6-252.28" - wire \main_sdram_inti_p0_cke - attribute \src "ls180.v:249.5-249.28" - wire \main_sdram_inti_p0_cs_n - attribute \src "ls180.v:253.6-253.28" - wire \main_sdram_inti_p0_odt - attribute \src "ls180.v:250.5-250.29" - wire \main_sdram_inti_p0_ras_n - attribute \src "ls180.v:260.12-260.37" - wire width 16 \main_sdram_inti_p0_rddata - attribute \src "ls180.v:259.6-259.34" - wire \main_sdram_inti_p0_rddata_en - attribute \src "ls180.v:261.5-261.36" - wire \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:254.6-254.32" - wire \main_sdram_inti_p0_reset_n - attribute \src "ls180.v:251.5-251.28" - wire \main_sdram_inti_p0_we_n - attribute \src "ls180.v:256.13-256.38" - wire width 16 \main_sdram_inti_p0_wrdata - attribute \src "ls180.v:257.6-257.34" - wire \main_sdram_inti_p0_wrdata_en - attribute \src "ls180.v:258.12-258.42" - wire width 2 \main_sdram_inti_p0_wrdata_mask - attribute \src "ls180.v:287.5-287.31" - wire \main_sdram_master_p0_act_n - attribute \src "ls180.v:278.12-278.40" - wire width 13 \main_sdram_master_p0_address - attribute \src "ls180.v:279.11-279.36" - wire width 2 \main_sdram_master_p0_bank - attribute \src "ls180.v:280.5-280.31" - wire \main_sdram_master_p0_cas_n - attribute \src "ls180.v:284.5-284.29" - wire \main_sdram_master_p0_cke - attribute \src "ls180.v:281.5-281.30" - wire \main_sdram_master_p0_cs_n - attribute \src "ls180.v:285.5-285.29" - wire \main_sdram_master_p0_odt - attribute \src "ls180.v:282.5-282.31" - wire \main_sdram_master_p0_ras_n - attribute \src "ls180.v:292.13-292.40" - wire width 16 \main_sdram_master_p0_rddata - attribute \src "ls180.v:291.5-291.35" - wire \main_sdram_master_p0_rddata_en - attribute \src "ls180.v:293.6-293.39" - wire \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:286.5-286.33" - wire \main_sdram_master_p0_reset_n - attribute \src "ls180.v:283.5-283.30" - wire \main_sdram_master_p0_we_n - attribute \src "ls180.v:288.12-288.39" - wire width 16 \main_sdram_master_p0_wrdata - attribute \src "ls180.v:289.5-289.35" - wire \main_sdram_master_p0_wrdata_en - attribute \src "ls180.v:290.11-290.43" - wire width 2 \main_sdram_master_p0_wrdata_mask - attribute \src "ls180.v:770.6-770.26" - wire \main_sdram_max_time0 - attribute \src "ls180.v:773.6-773.26" - wire \main_sdram_max_time1 - attribute \src "ls180.v:752.12-752.28" - wire width 13 \main_sdram_nop_a - attribute \src "ls180.v:753.11-753.28" - wire width 2 \main_sdram_nop_ba - attribute \src "ls180.v:296.6-296.20" - wire \main_sdram_odt - attribute \src "ls180.v:379.5-379.31" - wire \main_sdram_postponer_count - attribute \src "ls180.v:377.6-377.32" - wire \main_sdram_postponer_req_i - attribute \src "ls180.v:378.5-378.31" - wire \main_sdram_postponer_req_o - attribute \src "ls180.v:714.6-714.28" - wire \main_sdram_ras_allowed - attribute \src "ls180.v:299.5-299.18" - wire \main_sdram_re - attribute \src "ls180.v:767.6-767.31" - wire \main_sdram_read_available - attribute \src "ls180.v:297.6-297.24" - wire \main_sdram_reset_n - attribute \src "ls180.v:294.6-294.20" - wire \main_sdram_sel - attribute \src "ls180.v:385.5-385.31" - wire \main_sdram_sequencer_count - attribute \src "ls180.v:384.11-384.39" - wire width 4 \main_sdram_sequencer_counter - attribute \src "ls180.v:381.6-381.32" - wire \main_sdram_sequencer_done0 - attribute \src "ls180.v:383.5-383.31" - wire \main_sdram_sequencer_done1 - attribute \src "ls180.v:380.5-380.32" - wire \main_sdram_sequencer_start0 - attribute \src "ls180.v:382.6-382.33" - wire \main_sdram_sequencer_start1 - attribute \src "ls180.v:271.6-271.31" - wire \main_sdram_slave_p0_act_n - attribute \src "ls180.v:262.13-262.40" - wire width 13 \main_sdram_slave_p0_address - attribute \src "ls180.v:263.12-263.36" - wire width 2 \main_sdram_slave_p0_bank - attribute \src "ls180.v:264.6-264.31" - wire \main_sdram_slave_p0_cas_n - attribute \src "ls180.v:268.6-268.29" - wire \main_sdram_slave_p0_cke - attribute \src "ls180.v:265.6-265.30" - wire \main_sdram_slave_p0_cs_n - attribute \src "ls180.v:269.6-269.29" - wire \main_sdram_slave_p0_odt - attribute \src "ls180.v:266.6-266.31" - wire \main_sdram_slave_p0_ras_n - attribute \src "ls180.v:276.12-276.38" - wire width 16 \main_sdram_slave_p0_rddata - attribute \src "ls180.v:275.6-275.35" - wire \main_sdram_slave_p0_rddata_en - attribute \src "ls180.v:277.5-277.37" - wire \main_sdram_slave_p0_rddata_valid - attribute \src "ls180.v:270.6-270.33" - wire \main_sdram_slave_p0_reset_n - attribute \src "ls180.v:267.6-267.30" - wire \main_sdram_slave_p0_we_n - attribute \src "ls180.v:272.13-272.39" - wire width 16 \main_sdram_slave_p0_wrdata - attribute \src "ls180.v:273.6-273.35" - wire \main_sdram_slave_p0_wrdata_en - attribute \src "ls180.v:274.12-274.43" - wire width 2 \main_sdram_slave_p0_wrdata_mask - attribute \src "ls180.v:312.12-312.29" - wire width 16 \main_sdram_status - attribute \src "ls180.v:755.5-755.24" - wire \main_sdram_steerer0 - attribute \src "ls180.v:756.5-756.24" - wire \main_sdram_steerer1 - attribute \src "ls180.v:754.11-754.33" - wire width 2 \main_sdram_steerer_sel - attribute \src "ls180.v:298.11-298.29" - wire width 4 \main_sdram_storage - attribute \src "ls180.v:763.5-763.29" - wire \main_sdram_tccdcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:762.32-762.56" - wire \main_sdram_tccdcon_ready - attribute \src "ls180.v:761.6-761.30" - wire \main_sdram_tccdcon_valid - attribute \no_retiming "true" - attribute \src "ls180.v:760.32-760.56" - wire \main_sdram_tfawcon_ready - attribute \src "ls180.v:759.6-759.30" - wire \main_sdram_tfawcon_valid - attribute \src "ls180.v:771.11-771.27" - wire width 5 \main_sdram_time0 - attribute \src "ls180.v:774.11-774.27" - wire width 4 \main_sdram_time1 - attribute \src "ls180.v:374.12-374.35" - wire width 10 \main_sdram_timer_count0 - attribute \src "ls180.v:376.11-376.34" - wire width 10 \main_sdram_timer_count1 - attribute \src "ls180.v:373.6-373.28" - wire \main_sdram_timer_done0 - attribute \src "ls180.v:375.6-375.28" - wire \main_sdram_timer_done1 - attribute \src "ls180.v:372.6-372.27" - wire \main_sdram_timer_wait - attribute \no_retiming "true" - attribute \src "ls180.v:758.32-758.56" - wire \main_sdram_trrdcon_ready - attribute \src "ls180.v:757.6-757.30" - wire \main_sdram_trrdcon_valid - attribute \src "ls180.v:766.11-766.35" - wire width 3 \main_sdram_twtrcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:765.32-765.56" - wire \main_sdram_twtrcon_ready - attribute \src "ls180.v:764.6-764.30" - wire \main_sdram_twtrcon_valid - attribute \src "ls180.v:371.6-371.30" - wire \main_sdram_wants_refresh - attribute \src "ls180.v:313.6-313.19" - wire \main_sdram_we - attribute \src "ls180.v:311.5-311.25" - wire \main_sdram_wrdata_re - attribute \src "ls180.v:310.12-310.37" - wire width 16 \main_sdram_wrdata_storage - attribute \src "ls180.v:768.6-768.32" - wire \main_sdram_write_available - attribute \src "ls180.v:976.12-976.40" - wire width 16 \main_spi_master_clk_divider0 - attribute \src "ls180.v:998.12-998.40" - wire width 16 \main_spi_master_clk_divider1 - attribute \src "ls180.v:993.5-993.31" - wire \main_spi_master_clk_enable - attribute \src "ls180.v:1000.6-1000.30" - wire \main_spi_master_clk_fall - attribute \src "ls180.v:999.6-999.30" - wire \main_spi_master_clk_rise - attribute \src "ls180.v:980.5-980.31" - wire \main_spi_master_control_re - attribute \src "ls180.v:979.12-979.43" - wire width 16 \main_spi_master_control_storage - attribute \src "ls180.v:995.11-995.32" - wire width 3 \main_spi_master_count - attribute \src "ls180.v:1761.11-1761.54" - wire width 3 \main_spi_master_count_spimaster0_next_value - attribute \src "ls180.v:1762.5-1762.51" - wire \main_spi_master_count_spimaster0_next_value_ce - attribute \src "ls180.v:974.6-974.24" - wire \main_spi_master_cs - attribute \src "ls180.v:994.5-994.30" - wire \main_spi_master_cs_enable - attribute \src "ls180.v:990.5-990.26" - wire \main_spi_master_cs_re - attribute \src "ls180.v:989.5-989.31" - wire \main_spi_master_cs_storage - attribute \src "ls180.v:970.5-970.26" - wire \main_spi_master_done0 - attribute \src "ls180.v:981.6-981.27" - wire \main_spi_master_done1 - attribute \src "ls180.v:971.5-971.24" - wire \main_spi_master_irq - attribute \src "ls180.v:969.12-969.35" - wire width 8 \main_spi_master_length0 - attribute \src "ls180.v:978.12-978.35" - wire width 8 \main_spi_master_length1 - attribute \src "ls180.v:975.6-975.30" - wire \main_spi_master_loopback - attribute \src "ls180.v:992.5-992.32" - wire \main_spi_master_loopback_re - attribute \src "ls180.v:991.5-991.37" - wire \main_spi_master_loopback_storage - attribute \src "ls180.v:973.11-973.31" - wire width 8 \main_spi_master_miso - attribute \src "ls180.v:1003.11-1003.36" - wire width 8 \main_spi_master_miso_data - attribute \src "ls180.v:997.5-997.31" - wire \main_spi_master_miso_latch - attribute \src "ls180.v:986.12-986.39" - wire width 8 \main_spi_master_miso_status - attribute \src "ls180.v:987.6-987.29" - wire \main_spi_master_miso_we - attribute \src "ls180.v:972.12-972.32" - wire width 8 \main_spi_master_mosi - attribute \src "ls180.v:1001.11-1001.36" - wire width 8 \main_spi_master_mosi_data - attribute \src "ls180.v:996.5-996.31" - wire \main_spi_master_mosi_latch - attribute \src "ls180.v:985.5-985.28" - wire \main_spi_master_mosi_re - attribute \src "ls180.v:1002.11-1002.35" - wire width 3 \main_spi_master_mosi_sel - attribute \src "ls180.v:984.11-984.39" - wire width 8 \main_spi_master_mosi_storage - attribute \src "ls180.v:988.6-988.25" - wire \main_spi_master_sel - attribute \src "ls180.v:968.6-968.28" - wire \main_spi_master_start0 - attribute \src "ls180.v:977.5-977.27" - wire \main_spi_master_start1 - attribute \src "ls180.v:982.6-982.35" - wire \main_spi_master_status_status - attribute \src "ls180.v:983.6-983.31" - wire \main_spi_master_status_we - attribute \src "ls180.v:865.12-865.44" - wire width 2 \main_uart_eventmanager_pending_r - attribute \src "ls180.v:864.6-864.39" - wire \main_uart_eventmanager_pending_re - attribute \src "ls180.v:867.11-867.43" - wire width 2 \main_uart_eventmanager_pending_w - attribute \src "ls180.v:866.6-866.39" - wire \main_uart_eventmanager_pending_we - attribute \src "ls180.v:869.5-869.30" - wire \main_uart_eventmanager_re - attribute \src "ls180.v:861.12-861.43" - wire width 2 \main_uart_eventmanager_status_r - attribute \src "ls180.v:860.6-860.38" - wire \main_uart_eventmanager_status_re - attribute \src "ls180.v:863.11-863.42" - wire width 2 \main_uart_eventmanager_status_w - attribute \src "ls180.v:862.6-862.38" - wire \main_uart_eventmanager_status_we - attribute \src "ls180.v:868.11-868.41" - wire width 2 \main_uart_eventmanager_storage - attribute \src "ls180.v:849.6-849.19" - wire \main_uart_irq - attribute \src "ls180.v:835.12-835.46" - wire width 32 \main_uart_phy_phase_accumulator_rx - attribute \src "ls180.v:825.12-825.46" - wire width 32 \main_uart_phy_phase_accumulator_tx - attribute \src "ls180.v:818.5-818.21" - wire \main_uart_phy_re - attribute \src "ls180.v:836.6-836.22" - wire \main_uart_phy_rx - attribute \src "ls180.v:839.11-839.36" - wire width 4 \main_uart_phy_rx_bitcount - attribute \src "ls180.v:840.5-840.26" - wire \main_uart_phy_rx_busy - attribute \src "ls180.v:837.5-837.23" - wire \main_uart_phy_rx_r - attribute \src "ls180.v:838.11-838.31" - wire width 8 \main_uart_phy_rx_reg - attribute \src "ls180.v:821.6-821.30" - wire \main_uart_phy_sink_first - attribute \src "ls180.v:822.6-822.29" - wire \main_uart_phy_sink_last - attribute \src "ls180.v:823.12-823.43" - wire width 8 \main_uart_phy_sink_payload_data - attribute \src "ls180.v:820.5-820.29" - wire \main_uart_phy_sink_ready - attribute \src "ls180.v:819.6-819.30" - wire \main_uart_phy_sink_valid - attribute \src "ls180.v:831.5-831.31" - wire \main_uart_phy_source_first - attribute \src "ls180.v:832.5-832.30" - wire \main_uart_phy_source_last - attribute \src "ls180.v:833.11-833.44" - wire width 8 \main_uart_phy_source_payload_data - attribute \src "ls180.v:830.6-830.32" - wire \main_uart_phy_source_ready - attribute \src "ls180.v:829.5-829.31" - wire \main_uart_phy_source_valid - attribute \src "ls180.v:817.12-817.33" - wire width 32 \main_uart_phy_storage - attribute \src "ls180.v:827.11-827.36" - wire width 4 \main_uart_phy_tx_bitcount - attribute \src "ls180.v:828.5-828.26" - wire \main_uart_phy_tx_busy - attribute \src "ls180.v:826.11-826.31" - wire width 8 \main_uart_phy_tx_reg - attribute \src "ls180.v:834.5-834.32" - wire \main_uart_phy_uart_clk_rxen - attribute \src "ls180.v:824.5-824.32" - wire \main_uart_phy_uart_clk_txen - attribute \src "ls180.v:958.5-958.20" - wire \main_uart_reset - attribute \src "ls180.v:858.5-858.23" - wire \main_uart_rx_clear - attribute \src "ls180.v:942.11-942.36" - wire width 4 \main_uart_rx_fifo_consume - attribute \src "ls180.v:947.6-947.31" - wire \main_uart_rx_fifo_do_read - attribute \src "ls180.v:953.6-953.37" - wire \main_uart_rx_fifo_fifo_in_first - attribute \src "ls180.v:954.6-954.36" - wire \main_uart_rx_fifo_fifo_in_last - attribute \src "ls180.v:952.12-952.50" - wire width 8 \main_uart_rx_fifo_fifo_in_payload_data - attribute \src "ls180.v:956.6-956.38" - wire \main_uart_rx_fifo_fifo_out_first - attribute \src "ls180.v:957.6-957.37" - wire \main_uart_rx_fifo_fifo_out_last - attribute \src "ls180.v:955.12-955.51" - wire width 8 \main_uart_rx_fifo_fifo_out_payload_data - attribute \src "ls180.v:939.11-939.35" - wire width 5 \main_uart_rx_fifo_level0 - attribute \src "ls180.v:951.12-951.36" - wire width 5 \main_uart_rx_fifo_level1 - attribute \src "ls180.v:941.11-941.36" - wire width 4 \main_uart_rx_fifo_produce - attribute \src "ls180.v:948.12-948.40" - wire width 4 \main_uart_rx_fifo_rdport_adr - attribute \src "ls180.v:949.12-949.42" - wire width 10 \main_uart_rx_fifo_rdport_dat_r - attribute \src "ls180.v:950.6-950.33" - wire \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:931.6-931.26" - wire \main_uart_rx_fifo_re - attribute \src "ls180.v:932.5-932.31" - wire \main_uart_rx_fifo_readable - attribute \src "ls180.v:940.5-940.30" - wire \main_uart_rx_fifo_replace - attribute \src "ls180.v:923.6-923.34" - wire \main_uart_rx_fifo_sink_first - attribute \src "ls180.v:924.6-924.33" - wire \main_uart_rx_fifo_sink_last - attribute \src "ls180.v:925.12-925.47" - wire width 8 \main_uart_rx_fifo_sink_payload_data - attribute \src "ls180.v:922.6-922.34" - wire \main_uart_rx_fifo_sink_ready - attribute \src "ls180.v:921.6-921.34" - wire \main_uart_rx_fifo_sink_valid - attribute \src "ls180.v:928.6-928.36" - wire \main_uart_rx_fifo_source_first - attribute \src "ls180.v:929.6-929.35" - wire \main_uart_rx_fifo_source_last - attribute \src "ls180.v:930.12-930.49" - wire width 8 \main_uart_rx_fifo_source_payload_data - attribute \src "ls180.v:927.6-927.36" - wire \main_uart_rx_fifo_source_ready - attribute \src "ls180.v:926.6-926.36" - wire \main_uart_rx_fifo_source_valid - attribute \src "ls180.v:937.12-937.42" - wire width 10 \main_uart_rx_fifo_syncfifo_din - attribute \src "ls180.v:938.12-938.43" - wire width 10 \main_uart_rx_fifo_syncfifo_dout - attribute \src "ls180.v:935.6-935.35" - wire \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:936.6-936.41" - wire \main_uart_rx_fifo_syncfifo_readable - attribute \src "ls180.v:933.6-933.35" - wire \main_uart_rx_fifo_syncfifo_we - attribute \src "ls180.v:934.6-934.41" - wire \main_uart_rx_fifo_syncfifo_writable - attribute \src "ls180.v:943.11-943.39" - wire width 4 \main_uart_rx_fifo_wrport_adr - attribute \src "ls180.v:944.12-944.42" - wire width 10 \main_uart_rx_fifo_wrport_dat_r - attribute \src "ls180.v:946.12-946.42" - wire width 10 \main_uart_rx_fifo_wrport_dat_w - attribute \src "ls180.v:945.6-945.33" - wire \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:859.5-859.29" - wire \main_uart_rx_old_trigger - attribute \src "ls180.v:856.5-856.25" - wire \main_uart_rx_pending - attribute \src "ls180.v:855.6-855.25" - wire \main_uart_rx_status - attribute \src "ls180.v:857.6-857.26" - wire \main_uart_rx_trigger - attribute \src "ls180.v:847.6-847.30" - wire \main_uart_rxempty_status - attribute \src "ls180.v:848.6-848.26" - wire \main_uart_rxempty_we - attribute \src "ls180.v:872.6-872.29" - wire \main_uart_rxfull_status - attribute \src "ls180.v:873.6-873.25" - wire \main_uart_rxfull_we - attribute \src "ls180.v:842.12-842.28" - wire width 8 \main_uart_rxtx_r - attribute \src "ls180.v:841.6-841.23" - wire \main_uart_rxtx_re - attribute \src "ls180.v:844.12-844.28" - wire width 8 \main_uart_rxtx_w - attribute \src "ls180.v:843.6-843.23" - wire \main_uart_rxtx_we - attribute \src "ls180.v:853.5-853.23" - wire \main_uart_tx_clear - attribute \src "ls180.v:905.11-905.36" - wire width 4 \main_uart_tx_fifo_consume - attribute \src "ls180.v:910.6-910.31" - wire \main_uart_tx_fifo_do_read - attribute \src "ls180.v:916.6-916.37" - wire \main_uart_tx_fifo_fifo_in_first - attribute \src "ls180.v:917.6-917.36" - wire \main_uart_tx_fifo_fifo_in_last - attribute \src "ls180.v:915.12-915.50" - wire width 8 \main_uart_tx_fifo_fifo_in_payload_data - attribute \src "ls180.v:919.6-919.38" - wire \main_uart_tx_fifo_fifo_out_first - attribute \src "ls180.v:920.6-920.37" - wire \main_uart_tx_fifo_fifo_out_last - attribute \src "ls180.v:918.12-918.51" - wire width 8 \main_uart_tx_fifo_fifo_out_payload_data - attribute \src "ls180.v:902.11-902.35" - wire width 5 \main_uart_tx_fifo_level0 - attribute \src "ls180.v:914.12-914.36" - wire width 5 \main_uart_tx_fifo_level1 - attribute \src "ls180.v:904.11-904.36" - wire width 4 \main_uart_tx_fifo_produce - attribute \src "ls180.v:911.12-911.40" - wire width 4 \main_uart_tx_fifo_rdport_adr - attribute \src "ls180.v:912.12-912.42" - wire width 10 \main_uart_tx_fifo_rdport_dat_r - attribute \src "ls180.v:913.6-913.33" - wire \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:894.6-894.26" - wire \main_uart_tx_fifo_re - attribute \src "ls180.v:895.5-895.31" - wire \main_uart_tx_fifo_readable - attribute \src "ls180.v:903.5-903.30" - wire \main_uart_tx_fifo_replace - attribute \src "ls180.v:886.5-886.33" - wire \main_uart_tx_fifo_sink_first - attribute \src "ls180.v:887.5-887.32" - wire \main_uart_tx_fifo_sink_last - attribute \src "ls180.v:888.12-888.47" - wire width 8 \main_uart_tx_fifo_sink_payload_data - attribute \src "ls180.v:885.6-885.34" - wire \main_uart_tx_fifo_sink_ready - attribute \src "ls180.v:884.6-884.34" - wire \main_uart_tx_fifo_sink_valid - attribute \src "ls180.v:891.6-891.36" - wire \main_uart_tx_fifo_source_first - attribute \src "ls180.v:892.6-892.35" - wire \main_uart_tx_fifo_source_last - attribute \src "ls180.v:893.12-893.49" - wire width 8 \main_uart_tx_fifo_source_payload_data - attribute \src "ls180.v:890.6-890.36" - wire \main_uart_tx_fifo_source_ready - attribute \src "ls180.v:889.6-889.36" - wire \main_uart_tx_fifo_source_valid - attribute \src "ls180.v:900.12-900.42" - wire width 10 \main_uart_tx_fifo_syncfifo_din - attribute \src "ls180.v:901.12-901.43" - wire width 10 \main_uart_tx_fifo_syncfifo_dout - attribute \src "ls180.v:898.6-898.35" - wire \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:899.6-899.41" - wire \main_uart_tx_fifo_syncfifo_readable - attribute \src "ls180.v:896.6-896.35" - wire \main_uart_tx_fifo_syncfifo_we - attribute \src "ls180.v:897.6-897.41" - wire \main_uart_tx_fifo_syncfifo_writable - attribute \src "ls180.v:906.11-906.39" - wire width 4 \main_uart_tx_fifo_wrport_adr - attribute \src "ls180.v:907.12-907.42" - wire width 10 \main_uart_tx_fifo_wrport_dat_r - attribute \src "ls180.v:909.12-909.42" - wire width 10 \main_uart_tx_fifo_wrport_dat_w - attribute \src "ls180.v:908.6-908.33" - wire \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:854.5-854.29" - wire \main_uart_tx_old_trigger - attribute \src "ls180.v:851.5-851.25" - wire \main_uart_tx_pending - attribute \src "ls180.v:850.6-850.25" - wire \main_uart_tx_status - attribute \src "ls180.v:852.6-852.26" - wire \main_uart_tx_trigger - attribute \src "ls180.v:870.6-870.30" - wire \main_uart_txempty_status - attribute \src "ls180.v:871.6-871.26" - wire \main_uart_txempty_we - attribute \src "ls180.v:845.6-845.29" - wire \main_uart_txfull_status - attribute \src "ls180.v:846.6-846.25" - wire \main_uart_txfull_we - attribute \src "ls180.v:876.6-876.31" - wire \main_uart_uart_sink_first - attribute \src "ls180.v:877.6-877.30" - wire \main_uart_uart_sink_last - attribute \src "ls180.v:878.12-878.44" - wire width 8 \main_uart_uart_sink_payload_data - attribute \src "ls180.v:875.6-875.31" - wire \main_uart_uart_sink_ready - attribute \src "ls180.v:874.6-874.31" - wire \main_uart_uart_sink_valid - attribute \src "ls180.v:881.6-881.33" - wire \main_uart_uart_source_first - attribute \src "ls180.v:882.6-882.32" - wire \main_uart_uart_source_last - attribute \src "ls180.v:883.12-883.46" - wire width 8 \main_uart_uart_source_payload_data - attribute \src "ls180.v:880.6-880.33" - wire \main_uart_uart_source_ready - attribute \src "ls180.v:879.6-879.33" - wire \main_uart_uart_source_valid - attribute \src "ls180.v:795.5-795.22" - wire \main_wb_sdram_ack - attribute \src "ls180.v:789.13-789.30" - wire width 30 \main_wb_sdram_adr - attribute \src "ls180.v:798.12-798.29" - wire width 2 \main_wb_sdram_bte - attribute \src "ls180.v:797.12-797.29" - wire width 3 \main_wb_sdram_cti - attribute \src "ls180.v:793.6-793.23" - wire \main_wb_sdram_cyc - attribute \src "ls180.v:791.13-791.32" - wire width 32 \main_wb_sdram_dat_r - attribute \src "ls180.v:790.13-790.32" - wire width 32 \main_wb_sdram_dat_w - attribute \src "ls180.v:799.5-799.22" - wire \main_wb_sdram_err - attribute \src "ls180.v:792.12-792.29" - wire width 4 \main_wb_sdram_sel - attribute \src "ls180.v:794.6-794.23" - wire \main_wb_sdram_stb - attribute \src "ls180.v:796.6-796.22" - wire \main_wb_sdram_we - attribute \src "ls180.v:813.5-813.24" - wire \main_wdata_consumed - attribute \src "ls180.v:10039.11-10039.17" - wire width 7 \memadr - attribute \src "ls180.v:10059.12-10059.18" - wire width 25 \memdat - attribute \src "ls180.v:10073.12-10073.20" - wire width 25 \memdat_1 - attribute \src "ls180.v:10087.12-10087.20" - wire width 25 \memdat_2 - attribute \src "ls180.v:10101.12-10101.20" - wire width 25 \memdat_3 - attribute \src "ls180.v:10115.11-10115.19" - wire width 10 \memdat_4 - attribute \src "ls180.v:10116.11-10116.19" - wire width 10 \memdat_5 - attribute \src "ls180.v:10132.11-10132.19" - wire width 10 \memdat_6 - attribute \src "ls180.v:10133.11-10133.19" - wire width 10 \memdat_7 - attribute \src "ls180.v:10149.11-10149.19" - wire width 10 \memdat_8 - attribute \src "ls180.v:10163.11-10163.19" - wire width 10 \memdat_9 - attribute \src "ls180.v:35.20-35.22" - wire width 36 input 31 \nc - attribute \src "ls180.v:227.6-227.13" - wire \por_clk - attribute \src "ls180.v:36.13-36.17" - wire output 32 \pwm0 - attribute \src "ls180.v:37.13-37.17" - wire output 33 \pwm1 - attribute \src "ls180.v:42.13-42.23" - wire output 38 \sdcard_clk - attribute \src "ls180.v:43.13-43.25" - wire input 39 \sdcard_cmd_i - attribute \src "ls180.v:44.13-44.25" - wire output 40 \sdcard_cmd_o - attribute \src "ls180.v:45.13-45.26" - wire output 41 \sdcard_cmd_oe - attribute \src "ls180.v:46.19-46.32" - wire width 4 input 42 \sdcard_data_i - attribute \src "ls180.v:47.19-47.32" - wire width 4 output 43 \sdcard_data_o - attribute \src "ls180.v:48.13-48.27" - wire output 44 \sdcard_data_oe - attribute \src "ls180.v:9.20-9.27" - wire width 13 output 5 \sdram_a - attribute \src "ls180.v:18.19-18.27" - wire width 2 output 14 \sdram_ba - attribute \src "ls180.v:15.13-15.24" - wire output 11 \sdram_cas_n - attribute \src "ls180.v:17.13-17.22" - wire output 13 \sdram_cke - attribute \src "ls180.v:20.13-20.24" - wire output 16 \sdram_clock - attribute \src "ls180.v:16.13-16.23" - wire output 12 \sdram_cs_n - attribute \src "ls180.v:19.19-19.27" - wire width 2 output 15 \sdram_dm - attribute \src "ls180.v:10.20-10.30" - wire width 16 input 6 \sdram_dq_i - attribute \src "ls180.v:11.20-11.30" - wire width 16 output 7 \sdram_dq_o - attribute \src "ls180.v:12.13-12.24" - wire output 8 \sdram_dq_oe - attribute \src "ls180.v:14.13-14.24" - wire output 10 \sdram_ras_n - attribute \src "ls180.v:13.13-13.23" - wire output 9 \sdram_we_n - attribute \src "ls180.v:2623.6-2623.15" - wire \sdrio_clk - attribute \src "ls180.v:2624.6-2624.17" - wire \sdrio_clk_1 - attribute \src "ls180.v:2633.6-2633.18" - wire \sdrio_clk_10 - attribute \src "ls180.v:2634.6-2634.18" - wire \sdrio_clk_11 - attribute \src "ls180.v:2635.6-2635.18" - wire \sdrio_clk_12 - attribute \src "ls180.v:2636.6-2636.18" - wire \sdrio_clk_13 - attribute \src "ls180.v:2637.6-2637.18" - wire \sdrio_clk_14 - attribute \src "ls180.v:2638.6-2638.18" - wire \sdrio_clk_15 - attribute \src "ls180.v:2639.6-2639.18" - wire \sdrio_clk_16 - attribute \src "ls180.v:2640.6-2640.18" - wire \sdrio_clk_17 - attribute \src "ls180.v:2641.6-2641.18" - wire \sdrio_clk_18 - attribute \src "ls180.v:2642.6-2642.18" - wire \sdrio_clk_19 - attribute \src "ls180.v:2625.6-2625.17" - wire \sdrio_clk_2 - attribute \src "ls180.v:2643.6-2643.18" - wire \sdrio_clk_20 - attribute \src "ls180.v:2644.6-2644.18" - wire \sdrio_clk_21 - attribute \src "ls180.v:2645.6-2645.18" - wire \sdrio_clk_22 - attribute \src "ls180.v:2646.6-2646.18" - wire \sdrio_clk_23 - attribute \src "ls180.v:2647.6-2647.18" - wire \sdrio_clk_24 - attribute \src "ls180.v:2648.6-2648.18" - wire \sdrio_clk_25 - attribute \src "ls180.v:2649.6-2649.18" - wire \sdrio_clk_26 - attribute \src "ls180.v:2650.6-2650.18" - wire \sdrio_clk_27 - attribute \src "ls180.v:2651.6-2651.18" - wire \sdrio_clk_28 - attribute \src "ls180.v:2652.6-2652.18" - wire \sdrio_clk_29 - attribute \src "ls180.v:2626.6-2626.17" - wire \sdrio_clk_3 - attribute \src "ls180.v:2653.6-2653.18" - wire \sdrio_clk_30 - attribute \src "ls180.v:2654.6-2654.18" - wire \sdrio_clk_31 - attribute \src "ls180.v:2655.6-2655.18" - wire \sdrio_clk_32 - attribute \src "ls180.v:2656.6-2656.18" - wire \sdrio_clk_33 - attribute \src "ls180.v:2657.6-2657.18" - wire \sdrio_clk_34 - attribute \src "ls180.v:2658.6-2658.18" - wire \sdrio_clk_35 - attribute \src "ls180.v:2659.6-2659.18" - wire \sdrio_clk_36 - attribute \src "ls180.v:2660.6-2660.18" - wire \sdrio_clk_37 - attribute \src "ls180.v:2661.6-2661.18" - wire \sdrio_clk_38 - attribute \src "ls180.v:2662.6-2662.18" - wire \sdrio_clk_39 - attribute \src "ls180.v:2627.6-2627.17" - wire \sdrio_clk_4 - attribute \src "ls180.v:2663.6-2663.18" - wire \sdrio_clk_40 - attribute \src "ls180.v:2664.6-2664.18" - wire \sdrio_clk_41 - attribute \src "ls180.v:2665.6-2665.18" - wire \sdrio_clk_42 - attribute \src "ls180.v:2666.6-2666.18" - wire \sdrio_clk_43 - attribute \src "ls180.v:2667.6-2667.18" - wire \sdrio_clk_44 - attribute \src "ls180.v:2668.6-2668.18" - wire \sdrio_clk_45 - attribute \src "ls180.v:2669.6-2669.18" - wire \sdrio_clk_46 - attribute \src "ls180.v:2670.6-2670.18" - wire \sdrio_clk_47 - attribute \src "ls180.v:2671.6-2671.18" - wire \sdrio_clk_48 - attribute \src "ls180.v:2672.6-2672.18" - wire \sdrio_clk_49 - attribute \src "ls180.v:2628.6-2628.17" - wire \sdrio_clk_5 - attribute \src "ls180.v:2673.6-2673.18" - wire \sdrio_clk_50 - attribute \src "ls180.v:2674.6-2674.18" - wire \sdrio_clk_51 - attribute \src "ls180.v:2675.6-2675.18" - wire \sdrio_clk_52 - attribute \src "ls180.v:2676.6-2676.18" - wire \sdrio_clk_53 - attribute \src "ls180.v:2677.6-2677.18" - wire \sdrio_clk_54 - attribute \src "ls180.v:2678.6-2678.18" - wire \sdrio_clk_55 - attribute \src "ls180.v:2713.6-2713.18" - wire \sdrio_clk_56 - attribute \src "ls180.v:2714.6-2714.18" - wire \sdrio_clk_57 - attribute \src "ls180.v:2715.6-2715.18" - wire \sdrio_clk_58 - attribute \src "ls180.v:2716.6-2716.18" - wire \sdrio_clk_59 - attribute \src "ls180.v:2629.6-2629.17" - wire \sdrio_clk_6 - attribute \src "ls180.v:2717.6-2717.18" - wire \sdrio_clk_60 - attribute \src "ls180.v:2718.6-2718.18" - wire \sdrio_clk_61 - attribute \src "ls180.v:2719.6-2719.18" - wire \sdrio_clk_62 - attribute \src "ls180.v:2720.6-2720.18" - wire \sdrio_clk_63 - attribute \src "ls180.v:2721.6-2721.18" - wire \sdrio_clk_64 - attribute \src "ls180.v:2722.6-2722.18" - wire \sdrio_clk_65 - attribute \src "ls180.v:2723.6-2723.18" - wire \sdrio_clk_66 - attribute \src "ls180.v:2724.6-2724.18" - wire \sdrio_clk_67 - attribute \src "ls180.v:2725.6-2725.18" - wire \sdrio_clk_68 - attribute \src "ls180.v:2630.6-2630.17" - wire \sdrio_clk_7 - attribute \src "ls180.v:2631.6-2631.17" - wire \sdrio_clk_8 - attribute \src "ls180.v:2632.6-2632.17" - wire \sdrio_clk_9 - attribute \src "ls180.v:26.13-26.27" - wire output 22 \spi_master_clk - attribute \src "ls180.v:28.13-28.28" - wire output 24 \spi_master_cs_n - attribute \src "ls180.v:29.13-29.28" - wire input 25 \spi_master_miso - attribute \src "ls180.v:27.13-27.28" - wire output 23 \spi_master_mosi - attribute \src "ls180.v:49.13-49.26" - wire output 45 \spisdcard_clk - attribute \src "ls180.v:51.13-51.27" - wire output 47 \spisdcard_cs_n - attribute \src "ls180.v:52.13-52.27" - wire input 48 \spisdcard_miso - attribute \src "ls180.v:50.13-50.27" - wire output 46 \spisdcard_mosi - attribute \src "ls180.v:5.13-5.20" - wire input 1 \sys_clk - attribute \src "ls180.v:225.6-225.15" - wire \sys_clk_1 - attribute \src "ls180.v:7.19-7.31" - wire width 3 input 3 \sys_clksel_i - attribute \src "ls180.v:8.14-8.26" - wire output 4 \sys_pll_48_o - attribute \src "ls180.v:6.13-6.20" - wire input 2 \sys_rst - attribute \src "ls180.v:226.6-226.15" - wire \sys_rst_1 - attribute \src "ls180.v:22.13-22.20" - wire input 18 \uart_rx - attribute \src "ls180.v:21.14-21.21" - wire output 17 \uart_tx - attribute \src "ls180.v:10038.12-10038.15" - memory width 32 size 128 \mem - attribute \src "ls180.v:10058.12-10058.19" - memory width 25 size 8 \storage - attribute \src "ls180.v:10072.12-10072.21" - memory width 25 size 8 \storage_1 - attribute \src "ls180.v:10086.12-10086.21" - memory width 25 size 8 \storage_2 - attribute \src "ls180.v:10100.12-10100.21" - memory width 25 size 8 \storage_3 - attribute \src "ls180.v:10114.11-10114.20" - memory width 10 size 16 \storage_4 - attribute \src "ls180.v:10131.11-10131.20" - memory width 10 size 16 \storage_5 - attribute \src "ls180.v:10148.11-10148.20" - memory width 10 size 32 \storage_6 - attribute \src "ls180.v:10162.11-10162.20" - memory width 10 size 32 \storage_7 - attribute \src "ls180.v:2799.68-2799.110" - cell $add $add$ls180.v:2799$22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_counter - connect \B 1'1 - connect \Y $add$ls180.v:2799$22_Y - end - attribute \src "ls180.v:2859.68-2859.110" - cell $add $add$ls180.v:2859$33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_counter - connect \B 1'1 - connect \Y $add$ls180.v:2859$33_Y - end - attribute \src "ls180.v:2919.68-2919.110" - cell $add $add$ls180.v:2919$44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter2_counter - connect \B 1'1 - connect \Y $add$ls180.v:2919$44_Y - end - attribute \src "ls180.v:4052.54-4052.83" - cell $add $add$ls180.v:4052$537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter_counter - connect \B 1'1 - connect \Y $add$ls180.v:4052$537_Y - end - attribute \src "ls180.v:4152.36-4152.89" - cell $add $add$ls180.v:4152$583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_tx_fifo_level0 - connect \B \main_uart_tx_fifo_readable - connect \Y $add$ls180.v:4152$583_Y - end - attribute \src "ls180.v:4182.36-4182.89" - cell $add $add$ls180.v:4182$594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_rx_fifo_level0 - connect \B \main_uart_rx_fifo_readable - connect \Y $add$ls180.v:4182$594_Y - end - attribute \src "ls180.v:4237.53-4237.81" - cell $add $add$ls180.v:4237$607 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_spi_master_count - connect \B 1'1 - connect \Y $add$ls180.v:4237$607_Y - end - attribute \src "ls180.v:4341.58-4341.86" - cell $add $add$ls180.v:4341$635 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_init_count - connect \B 1'1 - connect \Y $add$ls180.v:4341$635_Y - end - attribute \src "ls180.v:4398.58-4398.86" - cell $add $add$ls180.v:4398$638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdw_count - connect \B 1'1 - connect \Y $add$ls180.v:4398$638_Y - end - attribute \src "ls180.v:4415.58-4415.86" - cell $add $add$ls180.v:4415$640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdw_count - connect \B 1'1 - connect \Y $add$ls180.v:4415$640_Y - end - attribute \src "ls180.v:4508.59-4508.87" - cell $add $add$ls180.v:4508$657 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdr_count - connect \B 1'1 - connect \Y $add$ls180.v:4508$657_Y - end - attribute \src "ls180.v:4533.59-4533.87" - cell $add $add$ls180.v:4533$660 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdr_count - connect \B 1'1 - connect \Y $add$ls180.v:4533$660_Y - end - attribute \src "ls180.v:4655.53-4655.82" - cell $add $add$ls180.v:4655$677 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_dataw_count - connect \B 1'1 - connect \Y $add$ls180.v:4655$677_Y - end - attribute \src "ls180.v:4766.65-4766.114" - cell $add $add$ls180.v:4766$691 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 10 - connect \A \main_sdphy_datar_sink_payload_block_length - connect \B 4'1000 - connect \Y $add$ls180.v:4766$691_Y - end - attribute \src "ls180.v:4771.62-4771.91" - cell $add $add$ls180.v:4771$694 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A \main_sdphy_datar_count - connect \B 1'1 - connect \Y $add$ls180.v:4771$694_Y - end - attribute \src "ls180.v:4797.61-4797.90" - cell $add $add$ls180.v:4797$697 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A \main_sdphy_datar_count - connect \B 1'1 - connect \Y $add$ls180.v:4797$697_Y - end - attribute \src "ls180.v:5001.80-5001.117" - cell $add $add$ls180.v:5001$882 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdcore_crc16_inserter_cnt - connect \B 1'1 - connect \Y $add$ls180.v:5001$882_Y - end - attribute \src "ls180.v:5195.54-5195.82" - cell $add $add$ls180.v:5195$957 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdcore_cmd_count - connect \B 1'1 - connect \Y $add$ls180.v:5195$957_Y - end - attribute \src "ls180.v:5247.55-5247.84" - cell $add $add$ls180.v:5247$967 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_data_count - connect \B 1'1 - connect \Y $add$ls180.v:5247$967_Y - end - attribute \src "ls180.v:5273.57-5273.86" - cell $add $add$ls180.v:5273$975 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_data_count - connect \B 1'1 - connect \Y $add$ls180.v:5273$975_Y - end - attribute \src "ls180.v:5394.51-5394.134" - cell $add $add$ls180.v:5394$991 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \main_sdblock2mem_wishbonedmawriter_base - connect \B \main_sdblock2mem_wishbonedmawriter_offset - connect \Y $add$ls180.v:5394$991_Y - end - attribute \src "ls180.v:5397.77-5397.125" - cell $add $add$ls180.v:5397$993 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdblock2mem_wishbonedmawriter_offset - connect \B 1'1 - connect \Y $add$ls180.v:5397$993_Y - end - attribute \src "ls180.v:5490.50-5490.105" - cell $add $add$ls180.v:5490$1002 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \main_sdmem2block_dma_base - connect \B \main_sdmem2block_dma_offset - connect \Y $add$ls180.v:5490$1002_Y - end - attribute \src "ls180.v:5492.77-5492.111" - cell $add $add$ls180.v:5492$1003 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdmem2block_dma_offset - connect \B 1'1 - connect \Y $add$ls180.v:5492$1003_Y - end - attribute \src "ls180.v:5604.49-5604.73" - cell $add $add$ls180.v:5604$1022 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \libresocsim_count - connect \B 1'1 - connect \Y $add$ls180.v:5604$1022_Y - end - attribute \src "ls180.v:7483.36-7483.70" - cell $add $add$ls180.v:7483$2415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_libresocsim_bus_errors - connect \B 1'1 - connect \Y $add$ls180.v:7483$2415_Y - end - attribute \src "ls180.v:7568.37-7568.72" - cell $add $add$ls180.v:7568$2436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_sequencer_counter - connect \B 1'1 - connect \Y $add$ls180.v:7568$2436_Y - end - attribute \src "ls180.v:7585.60-7585.119" - cell $add $add$ls180.v:7585$2440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $add$ls180.v:7585$2440_Y - end - attribute \src "ls180.v:7588.60-7588.119" - cell $add $add$ls180.v:7588$2441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - connect \B 1'1 - connect \Y $add$ls180.v:7588$2441_Y - end - attribute \src "ls180.v:7592.59-7592.116" - cell $add $add$ls180.v:7592$2446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $add$ls180.v:7592$2446_Y - end - attribute \src "ls180.v:7631.60-7631.119" - cell $add $add$ls180.v:7631$2456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $add$ls180.v:7631$2456_Y - end - attribute \src "ls180.v:7634.60-7634.119" - cell $add $add$ls180.v:7634$2457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - connect \B 1'1 - connect \Y $add$ls180.v:7634$2457_Y - end - attribute \src "ls180.v:7638.59-7638.116" - cell $add $add$ls180.v:7638$2462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $add$ls180.v:7638$2462_Y - end - attribute \src "ls180.v:7677.60-7677.119" - cell $add $add$ls180.v:7677$2472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $add$ls180.v:7677$2472_Y - end - attribute \src "ls180.v:7680.60-7680.119" - cell $add $add$ls180.v:7680$2473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - connect \B 1'1 - connect \Y $add$ls180.v:7680$2473_Y - end - attribute \src "ls180.v:7684.59-7684.116" - cell $add $add$ls180.v:7684$2478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $add$ls180.v:7684$2478_Y - end - attribute \src "ls180.v:7723.60-7723.119" - cell $add $add$ls180.v:7723$2488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $add$ls180.v:7723$2488_Y - end - attribute \src "ls180.v:7726.60-7726.119" - cell $add $add$ls180.v:7726$2489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - connect \B 1'1 - connect \Y $add$ls180.v:7726$2489_Y - end - attribute \src "ls180.v:7730.59-7730.116" - cell $add $add$ls180.v:7730$2494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $add$ls180.v:7730$2494_Y - end - attribute \src "ls180.v:7960.34-7960.66" - cell $add $add$ls180.v:7960$2548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_phy_tx_bitcount - connect \B 1'1 - connect \Y $add$ls180.v:7960$2548_Y - end - attribute \src "ls180.v:7976.73-7976.131" - cell $add $add$ls180.v:7976$2551 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 33 - connect \A \main_uart_phy_phase_accumulator_tx - connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:7976$2551_Y - end - attribute \src "ls180.v:7989.34-7989.66" - cell $add $add$ls180.v:7989$2555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_phy_rx_bitcount - connect \B 1'1 - connect \Y $add$ls180.v:7989$2555_Y - end - attribute \src "ls180.v:8008.73-8008.131" - cell $add $add$ls180.v:8008$2558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 33 - connect \A \main_uart_phy_phase_accumulator_rx - connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:8008$2558_Y - end - attribute \src "ls180.v:8034.33-8034.65" - cell $add $add$ls180.v:8034$2566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_tx_fifo_produce - connect \B 1'1 - connect \Y $add$ls180.v:8034$2566_Y - end - attribute \src "ls180.v:8037.33-8037.65" - cell $add $add$ls180.v:8037$2567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_tx_fifo_consume - connect \B 1'1 - connect \Y $add$ls180.v:8037$2567_Y - end - attribute \src "ls180.v:8041.33-8041.64" - cell $add $add$ls180.v:8041$2572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_tx_fifo_level0 - connect \B 1'1 - connect \Y $add$ls180.v:8041$2572_Y - end - attribute \src "ls180.v:8056.33-8056.65" - cell $add $add$ls180.v:8056$2577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_rx_fifo_produce - connect \B 1'1 - connect \Y $add$ls180.v:8056$2577_Y - end - attribute \src "ls180.v:8059.33-8059.65" - cell $add $add$ls180.v:8059$2578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_rx_fifo_consume - connect \B 1'1 - connect \Y $add$ls180.v:8059$2578_Y - end - attribute \src "ls180.v:8063.33-8063.64" - cell $add $add$ls180.v:8063$2583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_rx_fifo_level0 - connect \B 1'1 - connect \Y $add$ls180.v:8063$2583_Y - end - attribute \src "ls180.v:8084.35-8084.70" - cell $add $add$ls180.v:8084$2585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spi_master_clk_divider1 - connect \B 1'1 - connect \Y $add$ls180.v:8084$2585_Y - end - attribute \src "ls180.v:8120.25-8120.49" - cell $add $add$ls180.v:8120$2590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_pwm0_counter - connect \B 1'1 - connect \Y $add$ls180.v:8120$2590_Y - end - attribute \src "ls180.v:8134.25-8134.49" - cell $add $add$ls180.v:8134$2594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_pwm1_counter - connect \B 1'1 - connect \Y $add$ls180.v:8134$2594_Y - end - attribute \src "ls180.v:8148.31-8148.61" - cell $add $add$ls180.v:8148$2599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 9 - connect \A \main_sdphy_clocker_clks - connect \B 1'1 - connect \Y $add$ls180.v:8148$2599_Y - end - attribute \src "ls180.v:8171.45-8171.88" - cell $add $add$ls180.v:8171$2603 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdphy_cmdr_cmdr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8171$2603_Y - end - attribute \src "ls180.v:8217.71-8217.114" - cell $add $add$ls180.v:8217$2609 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdphy_cmdr_cmdr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8217$2609_Y - end - attribute \src "ls180.v:8252.46-8252.90" - cell $add $add$ls180.v:8252$2615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdphy_dataw_crcr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8252$2615_Y - end - attribute \src "ls180.v:8298.72-8298.116" - cell $add $add$ls180.v:8298$2621 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdphy_dataw_crcr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8298$2621_Y - end - attribute \src "ls180.v:8331.47-8331.92" - cell $add $add$ls180.v:8331$2627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8331$2627_Y - end - attribute \src "ls180.v:8359.73-8359.118" - cell $add $add$ls180.v:8359$2633 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \main_sdphy_datar_datar_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8359$2633_Y - end - attribute \src "ls180.v:8471.39-8471.75" - cell $add $add$ls180.v:8471$2646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 1'1 - connect \Y $add$ls180.v:8471$2646_Y - end - attribute \src "ls180.v:8532.37-8532.73" - cell $add $add$ls180.v:8532$2650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdblock2mem_fifo_produce - connect \B 1'1 - connect \Y $add$ls180.v:8532$2650_Y - end - attribute \src "ls180.v:8535.37-8535.73" - cell $add $add$ls180.v:8535$2651 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdblock2mem_fifo_consume - connect \B 1'1 - connect \Y $add$ls180.v:8535$2651_Y - end - attribute \src "ls180.v:8539.36-8539.70" - cell $add $add$ls180.v:8539$2656 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \main_sdblock2mem_fifo_level - connect \B 1'1 - connect \Y $add$ls180.v:8539$2656_Y - end - attribute \src "ls180.v:8554.41-8554.80" - cell $add $add$ls180.v:8554$2660 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \main_sdblock2mem_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8554$2660_Y - end - attribute \src "ls180.v:8588.67-8588.106" - cell $add $add$ls180.v:8588$2666 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdblock2mem_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8588$2666_Y - end - attribute \src "ls180.v:8614.39-8614.76" - cell $add $add$ls180.v:8614$2668 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \main_sdmem2block_converter_mux - connect \B 1'1 - connect \Y $add$ls180.v:8614$2668_Y - end - attribute \src "ls180.v:8618.37-8618.73" - cell $add $add$ls180.v:8618$2672 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdmem2block_fifo_produce - connect \B 1'1 - connect \Y $add$ls180.v:8618$2672_Y - end - attribute \src "ls180.v:8621.37-8621.73" - cell $add $add$ls180.v:8621$2673 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdmem2block_fifo_consume - connect \B 1'1 - connect \Y $add$ls180.v:8621$2673_Y - end - attribute \src "ls180.v:8625.36-8625.70" - cell $add $add$ls180.v:8625$2678 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \main_sdmem2block_fifo_level - connect \B 1'1 - connect \Y $add$ls180.v:8625$2678_Y - end - attribute \src "ls180.v:8632.31-8632.62" - cell $add $add$ls180.v:8632$2680 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \libresocsim_clk_divider1 - connect \B 1'1 - connect \Y $add$ls180.v:8632$2680_Y - end - attribute \src "ls180.v:2793.9-2793.80" - cell $and $and$ls180.v:2793$17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_ibus_stb - connect \B \main_libresocsim_libresoc_ibus_cyc - connect \Y $and$ls180.v:2793$17_Y - end - attribute \src "ls180.v:2811.9-2811.80" - cell $and $and$ls180.v:2811$24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_ibus_stb - connect \B \main_libresocsim_libresoc_ibus_cyc - connect \Y $and$ls180.v:2811$24_Y - end - attribute \src "ls180.v:2853.9-2853.80" - cell $and $and$ls180.v:2853$28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_dbus_stb - connect \B \main_libresocsim_libresoc_dbus_cyc - connect \Y $and$ls180.v:2853$28_Y - end - attribute \src "ls180.v:2871.9-2871.80" - cell $and $and$ls180.v:2871$35 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_dbus_stb - connect \B \main_libresocsim_libresoc_dbus_cyc - connect \Y $and$ls180.v:2871$35_Y - end - attribute \src "ls180.v:2913.9-2913.86" - cell $and $and$ls180.v:2913$39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_jtag_wb_stb - connect \B \main_libresocsim_libresoc_jtag_wb_cyc - connect \Y $and$ls180.v:2913$39_Y - end - attribute \src "ls180.v:2931.9-2931.86" - cell $and $and$ls180.v:2931$46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_jtag_wb_stb - connect \B \main_libresocsim_libresoc_jtag_wb_cyc - connect \Y $and$ls180.v:2931$46_Y - end - attribute \src "ls180.v:2941.31-2941.90" - cell $and $and$ls180.v:2941$48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2941$48_Y - end - attribute \src "ls180.v:2941.30-2941.121" - cell $and $and$ls180.v:2941$49 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2941$48_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2941$49_Y - end - attribute \src "ls180.v:2941.29-2941.156" - cell $and $and$ls180.v:2941$50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2941$49_Y - connect \B \main_libresocsim_ram_bus_sel [0] - connect \Y $and$ls180.v:2941$50_Y - end - attribute \src "ls180.v:2942.31-2942.90" - cell $and $and$ls180.v:2942$51 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2942$51_Y - end - attribute \src "ls180.v:2942.30-2942.121" - cell $and $and$ls180.v:2942$52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2942$51_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2942$52_Y - end - attribute \src "ls180.v:2942.29-2942.156" - cell $and $and$ls180.v:2942$53 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2942$52_Y - connect \B \main_libresocsim_ram_bus_sel [1] - connect \Y $and$ls180.v:2942$53_Y - end - attribute \src "ls180.v:2943.31-2943.90" - cell $and $and$ls180.v:2943$54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2943$54_Y - end - attribute \src "ls180.v:2943.30-2943.121" - cell $and $and$ls180.v:2943$55 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2943$54_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2943$55_Y - end - attribute \src "ls180.v:2943.29-2943.156" - cell $and $and$ls180.v:2943$56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2943$55_Y - connect \B \main_libresocsim_ram_bus_sel [2] - connect \Y $and$ls180.v:2943$56_Y - end - attribute \src "ls180.v:2944.31-2944.90" - cell $and $and$ls180.v:2944$57 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2944$57_Y - end - attribute \src "ls180.v:2944.30-2944.121" - cell $and $and$ls180.v:2944$58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2944$57_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2944$58_Y - end - attribute \src "ls180.v:2944.29-2944.156" - cell $and $and$ls180.v:2944$59 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2944$58_Y - connect \B \main_libresocsim_ram_bus_sel [3] - connect \Y $and$ls180.v:2944$59_Y - end - attribute \src "ls180.v:2953.7-2953.89" - cell $and $and$ls180.v:2953$62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_eventmanager_pending_re - connect \B \main_libresocsim_eventmanager_pending_r - connect \Y $and$ls180.v:2953$62_Y - end - attribute \src "ls180.v:2958.32-2958.111" - cell $and $and$ls180.v:2958$63 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_eventmanager_pending_w - connect \B \main_libresocsim_eventmanager_storage - connect \Y $and$ls180.v:2958$63_Y - end - attribute \src "ls180.v:3072.40-3072.99" - cell $and $and$ls180.v:3072$70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_issue_re - connect \B \main_sdram_command_storage [4] - connect \Y $and$ls180.v:3072$70_Y - end - attribute \src "ls180.v:3073.40-3073.99" - cell $and $and$ls180.v:3073$71 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_issue_re - connect \B \main_sdram_command_storage [5] - connect \Y $and$ls180.v:3073$71_Y - end - attribute \src "ls180.v:3111.38-3111.103" - cell $and $and$ls180.v:3111$77 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_done1 - connect \B $eq$ls180.v:3111$76_Y - connect \Y $and$ls180.v:3111$77_Y - end - attribute \src "ls180.v:3165.50-3165.119" - cell $and $and$ls180.v:3165$85 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3165$85_Y - end - attribute \src "ls180.v:3165.49-3165.167" - cell $and $and$ls180.v:3165$86 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3165$85_Y - connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3165$86_Y - end - attribute \src "ls180.v:3166.49-3166.118" - cell $and $and$ls180.v:3166$87 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3166$87_Y - end - attribute \src "ls180.v:3166.48-3166.154" - cell $and $and$ls180.v:3166$88 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3166$87_Y - connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3166$88_Y - end - attribute \src "ls180.v:3167.50-3167.119" - cell $and $and$ls180.v:3167$89 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3167$89_Y - end - attribute \src "ls180.v:3167.49-3167.155" - cell $and $and$ls180.v:3167$90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3167$89_Y - connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3167$90_Y - end - attribute \src "ls180.v:3170.7-3170.114" - cell $and $and$ls180.v:3170$92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $and$ls180.v:3170$92_Y - end - attribute \src "ls180.v:3199.66-3199.246" - cell $and $and$ls180.v:3199$98 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B $or$ls180.v:3199$97_Y - connect \Y $and$ls180.v:3199$98_Y - end - attribute \src "ls180.v:3200.64-3200.187" - cell $and $and$ls180.v:3200$99 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - connect \Y $and$ls180.v:3200$99_Y - end - attribute \src "ls180.v:3224.9-3224.86" - cell $and $and$ls180.v:3224$105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3224$105_Y - end - attribute \src "ls180.v:3236.9-3236.86" - cell $and $and$ls180.v:3236$106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3236$106_Y - end - attribute \src "ls180.v:3286.13-3286.87" - cell $and $and$ls180.v:3286$108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_ready - connect \B \main_sdram_bankmachine0_auto_precharge - connect \Y $and$ls180.v:3286$108_Y - end - attribute \src "ls180.v:3322.50-3322.119" - cell $and $and$ls180.v:3322$115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3322$115_Y - end - attribute \src "ls180.v:3322.49-3322.167" - cell $and $and$ls180.v:3322$116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3322$115_Y - connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3322$116_Y - end - attribute \src "ls180.v:3323.49-3323.118" - cell $and $and$ls180.v:3323$117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3323$117_Y - end - attribute \src "ls180.v:3323.48-3323.154" - cell $and $and$ls180.v:3323$118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3323$117_Y - connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3323$118_Y - end - attribute \src "ls180.v:3324.50-3324.119" - cell $and $and$ls180.v:3324$119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3324$119_Y - end - attribute \src "ls180.v:3324.49-3324.155" - cell $and $and$ls180.v:3324$120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3324$119_Y - connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3324$120_Y - end - attribute \src "ls180.v:3327.7-3327.114" - cell $and $and$ls180.v:3327$122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $and$ls180.v:3327$122_Y - end - attribute \src "ls180.v:3356.66-3356.246" - cell $and $and$ls180.v:3356$128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B $or$ls180.v:3356$127_Y - connect \Y $and$ls180.v:3356$128_Y - end - attribute \src "ls180.v:3357.64-3357.187" - cell $and $and$ls180.v:3357$129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - connect \Y $and$ls180.v:3357$129_Y - end - attribute \src "ls180.v:3381.9-3381.86" - cell $and $and$ls180.v:3381$135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3381$135_Y - end - attribute \src "ls180.v:3393.9-3393.86" - cell $and $and$ls180.v:3393$136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3393$136_Y - end - attribute \src "ls180.v:3443.13-3443.87" - cell $and $and$ls180.v:3443$138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_ready - connect \B \main_sdram_bankmachine1_auto_precharge - connect \Y $and$ls180.v:3443$138_Y - end - attribute \src "ls180.v:3479.50-3479.119" - cell $and $and$ls180.v:3479$145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3479$145_Y - end - attribute \src "ls180.v:3479.49-3479.167" - cell $and $and$ls180.v:3479$146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3479$145_Y - connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3479$146_Y - end - attribute \src "ls180.v:3480.49-3480.118" - cell $and $and$ls180.v:3480$147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3480$147_Y - end - attribute \src "ls180.v:3480.48-3480.154" - cell $and $and$ls180.v:3480$148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3480$147_Y - connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3480$148_Y - end - attribute \src "ls180.v:3481.50-3481.119" - cell $and $and$ls180.v:3481$149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3481$149_Y - end - attribute \src "ls180.v:3481.49-3481.155" - cell $and $and$ls180.v:3481$150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3481$149_Y - connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3481$150_Y - end - attribute \src "ls180.v:3484.7-3484.114" - cell $and $and$ls180.v:3484$152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $and$ls180.v:3484$152_Y - end - attribute \src "ls180.v:3513.66-3513.246" - cell $and $and$ls180.v:3513$158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B $or$ls180.v:3513$157_Y - connect \Y $and$ls180.v:3513$158_Y - end - attribute \src "ls180.v:3514.64-3514.187" - cell $and $and$ls180.v:3514$159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - connect \Y $and$ls180.v:3514$159_Y - end - attribute \src "ls180.v:3538.9-3538.86" - cell $and $and$ls180.v:3538$165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3538$165_Y - end - attribute \src "ls180.v:3550.9-3550.86" - cell $and $and$ls180.v:3550$166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3550$166_Y - end - attribute \src "ls180.v:3600.13-3600.87" - cell $and $and$ls180.v:3600$168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_ready - connect \B \main_sdram_bankmachine2_auto_precharge - connect \Y $and$ls180.v:3600$168_Y - end - attribute \src "ls180.v:3636.50-3636.119" - cell $and $and$ls180.v:3636$175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3636$175_Y - end - attribute \src "ls180.v:3636.49-3636.167" - cell $and $and$ls180.v:3636$176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3636$175_Y - connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3636$176_Y - end - attribute \src "ls180.v:3637.49-3637.118" - cell $and $and$ls180.v:3637$177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3637$177_Y - end - attribute \src "ls180.v:3637.48-3637.154" - cell $and $and$ls180.v:3637$178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3637$177_Y - connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3637$178_Y - end - attribute \src "ls180.v:3638.50-3638.119" - cell $and $and$ls180.v:3638$179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3638$179_Y - end - attribute \src "ls180.v:3638.49-3638.155" - cell $and $and$ls180.v:3638$180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3638$179_Y - connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3638$180_Y - end - attribute \src "ls180.v:3641.7-3641.114" - cell $and $and$ls180.v:3641$182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $and$ls180.v:3641$182_Y - end - attribute \src "ls180.v:3670.66-3670.246" - cell $and $and$ls180.v:3670$188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B $or$ls180.v:3670$187_Y - connect \Y $and$ls180.v:3670$188_Y - end - attribute \src "ls180.v:3671.64-3671.187" - cell $and $and$ls180.v:3671$189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - connect \Y $and$ls180.v:3671$189_Y - end - attribute \src "ls180.v:3695.9-3695.86" - cell $and $and$ls180.v:3695$195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3695$195_Y - end - attribute \src "ls180.v:3707.9-3707.86" - cell $and $and$ls180.v:3707$196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3707$196_Y - end - attribute \src "ls180.v:3757.13-3757.87" - cell $and $and$ls180.v:3757$198 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_ready - connect \B \main_sdram_bankmachine3_auto_precharge - connect \Y $and$ls180.v:3757$198_Y - end - attribute \src "ls180.v:3772.37-3772.102" - cell $and $and$ls180.v:3772$199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3772$199_Y - end - attribute \src "ls180.v:3772.108-3772.188" - cell $and $and$ls180.v:3772$201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3772$200_Y - connect \Y $and$ls180.v:3772$201_Y - end - attribute \src "ls180.v:3772.107-3772.231" - cell $and $and$ls180.v:3772$203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3772$201_Y - connect \B $not$ls180.v:3772$202_Y - connect \Y $and$ls180.v:3772$203_Y - end - attribute \src "ls180.v:3772.36-3772.232" - cell $and $and$ls180.v:3772$204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3772$199_Y - connect \B $and$ls180.v:3772$203_Y - connect \Y $and$ls180.v:3772$204_Y - end - attribute \src "ls180.v:3773.37-3773.102" - cell $and $and$ls180.v:3773$205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3773$205_Y - end - attribute \src "ls180.v:3773.108-3773.188" - cell $and $and$ls180.v:3773$207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3773$206_Y - connect \Y $and$ls180.v:3773$207_Y - end - attribute \src "ls180.v:3773.107-3773.231" - cell $and $and$ls180.v:3773$209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3773$207_Y - connect \B $not$ls180.v:3773$208_Y - connect \Y $and$ls180.v:3773$209_Y - end - attribute \src "ls180.v:3773.36-3773.232" - cell $and $and$ls180.v:3773$210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3773$205_Y - connect \B $and$ls180.v:3773$209_Y - connect \Y $and$ls180.v:3773$210_Y - end - attribute \src "ls180.v:3774.34-3774.85" - cell $and $and$ls180.v:3774$211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_trrdcon_ready - connect \B \main_sdram_tfawcon_ready - connect \Y $and$ls180.v:3774$211_Y - end - attribute \src "ls180.v:3775.37-3775.102" - cell $and $and$ls180.v:3775$212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3775$212_Y - end - attribute \src "ls180.v:3775.36-3775.194" - cell $and $and$ls180.v:3775$214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3775$212_Y - connect \B $or$ls180.v:3775$213_Y - connect \Y $and$ls180.v:3775$214_Y - end - attribute \src "ls180.v:3777.37-3777.102" - cell $and $and$ls180.v:3777$215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3777$215_Y - end - attribute \src "ls180.v:3777.36-3777.148" - cell $and $and$ls180.v:3777$216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3777$215_Y - connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:3777$216_Y - end - attribute \src "ls180.v:3778.40-3778.119" - cell $and $and$ls180.v:3778$217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_payload_is_read - connect \Y $and$ls180.v:3778$217_Y - end - attribute \src "ls180.v:3778.124-3778.203" - cell $and $and$ls180.v:3778$218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_payload_is_read - connect \Y $and$ls180.v:3778$218_Y - end - attribute \src "ls180.v:3778.209-3778.288" - cell $and $and$ls180.v:3778$220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_payload_is_read - connect \Y $and$ls180.v:3778$220_Y - end - attribute \src "ls180.v:3778.294-3778.373" - cell $and $and$ls180.v:3778$222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_payload_is_read - connect \Y $and$ls180.v:3778$222_Y - end - attribute \src "ls180.v:3779.41-3779.121" - cell $and $and$ls180.v:3779$224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3779$224_Y - end - attribute \src "ls180.v:3779.126-3779.206" - cell $and $and$ls180.v:3779$225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3779$225_Y - end - attribute \src "ls180.v:3779.212-3779.292" - cell $and $and$ls180.v:3779$227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3779$227_Y - end - attribute \src "ls180.v:3779.298-3779.378" - cell $and $and$ls180.v:3779$229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3779$229_Y - end - attribute \src "ls180.v:3786.38-3786.111" - cell $and $and$ls180.v:3786$233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_refresh_gnt - connect \B \main_sdram_bankmachine1_refresh_gnt - connect \Y $and$ls180.v:3786$233_Y - end - attribute \src "ls180.v:3786.37-3786.150" - cell $and $and$ls180.v:3786$234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3786$233_Y - connect \B \main_sdram_bankmachine2_refresh_gnt - connect \Y $and$ls180.v:3786$234_Y - end - attribute \src "ls180.v:3786.36-3786.189" - cell $and $and$ls180.v:3786$235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3786$234_Y - connect \B \main_sdram_bankmachine3_refresh_gnt - connect \Y $and$ls180.v:3786$235_Y - end - attribute \src "ls180.v:3792.77-3792.153" - cell $and $and$ls180.v:3792$238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3792$238_Y - end - attribute \src "ls180.v:3792.162-3792.246" - cell $and $and$ls180.v:3792$240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3792$239_Y - connect \Y $and$ls180.v:3792$240_Y - end - attribute \src "ls180.v:3792.161-3792.291" - cell $and $and$ls180.v:3792$242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3792$240_Y - connect \B $not$ls180.v:3792$241_Y - connect \Y $and$ls180.v:3792$242_Y - end - attribute \src "ls180.v:3792.76-3792.333" - cell $and $and$ls180.v:3792$245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3792$238_Y - connect \B $or$ls180.v:3792$244_Y - connect \Y $and$ls180.v:3792$245_Y - end - attribute \src "ls180.v:3792.338-3792.505" - cell $and $and$ls180.v:3792$248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3792$246_Y - connect \B $eq$ls180.v:3792$247_Y - connect \Y $and$ls180.v:3792$248_Y - end - attribute \src "ls180.v:3792.38-3792.507" - cell $and $and$ls180.v:3792$250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3792$249_Y - connect \Y $and$ls180.v:3792$250_Y - end - attribute \src "ls180.v:3793.77-3793.153" - cell $and $and$ls180.v:3793$251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3793$251_Y - end - attribute \src "ls180.v:3793.162-3793.246" - cell $and $and$ls180.v:3793$253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3793$252_Y - connect \Y $and$ls180.v:3793$253_Y - end - attribute \src "ls180.v:3793.161-3793.291" - cell $and $and$ls180.v:3793$255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3793$253_Y - connect \B $not$ls180.v:3793$254_Y - connect \Y $and$ls180.v:3793$255_Y - end - attribute \src "ls180.v:3793.76-3793.333" - cell $and $and$ls180.v:3793$258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3793$251_Y - connect \B $or$ls180.v:3793$257_Y - connect \Y $and$ls180.v:3793$258_Y - end - attribute \src "ls180.v:3793.338-3793.505" - cell $and $and$ls180.v:3793$261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3793$259_Y - connect \B $eq$ls180.v:3793$260_Y - connect \Y $and$ls180.v:3793$261_Y - end - attribute \src "ls180.v:3793.38-3793.507" - cell $and $and$ls180.v:3793$263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3793$262_Y - connect \Y $and$ls180.v:3793$263_Y - end - attribute \src "ls180.v:3794.77-3794.153" - cell $and $and$ls180.v:3794$264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3794$264_Y - end - attribute \src "ls180.v:3794.162-3794.246" - cell $and $and$ls180.v:3794$266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3794$265_Y - connect \Y $and$ls180.v:3794$266_Y - end - attribute \src "ls180.v:3794.161-3794.291" - cell $and $and$ls180.v:3794$268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3794$266_Y - connect \B $not$ls180.v:3794$267_Y - connect \Y $and$ls180.v:3794$268_Y - end - attribute \src "ls180.v:3794.76-3794.333" - cell $and $and$ls180.v:3794$271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3794$264_Y - connect \B $or$ls180.v:3794$270_Y - connect \Y $and$ls180.v:3794$271_Y - end - attribute \src "ls180.v:3794.338-3794.505" - cell $and $and$ls180.v:3794$274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3794$272_Y - connect \B $eq$ls180.v:3794$273_Y - connect \Y $and$ls180.v:3794$274_Y - end - attribute \src "ls180.v:3794.38-3794.507" - cell $and $and$ls180.v:3794$276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3794$275_Y - connect \Y $and$ls180.v:3794$276_Y - end - attribute \src "ls180.v:3795.77-3795.153" - cell $and $and$ls180.v:3795$277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3795$277_Y - end - attribute \src "ls180.v:3795.162-3795.246" - cell $and $and$ls180.v:3795$279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3795$278_Y - connect \Y $and$ls180.v:3795$279_Y - end - attribute \src "ls180.v:3795.161-3795.291" - cell $and $and$ls180.v:3795$281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3795$279_Y - connect \B $not$ls180.v:3795$280_Y - connect \Y $and$ls180.v:3795$281_Y - end - attribute \src "ls180.v:3795.76-3795.333" - cell $and $and$ls180.v:3795$284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3795$277_Y - connect \B $or$ls180.v:3795$283_Y - connect \Y $and$ls180.v:3795$284_Y - end - attribute \src "ls180.v:3795.338-3795.505" - cell $and $and$ls180.v:3795$287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3795$285_Y - connect \B $eq$ls180.v:3795$286_Y - connect \Y $and$ls180.v:3795$287_Y - end - attribute \src "ls180.v:3795.38-3795.507" - cell $and $and$ls180.v:3795$289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3795$288_Y - connect \Y $and$ls180.v:3795$289_Y - end - attribute \src "ls180.v:3825.77-3825.153" - cell $and $and$ls180.v:3825$296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3825$296_Y - end - attribute \src "ls180.v:3825.162-3825.246" - cell $and $and$ls180.v:3825$298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3825$297_Y - connect \Y $and$ls180.v:3825$298_Y - end - attribute \src "ls180.v:3825.161-3825.291" - cell $and $and$ls180.v:3825$300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3825$298_Y - connect \B $not$ls180.v:3825$299_Y - connect \Y $and$ls180.v:3825$300_Y - end - attribute \src "ls180.v:3825.76-3825.333" - cell $and $and$ls180.v:3825$303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3825$296_Y - connect \B $or$ls180.v:3825$302_Y - connect \Y $and$ls180.v:3825$303_Y - end - attribute \src "ls180.v:3825.338-3825.505" - cell $and $and$ls180.v:3825$306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3825$304_Y - connect \B $eq$ls180.v:3825$305_Y - connect \Y $and$ls180.v:3825$306_Y - end - attribute \src "ls180.v:3825.38-3825.507" - cell $and $and$ls180.v:3825$308 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3825$307_Y - connect \Y $and$ls180.v:3825$308_Y - end - attribute \src "ls180.v:3826.77-3826.153" - cell $and $and$ls180.v:3826$309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3826$309_Y - end - attribute \src "ls180.v:3826.162-3826.246" - cell $and $and$ls180.v:3826$311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3826$310_Y - connect \Y $and$ls180.v:3826$311_Y - end - attribute \src "ls180.v:3826.161-3826.291" - cell $and $and$ls180.v:3826$313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3826$311_Y - connect \B $not$ls180.v:3826$312_Y - connect \Y $and$ls180.v:3826$313_Y - end - attribute \src "ls180.v:3826.76-3826.333" - cell $and $and$ls180.v:3826$316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3826$309_Y - connect \B $or$ls180.v:3826$315_Y - connect \Y $and$ls180.v:3826$316_Y - end - attribute \src "ls180.v:3826.338-3826.505" - cell $and $and$ls180.v:3826$319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3826$317_Y - connect \B $eq$ls180.v:3826$318_Y - connect \Y $and$ls180.v:3826$319_Y - end - attribute \src "ls180.v:3826.38-3826.507" - cell $and $and$ls180.v:3826$321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3826$320_Y - connect \Y $and$ls180.v:3826$321_Y - end - attribute \src "ls180.v:3827.77-3827.153" - cell $and $and$ls180.v:3827$322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3827$322_Y - end - attribute \src "ls180.v:3827.162-3827.246" - cell $and $and$ls180.v:3827$324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3827$323_Y - connect \Y $and$ls180.v:3827$324_Y - end - attribute \src "ls180.v:3827.161-3827.291" - cell $and $and$ls180.v:3827$326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3827$324_Y - connect \B $not$ls180.v:3827$325_Y - connect \Y $and$ls180.v:3827$326_Y - end - attribute \src "ls180.v:3827.76-3827.333" - cell $and $and$ls180.v:3827$329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3827$322_Y - connect \B $or$ls180.v:3827$328_Y - connect \Y $and$ls180.v:3827$329_Y - end - attribute \src "ls180.v:3827.338-3827.505" - cell $and $and$ls180.v:3827$332 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3827$330_Y - connect \B $eq$ls180.v:3827$331_Y - connect \Y $and$ls180.v:3827$332_Y - end - attribute \src "ls180.v:3827.38-3827.507" - cell $and $and$ls180.v:3827$334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3827$333_Y - connect \Y $and$ls180.v:3827$334_Y - end - attribute \src "ls180.v:3828.77-3828.153" - cell $and $and$ls180.v:3828$335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3828$335_Y - end - attribute \src "ls180.v:3828.162-3828.246" - cell $and $and$ls180.v:3828$337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3828$336_Y - connect \Y $and$ls180.v:3828$337_Y - end - attribute \src "ls180.v:3828.161-3828.291" - cell $and $and$ls180.v:3828$339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3828$337_Y - connect \B $not$ls180.v:3828$338_Y - connect \Y $and$ls180.v:3828$339_Y - end - attribute \src "ls180.v:3828.76-3828.333" - cell $and $and$ls180.v:3828$342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3828$335_Y - connect \B $or$ls180.v:3828$341_Y - connect \Y $and$ls180.v:3828$342_Y - end - attribute \src "ls180.v:3828.338-3828.505" - cell $and $and$ls180.v:3828$345 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3828$343_Y - connect \B $eq$ls180.v:3828$344_Y - connect \Y $and$ls180.v:3828$345_Y - end - attribute \src "ls180.v:3828.38-3828.507" - cell $and $and$ls180.v:3828$347 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3828$346_Y - connect \Y $and$ls180.v:3828$347_Y - end - attribute \src "ls180.v:3857.8-3857.73" - cell $and $and$ls180.v:3857$352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3857$352_Y - end - attribute \src "ls180.v:3857.7-3857.114" - cell $and $and$ls180.v:3857$354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3857$352_Y - connect \B $eq$ls180.v:3857$353_Y - connect \Y $and$ls180.v:3857$354_Y - end - attribute \src "ls180.v:3860.8-3860.73" - cell $and $and$ls180.v:3860$355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3860$355_Y - end - attribute \src "ls180.v:3860.7-3860.114" - cell $and $and$ls180.v:3860$357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3860$355_Y - connect \B $eq$ls180.v:3860$356_Y - connect \Y $and$ls180.v:3860$357_Y - end - attribute \src "ls180.v:3866.8-3866.73" - cell $and $and$ls180.v:3866$359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3866$359_Y - end - attribute \src "ls180.v:3866.7-3866.114" - cell $and $and$ls180.v:3866$361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3866$359_Y - connect \B $eq$ls180.v:3866$360_Y - connect \Y $and$ls180.v:3866$361_Y - end - attribute \src "ls180.v:3869.8-3869.73" - cell $and $and$ls180.v:3869$362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3869$362_Y - end - attribute \src "ls180.v:3869.7-3869.114" - cell $and $and$ls180.v:3869$364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3869$362_Y - connect \B $eq$ls180.v:3869$363_Y - connect \Y $and$ls180.v:3869$364_Y - end - attribute \src "ls180.v:3875.8-3875.73" - cell $and $and$ls180.v:3875$366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3875$366_Y - end - attribute \src "ls180.v:3875.7-3875.114" - cell $and $and$ls180.v:3875$368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3875$366_Y - connect \B $eq$ls180.v:3875$367_Y - connect \Y $and$ls180.v:3875$368_Y - end - attribute \src "ls180.v:3878.8-3878.73" - cell $and $and$ls180.v:3878$369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3878$369_Y - end - attribute \src "ls180.v:3878.7-3878.114" - cell $and $and$ls180.v:3878$371 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3878$369_Y - connect \B $eq$ls180.v:3878$370_Y - connect \Y $and$ls180.v:3878$371_Y - end - attribute \src "ls180.v:3884.8-3884.73" - cell $and $and$ls180.v:3884$373 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3884$373_Y - end - attribute \src "ls180.v:3884.7-3884.114" - cell $and $and$ls180.v:3884$375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3884$373_Y - connect \B $eq$ls180.v:3884$374_Y - connect \Y $and$ls180.v:3884$375_Y - end - attribute \src "ls180.v:3887.8-3887.73" - cell $and $and$ls180.v:3887$376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3887$376_Y - end - attribute \src "ls180.v:3887.7-3887.114" - cell $and $and$ls180.v:3887$378 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3887$376_Y - connect \B $eq$ls180.v:3887$377_Y - connect \Y $and$ls180.v:3887$378_Y - end - attribute \src "ls180.v:3912.71-3912.151" - cell $and $and$ls180.v:3912$383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3912$382_Y - connect \Y $and$ls180.v:3912$383_Y - end - attribute \src "ls180.v:3912.70-3912.194" - cell $and $and$ls180.v:3912$385 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3912$383_Y - connect \B $not$ls180.v:3912$384_Y - connect \Y $and$ls180.v:3912$385_Y - end - attribute \src "ls180.v:3912.41-3912.222" - cell $and $and$ls180.v:3912$388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:3912$387_Y - connect \Y $and$ls180.v:3912$388_Y - end - attribute \src "ls180.v:3950.71-3950.151" - cell $and $and$ls180.v:3950$392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3950$391_Y - connect \Y $and$ls180.v:3950$392_Y - end - attribute \src "ls180.v:3950.70-3950.194" - cell $and $and$ls180.v:3950$394 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3950$392_Y - connect \B $not$ls180.v:3950$393_Y - connect \Y $and$ls180.v:3950$394_Y - end - attribute \src "ls180.v:3950.41-3950.222" - cell $and $and$ls180.v:3950$397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:3950$396_Y - connect \Y $and$ls180.v:3950$397_Y - end - attribute \src "ls180.v:3968.110-3968.179" - cell $and $and$ls180.v:3968$402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3968$401_Y - connect \Y $and$ls180.v:3968$402_Y - end - attribute \src "ls180.v:3968.185-3968.254" - cell $and $and$ls180.v:3968$405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3968$404_Y - connect \Y $and$ls180.v:3968$405_Y - end - attribute \src "ls180.v:3968.260-3968.329" - cell $and $and$ls180.v:3968$408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3968$407_Y - connect \Y $and$ls180.v:3968$408_Y - end - attribute \src "ls180.v:3968.41-3968.332" - cell $and $and$ls180.v:3968$411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3968$400_Y - connect \B $not$ls180.v:3968$410_Y - connect \Y $and$ls180.v:3968$411_Y - end - attribute \src "ls180.v:3968.40-3968.355" - cell $and $and$ls180.v:3968$412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3968$411_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3968$412_Y - end - attribute \src "ls180.v:3969.34-3969.106" - cell $and $and$ls180.v:3969$415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3969$413_Y - connect \B $not$ls180.v:3969$414_Y - connect \Y $and$ls180.v:3969$415_Y - end - attribute \src "ls180.v:3973.110-3973.179" - cell $and $and$ls180.v:3973$418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3973$417_Y - connect \Y $and$ls180.v:3973$418_Y - end - attribute \src "ls180.v:3973.185-3973.254" - cell $and $and$ls180.v:3973$421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3973$420_Y - connect \Y $and$ls180.v:3973$421_Y - end - attribute \src "ls180.v:3973.260-3973.329" - cell $and $and$ls180.v:3973$424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3973$423_Y - connect \Y $and$ls180.v:3973$424_Y - end - attribute \src "ls180.v:3973.41-3973.332" - cell $and $and$ls180.v:3973$427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3973$416_Y - connect \B $not$ls180.v:3973$426_Y - connect \Y $and$ls180.v:3973$427_Y - end - attribute \src "ls180.v:3973.40-3973.355" - cell $and $and$ls180.v:3973$428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3973$427_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3973$428_Y - end - attribute \src "ls180.v:3974.34-3974.106" - cell $and $and$ls180.v:3974$431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3974$429_Y - connect \B $not$ls180.v:3974$430_Y - connect \Y $and$ls180.v:3974$431_Y - end - attribute \src "ls180.v:3978.110-3978.179" - cell $and $and$ls180.v:3978$434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3978$433_Y - connect \Y $and$ls180.v:3978$434_Y - end - attribute \src "ls180.v:3978.185-3978.254" - cell $and $and$ls180.v:3978$437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3978$436_Y - connect \Y $and$ls180.v:3978$437_Y - end - attribute \src "ls180.v:3978.260-3978.329" - cell $and $and$ls180.v:3978$440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3978$439_Y - connect \Y $and$ls180.v:3978$440_Y - end - attribute \src "ls180.v:3978.41-3978.332" - cell $and $and$ls180.v:3978$443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3978$432_Y - connect \B $not$ls180.v:3978$442_Y - connect \Y $and$ls180.v:3978$443_Y - end - attribute \src "ls180.v:3978.40-3978.355" - cell $and $and$ls180.v:3978$444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3978$443_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3978$444_Y - end - attribute \src "ls180.v:3979.34-3979.106" - cell $and $and$ls180.v:3979$447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3979$445_Y - connect \B $not$ls180.v:3979$446_Y - connect \Y $and$ls180.v:3979$447_Y - end - attribute \src "ls180.v:3983.110-3983.179" - cell $and $and$ls180.v:3983$450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3983$449_Y - connect \Y $and$ls180.v:3983$450_Y - end - attribute \src "ls180.v:3983.185-3983.254" - cell $and $and$ls180.v:3983$453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3983$452_Y - connect \Y $and$ls180.v:3983$453_Y - end - attribute \src "ls180.v:3983.260-3983.329" - cell $and $and$ls180.v:3983$456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3983$455_Y - connect \Y $and$ls180.v:3983$456_Y - end - attribute \src "ls180.v:3983.41-3983.332" - cell $and $and$ls180.v:3983$459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3983$448_Y - connect \B $not$ls180.v:3983$458_Y - connect \Y $and$ls180.v:3983$459_Y - end - attribute \src "ls180.v:3983.40-3983.355" - cell $and $and$ls180.v:3983$460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3983$459_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3983$460_Y - end - attribute \src "ls180.v:3984.34-3984.106" - cell $and $and$ls180.v:3984$463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3984$461_Y - connect \B $not$ls180.v:3984$462_Y - connect \Y $and$ls180.v:3984$463_Y - end - attribute \src "ls180.v:3988.151-3988.220" - cell $and $and$ls180.v:3988$467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3988$466_Y - connect \Y $and$ls180.v:3988$467_Y - end - attribute \src "ls180.v:3988.226-3988.295" - cell $and $and$ls180.v:3988$470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3988$469_Y - connect \Y $and$ls180.v:3988$470_Y - end - attribute \src "ls180.v:3988.301-3988.370" - cell $and $and$ls180.v:3988$473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3988$472_Y - connect \Y $and$ls180.v:3988$473_Y - end - attribute \src "ls180.v:3988.82-3988.373" - cell $and $and$ls180.v:3988$476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3988$465_Y - connect \B $not$ls180.v:3988$475_Y - connect \Y $and$ls180.v:3988$476_Y - end - attribute \src "ls180.v:3988.43-3988.374" - cell $and $and$ls180.v:3988$477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3988$464_Y - connect \B $and$ls180.v:3988$476_Y - connect \Y $and$ls180.v:3988$477_Y - end - attribute \src "ls180.v:3988.42-3988.410" - cell $and $and$ls180.v:3988$478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3988$477_Y - connect \B \main_sdram_interface_bank0_ready - connect \Y $and$ls180.v:3988$478_Y - end - attribute \src "ls180.v:3988.525-3988.594" - cell $and $and$ls180.v:3988$483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3988$482_Y - connect \Y $and$ls180.v:3988$483_Y - end - attribute \src "ls180.v:3988.600-3988.669" - cell $and $and$ls180.v:3988$486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3988$485_Y - connect \Y $and$ls180.v:3988$486_Y - end - attribute \src "ls180.v:3988.675-3988.744" - cell $and $and$ls180.v:3988$489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3988$488_Y - connect \Y $and$ls180.v:3988$489_Y - end - attribute \src "ls180.v:3988.456-3988.747" - cell $and $and$ls180.v:3988$492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3988$481_Y - connect \B $not$ls180.v:3988$491_Y - connect \Y $and$ls180.v:3988$492_Y - end - attribute \src "ls180.v:3988.417-3988.748" - cell $and $and$ls180.v:3988$493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3988$480_Y - connect \B $and$ls180.v:3988$492_Y - connect \Y $and$ls180.v:3988$493_Y - end - attribute \src "ls180.v:3988.416-3988.784" - cell $and $and$ls180.v:3988$494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3988$493_Y - connect \B \main_sdram_interface_bank1_ready - connect \Y $and$ls180.v:3988$494_Y - end - attribute \src "ls180.v:3988.899-3988.968" - cell $and $and$ls180.v:3988$499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3988$498_Y - connect \Y $and$ls180.v:3988$499_Y - end - attribute \src "ls180.v:3988.974-3988.1043" - cell $and $and$ls180.v:3988$502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3988$501_Y - connect \Y $and$ls180.v:3988$502_Y - end - attribute \src "ls180.v:3988.1049-3988.1118" - cell $and $and$ls180.v:3988$505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3988$504_Y - connect \Y $and$ls180.v:3988$505_Y - end - attribute \src "ls180.v:3988.830-3988.1121" - cell $and $and$ls180.v:3988$508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3988$497_Y - connect \B $not$ls180.v:3988$507_Y - connect \Y $and$ls180.v:3988$508_Y - end - attribute \src "ls180.v:3988.791-3988.1122" - cell $and $and$ls180.v:3988$509 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3988$496_Y - connect \B $and$ls180.v:3988$508_Y - connect \Y $and$ls180.v:3988$509_Y - end - attribute \src "ls180.v:3988.790-3988.1158" - cell $and $and$ls180.v:3988$510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3988$509_Y - connect \B \main_sdram_interface_bank2_ready - connect \Y $and$ls180.v:3988$510_Y - end - attribute \src "ls180.v:3988.1273-3988.1342" - cell $and $and$ls180.v:3988$515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3988$514_Y - connect \Y $and$ls180.v:3988$515_Y - end - attribute \src "ls180.v:3988.1348-3988.1417" - cell $and $and$ls180.v:3988$518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3988$517_Y - connect \Y $and$ls180.v:3988$518_Y - end - attribute \src "ls180.v:3988.1423-3988.1492" - cell $and $and$ls180.v:3988$521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3988$520_Y - connect \Y $and$ls180.v:3988$521_Y - end - attribute \src "ls180.v:3988.1204-3988.1495" - cell $and $and$ls180.v:3988$524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3988$513_Y - connect \B $not$ls180.v:3988$523_Y - connect \Y $and$ls180.v:3988$524_Y - end - attribute \src "ls180.v:3988.1165-3988.1496" - cell $and $and$ls180.v:3988$525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3988$512_Y - connect \B $and$ls180.v:3988$524_Y - connect \Y $and$ls180.v:3988$525_Y - end - attribute \src "ls180.v:3988.1164-3988.1532" - cell $and $and$ls180.v:3988$526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3988$525_Y - connect \B \main_sdram_interface_bank3_ready - connect \Y $and$ls180.v:3988$526_Y - end - attribute \src "ls180.v:4046.9-4046.46" - cell $and $and$ls180.v:4046$532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_stb - connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4046$532_Y - end - attribute \src "ls180.v:4064.9-4064.46" - cell $and $and$ls180.v:4064$539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_stb - connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4064$539_Y - end - attribute \src "ls180.v:4077.32-4077.75" - cell $and $and$ls180.v:4077$543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_cyc - connect \B \main_litedram_wb_stb - connect \Y $and$ls180.v:4077$543_Y - end - attribute \src "ls180.v:4077.31-4077.99" - cell $and $and$ls180.v:4077$545 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4077$543_Y - connect \B $not$ls180.v:4077$544_Y - connect \Y $and$ls180.v:4077$545_Y - end - attribute \src "ls180.v:4078.34-4078.102" - cell $and $and$ls180.v:4078$547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4078$546_Y - connect \B \main_port_cmd_payload_we - connect \Y $and$ls180.v:4078$547_Y - end - attribute \src "ls180.v:4078.33-4078.128" - cell $and $and$ls180.v:4078$549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4078$547_Y - connect \B $not$ls180.v:4078$548_Y - connect \Y $and$ls180.v:4078$549_Y - end - attribute \src "ls180.v:4079.33-4079.104" - cell $and $and$ls180.v:4079$552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$550_Y - connect \B $not$ls180.v:4079$551_Y - connect \Y $and$ls180.v:4079$552_Y - end - attribute \src "ls180.v:4080.49-4080.85" - cell $and $and$ls180.v:4080$553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_we - connect \B \main_ack_wdata - connect \Y $and$ls180.v:4080$553_Y - end - attribute \src "ls180.v:4080.90-4080.129" - cell $and $and$ls180.v:4080$555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4080$554_Y - connect \B \main_ack_rdata - connect \Y $and$ls180.v:4080$555_Y - end - attribute \src "ls180.v:4080.32-4080.131" - cell $and $and$ls180.v:4080$557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_ack_cmd - connect \B $or$ls180.v:4080$556_Y - connect \Y $and$ls180.v:4080$557_Y - end - attribute \src "ls180.v:4081.25-4081.66" - cell $and $and$ls180.v:4081$558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:4081$558_Y - end - attribute \src "ls180.v:4082.27-4082.72" - cell $and $and$ls180.v:4082$560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_wdata_valid - connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:4082$560_Y - end - attribute \src "ls180.v:4083.26-4083.71" - cell $and $and$ls180.v:4083$562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_rdata_valid - connect \B \main_port_rdata_ready - connect \Y $and$ls180.v:4083$562_Y - end - attribute \src "ls180.v:4112.64-4112.88" - cell $and $and$ls180.v:4112$568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B \main_uart_rxtx_we - connect \Y $and$ls180.v:4112$568_Y - end - attribute \src "ls180.v:4116.7-4116.78" - cell $and $and$ls180.v:4116$572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_eventmanager_pending_re - connect \B \main_uart_eventmanager_pending_r [0] - connect \Y $and$ls180.v:4116$572_Y - end - attribute \src "ls180.v:4127.7-4127.78" - cell $and $and$ls180.v:4127$575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_eventmanager_pending_re - connect \B \main_uart_eventmanager_pending_r [1] - connect \Y $and$ls180.v:4127$575_Y - end - attribute \src "ls180.v:4136.26-4136.97" - cell $and $and$ls180.v:4136$577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_eventmanager_pending_w [0] - connect \B \main_uart_eventmanager_storage [0] - connect \Y $and$ls180.v:4136$577_Y - end - attribute \src "ls180.v:4136.102-4136.173" - cell $and $and$ls180.v:4136$578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_eventmanager_pending_w [1] - connect \B \main_uart_eventmanager_storage [1] - connect \Y $and$ls180.v:4136$578_Y - end - attribute \src "ls180.v:4151.41-4151.133" - cell $and $and$ls180.v:4151$582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_readable - connect \B $or$ls180.v:4151$581_Y - connect \Y $and$ls180.v:4151$582_Y - end - attribute \src "ls180.v:4162.39-4162.136" - cell $and $and$ls180.v:4162$587 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_we - connect \B $or$ls180.v:4162$586_Y - connect \Y $and$ls180.v:4162$587_Y - end - attribute \src "ls180.v:4163.37-4163.104" - cell $and $and$ls180.v:4163$588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_readable - connect \B \main_uart_tx_fifo_syncfifo_re - connect \Y $and$ls180.v:4163$588_Y - end - attribute \src "ls180.v:4181.41-4181.133" - cell $and $and$ls180.v:4181$593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_readable - connect \B $or$ls180.v:4181$592_Y - connect \Y $and$ls180.v:4181$593_Y - end - attribute \src "ls180.v:4192.39-4192.136" - cell $and $and$ls180.v:4192$598 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_we - connect \B $or$ls180.v:4192$597_Y - connect \Y $and$ls180.v:4192$598_Y - end - attribute \src "ls180.v:4193.37-4193.104" - cell $and $and$ls180.v:4193$599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_readable - connect \B \main_uart_rx_fifo_syncfifo_re - connect \Y $and$ls180.v:4193$599_Y - end - attribute \src "ls180.v:4322.33-4322.86" - cell $and $and$ls180.v:4322$633 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_clocker_clk1 - connect \B $not$ls180.v:4322$632_Y - connect \Y $and$ls180.v:4322$633_Y - end - attribute \src "ls180.v:4426.9-4426.68" - cell $and $and$ls180.v:4426$642 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdw_sink_valid - connect \B \main_sdphy_cmdw_pads_out_ready - connect \Y $and$ls180.v:4426$642_Y - end - attribute \src "ls180.v:4446.53-4446.145" - cell $and $and$ls180.v:4446$645 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_pads_in_valid - connect \B $or$ls180.v:4446$644_Y - connect \Y $and$ls180.v:4446$645_Y - end - attribute \src "ls180.v:4465.52-4465.137" - cell $and $and$ls180.v:4465$648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid - connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:4465$648_Y - end - attribute \src "ls180.v:4506.9-4506.68" - cell $and $and$ls180.v:4506$656 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_source_valid - connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4506$656_Y - end - attribute \src "ls180.v:4544.9-4544.68" - cell $and $and$ls180.v:4544$662 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_source_valid - connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4544$662_Y - end - attribute \src "ls180.v:4553.10-4553.69" - cell $and $and$ls180.v:4553$663 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_sink_valid - connect \B \main_sdphy_cmdr_pads_out_ready - connect \Y $and$ls180.v:4553$663_Y - end - attribute \src "ls180.v:4553.9-4553.93" - cell $and $and$ls180.v:4553$664 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4553$663_Y - connect \B \main_sdphy_cmdw_done - connect \Y $and$ls180.v:4553$664_Y - end - attribute \src "ls180.v:4573.54-4573.117" - cell $and $and$ls180.v:4573$666 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_pads_in_valid - connect \B \main_sdphy_dataw_crcr_run - connect \Y $and$ls180.v:4573$666_Y - end - attribute \src "ls180.v:4592.53-4592.140" - cell $and $and$ls180.v:4592$669 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_valid - connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:4592$669_Y - end - attribute \src "ls180.v:4689.9-4689.70" - cell $and $and$ls180.v:4689$679 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_sink_valid - connect \B \main_sdphy_dataw_pads_out_ready - connect \Y $and$ls180.v:4689$679_Y - end - attribute \src "ls180.v:4707.55-4707.120" - cell $and $and$ls180.v:4707$681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_pads_in_valid - connect \B \main_sdphy_datar_datar_run - connect \Y $and$ls180.v:4707$681_Y - end - attribute \src "ls180.v:4726.54-4726.143" - cell $and $and$ls180.v:4726$684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_valid - connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:4726$684_Y - end - attribute \src "ls180.v:4808.9-4808.70" - cell $and $and$ls180.v:4808$699 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_valid - connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:4808$699_Y - end - attribute \src "ls180.v:4815.9-4815.70" - cell $and $and$ls180.v:4815$700 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_sink_valid - connect \B \main_sdphy_datar_pads_out_ready - connect \Y $and$ls180.v:4815$700_Y - end - attribute \src "ls180.v:4896.48-4896.124" - cell $and $and$ls180.v:4896$823 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_last - connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4896$823_Y - end - attribute \src "ls180.v:4896.47-4896.165" - cell $and $and$ls180.v:4896$824 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4896$823_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4896$824_Y - end - attribute \src "ls180.v:4897.50-4897.127" - cell $and $and$ls180.v:4897$825 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4897$825_Y - end - attribute \src "ls180.v:4899.48-4899.124" - cell $and $and$ls180.v:4899$826 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_last - connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4899$826_Y - end - attribute \src "ls180.v:4899.47-4899.165" - cell $and $and$ls180.v:4899$827 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4899$826_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4899$827_Y - end - attribute \src "ls180.v:4900.50-4900.127" - cell $and $and$ls180.v:4900$828 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4900$828_Y - end - attribute \src "ls180.v:4902.48-4902.124" - cell $and $and$ls180.v:4902$829 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_last - connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4902$829_Y - end - attribute \src "ls180.v:4902.47-4902.165" - cell $and $and$ls180.v:4902$830 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4902$829_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4902$830_Y - end - attribute \src "ls180.v:4903.50-4903.127" - cell $and $and$ls180.v:4903$831 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4903$831_Y - end - attribute \src "ls180.v:4905.48-4905.124" - cell $and $and$ls180.v:4905$832 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_last - connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4905$832_Y - end - attribute \src "ls180.v:4905.47-4905.165" - cell $and $and$ls180.v:4905$833 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4905$832_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4905$833_Y - end - attribute \src "ls180.v:4906.50-4906.127" - cell $and $and$ls180.v:4906$834 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4906$834_Y - end - attribute \src "ls180.v:5019.10-5019.86" - cell $and $and$ls180.v:5019$883 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_last - connect \Y $and$ls180.v:5019$883_Y - end - attribute \src "ls180.v:5019.9-5019.127" - cell $and $and$ls180.v:5019$884 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5019$883_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5019$884_Y - end - attribute \src "ls180.v:5029.9-5029.152" - cell $and $and$ls180.v:5029$888 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:5029$886_Y - connect \B $eq$ls180.v:5029$887_Y - connect \Y $and$ls180.v:5029$888_Y - end - attribute \src "ls180.v:5029.8-5029.226" - cell $and $and$ls180.v:5029$890 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5029$888_Y - connect \B $eq$ls180.v:5029$889_Y - connect \Y $and$ls180.v:5029$890_Y - end - attribute \src "ls180.v:5029.7-5029.300" - cell $and $and$ls180.v:5029$892 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5029$890_Y - connect \B $eq$ls180.v:5029$891_Y - connect \Y $and$ls180.v:5029$892_Y - end - attribute \src "ls180.v:5034.49-5034.124" - cell $and $and$ls180.v:5034$893 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5034$893_Y - end - attribute \src "ls180.v:5044.49-5044.124" - cell $and $and$ls180.v:5044$896 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5044$896_Y - end - attribute \src "ls180.v:5054.49-5054.124" - cell $and $and$ls180.v:5054$899 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5054$899_Y - end - attribute \src "ls180.v:5064.49-5064.124" - cell $and $and$ls180.v:5064$902 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5064$902_Y - end - attribute \src "ls180.v:5076.7-5076.84" - cell $and $and$ls180.v:5076$907 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B $gt$ls180.v:5076$906_Y - connect \Y $and$ls180.v:5076$907_Y - end - attribute \src "ls180.v:5194.9-5194.64" - cell $and $and$ls180.v:5194$956 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdw_sink_valid - connect \B \main_sdphy_cmdw_sink_ready - connect \Y $and$ls180.v:5194$956_Y - end - attribute \src "ls180.v:5246.10-5246.66" - cell $and $and$ls180.v:5246$965 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_sink_valid - connect \B \main_sdphy_dataw_sink_last - connect \Y $and$ls180.v:5246$965_Y - end - attribute \src "ls180.v:5246.9-5246.97" - cell $and $and$ls180.v:5246$966 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5246$965_Y - connect \B \main_sdphy_dataw_sink_ready - connect \Y $and$ls180.v:5246$966_Y - end - attribute \src "ls180.v:5272.11-5272.71" - cell $and $and$ls180.v:5272$974 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_last - connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:5272$974_Y - end - attribute \src "ls180.v:5356.43-5356.152" - cell $and $and$ls180.v:5356$982 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B $or$ls180.v:5356$981_Y - connect \Y $and$ls180.v:5356$982_Y - end - attribute \src "ls180.v:5357.41-5357.116" - cell $and $and$ls180.v:5357$983 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_readable - connect \B \main_sdblock2mem_fifo_syncfifo_re - connect \Y $and$ls180.v:5357$983_Y - end - attribute \src "ls180.v:5369.48-5369.125" - cell $and $and$ls180.v:5369$988 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_valid - connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:5369$988_Y - end - attribute \src "ls180.v:5396.9-5396.102" - cell $and $and$ls180.v:5396$992 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid - connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready - connect \Y $and$ls180.v:5396$992_Y - end - attribute \src "ls180.v:5469.9-5469.58" - cell $and $and$ls180.v:5469$998 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_bus_stb - connect \B \main_interface1_bus_ack - connect \Y $and$ls180.v:5469$998_Y - end - attribute \src "ls180.v:5522.51-5522.123" - cell $and $and$ls180.v:5522$1006 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_sink_first - connect \B \main_sdmem2block_converter_first - connect \Y $and$ls180.v:5522$1006_Y - end - attribute \src "ls180.v:5523.50-5523.120" - cell $and $and$ls180.v:5523$1007 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_sink_last - connect \B \main_sdmem2block_converter_last - connect \Y $and$ls180.v:5523$1007_Y - end - attribute \src "ls180.v:5524.49-5524.122" - cell $and $and$ls180.v:5524$1008 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_last - connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:5524$1008_Y - end - attribute \src "ls180.v:5564.43-5564.152" - cell $and $and$ls180.v:5564$1013 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B $or$ls180.v:5564$1012_Y - connect \Y $and$ls180.v:5564$1013_Y - end - attribute \src "ls180.v:5565.41-5565.116" - cell $and $and$ls180.v:5565$1014 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_readable - connect \B \main_sdmem2block_fifo_syncfifo_re - connect \Y $and$ls180.v:5565$1014_Y - end - attribute \src "ls180.v:5656.9-5656.76" - cell $and $and$ls180.v:5656$1026 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_libresocsim_wishbone_cyc - connect \B \builder_libresocsim_wishbone_stb - connect \Y $and$ls180.v:5656$1026_Y - end - attribute \src "ls180.v:5659.44-5659.120" - cell $and $and$ls180.v:5659$1028 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_libresocsim_wishbone_we - connect \B $ne$ls180.v:5659$1027_Y - connect \Y $and$ls180.v:5659$1028_Y - end - attribute \src "ls180.v:5679.63-5679.107" - cell $and $and$ls180.v:5679$1030 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5679$1029_Y - connect \Y $and$ls180.v:5679$1030_Y - end - attribute \src "ls180.v:5680.63-5680.107" - cell $and $and$ls180.v:5680$1032 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5680$1031_Y - connect \Y $and$ls180.v:5680$1032_Y - end - attribute \src "ls180.v:5681.63-5681.107" - cell $and $and$ls180.v:5681$1034 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5681$1033_Y - connect \Y $and$ls180.v:5681$1034_Y - end - attribute \src "ls180.v:5682.35-5682.79" - cell $and $and$ls180.v:5682$1036 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5682$1035_Y - connect \Y $and$ls180.v:5682$1036_Y - end - attribute \src "ls180.v:5683.35-5683.79" - cell $and $and$ls180.v:5683$1038 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5683$1037_Y - connect \Y $and$ls180.v:5683$1038_Y - end - attribute \src "ls180.v:5684.63-5684.107" - cell $and $and$ls180.v:5684$1040 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5684$1039_Y - connect \Y $and$ls180.v:5684$1040_Y - end - attribute \src "ls180.v:5685.63-5685.107" - cell $and $and$ls180.v:5685$1042 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5685$1041_Y - connect \Y $and$ls180.v:5685$1042_Y - end - attribute \src "ls180.v:5686.63-5686.107" - cell $and $and$ls180.v:5686$1044 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5686$1043_Y - connect \Y $and$ls180.v:5686$1044_Y - end - attribute \src "ls180.v:5687.35-5687.79" - cell $and $and$ls180.v:5687$1046 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5687$1045_Y - connect \Y $and$ls180.v:5687$1046_Y - end - attribute \src "ls180.v:5688.35-5688.79" - cell $and $and$ls180.v:5688$1048 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5688$1047_Y - connect \Y $and$ls180.v:5688$1048_Y - end - attribute \src "ls180.v:5733.40-5733.81" - cell $and $and$ls180.v:5733$1055 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [0] - connect \Y $and$ls180.v:5733$1055_Y - end - attribute \src "ls180.v:5734.50-5734.91" - cell $and $and$ls180.v:5734$1056 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [1] - connect \Y $and$ls180.v:5734$1056_Y - end - attribute \src "ls180.v:5735.50-5735.91" - cell $and $and$ls180.v:5735$1057 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [2] - connect \Y $and$ls180.v:5735$1057_Y - end - attribute \src "ls180.v:5736.29-5736.70" - cell $and $and$ls180.v:5736$1058 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [3] - connect \Y $and$ls180.v:5736$1058_Y - end - attribute \src "ls180.v:5737.44-5737.85" - cell $and $and$ls180.v:5737$1059 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [4] - connect \Y $and$ls180.v:5737$1059_Y - end - attribute \src "ls180.v:5739.25-5739.64" - cell $and $and$ls180.v:5739$1064 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_stb - connect \B \builder_shared_cyc - connect \Y $and$ls180.v:5739$1064_Y - end - attribute \src "ls180.v:5739.24-5739.89" - cell $and $and$ls180.v:5739$1066 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5739$1064_Y - connect \B $not$ls180.v:5739$1065_Y - connect \Y $and$ls180.v:5739$1066_Y - end - attribute \src "ls180.v:5745.31-5745.92" - cell $and $and$ls180.v:5745$1072 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } - connect \B \main_libresocsim_ram_bus_dat_r - connect \Y $and$ls180.v:5745$1072_Y - end - attribute \src "ls180.v:5745.97-5745.168" - cell $and $and$ls180.v:5745$1073 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } - connect \B \main_libresocsim_libresoc_xics_icp_dat_r - connect \Y $and$ls180.v:5745$1073_Y - end - attribute \src "ls180.v:5745.174-5745.245" - cell $and $and$ls180.v:5745$1075 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } - connect \B \main_libresocsim_libresoc_xics_ics_dat_r - connect \Y $and$ls180.v:5745$1075_Y - end - attribute \src "ls180.v:5745.251-5745.301" - cell $and $and$ls180.v:5745$1077 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } - connect \B \main_wb_sdram_dat_r - connect \Y $and$ls180.v:5745$1077_Y - end - attribute \src "ls180.v:5745.307-5745.372" - cell $and $and$ls180.v:5745$1079 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } - connect \B \builder_libresocsim_wishbone_dat_r - connect \Y $and$ls180.v:5745$1079_Y - end - attribute \src "ls180.v:5755.39-5755.92" - cell $and $and$ls180.v:5755$1083 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5755$1083_Y - end - attribute \src "ls180.v:5755.38-5755.142" - cell $and $and$ls180.v:5755$1085 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5755$1083_Y - connect \B $eq$ls180.v:5755$1084_Y - connect \Y $and$ls180.v:5755$1085_Y - end - attribute \src "ls180.v:5756.39-5756.95" - cell $and $and$ls180.v:5756$1087 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5756$1086_Y - connect \Y $and$ls180.v:5756$1087_Y - end - attribute \src "ls180.v:5756.38-5756.145" - cell $and $and$ls180.v:5756$1089 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5756$1087_Y - connect \B $eq$ls180.v:5756$1088_Y - connect \Y $and$ls180.v:5756$1089_Y - end - attribute \src "ls180.v:5758.41-5758.94" - cell $and $and$ls180.v:5758$1090 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5758$1090_Y - end - attribute \src "ls180.v:5758.40-5758.144" - cell $and $and$ls180.v:5758$1092 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5758$1090_Y - connect \B $eq$ls180.v:5758$1091_Y - connect \Y $and$ls180.v:5758$1092_Y - end - attribute \src "ls180.v:5759.41-5759.97" - cell $and $and$ls180.v:5759$1094 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5759$1093_Y - connect \Y $and$ls180.v:5759$1094_Y - end - attribute \src "ls180.v:5759.40-5759.147" - cell $and $and$ls180.v:5759$1096 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5759$1094_Y - connect \B $eq$ls180.v:5759$1095_Y - connect \Y $and$ls180.v:5759$1096_Y - end - attribute \src "ls180.v:5761.41-5761.94" - cell $and $and$ls180.v:5761$1097 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5761$1097_Y - end - attribute \src "ls180.v:5761.40-5761.144" - cell $and $and$ls180.v:5761$1099 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5761$1097_Y - connect \B $eq$ls180.v:5761$1098_Y - connect \Y $and$ls180.v:5761$1099_Y - end - attribute \src "ls180.v:5762.41-5762.97" - cell $and $and$ls180.v:5762$1101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5762$1100_Y - connect \Y $and$ls180.v:5762$1101_Y - end - attribute \src "ls180.v:5762.40-5762.147" - cell $and $and$ls180.v:5762$1103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5762$1101_Y - connect \B $eq$ls180.v:5762$1102_Y - connect \Y $and$ls180.v:5762$1103_Y - end - attribute \src "ls180.v:5764.41-5764.94" - cell $and $and$ls180.v:5764$1104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5764$1104_Y - end - attribute \src "ls180.v:5764.40-5764.144" - cell $and $and$ls180.v:5764$1106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5764$1104_Y - connect \B $eq$ls180.v:5764$1105_Y - connect \Y $and$ls180.v:5764$1106_Y - end - attribute \src "ls180.v:5765.41-5765.97" - cell $and $and$ls180.v:5765$1108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5765$1107_Y - connect \Y $and$ls180.v:5765$1108_Y - end - attribute \src "ls180.v:5765.40-5765.147" - cell $and $and$ls180.v:5765$1110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5765$1108_Y - connect \B $eq$ls180.v:5765$1109_Y - connect \Y $and$ls180.v:5765$1110_Y - end - attribute \src "ls180.v:5767.41-5767.94" - cell $and $and$ls180.v:5767$1111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5767$1111_Y - end - attribute \src "ls180.v:5767.40-5767.144" - cell $and $and$ls180.v:5767$1113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5767$1111_Y - connect \B $eq$ls180.v:5767$1112_Y - connect \Y $and$ls180.v:5767$1113_Y - end - attribute \src "ls180.v:5768.41-5768.97" - cell $and $and$ls180.v:5768$1115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5768$1114_Y - connect \Y $and$ls180.v:5768$1115_Y - end - attribute \src "ls180.v:5768.40-5768.147" - cell $and $and$ls180.v:5768$1117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5768$1115_Y - connect \B $eq$ls180.v:5768$1116_Y - connect \Y $and$ls180.v:5768$1117_Y - end - attribute \src "ls180.v:5770.44-5770.97" - cell $and $and$ls180.v:5770$1118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5770$1118_Y - end - attribute \src "ls180.v:5770.43-5770.147" - cell $and $and$ls180.v:5770$1120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5770$1118_Y - connect \B $eq$ls180.v:5770$1119_Y - connect \Y $and$ls180.v:5770$1120_Y - end - attribute \src "ls180.v:5771.44-5771.100" - cell $and $and$ls180.v:5771$1122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5771$1121_Y - connect \Y $and$ls180.v:5771$1122_Y - end - attribute \src "ls180.v:5771.43-5771.150" - cell $and $and$ls180.v:5771$1124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5771$1122_Y - connect \B $eq$ls180.v:5771$1123_Y - connect \Y $and$ls180.v:5771$1124_Y - end - attribute \src "ls180.v:5773.44-5773.97" - cell $and $and$ls180.v:5773$1125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5773$1125_Y - end - attribute \src "ls180.v:5773.43-5773.147" - cell $and $and$ls180.v:5773$1127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5773$1125_Y - connect \B $eq$ls180.v:5773$1126_Y - connect \Y $and$ls180.v:5773$1127_Y - end - attribute \src "ls180.v:5774.44-5774.100" - cell $and $and$ls180.v:5774$1129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5774$1128_Y - connect \Y $and$ls180.v:5774$1129_Y - end - attribute \src "ls180.v:5774.43-5774.150" - cell $and $and$ls180.v:5774$1131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5774$1129_Y - connect \B $eq$ls180.v:5774$1130_Y - connect \Y $and$ls180.v:5774$1131_Y - end - attribute \src "ls180.v:5776.44-5776.97" - cell $and $and$ls180.v:5776$1132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5776$1132_Y - end - attribute \src "ls180.v:5776.43-5776.147" - cell $and $and$ls180.v:5776$1134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5776$1132_Y - connect \B $eq$ls180.v:5776$1133_Y - connect \Y $and$ls180.v:5776$1134_Y - end - attribute \src "ls180.v:5777.44-5777.100" - cell $and $and$ls180.v:5777$1136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5777$1135_Y - connect \Y $and$ls180.v:5777$1136_Y - end - attribute \src "ls180.v:5777.43-5777.150" - cell $and $and$ls180.v:5777$1138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5777$1136_Y - connect \B $eq$ls180.v:5777$1137_Y - connect \Y $and$ls180.v:5777$1138_Y - end - attribute \src "ls180.v:5779.44-5779.97" - cell $and $and$ls180.v:5779$1139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5779$1139_Y - end - attribute \src "ls180.v:5779.43-5779.147" - cell $and $and$ls180.v:5779$1141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5779$1139_Y - connect \B $eq$ls180.v:5779$1140_Y - connect \Y $and$ls180.v:5779$1141_Y - end - attribute \src "ls180.v:5780.44-5780.100" - cell $and $and$ls180.v:5780$1143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5780$1142_Y - connect \Y $and$ls180.v:5780$1143_Y - end - attribute \src "ls180.v:5780.43-5780.150" - cell $and $and$ls180.v:5780$1145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5780$1143_Y - connect \B $eq$ls180.v:5780$1144_Y - connect \Y $and$ls180.v:5780$1145_Y - end - attribute \src "ls180.v:5793.36-5793.89" - cell $and $and$ls180.v:5793$1147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5793$1147_Y - end - attribute \src "ls180.v:5793.35-5793.139" - cell $and $and$ls180.v:5793$1149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5793$1147_Y - connect \B $eq$ls180.v:5793$1148_Y - connect \Y $and$ls180.v:5793$1149_Y - end - attribute \src "ls180.v:5794.36-5794.92" - cell $and $and$ls180.v:5794$1151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5794$1150_Y - connect \Y $and$ls180.v:5794$1151_Y - end - attribute \src "ls180.v:5794.35-5794.142" - cell $and $and$ls180.v:5794$1153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5794$1151_Y - connect \B $eq$ls180.v:5794$1152_Y - connect \Y $and$ls180.v:5794$1153_Y - end - attribute \src "ls180.v:5796.36-5796.89" - cell $and $and$ls180.v:5796$1154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5796$1154_Y - end - attribute \src "ls180.v:5796.35-5796.139" - cell $and $and$ls180.v:5796$1156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5796$1154_Y - connect \B $eq$ls180.v:5796$1155_Y - connect \Y $and$ls180.v:5796$1156_Y - end - attribute \src "ls180.v:5797.36-5797.92" - cell $and $and$ls180.v:5797$1158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5797$1157_Y - connect \Y $and$ls180.v:5797$1158_Y - end - attribute \src "ls180.v:5797.35-5797.142" - cell $and $and$ls180.v:5797$1160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5797$1158_Y - connect \B $eq$ls180.v:5797$1159_Y - connect \Y $and$ls180.v:5797$1160_Y - end - attribute \src "ls180.v:5799.36-5799.89" - cell $and $and$ls180.v:5799$1161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5799$1161_Y - end - attribute \src "ls180.v:5799.35-5799.139" - cell $and $and$ls180.v:5799$1163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5799$1161_Y - connect \B $eq$ls180.v:5799$1162_Y - connect \Y $and$ls180.v:5799$1163_Y - end - attribute \src "ls180.v:5800.36-5800.92" - cell $and $and$ls180.v:5800$1165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5800$1164_Y - connect \Y $and$ls180.v:5800$1165_Y - end - attribute \src "ls180.v:5800.35-5800.142" - cell $and $and$ls180.v:5800$1167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5800$1165_Y - connect \B $eq$ls180.v:5800$1166_Y - connect \Y $and$ls180.v:5800$1167_Y - end - attribute \src "ls180.v:5802.36-5802.89" - cell $and $and$ls180.v:5802$1168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5802$1168_Y - end - attribute \src "ls180.v:5802.35-5802.139" - cell $and $and$ls180.v:5802$1170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5802$1168_Y - connect \B $eq$ls180.v:5802$1169_Y - connect \Y $and$ls180.v:5802$1170_Y - end - attribute \src "ls180.v:5803.36-5803.92" - cell $and $and$ls180.v:5803$1172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5803$1171_Y - connect \Y $and$ls180.v:5803$1172_Y - end - attribute \src "ls180.v:5803.35-5803.142" - cell $and $and$ls180.v:5803$1174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5803$1172_Y - connect \B $eq$ls180.v:5803$1173_Y - connect \Y $and$ls180.v:5803$1174_Y - end - attribute \src "ls180.v:5805.37-5805.90" - cell $and $and$ls180.v:5805$1175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5805$1175_Y - end - attribute \src "ls180.v:5805.36-5805.140" - cell $and $and$ls180.v:5805$1177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5805$1175_Y - connect \B $eq$ls180.v:5805$1176_Y - connect \Y $and$ls180.v:5805$1177_Y - end - attribute \src "ls180.v:5806.37-5806.93" - cell $and $and$ls180.v:5806$1179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5806$1178_Y - connect \Y $and$ls180.v:5806$1179_Y - end - attribute \src "ls180.v:5806.36-5806.143" - cell $and $and$ls180.v:5806$1181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5806$1179_Y - connect \B $eq$ls180.v:5806$1180_Y - connect \Y $and$ls180.v:5806$1181_Y - end - attribute \src "ls180.v:5808.37-5808.90" - cell $and $and$ls180.v:5808$1182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5808$1182_Y - end - attribute \src "ls180.v:5808.36-5808.140" - cell $and $and$ls180.v:5808$1184 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5808$1182_Y - connect \B $eq$ls180.v:5808$1183_Y - connect \Y $and$ls180.v:5808$1184_Y - end - attribute \src "ls180.v:5809.37-5809.93" - cell $and $and$ls180.v:5809$1186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5809$1185_Y - connect \Y $and$ls180.v:5809$1186_Y - end - attribute \src "ls180.v:5809.36-5809.143" - cell $and $and$ls180.v:5809$1188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5809$1186_Y - connect \B $eq$ls180.v:5809$1187_Y - connect \Y $and$ls180.v:5809$1188_Y - end - attribute \src "ls180.v:5819.35-5819.88" - cell $and $and$ls180.v:5819$1190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5819$1190_Y - end - attribute \src "ls180.v:5819.34-5819.136" - cell $and $and$ls180.v:5819$1192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5819$1190_Y - connect \B $eq$ls180.v:5819$1191_Y - connect \Y $and$ls180.v:5819$1192_Y - end - attribute \src "ls180.v:5820.35-5820.91" - cell $and $and$ls180.v:5820$1194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5820$1193_Y - connect \Y $and$ls180.v:5820$1194_Y - end - attribute \src "ls180.v:5820.34-5820.139" - cell $and $and$ls180.v:5820$1196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5820$1194_Y - connect \B $eq$ls180.v:5820$1195_Y - connect \Y $and$ls180.v:5820$1196_Y - end - attribute \src "ls180.v:5822.34-5822.87" - cell $and $and$ls180.v:5822$1197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5822$1197_Y - end - attribute \src "ls180.v:5822.33-5822.135" - cell $and $and$ls180.v:5822$1199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5822$1197_Y - connect \B $eq$ls180.v:5822$1198_Y - connect \Y $and$ls180.v:5822$1199_Y - end - attribute \src "ls180.v:5823.34-5823.90" - cell $and $and$ls180.v:5823$1201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5823$1200_Y - connect \Y $and$ls180.v:5823$1201_Y - end - attribute \src "ls180.v:5823.33-5823.138" - cell $and $and$ls180.v:5823$1203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5823$1201_Y - connect \B $eq$ls180.v:5823$1202_Y - connect \Y $and$ls180.v:5823$1203_Y - end - attribute \src "ls180.v:5833.40-5833.93" - cell $and $and$ls180.v:5833$1205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5833$1205_Y - end - attribute \src "ls180.v:5833.39-5833.143" - cell $and $and$ls180.v:5833$1207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5833$1205_Y - connect \B $eq$ls180.v:5833$1206_Y - connect \Y $and$ls180.v:5833$1207_Y - end - attribute \src "ls180.v:5834.40-5834.96" - cell $and $and$ls180.v:5834$1209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5834$1208_Y - connect \Y $and$ls180.v:5834$1209_Y - end - attribute \src "ls180.v:5834.39-5834.146" - cell $and $and$ls180.v:5834$1211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5834$1209_Y - connect \B $eq$ls180.v:5834$1210_Y - connect \Y $and$ls180.v:5834$1211_Y - end - attribute \src "ls180.v:5836.39-5836.92" - cell $and $and$ls180.v:5836$1212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5836$1212_Y - end - attribute \src "ls180.v:5836.38-5836.142" - cell $and $and$ls180.v:5836$1214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5836$1212_Y - connect \B $eq$ls180.v:5836$1213_Y - connect \Y $and$ls180.v:5836$1214_Y - end - attribute \src "ls180.v:5837.39-5837.95" - cell $and $and$ls180.v:5837$1216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5837$1215_Y - connect \Y $and$ls180.v:5837$1216_Y - end - attribute \src "ls180.v:5837.38-5837.145" - cell $and $and$ls180.v:5837$1218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5837$1216_Y - connect \B $eq$ls180.v:5837$1217_Y - connect \Y $and$ls180.v:5837$1218_Y - end - attribute \src "ls180.v:5839.39-5839.92" - cell $and $and$ls180.v:5839$1219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5839$1219_Y - end - attribute \src "ls180.v:5839.38-5839.142" - cell $and $and$ls180.v:5839$1221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5839$1219_Y - connect \B $eq$ls180.v:5839$1220_Y - connect \Y $and$ls180.v:5839$1221_Y - end - attribute \src "ls180.v:5840.39-5840.95" - cell $and $and$ls180.v:5840$1223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5840$1222_Y - connect \Y $and$ls180.v:5840$1223_Y - end - attribute \src "ls180.v:5840.38-5840.145" - cell $and $and$ls180.v:5840$1225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5840$1223_Y - connect \B $eq$ls180.v:5840$1224_Y - connect \Y $and$ls180.v:5840$1225_Y - end - attribute \src "ls180.v:5842.39-5842.92" - cell $and $and$ls180.v:5842$1226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5842$1226_Y - end - attribute \src "ls180.v:5842.38-5842.142" - cell $and $and$ls180.v:5842$1228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5842$1226_Y - connect \B $eq$ls180.v:5842$1227_Y - connect \Y $and$ls180.v:5842$1228_Y - end - attribute \src "ls180.v:5843.39-5843.95" - cell $and $and$ls180.v:5843$1230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5843$1229_Y - connect \Y $and$ls180.v:5843$1230_Y - end - attribute \src "ls180.v:5843.38-5843.145" - cell $and $and$ls180.v:5843$1232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5843$1230_Y - connect \B $eq$ls180.v:5843$1231_Y - connect \Y $and$ls180.v:5843$1232_Y - end - attribute \src "ls180.v:5845.39-5845.92" - cell $and $and$ls180.v:5845$1233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5845$1233_Y - end - attribute \src "ls180.v:5845.38-5845.142" - cell $and $and$ls180.v:5845$1235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5845$1233_Y - connect \B $eq$ls180.v:5845$1234_Y - connect \Y $and$ls180.v:5845$1235_Y - end - attribute \src "ls180.v:5846.39-5846.95" - cell $and $and$ls180.v:5846$1237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5846$1236_Y - connect \Y $and$ls180.v:5846$1237_Y - end - attribute \src "ls180.v:5846.38-5846.145" - cell $and $and$ls180.v:5846$1239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5846$1237_Y - connect \B $eq$ls180.v:5846$1238_Y - connect \Y $and$ls180.v:5846$1239_Y - end - attribute \src "ls180.v:5848.40-5848.93" - cell $and $and$ls180.v:5848$1240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5848$1240_Y - end - attribute \src "ls180.v:5848.39-5848.143" - cell $and $and$ls180.v:5848$1242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5848$1240_Y - connect \B $eq$ls180.v:5848$1241_Y - connect \Y $and$ls180.v:5848$1242_Y - end - attribute \src "ls180.v:5849.40-5849.96" - cell $and $and$ls180.v:5849$1244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5849$1243_Y - connect \Y $and$ls180.v:5849$1244_Y - end - attribute \src "ls180.v:5849.39-5849.146" - cell $and $and$ls180.v:5849$1246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5849$1244_Y - connect \B $eq$ls180.v:5849$1245_Y - connect \Y $and$ls180.v:5849$1246_Y - end - attribute \src "ls180.v:5851.40-5851.93" - cell $and $and$ls180.v:5851$1247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5851$1247_Y - end - attribute \src "ls180.v:5851.39-5851.143" - cell $and $and$ls180.v:5851$1249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5851$1247_Y - connect \B $eq$ls180.v:5851$1248_Y - connect \Y $and$ls180.v:5851$1249_Y - end - attribute \src "ls180.v:5852.40-5852.96" - cell $and $and$ls180.v:5852$1251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5852$1250_Y - connect \Y $and$ls180.v:5852$1251_Y - end - attribute \src "ls180.v:5852.39-5852.146" - cell $and $and$ls180.v:5852$1253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5852$1251_Y - connect \B $eq$ls180.v:5852$1252_Y - connect \Y $and$ls180.v:5852$1253_Y - end - attribute \src "ls180.v:5854.40-5854.93" - cell $and $and$ls180.v:5854$1254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5854$1254_Y - end - attribute \src "ls180.v:5854.39-5854.143" - cell $and $and$ls180.v:5854$1256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5854$1254_Y - connect \B $eq$ls180.v:5854$1255_Y - connect \Y $and$ls180.v:5854$1256_Y - end - attribute \src "ls180.v:5855.40-5855.96" - cell $and $and$ls180.v:5855$1258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5855$1257_Y - connect \Y $and$ls180.v:5855$1258_Y - end - attribute \src "ls180.v:5855.39-5855.146" - cell $and $and$ls180.v:5855$1260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5855$1258_Y - connect \B $eq$ls180.v:5855$1259_Y - connect \Y $and$ls180.v:5855$1260_Y - end - attribute \src "ls180.v:5857.40-5857.93" - cell $and $and$ls180.v:5857$1261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5857$1261_Y - end - attribute \src "ls180.v:5857.39-5857.143" - cell $and $and$ls180.v:5857$1263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5857$1261_Y - connect \B $eq$ls180.v:5857$1262_Y - connect \Y $and$ls180.v:5857$1263_Y - end - attribute \src "ls180.v:5858.40-5858.96" - cell $and $and$ls180.v:5858$1265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5858$1264_Y - connect \Y $and$ls180.v:5858$1265_Y - end - attribute \src "ls180.v:5858.39-5858.146" - cell $and $and$ls180.v:5858$1267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5858$1265_Y - connect \B $eq$ls180.v:5858$1266_Y - connect \Y $and$ls180.v:5858$1267_Y - end - attribute \src "ls180.v:5870.40-5870.93" - cell $and $and$ls180.v:5870$1269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5870$1269_Y - end - attribute \src "ls180.v:5870.39-5870.143" - cell $and $and$ls180.v:5870$1271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5870$1269_Y - connect \B $eq$ls180.v:5870$1270_Y - connect \Y $and$ls180.v:5870$1271_Y - end - attribute \src "ls180.v:5871.40-5871.96" - cell $and $and$ls180.v:5871$1273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5871$1272_Y - connect \Y $and$ls180.v:5871$1273_Y - end - attribute \src "ls180.v:5871.39-5871.146" - cell $and $and$ls180.v:5871$1275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5871$1273_Y - connect \B $eq$ls180.v:5871$1274_Y - connect \Y $and$ls180.v:5871$1275_Y - end - attribute \src "ls180.v:5873.39-5873.92" - cell $and $and$ls180.v:5873$1276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5873$1276_Y - end - attribute \src "ls180.v:5873.38-5873.142" - cell $and $and$ls180.v:5873$1278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5873$1276_Y - connect \B $eq$ls180.v:5873$1277_Y - connect \Y $and$ls180.v:5873$1278_Y - end - attribute \src "ls180.v:5874.39-5874.95" - cell $and $and$ls180.v:5874$1280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5874$1279_Y - connect \Y $and$ls180.v:5874$1280_Y - end - attribute \src "ls180.v:5874.38-5874.145" - cell $and $and$ls180.v:5874$1282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5874$1280_Y - connect \B $eq$ls180.v:5874$1281_Y - connect \Y $and$ls180.v:5874$1282_Y - end - attribute \src "ls180.v:5876.39-5876.92" - cell $and $and$ls180.v:5876$1283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5876$1283_Y - end - attribute \src "ls180.v:5876.38-5876.142" - cell $and $and$ls180.v:5876$1285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5876$1283_Y - connect \B $eq$ls180.v:5876$1284_Y - connect \Y $and$ls180.v:5876$1285_Y - end - attribute \src "ls180.v:5877.39-5877.95" - cell $and $and$ls180.v:5877$1287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5877$1286_Y - connect \Y $and$ls180.v:5877$1287_Y - end - attribute \src "ls180.v:5877.38-5877.145" - cell $and $and$ls180.v:5877$1289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5877$1287_Y - connect \B $eq$ls180.v:5877$1288_Y - connect \Y $and$ls180.v:5877$1289_Y - end - attribute \src "ls180.v:5879.39-5879.92" - cell $and $and$ls180.v:5879$1290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5879$1290_Y - end - attribute \src "ls180.v:5879.38-5879.142" - cell $and $and$ls180.v:5879$1292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5879$1290_Y - connect \B $eq$ls180.v:5879$1291_Y - connect \Y $and$ls180.v:5879$1292_Y - end - attribute \src "ls180.v:5880.39-5880.95" - cell $and $and$ls180.v:5880$1294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5880$1293_Y - connect \Y $and$ls180.v:5880$1294_Y - end - attribute \src "ls180.v:5880.38-5880.145" - cell $and $and$ls180.v:5880$1296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5880$1294_Y - connect \B $eq$ls180.v:5880$1295_Y - connect \Y $and$ls180.v:5880$1296_Y - end - attribute \src "ls180.v:5882.39-5882.92" - cell $and $and$ls180.v:5882$1297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5882$1297_Y - end - attribute \src "ls180.v:5882.38-5882.142" - cell $and $and$ls180.v:5882$1299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5882$1297_Y - connect \B $eq$ls180.v:5882$1298_Y - connect \Y $and$ls180.v:5882$1299_Y - end - attribute \src "ls180.v:5883.39-5883.95" - cell $and $and$ls180.v:5883$1301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5883$1300_Y - connect \Y $and$ls180.v:5883$1301_Y - end - attribute \src "ls180.v:5883.38-5883.145" - cell $and $and$ls180.v:5883$1303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5883$1301_Y - connect \B $eq$ls180.v:5883$1302_Y - connect \Y $and$ls180.v:5883$1303_Y - end - attribute \src "ls180.v:5885.40-5885.93" - cell $and $and$ls180.v:5885$1304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5885$1304_Y - end - attribute \src "ls180.v:5885.39-5885.143" - cell $and $and$ls180.v:5885$1306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5885$1304_Y - connect \B $eq$ls180.v:5885$1305_Y - connect \Y $and$ls180.v:5885$1306_Y - end - attribute \src "ls180.v:5886.40-5886.96" - cell $and $and$ls180.v:5886$1308 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5886$1307_Y - connect \Y $and$ls180.v:5886$1308_Y - end - attribute \src "ls180.v:5886.39-5886.146" - cell $and $and$ls180.v:5886$1310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5886$1308_Y - connect \B $eq$ls180.v:5886$1309_Y - connect \Y $and$ls180.v:5886$1310_Y - end - attribute \src "ls180.v:5888.40-5888.93" - cell $and $and$ls180.v:5888$1311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5888$1311_Y - end - attribute \src "ls180.v:5888.39-5888.143" - cell $and $and$ls180.v:5888$1313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5888$1311_Y - connect \B $eq$ls180.v:5888$1312_Y - connect \Y $and$ls180.v:5888$1313_Y - end - attribute \src "ls180.v:5889.40-5889.96" - cell $and $and$ls180.v:5889$1315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5889$1314_Y - connect \Y $and$ls180.v:5889$1315_Y - end - attribute \src "ls180.v:5889.39-5889.146" - cell $and $and$ls180.v:5889$1317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5889$1315_Y - connect \B $eq$ls180.v:5889$1316_Y - connect \Y $and$ls180.v:5889$1317_Y - end - attribute \src "ls180.v:5891.40-5891.93" - cell $and $and$ls180.v:5891$1318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5891$1318_Y - end - attribute \src "ls180.v:5891.39-5891.143" - cell $and $and$ls180.v:5891$1320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5891$1318_Y - connect \B $eq$ls180.v:5891$1319_Y - connect \Y $and$ls180.v:5891$1320_Y - end - attribute \src "ls180.v:5892.40-5892.96" - cell $and $and$ls180.v:5892$1322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5892$1321_Y - connect \Y $and$ls180.v:5892$1322_Y - end - attribute \src "ls180.v:5892.39-5892.146" - cell $and $and$ls180.v:5892$1324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5892$1322_Y - connect \B $eq$ls180.v:5892$1323_Y - connect \Y $and$ls180.v:5892$1324_Y - end - attribute \src "ls180.v:5894.40-5894.93" - cell $and $and$ls180.v:5894$1325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5894$1325_Y - end - attribute \src "ls180.v:5894.39-5894.143" - cell $and $and$ls180.v:5894$1327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5894$1325_Y - connect \B $eq$ls180.v:5894$1326_Y - connect \Y $and$ls180.v:5894$1327_Y - end - attribute \src "ls180.v:5895.40-5895.96" - cell $and $and$ls180.v:5895$1329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5895$1328_Y - connect \Y $and$ls180.v:5895$1329_Y - end - attribute \src "ls180.v:5895.39-5895.146" - cell $and $and$ls180.v:5895$1331 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5895$1329_Y - connect \B $eq$ls180.v:5895$1330_Y - connect \Y $and$ls180.v:5895$1331_Y - end - attribute \src "ls180.v:5907.42-5907.95" - cell $and $and$ls180.v:5907$1333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5907$1333_Y - end - attribute \src "ls180.v:5907.41-5907.145" - cell $and $and$ls180.v:5907$1335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5907$1333_Y - connect \B $eq$ls180.v:5907$1334_Y - connect \Y $and$ls180.v:5907$1335_Y - end - attribute \src "ls180.v:5908.42-5908.98" - cell $and $and$ls180.v:5908$1337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5908$1336_Y - connect \Y $and$ls180.v:5908$1337_Y - end - attribute \src "ls180.v:5908.41-5908.148" - cell $and $and$ls180.v:5908$1339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5908$1337_Y - connect \B $eq$ls180.v:5908$1338_Y - connect \Y $and$ls180.v:5908$1339_Y - end - attribute \src "ls180.v:5910.42-5910.95" - cell $and $and$ls180.v:5910$1340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5910$1340_Y - end - attribute \src "ls180.v:5910.41-5910.145" - cell $and $and$ls180.v:5910$1342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5910$1340_Y - connect \B $eq$ls180.v:5910$1341_Y - connect \Y $and$ls180.v:5910$1342_Y - end - attribute \src "ls180.v:5911.42-5911.98" - cell $and $and$ls180.v:5911$1344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5911$1343_Y - connect \Y $and$ls180.v:5911$1344_Y - end - attribute \src "ls180.v:5911.41-5911.148" - cell $and $and$ls180.v:5911$1346 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5911$1344_Y - connect \B $eq$ls180.v:5911$1345_Y - connect \Y $and$ls180.v:5911$1346_Y - end - attribute \src "ls180.v:5913.42-5913.95" - cell $and $and$ls180.v:5913$1347 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5913$1347_Y - end - attribute \src "ls180.v:5913.41-5913.145" - cell $and $and$ls180.v:5913$1349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5913$1347_Y - connect \B $eq$ls180.v:5913$1348_Y - connect \Y $and$ls180.v:5913$1349_Y - end - attribute \src "ls180.v:5914.42-5914.98" - cell $and $and$ls180.v:5914$1351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5914$1350_Y - connect \Y $and$ls180.v:5914$1351_Y - end - attribute \src "ls180.v:5914.41-5914.148" - cell $and $and$ls180.v:5914$1353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5914$1351_Y - connect \B $eq$ls180.v:5914$1352_Y - connect \Y $and$ls180.v:5914$1353_Y - end - attribute \src "ls180.v:5916.42-5916.95" - cell $and $and$ls180.v:5916$1354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5916$1354_Y - end - attribute \src "ls180.v:5916.41-5916.145" - cell $and $and$ls180.v:5916$1356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5916$1354_Y - connect \B $eq$ls180.v:5916$1355_Y - connect \Y $and$ls180.v:5916$1356_Y - end - attribute \src "ls180.v:5917.42-5917.98" - cell $and $and$ls180.v:5917$1358 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5917$1357_Y - connect \Y $and$ls180.v:5917$1358_Y - end - attribute \src "ls180.v:5917.41-5917.148" - cell $and $and$ls180.v:5917$1360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5917$1358_Y - connect \B $eq$ls180.v:5917$1359_Y - connect \Y $and$ls180.v:5917$1360_Y - end - attribute \src "ls180.v:5919.42-5919.95" - cell $and $and$ls180.v:5919$1361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5919$1361_Y - end - attribute \src "ls180.v:5919.41-5919.145" - cell $and $and$ls180.v:5919$1363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5919$1361_Y - connect \B $eq$ls180.v:5919$1362_Y - connect \Y $and$ls180.v:5919$1363_Y - end - attribute \src "ls180.v:5920.42-5920.98" - cell $and $and$ls180.v:5920$1365 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5920$1364_Y - connect \Y $and$ls180.v:5920$1365_Y - end - attribute \src "ls180.v:5920.41-5920.148" - cell $and $and$ls180.v:5920$1367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5920$1365_Y - connect \B $eq$ls180.v:5920$1366_Y - connect \Y $and$ls180.v:5920$1367_Y - end - attribute \src "ls180.v:5922.42-5922.95" - cell $and $and$ls180.v:5922$1368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5922$1368_Y - end - attribute \src "ls180.v:5922.41-5922.145" - cell $and $and$ls180.v:5922$1370 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5922$1368_Y - connect \B $eq$ls180.v:5922$1369_Y - connect \Y $and$ls180.v:5922$1370_Y - end - attribute \src "ls180.v:5923.42-5923.98" - cell $and $and$ls180.v:5923$1372 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5923$1371_Y - connect \Y $and$ls180.v:5923$1372_Y - end - attribute \src "ls180.v:5923.41-5923.148" - cell $and $and$ls180.v:5923$1374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5923$1372_Y - connect \B $eq$ls180.v:5923$1373_Y - connect \Y $and$ls180.v:5923$1374_Y - end - attribute \src "ls180.v:5925.42-5925.95" - cell $and $and$ls180.v:5925$1375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5925$1375_Y - end - attribute \src "ls180.v:5925.41-5925.145" - cell $and $and$ls180.v:5925$1377 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5925$1375_Y - connect \B $eq$ls180.v:5925$1376_Y - connect \Y $and$ls180.v:5925$1377_Y - end - attribute \src "ls180.v:5926.42-5926.98" - cell $and $and$ls180.v:5926$1379 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5926$1378_Y - connect \Y $and$ls180.v:5926$1379_Y - end - attribute \src "ls180.v:5926.41-5926.148" - cell $and $and$ls180.v:5926$1381 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5926$1379_Y - connect \B $eq$ls180.v:5926$1380_Y - connect \Y $and$ls180.v:5926$1381_Y - end - attribute \src "ls180.v:5928.42-5928.95" - cell $and $and$ls180.v:5928$1382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5928$1382_Y - end - attribute \src "ls180.v:5928.41-5928.145" - cell $and $and$ls180.v:5928$1384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5928$1382_Y - connect \B $eq$ls180.v:5928$1383_Y - connect \Y $and$ls180.v:5928$1384_Y - end - attribute \src "ls180.v:5929.42-5929.98" - cell $and $and$ls180.v:5929$1386 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5929$1385_Y - connect \Y $and$ls180.v:5929$1386_Y - end - attribute \src "ls180.v:5929.41-5929.148" - cell $and $and$ls180.v:5929$1388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5929$1386_Y - connect \B $eq$ls180.v:5929$1387_Y - connect \Y $and$ls180.v:5929$1388_Y - end - attribute \src "ls180.v:5931.44-5931.97" - cell $and $and$ls180.v:5931$1389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5931$1389_Y - end - attribute \src "ls180.v:5931.43-5931.147" - cell $and $and$ls180.v:5931$1391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5931$1389_Y - connect \B $eq$ls180.v:5931$1390_Y - connect \Y $and$ls180.v:5931$1391_Y - end - attribute \src "ls180.v:5932.44-5932.100" - cell $and $and$ls180.v:5932$1393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5932$1392_Y - connect \Y $and$ls180.v:5932$1393_Y - end - attribute \src "ls180.v:5932.43-5932.150" - cell $and $and$ls180.v:5932$1395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5932$1393_Y - connect \B $eq$ls180.v:5932$1394_Y - connect \Y $and$ls180.v:5932$1395_Y - end - attribute \src "ls180.v:5934.44-5934.97" - cell $and $and$ls180.v:5934$1396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5934$1396_Y - end - attribute \src "ls180.v:5934.43-5934.147" - cell $and $and$ls180.v:5934$1398 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5934$1396_Y - connect \B $eq$ls180.v:5934$1397_Y - connect \Y $and$ls180.v:5934$1398_Y - end - attribute \src "ls180.v:5935.44-5935.100" - cell $and $and$ls180.v:5935$1400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5935$1399_Y - connect \Y $and$ls180.v:5935$1400_Y - end - attribute \src "ls180.v:5935.43-5935.150" - cell $and $and$ls180.v:5935$1402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5935$1400_Y - connect \B $eq$ls180.v:5935$1401_Y - connect \Y $and$ls180.v:5935$1402_Y - end - attribute \src "ls180.v:5937.44-5937.97" - cell $and $and$ls180.v:5937$1403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5937$1403_Y - end - attribute \src "ls180.v:5937.43-5937.148" - cell $and $and$ls180.v:5937$1405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5937$1403_Y - connect \B $eq$ls180.v:5937$1404_Y - connect \Y $and$ls180.v:5937$1405_Y - end - attribute \src "ls180.v:5938.44-5938.100" - cell $and $and$ls180.v:5938$1407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5938$1406_Y - connect \Y $and$ls180.v:5938$1407_Y - end - attribute \src "ls180.v:5938.43-5938.151" - cell $and $and$ls180.v:5938$1409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5938$1407_Y - connect \B $eq$ls180.v:5938$1408_Y - connect \Y $and$ls180.v:5938$1409_Y - end - attribute \src "ls180.v:5940.44-5940.97" - cell $and $and$ls180.v:5940$1410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5940$1410_Y - end - attribute \src "ls180.v:5940.43-5940.148" - cell $and $and$ls180.v:5940$1412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5940$1410_Y - connect \B $eq$ls180.v:5940$1411_Y - connect \Y $and$ls180.v:5940$1412_Y - end - attribute \src "ls180.v:5941.44-5941.100" - cell $and $and$ls180.v:5941$1414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5941$1413_Y - connect \Y $and$ls180.v:5941$1414_Y - end - attribute \src "ls180.v:5941.43-5941.151" - cell $and $and$ls180.v:5941$1416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5941$1414_Y - connect \B $eq$ls180.v:5941$1415_Y - connect \Y $and$ls180.v:5941$1416_Y - end - attribute \src "ls180.v:5943.44-5943.97" - cell $and $and$ls180.v:5943$1417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5943$1417_Y - end - attribute \src "ls180.v:5943.43-5943.148" - cell $and $and$ls180.v:5943$1419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5943$1417_Y - connect \B $eq$ls180.v:5943$1418_Y - connect \Y $and$ls180.v:5943$1419_Y - end - attribute \src "ls180.v:5944.44-5944.100" - cell $and $and$ls180.v:5944$1421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5944$1420_Y - connect \Y $and$ls180.v:5944$1421_Y - end - attribute \src "ls180.v:5944.43-5944.151" - cell $and $and$ls180.v:5944$1423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5944$1421_Y - connect \B $eq$ls180.v:5944$1422_Y - connect \Y $and$ls180.v:5944$1423_Y - end - attribute \src "ls180.v:5946.41-5946.94" - cell $and $and$ls180.v:5946$1424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5946$1424_Y - end - attribute \src "ls180.v:5946.40-5946.145" - cell $and $and$ls180.v:5946$1426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5946$1424_Y - connect \B $eq$ls180.v:5946$1425_Y - connect \Y $and$ls180.v:5946$1426_Y - end - attribute \src "ls180.v:5947.41-5947.97" - cell $and $and$ls180.v:5947$1428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5947$1427_Y - connect \Y $and$ls180.v:5947$1428_Y - end - attribute \src "ls180.v:5947.40-5947.148" - cell $and $and$ls180.v:5947$1430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5947$1428_Y - connect \B $eq$ls180.v:5947$1429_Y - connect \Y $and$ls180.v:5947$1430_Y - end - attribute \src "ls180.v:5949.42-5949.95" - cell $and $and$ls180.v:5949$1431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5949$1431_Y - end - attribute \src "ls180.v:5949.41-5949.146" - cell $and $and$ls180.v:5949$1433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5949$1431_Y - connect \B $eq$ls180.v:5949$1432_Y - connect \Y $and$ls180.v:5949$1433_Y - end - attribute \src "ls180.v:5950.42-5950.98" - cell $and $and$ls180.v:5950$1435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5950$1434_Y - connect \Y $and$ls180.v:5950$1435_Y - end - attribute \src "ls180.v:5950.41-5950.149" - cell $and $and$ls180.v:5950$1437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5950$1435_Y - connect \B $eq$ls180.v:5950$1436_Y - connect \Y $and$ls180.v:5950$1437_Y - end - attribute \src "ls180.v:5969.46-5969.99" - cell $and $and$ls180.v:5969$1439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5969$1439_Y - end - attribute \src "ls180.v:5969.45-5969.149" - cell $and $and$ls180.v:5969$1441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5969$1439_Y - connect \B $eq$ls180.v:5969$1440_Y - connect \Y $and$ls180.v:5969$1441_Y - end - attribute \src "ls180.v:5970.46-5970.102" - cell $and $and$ls180.v:5970$1443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5970$1442_Y - connect \Y $and$ls180.v:5970$1443_Y - end - attribute \src "ls180.v:5970.45-5970.152" - cell $and $and$ls180.v:5970$1445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5970$1443_Y - connect \B $eq$ls180.v:5970$1444_Y - connect \Y $and$ls180.v:5970$1445_Y - end - attribute \src "ls180.v:5972.46-5972.99" - cell $and $and$ls180.v:5972$1446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5972$1446_Y - end - attribute \src "ls180.v:5972.45-5972.149" - cell $and $and$ls180.v:5972$1448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5972$1446_Y - connect \B $eq$ls180.v:5972$1447_Y - connect \Y $and$ls180.v:5972$1448_Y - end - attribute \src "ls180.v:5973.46-5973.102" - cell $and $and$ls180.v:5973$1450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5973$1449_Y - connect \Y $and$ls180.v:5973$1450_Y - end - attribute \src "ls180.v:5973.45-5973.152" - cell $and $and$ls180.v:5973$1452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5973$1450_Y - connect \B $eq$ls180.v:5973$1451_Y - connect \Y $and$ls180.v:5973$1452_Y - end - attribute \src "ls180.v:5975.46-5975.99" - cell $and $and$ls180.v:5975$1453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5975$1453_Y - end - attribute \src "ls180.v:5975.45-5975.149" - cell $and $and$ls180.v:5975$1455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5975$1453_Y - connect \B $eq$ls180.v:5975$1454_Y - connect \Y $and$ls180.v:5975$1455_Y - end - attribute \src "ls180.v:5976.46-5976.102" - cell $and $and$ls180.v:5976$1457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5976$1456_Y - connect \Y $and$ls180.v:5976$1457_Y - end - attribute \src "ls180.v:5976.45-5976.152" - cell $and $and$ls180.v:5976$1459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5976$1457_Y - connect \B $eq$ls180.v:5976$1458_Y - connect \Y $and$ls180.v:5976$1459_Y - end - attribute \src "ls180.v:5978.46-5978.99" - cell $and $and$ls180.v:5978$1460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5978$1460_Y - end - attribute \src "ls180.v:5978.45-5978.149" - cell $and $and$ls180.v:5978$1462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5978$1460_Y - connect \B $eq$ls180.v:5978$1461_Y - connect \Y $and$ls180.v:5978$1462_Y - end - attribute \src "ls180.v:5979.46-5979.102" - cell $and $and$ls180.v:5979$1464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5979$1463_Y - connect \Y $and$ls180.v:5979$1464_Y - end - attribute \src "ls180.v:5979.45-5979.152" - cell $and $and$ls180.v:5979$1466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5979$1464_Y - connect \B $eq$ls180.v:5979$1465_Y - connect \Y $and$ls180.v:5979$1466_Y - end - attribute \src "ls180.v:5981.45-5981.98" - cell $and $and$ls180.v:5981$1467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5981$1467_Y - end - attribute \src "ls180.v:5981.44-5981.148" - cell $and $and$ls180.v:5981$1469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5981$1467_Y - connect \B $eq$ls180.v:5981$1468_Y - connect \Y $and$ls180.v:5981$1469_Y - end - attribute \src "ls180.v:5982.45-5982.101" - cell $and $and$ls180.v:5982$1471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5982$1470_Y - connect \Y $and$ls180.v:5982$1471_Y - end - attribute \src "ls180.v:5982.44-5982.151" - cell $and $and$ls180.v:5982$1473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5982$1471_Y - connect \B $eq$ls180.v:5982$1472_Y - connect \Y $and$ls180.v:5982$1473_Y - end - attribute \src "ls180.v:5984.45-5984.98" - cell $and $and$ls180.v:5984$1474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5984$1474_Y - end - attribute \src "ls180.v:5984.44-5984.148" - cell $and $and$ls180.v:5984$1476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5984$1474_Y - connect \B $eq$ls180.v:5984$1475_Y - connect \Y $and$ls180.v:5984$1476_Y - end - attribute \src "ls180.v:5985.45-5985.101" - cell $and $and$ls180.v:5985$1478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5985$1477_Y - connect \Y $and$ls180.v:5985$1478_Y - end - attribute \src "ls180.v:5985.44-5985.151" - cell $and $and$ls180.v:5985$1480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5985$1478_Y - connect \B $eq$ls180.v:5985$1479_Y - connect \Y $and$ls180.v:5985$1480_Y - end - attribute \src "ls180.v:5987.45-5987.98" - cell $and $and$ls180.v:5987$1481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5987$1481_Y - end - attribute \src "ls180.v:5987.44-5987.148" - cell $and $and$ls180.v:5987$1483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5987$1481_Y - connect \B $eq$ls180.v:5987$1482_Y - connect \Y $and$ls180.v:5987$1483_Y - end - attribute \src "ls180.v:5988.45-5988.101" - cell $and $and$ls180.v:5988$1485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5988$1484_Y - connect \Y $and$ls180.v:5988$1485_Y - end - attribute \src "ls180.v:5988.44-5988.151" - cell $and $and$ls180.v:5988$1487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5988$1485_Y - connect \B $eq$ls180.v:5988$1486_Y - connect \Y $and$ls180.v:5988$1487_Y - end - attribute \src "ls180.v:5990.45-5990.98" - cell $and $and$ls180.v:5990$1488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5990$1488_Y - end - attribute \src "ls180.v:5990.44-5990.148" - cell $and $and$ls180.v:5990$1490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5990$1488_Y - connect \B $eq$ls180.v:5990$1489_Y - connect \Y $and$ls180.v:5990$1490_Y - end - attribute \src "ls180.v:5991.45-5991.101" - cell $and $and$ls180.v:5991$1492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5991$1491_Y - connect \Y $and$ls180.v:5991$1492_Y - end - attribute \src "ls180.v:5991.44-5991.151" - cell $and $and$ls180.v:5991$1494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5991$1492_Y - connect \B $eq$ls180.v:5991$1493_Y - connect \Y $and$ls180.v:5991$1494_Y - end - attribute \src "ls180.v:5993.36-5993.89" - cell $and $and$ls180.v:5993$1495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5993$1495_Y - end - attribute \src "ls180.v:5993.35-5993.139" - cell $and $and$ls180.v:5993$1497 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5993$1495_Y - connect \B $eq$ls180.v:5993$1496_Y - connect \Y $and$ls180.v:5993$1497_Y - end - attribute \src "ls180.v:5994.36-5994.92" - cell $and $and$ls180.v:5994$1499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5994$1498_Y - connect \Y $and$ls180.v:5994$1499_Y - end - attribute \src "ls180.v:5994.35-5994.142" - cell $and $and$ls180.v:5994$1501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5994$1499_Y - connect \B $eq$ls180.v:5994$1500_Y - connect \Y $and$ls180.v:5994$1501_Y - end - attribute \src "ls180.v:5996.47-5996.100" - cell $and $and$ls180.v:5996$1502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5996$1502_Y - end - attribute \src "ls180.v:5996.46-5996.150" - cell $and $and$ls180.v:5996$1504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5996$1502_Y - connect \B $eq$ls180.v:5996$1503_Y - connect \Y $and$ls180.v:5996$1504_Y - end - attribute \src "ls180.v:5997.47-5997.103" - cell $and $and$ls180.v:5997$1506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5997$1505_Y - connect \Y $and$ls180.v:5997$1506_Y - end - attribute \src "ls180.v:5997.46-5997.153" - cell $and $and$ls180.v:5997$1508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5997$1506_Y - connect \B $eq$ls180.v:5997$1507_Y - connect \Y $and$ls180.v:5997$1508_Y - end - attribute \src "ls180.v:5999.47-5999.100" - cell $and $and$ls180.v:5999$1509 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5999$1509_Y - end - attribute \src "ls180.v:5999.46-5999.151" - cell $and $and$ls180.v:5999$1511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5999$1509_Y - connect \B $eq$ls180.v:5999$1510_Y - connect \Y $and$ls180.v:5999$1511_Y - end - attribute \src "ls180.v:6000.47-6000.103" - cell $and $and$ls180.v:6000$1513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6000$1512_Y - connect \Y $and$ls180.v:6000$1513_Y - end - attribute \src "ls180.v:6000.46-6000.154" - cell $and $and$ls180.v:6000$1515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6000$1513_Y - connect \B $eq$ls180.v:6000$1514_Y - connect \Y $and$ls180.v:6000$1515_Y - end - attribute \src "ls180.v:6002.47-6002.100" - cell $and $and$ls180.v:6002$1516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6002$1516_Y - end - attribute \src "ls180.v:6002.46-6002.151" - cell $and $and$ls180.v:6002$1518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6002$1516_Y - connect \B $eq$ls180.v:6002$1517_Y - connect \Y $and$ls180.v:6002$1518_Y - end - attribute \src "ls180.v:6003.47-6003.103" - cell $and $and$ls180.v:6003$1520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6003$1519_Y - connect \Y $and$ls180.v:6003$1520_Y - end - attribute \src "ls180.v:6003.46-6003.154" - cell $and $and$ls180.v:6003$1522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6003$1520_Y - connect \B $eq$ls180.v:6003$1521_Y - connect \Y $and$ls180.v:6003$1522_Y - end - attribute \src "ls180.v:6005.47-6005.100" - cell $and $and$ls180.v:6005$1523 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6005$1523_Y - end - attribute \src "ls180.v:6005.46-6005.151" - cell $and $and$ls180.v:6005$1525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6005$1523_Y - connect \B $eq$ls180.v:6005$1524_Y - connect \Y $and$ls180.v:6005$1525_Y - end - attribute \src "ls180.v:6006.47-6006.103" - cell $and $and$ls180.v:6006$1527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6006$1526_Y - connect \Y $and$ls180.v:6006$1527_Y - end - attribute \src "ls180.v:6006.46-6006.154" - cell $and $and$ls180.v:6006$1529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6006$1527_Y - connect \B $eq$ls180.v:6006$1528_Y - connect \Y $and$ls180.v:6006$1529_Y - end - attribute \src "ls180.v:6008.47-6008.100" - cell $and $and$ls180.v:6008$1530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6008$1530_Y - end - attribute \src "ls180.v:6008.46-6008.151" - cell $and $and$ls180.v:6008$1532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6008$1530_Y - connect \B $eq$ls180.v:6008$1531_Y - connect \Y $and$ls180.v:6008$1532_Y - end - attribute \src "ls180.v:6009.47-6009.103" - cell $and $and$ls180.v:6009$1534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6009$1533_Y - connect \Y $and$ls180.v:6009$1534_Y - end - attribute \src "ls180.v:6009.46-6009.154" - cell $and $and$ls180.v:6009$1536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6009$1534_Y - connect \B $eq$ls180.v:6009$1535_Y - connect \Y $and$ls180.v:6009$1536_Y - end - attribute \src "ls180.v:6011.47-6011.100" - cell $and $and$ls180.v:6011$1537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6011$1537_Y - end - attribute \src "ls180.v:6011.46-6011.151" - cell $and $and$ls180.v:6011$1539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6011$1537_Y - connect \B $eq$ls180.v:6011$1538_Y - connect \Y $and$ls180.v:6011$1539_Y - end - attribute \src "ls180.v:6012.47-6012.103" - cell $and $and$ls180.v:6012$1541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6012$1540_Y - connect \Y $and$ls180.v:6012$1541_Y - end - attribute \src "ls180.v:6012.46-6012.154" - cell $and $and$ls180.v:6012$1543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6012$1541_Y - connect \B $eq$ls180.v:6012$1542_Y - connect \Y $and$ls180.v:6012$1543_Y - end - attribute \src "ls180.v:6014.46-6014.99" - cell $and $and$ls180.v:6014$1544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6014$1544_Y - end - attribute \src "ls180.v:6014.45-6014.150" - cell $and $and$ls180.v:6014$1546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6014$1544_Y - connect \B $eq$ls180.v:6014$1545_Y - connect \Y $and$ls180.v:6014$1546_Y - end - attribute \src "ls180.v:6015.46-6015.102" - cell $and $and$ls180.v:6015$1548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6015$1547_Y - connect \Y $and$ls180.v:6015$1548_Y - end - attribute \src "ls180.v:6015.45-6015.153" - cell $and $and$ls180.v:6015$1550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6015$1548_Y - connect \B $eq$ls180.v:6015$1549_Y - connect \Y $and$ls180.v:6015$1550_Y - end - attribute \src "ls180.v:6017.46-6017.99" - cell $and $and$ls180.v:6017$1551 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6017$1551_Y - end - attribute \src "ls180.v:6017.45-6017.150" - cell $and $and$ls180.v:6017$1553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6017$1551_Y - connect \B $eq$ls180.v:6017$1552_Y - connect \Y $and$ls180.v:6017$1553_Y - end - attribute \src "ls180.v:6018.46-6018.102" - cell $and $and$ls180.v:6018$1555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6018$1554_Y - connect \Y $and$ls180.v:6018$1555_Y - end - attribute \src "ls180.v:6018.45-6018.153" - cell $and $and$ls180.v:6018$1557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6018$1555_Y - connect \B $eq$ls180.v:6018$1556_Y - connect \Y $and$ls180.v:6018$1557_Y - end - attribute \src "ls180.v:6020.46-6020.99" - cell $and $and$ls180.v:6020$1558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6020$1558_Y - end - attribute \src "ls180.v:6020.45-6020.150" - cell $and $and$ls180.v:6020$1560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6020$1558_Y - connect \B $eq$ls180.v:6020$1559_Y - connect \Y $and$ls180.v:6020$1560_Y - end - attribute \src "ls180.v:6021.46-6021.102" - cell $and $and$ls180.v:6021$1562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6021$1561_Y - connect \Y $and$ls180.v:6021$1562_Y - end - attribute \src "ls180.v:6021.45-6021.153" - cell $and $and$ls180.v:6021$1564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6021$1562_Y - connect \B $eq$ls180.v:6021$1563_Y - connect \Y $and$ls180.v:6021$1564_Y - end - attribute \src "ls180.v:6023.46-6023.99" - cell $and $and$ls180.v:6023$1565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6023$1565_Y - end - attribute \src "ls180.v:6023.45-6023.150" - cell $and $and$ls180.v:6023$1567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6023$1565_Y - connect \B $eq$ls180.v:6023$1566_Y - connect \Y $and$ls180.v:6023$1567_Y - end - attribute \src "ls180.v:6024.46-6024.102" - cell $and $and$ls180.v:6024$1569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6024$1568_Y - connect \Y $and$ls180.v:6024$1569_Y - end - attribute \src "ls180.v:6024.45-6024.153" - cell $and $and$ls180.v:6024$1571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6024$1569_Y - connect \B $eq$ls180.v:6024$1570_Y - connect \Y $and$ls180.v:6024$1571_Y - end - attribute \src "ls180.v:6026.46-6026.99" - cell $and $and$ls180.v:6026$1572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6026$1572_Y - end - attribute \src "ls180.v:6026.45-6026.150" - cell $and $and$ls180.v:6026$1574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6026$1572_Y - connect \B $eq$ls180.v:6026$1573_Y - connect \Y $and$ls180.v:6026$1574_Y - end - attribute \src "ls180.v:6027.46-6027.102" - cell $and $and$ls180.v:6027$1576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6027$1575_Y - connect \Y $and$ls180.v:6027$1576_Y - end - attribute \src "ls180.v:6027.45-6027.153" - cell $and $and$ls180.v:6027$1578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6027$1576_Y - connect \B $eq$ls180.v:6027$1577_Y - connect \Y $and$ls180.v:6027$1578_Y - end - attribute \src "ls180.v:6029.46-6029.99" - cell $and $and$ls180.v:6029$1579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6029$1579_Y - end - attribute \src "ls180.v:6029.45-6029.150" - cell $and $and$ls180.v:6029$1581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6029$1579_Y - connect \B $eq$ls180.v:6029$1580_Y - connect \Y $and$ls180.v:6029$1581_Y - end - attribute \src "ls180.v:6030.46-6030.102" - cell $and $and$ls180.v:6030$1583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6030$1582_Y - connect \Y $and$ls180.v:6030$1583_Y - end - attribute \src "ls180.v:6030.45-6030.153" - cell $and $and$ls180.v:6030$1585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6030$1583_Y - connect \B $eq$ls180.v:6030$1584_Y - connect \Y $and$ls180.v:6030$1585_Y - end - attribute \src "ls180.v:6032.46-6032.99" - cell $and $and$ls180.v:6032$1586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6032$1586_Y - end - attribute \src "ls180.v:6032.45-6032.150" - cell $and $and$ls180.v:6032$1588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6032$1586_Y - connect \B $eq$ls180.v:6032$1587_Y - connect \Y $and$ls180.v:6032$1588_Y - end - attribute \src "ls180.v:6033.46-6033.102" - cell $and $and$ls180.v:6033$1590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6033$1589_Y - connect \Y $and$ls180.v:6033$1590_Y - end - attribute \src "ls180.v:6033.45-6033.153" - cell $and $and$ls180.v:6033$1592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6033$1590_Y - connect \B $eq$ls180.v:6033$1591_Y - connect \Y $and$ls180.v:6033$1592_Y - end - attribute \src "ls180.v:6035.46-6035.99" - cell $and $and$ls180.v:6035$1593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6035$1593_Y - end - attribute \src "ls180.v:6035.45-6035.150" - cell $and $and$ls180.v:6035$1595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6035$1593_Y - connect \B $eq$ls180.v:6035$1594_Y - connect \Y $and$ls180.v:6035$1595_Y - end - attribute \src "ls180.v:6036.46-6036.102" - cell $and $and$ls180.v:6036$1597 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6036$1596_Y - connect \Y $and$ls180.v:6036$1597_Y - end - attribute \src "ls180.v:6036.45-6036.153" - cell $and $and$ls180.v:6036$1599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6036$1597_Y - connect \B $eq$ls180.v:6036$1598_Y - connect \Y $and$ls180.v:6036$1599_Y - end - attribute \src "ls180.v:6038.46-6038.99" - cell $and $and$ls180.v:6038$1600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6038$1600_Y - end - attribute \src "ls180.v:6038.45-6038.150" - cell $and $and$ls180.v:6038$1602 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6038$1600_Y - connect \B $eq$ls180.v:6038$1601_Y - connect \Y $and$ls180.v:6038$1602_Y - end - attribute \src "ls180.v:6039.46-6039.102" - cell $and $and$ls180.v:6039$1604 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6039$1603_Y - connect \Y $and$ls180.v:6039$1604_Y - end - attribute \src "ls180.v:6039.45-6039.153" - cell $and $and$ls180.v:6039$1606 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6039$1604_Y - connect \B $eq$ls180.v:6039$1605_Y - connect \Y $and$ls180.v:6039$1606_Y - end - attribute \src "ls180.v:6041.46-6041.99" - cell $and $and$ls180.v:6041$1607 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6041$1607_Y - end - attribute \src "ls180.v:6041.45-6041.150" - cell $and $and$ls180.v:6041$1609 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6041$1607_Y - connect \B $eq$ls180.v:6041$1608_Y - connect \Y $and$ls180.v:6041$1609_Y - end - attribute \src "ls180.v:6042.46-6042.102" - cell $and $and$ls180.v:6042$1611 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6042$1610_Y - connect \Y $and$ls180.v:6042$1611_Y - end - attribute \src "ls180.v:6042.45-6042.153" - cell $and $and$ls180.v:6042$1613 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6042$1611_Y - connect \B $eq$ls180.v:6042$1612_Y - connect \Y $and$ls180.v:6042$1613_Y - end - attribute \src "ls180.v:6044.42-6044.95" - cell $and $and$ls180.v:6044$1614 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6044$1614_Y - end - attribute \src "ls180.v:6044.41-6044.146" - cell $and $and$ls180.v:6044$1616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6044$1614_Y - connect \B $eq$ls180.v:6044$1615_Y - connect \Y $and$ls180.v:6044$1616_Y - end - attribute \src "ls180.v:6045.42-6045.98" - cell $and $and$ls180.v:6045$1618 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6045$1617_Y - connect \Y $and$ls180.v:6045$1618_Y - end - attribute \src "ls180.v:6045.41-6045.149" - cell $and $and$ls180.v:6045$1620 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6045$1618_Y - connect \B $eq$ls180.v:6045$1619_Y - connect \Y $and$ls180.v:6045$1620_Y - end - attribute \src "ls180.v:6047.43-6047.96" - cell $and $and$ls180.v:6047$1621 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6047$1621_Y - end - attribute \src "ls180.v:6047.42-6047.147" - cell $and $and$ls180.v:6047$1623 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6047$1621_Y - connect \B $eq$ls180.v:6047$1622_Y - connect \Y $and$ls180.v:6047$1623_Y - end - attribute \src "ls180.v:6048.43-6048.99" - cell $and $and$ls180.v:6048$1625 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6048$1624_Y - connect \Y $and$ls180.v:6048$1625_Y - end - attribute \src "ls180.v:6048.42-6048.150" - cell $and $and$ls180.v:6048$1627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6048$1625_Y - connect \B $eq$ls180.v:6048$1626_Y - connect \Y $and$ls180.v:6048$1627_Y - end - attribute \src "ls180.v:6050.46-6050.99" - cell $and $and$ls180.v:6050$1628 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6050$1628_Y - end - attribute \src "ls180.v:6050.45-6050.150" - cell $and $and$ls180.v:6050$1630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6050$1628_Y - connect \B $eq$ls180.v:6050$1629_Y - connect \Y $and$ls180.v:6050$1630_Y - end - attribute \src "ls180.v:6051.46-6051.102" - cell $and $and$ls180.v:6051$1632 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6051$1631_Y - connect \Y $and$ls180.v:6051$1632_Y - end - attribute \src "ls180.v:6051.45-6051.153" - cell $and $and$ls180.v:6051$1634 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6051$1632_Y - connect \B $eq$ls180.v:6051$1633_Y - connect \Y $and$ls180.v:6051$1634_Y - end - attribute \src "ls180.v:6053.46-6053.99" - cell $and $and$ls180.v:6053$1635 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6053$1635_Y - end - attribute \src "ls180.v:6053.45-6053.150" - cell $and $and$ls180.v:6053$1637 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6053$1635_Y - connect \B $eq$ls180.v:6053$1636_Y - connect \Y $and$ls180.v:6053$1637_Y - end - attribute \src "ls180.v:6054.46-6054.102" - cell $and $and$ls180.v:6054$1639 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6054$1638_Y - connect \Y $and$ls180.v:6054$1639_Y - end - attribute \src "ls180.v:6054.45-6054.153" - cell $and $and$ls180.v:6054$1641 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6054$1639_Y - connect \B $eq$ls180.v:6054$1640_Y - connect \Y $and$ls180.v:6054$1641_Y - end - attribute \src "ls180.v:6056.45-6056.98" - cell $and $and$ls180.v:6056$1642 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6056$1642_Y - end - attribute \src "ls180.v:6056.44-6056.149" - cell $and $and$ls180.v:6056$1644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6056$1642_Y - connect \B $eq$ls180.v:6056$1643_Y - connect \Y $and$ls180.v:6056$1644_Y - end - attribute \src "ls180.v:6057.45-6057.101" - cell $and $and$ls180.v:6057$1646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6057$1645_Y - connect \Y $and$ls180.v:6057$1646_Y - end - attribute \src "ls180.v:6057.44-6057.152" - cell $and $and$ls180.v:6057$1648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6057$1646_Y - connect \B $eq$ls180.v:6057$1647_Y - connect \Y $and$ls180.v:6057$1648_Y - end - attribute \src "ls180.v:6059.45-6059.98" - cell $and $and$ls180.v:6059$1649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6059$1649_Y - end - attribute \src "ls180.v:6059.44-6059.149" - cell $and $and$ls180.v:6059$1651 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6059$1649_Y - connect \B $eq$ls180.v:6059$1650_Y - connect \Y $and$ls180.v:6059$1651_Y - end - attribute \src "ls180.v:6060.45-6060.101" - cell $and $and$ls180.v:6060$1653 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6060$1652_Y - connect \Y $and$ls180.v:6060$1653_Y - end - attribute \src "ls180.v:6060.44-6060.152" - cell $and $and$ls180.v:6060$1655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6060$1653_Y - connect \B $eq$ls180.v:6060$1654_Y - connect \Y $and$ls180.v:6060$1655_Y - end - attribute \src "ls180.v:6062.45-6062.98" - cell $and $and$ls180.v:6062$1656 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6062$1656_Y - end - attribute \src "ls180.v:6062.44-6062.149" - cell $and $and$ls180.v:6062$1658 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6062$1656_Y - connect \B $eq$ls180.v:6062$1657_Y - connect \Y $and$ls180.v:6062$1658_Y - end - attribute \src "ls180.v:6063.45-6063.101" - cell $and $and$ls180.v:6063$1660 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6063$1659_Y - connect \Y $and$ls180.v:6063$1660_Y - end - attribute \src "ls180.v:6063.44-6063.152" - cell $and $and$ls180.v:6063$1662 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6063$1660_Y - connect \B $eq$ls180.v:6063$1661_Y - connect \Y $and$ls180.v:6063$1662_Y - end - attribute \src "ls180.v:6065.45-6065.98" - cell $and $and$ls180.v:6065$1663 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6065$1663_Y - end - attribute \src "ls180.v:6065.44-6065.149" - cell $and $and$ls180.v:6065$1665 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6065$1663_Y - connect \B $eq$ls180.v:6065$1664_Y - connect \Y $and$ls180.v:6065$1665_Y - end - attribute \src "ls180.v:6066.45-6066.101" - cell $and $and$ls180.v:6066$1667 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6066$1666_Y - connect \Y $and$ls180.v:6066$1667_Y - end - attribute \src "ls180.v:6066.44-6066.152" - cell $and $and$ls180.v:6066$1669 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6066$1667_Y - connect \B $eq$ls180.v:6066$1668_Y - connect \Y $and$ls180.v:6066$1669_Y - end - attribute \src "ls180.v:6104.42-6104.95" - cell $and $and$ls180.v:6104$1671 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6104$1671_Y - end - attribute \src "ls180.v:6104.41-6104.145" - cell $and $and$ls180.v:6104$1673 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6104$1671_Y - connect \B $eq$ls180.v:6104$1672_Y - connect \Y $and$ls180.v:6104$1673_Y - end - attribute \src "ls180.v:6105.42-6105.98" - cell $and $and$ls180.v:6105$1675 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6105$1674_Y - connect \Y $and$ls180.v:6105$1675_Y - end - attribute \src "ls180.v:6105.41-6105.148" - cell $and $and$ls180.v:6105$1677 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6105$1675_Y - connect \B $eq$ls180.v:6105$1676_Y - connect \Y $and$ls180.v:6105$1677_Y - end - attribute \src "ls180.v:6107.42-6107.95" - cell $and $and$ls180.v:6107$1678 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6107$1678_Y - end - attribute \src "ls180.v:6107.41-6107.145" - cell $and $and$ls180.v:6107$1680 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6107$1678_Y - connect \B $eq$ls180.v:6107$1679_Y - connect \Y $and$ls180.v:6107$1680_Y - end - attribute \src "ls180.v:6108.42-6108.98" - cell $and $and$ls180.v:6108$1682 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6108$1681_Y - connect \Y $and$ls180.v:6108$1682_Y - end - attribute \src "ls180.v:6108.41-6108.148" - cell $and $and$ls180.v:6108$1684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6108$1682_Y - connect \B $eq$ls180.v:6108$1683_Y - connect \Y $and$ls180.v:6108$1684_Y - end - attribute \src "ls180.v:6110.42-6110.95" - cell $and $and$ls180.v:6110$1685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6110$1685_Y - end - attribute \src "ls180.v:6110.41-6110.145" - cell $and $and$ls180.v:6110$1687 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6110$1685_Y - connect \B $eq$ls180.v:6110$1686_Y - connect \Y $and$ls180.v:6110$1687_Y - end - attribute \src "ls180.v:6111.42-6111.98" - cell $and $and$ls180.v:6111$1689 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6111$1688_Y - connect \Y $and$ls180.v:6111$1689_Y - end - attribute \src "ls180.v:6111.41-6111.148" - cell $and $and$ls180.v:6111$1691 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6111$1689_Y - connect \B $eq$ls180.v:6111$1690_Y - connect \Y $and$ls180.v:6111$1691_Y - end - attribute \src "ls180.v:6113.42-6113.95" - cell $and $and$ls180.v:6113$1692 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6113$1692_Y - end - attribute \src "ls180.v:6113.41-6113.145" - cell $and $and$ls180.v:6113$1694 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6113$1692_Y - connect \B $eq$ls180.v:6113$1693_Y - connect \Y $and$ls180.v:6113$1694_Y - end - attribute \src "ls180.v:6114.42-6114.98" - cell $and $and$ls180.v:6114$1696 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6114$1695_Y - connect \Y $and$ls180.v:6114$1696_Y - end - attribute \src "ls180.v:6114.41-6114.148" - cell $and $and$ls180.v:6114$1698 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6114$1696_Y - connect \B $eq$ls180.v:6114$1697_Y - connect \Y $and$ls180.v:6114$1698_Y - end - attribute \src "ls180.v:6116.42-6116.95" - cell $and $and$ls180.v:6116$1699 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6116$1699_Y - end - attribute \src "ls180.v:6116.41-6116.145" - cell $and $and$ls180.v:6116$1701 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6116$1699_Y - connect \B $eq$ls180.v:6116$1700_Y - connect \Y $and$ls180.v:6116$1701_Y - end - attribute \src "ls180.v:6117.42-6117.98" - cell $and $and$ls180.v:6117$1703 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6117$1702_Y - connect \Y $and$ls180.v:6117$1703_Y - end - attribute \src "ls180.v:6117.41-6117.148" - cell $and $and$ls180.v:6117$1705 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6117$1703_Y - connect \B $eq$ls180.v:6117$1704_Y - connect \Y $and$ls180.v:6117$1705_Y - end - attribute \src "ls180.v:6119.42-6119.95" - cell $and $and$ls180.v:6119$1706 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6119$1706_Y - end - attribute \src "ls180.v:6119.41-6119.145" - cell $and $and$ls180.v:6119$1708 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6119$1706_Y - connect \B $eq$ls180.v:6119$1707_Y - connect \Y $and$ls180.v:6119$1708_Y - end - attribute \src "ls180.v:6120.42-6120.98" - cell $and $and$ls180.v:6120$1710 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6120$1709_Y - connect \Y $and$ls180.v:6120$1710_Y - end - attribute \src "ls180.v:6120.41-6120.148" - cell $and $and$ls180.v:6120$1712 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6120$1710_Y - connect \B $eq$ls180.v:6120$1711_Y - connect \Y $and$ls180.v:6120$1712_Y - end - attribute \src "ls180.v:6122.42-6122.95" - cell $and $and$ls180.v:6122$1713 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6122$1713_Y - end - attribute \src "ls180.v:6122.41-6122.145" - cell $and $and$ls180.v:6122$1715 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6122$1713_Y - connect \B $eq$ls180.v:6122$1714_Y - connect \Y $and$ls180.v:6122$1715_Y - end - attribute \src "ls180.v:6123.42-6123.98" - cell $and $and$ls180.v:6123$1717 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6123$1716_Y - connect \Y $and$ls180.v:6123$1717_Y - end - attribute \src "ls180.v:6123.41-6123.148" - cell $and $and$ls180.v:6123$1719 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6123$1717_Y - connect \B $eq$ls180.v:6123$1718_Y - connect \Y $and$ls180.v:6123$1719_Y - end - attribute \src "ls180.v:6125.42-6125.95" - cell $and $and$ls180.v:6125$1720 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6125$1720_Y - end - attribute \src "ls180.v:6125.41-6125.145" - cell $and $and$ls180.v:6125$1722 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6125$1720_Y - connect \B $eq$ls180.v:6125$1721_Y - connect \Y $and$ls180.v:6125$1722_Y - end - attribute \src "ls180.v:6126.42-6126.98" - cell $and $and$ls180.v:6126$1724 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6126$1723_Y - connect \Y $and$ls180.v:6126$1724_Y - end - attribute \src "ls180.v:6126.41-6126.148" - cell $and $and$ls180.v:6126$1726 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6126$1724_Y - connect \B $eq$ls180.v:6126$1725_Y - connect \Y $and$ls180.v:6126$1726_Y - end - attribute \src "ls180.v:6128.44-6128.97" - cell $and $and$ls180.v:6128$1727 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6128$1727_Y - end - attribute \src "ls180.v:6128.43-6128.147" - cell $and $and$ls180.v:6128$1729 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6128$1727_Y - connect \B $eq$ls180.v:6128$1728_Y - connect \Y $and$ls180.v:6128$1729_Y - end - attribute \src "ls180.v:6129.44-6129.100" - cell $and $and$ls180.v:6129$1731 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6129$1730_Y - connect \Y $and$ls180.v:6129$1731_Y - end - attribute \src "ls180.v:6129.43-6129.150" - cell $and $and$ls180.v:6129$1733 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6129$1731_Y - connect \B $eq$ls180.v:6129$1732_Y - connect \Y $and$ls180.v:6129$1733_Y - end - attribute \src "ls180.v:6131.44-6131.97" - cell $and $and$ls180.v:6131$1734 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6131$1734_Y - end - attribute \src "ls180.v:6131.43-6131.147" - cell $and $and$ls180.v:6131$1736 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6131$1734_Y - connect \B $eq$ls180.v:6131$1735_Y - connect \Y $and$ls180.v:6131$1736_Y - end - attribute \src "ls180.v:6132.44-6132.100" - cell $and $and$ls180.v:6132$1738 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6132$1737_Y - connect \Y $and$ls180.v:6132$1738_Y - end - attribute \src "ls180.v:6132.43-6132.150" - cell $and $and$ls180.v:6132$1740 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6132$1738_Y - connect \B $eq$ls180.v:6132$1739_Y - connect \Y $and$ls180.v:6132$1740_Y - end - attribute \src "ls180.v:6134.44-6134.97" - cell $and $and$ls180.v:6134$1741 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6134$1741_Y - end - attribute \src "ls180.v:6134.43-6134.148" - cell $and $and$ls180.v:6134$1743 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6134$1741_Y - connect \B $eq$ls180.v:6134$1742_Y - connect \Y $and$ls180.v:6134$1743_Y - end - attribute \src "ls180.v:6135.44-6135.100" - cell $and $and$ls180.v:6135$1745 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6135$1744_Y - connect \Y $and$ls180.v:6135$1745_Y - end - attribute \src "ls180.v:6135.43-6135.151" - cell $and $and$ls180.v:6135$1747 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6135$1745_Y - connect \B $eq$ls180.v:6135$1746_Y - connect \Y $and$ls180.v:6135$1747_Y - end - attribute \src "ls180.v:6137.44-6137.97" - cell $and $and$ls180.v:6137$1748 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6137$1748_Y - end - attribute \src "ls180.v:6137.43-6137.148" - cell $and $and$ls180.v:6137$1750 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6137$1748_Y - connect \B $eq$ls180.v:6137$1749_Y - connect \Y $and$ls180.v:6137$1750_Y - end - attribute \src "ls180.v:6138.44-6138.100" - cell $and $and$ls180.v:6138$1752 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6138$1751_Y - connect \Y $and$ls180.v:6138$1752_Y - end - attribute \src "ls180.v:6138.43-6138.151" - cell $and $and$ls180.v:6138$1754 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6138$1752_Y - connect \B $eq$ls180.v:6138$1753_Y - connect \Y $and$ls180.v:6138$1754_Y - end - attribute \src "ls180.v:6140.44-6140.97" - cell $and $and$ls180.v:6140$1755 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6140$1755_Y - end - attribute \src "ls180.v:6140.43-6140.148" - cell $and $and$ls180.v:6140$1757 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6140$1755_Y - connect \B $eq$ls180.v:6140$1756_Y - connect \Y $and$ls180.v:6140$1757_Y - end - attribute \src "ls180.v:6141.44-6141.100" - cell $and $and$ls180.v:6141$1759 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6141$1758_Y - connect \Y $and$ls180.v:6141$1759_Y - end - attribute \src "ls180.v:6141.43-6141.151" - cell $and $and$ls180.v:6141$1761 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6141$1759_Y - connect \B $eq$ls180.v:6141$1760_Y - connect \Y $and$ls180.v:6141$1761_Y - end - attribute \src "ls180.v:6143.41-6143.94" - cell $and $and$ls180.v:6143$1762 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6143$1762_Y - end - attribute \src "ls180.v:6143.40-6143.145" - cell $and $and$ls180.v:6143$1764 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6143$1762_Y - connect \B $eq$ls180.v:6143$1763_Y - connect \Y $and$ls180.v:6143$1764_Y - end - attribute \src "ls180.v:6144.41-6144.97" - cell $and $and$ls180.v:6144$1766 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6144$1765_Y - connect \Y $and$ls180.v:6144$1766_Y - end - attribute \src "ls180.v:6144.40-6144.148" - cell $and $and$ls180.v:6144$1768 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6144$1766_Y - connect \B $eq$ls180.v:6144$1767_Y - connect \Y $and$ls180.v:6144$1768_Y - end - attribute \src "ls180.v:6146.42-6146.95" - cell $and $and$ls180.v:6146$1769 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6146$1769_Y - end - attribute \src "ls180.v:6146.41-6146.146" - cell $and $and$ls180.v:6146$1771 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6146$1769_Y - connect \B $eq$ls180.v:6146$1770_Y - connect \Y $and$ls180.v:6146$1771_Y - end - attribute \src "ls180.v:6147.42-6147.98" - cell $and $and$ls180.v:6147$1773 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6147$1772_Y - connect \Y $and$ls180.v:6147$1773_Y - end - attribute \src "ls180.v:6147.41-6147.149" - cell $and $and$ls180.v:6147$1775 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6147$1773_Y - connect \B $eq$ls180.v:6147$1774_Y - connect \Y $and$ls180.v:6147$1775_Y - end - attribute \src "ls180.v:6149.44-6149.97" - cell $and $and$ls180.v:6149$1776 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6149$1776_Y - end - attribute \src "ls180.v:6149.43-6149.148" - cell $and $and$ls180.v:6149$1778 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6149$1776_Y - connect \B $eq$ls180.v:6149$1777_Y - connect \Y $and$ls180.v:6149$1778_Y - end - attribute \src "ls180.v:6150.44-6150.100" - cell $and $and$ls180.v:6150$1780 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6150$1779_Y - connect \Y $and$ls180.v:6150$1780_Y - end - attribute \src "ls180.v:6150.43-6150.151" - cell $and $and$ls180.v:6150$1782 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6150$1780_Y - connect \B $eq$ls180.v:6150$1781_Y - connect \Y $and$ls180.v:6150$1782_Y - end - attribute \src "ls180.v:6152.44-6152.97" - cell $and $and$ls180.v:6152$1783 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6152$1783_Y - end - attribute \src "ls180.v:6152.43-6152.148" - cell $and $and$ls180.v:6152$1785 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6152$1783_Y - connect \B $eq$ls180.v:6152$1784_Y - connect \Y $and$ls180.v:6152$1785_Y - end - attribute \src "ls180.v:6153.44-6153.100" - cell $and $and$ls180.v:6153$1787 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6153$1786_Y - connect \Y $and$ls180.v:6153$1787_Y - end - attribute \src "ls180.v:6153.43-6153.151" - cell $and $and$ls180.v:6153$1789 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6153$1787_Y - connect \B $eq$ls180.v:6153$1788_Y - connect \Y $and$ls180.v:6153$1789_Y - end - attribute \src "ls180.v:6155.44-6155.97" - cell $and $and$ls180.v:6155$1790 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6155$1790_Y - end - attribute \src "ls180.v:6155.43-6155.148" - cell $and $and$ls180.v:6155$1792 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6155$1790_Y - connect \B $eq$ls180.v:6155$1791_Y - connect \Y $and$ls180.v:6155$1792_Y - end - attribute \src "ls180.v:6156.44-6156.100" - cell $and $and$ls180.v:6156$1794 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6156$1793_Y - connect \Y $and$ls180.v:6156$1794_Y - end - attribute \src "ls180.v:6156.43-6156.151" - cell $and $and$ls180.v:6156$1796 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6156$1794_Y - connect \B $eq$ls180.v:6156$1795_Y - connect \Y $and$ls180.v:6156$1796_Y - end - attribute \src "ls180.v:6158.44-6158.97" - cell $and $and$ls180.v:6158$1797 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6158$1797_Y - end - attribute \src "ls180.v:6158.43-6158.148" - cell $and $and$ls180.v:6158$1799 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6158$1797_Y - connect \B $eq$ls180.v:6158$1798_Y - connect \Y $and$ls180.v:6158$1799_Y - end - attribute \src "ls180.v:6159.44-6159.100" - cell $and $and$ls180.v:6159$1801 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6159$1800_Y - connect \Y $and$ls180.v:6159$1801_Y - end - attribute \src "ls180.v:6159.43-6159.151" - cell $and $and$ls180.v:6159$1803 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6159$1801_Y - connect \B $eq$ls180.v:6159$1802_Y - connect \Y $and$ls180.v:6159$1803_Y - end - attribute \src "ls180.v:6183.44-6183.97" - cell $and $and$ls180.v:6183$1805 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6183$1805_Y - end - attribute \src "ls180.v:6183.43-6183.147" - cell $and $and$ls180.v:6183$1807 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6183$1805_Y - connect \B $eq$ls180.v:6183$1806_Y - connect \Y $and$ls180.v:6183$1807_Y - end - attribute \src "ls180.v:6184.44-6184.100" - cell $and $and$ls180.v:6184$1809 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6184$1808_Y - connect \Y $and$ls180.v:6184$1809_Y - end - attribute \src "ls180.v:6184.43-6184.150" - cell $and $and$ls180.v:6184$1811 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6184$1809_Y - connect \B $eq$ls180.v:6184$1810_Y - connect \Y $and$ls180.v:6184$1811_Y - end - attribute \src "ls180.v:6186.49-6186.102" - cell $and $and$ls180.v:6186$1812 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6186$1812_Y - end - attribute \src "ls180.v:6186.48-6186.152" - cell $and $and$ls180.v:6186$1814 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6186$1812_Y - connect \B $eq$ls180.v:6186$1813_Y - connect \Y $and$ls180.v:6186$1814_Y - end - attribute \src "ls180.v:6187.49-6187.105" - cell $and $and$ls180.v:6187$1816 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6187$1815_Y - connect \Y $and$ls180.v:6187$1816_Y - end - attribute \src "ls180.v:6187.48-6187.155" - cell $and $and$ls180.v:6187$1818 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6187$1816_Y - connect \B $eq$ls180.v:6187$1817_Y - connect \Y $and$ls180.v:6187$1818_Y - end - attribute \src "ls180.v:6189.49-6189.102" - cell $and $and$ls180.v:6189$1819 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6189$1819_Y - end - attribute \src "ls180.v:6189.48-6189.152" - cell $and $and$ls180.v:6189$1821 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6189$1819_Y - connect \B $eq$ls180.v:6189$1820_Y - connect \Y $and$ls180.v:6189$1821_Y - end - attribute \src "ls180.v:6190.49-6190.105" - cell $and $and$ls180.v:6190$1823 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6190$1822_Y - connect \Y $and$ls180.v:6190$1823_Y - end - attribute \src "ls180.v:6190.48-6190.155" - cell $and $and$ls180.v:6190$1825 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6190$1823_Y - connect \B $eq$ls180.v:6190$1824_Y - connect \Y $and$ls180.v:6190$1825_Y - end - attribute \src "ls180.v:6192.42-6192.95" - cell $and $and$ls180.v:6192$1826 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6192$1826_Y - end - attribute \src "ls180.v:6192.41-6192.145" - cell $and $and$ls180.v:6192$1828 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6192$1826_Y - connect \B $eq$ls180.v:6192$1827_Y - connect \Y $and$ls180.v:6192$1828_Y - end - attribute \src "ls180.v:6193.42-6193.98" - cell $and $and$ls180.v:6193$1830 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6193$1829_Y - connect \Y $and$ls180.v:6193$1830_Y - end - attribute \src "ls180.v:6193.41-6193.148" - cell $and $and$ls180.v:6193$1832 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6193$1830_Y - connect \B $eq$ls180.v:6193$1831_Y - connect \Y $and$ls180.v:6193$1832_Y - end - attribute \src "ls180.v:6200.46-6200.99" - cell $and $and$ls180.v:6200$1834 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6200$1834_Y - end - attribute \src "ls180.v:6200.45-6200.149" - cell $and $and$ls180.v:6200$1836 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6200$1834_Y - connect \B $eq$ls180.v:6200$1835_Y - connect \Y $and$ls180.v:6200$1836_Y - end - attribute \src "ls180.v:6201.46-6201.102" - cell $and $and$ls180.v:6201$1838 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6201$1837_Y - connect \Y $and$ls180.v:6201$1838_Y - end - attribute \src "ls180.v:6201.45-6201.152" - cell $and $and$ls180.v:6201$1840 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6201$1838_Y - connect \B $eq$ls180.v:6201$1839_Y - connect \Y $and$ls180.v:6201$1840_Y - end - attribute \src "ls180.v:6203.50-6203.103" - cell $and $and$ls180.v:6203$1841 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6203$1841_Y - end - attribute \src "ls180.v:6203.49-6203.153" - cell $and $and$ls180.v:6203$1843 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6203$1841_Y - connect \B $eq$ls180.v:6203$1842_Y - connect \Y $and$ls180.v:6203$1843_Y - end - attribute \src "ls180.v:6204.50-6204.106" - cell $and $and$ls180.v:6204$1845 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6204$1844_Y - connect \Y $and$ls180.v:6204$1845_Y - end - attribute \src "ls180.v:6204.49-6204.156" - cell $and $and$ls180.v:6204$1847 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6204$1845_Y - connect \B $eq$ls180.v:6204$1846_Y - connect \Y $and$ls180.v:6204$1847_Y - end - attribute \src "ls180.v:6206.40-6206.93" - cell $and $and$ls180.v:6206$1848 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6206$1848_Y - end - attribute \src "ls180.v:6206.39-6206.143" - cell $and $and$ls180.v:6206$1850 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6206$1848_Y - connect \B $eq$ls180.v:6206$1849_Y - connect \Y $and$ls180.v:6206$1850_Y - end - attribute \src "ls180.v:6207.40-6207.96" - cell $and $and$ls180.v:6207$1852 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6207$1851_Y - connect \Y $and$ls180.v:6207$1852_Y - end - attribute \src "ls180.v:6207.39-6207.146" - cell $and $and$ls180.v:6207$1854 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6207$1852_Y - connect \B $eq$ls180.v:6207$1853_Y - connect \Y $and$ls180.v:6207$1854_Y - end - attribute \src "ls180.v:6209.50-6209.103" - cell $and $and$ls180.v:6209$1855 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6209$1855_Y - end - attribute \src "ls180.v:6209.49-6209.153" - cell $and $and$ls180.v:6209$1857 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6209$1855_Y - connect \B $eq$ls180.v:6209$1856_Y - connect \Y $and$ls180.v:6209$1857_Y - end - attribute \src "ls180.v:6210.50-6210.106" - cell $and $and$ls180.v:6210$1859 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6210$1858_Y - connect \Y $and$ls180.v:6210$1859_Y - end - attribute \src "ls180.v:6210.49-6210.156" - cell $and $and$ls180.v:6210$1861 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6210$1859_Y - connect \B $eq$ls180.v:6210$1860_Y - connect \Y $and$ls180.v:6210$1861_Y - end - attribute \src "ls180.v:6212.50-6212.103" - cell $and $and$ls180.v:6212$1862 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6212$1862_Y - end - attribute \src "ls180.v:6212.49-6212.153" - cell $and $and$ls180.v:6212$1864 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6212$1862_Y - connect \B $eq$ls180.v:6212$1863_Y - connect \Y $and$ls180.v:6212$1864_Y - end - attribute \src "ls180.v:6213.50-6213.106" - cell $and $and$ls180.v:6213$1866 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6213$1865_Y - connect \Y $and$ls180.v:6213$1866_Y - end - attribute \src "ls180.v:6213.49-6213.156" - cell $and $and$ls180.v:6213$1868 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6213$1866_Y - connect \B $eq$ls180.v:6213$1867_Y - connect \Y $and$ls180.v:6213$1868_Y - end - attribute \src "ls180.v:6215.51-6215.104" - cell $and $and$ls180.v:6215$1869 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6215$1869_Y - end - attribute \src "ls180.v:6215.50-6215.154" - cell $and $and$ls180.v:6215$1871 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6215$1869_Y - connect \B $eq$ls180.v:6215$1870_Y - connect \Y $and$ls180.v:6215$1871_Y - end - attribute \src "ls180.v:6216.51-6216.107" - cell $and $and$ls180.v:6216$1873 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6216$1872_Y - connect \Y $and$ls180.v:6216$1873_Y - end - attribute \src "ls180.v:6216.50-6216.157" - cell $and $and$ls180.v:6216$1875 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6216$1873_Y - connect \B $eq$ls180.v:6216$1874_Y - connect \Y $and$ls180.v:6216$1875_Y - end - attribute \src "ls180.v:6218.49-6218.102" - cell $and $and$ls180.v:6218$1876 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6218$1876_Y - end - attribute \src "ls180.v:6218.48-6218.152" - cell $and $and$ls180.v:6218$1878 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6218$1876_Y - connect \B $eq$ls180.v:6218$1877_Y - connect \Y $and$ls180.v:6218$1878_Y - end - attribute \src "ls180.v:6219.49-6219.105" - cell $and $and$ls180.v:6219$1880 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6219$1879_Y - connect \Y $and$ls180.v:6219$1880_Y - end - attribute \src "ls180.v:6219.48-6219.155" - cell $and $and$ls180.v:6219$1882 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6219$1880_Y - connect \B $eq$ls180.v:6219$1881_Y - connect \Y $and$ls180.v:6219$1882_Y - end - attribute \src "ls180.v:6221.49-6221.102" - cell $and $and$ls180.v:6221$1883 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6221$1883_Y - end - attribute \src "ls180.v:6221.48-6221.152" - cell $and $and$ls180.v:6221$1885 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6221$1883_Y - connect \B $eq$ls180.v:6221$1884_Y - connect \Y $and$ls180.v:6221$1885_Y - end - attribute \src "ls180.v:6222.49-6222.105" - cell $and $and$ls180.v:6222$1887 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6222$1886_Y - connect \Y $and$ls180.v:6222$1887_Y - end - attribute \src "ls180.v:6222.48-6222.155" - cell $and $and$ls180.v:6222$1889 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6222$1887_Y - connect \B $eq$ls180.v:6222$1888_Y - connect \Y $and$ls180.v:6222$1889_Y - end - attribute \src "ls180.v:6224.49-6224.102" - cell $and $and$ls180.v:6224$1890 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6224$1890_Y - end - attribute \src "ls180.v:6224.48-6224.152" - cell $and $and$ls180.v:6224$1892 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6224$1890_Y - connect \B $eq$ls180.v:6224$1891_Y - connect \Y $and$ls180.v:6224$1892_Y - end - attribute \src "ls180.v:6225.49-6225.105" - cell $and $and$ls180.v:6225$1894 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6225$1893_Y - connect \Y $and$ls180.v:6225$1894_Y - end - attribute \src "ls180.v:6225.48-6225.155" - cell $and $and$ls180.v:6225$1896 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6225$1894_Y - connect \B $eq$ls180.v:6225$1895_Y - connect \Y $and$ls180.v:6225$1896_Y - end - attribute \src "ls180.v:6227.49-6227.102" - cell $and $and$ls180.v:6227$1897 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6227$1897_Y - end - attribute \src "ls180.v:6227.48-6227.152" - cell $and $and$ls180.v:6227$1899 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6227$1897_Y - connect \B $eq$ls180.v:6227$1898_Y - connect \Y $and$ls180.v:6227$1899_Y - end - attribute \src "ls180.v:6228.49-6228.105" - cell $and $and$ls180.v:6228$1901 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6228$1900_Y - connect \Y $and$ls180.v:6228$1901_Y - end - attribute \src "ls180.v:6228.48-6228.155" - cell $and $and$ls180.v:6228$1903 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6228$1901_Y - connect \B $eq$ls180.v:6228$1902_Y - connect \Y $and$ls180.v:6228$1903_Y - end - attribute \src "ls180.v:6245.42-6245.97" - cell $and $and$ls180.v:6245$1905 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6245$1905_Y - end - attribute \src "ls180.v:6245.41-6245.148" - cell $and $and$ls180.v:6245$1907 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6245$1905_Y - connect \B $eq$ls180.v:6245$1906_Y - connect \Y $and$ls180.v:6245$1907_Y - end - attribute \src "ls180.v:6246.42-6246.100" - cell $and $and$ls180.v:6246$1909 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6246$1908_Y - connect \Y $and$ls180.v:6246$1909_Y - end - attribute \src "ls180.v:6246.41-6246.151" - cell $and $and$ls180.v:6246$1911 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6246$1909_Y - connect \B $eq$ls180.v:6246$1910_Y - connect \Y $and$ls180.v:6246$1911_Y - end - attribute \src "ls180.v:6248.42-6248.97" - cell $and $and$ls180.v:6248$1912 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6248$1912_Y - end - attribute \src "ls180.v:6248.41-6248.148" - cell $and $and$ls180.v:6248$1914 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6248$1912_Y - connect \B $eq$ls180.v:6248$1913_Y - connect \Y $and$ls180.v:6248$1914_Y - end - attribute \src "ls180.v:6249.42-6249.100" - cell $and $and$ls180.v:6249$1916 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6249$1915_Y - connect \Y $and$ls180.v:6249$1916_Y - end - attribute \src "ls180.v:6249.41-6249.151" - cell $and $and$ls180.v:6249$1918 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6249$1916_Y - connect \B $eq$ls180.v:6249$1917_Y - connect \Y $and$ls180.v:6249$1918_Y - end - attribute \src "ls180.v:6251.40-6251.95" - cell $and $and$ls180.v:6251$1919 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6251$1919_Y - end - attribute \src "ls180.v:6251.39-6251.146" - cell $and $and$ls180.v:6251$1921 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6251$1919_Y - connect \B $eq$ls180.v:6251$1920_Y - connect \Y $and$ls180.v:6251$1921_Y - end - attribute \src "ls180.v:6252.40-6252.98" - cell $and $and$ls180.v:6252$1923 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6252$1922_Y - connect \Y $and$ls180.v:6252$1923_Y - end - attribute \src "ls180.v:6252.39-6252.149" - cell $and $and$ls180.v:6252$1925 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6252$1923_Y - connect \B $eq$ls180.v:6252$1924_Y - connect \Y $and$ls180.v:6252$1925_Y - end - attribute \src "ls180.v:6254.39-6254.94" - cell $and $and$ls180.v:6254$1926 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6254$1926_Y - end - attribute \src "ls180.v:6254.38-6254.145" - cell $and $and$ls180.v:6254$1928 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6254$1926_Y - connect \B $eq$ls180.v:6254$1927_Y - connect \Y $and$ls180.v:6254$1928_Y - end - attribute \src "ls180.v:6255.39-6255.97" - cell $and $and$ls180.v:6255$1930 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6255$1929_Y - connect \Y $and$ls180.v:6255$1930_Y - end - attribute \src "ls180.v:6255.38-6255.148" - cell $and $and$ls180.v:6255$1932 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6255$1930_Y - connect \B $eq$ls180.v:6255$1931_Y - connect \Y $and$ls180.v:6255$1932_Y - end - attribute \src "ls180.v:6257.38-6257.93" - cell $and $and$ls180.v:6257$1933 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6257$1933_Y - end - attribute \src "ls180.v:6257.37-6257.144" - cell $and $and$ls180.v:6257$1935 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6257$1933_Y - connect \B $eq$ls180.v:6257$1934_Y - connect \Y $and$ls180.v:6257$1935_Y - end - attribute \src "ls180.v:6258.38-6258.96" - cell $and $and$ls180.v:6258$1937 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6258$1936_Y - connect \Y $and$ls180.v:6258$1937_Y - end - attribute \src "ls180.v:6258.37-6258.147" - cell $and $and$ls180.v:6258$1939 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6258$1937_Y - connect \B $eq$ls180.v:6258$1938_Y - connect \Y $and$ls180.v:6258$1939_Y - end - attribute \src "ls180.v:6260.37-6260.92" - cell $and $and$ls180.v:6260$1940 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6260$1940_Y - end - attribute \src "ls180.v:6260.36-6260.143" - cell $and $and$ls180.v:6260$1942 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6260$1940_Y - connect \B $eq$ls180.v:6260$1941_Y - connect \Y $and$ls180.v:6260$1942_Y - end - attribute \src "ls180.v:6261.37-6261.95" - cell $and $and$ls180.v:6261$1944 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6261$1943_Y - connect \Y $and$ls180.v:6261$1944_Y - end - attribute \src "ls180.v:6261.36-6261.146" - cell $and $and$ls180.v:6261$1946 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6261$1944_Y - connect \B $eq$ls180.v:6261$1945_Y - connect \Y $and$ls180.v:6261$1946_Y - end - attribute \src "ls180.v:6263.43-6263.98" - cell $and $and$ls180.v:6263$1947 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6263$1947_Y - end - attribute \src "ls180.v:6263.42-6263.149" - cell $and $and$ls180.v:6263$1949 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6263$1947_Y - connect \B $eq$ls180.v:6263$1948_Y - connect \Y $and$ls180.v:6263$1949_Y - end - attribute \src "ls180.v:6264.43-6264.101" - cell $and $and$ls180.v:6264$1951 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6264$1950_Y - connect \Y $and$ls180.v:6264$1951_Y - end - attribute \src "ls180.v:6264.42-6264.152" - cell $and $and$ls180.v:6264$1953 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6264$1951_Y - connect \B $eq$ls180.v:6264$1952_Y - connect \Y $and$ls180.v:6264$1953_Y - end - attribute \src "ls180.v:6285.42-6285.97" - cell $and $and$ls180.v:6285$1956 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6285$1956_Y - end - attribute \src "ls180.v:6285.41-6285.148" - cell $and $and$ls180.v:6285$1958 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6285$1956_Y - connect \B $eq$ls180.v:6285$1957_Y - connect \Y $and$ls180.v:6285$1958_Y - end - attribute \src "ls180.v:6286.42-6286.100" - cell $and $and$ls180.v:6286$1960 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6286$1959_Y - connect \Y $and$ls180.v:6286$1960_Y - end - attribute \src "ls180.v:6286.41-6286.151" - cell $and $and$ls180.v:6286$1962 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6286$1960_Y - connect \B $eq$ls180.v:6286$1961_Y - connect \Y $and$ls180.v:6286$1962_Y - end - attribute \src "ls180.v:6288.42-6288.97" - cell $and $and$ls180.v:6288$1963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6288$1963_Y - end - attribute \src "ls180.v:6288.41-6288.148" - cell $and $and$ls180.v:6288$1965 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6288$1963_Y - connect \B $eq$ls180.v:6288$1964_Y - connect \Y $and$ls180.v:6288$1965_Y - end - attribute \src "ls180.v:6289.42-6289.100" - cell $and $and$ls180.v:6289$1967 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6289$1966_Y - connect \Y $and$ls180.v:6289$1967_Y - end - attribute \src "ls180.v:6289.41-6289.151" - cell $and $and$ls180.v:6289$1969 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6289$1967_Y - connect \B $eq$ls180.v:6289$1968_Y - connect \Y $and$ls180.v:6289$1969_Y - end - attribute \src "ls180.v:6291.40-6291.95" - cell $and $and$ls180.v:6291$1970 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6291$1970_Y - end - attribute \src "ls180.v:6291.39-6291.146" - cell $and $and$ls180.v:6291$1972 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6291$1970_Y - connect \B $eq$ls180.v:6291$1971_Y - connect \Y $and$ls180.v:6291$1972_Y - end - attribute \src "ls180.v:6292.40-6292.98" - cell $and $and$ls180.v:6292$1974 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6292$1973_Y - connect \Y $and$ls180.v:6292$1974_Y - end - attribute \src "ls180.v:6292.39-6292.149" - cell $and $and$ls180.v:6292$1976 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6292$1974_Y - connect \B $eq$ls180.v:6292$1975_Y - connect \Y $and$ls180.v:6292$1976_Y - end - attribute \src "ls180.v:6294.39-6294.94" - cell $and $and$ls180.v:6294$1977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6294$1977_Y - end - attribute \src "ls180.v:6294.38-6294.145" - cell $and $and$ls180.v:6294$1979 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6294$1977_Y - connect \B $eq$ls180.v:6294$1978_Y - connect \Y $and$ls180.v:6294$1979_Y - end - attribute \src "ls180.v:6295.39-6295.97" - cell $and $and$ls180.v:6295$1981 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6295$1980_Y - connect \Y $and$ls180.v:6295$1981_Y - end - attribute \src "ls180.v:6295.38-6295.148" - cell $and $and$ls180.v:6295$1983 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6295$1981_Y - connect \B $eq$ls180.v:6295$1982_Y - connect \Y $and$ls180.v:6295$1983_Y - end - attribute \src "ls180.v:6297.38-6297.93" - cell $and $and$ls180.v:6297$1984 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6297$1984_Y - end - attribute \src "ls180.v:6297.37-6297.144" - cell $and $and$ls180.v:6297$1986 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6297$1984_Y - connect \B $eq$ls180.v:6297$1985_Y - connect \Y $and$ls180.v:6297$1986_Y - end - attribute \src "ls180.v:6298.38-6298.96" - cell $and $and$ls180.v:6298$1988 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6298$1987_Y - connect \Y $and$ls180.v:6298$1988_Y - end - attribute \src "ls180.v:6298.37-6298.147" - cell $and $and$ls180.v:6298$1990 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6298$1988_Y - connect \B $eq$ls180.v:6298$1989_Y - connect \Y $and$ls180.v:6298$1990_Y - end - attribute \src "ls180.v:6300.37-6300.92" - cell $and $and$ls180.v:6300$1991 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6300$1991_Y - end - attribute \src "ls180.v:6300.36-6300.143" - cell $and $and$ls180.v:6300$1993 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6300$1991_Y - connect \B $eq$ls180.v:6300$1992_Y - connect \Y $and$ls180.v:6300$1993_Y - end - attribute \src "ls180.v:6301.37-6301.95" - cell $and $and$ls180.v:6301$1995 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6301$1994_Y - connect \Y $and$ls180.v:6301$1995_Y - end - attribute \src "ls180.v:6301.36-6301.146" - cell $and $and$ls180.v:6301$1997 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6301$1995_Y - connect \B $eq$ls180.v:6301$1996_Y - connect \Y $and$ls180.v:6301$1997_Y - end - attribute \src "ls180.v:6303.43-6303.98" - cell $and $and$ls180.v:6303$1998 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6303$1998_Y - end - attribute \src "ls180.v:6303.42-6303.149" - cell $and $and$ls180.v:6303$2000 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6303$1998_Y - connect \B $eq$ls180.v:6303$1999_Y - connect \Y $and$ls180.v:6303$2000_Y - end - attribute \src "ls180.v:6304.43-6304.101" - cell $and $and$ls180.v:6304$2002 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6304$2001_Y - connect \Y $and$ls180.v:6304$2002_Y - end - attribute \src "ls180.v:6304.42-6304.152" - cell $and $and$ls180.v:6304$2004 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6304$2002_Y - connect \B $eq$ls180.v:6304$2003_Y - connect \Y $and$ls180.v:6304$2004_Y - end - attribute \src "ls180.v:6306.46-6306.101" - cell $and $and$ls180.v:6306$2005 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6306$2005_Y - end - attribute \src "ls180.v:6306.45-6306.152" - cell $and $and$ls180.v:6306$2007 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6306$2005_Y - connect \B $eq$ls180.v:6306$2006_Y - connect \Y $and$ls180.v:6306$2007_Y - end - attribute \src "ls180.v:6307.46-6307.104" - cell $and $and$ls180.v:6307$2009 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6307$2008_Y - connect \Y $and$ls180.v:6307$2009_Y - end - attribute \src "ls180.v:6307.45-6307.155" - cell $and $and$ls180.v:6307$2011 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6307$2009_Y - connect \B $eq$ls180.v:6307$2010_Y - connect \Y $and$ls180.v:6307$2011_Y - end - attribute \src "ls180.v:6309.46-6309.101" - cell $and $and$ls180.v:6309$2012 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6309$2012_Y - end - attribute \src "ls180.v:6309.45-6309.152" - cell $and $and$ls180.v:6309$2014 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6309$2012_Y - connect \B $eq$ls180.v:6309$2013_Y - connect \Y $and$ls180.v:6309$2014_Y - end - attribute \src "ls180.v:6310.46-6310.104" - cell $and $and$ls180.v:6310$2016 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6310$2015_Y - connect \Y $and$ls180.v:6310$2016_Y - end - attribute \src "ls180.v:6310.45-6310.155" - cell $and $and$ls180.v:6310$2018 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6310$2016_Y - connect \B $eq$ls180.v:6310$2017_Y - connect \Y $and$ls180.v:6310$2018_Y - end - attribute \src "ls180.v:6333.39-6333.94" - cell $and $and$ls180.v:6333$2021 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6333$2021_Y - end - attribute \src "ls180.v:6333.38-6333.145" - cell $and $and$ls180.v:6333$2023 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6333$2021_Y - connect \B $eq$ls180.v:6333$2022_Y - connect \Y $and$ls180.v:6333$2023_Y - end - attribute \src "ls180.v:6334.39-6334.97" - cell $and $and$ls180.v:6334$2025 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6334$2024_Y - connect \Y $and$ls180.v:6334$2025_Y - end - attribute \src "ls180.v:6334.38-6334.148" - cell $and $and$ls180.v:6334$2027 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6334$2025_Y - connect \B $eq$ls180.v:6334$2026_Y - connect \Y $and$ls180.v:6334$2027_Y - end - attribute \src "ls180.v:6336.39-6336.94" - cell $and $and$ls180.v:6336$2028 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6336$2028_Y - end - attribute \src "ls180.v:6336.38-6336.145" - cell $and $and$ls180.v:6336$2030 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6336$2028_Y - connect \B $eq$ls180.v:6336$2029_Y - connect \Y $and$ls180.v:6336$2030_Y - end - attribute \src "ls180.v:6337.39-6337.97" - cell $and $and$ls180.v:6337$2032 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6337$2031_Y - connect \Y $and$ls180.v:6337$2032_Y - end - attribute \src "ls180.v:6337.38-6337.148" - cell $and $and$ls180.v:6337$2034 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6337$2032_Y - connect \B $eq$ls180.v:6337$2033_Y - connect \Y $and$ls180.v:6337$2034_Y - end - attribute \src "ls180.v:6339.39-6339.94" - cell $and $and$ls180.v:6339$2035 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6339$2035_Y - end - attribute \src "ls180.v:6339.38-6339.145" - cell $and $and$ls180.v:6339$2037 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6339$2035_Y - connect \B $eq$ls180.v:6339$2036_Y - connect \Y $and$ls180.v:6339$2037_Y - end - attribute \src "ls180.v:6340.39-6340.97" - cell $and $and$ls180.v:6340$2039 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6340$2038_Y - connect \Y $and$ls180.v:6340$2039_Y - end - attribute \src "ls180.v:6340.38-6340.148" - cell $and $and$ls180.v:6340$2041 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6340$2039_Y - connect \B $eq$ls180.v:6340$2040_Y - connect \Y $and$ls180.v:6340$2041_Y - end - attribute \src "ls180.v:6342.39-6342.94" - cell $and $and$ls180.v:6342$2042 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6342$2042_Y - end - attribute \src "ls180.v:6342.38-6342.145" - cell $and $and$ls180.v:6342$2044 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6342$2042_Y - connect \B $eq$ls180.v:6342$2043_Y - connect \Y $and$ls180.v:6342$2044_Y - end - attribute \src "ls180.v:6343.39-6343.97" - cell $and $and$ls180.v:6343$2046 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6343$2045_Y - connect \Y $and$ls180.v:6343$2046_Y - end - attribute \src "ls180.v:6343.38-6343.148" - cell $and $and$ls180.v:6343$2048 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6343$2046_Y - connect \B $eq$ls180.v:6343$2047_Y - connect \Y $and$ls180.v:6343$2048_Y - end - attribute \src "ls180.v:6345.41-6345.96" - cell $and $and$ls180.v:6345$2049 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6345$2049_Y - end - attribute \src "ls180.v:6345.40-6345.147" - cell $and $and$ls180.v:6345$2051 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6345$2049_Y - connect \B $eq$ls180.v:6345$2050_Y - connect \Y $and$ls180.v:6345$2051_Y - end - attribute \src "ls180.v:6346.41-6346.99" - cell $and $and$ls180.v:6346$2053 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6346$2052_Y - connect \Y $and$ls180.v:6346$2053_Y - end - attribute \src "ls180.v:6346.40-6346.150" - cell $and $and$ls180.v:6346$2055 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6346$2053_Y - connect \B $eq$ls180.v:6346$2054_Y - connect \Y $and$ls180.v:6346$2055_Y - end - attribute \src "ls180.v:6348.41-6348.96" - cell $and $and$ls180.v:6348$2056 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6348$2056_Y - end - attribute \src "ls180.v:6348.40-6348.147" - cell $and $and$ls180.v:6348$2058 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6348$2056_Y - connect \B $eq$ls180.v:6348$2057_Y - connect \Y $and$ls180.v:6348$2058_Y - end - attribute \src "ls180.v:6349.41-6349.99" - cell $and $and$ls180.v:6349$2060 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6349$2059_Y - connect \Y $and$ls180.v:6349$2060_Y - end - attribute \src "ls180.v:6349.40-6349.150" - cell $and $and$ls180.v:6349$2062 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6349$2060_Y - connect \B $eq$ls180.v:6349$2061_Y - connect \Y $and$ls180.v:6349$2062_Y - end - attribute \src "ls180.v:6351.41-6351.96" - cell $and $and$ls180.v:6351$2063 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6351$2063_Y - end - attribute \src "ls180.v:6351.40-6351.147" - cell $and $and$ls180.v:6351$2065 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6351$2063_Y - connect \B $eq$ls180.v:6351$2064_Y - connect \Y $and$ls180.v:6351$2065_Y - end - attribute \src "ls180.v:6352.41-6352.99" - cell $and $and$ls180.v:6352$2067 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6352$2066_Y - connect \Y $and$ls180.v:6352$2067_Y - end - attribute \src "ls180.v:6352.40-6352.150" - cell $and $and$ls180.v:6352$2069 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6352$2067_Y - connect \B $eq$ls180.v:6352$2068_Y - connect \Y $and$ls180.v:6352$2069_Y - end - attribute \src "ls180.v:6354.41-6354.96" - cell $and $and$ls180.v:6354$2070 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6354$2070_Y - end - attribute \src "ls180.v:6354.40-6354.147" - cell $and $and$ls180.v:6354$2072 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6354$2070_Y - connect \B $eq$ls180.v:6354$2071_Y - connect \Y $and$ls180.v:6354$2072_Y - end - attribute \src "ls180.v:6355.41-6355.99" - cell $and $and$ls180.v:6355$2074 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6355$2073_Y - connect \Y $and$ls180.v:6355$2074_Y - end - attribute \src "ls180.v:6355.40-6355.150" - cell $and $and$ls180.v:6355$2076 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6355$2074_Y - connect \B $eq$ls180.v:6355$2075_Y - connect \Y $and$ls180.v:6355$2076_Y - end - attribute \src "ls180.v:6357.37-6357.92" - cell $and $and$ls180.v:6357$2077 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6357$2077_Y - end - attribute \src "ls180.v:6357.36-6357.143" - cell $and $and$ls180.v:6357$2079 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6357$2077_Y - connect \B $eq$ls180.v:6357$2078_Y - connect \Y $and$ls180.v:6357$2079_Y - end - attribute \src "ls180.v:6358.37-6358.95" - cell $and $and$ls180.v:6358$2081 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6358$2080_Y - connect \Y $and$ls180.v:6358$2081_Y - end - attribute \src "ls180.v:6358.36-6358.146" - cell $and $and$ls180.v:6358$2083 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6358$2081_Y - connect \B $eq$ls180.v:6358$2082_Y - connect \Y $and$ls180.v:6358$2083_Y - end - attribute \src "ls180.v:6360.47-6360.102" - cell $and $and$ls180.v:6360$2084 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6360$2084_Y - end - attribute \src "ls180.v:6360.46-6360.153" - cell $and $and$ls180.v:6360$2086 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6360$2084_Y - connect \B $eq$ls180.v:6360$2085_Y - connect \Y $and$ls180.v:6360$2086_Y - end - attribute \src "ls180.v:6361.47-6361.105" - cell $and $and$ls180.v:6361$2088 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6361$2087_Y - connect \Y $and$ls180.v:6361$2088_Y - end - attribute \src "ls180.v:6361.46-6361.156" - cell $and $and$ls180.v:6361$2090 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6361$2088_Y - connect \B $eq$ls180.v:6361$2089_Y - connect \Y $and$ls180.v:6361$2090_Y - end - attribute \src "ls180.v:6363.40-6363.95" - cell $and $and$ls180.v:6363$2091 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6363$2091_Y - end - attribute \src "ls180.v:6363.39-6363.147" - cell $and $and$ls180.v:6363$2093 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6363$2091_Y - connect \B $eq$ls180.v:6363$2092_Y - connect \Y $and$ls180.v:6363$2093_Y - end - attribute \src "ls180.v:6364.40-6364.98" - cell $and $and$ls180.v:6364$2095 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6364$2094_Y - connect \Y $and$ls180.v:6364$2095_Y - end - attribute \src "ls180.v:6364.39-6364.150" - cell $and $and$ls180.v:6364$2097 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6364$2095_Y - connect \B $eq$ls180.v:6364$2096_Y - connect \Y $and$ls180.v:6364$2097_Y - end - attribute \src "ls180.v:6366.40-6366.95" - cell $and $and$ls180.v:6366$2098 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6366$2098_Y - end - attribute \src "ls180.v:6366.39-6366.147" - cell $and $and$ls180.v:6366$2100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6366$2098_Y - connect \B $eq$ls180.v:6366$2099_Y - connect \Y $and$ls180.v:6366$2100_Y - end - attribute \src "ls180.v:6367.40-6367.98" - cell $and $and$ls180.v:6367$2102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6367$2101_Y - connect \Y $and$ls180.v:6367$2102_Y - end - attribute \src "ls180.v:6367.39-6367.150" - cell $and $and$ls180.v:6367$2104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6367$2102_Y - connect \B $eq$ls180.v:6367$2103_Y - connect \Y $and$ls180.v:6367$2104_Y - end - attribute \src "ls180.v:6369.40-6369.95" - cell $and $and$ls180.v:6369$2105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6369$2105_Y - end - attribute \src "ls180.v:6369.39-6369.147" - cell $and $and$ls180.v:6369$2107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6369$2105_Y - connect \B $eq$ls180.v:6369$2106_Y - connect \Y $and$ls180.v:6369$2107_Y - end - attribute \src "ls180.v:6370.40-6370.98" - cell $and $and$ls180.v:6370$2109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6370$2108_Y - connect \Y $and$ls180.v:6370$2109_Y - end - attribute \src "ls180.v:6370.39-6370.150" - cell $and $and$ls180.v:6370$2111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6370$2109_Y - connect \B $eq$ls180.v:6370$2110_Y - connect \Y $and$ls180.v:6370$2111_Y - end - attribute \src "ls180.v:6372.40-6372.95" - cell $and $and$ls180.v:6372$2112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6372$2112_Y - end - attribute \src "ls180.v:6372.39-6372.147" - cell $and $and$ls180.v:6372$2114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6372$2112_Y - connect \B $eq$ls180.v:6372$2113_Y - connect \Y $and$ls180.v:6372$2114_Y - end - attribute \src "ls180.v:6373.40-6373.98" - cell $and $and$ls180.v:6373$2116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6373$2115_Y - connect \Y $and$ls180.v:6373$2116_Y - end - attribute \src "ls180.v:6373.39-6373.150" - cell $and $and$ls180.v:6373$2118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6373$2116_Y - connect \B $eq$ls180.v:6373$2117_Y - connect \Y $and$ls180.v:6373$2118_Y - end - attribute \src "ls180.v:6375.52-6375.107" - cell $and $and$ls180.v:6375$2119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6375$2119_Y - end - attribute \src "ls180.v:6375.51-6375.159" - cell $and $and$ls180.v:6375$2121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6375$2119_Y - connect \B $eq$ls180.v:6375$2120_Y - connect \Y $and$ls180.v:6375$2121_Y - end - attribute \src "ls180.v:6376.52-6376.110" - cell $and $and$ls180.v:6376$2123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6376$2122_Y - connect \Y $and$ls180.v:6376$2123_Y - end - attribute \src "ls180.v:6376.51-6376.162" - cell $and $and$ls180.v:6376$2125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6376$2123_Y - connect \B $eq$ls180.v:6376$2124_Y - connect \Y $and$ls180.v:6376$2125_Y - end - attribute \src "ls180.v:6378.53-6378.108" - cell $and $and$ls180.v:6378$2126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6378$2126_Y - end - attribute \src "ls180.v:6378.52-6378.160" - cell $and $and$ls180.v:6378$2128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6378$2126_Y - connect \B $eq$ls180.v:6378$2127_Y - connect \Y $and$ls180.v:6378$2128_Y - end - attribute \src "ls180.v:6379.53-6379.111" - cell $and $and$ls180.v:6379$2130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6379$2129_Y - connect \Y $and$ls180.v:6379$2130_Y - end - attribute \src "ls180.v:6379.52-6379.163" - cell $and $and$ls180.v:6379$2132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6379$2130_Y - connect \B $eq$ls180.v:6379$2131_Y - connect \Y $and$ls180.v:6379$2132_Y - end - attribute \src "ls180.v:6381.44-6381.99" - cell $and $and$ls180.v:6381$2133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6381$2133_Y - end - attribute \src "ls180.v:6381.43-6381.151" - cell $and $and$ls180.v:6381$2135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6381$2133_Y - connect \B $eq$ls180.v:6381$2134_Y - connect \Y $and$ls180.v:6381$2135_Y - end - attribute \src "ls180.v:6382.44-6382.102" - cell $and $and$ls180.v:6382$2137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6382$2136_Y - connect \Y $and$ls180.v:6382$2137_Y - end - attribute \src "ls180.v:6382.43-6382.154" - cell $and $and$ls180.v:6382$2139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6382$2137_Y - connect \B $eq$ls180.v:6382$2138_Y - connect \Y $and$ls180.v:6382$2139_Y - end - attribute \src "ls180.v:6401.30-6401.85" - cell $and $and$ls180.v:6401$2141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6401$2141_Y - end - attribute \src "ls180.v:6401.29-6401.136" - cell $and $and$ls180.v:6401$2143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6401$2141_Y - connect \B $eq$ls180.v:6401$2142_Y - connect \Y $and$ls180.v:6401$2143_Y - end - attribute \src "ls180.v:6402.30-6402.88" - cell $and $and$ls180.v:6402$2145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6402$2144_Y - connect \Y $and$ls180.v:6402$2145_Y - end - attribute \src "ls180.v:6402.29-6402.139" - cell $and $and$ls180.v:6402$2147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6402$2145_Y - connect \B $eq$ls180.v:6402$2146_Y - connect \Y $and$ls180.v:6402$2147_Y - end - attribute \src "ls180.v:6404.40-6404.95" - cell $and $and$ls180.v:6404$2148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6404$2148_Y - end - attribute \src "ls180.v:6404.39-6404.146" - cell $and $and$ls180.v:6404$2150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6404$2148_Y - connect \B $eq$ls180.v:6404$2149_Y - connect \Y $and$ls180.v:6404$2150_Y - end - attribute \src "ls180.v:6405.40-6405.98" - cell $and $and$ls180.v:6405$2152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6405$2151_Y - connect \Y $and$ls180.v:6405$2152_Y - end - attribute \src "ls180.v:6405.39-6405.149" - cell $and $and$ls180.v:6405$2154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6405$2152_Y - connect \B $eq$ls180.v:6405$2153_Y - connect \Y $and$ls180.v:6405$2154_Y - end - attribute \src "ls180.v:6407.41-6407.96" - cell $and $and$ls180.v:6407$2155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6407$2155_Y - end - attribute \src "ls180.v:6407.40-6407.147" - cell $and $and$ls180.v:6407$2157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6407$2155_Y - connect \B $eq$ls180.v:6407$2156_Y - connect \Y $and$ls180.v:6407$2157_Y - end - attribute \src "ls180.v:6408.41-6408.99" - cell $and $and$ls180.v:6408$2159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6408$2158_Y - connect \Y $and$ls180.v:6408$2159_Y - end - attribute \src "ls180.v:6408.40-6408.150" - cell $and $and$ls180.v:6408$2161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6408$2159_Y - connect \B $eq$ls180.v:6408$2160_Y - connect \Y $and$ls180.v:6408$2161_Y - end - attribute \src "ls180.v:6410.45-6410.100" - cell $and $and$ls180.v:6410$2162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6410$2162_Y - end - attribute \src "ls180.v:6410.44-6410.151" - cell $and $and$ls180.v:6410$2164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6410$2162_Y - connect \B $eq$ls180.v:6410$2163_Y - connect \Y $and$ls180.v:6410$2164_Y - end - attribute \src "ls180.v:6411.45-6411.103" - cell $and $and$ls180.v:6411$2166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6411$2165_Y - connect \Y $and$ls180.v:6411$2166_Y - end - attribute \src "ls180.v:6411.44-6411.154" - cell $and $and$ls180.v:6411$2168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6411$2166_Y - connect \B $eq$ls180.v:6411$2167_Y - connect \Y $and$ls180.v:6411$2168_Y - end - attribute \src "ls180.v:6413.46-6413.101" - cell $and $and$ls180.v:6413$2169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6413$2169_Y - end - attribute \src "ls180.v:6413.45-6413.152" - cell $and $and$ls180.v:6413$2171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6413$2169_Y - connect \B $eq$ls180.v:6413$2170_Y - connect \Y $and$ls180.v:6413$2171_Y - end - attribute \src "ls180.v:6414.46-6414.104" - cell $and $and$ls180.v:6414$2173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6414$2172_Y - connect \Y $and$ls180.v:6414$2173_Y - end - attribute \src "ls180.v:6414.45-6414.155" - cell $and $and$ls180.v:6414$2175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6414$2173_Y - connect \B $eq$ls180.v:6414$2174_Y - connect \Y $and$ls180.v:6414$2175_Y - end - attribute \src "ls180.v:6416.44-6416.99" - cell $and $and$ls180.v:6416$2176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6416$2176_Y - end - attribute \src "ls180.v:6416.43-6416.150" - cell $and $and$ls180.v:6416$2178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6416$2176_Y - connect \B $eq$ls180.v:6416$2177_Y - connect \Y $and$ls180.v:6416$2178_Y - end - attribute \src "ls180.v:6417.44-6417.102" - cell $and $and$ls180.v:6417$2180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6417$2179_Y - connect \Y $and$ls180.v:6417$2180_Y - end - attribute \src "ls180.v:6417.43-6417.153" - cell $and $and$ls180.v:6417$2182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6417$2180_Y - connect \B $eq$ls180.v:6417$2181_Y - connect \Y $and$ls180.v:6417$2182_Y - end - attribute \src "ls180.v:6419.41-6419.96" - cell $and $and$ls180.v:6419$2183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6419$2183_Y - end - attribute \src "ls180.v:6419.40-6419.147" - cell $and $and$ls180.v:6419$2185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6419$2183_Y - connect \B $eq$ls180.v:6419$2184_Y - connect \Y $and$ls180.v:6419$2185_Y - end - attribute \src "ls180.v:6420.41-6420.99" - cell $and $and$ls180.v:6420$2187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6420$2186_Y - connect \Y $and$ls180.v:6420$2187_Y - end - attribute \src "ls180.v:6420.40-6420.150" - cell $and $and$ls180.v:6420$2189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6420$2187_Y - connect \B $eq$ls180.v:6420$2188_Y - connect \Y $and$ls180.v:6420$2189_Y - end - attribute \src "ls180.v:6422.40-6422.95" - cell $and $and$ls180.v:6422$2190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6422$2190_Y - end - attribute \src "ls180.v:6422.39-6422.146" - cell $and $and$ls180.v:6422$2192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6422$2190_Y - connect \B $eq$ls180.v:6422$2191_Y - connect \Y $and$ls180.v:6422$2192_Y - end - attribute \src "ls180.v:6423.40-6423.98" - cell $and $and$ls180.v:6423$2194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6423$2193_Y - connect \Y $and$ls180.v:6423$2194_Y - end - attribute \src "ls180.v:6423.39-6423.149" - cell $and $and$ls180.v:6423$2196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6423$2194_Y - connect \B $eq$ls180.v:6423$2195_Y - connect \Y $and$ls180.v:6423$2196_Y - end - attribute \src "ls180.v:6435.46-6435.101" - cell $and $and$ls180.v:6435$2198 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6435$2198_Y - end - attribute \src "ls180.v:6435.45-6435.152" - cell $and $and$ls180.v:6435$2200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6435$2198_Y - connect \B $eq$ls180.v:6435$2199_Y - connect \Y $and$ls180.v:6435$2200_Y - end - attribute \src "ls180.v:6436.46-6436.104" - cell $and $and$ls180.v:6436$2202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6436$2201_Y - connect \Y $and$ls180.v:6436$2202_Y - end - attribute \src "ls180.v:6436.45-6436.155" - cell $and $and$ls180.v:6436$2204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6436$2202_Y - connect \B $eq$ls180.v:6436$2203_Y - connect \Y $and$ls180.v:6436$2204_Y - end - attribute \src "ls180.v:6438.46-6438.101" - cell $and $and$ls180.v:6438$2205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6438$2205_Y - end - attribute \src "ls180.v:6438.45-6438.152" - cell $and $and$ls180.v:6438$2207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6438$2205_Y - connect \B $eq$ls180.v:6438$2206_Y - connect \Y $and$ls180.v:6438$2207_Y - end - attribute \src "ls180.v:6439.46-6439.104" - cell $and $and$ls180.v:6439$2209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6439$2208_Y - connect \Y $and$ls180.v:6439$2209_Y - end - attribute \src "ls180.v:6439.45-6439.155" - cell $and $and$ls180.v:6439$2211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6439$2209_Y - connect \B $eq$ls180.v:6439$2210_Y - connect \Y $and$ls180.v:6439$2211_Y - end - attribute \src "ls180.v:6441.46-6441.101" - cell $and $and$ls180.v:6441$2212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6441$2212_Y - end - attribute \src "ls180.v:6441.45-6441.152" - cell $and $and$ls180.v:6441$2214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6441$2212_Y - connect \B $eq$ls180.v:6441$2213_Y - connect \Y $and$ls180.v:6441$2214_Y - end - attribute \src "ls180.v:6442.46-6442.104" - cell $and $and$ls180.v:6442$2216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6442$2215_Y - connect \Y $and$ls180.v:6442$2216_Y - end - attribute \src "ls180.v:6442.45-6442.155" - cell $and $and$ls180.v:6442$2218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6442$2216_Y - connect \B $eq$ls180.v:6442$2217_Y - connect \Y $and$ls180.v:6442$2218_Y - end - attribute \src "ls180.v:6444.46-6444.101" - cell $and $and$ls180.v:6444$2219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6444$2219_Y - end - attribute \src "ls180.v:6444.45-6444.152" - cell $and $and$ls180.v:6444$2221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6444$2219_Y - connect \B $eq$ls180.v:6444$2220_Y - connect \Y $and$ls180.v:6444$2221_Y - end - attribute \src "ls180.v:6445.46-6445.104" - cell $and $and$ls180.v:6445$2223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6445$2222_Y - connect \Y $and$ls180.v:6445$2223_Y - end - attribute \src "ls180.v:6445.45-6445.155" - cell $and $and$ls180.v:6445$2225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6445$2223_Y - connect \B $eq$ls180.v:6445$2224_Y - connect \Y $and$ls180.v:6445$2225_Y - end - attribute \src "ls180.v:6826.109-6826.178" - cell $and $and$ls180.v:6826$2263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6826$2262_Y - connect \Y $and$ls180.v:6826$2263_Y - end - attribute \src "ls180.v:6826.184-6826.253" - cell $and $and$ls180.v:6826$2266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6826$2265_Y - connect \Y $and$ls180.v:6826$2266_Y - end - attribute \src "ls180.v:6826.259-6826.328" - cell $and $and$ls180.v:6826$2269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6826$2268_Y - connect \Y $and$ls180.v:6826$2269_Y - end - attribute \src "ls180.v:6826.40-6826.331" - cell $and $and$ls180.v:6826$2272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6826$2261_Y - connect \B $not$ls180.v:6826$2271_Y - connect \Y $and$ls180.v:6826$2272_Y - end - attribute \src "ls180.v:6826.39-6826.354" - cell $and $and$ls180.v:6826$2273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6826$2272_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6826$2273_Y - end - attribute \src "ls180.v:6850.109-6850.178" - cell $and $and$ls180.v:6850$2279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6850$2278_Y - connect \Y $and$ls180.v:6850$2279_Y - end - attribute \src "ls180.v:6850.184-6850.253" - cell $and $and$ls180.v:6850$2282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6850$2281_Y - connect \Y $and$ls180.v:6850$2282_Y - end - attribute \src "ls180.v:6850.259-6850.328" - cell $and $and$ls180.v:6850$2285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6850$2284_Y - connect \Y $and$ls180.v:6850$2285_Y - end - attribute \src "ls180.v:6850.40-6850.331" - cell $and $and$ls180.v:6850$2288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6850$2277_Y - connect \B $not$ls180.v:6850$2287_Y - connect \Y $and$ls180.v:6850$2288_Y - end - attribute \src "ls180.v:6850.39-6850.354" - cell $and $and$ls180.v:6850$2289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6850$2288_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6850$2289_Y - end - attribute \src "ls180.v:6874.109-6874.178" - cell $and $and$ls180.v:6874$2295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6874$2294_Y - connect \Y $and$ls180.v:6874$2295_Y - end - attribute \src "ls180.v:6874.184-6874.253" - cell $and $and$ls180.v:6874$2298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6874$2297_Y - connect \Y $and$ls180.v:6874$2298_Y - end - attribute \src "ls180.v:6874.259-6874.328" - cell $and $and$ls180.v:6874$2301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6874$2300_Y - connect \Y $and$ls180.v:6874$2301_Y - end - attribute \src "ls180.v:6874.40-6874.331" - cell $and $and$ls180.v:6874$2304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6874$2293_Y - connect \B $not$ls180.v:6874$2303_Y - connect \Y $and$ls180.v:6874$2304_Y - end - attribute \src "ls180.v:6874.39-6874.354" - cell $and $and$ls180.v:6874$2305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6874$2304_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6874$2305_Y - end - attribute \src "ls180.v:6898.109-6898.178" - cell $and $and$ls180.v:6898$2311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6898$2310_Y - connect \Y $and$ls180.v:6898$2311_Y - end - attribute \src "ls180.v:6898.184-6898.253" - cell $and $and$ls180.v:6898$2314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6898$2313_Y - connect \Y $and$ls180.v:6898$2314_Y - end - attribute \src "ls180.v:6898.259-6898.328" - cell $and $and$ls180.v:6898$2317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6898$2316_Y - connect \Y $and$ls180.v:6898$2317_Y - end - attribute \src "ls180.v:6898.40-6898.331" - cell $and $and$ls180.v:6898$2320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6898$2309_Y - connect \B $not$ls180.v:6898$2319_Y - connect \Y $and$ls180.v:6898$2320_Y - end - attribute \src "ls180.v:6898.39-6898.354" - cell $and $and$ls180.v:6898$2321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6898$2320_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6898$2321_Y - end - attribute \src "ls180.v:7103.39-7103.104" - cell $and $and$ls180.v:7103$2333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7103$2333_Y - end - attribute \src "ls180.v:7103.38-7103.145" - cell $and $and$ls180.v:7103$2334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7103$2333_Y - connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7103$2334_Y - end - attribute \src "ls180.v:7106.39-7106.104" - cell $and $and$ls180.v:7106$2335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7106$2335_Y - end - attribute \src "ls180.v:7106.38-7106.145" - cell $and $and$ls180.v:7106$2336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7106$2335_Y - connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7106$2336_Y - end - attribute \src "ls180.v:7109.39-7109.82" - cell $and $and$ls180.v:7109$2337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7109$2337_Y - end - attribute \src "ls180.v:7109.38-7109.112" - cell $and $and$ls180.v:7109$2338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7109$2337_Y - connect \B \main_sdram_cmd_payload_cas - connect \Y $and$ls180.v:7109$2338_Y - end - attribute \src "ls180.v:7120.39-7120.104" - cell $and $and$ls180.v:7120$2340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7120$2340_Y - end - attribute \src "ls180.v:7120.38-7120.145" - cell $and $and$ls180.v:7120$2341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7120$2340_Y - connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7120$2341_Y - end - attribute \src "ls180.v:7123.39-7123.104" - cell $and $and$ls180.v:7123$2342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7123$2342_Y - end - attribute \src "ls180.v:7123.38-7123.145" - cell $and $and$ls180.v:7123$2343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7123$2342_Y - connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7123$2343_Y - end - attribute \src "ls180.v:7126.39-7126.82" - cell $and $and$ls180.v:7126$2344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7126$2344_Y - end - attribute \src "ls180.v:7126.38-7126.112" - cell $and $and$ls180.v:7126$2345 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7126$2344_Y - connect \B \main_sdram_cmd_payload_ras - connect \Y $and$ls180.v:7126$2345_Y - end - attribute \src "ls180.v:7137.39-7137.104" - cell $and $and$ls180.v:7137$2347 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7137$2347_Y - end - attribute \src "ls180.v:7137.38-7137.144" - cell $and $and$ls180.v:7137$2348 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7137$2347_Y - connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7137$2348_Y - end - attribute \src "ls180.v:7140.39-7140.104" - cell $and $and$ls180.v:7140$2349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7140$2349_Y - end - attribute \src "ls180.v:7140.38-7140.144" - cell $and $and$ls180.v:7140$2350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7140$2349_Y - connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7140$2350_Y - end - attribute \src "ls180.v:7143.39-7143.82" - cell $and $and$ls180.v:7143$2351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7143$2351_Y - end - attribute \src "ls180.v:7143.38-7143.111" - cell $and $and$ls180.v:7143$2352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7143$2351_Y - connect \B \main_sdram_cmd_payload_we - connect \Y $and$ls180.v:7143$2352_Y - end - attribute \src "ls180.v:7154.39-7154.104" - cell $and $and$ls180.v:7154$2354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7154$2354_Y - end - attribute \src "ls180.v:7154.38-7154.149" - cell $and $and$ls180.v:7154$2355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7154$2354_Y - connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7154$2355_Y - end - attribute \src "ls180.v:7157.39-7157.104" - cell $and $and$ls180.v:7157$2356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7157$2356_Y - end - attribute \src "ls180.v:7157.38-7157.149" - cell $and $and$ls180.v:7157$2357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7157$2356_Y - connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7157$2357_Y - end - attribute \src "ls180.v:7160.39-7160.82" - cell $and $and$ls180.v:7160$2358 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7160$2358_Y - end - attribute \src "ls180.v:7160.38-7160.116" - cell $and $and$ls180.v:7160$2359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7160$2358_Y - connect \B \main_sdram_cmd_payload_is_read - connect \Y $and$ls180.v:7160$2359_Y - end - attribute \src "ls180.v:7171.39-7171.104" - cell $and $and$ls180.v:7171$2361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7171$2361_Y - end - attribute \src "ls180.v:7171.38-7171.150" - cell $and $and$ls180.v:7171$2362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7171$2361_Y - connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7171$2362_Y - end - attribute \src "ls180.v:7174.39-7174.104" - cell $and $and$ls180.v:7174$2363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7174$2363_Y - end - attribute \src "ls180.v:7174.38-7174.150" - cell $and $and$ls180.v:7174$2364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7174$2363_Y - connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7174$2364_Y - end - attribute \src "ls180.v:7177.39-7177.82" - cell $and $and$ls180.v:7177$2365 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7177$2365_Y - end - attribute \src "ls180.v:7177.38-7177.117" - cell $and $and$ls180.v:7177$2366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7177$2365_Y - connect \B \main_sdram_cmd_payload_is_write - connect \Y $and$ls180.v:7177$2366_Y - end - attribute \src "ls180.v:7396.17-7396.67" - cell $and $and$ls180.v:7396$2373 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7396$2372_Y - connect \B \main_sdphy_sdpads_clk - connect \Y $and$ls180.v:7396$2373_Y - end - attribute \src "ls180.v:7487.8-7487.67" - cell $and $and$ls180.v:7487$2416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:7487$2416_Y - end - attribute \src "ls180.v:7487.7-7487.102" - cell $and $and$ls180.v:7487$2418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7487$2416_Y - connect \B $not$ls180.v:7487$2417_Y - connect \Y $and$ls180.v:7487$2418_Y - end - attribute \src "ls180.v:7506.7-7506.75" - cell $and $and$ls180.v:7506$2422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7506$2421_Y - connect \B \main_libresocsim_zero_old_trigger - connect \Y $and$ls180.v:7506$2422_Y - end - attribute \src "ls180.v:7514.7-7514.56" - cell $and $and$ls180.v:7514$2424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_wait - connect \B $not$ls180.v:7514$2423_Y - connect \Y $and$ls180.v:7514$2424_Y - end - attribute \src "ls180.v:7542.7-7542.75" - cell $and $and$ls180.v:7542$2431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_start1 - connect \B $eq$ls180.v:7542$2430_Y - connect \Y $and$ls180.v:7542$2431_Y - end - attribute \src "ls180.v:7584.8-7584.131" - cell $and $and$ls180.v:7584$2437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7584$2437_Y - end - attribute \src "ls180.v:7584.7-7584.190" - cell $and $and$ls180.v:7584$2439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7584$2437_Y - connect \B $not$ls180.v:7584$2438_Y - connect \Y $and$ls180.v:7584$2439_Y - end - attribute \src "ls180.v:7590.8-7590.131" - cell $and $and$ls180.v:7590$2442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7590$2442_Y - end - attribute \src "ls180.v:7590.7-7590.190" - cell $and $and$ls180.v:7590$2444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7590$2442_Y - connect \B $not$ls180.v:7590$2443_Y - connect \Y $and$ls180.v:7590$2444_Y - end - attribute \src "ls180.v:7630.8-7630.131" - cell $and $and$ls180.v:7630$2453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7630$2453_Y - end - attribute \src "ls180.v:7630.7-7630.190" - cell $and $and$ls180.v:7630$2455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7630$2453_Y - connect \B $not$ls180.v:7630$2454_Y - connect \Y $and$ls180.v:7630$2455_Y - end - attribute \src "ls180.v:7636.8-7636.131" - cell $and $and$ls180.v:7636$2458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7636$2458_Y - end - attribute \src "ls180.v:7636.7-7636.190" - cell $and $and$ls180.v:7636$2460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7636$2458_Y - connect \B $not$ls180.v:7636$2459_Y - connect \Y $and$ls180.v:7636$2460_Y - end - attribute \src "ls180.v:7676.8-7676.131" - cell $and $and$ls180.v:7676$2469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7676$2469_Y - end - attribute \src "ls180.v:7676.7-7676.190" - cell $and $and$ls180.v:7676$2471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7676$2469_Y - connect \B $not$ls180.v:7676$2470_Y - connect \Y $and$ls180.v:7676$2471_Y - end - attribute \src "ls180.v:7682.8-7682.131" - cell $and $and$ls180.v:7682$2474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7682$2474_Y - end - attribute \src "ls180.v:7682.7-7682.190" - cell $and $and$ls180.v:7682$2476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7682$2474_Y - connect \B $not$ls180.v:7682$2475_Y - connect \Y $and$ls180.v:7682$2476_Y - end - attribute \src "ls180.v:7722.8-7722.131" - cell $and $and$ls180.v:7722$2485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:7722$2485_Y - end - attribute \src "ls180.v:7722.7-7722.190" - cell $and $and$ls180.v:7722$2487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7722$2485_Y - connect \B $not$ls180.v:7722$2486_Y - connect \Y $and$ls180.v:7722$2487_Y - end - attribute \src "ls180.v:7728.8-7728.131" - cell $and $and$ls180.v:7728$2490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:7728$2490_Y - end - attribute \src "ls180.v:7728.7-7728.190" - cell $and $and$ls180.v:7728$2492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7728$2490_Y - connect \B $not$ls180.v:7728$2491_Y - connect \Y $and$ls180.v:7728$2492_Y - end - attribute \src "ls180.v:7925.48-7925.124" - cell $and $and$ls180.v:7925$2517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7925$2516_Y - connect \B \main_sdram_interface_bank0_wdata_ready - connect \Y $and$ls180.v:7925$2517_Y - end - attribute \src "ls180.v:7925.130-7925.206" - cell $and $and$ls180.v:7925$2520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7925$2519_Y - connect \B \main_sdram_interface_bank1_wdata_ready - connect \Y $and$ls180.v:7925$2520_Y - end - attribute \src "ls180.v:7925.212-7925.288" - cell $and $and$ls180.v:7925$2523 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7925$2522_Y - connect \B \main_sdram_interface_bank2_wdata_ready - connect \Y $and$ls180.v:7925$2523_Y - end - attribute \src "ls180.v:7925.294-7925.370" - cell $and $and$ls180.v:7925$2526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7925$2525_Y - connect \B \main_sdram_interface_bank3_wdata_ready - connect \Y $and$ls180.v:7925$2526_Y - end - attribute \src "ls180.v:7926.49-7926.125" - cell $and $and$ls180.v:7926$2529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7926$2528_Y - connect \B \main_sdram_interface_bank0_rdata_valid - connect \Y $and$ls180.v:7926$2529_Y - end - attribute \src "ls180.v:7926.131-7926.207" - cell $and $and$ls180.v:7926$2532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7926$2531_Y - connect \B \main_sdram_interface_bank1_rdata_valid - connect \Y $and$ls180.v:7926$2532_Y - end - attribute \src "ls180.v:7926.213-7926.289" - cell $and $and$ls180.v:7926$2535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7926$2534_Y - connect \B \main_sdram_interface_bank2_rdata_valid - connect \Y $and$ls180.v:7926$2535_Y - end - attribute \src "ls180.v:7926.295-7926.371" - cell $and $and$ls180.v:7926$2538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7926$2537_Y - connect \B \main_sdram_interface_bank3_rdata_valid - connect \Y $and$ls180.v:7926$2538_Y - end - attribute \src "ls180.v:7945.8-7945.49" - cell $and $and$ls180.v:7945$2541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:7945$2541_Y - end - attribute \src "ls180.v:7948.8-7948.53" - cell $and $and$ls180.v:7948$2542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_wdata_valid - connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:7948$2542_Y - end - attribute \src "ls180.v:7953.8-7953.59" - cell $and $and$ls180.v:7953$2544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_sink_valid - connect \B $not$ls180.v:7953$2543_Y - connect \Y $and$ls180.v:7953$2544_Y - end - attribute \src "ls180.v:7953.7-7953.90" - cell $and $and$ls180.v:7953$2546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7953$2544_Y - connect \B $not$ls180.v:7953$2545_Y - connect \Y $and$ls180.v:7953$2546_Y - end - attribute \src "ls180.v:7959.8-7959.59" - cell $and $and$ls180.v:7959$2547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_uart_clk_txen - connect \B \main_uart_phy_tx_busy - connect \Y $and$ls180.v:7959$2547_Y - end - attribute \src "ls180.v:7983.8-7983.48" - cell $and $and$ls180.v:7983$2554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7983$2553_Y - connect \B \main_uart_phy_rx_r - connect \Y $and$ls180.v:7983$2554_Y - end - attribute \src "ls180.v:8016.7-8016.57" - cell $and $and$ls180.v:8016$2560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8016$2559_Y - connect \B \main_uart_tx_old_trigger - connect \Y $and$ls180.v:8016$2560_Y - end - attribute \src "ls180.v:8023.7-8023.57" - cell $and $and$ls180.v:8023$2562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8023$2561_Y - connect \B \main_uart_rx_old_trigger - connect \Y $and$ls180.v:8023$2562_Y - end - attribute \src "ls180.v:8033.8-8033.75" - cell $and $and$ls180.v:8033$2563 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_we - connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8033$2563_Y - end - attribute \src "ls180.v:8033.7-8033.107" - cell $and $and$ls180.v:8033$2565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8033$2563_Y - connect \B $not$ls180.v:8033$2564_Y - connect \Y $and$ls180.v:8033$2565_Y - end - attribute \src "ls180.v:8039.8-8039.75" - cell $and $and$ls180.v:8039$2568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_we - connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8039$2568_Y - end - attribute \src "ls180.v:8039.7-8039.107" - cell $and $and$ls180.v:8039$2570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8039$2568_Y - connect \B $not$ls180.v:8039$2569_Y - connect \Y $and$ls180.v:8039$2570_Y - end - attribute \src "ls180.v:8055.8-8055.75" - cell $and $and$ls180.v:8055$2574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_we - connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8055$2574_Y - end - attribute \src "ls180.v:8055.7-8055.107" - cell $and $and$ls180.v:8055$2576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8055$2574_Y - connect \B $not$ls180.v:8055$2575_Y - connect \Y $and$ls180.v:8055$2576_Y - end - attribute \src "ls180.v:8061.8-8061.75" - cell $and $and$ls180.v:8061$2579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_we - connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8061$2579_Y - end - attribute \src "ls180.v:8061.7-8061.107" - cell $and $and$ls180.v:8061$2581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8061$2579_Y - connect \B $not$ls180.v:8061$2580_Y - connect \Y $and$ls180.v:8061$2581_Y - end - attribute \src "ls180.v:8174.7-8174.96" - cell $and $and$ls180.v:8174$2604 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_source_valid - connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $and$ls180.v:8174$2604_Y - end - attribute \src "ls180.v:8175.8-8175.93" - cell $and $and$ls180.v:8175$2605 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid - connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8175$2605_Y - end - attribute \src "ls180.v:8183.8-8183.93" - cell $and $and$ls180.v:8183$2606 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid - connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8183$2606_Y - end - attribute \src "ls180.v:8255.7-8255.98" - cell $and $and$ls180.v:8255$2616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_source_valid - connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $and$ls180.v:8255$2616_Y - end - attribute \src "ls180.v:8256.8-8256.95" - cell $and $and$ls180.v:8256$2617 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_valid - connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8256$2617_Y - end - attribute \src "ls180.v:8264.8-8264.95" - cell $and $and$ls180.v:8264$2618 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_valid - connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8264$2618_Y - end - attribute \src "ls180.v:8334.7-8334.100" - cell $and $and$ls180.v:8334$2628 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_source_valid - connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $and$ls180.v:8334$2628_Y - end - attribute \src "ls180.v:8335.8-8335.97" - cell $and $and$ls180.v:8335$2629 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_valid - connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8335$2629_Y - end - attribute \src "ls180.v:8343.8-8343.97" - cell $and $and$ls180.v:8343$2630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_valid - connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8343$2630_Y - end - attribute \src "ls180.v:8434.7-8434.82" - cell $and $and$ls180.v:8434$2636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_ready - connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8434$2636_Y - end - attribute \src "ls180.v:8437.7-8437.82" - cell $and $and$ls180.v:8437$2637 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_ready - connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8437$2637_Y - end - attribute \src "ls180.v:8440.7-8440.82" - cell $and $and$ls180.v:8440$2638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_ready - connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8440$2638_Y - end - attribute \src "ls180.v:8443.7-8443.82" - cell $and $and$ls180.v:8443$2639 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_ready - connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8443$2639_Y - end - attribute \src "ls180.v:8446.7-8446.82" - cell $and $and$ls180.v:8446$2640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8446$2640_Y - end - attribute \src "ls180.v:8451.7-8451.82" - cell $and $and$ls180.v:8451$2641 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8451$2641_Y - end - attribute \src "ls180.v:8456.7-8456.82" - cell $and $and$ls180.v:8456$2642 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8456$2642_Y - end - attribute \src "ls180.v:8461.7-8461.82" - cell $and $and$ls180.v:8461$2643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8461$2643_Y - end - attribute \src "ls180.v:8466.7-8466.82" - cell $and $and$ls180.v:8466$2644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8466$2644_Y - end - attribute \src "ls180.v:8531.8-8531.83" - cell $and $and$ls180.v:8531$2647 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8531$2647_Y - end - attribute \src "ls180.v:8531.7-8531.119" - cell $and $and$ls180.v:8531$2649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8531$2647_Y - connect \B $not$ls180.v:8531$2648_Y - connect \Y $and$ls180.v:8531$2649_Y - end - attribute \src "ls180.v:8537.8-8537.83" - cell $and $and$ls180.v:8537$2652 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8537$2652_Y - end - attribute \src "ls180.v:8537.7-8537.119" - cell $and $and$ls180.v:8537$2654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8537$2652_Y - connect \B $not$ls180.v:8537$2653_Y - connect \Y $and$ls180.v:8537$2654_Y - end - attribute \src "ls180.v:8557.7-8557.88" - cell $and $and$ls180.v:8557$2661 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_source_valid - connect \B \main_sdblock2mem_converter_source_ready - connect \Y $and$ls180.v:8557$2661_Y - end - attribute \src "ls180.v:8558.8-8558.85" - cell $and $and$ls180.v:8558$2662 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_valid - connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8558$2662_Y - end - attribute \src "ls180.v:8566.8-8566.85" - cell $and $and$ls180.v:8566$2663 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_valid - connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8566$2663_Y - end - attribute \src "ls180.v:8610.7-8610.88" - cell $and $and$ls180.v:8610$2667 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_source_valid - connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:8610$2667_Y - end - attribute \src "ls180.v:8617.8-8617.83" - cell $and $and$ls180.v:8617$2669 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8617$2669_Y - end - attribute \src "ls180.v:8617.7-8617.119" - cell $and $and$ls180.v:8617$2671 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8617$2669_Y - connect \B $not$ls180.v:8617$2670_Y - connect \Y $and$ls180.v:8617$2671_Y - end - attribute \src "ls180.v:8623.8-8623.83" - cell $and $and$ls180.v:8623$2674 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8623$2674_Y - end - attribute \src "ls180.v:8623.7-8623.119" - cell $and $and$ls180.v:8623$2676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8623$2674_Y - connect \B $not$ls180.v:8623$2675_Y - connect \Y $and$ls180.v:8623$2676_Y - end - attribute \src "ls180.v:2794.42-2794.101" - cell $eq $eq$ls180.v:2794$18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface0_converted_interface_sel - connect \B 1'0 - connect \Y $eq$ls180.v:2794$18_Y - end - attribute \src "ls180.v:2801.11-2801.54" - cell $eq $eq$ls180.v:2801$23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_counter - connect \B 1'1 - connect \Y $eq$ls180.v:2801$23_Y - end - attribute \src "ls180.v:2854.42-2854.101" - cell $eq $eq$ls180.v:2854$29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface1_converted_interface_sel - connect \B 1'0 - connect \Y $eq$ls180.v:2854$29_Y - end - attribute \src "ls180.v:2861.11-2861.54" - cell $eq $eq$ls180.v:2861$34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_counter - connect \B 1'1 - connect \Y $eq$ls180.v:2861$34_Y - end - attribute \src "ls180.v:2914.42-2914.101" - cell $eq $eq$ls180.v:2914$40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface2_converted_interface_sel - connect \B 1'0 - connect \Y $eq$ls180.v:2914$40_Y - end - attribute \src "ls180.v:2921.11-2921.54" - cell $eq $eq$ls180.v:2921$45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter2_counter - connect \B 1'1 - connect \Y $eq$ls180.v:2921$45_Y - end - attribute \src "ls180.v:3107.34-3107.65" - cell $eq $eq$ls180.v:3107$73 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_count1 - connect \B 1'0 - connect \Y $eq$ls180.v:3107$73_Y - end - attribute \src "ls180.v:3111.68-3111.102" - cell $eq $eq$ls180.v:3111$76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'0 - connect \Y $eq$ls180.v:3111$76_Y - end - attribute \src "ls180.v:3155.43-3155.134" - cell $eq $eq$ls180.v:3155$81 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_row - connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3155$81_Y - end - attribute \src "ls180.v:3172.47-3172.88" - cell $eq $eq$ls180.v:3172$94 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3172$94_Y - end - attribute \src "ls180.v:3312.43-3312.134" - cell $eq $eq$ls180.v:3312$111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_row - connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3312$111_Y - end - attribute \src "ls180.v:3329.47-3329.88" - cell $eq $eq$ls180.v:3329$124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3329$124_Y - end - attribute \src "ls180.v:3469.43-3469.134" - cell $eq $eq$ls180.v:3469$141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_row - connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3469$141_Y - end - attribute \src "ls180.v:3486.47-3486.88" - cell $eq $eq$ls180.v:3486$154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3486$154_Y - end - attribute \src "ls180.v:3626.43-3626.134" - cell $eq $eq$ls180.v:3626$171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_row - connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3626$171_Y - end - attribute \src "ls180.v:3643.47-3643.88" - cell $eq $eq$ls180.v:3643$184 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3643$184_Y - end - attribute \src "ls180.v:3780.32-3780.56" - cell $eq $eq$ls180.v:3780$231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_time0 - connect \B 1'0 - connect \Y $eq$ls180.v:3780$231_Y - end - attribute \src "ls180.v:3781.32-3781.56" - cell $eq $eq$ls180.v:3781$232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_time1 - connect \B 1'0 - connect \Y $eq$ls180.v:3781$232_Y - end - attribute \src "ls180.v:3792.339-3792.418" - cell $eq $eq$ls180.v:3792$246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3792$246_Y - end - attribute \src "ls180.v:3792.423-3792.504" - cell $eq $eq$ls180.v:3792$247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3792$247_Y - end - attribute \src "ls180.v:3793.339-3793.418" - cell $eq $eq$ls180.v:3793$259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3793$259_Y - end - attribute \src "ls180.v:3793.423-3793.504" - cell $eq $eq$ls180.v:3793$260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3793$260_Y - end - attribute \src "ls180.v:3794.339-3794.418" - cell $eq $eq$ls180.v:3794$272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3794$272_Y - end - attribute \src "ls180.v:3794.423-3794.504" - cell $eq $eq$ls180.v:3794$273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3794$273_Y - end - attribute \src "ls180.v:3795.339-3795.418" - cell $eq $eq$ls180.v:3795$285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3795$285_Y - end - attribute \src "ls180.v:3795.423-3795.504" - cell $eq $eq$ls180.v:3795$286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3795$286_Y - end - attribute \src "ls180.v:3825.339-3825.418" - cell $eq $eq$ls180.v:3825$304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3825$304_Y - end - attribute \src "ls180.v:3825.423-3825.504" - cell $eq $eq$ls180.v:3825$305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3825$305_Y - end - attribute \src "ls180.v:3826.339-3826.418" - cell $eq $eq$ls180.v:3826$317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3826$317_Y - end - attribute \src "ls180.v:3826.423-3826.504" - cell $eq $eq$ls180.v:3826$318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3826$318_Y - end - attribute \src "ls180.v:3827.339-3827.418" - cell $eq $eq$ls180.v:3827$330 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3827$330_Y - end - attribute \src "ls180.v:3827.423-3827.504" - cell $eq $eq$ls180.v:3827$331 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3827$331_Y - end - attribute \src "ls180.v:3828.339-3828.418" - cell $eq $eq$ls180.v:3828$343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3828$343_Y - end - attribute \src "ls180.v:3828.423-3828.504" - cell $eq $eq$ls180.v:3828$344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3828$344_Y - end - attribute \src "ls180.v:3857.78-3857.113" - cell $eq $eq$ls180.v:3857$353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3857$353_Y - end - attribute \src "ls180.v:3860.78-3860.113" - cell $eq $eq$ls180.v:3860$356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3860$356_Y - end - attribute \src "ls180.v:3866.78-3866.113" - cell $eq $eq$ls180.v:3866$360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 1'1 - connect \Y $eq$ls180.v:3866$360_Y - end - attribute \src "ls180.v:3869.78-3869.113" - cell $eq $eq$ls180.v:3869$363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 1'1 - connect \Y $eq$ls180.v:3869$363_Y - end - attribute \src "ls180.v:3875.78-3875.113" - cell $eq $eq$ls180.v:3875$367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 2'10 - connect \Y $eq$ls180.v:3875$367_Y - end - attribute \src "ls180.v:3878.78-3878.113" - cell $eq $eq$ls180.v:3878$370 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 2'10 - connect \Y $eq$ls180.v:3878$370_Y - end - attribute \src "ls180.v:3884.78-3884.113" - cell $eq $eq$ls180.v:3884$374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 2'11 - connect \Y $eq$ls180.v:3884$374_Y - end - attribute \src "ls180.v:3887.78-3887.113" - cell $eq $eq$ls180.v:3887$377 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 2'11 - connect \Y $eq$ls180.v:3887$377_Y - end - attribute \src "ls180.v:3968.42-3968.82" - cell $eq $eq$ls180.v:3968$400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'0 - connect \Y $eq$ls180.v:3968$400_Y - end - attribute \src "ls180.v:3968.145-3968.178" - cell $eq $eq$ls180.v:3968$401 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3968$401_Y - end - attribute \src "ls180.v:3968.220-3968.253" - cell $eq $eq$ls180.v:3968$404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3968$404_Y - end - attribute \src "ls180.v:3968.295-3968.328" - cell $eq $eq$ls180.v:3968$407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3968$407_Y - end - attribute \src "ls180.v:3973.42-3973.82" - cell $eq $eq$ls180.v:3973$416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'1 - connect \Y $eq$ls180.v:3973$416_Y - end - attribute \src "ls180.v:3973.145-3973.178" - cell $eq $eq$ls180.v:3973$417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3973$417_Y - end - attribute \src "ls180.v:3973.220-3973.253" - cell $eq $eq$ls180.v:3973$420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3973$420_Y - end - attribute \src "ls180.v:3973.295-3973.328" - cell $eq $eq$ls180.v:3973$423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3973$423_Y - end - attribute \src "ls180.v:3978.42-3978.82" - cell $eq $eq$ls180.v:3978$432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'10 - connect \Y $eq$ls180.v:3978$432_Y - end - attribute \src "ls180.v:3978.145-3978.178" - cell $eq $eq$ls180.v:3978$433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3978$433_Y - end - attribute \src "ls180.v:3978.220-3978.253" - cell $eq $eq$ls180.v:3978$436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3978$436_Y - end - attribute \src "ls180.v:3978.295-3978.328" - cell $eq $eq$ls180.v:3978$439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3978$439_Y - end - attribute \src "ls180.v:3983.42-3983.82" - cell $eq $eq$ls180.v:3983$448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'11 - connect \Y $eq$ls180.v:3983$448_Y - end - attribute \src "ls180.v:3983.145-3983.178" - cell $eq $eq$ls180.v:3983$449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3983$449_Y - end - attribute \src "ls180.v:3983.220-3983.253" - cell $eq $eq$ls180.v:3983$452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3983$452_Y - end - attribute \src "ls180.v:3983.295-3983.328" - cell $eq $eq$ls180.v:3983$455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3983$455_Y - end - attribute \src "ls180.v:3988.44-3988.77" - cell $eq $eq$ls180.v:3988$464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3988$464_Y - end - attribute \src "ls180.v:3988.83-3988.123" - cell $eq $eq$ls180.v:3988$465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'0 - connect \Y $eq$ls180.v:3988$465_Y - end - attribute \src "ls180.v:3988.186-3988.219" - cell $eq $eq$ls180.v:3988$466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3988$466_Y - end - attribute \src "ls180.v:3988.261-3988.294" - cell $eq $eq$ls180.v:3988$469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3988$469_Y - end - attribute \src "ls180.v:3988.336-3988.369" - cell $eq $eq$ls180.v:3988$472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3988$472_Y - end - attribute \src "ls180.v:3988.418-3988.451" - cell $eq $eq$ls180.v:3988$480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3988$480_Y - end - attribute \src "ls180.v:3988.457-3988.497" - cell $eq $eq$ls180.v:3988$481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'1 - connect \Y $eq$ls180.v:3988$481_Y - end - attribute \src "ls180.v:3988.560-3988.593" - cell $eq $eq$ls180.v:3988$482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3988$482_Y - end - attribute \src "ls180.v:3988.635-3988.668" - cell $eq $eq$ls180.v:3988$485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3988$485_Y - end - attribute \src "ls180.v:3988.710-3988.743" - cell $eq $eq$ls180.v:3988$488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3988$488_Y - end - attribute \src "ls180.v:3988.792-3988.825" - cell $eq $eq$ls180.v:3988$496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3988$496_Y - end - attribute \src "ls180.v:3988.831-3988.871" - cell $eq $eq$ls180.v:3988$497 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'10 - connect \Y $eq$ls180.v:3988$497_Y - end - attribute \src "ls180.v:3988.934-3988.967" - cell $eq $eq$ls180.v:3988$498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3988$498_Y - end - attribute \src "ls180.v:3988.1009-3988.1042" - cell $eq $eq$ls180.v:3988$501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3988$501_Y - end - attribute \src "ls180.v:3988.1084-3988.1117" - cell $eq $eq$ls180.v:3988$504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3988$504_Y - end - attribute \src "ls180.v:3988.1166-3988.1199" - cell $eq $eq$ls180.v:3988$512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3988$512_Y - end - attribute \src "ls180.v:3988.1205-3988.1245" - cell $eq $eq$ls180.v:3988$513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'11 - connect \Y $eq$ls180.v:3988$513_Y - end - attribute \src "ls180.v:3988.1308-3988.1341" - cell $eq $eq$ls180.v:3988$514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3988$514_Y - end - attribute \src "ls180.v:3988.1383-3988.1416" - cell $eq $eq$ls180.v:3988$517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3988$517_Y - end - attribute \src "ls180.v:3988.1458-3988.1491" - cell $eq $eq$ls180.v:3988$520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3988$520_Y - end - attribute \src "ls180.v:4047.29-4047.57" - cell $eq $eq$ls180.v:4047$533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_sel - connect \B 1'0 - connect \Y $eq$ls180.v:4047$533_Y - end - attribute \src "ls180.v:4054.11-4054.41" - cell $eq $eq$ls180.v:4054$538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter_counter - connect \B 1'1 - connect \Y $eq$ls180.v:4054$538_Y - end - attribute \src "ls180.v:4211.36-4211.111" - cell $eq $eq$ls180.v:4211$603 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_spi_master_clk_divider1 - connect \B $sub$ls180.v:4211$602_Y - connect \Y $eq$ls180.v:4211$603_Y - end - attribute \src "ls180.v:4212.36-4212.105" - cell $eq $eq$ls180.v:4212$605 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_spi_master_clk_divider1 - connect \B $sub$ls180.v:4212$604_Y - connect \Y $eq$ls180.v:4212$605_Y - end - attribute \src "ls180.v:4239.10-4239.67" - cell $eq $eq$ls180.v:4239$609 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \main_spi_master_count - connect \B $sub$ls180.v:4239$608_Y - connect \Y $eq$ls180.v:4239$609_Y - end - attribute \src "ls180.v:4343.10-4343.40" - cell $eq $eq$ls180.v:4343$636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_count - connect \B 7'1001111 - connect \Y $eq$ls180.v:4343$636_Y - end - attribute \src "ls180.v:4400.10-4400.39" - cell $eq $eq$ls180.v:4400$639 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdw_count - connect \B 3'111 - connect \Y $eq$ls180.v:4400$639_Y - end - attribute \src "ls180.v:4417.10-4417.39" - cell $eq $eq$ls180.v:4417$641 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdw_count - connect \B 3'111 - connect \Y $eq$ls180.v:4417$641_Y - end - attribute \src "ls180.v:4445.38-4445.88" - cell $eq $eq$ls180.v:4445$643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - connect \B 1'0 - connect \Y $eq$ls180.v:4445$643_Y - end - attribute \src "ls180.v:4495.9-4495.40" - cell $eq $eq$ls180.v:4495$653 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:4495$653_Y - end - attribute \src "ls180.v:4504.36-4504.105" - cell $eq $eq$ls180.v:4504$655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_count - connect \B $sub$ls180.v:4504$654_Y - connect \Y $eq$ls180.v:4504$655_Y - end - attribute \src "ls180.v:4523.9-4523.40" - cell $eq $eq$ls180.v:4523$659 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:4523$659_Y - end - attribute \src "ls180.v:4535.10-4535.39" - cell $eq $eq$ls180.v:4535$661 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_count - connect \B 3'111 - connect \Y $eq$ls180.v:4535$661_Y - end - attribute \src "ls180.v:4572.39-4572.94" - cell $eq $eq$ls180.v:4572$665 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] - connect \B 1'0 - connect \Y $eq$ls180.v:4572$665_Y - end - attribute \src "ls180.v:4609.32-4609.89" - cell $eq $eq$ls180.v:4609$674 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 - connect \B 3'101 - connect \Y $eq$ls180.v:4609$674_Y - end - attribute \src "ls180.v:4657.10-4657.40" - cell $eq $eq$ls180.v:4657$678 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_count - connect \B 1'1 - connect \Y $eq$ls180.v:4657$678_Y - end - attribute \src "ls180.v:4706.40-4706.98" - cell $eq $eq$ls180.v:4706$680 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_pads_in_payload_data_i - connect \B 1'0 - connect \Y $eq$ls180.v:4706$680_Y - end - attribute \src "ls180.v:4757.9-4757.41" - cell $eq $eq$ls180.v:4757$690 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:4757$690_Y - end - attribute \src "ls180.v:4766.37-4766.123" - cell $eq $eq$ls180.v:4766$693 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_count - connect \B $sub$ls180.v:4766$692_Y - connect \Y $eq$ls180.v:4766$693_Y - end - attribute \src "ls180.v:4789.9-4789.41" - cell $eq $eq$ls180.v:4789$696 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:4789$696_Y - end - attribute \src "ls180.v:4799.10-4799.41" - cell $eq $eq$ls180.v:4799$698 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_count - connect \B 6'100111 - connect \Y $eq$ls180.v:4799$698_Y - end - attribute \src "ls180.v:4968.9-4968.47" - cell $eq $eq$ls180.v:4968$880 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:4968$880_Y - end - attribute \src "ls180.v:4998.10-4998.48" - cell $eq $eq$ls180.v:4998$881 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:4998$881_Y - end - attribute \src "ls180.v:5029.10-5029.78" - cell $eq $eq$ls180.v:5029$886 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_fifo0 - connect \B \main_sdcore_crc16_checker_crctmp0 - connect \Y $eq$ls180.v:5029$886_Y - end - attribute \src "ls180.v:5029.83-5029.151" - cell $eq $eq$ls180.v:5029$887 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_fifo1 - connect \B \main_sdcore_crc16_checker_crctmp1 - connect \Y $eq$ls180.v:5029$887_Y - end - attribute \src "ls180.v:5029.157-5029.225" - cell $eq $eq$ls180.v:5029$889 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_fifo2 - connect \B \main_sdcore_crc16_checker_crctmp2 - connect \Y $eq$ls180.v:5029$889_Y - end - attribute \src "ls180.v:5029.231-5029.299" - cell $eq $eq$ls180.v:5029$891 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_fifo3 - connect \B \main_sdcore_crc16_checker_crctmp3 - connect \Y $eq$ls180.v:5029$891_Y - end - attribute \src "ls180.v:5037.7-5037.44" - cell $eq $eq$ls180.v:5037$895 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5037$895_Y - end - attribute \src "ls180.v:5047.7-5047.44" - cell $eq $eq$ls180.v:5047$898 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5047$898_Y - end - attribute \src "ls180.v:5057.7-5057.44" - cell $eq $eq$ls180.v:5057$901 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5057$901_Y - end - attribute \src "ls180.v:5067.7-5067.44" - cell $eq $eq$ls180.v:5067$904 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5067$904_Y - end - attribute \src "ls180.v:5191.36-5191.64" - cell $eq $eq$ls180.v:5191$955 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_cmd_type - connect \B 1'0 - connect \Y $eq$ls180.v:5191$955_Y - end - attribute \src "ls180.v:5197.10-5197.39" - cell $eq $eq$ls180.v:5197$958 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_cmd_count - connect \B 3'101 - connect \Y $eq$ls180.v:5197$958_Y - end - attribute \src "ls180.v:5198.11-5198.39" - cell $eq $eq$ls180.v:5198$959 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_cmd_type - connect \B 1'0 - connect \Y $eq$ls180.v:5198$959_Y - end - attribute \src "ls180.v:5210.34-5210.63" - cell $eq $eq$ls180.v:5210$960 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_type - connect \B 1'0 - connect \Y $eq$ls180.v:5210$960_Y - end - attribute \src "ls180.v:5211.9-5211.37" - cell $eq $eq$ls180.v:5211$961 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_cmd_type - connect \B 2'10 - connect \Y $eq$ls180.v:5211$961_Y - end - attribute \src "ls180.v:5218.10-5218.55" - cell $eq $eq$ls180.v:5218$962 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_source_payload_status - connect \B 1'1 - connect \Y $eq$ls180.v:5218$962_Y - end - attribute \src "ls180.v:5224.12-5224.41" - cell $eq $eq$ls180.v:5224$963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_type - connect \B 2'10 - connect \Y $eq$ls180.v:5224$963_Y - end - attribute \src "ls180.v:5227.13-5227.42" - cell $eq $eq$ls180.v:5227$964 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_type - connect \B 1'1 - connect \Y $eq$ls180.v:5227$964_Y - end - attribute \src "ls180.v:5249.10-5249.76" - cell $eq $eq$ls180.v:5249$969 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5249$968_Y - connect \Y $eq$ls180.v:5249$969_Y - end - attribute \src "ls180.v:5264.35-5264.101" - cell $eq $eq$ls180.v:5264$972 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5264$971_Y - connect \Y $eq$ls180.v:5264$972_Y - end - attribute \src "ls180.v:5266.10-5266.56" - cell $eq $eq$ls180.v:5266$973 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_payload_status - connect \B 1'0 - connect \Y $eq$ls180.v:5266$973_Y - end - attribute \src "ls180.v:5275.12-5275.78" - cell $eq $eq$ls180.v:5275$977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5275$976_Y - connect \Y $eq$ls180.v:5275$977_Y - end - attribute \src "ls180.v:5282.11-5282.57" - cell $eq $eq$ls180.v:5282$978 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_payload_status - connect \B 1'1 - connect \Y $eq$ls180.v:5282$978_Y - end - attribute \src "ls180.v:5399.10-5399.105" - cell $eq $eq$ls180.v:5399$995 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_wishbonedmawriter_offset - connect \B $sub$ls180.v:5399$994_Y - connect \Y $eq$ls180.v:5399$995_Y - end - attribute \src "ls180.v:5489.39-5489.106" - cell $eq $eq$ls180.v:5489$1001 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_dma_offset - connect \B $sub$ls180.v:5489$1000_Y - connect \Y $eq$ls180.v:5489$1001_Y - end - attribute \src "ls180.v:5519.44-5519.82" - cell $eq $eq$ls180.v:5519$1004 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_mux - connect \B 1'0 - connect \Y $eq$ls180.v:5519$1004_Y - end - attribute \src "ls180.v:5520.43-5520.81" - cell $eq $eq$ls180.v:5520$1005 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_mux - connect \B 2'11 - connect \Y $eq$ls180.v:5520$1005_Y - end - attribute \src "ls180.v:5577.32-5577.99" - cell $eq $eq$ls180.v:5577$1018 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \libresocsim_clk_divider1 - connect \B $sub$ls180.v:5577$1017_Y - connect \Y $eq$ls180.v:5577$1018_Y - end - attribute \src "ls180.v:5578.32-5578.93" - cell $eq $eq$ls180.v:5578$1020 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \libresocsim_clk_divider1 - connect \B $sub$ls180.v:5578$1019_Y - connect \Y $eq$ls180.v:5578$1020_Y - end - attribute \src "ls180.v:5606.10-5606.59" - cell $eq $eq$ls180.v:5606$1024 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \libresocsim_count - connect \B $sub$ls180.v:5606$1023_Y - connect \Y $eq$ls180.v:5606$1024_Y - end - attribute \src "ls180.v:5679.85-5679.106" - cell $eq $eq$ls180.v:5679$1029 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'0 - connect \Y $eq$ls180.v:5679$1029_Y - end - attribute \src "ls180.v:5680.85-5680.106" - cell $eq $eq$ls180.v:5680$1031 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'1 - connect \Y $eq$ls180.v:5680$1031_Y - end - attribute \src "ls180.v:5681.85-5681.106" - cell $eq $eq$ls180.v:5681$1033 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'10 - connect \Y $eq$ls180.v:5681$1033_Y - end - attribute \src "ls180.v:5682.57-5682.78" - cell $eq $eq$ls180.v:5682$1035 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'11 - connect \Y $eq$ls180.v:5682$1035_Y - end - attribute \src "ls180.v:5683.57-5683.78" - cell $eq $eq$ls180.v:5683$1037 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 3'100 - connect \Y $eq$ls180.v:5683$1037_Y - end - attribute \src "ls180.v:5684.85-5684.106" - cell $eq $eq$ls180.v:5684$1039 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'0 - connect \Y $eq$ls180.v:5684$1039_Y - end - attribute \src "ls180.v:5685.85-5685.106" - cell $eq $eq$ls180.v:5685$1041 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'1 - connect \Y $eq$ls180.v:5685$1041_Y - end - attribute \src "ls180.v:5686.85-5686.106" - cell $eq $eq$ls180.v:5686$1043 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'10 - connect \Y $eq$ls180.v:5686$1043_Y - end - attribute \src "ls180.v:5687.57-5687.78" - cell $eq $eq$ls180.v:5687$1045 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'11 - connect \Y $eq$ls180.v:5687$1045_Y - end - attribute \src "ls180.v:5688.57-5688.78" - cell $eq $eq$ls180.v:5688$1047 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 3'100 - connect \Y $eq$ls180.v:5688$1047_Y - end - attribute \src "ls180.v:5692.27-5692.59" - cell $eq $eq$ls180.v:5692$1050 - parameter \A_SIGNED 0 - parameter \A_WIDTH 23 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:7] - connect \B 1'0 - connect \Y $eq$ls180.v:5692$1050_Y - end - attribute \src "ls180.v:5693.27-5693.68" - cell $eq $eq$ls180.v:5693$1051 - parameter \A_SIGNED 0 - parameter \A_WIDTH 27 - parameter \B_SIGNED 0 - parameter \B_WIDTH 27 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:3] - connect \B 27'110000000000000100000000000 - connect \Y $eq$ls180.v:5693$1051_Y - end - attribute \src "ls180.v:5694.27-5694.66" - cell $eq $eq$ls180.v:5694$1052 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \B_SIGNED 0 - parameter \B_WIDTH 20 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:10] - connect \B 20'11000000000000010001 - connect \Y $eq$ls180.v:5694$1052_Y - end - attribute \src "ls180.v:5695.27-5695.61" - cell $eq $eq$ls180.v:5695$1053 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:23] - connect \B 7'1001000 - connect \Y $eq$ls180.v:5695$1053_Y - end - attribute \src "ls180.v:5696.27-5696.65" - cell $eq $eq$ls180.v:5696$1054 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:14] - connect \B 16'1100000000000000 - connect \Y $eq$ls180.v:5696$1054_Y - end - attribute \src "ls180.v:5752.24-5752.45" - cell $eq $eq$ls180.v:5752$1081 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_count - connect \B 1'0 - connect \Y $eq$ls180.v:5752$1081_Y - end - attribute \src "ls180.v:5753.32-5753.77" - cell $eq $eq$ls180.v:5753$1082 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [13:9] - connect \B 1'0 - connect \Y $eq$ls180.v:5753$1082_Y - end - attribute \src "ls180.v:5755.97-5755.141" - cell $eq $eq$ls180.v:5755$1084 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5755$1084_Y - end - attribute \src "ls180.v:5756.100-5756.144" - cell $eq $eq$ls180.v:5756$1088 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5756$1088_Y - end - attribute \src "ls180.v:5758.99-5758.143" - cell $eq $eq$ls180.v:5758$1091 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5758$1091_Y - end - attribute \src "ls180.v:5759.102-5759.146" - cell $eq $eq$ls180.v:5759$1095 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5759$1095_Y - end - attribute \src "ls180.v:5761.99-5761.143" - cell $eq $eq$ls180.v:5761$1098 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5761$1098_Y - end - attribute \src "ls180.v:5762.102-5762.146" - cell $eq $eq$ls180.v:5762$1102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5762$1102_Y - end - attribute \src "ls180.v:5764.99-5764.143" - cell $eq $eq$ls180.v:5764$1105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5764$1105_Y - end - attribute \src "ls180.v:5765.102-5765.146" - cell $eq $eq$ls180.v:5765$1109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5765$1109_Y - end - attribute \src "ls180.v:5767.99-5767.143" - cell $eq $eq$ls180.v:5767$1112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5767$1112_Y - end - attribute \src "ls180.v:5768.102-5768.146" - cell $eq $eq$ls180.v:5768$1116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5768$1116_Y - end - attribute \src "ls180.v:5770.102-5770.146" - cell $eq $eq$ls180.v:5770$1119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5770$1119_Y - end - attribute \src "ls180.v:5771.105-5771.149" - cell $eq $eq$ls180.v:5771$1123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5771$1123_Y - end - attribute \src "ls180.v:5773.102-5773.146" - cell $eq $eq$ls180.v:5773$1126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5773$1126_Y - end - attribute \src "ls180.v:5774.105-5774.149" - cell $eq $eq$ls180.v:5774$1130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5774$1130_Y - end - attribute \src "ls180.v:5776.102-5776.146" - cell $eq $eq$ls180.v:5776$1133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5776$1133_Y - end - attribute \src "ls180.v:5777.105-5777.149" - cell $eq $eq$ls180.v:5777$1137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5777$1137_Y - end - attribute \src "ls180.v:5779.102-5779.146" - cell $eq $eq$ls180.v:5779$1140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5779$1140_Y - end - attribute \src "ls180.v:5780.105-5780.149" - cell $eq $eq$ls180.v:5780$1144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5780$1144_Y - end - attribute \src "ls180.v:5791.32-5791.77" - cell $eq $eq$ls180.v:5791$1146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [13:9] - connect \B 3'110 - connect \Y $eq$ls180.v:5791$1146_Y - end - attribute \src "ls180.v:5793.94-5793.138" - cell $eq $eq$ls180.v:5793$1148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5793$1148_Y - end - attribute \src "ls180.v:5794.97-5794.141" - cell $eq $eq$ls180.v:5794$1152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5794$1152_Y - end - attribute \src "ls180.v:5796.94-5796.138" - cell $eq $eq$ls180.v:5796$1155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5796$1155_Y - end - attribute \src "ls180.v:5797.97-5797.141" - cell $eq $eq$ls180.v:5797$1159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5797$1159_Y - end - attribute \src "ls180.v:5799.94-5799.138" - cell $eq $eq$ls180.v:5799$1162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5799$1162_Y - end - attribute \src "ls180.v:5800.97-5800.141" - cell $eq $eq$ls180.v:5800$1166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5800$1166_Y - end - attribute \src "ls180.v:5802.94-5802.138" - cell $eq $eq$ls180.v:5802$1169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5802$1169_Y - end - attribute \src "ls180.v:5803.97-5803.141" - cell $eq $eq$ls180.v:5803$1173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5803$1173_Y - end - attribute \src "ls180.v:5805.95-5805.139" - cell $eq $eq$ls180.v:5805$1176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5805$1176_Y - end - attribute \src "ls180.v:5806.98-5806.142" - cell $eq $eq$ls180.v:5806$1180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5806$1180_Y - end - attribute \src "ls180.v:5808.95-5808.139" - cell $eq $eq$ls180.v:5808$1183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5808$1183_Y - end - attribute \src "ls180.v:5809.98-5809.142" - cell $eq $eq$ls180.v:5809$1187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5809$1187_Y - end - attribute \src "ls180.v:5817.32-5817.78" - cell $eq $eq$ls180.v:5817$1189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [13:9] - connect \B 4'1010 - connect \Y $eq$ls180.v:5817$1189_Y - end - attribute \src "ls180.v:5819.93-5819.135" - cell $eq $eq$ls180.v:5819$1191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] - connect \B 1'0 - connect \Y $eq$ls180.v:5819$1191_Y - end - attribute \src "ls180.v:5820.96-5820.138" - cell $eq $eq$ls180.v:5820$1195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] - connect \B 1'0 - connect \Y $eq$ls180.v:5820$1195_Y - end - attribute \src "ls180.v:5822.92-5822.134" - cell $eq $eq$ls180.v:5822$1198 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] - connect \B 1'1 - connect \Y $eq$ls180.v:5822$1198_Y - end - attribute \src "ls180.v:5823.95-5823.137" - cell $eq $eq$ls180.v:5823$1202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] - connect \B 1'1 - connect \Y $eq$ls180.v:5823$1202_Y - end - attribute \src "ls180.v:5831.32-5831.77" - cell $eq $eq$ls180.v:5831$1204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [13:9] - connect \B 4'1000 - connect \Y $eq$ls180.v:5831$1204_Y - end - attribute \src "ls180.v:5833.98-5833.142" - cell $eq $eq$ls180.v:5833$1206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5833$1206_Y - end - attribute \src "ls180.v:5834.101-5834.145" - cell $eq $eq$ls180.v:5834$1210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5834$1210_Y - end - attribute \src "ls180.v:5836.97-5836.141" - cell $eq $eq$ls180.v:5836$1213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5836$1213_Y - end - attribute \src "ls180.v:5837.100-5837.144" - cell $eq $eq$ls180.v:5837$1217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5837$1217_Y - end - attribute \src "ls180.v:5839.97-5839.141" - cell $eq $eq$ls180.v:5839$1220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5839$1220_Y - end - attribute \src "ls180.v:5840.100-5840.144" - cell $eq $eq$ls180.v:5840$1224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5840$1224_Y - end - attribute \src "ls180.v:5842.97-5842.141" - cell $eq $eq$ls180.v:5842$1227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5842$1227_Y - end - attribute \src "ls180.v:5843.100-5843.144" - cell $eq $eq$ls180.v:5843$1231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5843$1231_Y - end - attribute \src "ls180.v:5845.97-5845.141" - cell $eq $eq$ls180.v:5845$1234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5845$1234_Y - end - attribute \src "ls180.v:5846.100-5846.144" - cell $eq $eq$ls180.v:5846$1238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5846$1238_Y - end - attribute \src "ls180.v:5848.98-5848.142" - cell $eq $eq$ls180.v:5848$1241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5848$1241_Y - end - attribute \src "ls180.v:5849.101-5849.145" - cell $eq $eq$ls180.v:5849$1245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5849$1245_Y - end - attribute \src "ls180.v:5851.98-5851.142" - cell $eq $eq$ls180.v:5851$1248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5851$1248_Y - end - attribute \src "ls180.v:5852.101-5852.145" - cell $eq $eq$ls180.v:5852$1252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5852$1252_Y - end - attribute \src "ls180.v:5854.98-5854.142" - cell $eq $eq$ls180.v:5854$1255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5854$1255_Y - end - attribute \src "ls180.v:5855.101-5855.145" - cell $eq $eq$ls180.v:5855$1259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5855$1259_Y - end - attribute \src "ls180.v:5857.98-5857.142" - cell $eq $eq$ls180.v:5857$1262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5857$1262_Y - end - attribute \src "ls180.v:5858.101-5858.145" - cell $eq $eq$ls180.v:5858$1266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5858$1266_Y - end - attribute \src "ls180.v:5868.32-5868.77" - cell $eq $eq$ls180.v:5868$1268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [13:9] - connect \B 4'1001 - connect \Y $eq$ls180.v:5868$1268_Y - end - attribute \src "ls180.v:5870.98-5870.142" - cell $eq $eq$ls180.v:5870$1270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5870$1270_Y - end - attribute \src "ls180.v:5871.101-5871.145" - cell $eq $eq$ls180.v:5871$1274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5871$1274_Y - end - attribute \src "ls180.v:5873.97-5873.141" - cell $eq $eq$ls180.v:5873$1277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5873$1277_Y - end - attribute \src "ls180.v:5874.100-5874.144" - cell $eq $eq$ls180.v:5874$1281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5874$1281_Y - end - attribute \src "ls180.v:5876.97-5876.141" - cell $eq $eq$ls180.v:5876$1284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5876$1284_Y - end - attribute \src "ls180.v:5877.100-5877.144" - cell $eq $eq$ls180.v:5877$1288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5877$1288_Y - end - attribute \src "ls180.v:5879.97-5879.141" - cell $eq $eq$ls180.v:5879$1291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5879$1291_Y - end - attribute \src "ls180.v:5880.100-5880.144" - cell $eq $eq$ls180.v:5880$1295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5880$1295_Y - end - attribute \src "ls180.v:5882.97-5882.141" - cell $eq $eq$ls180.v:5882$1298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5882$1298_Y - end - attribute \src "ls180.v:5883.100-5883.144" - cell $eq $eq$ls180.v:5883$1302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5883$1302_Y - end - attribute \src "ls180.v:5885.98-5885.142" - cell $eq $eq$ls180.v:5885$1305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5885$1305_Y - end - attribute \src "ls180.v:5886.101-5886.145" - cell $eq $eq$ls180.v:5886$1309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5886$1309_Y - end - attribute \src "ls180.v:5888.98-5888.142" - cell $eq $eq$ls180.v:5888$1312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5888$1312_Y - end - attribute \src "ls180.v:5889.101-5889.145" - cell $eq $eq$ls180.v:5889$1316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5889$1316_Y - end - attribute \src "ls180.v:5891.98-5891.142" - cell $eq $eq$ls180.v:5891$1319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5891$1319_Y - end - attribute \src "ls180.v:5892.101-5892.145" - cell $eq $eq$ls180.v:5892$1323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5892$1323_Y - end - attribute \src "ls180.v:5894.98-5894.142" - cell $eq $eq$ls180.v:5894$1326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5894$1326_Y - end - attribute \src "ls180.v:5895.101-5895.145" - cell $eq $eq$ls180.v:5895$1330 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5895$1330_Y - end - attribute \src "ls180.v:5905.32-5905.78" - cell $eq $eq$ls180.v:5905$1332 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [13:9] - connect \B 4'1101 - connect \Y $eq$ls180.v:5905$1332_Y - end - attribute \src "ls180.v:5907.100-5907.144" - cell $eq $eq$ls180.v:5907$1334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5907$1334_Y - end - attribute \src "ls180.v:5908.103-5908.147" - cell $eq $eq$ls180.v:5908$1338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5908$1338_Y - end - attribute \src "ls180.v:5910.100-5910.144" - cell $eq $eq$ls180.v:5910$1341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5910$1341_Y - end - attribute \src "ls180.v:5911.103-5911.147" - cell $eq $eq$ls180.v:5911$1345 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5911$1345_Y - end - attribute \src "ls180.v:5913.100-5913.144" - cell $eq $eq$ls180.v:5913$1348 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5913$1348_Y - end - attribute \src "ls180.v:5914.103-5914.147" - cell $eq $eq$ls180.v:5914$1352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5914$1352_Y - end - attribute \src "ls180.v:5916.100-5916.144" - cell $eq $eq$ls180.v:5916$1355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5916$1355_Y - end - attribute \src "ls180.v:5917.103-5917.147" - cell $eq $eq$ls180.v:5917$1359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5917$1359_Y - end - attribute \src "ls180.v:5919.100-5919.144" - cell $eq $eq$ls180.v:5919$1362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5919$1362_Y - end - attribute \src "ls180.v:5920.103-5920.147" - cell $eq $eq$ls180.v:5920$1366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5920$1366_Y - end - attribute \src "ls180.v:5922.100-5922.144" - cell $eq $eq$ls180.v:5922$1369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5922$1369_Y - end - attribute \src "ls180.v:5923.103-5923.147" - cell $eq $eq$ls180.v:5923$1373 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5923$1373_Y - end - attribute \src "ls180.v:5925.100-5925.144" - cell $eq $eq$ls180.v:5925$1376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5925$1376_Y - end - attribute \src "ls180.v:5926.103-5926.147" - cell $eq $eq$ls180.v:5926$1380 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5926$1380_Y - end - attribute \src "ls180.v:5928.100-5928.144" - cell $eq $eq$ls180.v:5928$1383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5928$1383_Y - end - attribute \src "ls180.v:5929.103-5929.147" - cell $eq $eq$ls180.v:5929$1387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5929$1387_Y - end - attribute \src "ls180.v:5931.102-5931.146" - cell $eq $eq$ls180.v:5931$1390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5931$1390_Y - end - attribute \src "ls180.v:5932.105-5932.149" - cell $eq $eq$ls180.v:5932$1394 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5932$1394_Y - end - attribute \src "ls180.v:5934.102-5934.146" - cell $eq $eq$ls180.v:5934$1397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:5934$1397_Y - end - attribute \src "ls180.v:5935.105-5935.149" - cell $eq $eq$ls180.v:5935$1401 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:5935$1401_Y - end - attribute \src "ls180.v:5937.102-5937.147" - cell $eq $eq$ls180.v:5937$1404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:5937$1404_Y - end - attribute \src "ls180.v:5938.105-5938.150" - cell $eq $eq$ls180.v:5938$1408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:5938$1408_Y - end - attribute \src "ls180.v:5940.102-5940.147" - cell $eq $eq$ls180.v:5940$1411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:5940$1411_Y - end - attribute \src "ls180.v:5941.105-5941.150" - cell $eq $eq$ls180.v:5941$1415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:5941$1415_Y - end - attribute \src "ls180.v:5943.102-5943.147" - cell $eq $eq$ls180.v:5943$1418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:5943$1418_Y - end - attribute \src "ls180.v:5944.105-5944.150" - cell $eq $eq$ls180.v:5944$1422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:5944$1422_Y - end - attribute \src "ls180.v:5946.99-5946.144" - cell $eq $eq$ls180.v:5946$1425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:5946$1425_Y - end - attribute \src "ls180.v:5947.102-5947.147" - cell $eq $eq$ls180.v:5947$1429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:5947$1429_Y - end - attribute \src "ls180.v:5949.100-5949.145" - cell $eq $eq$ls180.v:5949$1432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:5949$1432_Y - end - attribute \src "ls180.v:5950.103-5950.148" - cell $eq $eq$ls180.v:5950$1436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:5950$1436_Y - end - attribute \src "ls180.v:5967.32-5967.78" - cell $eq $eq$ls180.v:5967$1438 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [13:9] - connect \B 4'1100 - connect \Y $eq$ls180.v:5967$1438_Y - end - attribute \src "ls180.v:5969.104-5969.148" - cell $eq $eq$ls180.v:5969$1440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5969$1440_Y - end - attribute \src "ls180.v:5970.107-5970.151" - cell $eq $eq$ls180.v:5970$1444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5970$1444_Y - end - attribute \src "ls180.v:5972.104-5972.148" - cell $eq $eq$ls180.v:5972$1447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5972$1447_Y - end - attribute \src "ls180.v:5973.107-5973.151" - cell $eq $eq$ls180.v:5973$1451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5973$1451_Y - end - attribute \src "ls180.v:5975.104-5975.148" - cell $eq $eq$ls180.v:5975$1454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5975$1454_Y - end - attribute \src "ls180.v:5976.107-5976.151" - cell $eq $eq$ls180.v:5976$1458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5976$1458_Y - end - attribute \src "ls180.v:5978.104-5978.148" - cell $eq $eq$ls180.v:5978$1461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5978$1461_Y - end - attribute \src "ls180.v:5979.107-5979.151" - cell $eq $eq$ls180.v:5979$1465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5979$1465_Y - end - attribute \src "ls180.v:5981.103-5981.147" - cell $eq $eq$ls180.v:5981$1468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5981$1468_Y - end - attribute \src "ls180.v:5982.106-5982.150" - cell $eq $eq$ls180.v:5982$1472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5982$1472_Y - end - attribute \src "ls180.v:5984.103-5984.147" - cell $eq $eq$ls180.v:5984$1475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5984$1475_Y - end - attribute \src "ls180.v:5985.106-5985.150" - cell $eq $eq$ls180.v:5985$1479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5985$1479_Y - end - attribute \src "ls180.v:5987.103-5987.147" - cell $eq $eq$ls180.v:5987$1482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5987$1482_Y - end - attribute \src "ls180.v:5988.106-5988.150" - cell $eq $eq$ls180.v:5988$1486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5988$1486_Y - end - attribute \src "ls180.v:5990.103-5990.147" - cell $eq $eq$ls180.v:5990$1489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5990$1489_Y - end - attribute \src "ls180.v:5991.106-5991.150" - cell $eq $eq$ls180.v:5991$1493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5991$1493_Y - end - attribute \src "ls180.v:5993.94-5993.138" - cell $eq $eq$ls180.v:5993$1496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5993$1496_Y - end - attribute \src "ls180.v:5994.97-5994.141" - cell $eq $eq$ls180.v:5994$1500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5994$1500_Y - end - attribute \src "ls180.v:5996.105-5996.149" - cell $eq $eq$ls180.v:5996$1503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:5996$1503_Y - end - attribute \src "ls180.v:5997.108-5997.152" - cell $eq $eq$ls180.v:5997$1507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:5997$1507_Y - end - attribute \src "ls180.v:5999.105-5999.150" - cell $eq $eq$ls180.v:5999$1510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:5999$1510_Y - end - attribute \src "ls180.v:6000.108-6000.153" - cell $eq $eq$ls180.v:6000$1514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6000$1514_Y - end - attribute \src "ls180.v:6002.105-6002.150" - cell $eq $eq$ls180.v:6002$1517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6002$1517_Y - end - attribute \src "ls180.v:6003.108-6003.153" - cell $eq $eq$ls180.v:6003$1521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6003$1521_Y - end - attribute \src "ls180.v:6005.105-6005.150" - cell $eq $eq$ls180.v:6005$1524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6005$1524_Y - end - attribute \src "ls180.v:6006.108-6006.153" - cell $eq $eq$ls180.v:6006$1528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6006$1528_Y - end - attribute \src "ls180.v:6008.105-6008.150" - cell $eq $eq$ls180.v:6008$1531 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6008$1531_Y - end - attribute \src "ls180.v:6009.108-6009.153" - cell $eq $eq$ls180.v:6009$1535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6009$1535_Y - end - attribute \src "ls180.v:6011.105-6011.150" - cell $eq $eq$ls180.v:6011$1538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6011$1538_Y - end - attribute \src "ls180.v:6012.108-6012.153" - cell $eq $eq$ls180.v:6012$1542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6012$1542_Y - end - attribute \src "ls180.v:6014.104-6014.149" - cell $eq $eq$ls180.v:6014$1545 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6014$1545_Y - end - attribute \src "ls180.v:6015.107-6015.152" - cell $eq $eq$ls180.v:6015$1549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6015$1549_Y - end - attribute \src "ls180.v:6017.104-6017.149" - cell $eq $eq$ls180.v:6017$1552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6017$1552_Y - end - attribute \src "ls180.v:6018.107-6018.152" - cell $eq $eq$ls180.v:6018$1556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6018$1556_Y - end - attribute \src "ls180.v:6020.104-6020.149" - cell $eq $eq$ls180.v:6020$1559 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:6020$1559_Y - end - attribute \src "ls180.v:6021.107-6021.152" - cell $eq $eq$ls180.v:6021$1563 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:6021$1563_Y - end - attribute \src "ls180.v:6023.104-6023.149" - cell $eq $eq$ls180.v:6023$1566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:6023$1566_Y - end - attribute \src "ls180.v:6024.107-6024.152" - cell $eq $eq$ls180.v:6024$1570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:6024$1570_Y - end - attribute \src "ls180.v:6026.104-6026.149" - cell $eq $eq$ls180.v:6026$1573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10011 - connect \Y $eq$ls180.v:6026$1573_Y - end - attribute \src "ls180.v:6027.107-6027.152" - cell $eq $eq$ls180.v:6027$1577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10011 - connect \Y $eq$ls180.v:6027$1577_Y - end - attribute \src "ls180.v:6029.104-6029.149" - cell $eq $eq$ls180.v:6029$1580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10100 - connect \Y $eq$ls180.v:6029$1580_Y - end - attribute \src "ls180.v:6030.107-6030.152" - cell $eq $eq$ls180.v:6030$1584 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10100 - connect \Y $eq$ls180.v:6030$1584_Y - end - attribute \src "ls180.v:6032.104-6032.149" - cell $eq $eq$ls180.v:6032$1587 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10101 - connect \Y $eq$ls180.v:6032$1587_Y - end - attribute \src "ls180.v:6033.107-6033.152" - cell $eq $eq$ls180.v:6033$1591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10101 - connect \Y $eq$ls180.v:6033$1591_Y - end - attribute \src "ls180.v:6035.104-6035.149" - cell $eq $eq$ls180.v:6035$1594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10110 - connect \Y $eq$ls180.v:6035$1594_Y - end - attribute \src "ls180.v:6036.107-6036.152" - cell $eq $eq$ls180.v:6036$1598 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10110 - connect \Y $eq$ls180.v:6036$1598_Y - end - attribute \src "ls180.v:6038.104-6038.149" - cell $eq $eq$ls180.v:6038$1601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10111 - connect \Y $eq$ls180.v:6038$1601_Y - end - attribute \src "ls180.v:6039.107-6039.152" - cell $eq $eq$ls180.v:6039$1605 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10111 - connect \Y $eq$ls180.v:6039$1605_Y - end - attribute \src "ls180.v:6041.104-6041.149" - cell $eq $eq$ls180.v:6041$1608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11000 - connect \Y $eq$ls180.v:6041$1608_Y - end - attribute \src "ls180.v:6042.107-6042.152" - cell $eq $eq$ls180.v:6042$1612 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11000 - connect \Y $eq$ls180.v:6042$1612_Y - end - attribute \src "ls180.v:6044.100-6044.145" - cell $eq $eq$ls180.v:6044$1615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11001 - connect \Y $eq$ls180.v:6044$1615_Y - end - attribute \src "ls180.v:6045.103-6045.148" - cell $eq $eq$ls180.v:6045$1619 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11001 - connect \Y $eq$ls180.v:6045$1619_Y - end - attribute \src "ls180.v:6047.101-6047.146" - cell $eq $eq$ls180.v:6047$1622 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11010 - connect \Y $eq$ls180.v:6047$1622_Y - end - attribute \src "ls180.v:6048.104-6048.149" - cell $eq $eq$ls180.v:6048$1626 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11010 - connect \Y $eq$ls180.v:6048$1626_Y - end - attribute \src "ls180.v:6050.104-6050.149" - cell $eq $eq$ls180.v:6050$1629 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11011 - connect \Y $eq$ls180.v:6050$1629_Y - end - attribute \src "ls180.v:6051.107-6051.152" - cell $eq $eq$ls180.v:6051$1633 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11011 - connect \Y $eq$ls180.v:6051$1633_Y - end - attribute \src "ls180.v:6053.104-6053.149" - cell $eq $eq$ls180.v:6053$1636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11100 - connect \Y $eq$ls180.v:6053$1636_Y - end - attribute \src "ls180.v:6054.107-6054.152" - cell $eq $eq$ls180.v:6054$1640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11100 - connect \Y $eq$ls180.v:6054$1640_Y - end - attribute \src "ls180.v:6056.103-6056.148" - cell $eq $eq$ls180.v:6056$1643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11101 - connect \Y $eq$ls180.v:6056$1643_Y - end - attribute \src "ls180.v:6057.106-6057.151" - cell $eq $eq$ls180.v:6057$1647 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11101 - connect \Y $eq$ls180.v:6057$1647_Y - end - attribute \src "ls180.v:6059.103-6059.148" - cell $eq $eq$ls180.v:6059$1650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11110 - connect \Y $eq$ls180.v:6059$1650_Y - end - attribute \src "ls180.v:6060.106-6060.151" - cell $eq $eq$ls180.v:6060$1654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11110 - connect \Y $eq$ls180.v:6060$1654_Y - end - attribute \src "ls180.v:6062.103-6062.148" - cell $eq $eq$ls180.v:6062$1657 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11111 - connect \Y $eq$ls180.v:6062$1657_Y - end - attribute \src "ls180.v:6063.106-6063.151" - cell $eq $eq$ls180.v:6063$1661 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11111 - connect \Y $eq$ls180.v:6063$1661_Y - end - attribute \src "ls180.v:6065.103-6065.148" - cell $eq $eq$ls180.v:6065$1664 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 6'100000 - connect \Y $eq$ls180.v:6065$1664_Y - end - attribute \src "ls180.v:6066.106-6066.151" - cell $eq $eq$ls180.v:6066$1668 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 6'100000 - connect \Y $eq$ls180.v:6066$1668_Y - end - attribute \src "ls180.v:6102.32-6102.78" - cell $eq $eq$ls180.v:6102$1670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [13:9] - connect \B 4'1110 - connect \Y $eq$ls180.v:6102$1670_Y - end - attribute \src "ls180.v:6104.100-6104.144" - cell $eq $eq$ls180.v:6104$1672 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6104$1672_Y - end - attribute \src "ls180.v:6105.103-6105.147" - cell $eq $eq$ls180.v:6105$1676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6105$1676_Y - end - attribute \src "ls180.v:6107.100-6107.144" - cell $eq $eq$ls180.v:6107$1679 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6107$1679_Y - end - attribute \src "ls180.v:6108.103-6108.147" - cell $eq $eq$ls180.v:6108$1683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6108$1683_Y - end - attribute \src "ls180.v:6110.100-6110.144" - cell $eq $eq$ls180.v:6110$1686 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6110$1686_Y - end - attribute \src "ls180.v:6111.103-6111.147" - cell $eq $eq$ls180.v:6111$1690 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6111$1690_Y - end - attribute \src "ls180.v:6113.100-6113.144" - cell $eq $eq$ls180.v:6113$1693 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6113$1693_Y - end - attribute \src "ls180.v:6114.103-6114.147" - cell $eq $eq$ls180.v:6114$1697 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6114$1697_Y - end - attribute \src "ls180.v:6116.100-6116.144" - cell $eq $eq$ls180.v:6116$1700 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6116$1700_Y - end - attribute \src "ls180.v:6117.103-6117.147" - cell $eq $eq$ls180.v:6117$1704 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6117$1704_Y - end - attribute \src "ls180.v:6119.100-6119.144" - cell $eq $eq$ls180.v:6119$1707 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6119$1707_Y - end - attribute \src "ls180.v:6120.103-6120.147" - cell $eq $eq$ls180.v:6120$1711 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6120$1711_Y - end - attribute \src "ls180.v:6122.100-6122.144" - cell $eq $eq$ls180.v:6122$1714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6122$1714_Y - end - attribute \src "ls180.v:6123.103-6123.147" - cell $eq $eq$ls180.v:6123$1718 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6123$1718_Y - end - attribute \src "ls180.v:6125.100-6125.144" - cell $eq $eq$ls180.v:6125$1721 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6125$1721_Y - end - attribute \src "ls180.v:6126.103-6126.147" - cell $eq $eq$ls180.v:6126$1725 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6126$1725_Y - end - attribute \src "ls180.v:6128.102-6128.146" - cell $eq $eq$ls180.v:6128$1728 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6128$1728_Y - end - attribute \src "ls180.v:6129.105-6129.149" - cell $eq $eq$ls180.v:6129$1732 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6129$1732_Y - end - attribute \src "ls180.v:6131.102-6131.146" - cell $eq $eq$ls180.v:6131$1735 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6131$1735_Y - end - attribute \src "ls180.v:6132.105-6132.149" - cell $eq $eq$ls180.v:6132$1739 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6132$1739_Y - end - attribute \src "ls180.v:6134.102-6134.147" - cell $eq $eq$ls180.v:6134$1742 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6134$1742_Y - end - attribute \src "ls180.v:6135.105-6135.150" - cell $eq $eq$ls180.v:6135$1746 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6135$1746_Y - end - attribute \src "ls180.v:6137.102-6137.147" - cell $eq $eq$ls180.v:6137$1749 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6137$1749_Y - end - attribute \src "ls180.v:6138.105-6138.150" - cell $eq $eq$ls180.v:6138$1753 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6138$1753_Y - end - attribute \src "ls180.v:6140.102-6140.147" - cell $eq $eq$ls180.v:6140$1756 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6140$1756_Y - end - attribute \src "ls180.v:6141.105-6141.150" - cell $eq $eq$ls180.v:6141$1760 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6141$1760_Y - end - attribute \src "ls180.v:6143.99-6143.144" - cell $eq $eq$ls180.v:6143$1763 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6143$1763_Y - end - attribute \src "ls180.v:6144.102-6144.147" - cell $eq $eq$ls180.v:6144$1767 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6144$1767_Y - end - attribute \src "ls180.v:6146.100-6146.145" - cell $eq $eq$ls180.v:6146$1770 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6146$1770_Y - end - attribute \src "ls180.v:6147.103-6147.148" - cell $eq $eq$ls180.v:6147$1774 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6147$1774_Y - end - attribute \src "ls180.v:6149.102-6149.147" - cell $eq $eq$ls180.v:6149$1777 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6149$1777_Y - end - attribute \src "ls180.v:6150.105-6150.150" - cell $eq $eq$ls180.v:6150$1781 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6150$1781_Y - end - attribute \src "ls180.v:6152.102-6152.147" - cell $eq $eq$ls180.v:6152$1784 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6152$1784_Y - end - attribute \src "ls180.v:6153.105-6153.150" - cell $eq $eq$ls180.v:6153$1788 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6153$1788_Y - end - attribute \src "ls180.v:6155.102-6155.147" - cell $eq $eq$ls180.v:6155$1791 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:6155$1791_Y - end - attribute \src "ls180.v:6156.105-6156.150" - cell $eq $eq$ls180.v:6156$1795 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:6156$1795_Y - end - attribute \src "ls180.v:6158.102-6158.147" - cell $eq $eq$ls180.v:6158$1798 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:6158$1798_Y - end - attribute \src "ls180.v:6159.105-6159.150" - cell $eq $eq$ls180.v:6159$1802 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:6159$1802_Y - end - attribute \src "ls180.v:6181.32-6181.78" - cell $eq $eq$ls180.v:6181$1804 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [13:9] - connect \B 4'1011 - connect \Y $eq$ls180.v:6181$1804_Y - end - attribute \src "ls180.v:6183.102-6183.146" - cell $eq $eq$ls180.v:6183$1806 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6183$1806_Y - end - attribute \src "ls180.v:6184.105-6184.149" - cell $eq $eq$ls180.v:6184$1810 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6184$1810_Y - end - attribute \src "ls180.v:6186.107-6186.151" - cell $eq $eq$ls180.v:6186$1813 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6186$1813_Y - end - attribute \src "ls180.v:6187.110-6187.154" - cell $eq $eq$ls180.v:6187$1817 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6187$1817_Y - end - attribute \src "ls180.v:6189.107-6189.151" - cell $eq $eq$ls180.v:6189$1820 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6189$1820_Y - end - attribute \src "ls180.v:6190.110-6190.154" - cell $eq $eq$ls180.v:6190$1824 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6190$1824_Y - end - attribute \src "ls180.v:6192.100-6192.144" - cell $eq $eq$ls180.v:6192$1827 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6192$1827_Y - end - attribute \src "ls180.v:6193.103-6193.147" - cell $eq $eq$ls180.v:6193$1831 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6193$1831_Y - end - attribute \src "ls180.v:6198.32-6198.77" - cell $eq $eq$ls180.v:6198$1833 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [13:9] - connect \B 2'11 - connect \Y $eq$ls180.v:6198$1833_Y - end - attribute \src "ls180.v:6200.104-6200.148" - cell $eq $eq$ls180.v:6200$1835 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6200$1835_Y - end - attribute \src "ls180.v:6201.107-6201.151" - cell $eq $eq$ls180.v:6201$1839 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6201$1839_Y - end - attribute \src "ls180.v:6203.108-6203.152" - cell $eq $eq$ls180.v:6203$1842 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6203$1842_Y - end - attribute \src "ls180.v:6204.111-6204.155" - cell $eq $eq$ls180.v:6204$1846 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6204$1846_Y - end - attribute \src "ls180.v:6206.98-6206.142" - cell $eq $eq$ls180.v:6206$1849 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6206$1849_Y - end - attribute \src "ls180.v:6207.101-6207.145" - cell $eq $eq$ls180.v:6207$1853 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6207$1853_Y - end - attribute \src "ls180.v:6209.108-6209.152" - cell $eq $eq$ls180.v:6209$1856 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6209$1856_Y - end - attribute \src "ls180.v:6210.111-6210.155" - cell $eq $eq$ls180.v:6210$1860 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6210$1860_Y - end - attribute \src "ls180.v:6212.108-6212.152" - cell $eq $eq$ls180.v:6212$1863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6212$1863_Y - end - attribute \src "ls180.v:6213.111-6213.155" - cell $eq $eq$ls180.v:6213$1867 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6213$1867_Y - end - attribute \src "ls180.v:6215.109-6215.153" - cell $eq $eq$ls180.v:6215$1870 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6215$1870_Y - end - attribute \src "ls180.v:6216.112-6216.156" - cell $eq $eq$ls180.v:6216$1874 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6216$1874_Y - end - attribute \src "ls180.v:6218.107-6218.151" - cell $eq $eq$ls180.v:6218$1877 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6218$1877_Y - end - attribute \src "ls180.v:6219.110-6219.154" - cell $eq $eq$ls180.v:6219$1881 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6219$1881_Y - end - attribute \src "ls180.v:6221.107-6221.151" - cell $eq $eq$ls180.v:6221$1884 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6221$1884_Y - end - attribute \src "ls180.v:6222.110-6222.154" - cell $eq $eq$ls180.v:6222$1888 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6222$1888_Y - end - attribute \src "ls180.v:6224.107-6224.151" - cell $eq $eq$ls180.v:6224$1891 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6224$1891_Y - end - attribute \src "ls180.v:6225.110-6225.154" - cell $eq $eq$ls180.v:6225$1895 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6225$1895_Y - end - attribute \src "ls180.v:6227.107-6227.151" - cell $eq $eq$ls180.v:6227$1898 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6227$1898_Y - end - attribute \src "ls180.v:6228.110-6228.154" - cell $eq $eq$ls180.v:6228$1902 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6228$1902_Y - end - attribute \src "ls180.v:6243.33-6243.79" - cell $eq $eq$ls180.v:6243$1904 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [13:9] - connect \B 3'111 - connect \Y $eq$ls180.v:6243$1904_Y - end - attribute \src "ls180.v:6245.102-6245.147" - cell $eq $eq$ls180.v:6245$1906 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6245$1906_Y - end - attribute \src "ls180.v:6246.105-6246.150" - cell $eq $eq$ls180.v:6246$1910 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6246$1910_Y - end - attribute \src "ls180.v:6248.102-6248.147" - cell $eq $eq$ls180.v:6248$1913 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6248$1913_Y - end - attribute \src "ls180.v:6249.105-6249.150" - cell $eq $eq$ls180.v:6249$1917 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6249$1917_Y - end - attribute \src "ls180.v:6251.100-6251.145" - cell $eq $eq$ls180.v:6251$1920 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6251$1920_Y - end - attribute \src "ls180.v:6252.103-6252.148" - cell $eq $eq$ls180.v:6252$1924 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6252$1924_Y - end - attribute \src "ls180.v:6254.99-6254.144" - cell $eq $eq$ls180.v:6254$1927 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6254$1927_Y - end - attribute \src "ls180.v:6255.102-6255.147" - cell $eq $eq$ls180.v:6255$1931 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6255$1931_Y - end - attribute \src "ls180.v:6257.98-6257.143" - cell $eq $eq$ls180.v:6257$1934 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6257$1934_Y - end - attribute \src "ls180.v:6258.101-6258.146" - cell $eq $eq$ls180.v:6258$1938 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6258$1938_Y - end - attribute \src "ls180.v:6260.97-6260.142" - cell $eq $eq$ls180.v:6260$1941 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6260$1941_Y - end - attribute \src "ls180.v:6261.100-6261.145" - cell $eq $eq$ls180.v:6261$1945 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6261$1945_Y - end - attribute \src "ls180.v:6263.103-6263.148" - cell $eq $eq$ls180.v:6263$1948 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6263$1948_Y - end - attribute \src "ls180.v:6264.106-6264.151" - cell $eq $eq$ls180.v:6264$1952 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6264$1952_Y - end - attribute \src "ls180.v:6283.33-6283.80" - cell $eq $eq$ls180.v:6283$1955 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [13:9] - connect \B 4'1111 - connect \Y $eq$ls180.v:6283$1955_Y - end - attribute \src "ls180.v:6285.102-6285.147" - cell $eq $eq$ls180.v:6285$1957 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6285$1957_Y - end - attribute \src "ls180.v:6286.105-6286.150" - cell $eq $eq$ls180.v:6286$1961 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6286$1961_Y - end - attribute \src "ls180.v:6288.102-6288.147" - cell $eq $eq$ls180.v:6288$1964 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6288$1964_Y - end - attribute \src "ls180.v:6289.105-6289.150" - cell $eq $eq$ls180.v:6289$1968 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6289$1968_Y - end - attribute \src "ls180.v:6291.100-6291.145" - cell $eq $eq$ls180.v:6291$1971 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6291$1971_Y - end - attribute \src "ls180.v:6292.103-6292.148" - cell $eq $eq$ls180.v:6292$1975 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6292$1975_Y - end - attribute \src "ls180.v:6294.99-6294.144" - cell $eq $eq$ls180.v:6294$1978 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6294$1978_Y - end - attribute \src "ls180.v:6295.102-6295.147" - cell $eq $eq$ls180.v:6295$1982 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6295$1982_Y - end - attribute \src "ls180.v:6297.98-6297.143" - cell $eq $eq$ls180.v:6297$1985 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6297$1985_Y - end - attribute \src "ls180.v:6298.101-6298.146" - cell $eq $eq$ls180.v:6298$1989 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6298$1989_Y - end - attribute \src "ls180.v:6300.97-6300.142" - cell $eq $eq$ls180.v:6300$1992 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6300$1992_Y - end - attribute \src "ls180.v:6301.100-6301.145" - cell $eq $eq$ls180.v:6301$1996 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6301$1996_Y - end - attribute \src "ls180.v:6303.103-6303.148" - cell $eq $eq$ls180.v:6303$1999 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6303$1999_Y - end - attribute \src "ls180.v:6304.106-6304.151" - cell $eq $eq$ls180.v:6304$2003 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6304$2003_Y - end - attribute \src "ls180.v:6306.106-6306.151" - cell $eq $eq$ls180.v:6306$2006 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6306$2006_Y - end - attribute \src "ls180.v:6307.109-6307.154" - cell $eq $eq$ls180.v:6307$2010 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6307$2010_Y - end - attribute \src "ls180.v:6309.106-6309.151" - cell $eq $eq$ls180.v:6309$2013 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6309$2013_Y - end - attribute \src "ls180.v:6310.109-6310.154" - cell $eq $eq$ls180.v:6310$2017 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6310$2017_Y - end - attribute \src "ls180.v:6331.33-6331.79" - cell $eq $eq$ls180.v:6331$2020 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [13:9] - connect \B 2'10 - connect \Y $eq$ls180.v:6331$2020_Y - end - attribute \src "ls180.v:6333.99-6333.144" - cell $eq $eq$ls180.v:6333$2022 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6333$2022_Y - end - attribute \src "ls180.v:6334.102-6334.147" - cell $eq $eq$ls180.v:6334$2026 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6334$2026_Y - end - attribute \src "ls180.v:6336.99-6336.144" - cell $eq $eq$ls180.v:6336$2029 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6336$2029_Y - end - attribute \src "ls180.v:6337.102-6337.147" - cell $eq $eq$ls180.v:6337$2033 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6337$2033_Y - end - attribute \src "ls180.v:6339.99-6339.144" - cell $eq $eq$ls180.v:6339$2036 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6339$2036_Y - end - attribute \src "ls180.v:6340.102-6340.147" - cell $eq $eq$ls180.v:6340$2040 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6340$2040_Y - end - attribute \src "ls180.v:6342.99-6342.144" - cell $eq $eq$ls180.v:6342$2043 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6342$2043_Y - end - attribute \src "ls180.v:6343.102-6343.147" - cell $eq $eq$ls180.v:6343$2047 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6343$2047_Y - end - attribute \src "ls180.v:6345.101-6345.146" - cell $eq $eq$ls180.v:6345$2050 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6345$2050_Y - end - attribute \src "ls180.v:6346.104-6346.149" - cell $eq $eq$ls180.v:6346$2054 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6346$2054_Y - end - attribute \src "ls180.v:6348.101-6348.146" - cell $eq $eq$ls180.v:6348$2057 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6348$2057_Y - end - attribute \src "ls180.v:6349.104-6349.149" - cell $eq $eq$ls180.v:6349$2061 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6349$2061_Y - end - attribute \src "ls180.v:6351.101-6351.146" - cell $eq $eq$ls180.v:6351$2064 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6351$2064_Y - end - attribute \src "ls180.v:6352.104-6352.149" - cell $eq $eq$ls180.v:6352$2068 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6352$2068_Y - end - attribute \src "ls180.v:6354.101-6354.146" - cell $eq $eq$ls180.v:6354$2071 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6354$2071_Y - end - attribute \src "ls180.v:6355.104-6355.149" - cell $eq $eq$ls180.v:6355$2075 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6355$2075_Y - end - attribute \src "ls180.v:6357.97-6357.142" - cell $eq $eq$ls180.v:6357$2078 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6357$2078_Y - end - attribute \src "ls180.v:6358.100-6358.145" - cell $eq $eq$ls180.v:6358$2082 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6358$2082_Y - end - attribute \src "ls180.v:6360.107-6360.152" - cell $eq $eq$ls180.v:6360$2085 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6360$2085_Y - end - attribute \src "ls180.v:6361.110-6361.155" - cell $eq $eq$ls180.v:6361$2089 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6361$2089_Y - end - attribute \src "ls180.v:6363.100-6363.146" - cell $eq $eq$ls180.v:6363$2092 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6363$2092_Y - end - attribute \src "ls180.v:6364.103-6364.149" - cell $eq $eq$ls180.v:6364$2096 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6364$2096_Y - end - attribute \src "ls180.v:6366.100-6366.146" - cell $eq $eq$ls180.v:6366$2099 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6366$2099_Y - end - attribute \src "ls180.v:6367.103-6367.149" - cell $eq $eq$ls180.v:6367$2103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6367$2103_Y - end - attribute \src "ls180.v:6369.100-6369.146" - cell $eq $eq$ls180.v:6369$2106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6369$2106_Y - end - attribute \src "ls180.v:6370.103-6370.149" - cell $eq $eq$ls180.v:6370$2110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6370$2110_Y - end - attribute \src "ls180.v:6372.100-6372.146" - cell $eq $eq$ls180.v:6372$2113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6372$2113_Y - end - attribute \src "ls180.v:6373.103-6373.149" - cell $eq $eq$ls180.v:6373$2117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6373$2117_Y - end - attribute \src "ls180.v:6375.112-6375.158" - cell $eq $eq$ls180.v:6375$2120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6375$2120_Y - end - attribute \src "ls180.v:6376.115-6376.161" - cell $eq $eq$ls180.v:6376$2124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6376$2124_Y - end - attribute \src "ls180.v:6378.113-6378.159" - cell $eq $eq$ls180.v:6378$2127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6378$2127_Y - end - attribute \src "ls180.v:6379.116-6379.162" - cell $eq $eq$ls180.v:6379$2131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6379$2131_Y - end - attribute \src "ls180.v:6381.104-6381.150" - cell $eq $eq$ls180.v:6381$2134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6381$2134_Y - end - attribute \src "ls180.v:6382.107-6382.153" - cell $eq $eq$ls180.v:6382$2138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6382$2138_Y - end - attribute \src "ls180.v:6399.33-6399.79" - cell $eq $eq$ls180.v:6399$2140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [13:9] - connect \B 3'101 - connect \Y $eq$ls180.v:6399$2140_Y - end - attribute \src "ls180.v:6401.90-6401.135" - cell $eq $eq$ls180.v:6401$2142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6401$2142_Y - end - attribute \src "ls180.v:6402.93-6402.138" - cell $eq $eq$ls180.v:6402$2146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6402$2146_Y - end - attribute \src "ls180.v:6404.100-6404.145" - cell $eq $eq$ls180.v:6404$2149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6404$2149_Y - end - attribute \src "ls180.v:6405.103-6405.148" - cell $eq $eq$ls180.v:6405$2153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6405$2153_Y - end - attribute \src "ls180.v:6407.101-6407.146" - cell $eq $eq$ls180.v:6407$2156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6407$2156_Y - end - attribute \src "ls180.v:6408.104-6408.149" - cell $eq $eq$ls180.v:6408$2160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6408$2160_Y - end - attribute \src "ls180.v:6410.105-6410.150" - cell $eq $eq$ls180.v:6410$2163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6410$2163_Y - end - attribute \src "ls180.v:6411.108-6411.153" - cell $eq $eq$ls180.v:6411$2167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6411$2167_Y - end - attribute \src "ls180.v:6413.106-6413.151" - cell $eq $eq$ls180.v:6413$2170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6413$2170_Y - end - attribute \src "ls180.v:6414.109-6414.154" - cell $eq $eq$ls180.v:6414$2174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6414$2174_Y - end - attribute \src "ls180.v:6416.104-6416.149" - cell $eq $eq$ls180.v:6416$2177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6416$2177_Y - end - attribute \src "ls180.v:6417.107-6417.152" - cell $eq $eq$ls180.v:6417$2181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6417$2181_Y - end - attribute \src "ls180.v:6419.101-6419.146" - cell $eq $eq$ls180.v:6419$2184 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6419$2184_Y - end - attribute \src "ls180.v:6420.104-6420.149" - cell $eq $eq$ls180.v:6420$2188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6420$2188_Y - end - attribute \src "ls180.v:6422.100-6422.145" - cell $eq $eq$ls180.v:6422$2191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6422$2191_Y - end - attribute \src "ls180.v:6423.103-6423.148" - cell $eq $eq$ls180.v:6423$2195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6423$2195_Y - end - attribute \src "ls180.v:6433.33-6433.79" - cell $eq $eq$ls180.v:6433$2197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [13:9] - connect \B 3'100 - connect \Y $eq$ls180.v:6433$2197_Y - end - attribute \src "ls180.v:6435.106-6435.151" - cell $eq $eq$ls180.v:6435$2199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6435$2199_Y - end - attribute \src "ls180.v:6436.109-6436.154" - cell $eq $eq$ls180.v:6436$2203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6436$2203_Y - end - attribute \src "ls180.v:6438.106-6438.151" - cell $eq $eq$ls180.v:6438$2206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6438$2206_Y - end - attribute \src "ls180.v:6439.109-6439.154" - cell $eq $eq$ls180.v:6439$2210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6439$2210_Y - end - attribute \src "ls180.v:6441.106-6441.151" - cell $eq $eq$ls180.v:6441$2213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6441$2213_Y - end - attribute \src "ls180.v:6442.109-6442.154" - cell $eq $eq$ls180.v:6442$2217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6442$2217_Y - end - attribute \src "ls180.v:6444.106-6444.151" - cell $eq $eq$ls180.v:6444$2220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6444$2220_Y - end - attribute \src "ls180.v:6445.109-6445.154" - cell $eq $eq$ls180.v:6445$2224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6445$2224_Y - end - attribute \src "ls180.v:6826.41-6826.81" - cell $eq $eq$ls180.v:6826$2261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'0 - connect \Y $eq$ls180.v:6826$2261_Y - end - attribute \src "ls180.v:6826.144-6826.177" - cell $eq $eq$ls180.v:6826$2262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6826$2262_Y - end - attribute \src "ls180.v:6826.219-6826.252" - cell $eq $eq$ls180.v:6826$2265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6826$2265_Y - end - attribute \src "ls180.v:6826.294-6826.327" - cell $eq $eq$ls180.v:6826$2268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6826$2268_Y - end - attribute \src "ls180.v:6850.41-6850.81" - cell $eq $eq$ls180.v:6850$2277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'1 - connect \Y $eq$ls180.v:6850$2277_Y - end - attribute \src "ls180.v:6850.144-6850.177" - cell $eq $eq$ls180.v:6850$2278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6850$2278_Y - end - attribute \src "ls180.v:6850.219-6850.252" - cell $eq $eq$ls180.v:6850$2281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6850$2281_Y - end - attribute \src "ls180.v:6850.294-6850.327" - cell $eq $eq$ls180.v:6850$2284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6850$2284_Y - end - attribute \src "ls180.v:6874.41-6874.81" - cell $eq $eq$ls180.v:6874$2293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'10 - connect \Y $eq$ls180.v:6874$2293_Y - end - attribute \src "ls180.v:6874.144-6874.177" - cell $eq $eq$ls180.v:6874$2294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6874$2294_Y - end - attribute \src "ls180.v:6874.219-6874.252" - cell $eq $eq$ls180.v:6874$2297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6874$2297_Y - end - attribute \src "ls180.v:6874.294-6874.327" - cell $eq $eq$ls180.v:6874$2300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6874$2300_Y - end - attribute \src "ls180.v:6898.41-6898.81" - cell $eq $eq$ls180.v:6898$2309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'11 - connect \Y $eq$ls180.v:6898$2309_Y - end - attribute \src "ls180.v:6898.144-6898.177" - cell $eq $eq$ls180.v:6898$2310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6898$2310_Y - end - attribute \src "ls180.v:6898.219-6898.252" - cell $eq $eq$ls180.v:6898$2313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6898$2313_Y - end - attribute \src "ls180.v:6898.294-6898.327" - cell $eq $eq$ls180.v:6898$2316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6898$2316_Y - end - attribute \src "ls180.v:7491.8-7491.38" - cell $eq $eq$ls180.v:7491$2419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_value - connect \B 1'0 - connect \Y $eq$ls180.v:7491$2419_Y - end - attribute \src "ls180.v:7522.8-7522.42" - cell $eq $eq$ls180.v:7522$2427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_postponer_count - connect \B 1'0 - connect \Y $eq$ls180.v:7522$2427_Y - end - attribute \src "ls180.v:7542.38-7542.74" - cell $eq $eq$ls180.v:7542$2430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 1'0 - connect \Y $eq$ls180.v:7542$2430_Y - end - attribute \src "ls180.v:7549.7-7549.43" - cell $eq $eq$ls180.v:7549$2432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 2'10 - connect \Y $eq$ls180.v:7549$2432_Y - end - attribute \src "ls180.v:7556.7-7556.43" - cell $eq $eq$ls180.v:7556$2433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 4'1000 - connect \Y $eq$ls180.v:7556$2433_Y - end - attribute \src "ls180.v:7564.7-7564.43" - cell $eq $eq$ls180.v:7564$2434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 4'1000 - connect \Y $eq$ls180.v:7564$2434_Y - end - attribute \src "ls180.v:7616.9-7616.54" - cell $eq $eq$ls180.v:7616$2452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7616$2452_Y - end - attribute \src "ls180.v:7662.9-7662.54" - cell $eq $eq$ls180.v:7662$2468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7662$2468_Y - end - attribute \src "ls180.v:7708.9-7708.54" - cell $eq $eq$ls180.v:7708$2484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7708$2484_Y - end - attribute \src "ls180.v:7754.9-7754.54" - cell $eq $eq$ls180.v:7754$2500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7754$2500_Y - end - attribute \src "ls180.v:7904.9-7904.41" - cell $eq $eq$ls180.v:7904$2512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_tccdcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7904$2512_Y - end - attribute \src "ls180.v:7919.9-7919.41" - cell $eq $eq$ls180.v:7919$2515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_twtrcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7919$2515_Y - end - attribute \src "ls180.v:7925.49-7925.82" - cell $eq $eq$ls180.v:7925$2516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7925$2516_Y - end - attribute \src "ls180.v:7925.131-7925.164" - cell $eq $eq$ls180.v:7925$2519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7925$2519_Y - end - attribute \src "ls180.v:7925.213-7925.246" - cell $eq $eq$ls180.v:7925$2522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7925$2522_Y - end - attribute \src "ls180.v:7925.295-7925.328" - cell $eq $eq$ls180.v:7925$2525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7925$2525_Y - end - attribute \src "ls180.v:7926.50-7926.83" - cell $eq $eq$ls180.v:7926$2528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7926$2528_Y - end - attribute \src "ls180.v:7926.132-7926.165" - cell $eq $eq$ls180.v:7926$2531 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7926$2531_Y - end - attribute \src "ls180.v:7926.214-7926.247" - cell $eq $eq$ls180.v:7926$2534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7926$2534_Y - end - attribute \src "ls180.v:7926.296-7926.329" - cell $eq $eq$ls180.v:7926$2537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7926$2537_Y - end - attribute \src "ls180.v:7961.9-7961.42" - cell $eq $eq$ls180.v:7961$2549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_tx_bitcount - connect \B 4'1000 - connect \Y $eq$ls180.v:7961$2549_Y - end - attribute \src "ls180.v:7964.10-7964.43" - cell $eq $eq$ls180.v:7964$2550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_tx_bitcount - connect \B 4'1001 - connect \Y $eq$ls180.v:7964$2550_Y - end - attribute \src "ls180.v:7990.9-7990.42" - cell $eq $eq$ls180.v:7990$2556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_rx_bitcount - connect \B 1'0 - connect \Y $eq$ls180.v:7990$2556_Y - end - attribute \src "ls180.v:7995.10-7995.43" - cell $eq $eq$ls180.v:7995$2557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_rx_bitcount - connect \B 4'1001 - connect \Y $eq$ls180.v:7995$2557_Y - end - attribute \src "ls180.v:8167.9-8167.53" - cell $eq $eq$ls180.v:8167$2601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_demux - connect \B 3'111 - connect \Y $eq$ls180.v:8167$2601_Y - end - attribute \src "ls180.v:8248.9-8248.54" - cell $eq $eq$ls180.v:8248$2613 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_demux - connect \B 3'111 - connect \Y $eq$ls180.v:8248$2613_Y - end - attribute \src "ls180.v:8327.9-8327.55" - cell $eq $eq$ls180.v:8327$2625 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_demux - connect \B 1'1 - connect \Y $eq$ls180.v:8327$2625_Y - end - attribute \src "ls180.v:8550.9-8550.49" - cell $eq $eq$ls180.v:8550$2658 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_demux - connect \B 2'11 - connect \Y $eq$ls180.v:8550$2658_Y - end - attribute \src "ls180.v:8126.8-8126.54" - cell $ge $ge$ls180.v:8126$2593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_pwm0_counter - connect \B $sub$ls180.v:8126$2592_Y - connect \Y $ge$ls180.v:8126$2593_Y - end - attribute \src "ls180.v:8140.8-8140.54" - cell $ge $ge$ls180.v:8140$2597 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_pwm1_counter - connect \B $sub$ls180.v:8140$2596_Y - connect \Y $ge$ls180.v:8140$2597_Y - end - attribute \src "ls180.v:5076.47-5076.83" - cell $gt $gt$ls180.v:5076$906 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $gt$ls180.v:5076$906_Y - end - attribute \src "ls180.v:5082.7-5082.43" - cell $lt $lt$ls180.v:5082$909 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 4'1000 - connect \Y $lt$ls180.v:5082$909_Y - end - attribute \src "ls180.v:8121.8-8121.43" - cell $lt $lt$ls180.v:8121$2591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_pwm0_counter - connect \B \main_pwm0_width - connect \Y $lt$ls180.v:8121$2591_Y - end - attribute \src "ls180.v:8135.8-8135.43" - cell $lt $lt$ls180.v:8135$2595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_pwm1_counter - connect \B \main_pwm1_width - connect \Y $lt$ls180.v:8135$2595_Y - end - attribute \src "ls180.v:10052.33-10052.36" - cell $memrd $memrd$\mem$ls180.v:10052$2705 - parameter \ABITS 7 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \TRANSPARENT 0 - parameter \WIDTH 32 - connect \ADDR \memadr - connect \CLK 1'x - connect \DATA $memrd$\mem$ls180.v:10052$2705_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10063.12-10063.19" - cell $memrd $memrd$\storage$ls180.v:10063$2710 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10063$2710_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10070.68-10070.75" - cell $memrd $memrd$\storage$ls180.v:10070$2712 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10070$2712_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10077.14-10077.23" - cell $memrd $memrd$\storage_1$ls180.v:10077$2717 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_1" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10077$2717_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10084.68-10084.77" - cell $memrd $memrd$\storage_1$ls180.v:10084$2719 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_1" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10084$2719_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10091.14-10091.23" - cell $memrd $memrd$\storage_2$ls180.v:10091$2724 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_2" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10091$2724_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10098.68-10098.77" - cell $memrd $memrd$\storage_2$ls180.v:10098$2726 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_2" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10098$2726_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10105.14-10105.23" - cell $memrd $memrd$\storage_3$ls180.v:10105$2731 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_3" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10105$2731_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10112.68-10112.77" - cell $memrd $memrd$\storage_3$ls180.v:10112$2733 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_3" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10112$2733_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10120.14-10120.23" - cell $memrd $memrd$\storage_4$ls180.v:10120$2738 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_4" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_uart_tx_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10120$2738_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10125.15-10125.24" - cell $memrd $memrd$\storage_4$ls180.v:10125$2740 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_4" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_uart_tx_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10125$2740_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10137.14-10137.23" - cell $memrd $memrd$\storage_5$ls180.v:10137$2745 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_5" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_uart_rx_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10137$2745_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10142.15-10142.24" - cell $memrd $memrd$\storage_5$ls180.v:10142$2747 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_5" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_uart_rx_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10142$2747_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10153.14-10153.23" - cell $memrd $memrd$\storage_6$ls180.v:10153$2752 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_6" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_sdblock2mem_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10153$2752_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10160.45-10160.54" - cell $memrd $memrd$\storage_6$ls180.v:10160$2754 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_6" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_sdblock2mem_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10160$2754_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10167.14-10167.23" - cell $memrd $memrd$\storage_7$ls180.v:10167$2759 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_7" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_sdmem2block_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10167$2759_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10174.45-10174.54" - cell $memrd $memrd$\storage_7$ls180.v:10174$2761 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_7" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_sdmem2block_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10174$2761_DATA - connect \EN 1'x - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2763 - parameter \ABITS 7 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 2763 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:10042$1_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10042$1_DATA - connect \EN $memwr$\mem$ls180.v:10042$1_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2764 - parameter \ABITS 7 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 2764 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:10044$2_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10044$2_DATA - connect \EN $memwr$\mem$ls180.v:10044$2_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2765 - parameter \ABITS 7 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 2765 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:10046$3_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10046$3_DATA - connect \EN $memwr$\mem$ls180.v:10046$3_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2766 - parameter \ABITS 7 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 2766 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:10048$4_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10048$4_DATA - connect \EN $memwr$\mem$ls180.v:10048$4_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage$ls180.v:0$2767 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage" - parameter \PRIORITY 2767 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage$ls180.v:10062$5_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage$ls180.v:10062$5_DATA - connect \EN $memwr$\storage$ls180.v:10062$5_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_1$ls180.v:0$2768 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_1" - parameter \PRIORITY 2768 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage_1$ls180.v:10076$6_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_1$ls180.v:10076$6_DATA - connect \EN $memwr$\storage_1$ls180.v:10076$6_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_2$ls180.v:0$2769 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_2" - parameter \PRIORITY 2769 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage_2$ls180.v:10090$7_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_2$ls180.v:10090$7_DATA - connect \EN $memwr$\storage_2$ls180.v:10090$7_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_3$ls180.v:0$2770 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_3" - parameter \PRIORITY 2770 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage_3$ls180.v:10104$8_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_3$ls180.v:10104$8_DATA - connect \EN $memwr$\storage_3$ls180.v:10104$8_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_4$ls180.v:0$2771 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_4" - parameter \PRIORITY 2771 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_4$ls180.v:10119$9_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_4$ls180.v:10119$9_DATA - connect \EN $memwr$\storage_4$ls180.v:10119$9_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_5$ls180.v:0$2772 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_5" - parameter \PRIORITY 2772 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_5$ls180.v:10136$10_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_5$ls180.v:10136$10_DATA - connect \EN $memwr$\storage_5$ls180.v:10136$10_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_6$ls180.v:0$2773 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_6" - parameter \PRIORITY 2773 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_6$ls180.v:10152$11_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_6$ls180.v:10152$11_DATA - connect \EN $memwr$\storage_6$ls180.v:10152$11_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_7$ls180.v:0$2774 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_7" - parameter \PRIORITY 2774 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_7$ls180.v:10166$12_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_7$ls180.v:10166$12_DATA - connect \EN $memwr$\storage_7$ls180.v:10166$12_EN - end - attribute \src "ls180.v:2949.41-2949.71" - cell $ne $ne$ls180.v:2949$60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_value - connect \B 1'0 - connect \Y $ne$ls180.v:2949$60_Y - end - attribute \src "ls180.v:3110.70-3110.104" - cell $ne $ne$ls180.v:3110$74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'0 - connect \Y $ne$ls180.v:3110$74_Y - end - attribute \src "ls180.v:3171.8-3171.142" - cell $ne $ne$ls180.v:3171$93 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3171$93_Y - end - attribute \src "ls180.v:3203.75-3203.133" - cell $ne $ne$ls180.v:3203$100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3203$100_Y - end - attribute \src "ls180.v:3204.75-3204.133" - cell $ne $ne$ls180.v:3204$101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3204$101_Y - end - attribute \src "ls180.v:3328.8-3328.142" - cell $ne $ne$ls180.v:3328$123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3328$123_Y - end - attribute \src "ls180.v:3360.75-3360.133" - cell $ne $ne$ls180.v:3360$130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3360$130_Y - end - attribute \src "ls180.v:3361.75-3361.133" - cell $ne $ne$ls180.v:3361$131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3361$131_Y - end - attribute \src "ls180.v:3485.8-3485.142" - cell $ne $ne$ls180.v:3485$153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3485$153_Y - end - attribute \src "ls180.v:3517.75-3517.133" - cell $ne $ne$ls180.v:3517$160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3517$160_Y - end - attribute \src "ls180.v:3518.75-3518.133" - cell $ne $ne$ls180.v:3518$161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3518$161_Y - end - attribute \src "ls180.v:3642.8-3642.142" - cell $ne $ne$ls180.v:3642$183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3642$183_Y - end - attribute \src "ls180.v:3674.75-3674.133" - cell $ne $ne$ls180.v:3674$190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3674$190_Y - end - attribute \src "ls180.v:3675.75-3675.133" - cell $ne $ne$ls180.v:3675$191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3675$191_Y - end - attribute \src "ls180.v:4167.47-4167.80" - cell $ne $ne$ls180.v:4167$589 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_level0 - connect \B 5'10000 - connect \Y $ne$ls180.v:4167$589_Y - end - attribute \src "ls180.v:4168.47-4168.79" - cell $ne $ne$ls180.v:4168$590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_level0 - connect \B 1'0 - connect \Y $ne$ls180.v:4168$590_Y - end - attribute \src "ls180.v:4197.47-4197.80" - cell $ne $ne$ls180.v:4197$600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_level0 - connect \B 5'10000 - connect \Y $ne$ls180.v:4197$600_Y - end - attribute \src "ls180.v:4198.47-4198.79" - cell $ne $ne$ls180.v:4198$601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_level0 - connect \B 1'0 - connect \Y $ne$ls180.v:4198$601_Y - end - attribute \src "ls180.v:4608.32-4608.89" - cell $ne $ne$ls180.v:4608$673 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 - connect \B 3'101 - connect \Y $ne$ls180.v:4608$673_Y - end - attribute \src "ls180.v:5255.10-5255.56" - cell $ne $ne$ls180.v:5255$970 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_payload_status - connect \B 2'10 - connect \Y $ne$ls180.v:5255$970_Y - end - attribute \src "ls180.v:5360.51-5360.87" - cell $ne $ne$ls180.v:5360$984 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_level - connect \B 6'100000 - connect \Y $ne$ls180.v:5360$984_Y - end - attribute \src "ls180.v:5361.51-5361.86" - cell $ne $ne$ls180.v:5361$985 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_level - connect \B 1'0 - connect \Y $ne$ls180.v:5361$985_Y - end - attribute \src "ls180.v:5568.51-5568.87" - cell $ne $ne$ls180.v:5568$1015 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_level - connect \B 6'100000 - connect \Y $ne$ls180.v:5568$1015_Y - end - attribute \src "ls180.v:5569.51-5569.86" - cell $ne $ne$ls180.v:5569$1016 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_level - connect \B 1'0 - connect \Y $ne$ls180.v:5569$1016_Y - end - attribute \src "ls180.v:5659.79-5659.119" - cell $ne $ne$ls180.v:5659$1027 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_libresocsim_wishbone_sel - connect \B 1'0 - connect \Y $ne$ls180.v:5659$1027_Y - end - attribute \src "ls180.v:7481.7-7481.52" - cell $ne $ne$ls180.v:7481$2414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_bus_errors - connect \B 32'11111111111111111111111111111111 - connect \Y $ne$ls180.v:7481$2414_Y - end - attribute \src "ls180.v:7531.9-7531.43" - cell $ne $ne$ls180.v:7531$2428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'0 - connect \Y $ne$ls180.v:7531$2428_Y - end - attribute \src "ls180.v:7567.8-7567.44" - cell $ne $ne$ls180.v:7567$2435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 1'0 - connect \Y $ne$ls180.v:7567$2435_Y - end - attribute \src "ls180.v:8470.9-8470.47" - cell $ne $ne$ls180.v:8470$2645 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 4'1010 - connect \Y $ne$ls180.v:8470$2645_Y - end - attribute \src "ls180.v:2757.45-2757.80" - cell $not $not$ls180.v:2757$14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_ibus_cyc - connect \Y $not$ls180.v:2757$14_Y - end - attribute \src "ls180.v:2796.61-2796.94" - cell $not $not$ls180.v:2796$19 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_skip - connect \Y $not$ls180.v:2796$19_Y - end - attribute \src "ls180.v:2797.61-2797.94" - cell $not $not$ls180.v:2797$20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_skip - connect \Y $not$ls180.v:2797$20_Y - end - attribute \src "ls180.v:2817.45-2817.80" - cell $not $not$ls180.v:2817$25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_dbus_cyc - connect \Y $not$ls180.v:2817$25_Y - end - attribute \src "ls180.v:2856.61-2856.94" - cell $not $not$ls180.v:2856$30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_skip - connect \Y $not$ls180.v:2856$30_Y - end - attribute \src "ls180.v:2857.61-2857.94" - cell $not $not$ls180.v:2857$31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_skip - connect \Y $not$ls180.v:2857$31_Y - end - attribute \src "ls180.v:2877.45-2877.83" - cell $not $not$ls180.v:2877$36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_jtag_wb_cyc - connect \Y $not$ls180.v:2877$36_Y - end - attribute \src "ls180.v:2916.61-2916.94" - cell $not $not$ls180.v:2916$41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter2_skip - connect \Y $not$ls180.v:2916$41_Y - end - attribute \src "ls180.v:2917.61-2917.94" - cell $not $not$ls180.v:2917$42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter2_skip - connect \Y $not$ls180.v:2917$42_Y - end - attribute \src "ls180.v:3059.34-3059.64" - cell $not $not$ls180.v:3059$66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [0] - connect \Y $not$ls180.v:3059$66_Y - end - attribute \src "ls180.v:3060.31-3060.61" - cell $not $not$ls180.v:3060$67 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [1] - connect \Y $not$ls180.v:3060$67_Y - end - attribute \src "ls180.v:3061.32-3061.62" - cell $not $not$ls180.v:3061$68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [2] - connect \Y $not$ls180.v:3061$68_Y - end - attribute \src "ls180.v:3062.32-3062.62" - cell $not $not$ls180.v:3062$69 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [3] - connect \Y $not$ls180.v:3062$69_Y - end - attribute \src "ls180.v:3104.33-3104.56" - cell $not $not$ls180.v:3104$72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:3104$72_Y - end - attribute \src "ls180.v:3205.58-3205.106" - cell $not $not$ls180.v:3205$102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:3205$102_Y - end - attribute \src "ls180.v:3259.9-3259.45" - cell $not $not$ls180.v:3259$107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_refresh_req - connect \Y $not$ls180.v:3259$107_Y - end - attribute \src "ls180.v:3362.58-3362.106" - cell $not $not$ls180.v:3362$132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:3362$132_Y - end - attribute \src "ls180.v:3416.9-3416.45" - cell $not $not$ls180.v:3416$137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_refresh_req - connect \Y $not$ls180.v:3416$137_Y - end - attribute \src "ls180.v:3519.58-3519.106" - cell $not $not$ls180.v:3519$162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:3519$162_Y - end - attribute \src "ls180.v:3573.9-3573.45" - cell $not $not$ls180.v:3573$167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_refresh_req - connect \Y $not$ls180.v:3573$167_Y - end - attribute \src "ls180.v:3676.58-3676.106" - cell $not $not$ls180.v:3676$192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:3676$192_Y - end - attribute \src "ls180.v:3730.9-3730.45" - cell $not $not$ls180.v:3730$197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_refresh_req - connect \Y $not$ls180.v:3730$197_Y - end - attribute \src "ls180.v:3772.149-3772.187" - cell $not $not$ls180.v:3772$200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3772$200_Y - end - attribute \src "ls180.v:3772.193-3772.230" - cell $not $not$ls180.v:3772$202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3772$202_Y - end - attribute \src "ls180.v:3773.149-3773.187" - cell $not $not$ls180.v:3773$206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3773$206_Y - end - attribute \src "ls180.v:3773.193-3773.230" - cell $not $not$ls180.v:3773$208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3773$208_Y - end - attribute \src "ls180.v:3789.43-3789.73" - cell $not $not$ls180.v:3789$236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \main_sdram_interface_wdata_we - connect \Y $not$ls180.v:3789$236_Y - end - attribute \src "ls180.v:3792.205-3792.245" - cell $not $not$ls180.v:3792$239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3792$239_Y - end - attribute \src "ls180.v:3792.251-3792.290" - cell $not $not$ls180.v:3792$241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3792$241_Y - end - attribute \src "ls180.v:3792.159-3792.292" - cell $not $not$ls180.v:3792$243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3792$242_Y - connect \Y $not$ls180.v:3792$243_Y - end - attribute \src "ls180.v:3793.205-3793.245" - cell $not $not$ls180.v:3793$252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3793$252_Y - end - attribute \src "ls180.v:3793.251-3793.290" - cell $not $not$ls180.v:3793$254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3793$254_Y - end - attribute \src "ls180.v:3793.159-3793.292" - cell $not $not$ls180.v:3793$256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3793$255_Y - connect \Y $not$ls180.v:3793$256_Y - end - attribute \src "ls180.v:3794.205-3794.245" - cell $not $not$ls180.v:3794$265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3794$265_Y - end - attribute \src "ls180.v:3794.251-3794.290" - cell $not $not$ls180.v:3794$267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3794$267_Y - end - attribute \src "ls180.v:3794.159-3794.292" - cell $not $not$ls180.v:3794$269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3794$268_Y - connect \Y $not$ls180.v:3794$269_Y - end - attribute \src "ls180.v:3795.205-3795.245" - cell $not $not$ls180.v:3795$278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3795$278_Y - end - attribute \src "ls180.v:3795.251-3795.290" - cell $not $not$ls180.v:3795$280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3795$280_Y - end - attribute \src "ls180.v:3795.159-3795.292" - cell $not $not$ls180.v:3795$282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3795$281_Y - connect \Y $not$ls180.v:3795$282_Y - end - attribute \src "ls180.v:3822.71-3822.103" - cell $not $not$ls180.v:3822$293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \Y $not$ls180.v:3822$293_Y - end - attribute \src "ls180.v:3825.205-3825.245" - cell $not $not$ls180.v:3825$297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3825$297_Y - end - attribute \src "ls180.v:3825.251-3825.290" - cell $not $not$ls180.v:3825$299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3825$299_Y - end - attribute \src "ls180.v:3825.159-3825.292" - cell $not $not$ls180.v:3825$301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3825$300_Y - connect \Y $not$ls180.v:3825$301_Y - end - attribute \src "ls180.v:3826.205-3826.245" - cell $not $not$ls180.v:3826$310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3826$310_Y - end - attribute \src "ls180.v:3826.251-3826.290" - cell $not $not$ls180.v:3826$312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3826$312_Y - end - attribute \src "ls180.v:3826.159-3826.292" - cell $not $not$ls180.v:3826$314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3826$313_Y - connect \Y $not$ls180.v:3826$314_Y - end - attribute \src "ls180.v:3827.205-3827.245" - cell $not $not$ls180.v:3827$323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3827$323_Y - end - attribute \src "ls180.v:3827.251-3827.290" - cell $not $not$ls180.v:3827$325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3827$325_Y - end - attribute \src "ls180.v:3827.159-3827.292" - cell $not $not$ls180.v:3827$327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3827$326_Y - connect \Y $not$ls180.v:3827$327_Y - end - attribute \src "ls180.v:3828.205-3828.245" - cell $not $not$ls180.v:3828$336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3828$336_Y - end - attribute \src "ls180.v:3828.251-3828.290" - cell $not $not$ls180.v:3828$338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3828$338_Y - end - attribute \src "ls180.v:3828.159-3828.292" - cell $not $not$ls180.v:3828$340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3828$339_Y - connect \Y $not$ls180.v:3828$340_Y - end - attribute \src "ls180.v:3891.71-3891.103" - cell $not $not$ls180.v:3891$379 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \Y $not$ls180.v:3891$379_Y - end - attribute \src "ls180.v:3912.112-3912.150" - cell $not $not$ls180.v:3912$382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3912$382_Y - end - attribute \src "ls180.v:3912.156-3912.193" - cell $not $not$ls180.v:3912$384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3912$384_Y - end - attribute \src "ls180.v:3912.68-3912.195" - cell $not $not$ls180.v:3912$386 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3912$385_Y - connect \Y $not$ls180.v:3912$386_Y - end - attribute \src "ls180.v:3920.11-3920.38" - cell $not $not$ls180.v:3920$389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_write_available - connect \Y $not$ls180.v:3920$389_Y - end - attribute \src "ls180.v:3950.112-3950.150" - cell $not $not$ls180.v:3950$391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3950$391_Y - end - attribute \src "ls180.v:3950.156-3950.193" - cell $not $not$ls180.v:3950$393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3950$393_Y - end - attribute \src "ls180.v:3950.68-3950.195" - cell $not $not$ls180.v:3950$395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3950$394_Y - connect \Y $not$ls180.v:3950$395_Y - end - attribute \src "ls180.v:3958.11-3958.37" - cell $not $not$ls180.v:3958$398 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_read_available - connect \Y $not$ls180.v:3958$398_Y - end - attribute \src "ls180.v:3968.87-3968.331" - cell $not $not$ls180.v:3968$410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3968$409_Y - connect \Y $not$ls180.v:3968$410_Y - end - attribute \src "ls180.v:3969.35-3969.68" - cell $not $not$ls180.v:3969$413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_valid - connect \Y $not$ls180.v:3969$413_Y - end - attribute \src "ls180.v:3969.73-3969.105" - cell $not $not$ls180.v:3969$414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \Y $not$ls180.v:3969$414_Y - end - attribute \src "ls180.v:3973.87-3973.331" - cell $not $not$ls180.v:3973$426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3973$425_Y - connect \Y $not$ls180.v:3973$426_Y - end - attribute \src "ls180.v:3974.35-3974.68" - cell $not $not$ls180.v:3974$429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_valid - connect \Y $not$ls180.v:3974$429_Y - end - attribute \src "ls180.v:3974.73-3974.105" - cell $not $not$ls180.v:3974$430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \Y $not$ls180.v:3974$430_Y - end - attribute \src "ls180.v:3978.87-3978.331" - cell $not $not$ls180.v:3978$442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3978$441_Y - connect \Y $not$ls180.v:3978$442_Y - end - attribute \src "ls180.v:3979.35-3979.68" - cell $not $not$ls180.v:3979$445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_valid - connect \Y $not$ls180.v:3979$445_Y - end - attribute \src "ls180.v:3979.73-3979.105" - cell $not $not$ls180.v:3979$446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \Y $not$ls180.v:3979$446_Y - end - attribute \src "ls180.v:3983.87-3983.331" - cell $not $not$ls180.v:3983$458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3983$457_Y - connect \Y $not$ls180.v:3983$458_Y - end - attribute \src "ls180.v:3984.35-3984.68" - cell $not $not$ls180.v:3984$461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_valid - connect \Y $not$ls180.v:3984$461_Y - end - attribute \src "ls180.v:3984.73-3984.105" - cell $not $not$ls180.v:3984$462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \Y $not$ls180.v:3984$462_Y - end - attribute \src "ls180.v:3988.128-3988.372" - cell $not $not$ls180.v:3988$475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3988$474_Y - connect \Y $not$ls180.v:3988$475_Y - end - attribute \src "ls180.v:3988.502-3988.746" - cell $not $not$ls180.v:3988$491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3988$490_Y - connect \Y $not$ls180.v:3988$491_Y - end - attribute \src "ls180.v:3988.876-3988.1120" - cell $not $not$ls180.v:3988$507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3988$506_Y - connect \Y $not$ls180.v:3988$507_Y - end - attribute \src "ls180.v:3988.1250-3988.1494" - cell $not $not$ls180.v:3988$523 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3988$522_Y - connect \Y $not$ls180.v:3988$523_Y - end - attribute \src "ls180.v:4010.32-4010.50" - cell $not $not$ls180.v:4010$529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_cyc - connect \Y $not$ls180.v:4010$529_Y - end - attribute \src "ls180.v:4049.30-4049.50" - cell $not $not$ls180.v:4049$534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter_skip - connect \Y $not$ls180.v:4049$534_Y - end - attribute \src "ls180.v:4050.30-4050.50" - cell $not $not$ls180.v:4050$535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter_skip - connect \Y $not$ls180.v:4050$535_Y - end - attribute \src "ls180.v:4075.27-4075.48" - cell $not $not$ls180.v:4075$541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_cyc - connect \Y $not$ls180.v:4075$541_Y - end - attribute \src "ls180.v:4076.30-4076.50" - cell $not $not$ls180.v:4076$542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4076$542_Y - end - attribute \src "ls180.v:4077.80-4077.98" - cell $not $not$ls180.v:4077$544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_cmd_consumed - connect \Y $not$ls180.v:4077$544_Y - end - attribute \src "ls180.v:4078.107-4078.127" - cell $not $not$ls180.v:4078$548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wdata_consumed - connect \Y $not$ls180.v:4078$548_Y - end - attribute \src "ls180.v:4079.78-4079.103" - cell $not $not$ls180.v:4079$551 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_we - connect \Y $not$ls180.v:4079$551_Y - end - attribute \src "ls180.v:4080.91-4080.111" - cell $not $not$ls180.v:4080$554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4080$554_Y - end - attribute \src "ls180.v:4096.35-4096.64" - cell $not $not$ls180.v:4096$563 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4096$563_Y - end - attribute \src "ls180.v:4097.36-4097.67" - cell $not $not$ls180.v:4097$564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_source_valid - connect \Y $not$ls180.v:4097$564_Y - end - attribute \src "ls180.v:4103.32-4103.61" - cell $not $not$ls180.v:4103$565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4103$565_Y - end - attribute \src "ls180.v:4109.36-4109.67" - cell $not $not$ls180.v:4109$566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4109$566_Y - end - attribute \src "ls180.v:4110.35-4110.64" - cell $not $not$ls180.v:4110$567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_sink_ready - connect \Y $not$ls180.v:4110$567_Y - end - attribute \src "ls180.v:4113.32-4113.63" - cell $not $not$ls180.v:4113$570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4113$570_Y - end - attribute \src "ls180.v:4151.81-4151.108" - cell $not $not$ls180.v:4151$580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_readable - connect \Y $not$ls180.v:4151$580_Y - end - attribute \src "ls180.v:4181.81-4181.108" - cell $not $not$ls180.v:4181$591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_readable - connect \Y $not$ls180.v:4181$591_Y - end - attribute \src "ls180.v:4322.60-4322.85" - cell $not $not$ls180.v:4322$632 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_clocker_clk_d - connect \Y $not$ls180.v:4322$632_Y - end - attribute \src "ls180.v:4463.54-4463.96" - cell $not $not$ls180.v:4463$646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \Y $not$ls180.v:4463$646_Y - end - attribute \src "ls180.v:4466.48-4466.86" - cell $not $not$ls180.v:4466$649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:4466$649_Y - end - attribute \src "ls180.v:4590.55-4590.98" - cell $not $not$ls180.v:4590$667 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_strobe_all - connect \Y $not$ls180.v:4590$667_Y - end - attribute \src "ls180.v:4593.49-4593.88" - cell $not $not$ls180.v:4593$670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:4593$670_Y - end - attribute \src "ls180.v:4643.30-4643.58" - cell $not $not$ls180.v:4643$676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_sink_valid - connect \Y $not$ls180.v:4643$676_Y - end - attribute \src "ls180.v:4724.56-4724.100" - cell $not $not$ls180.v:4724$682 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_strobe_all - connect \Y $not$ls180.v:4724$682_Y - end - attribute \src "ls180.v:4727.50-4727.90" - cell $not $not$ls180.v:4727$685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:4727$685_Y - end - attribute \src "ls180.v:4843.42-4843.74" - cell $not $not$ls180.v:4843$701 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_valid - connect \Y $not$ls180.v:4843$701_Y - end - attribute \src "ls180.v:5367.50-5367.88" - cell $not $not$ls180.v:5367$986 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_strobe_all - connect \Y $not$ls180.v:5367$986_Y - end - attribute \src "ls180.v:5379.52-5379.102" - cell $not $not$ls180.v:5379$989 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage - connect \Y $not$ls180.v:5379$989_Y - end - attribute \src "ls180.v:5438.38-5438.74" - cell $not $not$ls180.v:5438$996 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_dma_enable_storage - connect \Y $not$ls180.v:5438$996_Y - end - attribute \src "ls180.v:5739.69-5739.88" - cell $not $not$ls180.v:5739$1065 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \Y $not$ls180.v:5739$1065_Y - end - attribute \src "ls180.v:5756.63-5756.94" - cell $not $not$ls180.v:5756$1086 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5756$1086_Y - end - attribute \src "ls180.v:5759.65-5759.96" - cell $not $not$ls180.v:5759$1093 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5759$1093_Y - end - attribute \src "ls180.v:5762.65-5762.96" - cell $not $not$ls180.v:5762$1100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5762$1100_Y - end - attribute \src "ls180.v:5765.65-5765.96" - cell $not $not$ls180.v:5765$1107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5765$1107_Y - end - attribute \src "ls180.v:5768.65-5768.96" - cell $not $not$ls180.v:5768$1114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5768$1114_Y - end - attribute \src "ls180.v:5771.68-5771.99" - cell $not $not$ls180.v:5771$1121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5771$1121_Y - end - attribute \src "ls180.v:5774.68-5774.99" - cell $not $not$ls180.v:5774$1128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5774$1128_Y - end - attribute \src "ls180.v:5777.68-5777.99" - cell $not $not$ls180.v:5777$1135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5777$1135_Y - end - attribute \src "ls180.v:5780.68-5780.99" - cell $not $not$ls180.v:5780$1142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5780$1142_Y - end - attribute \src "ls180.v:5794.60-5794.91" - cell $not $not$ls180.v:5794$1150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5794$1150_Y - end - attribute \src "ls180.v:5797.60-5797.91" - cell $not $not$ls180.v:5797$1157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5797$1157_Y - end - attribute \src "ls180.v:5800.60-5800.91" - cell $not $not$ls180.v:5800$1164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5800$1164_Y - end - attribute \src "ls180.v:5803.60-5803.91" - cell $not $not$ls180.v:5803$1171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5803$1171_Y - end - attribute \src "ls180.v:5806.61-5806.92" - cell $not $not$ls180.v:5806$1178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5806$1178_Y - end - attribute \src "ls180.v:5809.61-5809.92" - cell $not $not$ls180.v:5809$1185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5809$1185_Y - end - attribute \src "ls180.v:5820.59-5820.90" - cell $not $not$ls180.v:5820$1193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5820$1193_Y - end - attribute \src "ls180.v:5823.58-5823.89" - cell $not $not$ls180.v:5823$1200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5823$1200_Y - end - attribute \src "ls180.v:5834.64-5834.95" - cell $not $not$ls180.v:5834$1208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5834$1208_Y - end - attribute \src "ls180.v:5837.63-5837.94" - cell $not $not$ls180.v:5837$1215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5837$1215_Y - end - attribute \src "ls180.v:5840.63-5840.94" - cell $not $not$ls180.v:5840$1222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5840$1222_Y - end - attribute \src "ls180.v:5843.63-5843.94" - cell $not $not$ls180.v:5843$1229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5843$1229_Y - end - attribute \src "ls180.v:5846.63-5846.94" - cell $not $not$ls180.v:5846$1236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5846$1236_Y - end - attribute \src "ls180.v:5849.64-5849.95" - cell $not $not$ls180.v:5849$1243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5849$1243_Y - end - attribute \src "ls180.v:5852.64-5852.95" - cell $not $not$ls180.v:5852$1250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5852$1250_Y - end - attribute \src "ls180.v:5855.64-5855.95" - cell $not $not$ls180.v:5855$1257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5855$1257_Y - end - attribute \src "ls180.v:5858.64-5858.95" - cell $not $not$ls180.v:5858$1264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5858$1264_Y - end - attribute \src "ls180.v:5871.64-5871.95" - cell $not $not$ls180.v:5871$1272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5871$1272_Y - end - attribute \src "ls180.v:5874.63-5874.94" - cell $not $not$ls180.v:5874$1279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5874$1279_Y - end - attribute \src "ls180.v:5877.63-5877.94" - cell $not $not$ls180.v:5877$1286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5877$1286_Y - end - attribute \src "ls180.v:5880.63-5880.94" - cell $not $not$ls180.v:5880$1293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5880$1293_Y - end - attribute \src "ls180.v:5883.63-5883.94" - cell $not $not$ls180.v:5883$1300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5883$1300_Y - end - attribute \src "ls180.v:5886.64-5886.95" - cell $not $not$ls180.v:5886$1307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5886$1307_Y - end - attribute \src "ls180.v:5889.64-5889.95" - cell $not $not$ls180.v:5889$1314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5889$1314_Y - end - attribute \src "ls180.v:5892.64-5892.95" - cell $not $not$ls180.v:5892$1321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5892$1321_Y - end - attribute \src "ls180.v:5895.64-5895.95" - cell $not $not$ls180.v:5895$1328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5895$1328_Y - end - attribute \src "ls180.v:5908.66-5908.97" - cell $not $not$ls180.v:5908$1336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5908$1336_Y - end - attribute \src "ls180.v:5911.66-5911.97" - cell $not $not$ls180.v:5911$1343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5911$1343_Y - end - attribute \src "ls180.v:5914.66-5914.97" - cell $not $not$ls180.v:5914$1350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5914$1350_Y - end - attribute \src "ls180.v:5917.66-5917.97" - cell $not $not$ls180.v:5917$1357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5917$1357_Y - end - attribute \src "ls180.v:5920.66-5920.97" - cell $not $not$ls180.v:5920$1364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5920$1364_Y - end - attribute \src "ls180.v:5923.66-5923.97" - cell $not $not$ls180.v:5923$1371 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5923$1371_Y - end - attribute \src "ls180.v:5926.66-5926.97" - cell $not $not$ls180.v:5926$1378 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5926$1378_Y - end - attribute \src "ls180.v:5929.66-5929.97" - cell $not $not$ls180.v:5929$1385 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5929$1385_Y - end - attribute \src "ls180.v:5932.68-5932.99" - cell $not $not$ls180.v:5932$1392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5932$1392_Y - end - attribute \src "ls180.v:5935.68-5935.99" - cell $not $not$ls180.v:5935$1399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5935$1399_Y - end - attribute \src "ls180.v:5938.68-5938.99" - cell $not $not$ls180.v:5938$1406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5938$1406_Y - end - attribute \src "ls180.v:5941.68-5941.99" - cell $not $not$ls180.v:5941$1413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5941$1413_Y - end - attribute \src "ls180.v:5944.68-5944.99" - cell $not $not$ls180.v:5944$1420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5944$1420_Y - end - attribute \src "ls180.v:5947.65-5947.96" - cell $not $not$ls180.v:5947$1427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5947$1427_Y - end - attribute \src "ls180.v:5950.66-5950.97" - cell $not $not$ls180.v:5950$1434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5950$1434_Y - end - attribute \src "ls180.v:5970.70-5970.101" - cell $not $not$ls180.v:5970$1442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5970$1442_Y - end - attribute \src "ls180.v:5973.70-5973.101" - cell $not $not$ls180.v:5973$1449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5973$1449_Y - end - attribute \src "ls180.v:5976.70-5976.101" - cell $not $not$ls180.v:5976$1456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5976$1456_Y - end - attribute \src "ls180.v:5979.70-5979.101" - cell $not $not$ls180.v:5979$1463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5979$1463_Y - end - attribute \src "ls180.v:5982.69-5982.100" - cell $not $not$ls180.v:5982$1470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5982$1470_Y - end - attribute \src "ls180.v:5985.69-5985.100" - cell $not $not$ls180.v:5985$1477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5985$1477_Y - end - attribute \src "ls180.v:5988.69-5988.100" - cell $not $not$ls180.v:5988$1484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5988$1484_Y - end - attribute \src "ls180.v:5991.69-5991.100" - cell $not $not$ls180.v:5991$1491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5991$1491_Y - end - attribute \src "ls180.v:5994.60-5994.91" - cell $not $not$ls180.v:5994$1498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5994$1498_Y - end - attribute \src "ls180.v:5997.71-5997.102" - cell $not $not$ls180.v:5997$1505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5997$1505_Y - end - attribute \src "ls180.v:6000.71-6000.102" - cell $not $not$ls180.v:6000$1512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6000$1512_Y - end - attribute \src "ls180.v:6003.71-6003.102" - cell $not $not$ls180.v:6003$1519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6003$1519_Y - end - attribute \src "ls180.v:6006.71-6006.102" - cell $not $not$ls180.v:6006$1526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6006$1526_Y - end - attribute \src "ls180.v:6009.71-6009.102" - cell $not $not$ls180.v:6009$1533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6009$1533_Y - end - attribute \src "ls180.v:6012.71-6012.102" - cell $not $not$ls180.v:6012$1540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6012$1540_Y - end - attribute \src "ls180.v:6015.70-6015.101" - cell $not $not$ls180.v:6015$1547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6015$1547_Y - end - attribute \src "ls180.v:6018.70-6018.101" - cell $not $not$ls180.v:6018$1554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6018$1554_Y - end - attribute \src "ls180.v:6021.70-6021.101" - cell $not $not$ls180.v:6021$1561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6021$1561_Y - end - attribute \src "ls180.v:6024.70-6024.101" - cell $not $not$ls180.v:6024$1568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6024$1568_Y - end - attribute \src "ls180.v:6027.70-6027.101" - cell $not $not$ls180.v:6027$1575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6027$1575_Y - end - attribute \src "ls180.v:6030.70-6030.101" - cell $not $not$ls180.v:6030$1582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6030$1582_Y - end - attribute \src "ls180.v:6033.70-6033.101" - cell $not $not$ls180.v:6033$1589 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6033$1589_Y - end - attribute \src "ls180.v:6036.70-6036.101" - cell $not $not$ls180.v:6036$1596 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6036$1596_Y - end - attribute \src "ls180.v:6039.70-6039.101" - cell $not $not$ls180.v:6039$1603 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6039$1603_Y - end - attribute \src "ls180.v:6042.70-6042.101" - cell $not $not$ls180.v:6042$1610 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6042$1610_Y - end - attribute \src "ls180.v:6045.66-6045.97" - cell $not $not$ls180.v:6045$1617 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6045$1617_Y - end - attribute \src "ls180.v:6048.67-6048.98" - cell $not $not$ls180.v:6048$1624 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6048$1624_Y - end - attribute \src "ls180.v:6051.70-6051.101" - cell $not $not$ls180.v:6051$1631 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6051$1631_Y - end - attribute \src "ls180.v:6054.70-6054.101" - cell $not $not$ls180.v:6054$1638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6054$1638_Y - end - attribute \src "ls180.v:6057.69-6057.100" - cell $not $not$ls180.v:6057$1645 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6057$1645_Y - end - attribute \src "ls180.v:6060.69-6060.100" - cell $not $not$ls180.v:6060$1652 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6060$1652_Y - end - attribute \src "ls180.v:6063.69-6063.100" - cell $not $not$ls180.v:6063$1659 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6063$1659_Y - end - attribute \src "ls180.v:6066.69-6066.100" - cell $not $not$ls180.v:6066$1666 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6066$1666_Y - end - attribute \src "ls180.v:6105.66-6105.97" - cell $not $not$ls180.v:6105$1674 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6105$1674_Y - end - attribute \src "ls180.v:6108.66-6108.97" - cell $not $not$ls180.v:6108$1681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6108$1681_Y - end - attribute \src "ls180.v:6111.66-6111.97" - cell $not $not$ls180.v:6111$1688 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6111$1688_Y - end - attribute \src "ls180.v:6114.66-6114.97" - cell $not $not$ls180.v:6114$1695 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6114$1695_Y - end - attribute \src "ls180.v:6117.66-6117.97" - cell $not $not$ls180.v:6117$1702 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6117$1702_Y - end - attribute \src "ls180.v:6120.66-6120.97" - cell $not $not$ls180.v:6120$1709 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6120$1709_Y - end - attribute \src "ls180.v:6123.66-6123.97" - cell $not $not$ls180.v:6123$1716 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6123$1716_Y - end - attribute \src "ls180.v:6126.66-6126.97" - cell $not $not$ls180.v:6126$1723 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6126$1723_Y - end - attribute \src "ls180.v:6129.68-6129.99" - cell $not $not$ls180.v:6129$1730 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6129$1730_Y - end - attribute \src "ls180.v:6132.68-6132.99" - cell $not $not$ls180.v:6132$1737 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6132$1737_Y - end - attribute \src "ls180.v:6135.68-6135.99" - cell $not $not$ls180.v:6135$1744 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6135$1744_Y - end - attribute \src "ls180.v:6138.68-6138.99" - cell $not $not$ls180.v:6138$1751 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6138$1751_Y - end - attribute \src "ls180.v:6141.68-6141.99" - cell $not $not$ls180.v:6141$1758 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6141$1758_Y - end - attribute \src "ls180.v:6144.65-6144.96" - cell $not $not$ls180.v:6144$1765 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6144$1765_Y - end - attribute \src "ls180.v:6147.66-6147.97" - cell $not $not$ls180.v:6147$1772 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6147$1772_Y - end - attribute \src "ls180.v:6150.68-6150.99" - cell $not $not$ls180.v:6150$1779 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6150$1779_Y - end - attribute \src "ls180.v:6153.68-6153.99" - cell $not $not$ls180.v:6153$1786 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6153$1786_Y - end - attribute \src "ls180.v:6156.68-6156.99" - cell $not $not$ls180.v:6156$1793 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6156$1793_Y - end - attribute \src "ls180.v:6159.68-6159.99" - cell $not $not$ls180.v:6159$1800 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6159$1800_Y - end - attribute \src "ls180.v:6184.68-6184.99" - cell $not $not$ls180.v:6184$1808 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6184$1808_Y - end - attribute \src "ls180.v:6187.73-6187.104" - cell $not $not$ls180.v:6187$1815 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6187$1815_Y - end - attribute \src "ls180.v:6190.73-6190.104" - cell $not $not$ls180.v:6190$1822 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6190$1822_Y - end - attribute \src "ls180.v:6193.66-6193.97" - cell $not $not$ls180.v:6193$1829 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6193$1829_Y - end - attribute \src "ls180.v:6201.70-6201.101" - cell $not $not$ls180.v:6201$1837 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6201$1837_Y - end - attribute \src "ls180.v:6204.74-6204.105" - cell $not $not$ls180.v:6204$1844 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6204$1844_Y - end - attribute \src "ls180.v:6207.64-6207.95" - cell $not $not$ls180.v:6207$1851 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6207$1851_Y - end - attribute \src "ls180.v:6210.74-6210.105" - cell $not $not$ls180.v:6210$1858 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6210$1858_Y - end - attribute \src "ls180.v:6213.74-6213.105" - cell $not $not$ls180.v:6213$1865 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6213$1865_Y - end - attribute \src "ls180.v:6216.75-6216.106" - cell $not $not$ls180.v:6216$1872 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6216$1872_Y - end - attribute \src "ls180.v:6219.73-6219.104" - cell $not $not$ls180.v:6219$1879 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6219$1879_Y - end - attribute \src "ls180.v:6222.73-6222.104" - cell $not $not$ls180.v:6222$1886 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6222$1886_Y - end - attribute \src "ls180.v:6225.73-6225.104" - cell $not $not$ls180.v:6225$1893 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6225$1893_Y - end - attribute \src "ls180.v:6228.73-6228.104" - cell $not $not$ls180.v:6228$1900 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6228$1900_Y - end - attribute \src "ls180.v:6246.67-6246.99" - cell $not $not$ls180.v:6246$1908 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6246$1908_Y - end - attribute \src "ls180.v:6249.67-6249.99" - cell $not $not$ls180.v:6249$1915 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6249$1915_Y - end - attribute \src "ls180.v:6252.65-6252.97" - cell $not $not$ls180.v:6252$1922 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6252$1922_Y - end - attribute \src "ls180.v:6255.64-6255.96" - cell $not $not$ls180.v:6255$1929 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6255$1929_Y - end - attribute \src "ls180.v:6258.63-6258.95" - cell $not $not$ls180.v:6258$1936 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6258$1936_Y - end - attribute \src "ls180.v:6261.62-6261.94" - cell $not $not$ls180.v:6261$1943 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6261$1943_Y - end - attribute \src "ls180.v:6264.68-6264.100" - cell $not $not$ls180.v:6264$1950 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6264$1950_Y - end - attribute \src "ls180.v:6286.67-6286.99" - cell $not $not$ls180.v:6286$1959 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6286$1959_Y - end - attribute \src "ls180.v:6289.67-6289.99" - cell $not $not$ls180.v:6289$1966 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6289$1966_Y - end - attribute \src "ls180.v:6292.65-6292.97" - cell $not $not$ls180.v:6292$1973 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6292$1973_Y - end - attribute \src "ls180.v:6295.64-6295.96" - cell $not $not$ls180.v:6295$1980 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6295$1980_Y - end - attribute \src "ls180.v:6298.63-6298.95" - cell $not $not$ls180.v:6298$1987 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6298$1987_Y - end - attribute \src "ls180.v:6301.62-6301.94" - cell $not $not$ls180.v:6301$1994 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6301$1994_Y - end - attribute \src "ls180.v:6304.68-6304.100" - cell $not $not$ls180.v:6304$2001 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6304$2001_Y - end - attribute \src "ls180.v:6307.71-6307.103" - cell $not $not$ls180.v:6307$2008 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6307$2008_Y - end - attribute \src "ls180.v:6310.71-6310.103" - cell $not $not$ls180.v:6310$2015 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6310$2015_Y - end - attribute \src "ls180.v:6334.64-6334.96" - cell $not $not$ls180.v:6334$2024 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6334$2024_Y - end - attribute \src "ls180.v:6337.64-6337.96" - cell $not $not$ls180.v:6337$2031 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6337$2031_Y - end - attribute \src "ls180.v:6340.64-6340.96" - cell $not $not$ls180.v:6340$2038 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6340$2038_Y - end - attribute \src "ls180.v:6343.64-6343.96" - cell $not $not$ls180.v:6343$2045 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6343$2045_Y - end - attribute \src "ls180.v:6346.66-6346.98" - cell $not $not$ls180.v:6346$2052 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6346$2052_Y - end - attribute \src "ls180.v:6349.66-6349.98" - cell $not $not$ls180.v:6349$2059 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6349$2059_Y - end - attribute \src "ls180.v:6352.66-6352.98" - cell $not $not$ls180.v:6352$2066 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6352$2066_Y - end - attribute \src "ls180.v:6355.66-6355.98" - cell $not $not$ls180.v:6355$2073 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6355$2073_Y - end - attribute \src "ls180.v:6358.62-6358.94" - cell $not $not$ls180.v:6358$2080 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6358$2080_Y - end - attribute \src "ls180.v:6361.72-6361.104" - cell $not $not$ls180.v:6361$2087 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6361$2087_Y - end - attribute \src "ls180.v:6364.65-6364.97" - cell $not $not$ls180.v:6364$2094 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6364$2094_Y - end - attribute \src "ls180.v:6367.65-6367.97" - cell $not $not$ls180.v:6367$2101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6367$2101_Y - end - attribute \src "ls180.v:6370.65-6370.97" - cell $not $not$ls180.v:6370$2108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6370$2108_Y - end - attribute \src "ls180.v:6373.65-6373.97" - cell $not $not$ls180.v:6373$2115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6373$2115_Y - end - attribute \src "ls180.v:6376.77-6376.109" - cell $not $not$ls180.v:6376$2122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6376$2122_Y - end - attribute \src "ls180.v:6379.78-6379.110" - cell $not $not$ls180.v:6379$2129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6379$2129_Y - end - attribute \src "ls180.v:6382.69-6382.101" - cell $not $not$ls180.v:6382$2136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6382$2136_Y - end - attribute \src "ls180.v:6402.55-6402.87" - cell $not $not$ls180.v:6402$2144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6402$2144_Y - end - attribute \src "ls180.v:6405.65-6405.97" - cell $not $not$ls180.v:6405$2151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6405$2151_Y - end - attribute \src "ls180.v:6408.66-6408.98" - cell $not $not$ls180.v:6408$2158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6408$2158_Y - end - attribute \src "ls180.v:6411.70-6411.102" - cell $not $not$ls180.v:6411$2165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6411$2165_Y - end - attribute \src "ls180.v:6414.71-6414.103" - cell $not $not$ls180.v:6414$2172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6414$2172_Y - end - attribute \src "ls180.v:6417.69-6417.101" - cell $not $not$ls180.v:6417$2179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6417$2179_Y - end - attribute \src "ls180.v:6420.66-6420.98" - cell $not $not$ls180.v:6420$2186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6420$2186_Y - end - attribute \src "ls180.v:6423.65-6423.97" - cell $not $not$ls180.v:6423$2193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6423$2193_Y - end - attribute \src "ls180.v:6436.71-6436.103" - cell $not $not$ls180.v:6436$2201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6436$2201_Y - end - attribute \src "ls180.v:6439.71-6439.103" - cell $not $not$ls180.v:6439$2208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6439$2208_Y - end - attribute \src "ls180.v:6442.71-6442.103" - cell $not $not$ls180.v:6442$2215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6442$2215_Y - end - attribute \src "ls180.v:6445.71-6445.103" - cell $not $not$ls180.v:6445$2222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6445$2222_Y - end - attribute \src "ls180.v:6826.86-6826.330" - cell $not $not$ls180.v:6826$2271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6826$2270_Y - connect \Y $not$ls180.v:6826$2271_Y - end - attribute \src "ls180.v:6850.86-6850.330" - cell $not $not$ls180.v:6850$2287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6850$2286_Y - connect \Y $not$ls180.v:6850$2287_Y - end - attribute \src "ls180.v:6874.86-6874.330" - cell $not $not$ls180.v:6874$2303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6874$2302_Y - connect \Y $not$ls180.v:6874$2303_Y - end - attribute \src "ls180.v:6898.86-6898.330" - cell $not $not$ls180.v:6898$2319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6898$2318_Y - connect \Y $not$ls180.v:6898$2319_Y - end - attribute \src "ls180.v:7396.18-7396.42" - cell $not $not$ls180.v:7396$2372 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_clocker_clk0 - connect \Y $not$ls180.v:7396$2372_Y - end - attribute \src "ls180.v:7487.72-7487.101" - cell $not $not$ls180.v:7487$2417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_ack - connect \Y $not$ls180.v:7487$2417_Y - end - attribute \src "ls180.v:7506.8-7506.38" - cell $not $not$ls180.v:7506$2421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_zero_trigger - connect \Y $not$ls180.v:7506$2421_Y - end - attribute \src "ls180.v:7514.32-7514.55" - cell $not $not$ls180.v:7514$2423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:7514$2423_Y - end - attribute \src "ls180.v:7584.136-7584.189" - cell $not $not$ls180.v:7584$2438 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7584$2438_Y - end - attribute \src "ls180.v:7590.136-7590.189" - cell $not $not$ls180.v:7590$2443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7590$2443_Y - end - attribute \src "ls180.v:7591.8-7591.61" - cell $not $not$ls180.v:7591$2445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7591$2445_Y - end - attribute \src "ls180.v:7599.8-7599.56" - cell $not $not$ls180.v:7599$2448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:7599$2448_Y - end - attribute \src "ls180.v:7614.8-7614.46" - cell $not $not$ls180.v:7614$2450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \Y $not$ls180.v:7614$2450_Y - end - attribute \src "ls180.v:7630.136-7630.189" - cell $not $not$ls180.v:7630$2454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7630$2454_Y - end - attribute \src "ls180.v:7636.136-7636.189" - cell $not $not$ls180.v:7636$2459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7636$2459_Y - end - attribute \src "ls180.v:7637.8-7637.61" - cell $not $not$ls180.v:7637$2461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7637$2461_Y - end - attribute \src "ls180.v:7645.8-7645.56" - cell $not $not$ls180.v:7645$2464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:7645$2464_Y - end - attribute \src "ls180.v:7660.8-7660.46" - cell $not $not$ls180.v:7660$2466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \Y $not$ls180.v:7660$2466_Y - end - attribute \src "ls180.v:7676.136-7676.189" - cell $not $not$ls180.v:7676$2470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7676$2470_Y - end - attribute \src "ls180.v:7682.136-7682.189" - cell $not $not$ls180.v:7682$2475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7682$2475_Y - end - attribute \src "ls180.v:7683.8-7683.61" - cell $not $not$ls180.v:7683$2477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7683$2477_Y - end - attribute \src "ls180.v:7691.8-7691.56" - cell $not $not$ls180.v:7691$2480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:7691$2480_Y - end - attribute \src "ls180.v:7706.8-7706.46" - cell $not $not$ls180.v:7706$2482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \Y $not$ls180.v:7706$2482_Y - end - attribute \src "ls180.v:7722.136-7722.189" - cell $not $not$ls180.v:7722$2486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7722$2486_Y - end - attribute \src "ls180.v:7728.136-7728.189" - cell $not $not$ls180.v:7728$2491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7728$2491_Y - end - attribute \src "ls180.v:7729.8-7729.61" - cell $not $not$ls180.v:7729$2493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7729$2493_Y - end - attribute \src "ls180.v:7737.8-7737.56" - cell $not $not$ls180.v:7737$2496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:7737$2496_Y - end - attribute \src "ls180.v:7752.8-7752.46" - cell $not $not$ls180.v:7752$2498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \Y $not$ls180.v:7752$2498_Y - end - attribute \src "ls180.v:7760.7-7760.22" - cell $not $not$ls180.v:7760$2501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_en0 - connect \Y $not$ls180.v:7760$2501_Y - end - attribute \src "ls180.v:7763.8-7763.29" - cell $not $not$ls180.v:7763$2502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_max_time0 - connect \Y $not$ls180.v:7763$2502_Y - end - attribute \src "ls180.v:7767.7-7767.22" - cell $not $not$ls180.v:7767$2504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_en1 - connect \Y $not$ls180.v:7767$2504_Y - end - attribute \src "ls180.v:7770.8-7770.29" - cell $not $not$ls180.v:7770$2505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_max_time1 - connect \Y $not$ls180.v:7770$2505_Y - end - attribute \src "ls180.v:7889.30-7889.60" - cell $not $not$ls180.v:7889$2507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_sync_rhs_array_muxed2 - connect \Y $not$ls180.v:7889$2507_Y - end - attribute \src "ls180.v:7890.30-7890.60" - cell $not $not$ls180.v:7890$2508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_sync_rhs_array_muxed3 - connect \Y $not$ls180.v:7890$2508_Y - end - attribute \src "ls180.v:7891.29-7891.59" - cell $not $not$ls180.v:7891$2509 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_sync_rhs_array_muxed4 - connect \Y $not$ls180.v:7891$2509_Y - end - attribute \src "ls180.v:7902.8-7902.33" - cell $not $not$ls180.v:7902$2510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_tccdcon_ready - connect \Y $not$ls180.v:7902$2510_Y - end - attribute \src "ls180.v:7917.8-7917.33" - cell $not $not$ls180.v:7917$2513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_twtrcon_ready - connect \Y $not$ls180.v:7917$2513_Y - end - attribute \src "ls180.v:7953.36-7953.58" - cell $not $not$ls180.v:7953$2543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_tx_busy - connect \Y $not$ls180.v:7953$2543_Y - end - attribute \src "ls180.v:7953.64-7953.89" - cell $not $not$ls180.v:7953$2545 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_sink_ready - connect \Y $not$ls180.v:7953$2545_Y - end - attribute \src "ls180.v:7982.7-7982.29" - cell $not $not$ls180.v:7982$2552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_rx_busy - connect \Y $not$ls180.v:7982$2552_Y - end - attribute \src "ls180.v:7983.9-7983.26" - cell $not $not$ls180.v:7983$2553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_rx - connect \Y $not$ls180.v:7983$2553_Y - end - attribute \src "ls180.v:8016.8-8016.29" - cell $not $not$ls180.v:8016$2559 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_trigger - connect \Y $not$ls180.v:8016$2559_Y - end - attribute \src "ls180.v:8023.8-8023.29" - cell $not $not$ls180.v:8023$2561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_trigger - connect \Y $not$ls180.v:8023$2561_Y - end - attribute \src "ls180.v:8033.80-8033.106" - cell $not $not$ls180.v:8033$2564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8033$2564_Y - end - attribute \src "ls180.v:8039.80-8039.106" - cell $not $not$ls180.v:8039$2569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8039$2569_Y - end - attribute \src "ls180.v:8040.8-8040.34" - cell $not $not$ls180.v:8040$2571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_do_read - connect \Y $not$ls180.v:8040$2571_Y - end - attribute \src "ls180.v:8055.80-8055.106" - cell $not $not$ls180.v:8055$2575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8055$2575_Y - end - attribute \src "ls180.v:8061.80-8061.106" - cell $not $not$ls180.v:8061$2580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8061$2580_Y - end - attribute \src "ls180.v:8062.8-8062.34" - cell $not $not$ls180.v:8062$2582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_do_read - connect \Y $not$ls180.v:8062$2582_Y - end - attribute \src "ls180.v:8093.23-8093.42" - cell $not $not$ls180.v:8093$2586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_spi_master_cs - connect \Y $not$ls180.v:8093$2586_Y - end - attribute \src "ls180.v:8093.47-8093.73" - cell $not $not$ls180.v:8093$2587 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_spi_master_cs_enable - connect \Y $not$ls180.v:8093$2587_Y - end - attribute \src "ls180.v:8147.7-8147.31" - cell $not $not$ls180.v:8147$2598 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_clocker_stop - connect \Y $not$ls180.v:8147$2598_Y - end - attribute \src "ls180.v:8219.8-8219.46" - cell $not $not$ls180.v:8219$2610 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:8219$2610_Y - end - attribute \src "ls180.v:8300.8-8300.47" - cell $not $not$ls180.v:8300$2622 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:8300$2622_Y - end - attribute \src "ls180.v:8361.8-8361.48" - cell $not $not$ls180.v:8361$2634 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:8361$2634_Y - end - attribute \src "ls180.v:8531.88-8531.118" - cell $not $not$ls180.v:8531$2648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8531$2648_Y - end - attribute \src "ls180.v:8537.88-8537.118" - cell $not $not$ls180.v:8537$2653 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8537$2653_Y - end - attribute \src "ls180.v:8538.8-8538.38" - cell $not $not$ls180.v:8538$2655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_do_read - connect \Y $not$ls180.v:8538$2655_Y - end - attribute \src "ls180.v:8617.88-8617.118" - cell $not $not$ls180.v:8617$2670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8617$2670_Y - end - attribute \src "ls180.v:8623.88-8623.118" - cell $not $not$ls180.v:8623$2675 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8623$2675_Y - end - attribute \src "ls180.v:8624.8-8624.38" - cell $not $not$ls180.v:8624$2677 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_do_read - connect \Y $not$ls180.v:8624$2677_Y - end - attribute \src "ls180.v:8641.22-8641.37" - cell $not $not$ls180.v:8641$2681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cs - connect \Y $not$ls180.v:8641$2681_Y - end - attribute \src "ls180.v:8641.42-8641.64" - cell $not $not$ls180.v:8641$2682 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cs_enable - connect \Y $not$ls180.v:8641$2682_Y - end - attribute \src "ls180.v:8679.9-8679.28" - cell $not $not$ls180.v:8679$2685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [0] - connect \Y $not$ls180.v:8679$2685_Y - end - attribute \src "ls180.v:8698.9-8698.28" - cell $not $not$ls180.v:8698$2686 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [1] - connect \Y $not$ls180.v:8698$2686_Y - end - attribute \src "ls180.v:8717.9-8717.28" - cell $not $not$ls180.v:8717$2687 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [2] - connect \Y $not$ls180.v:8717$2687_Y - end - attribute \src "ls180.v:8736.9-8736.28" - cell $not $not$ls180.v:8736$2688 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [3] - connect \Y $not$ls180.v:8736$2688_Y - end - attribute \src "ls180.v:8755.9-8755.28" - cell $not $not$ls180.v:8755$2689 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [4] - connect \Y $not$ls180.v:8755$2689_Y - end - attribute \src "ls180.v:8776.8-8776.21" - cell $not $not$ls180.v:8776$2690 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_done - connect \Y $not$ls180.v:8776$2690_Y - end - attribute \src "ls180.v:10259.8-10259.51" - cell $or $or$ls180.v:10259$2762 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sys_rst_1 - connect \B \main_libresocsim_libresoc_reset - connect \Y $or$ls180.v:10259$2762_Y - end - attribute \src "ls180.v:2798.10-2798.96" - cell $or $or$ls180.v:2798$21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface0_converted_interface_ack - connect \B \main_libresocsim_converter0_skip - connect \Y $or$ls180.v:2798$21_Y - end - attribute \src "ls180.v:2858.10-2858.96" - cell $or $or$ls180.v:2858$32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface1_converted_interface_ack - connect \B \main_libresocsim_converter1_skip - connect \Y $or$ls180.v:2858$32_Y - end - attribute \src "ls180.v:2918.10-2918.96" - cell $or $or$ls180.v:2918$43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface2_converted_interface_ack - connect \B \main_libresocsim_converter2_skip - connect \Y $or$ls180.v:2918$43_Y - end - attribute \src "ls180.v:3110.39-3110.105" - cell $or $or$ls180.v:3110$75 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_start0 - connect \B $ne$ls180.v:3110$74_Y - connect \Y $or$ls180.v:3110$75_Y - end - attribute \src "ls180.v:3153.59-3153.140" - cell $or $or$ls180.v:3153$79 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_req_wdata_ready - connect \B \main_sdram_bankmachine0_req_rdata_valid - connect \Y $or$ls180.v:3153$79_Y - end - attribute \src "ls180.v:3154.44-3154.151" - cell $or $or$ls180.v:3154$80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $or$ls180.v:3154$80_Y - end - attribute \src "ls180.v:3162.45-3162.170" - cell $or $or$ls180.v:3162$84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3162$83_Y - connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3162$84_Y - end - attribute \src "ls180.v:3199.127-3199.245" - cell $or $or$ls180.v:3199$97 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3199$97_Y - end - attribute \src "ls180.v:3205.57-3205.157" - cell $or $or$ls180.v:3205$103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3205$102_Y - connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:3205$103_Y - end - attribute \src "ls180.v:3310.59-3310.140" - cell $or $or$ls180.v:3310$109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_req_wdata_ready - connect \B \main_sdram_bankmachine1_req_rdata_valid - connect \Y $or$ls180.v:3310$109_Y - end - attribute \src "ls180.v:3311.44-3311.151" - cell $or $or$ls180.v:3311$110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $or$ls180.v:3311$110_Y - end - attribute \src "ls180.v:3319.45-3319.170" - cell $or $or$ls180.v:3319$114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3319$113_Y - connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3319$114_Y - end - attribute \src "ls180.v:3356.127-3356.245" - cell $or $or$ls180.v:3356$127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3356$127_Y - end - attribute \src "ls180.v:3362.57-3362.157" - cell $or $or$ls180.v:3362$133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3362$132_Y - connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:3362$133_Y - end - attribute \src "ls180.v:3467.59-3467.140" - cell $or $or$ls180.v:3467$139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_req_wdata_ready - connect \B \main_sdram_bankmachine2_req_rdata_valid - connect \Y $or$ls180.v:3467$139_Y - end - attribute \src "ls180.v:3468.44-3468.151" - cell $or $or$ls180.v:3468$140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $or$ls180.v:3468$140_Y - end - attribute \src "ls180.v:3476.45-3476.170" - cell $or $or$ls180.v:3476$144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3476$143_Y - connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3476$144_Y - end - attribute \src "ls180.v:3513.127-3513.245" - cell $or $or$ls180.v:3513$157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3513$157_Y - end - attribute \src "ls180.v:3519.57-3519.157" - cell $or $or$ls180.v:3519$163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3519$162_Y - connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:3519$163_Y - end - attribute \src "ls180.v:3624.59-3624.140" - cell $or $or$ls180.v:3624$169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_req_wdata_ready - connect \B \main_sdram_bankmachine3_req_rdata_valid - connect \Y $or$ls180.v:3624$169_Y - end - attribute \src "ls180.v:3625.44-3625.151" - cell $or $or$ls180.v:3625$170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $or$ls180.v:3625$170_Y - end - attribute \src "ls180.v:3633.45-3633.170" - cell $or $or$ls180.v:3633$174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3633$173_Y - connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3633$174_Y - end - attribute \src "ls180.v:3670.127-3670.245" - cell $or $or$ls180.v:3670$187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3670$187_Y - end - attribute \src "ls180.v:3676.57-3676.157" - cell $or $or$ls180.v:3676$193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3676$192_Y - connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:3676$193_Y - end - attribute \src "ls180.v:3775.107-3775.193" - cell $or $or$ls180.v:3775$213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_is_write - connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $or$ls180.v:3775$213_Y - end - attribute \src "ls180.v:3778.39-3778.204" - cell $or $or$ls180.v:3778$219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3778$217_Y - connect \B $and$ls180.v:3778$218_Y - connect \Y $or$ls180.v:3778$219_Y - end - attribute \src "ls180.v:3778.38-3778.289" - cell $or $or$ls180.v:3778$221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3778$219_Y - connect \B $and$ls180.v:3778$220_Y - connect \Y $or$ls180.v:3778$221_Y - end - attribute \src "ls180.v:3778.37-3778.374" - cell $or $or$ls180.v:3778$223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3778$221_Y - connect \B $and$ls180.v:3778$222_Y - connect \Y $or$ls180.v:3778$223_Y - end - attribute \src "ls180.v:3779.40-3779.207" - cell $or $or$ls180.v:3779$226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3779$224_Y - connect \B $and$ls180.v:3779$225_Y - connect \Y $or$ls180.v:3779$226_Y - end - attribute \src "ls180.v:3779.39-3779.293" - cell $or $or$ls180.v:3779$228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3779$226_Y - connect \B $and$ls180.v:3779$227_Y - connect \Y $or$ls180.v:3779$228_Y - end - attribute \src "ls180.v:3779.38-3779.379" - cell $or $or$ls180.v:3779$230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3779$228_Y - connect \B $and$ls180.v:3779$229_Y - connect \Y $or$ls180.v:3779$230_Y - end - attribute \src "ls180.v:3792.158-3792.332" - cell $or $or$ls180.v:3792$244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3792$243_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3792$244_Y - end - attribute \src "ls180.v:3792.75-3792.506" - cell $or $or$ls180.v:3792$249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3792$245_Y - connect \B $and$ls180.v:3792$248_Y - connect \Y $or$ls180.v:3792$249_Y - end - attribute \src "ls180.v:3793.158-3793.332" - cell $or $or$ls180.v:3793$257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3793$256_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3793$257_Y - end - attribute \src "ls180.v:3793.75-3793.506" - cell $or $or$ls180.v:3793$262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3793$258_Y - connect \B $and$ls180.v:3793$261_Y - connect \Y $or$ls180.v:3793$262_Y - end - attribute \src "ls180.v:3794.158-3794.332" - cell $or $or$ls180.v:3794$270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3794$269_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3794$270_Y - end - attribute \src "ls180.v:3794.75-3794.506" - cell $or $or$ls180.v:3794$275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3794$271_Y - connect \B $and$ls180.v:3794$274_Y - connect \Y $or$ls180.v:3794$275_Y - end - attribute \src "ls180.v:3795.158-3795.332" - cell $or $or$ls180.v:3795$283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3795$282_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3795$283_Y - end - attribute \src "ls180.v:3795.75-3795.506" - cell $or $or$ls180.v:3795$288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3795$284_Y - connect \B $and$ls180.v:3795$287_Y - connect \Y $or$ls180.v:3795$288_Y - end - attribute \src "ls180.v:3822.36-3822.104" - cell $or $or$ls180.v:3822$294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_ready - connect \B $not$ls180.v:3822$293_Y - connect \Y $or$ls180.v:3822$294_Y - end - attribute \src "ls180.v:3825.158-3825.332" - cell $or $or$ls180.v:3825$302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3825$301_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3825$302_Y - end - attribute \src "ls180.v:3825.75-3825.506" - cell $or $or$ls180.v:3825$307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3825$303_Y - connect \B $and$ls180.v:3825$306_Y - connect \Y $or$ls180.v:3825$307_Y - end - attribute \src "ls180.v:3826.158-3826.332" - cell $or $or$ls180.v:3826$315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3826$314_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3826$315_Y - end - attribute \src "ls180.v:3826.75-3826.506" - cell $or $or$ls180.v:3826$320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3826$316_Y - connect \B $and$ls180.v:3826$319_Y - connect \Y $or$ls180.v:3826$320_Y - end - attribute \src "ls180.v:3827.158-3827.332" - cell $or $or$ls180.v:3827$328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3827$327_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3827$328_Y - end - attribute \src "ls180.v:3827.75-3827.506" - cell $or $or$ls180.v:3827$333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3827$329_Y - connect \B $and$ls180.v:3827$332_Y - connect \Y $or$ls180.v:3827$333_Y - end - attribute \src "ls180.v:3828.158-3828.332" - cell $or $or$ls180.v:3828$341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3828$340_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3828$341_Y - end - attribute \src "ls180.v:3828.75-3828.506" - cell $or $or$ls180.v:3828$346 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3828$342_Y - connect \B $and$ls180.v:3828$345_Y - connect \Y $or$ls180.v:3828$346_Y - end - attribute \src "ls180.v:3891.36-3891.104" - cell $or $or$ls180.v:3891$380 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_ready - connect \B $not$ls180.v:3891$379_Y - connect \Y $or$ls180.v:3891$380_Y - end - attribute \src "ls180.v:3912.67-3912.221" - cell $or $or$ls180.v:3912$387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3912$386_Y - connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:3912$387_Y - end - attribute \src "ls180.v:3920.10-3920.62" - cell $or $or$ls180.v:3920$390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3920$389_Y - connect \B \main_sdram_max_time1 - connect \Y $or$ls180.v:3920$390_Y - end - attribute \src "ls180.v:3950.67-3950.221" - cell $or $or$ls180.v:3950$396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3950$395_Y - connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:3950$396_Y - end - attribute \src "ls180.v:3958.10-3958.61" - cell $or $or$ls180.v:3958$399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3958$398_Y - connect \B \main_sdram_max_time0 - connect \Y $or$ls180.v:3958$399_Y - end - attribute \src "ls180.v:3968.91-3968.180" - cell $or $or$ls180.v:3968$403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked0 - connect \B $and$ls180.v:3968$402_Y - connect \Y $or$ls180.v:3968$403_Y - end - attribute \src "ls180.v:3968.90-3968.255" - cell $or $or$ls180.v:3968$406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3968$403_Y - connect \B $and$ls180.v:3968$405_Y - connect \Y $or$ls180.v:3968$406_Y - end - attribute \src "ls180.v:3968.89-3968.330" - cell $or $or$ls180.v:3968$409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3968$406_Y - connect \B $and$ls180.v:3968$408_Y - connect \Y $or$ls180.v:3968$409_Y - end - attribute \src "ls180.v:3973.91-3973.180" - cell $or $or$ls180.v:3973$419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked1 - connect \B $and$ls180.v:3973$418_Y - connect \Y $or$ls180.v:3973$419_Y - end - attribute \src "ls180.v:3973.90-3973.255" - cell $or $or$ls180.v:3973$422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3973$419_Y - connect \B $and$ls180.v:3973$421_Y - connect \Y $or$ls180.v:3973$422_Y - end - attribute \src "ls180.v:3973.89-3973.330" - cell $or $or$ls180.v:3973$425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3973$422_Y - connect \B $and$ls180.v:3973$424_Y - connect \Y $or$ls180.v:3973$425_Y - end - attribute \src "ls180.v:3978.91-3978.180" - cell $or $or$ls180.v:3978$435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked2 - connect \B $and$ls180.v:3978$434_Y - connect \Y $or$ls180.v:3978$435_Y - end - attribute \src "ls180.v:3978.90-3978.255" - cell $or $or$ls180.v:3978$438 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3978$435_Y - connect \B $and$ls180.v:3978$437_Y - connect \Y $or$ls180.v:3978$438_Y - end - attribute \src "ls180.v:3978.89-3978.330" - cell $or $or$ls180.v:3978$441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3978$438_Y - connect \B $and$ls180.v:3978$440_Y - connect \Y $or$ls180.v:3978$441_Y - end - attribute \src "ls180.v:3983.91-3983.180" - cell $or $or$ls180.v:3983$451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked3 - connect \B $and$ls180.v:3983$450_Y - connect \Y $or$ls180.v:3983$451_Y - end - attribute \src "ls180.v:3983.90-3983.255" - cell $or $or$ls180.v:3983$454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3983$451_Y - connect \B $and$ls180.v:3983$453_Y - connect \Y $or$ls180.v:3983$454_Y - end - attribute \src "ls180.v:3983.89-3983.330" - cell $or $or$ls180.v:3983$457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3983$454_Y - connect \B $and$ls180.v:3983$456_Y - connect \Y $or$ls180.v:3983$457_Y - end - attribute \src "ls180.v:3988.132-3988.221" - cell $or $or$ls180.v:3988$468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked0 - connect \B $and$ls180.v:3988$467_Y - connect \Y $or$ls180.v:3988$468_Y - end - attribute \src "ls180.v:3988.131-3988.296" - cell $or $or$ls180.v:3988$471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3988$468_Y - connect \B $and$ls180.v:3988$470_Y - connect \Y $or$ls180.v:3988$471_Y - end - attribute \src "ls180.v:3988.130-3988.371" - cell $or $or$ls180.v:3988$474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3988$471_Y - connect \B $and$ls180.v:3988$473_Y - connect \Y $or$ls180.v:3988$474_Y - end - attribute \src "ls180.v:3988.34-3988.411" - cell $or $or$ls180.v:3988$479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B $and$ls180.v:3988$478_Y - connect \Y $or$ls180.v:3988$479_Y - end - attribute \src "ls180.v:3988.506-3988.595" - cell $or $or$ls180.v:3988$484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked1 - connect \B $and$ls180.v:3988$483_Y - connect \Y $or$ls180.v:3988$484_Y - end - attribute \src "ls180.v:3988.505-3988.670" - cell $or $or$ls180.v:3988$487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3988$484_Y - connect \B $and$ls180.v:3988$486_Y - connect \Y $or$ls180.v:3988$487_Y - end - attribute \src "ls180.v:3988.504-3988.745" - cell $or $or$ls180.v:3988$490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3988$487_Y - connect \B $and$ls180.v:3988$489_Y - connect \Y $or$ls180.v:3988$490_Y - end - attribute \src "ls180.v:3988.33-3988.785" - cell $or $or$ls180.v:3988$495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3988$479_Y - connect \B $and$ls180.v:3988$494_Y - connect \Y $or$ls180.v:3988$495_Y - end - attribute \src "ls180.v:3988.880-3988.969" - cell $or $or$ls180.v:3988$500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked2 - connect \B $and$ls180.v:3988$499_Y - connect \Y $or$ls180.v:3988$500_Y - end - attribute \src "ls180.v:3988.879-3988.1044" - cell $or $or$ls180.v:3988$503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3988$500_Y - connect \B $and$ls180.v:3988$502_Y - connect \Y $or$ls180.v:3988$503_Y - end - attribute \src "ls180.v:3988.878-3988.1119" - cell $or $or$ls180.v:3988$506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3988$503_Y - connect \B $and$ls180.v:3988$505_Y - connect \Y $or$ls180.v:3988$506_Y - end - attribute \src "ls180.v:3988.32-3988.1159" - cell $or $or$ls180.v:3988$511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3988$495_Y - connect \B $and$ls180.v:3988$510_Y - connect \Y $or$ls180.v:3988$511_Y - end - attribute \src "ls180.v:3988.1254-3988.1343" - cell $or $or$ls180.v:3988$516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked3 - connect \B $and$ls180.v:3988$515_Y - connect \Y $or$ls180.v:3988$516_Y - end - attribute \src "ls180.v:3988.1253-3988.1418" - cell $or $or$ls180.v:3988$519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3988$516_Y - connect \B $and$ls180.v:3988$518_Y - connect \Y $or$ls180.v:3988$519_Y - end - attribute \src "ls180.v:3988.1252-3988.1493" - cell $or $or$ls180.v:3988$522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3988$519_Y - connect \B $and$ls180.v:3988$521_Y - connect \Y $or$ls180.v:3988$522_Y - end - attribute \src "ls180.v:3988.31-3988.1533" - cell $or $or$ls180.v:3988$527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3988$511_Y - connect \B $and$ls180.v:3988$526_Y - connect \Y $or$ls180.v:3988$527_Y - end - attribute \src "ls180.v:4051.10-4051.52" - cell $or $or$ls180.v:4051$536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_ack - connect \B \main_converter_skip - connect \Y $or$ls180.v:4051$536_Y - end - attribute \src "ls180.v:4078.35-4078.74" - cell $or $or$ls180.v:4078$546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4078$546_Y - end - attribute \src "ls180.v:4079.34-4079.73" - cell $or $or$ls180.v:4079$550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4079$550_Y - end - attribute \src "ls180.v:4080.48-4080.130" - cell $or $or$ls180.v:4080$556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4080$553_Y - connect \B $and$ls180.v:4080$555_Y - connect \Y $or$ls180.v:4080$556_Y - end - attribute \src "ls180.v:4081.24-4081.87" - cell $or $or$ls180.v:4081$559 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4081$558_Y - connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4081$559_Y - end - attribute \src "ls180.v:4082.26-4082.95" - cell $or $or$ls180.v:4082$561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4082$560_Y - connect \B \main_wdata_consumed - connect \Y $or$ls180.v:4082$561_Y - end - attribute \src "ls180.v:4112.42-4112.89" - cell $or $or$ls180.v:4112$569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_clear - connect \B $and$ls180.v:4112$568_Y - connect \Y $or$ls180.v:4112$569_Y - end - attribute \src "ls180.v:4136.25-4136.174" - cell $or $or$ls180.v:4136$579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4136$577_Y - connect \B $and$ls180.v:4136$578_Y - connect \Y $or$ls180.v:4136$579_Y - end - attribute \src "ls180.v:4151.80-4151.132" - cell $or $or$ls180.v:4151$581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4151$580_Y - connect \B \main_uart_tx_fifo_re - connect \Y $or$ls180.v:4151$581_Y - end - attribute \src "ls180.v:4162.72-4162.135" - cell $or $or$ls180.v:4162$586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_writable - connect \B \main_uart_tx_fifo_replace - connect \Y $or$ls180.v:4162$586_Y - end - attribute \src "ls180.v:4181.80-4181.132" - cell $or $or$ls180.v:4181$592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4181$591_Y - connect \B \main_uart_rx_fifo_re - connect \Y $or$ls180.v:4181$592_Y - end - attribute \src "ls180.v:4192.72-4192.135" - cell $or $or$ls180.v:4192$597 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_writable - connect \B \main_uart_rx_fifo_replace - connect \Y $or$ls180.v:4192$597_Y - end - attribute \src "ls180.v:4267.36-4267.111" - cell $or $or$ls180.v:4267$610 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_pads_out_payload_clk - connect \B \main_sdphy_cmdw_pads_out_payload_clk - connect \Y $or$ls180.v:4267$610_Y - end - attribute \src "ls180.v:4267.35-4267.151" - cell $or $or$ls180.v:4267$611 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4267$610_Y - connect \B \main_sdphy_cmdr_pads_out_payload_clk - connect \Y $or$ls180.v:4267$611_Y - end - attribute \src "ls180.v:4267.34-4267.192" - cell $or $or$ls180.v:4267$612 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4267$611_Y - connect \B \main_sdphy_dataw_pads_out_payload_clk - connect \Y $or$ls180.v:4267$612_Y - end - attribute \src "ls180.v:4267.33-4267.233" - cell $or $or$ls180.v:4267$613 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4267$612_Y - connect \B \main_sdphy_datar_pads_out_payload_clk - connect \Y $or$ls180.v:4267$613_Y - end - attribute \src "ls180.v:4268.39-4268.120" - cell $or $or$ls180.v:4268$614 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_pads_out_payload_cmd_oe - connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4268$614_Y - end - attribute \src "ls180.v:4268.38-4268.163" - cell $or $or$ls180.v:4268$615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4268$614_Y - connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4268$615_Y - end - attribute \src "ls180.v:4268.37-4268.207" - cell $or $or$ls180.v:4268$616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4268$615_Y - connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4268$616_Y - end - attribute \src "ls180.v:4268.36-4268.251" - cell $or $or$ls180.v:4268$617 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4268$616_Y - connect \B \main_sdphy_datar_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4268$617_Y - end - attribute \src "ls180.v:4269.38-4269.117" - cell $or $or$ls180.v:4269$618 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_pads_out_payload_cmd_o - connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4269$618_Y - end - attribute \src "ls180.v:4269.37-4269.159" - cell $or $or$ls180.v:4269$619 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4269$618_Y - connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4269$619_Y - end - attribute \src "ls180.v:4269.36-4269.202" - cell $or $or$ls180.v:4269$620 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4269$619_Y - connect \B \main_sdphy_dataw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4269$620_Y - end - attribute \src "ls180.v:4269.35-4269.245" - cell $or $or$ls180.v:4269$621 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4269$620_Y - connect \B \main_sdphy_datar_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4269$621_Y - end - attribute \src "ls180.v:4270.40-4270.123" - cell $or $or$ls180.v:4270$622 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_pads_out_payload_data_oe - connect \B \main_sdphy_cmdw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4270$622_Y - end - attribute \src "ls180.v:4270.39-4270.167" - cell $or $or$ls180.v:4270$623 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4270$622_Y - connect \B \main_sdphy_cmdr_pads_out_payload_data_oe - connect \Y $or$ls180.v:4270$623_Y - end - attribute \src "ls180.v:4270.38-4270.212" - cell $or $or$ls180.v:4270$624 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4270$623_Y - connect \B \main_sdphy_dataw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4270$624_Y - end - attribute \src "ls180.v:4270.37-4270.257" - cell $or $or$ls180.v:4270$625 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4270$624_Y - connect \B \main_sdphy_datar_pads_out_payload_data_oe - connect \Y $or$ls180.v:4270$625_Y - end - attribute \src "ls180.v:4271.39-4271.120" - cell $or $or$ls180.v:4271$626 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \main_sdphy_init_pads_out_payload_data_o - connect \B \main_sdphy_cmdw_pads_out_payload_data_o - connect \Y $or$ls180.v:4271$626_Y - end - attribute \src "ls180.v:4271.38-4271.163" - cell $or $or$ls180.v:4271$627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4271$626_Y - connect \B \main_sdphy_cmdr_pads_out_payload_data_o - connect \Y $or$ls180.v:4271$627_Y - end - attribute \src "ls180.v:4271.37-4271.207" - cell $or $or$ls180.v:4271$628 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4271$627_Y - connect \B \main_sdphy_dataw_pads_out_payload_data_o - connect \Y $or$ls180.v:4271$628_Y - end - attribute \src "ls180.v:4271.36-4271.251" - cell $or $or$ls180.v:4271$629 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4271$628_Y - connect \B \main_sdphy_datar_pads_out_payload_data_o - connect \Y $or$ls180.v:4271$629_Y - end - attribute \src "ls180.v:4292.35-4292.80" - cell $or $or$ls180.v:4292$630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_stop - connect \B \main_sdphy_datar_stop - connect \Y $or$ls180.v:4292$630_Y - end - attribute \src "ls180.v:4446.91-4446.144" - cell $or $or$ls180.v:4446$644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_start - connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:4446$644_Y - end - attribute \src "ls180.v:4463.53-4463.143" - cell $or $or$ls180.v:4463$647 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4463$646_Y - connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $or$ls180.v:4463$647_Y - end - attribute \src "ls180.v:4466.47-4466.127" - cell $or $or$ls180.v:4466$650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4466$649_Y - connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:4466$650_Y - end - attribute \src "ls180.v:4590.54-4590.146" - cell $or $or$ls180.v:4590$668 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4590$667_Y - connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $or$ls180.v:4590$668_Y - end - attribute \src "ls180.v:4593.48-4593.130" - cell $or $or$ls180.v:4593$671 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4593$670_Y - connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:4593$671_Y - end - attribute \src "ls180.v:4724.55-4724.149" - cell $or $or$ls180.v:4724$683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4724$682_Y - connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $or$ls180.v:4724$683_Y - end - attribute \src "ls180.v:4727.49-4727.133" - cell $or $or$ls180.v:4727$686 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4727$685_Y - connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:4727$686_Y - end - attribute \src "ls180.v:5356.80-5356.151" - cell $or $or$ls180.v:5356$981 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_writable - connect \B \main_sdblock2mem_fifo_replace - connect \Y $or$ls180.v:5356$981_Y - end - attribute \src "ls180.v:5367.49-5367.131" - cell $or $or$ls180.v:5367$987 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:5367$986_Y - connect \B \main_sdblock2mem_converter_source_ready - connect \Y $or$ls180.v:5367$987_Y - end - attribute \src "ls180.v:5564.80-5564.151" - cell $or $or$ls180.v:5564$1012 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_writable - connect \B \main_sdmem2block_fifo_replace - connect \Y $or$ls180.v:5564$1012_Y - end - attribute \src "ls180.v:5738.33-5738.102" - cell $or $or$ls180.v:5738$1060 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_err - connect \B \main_libresocsim_libresoc_xics_icp_err - connect \Y $or$ls180.v:5738$1060_Y - end - attribute \src "ls180.v:5738.32-5738.144" - cell $or $or$ls180.v:5738$1061 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5738$1060_Y - connect \B \main_libresocsim_libresoc_xics_ics_err - connect \Y $or$ls180.v:5738$1061_Y - end - attribute \src "ls180.v:5738.31-5738.165" - cell $or $or$ls180.v:5738$1062 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5738$1061_Y - connect \B \main_wb_sdram_err - connect \Y $or$ls180.v:5738$1062_Y - end - attribute \src "ls180.v:5738.30-5738.201" - cell $or $or$ls180.v:5738$1063 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5738$1062_Y - connect \B \builder_libresocsim_wishbone_err - connect \Y $or$ls180.v:5738$1063_Y - end - attribute \src "ls180.v:5744.28-5744.97" - cell $or $or$ls180.v:5744$1068 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_ack - connect \B \main_libresocsim_libresoc_xics_icp_ack - connect \Y $or$ls180.v:5744$1068_Y - end - attribute \src "ls180.v:5744.27-5744.139" - cell $or $or$ls180.v:5744$1069 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5744$1068_Y - connect \B \main_libresocsim_libresoc_xics_ics_ack - connect \Y $or$ls180.v:5744$1069_Y - end - attribute \src "ls180.v:5744.26-5744.160" - cell $or $or$ls180.v:5744$1070 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5744$1069_Y - connect \B \main_wb_sdram_ack - connect \Y $or$ls180.v:5744$1070_Y - end - attribute \src "ls180.v:5744.25-5744.196" - cell $or $or$ls180.v:5744$1071 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5744$1070_Y - connect \B \builder_libresocsim_wishbone_ack - connect \Y $or$ls180.v:5744$1071_Y - end - attribute \src "ls180.v:5745.30-5745.169" - cell $or $or$ls180.v:5745$1074 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $and$ls180.v:5745$1072_Y - connect \B $and$ls180.v:5745$1073_Y - connect \Y $or$ls180.v:5745$1074_Y - end - attribute \src "ls180.v:5745.29-5745.246" - cell $or $or$ls180.v:5745$1076 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5745$1074_Y - connect \B $and$ls180.v:5745$1075_Y - connect \Y $or$ls180.v:5745$1076_Y - end - attribute \src "ls180.v:5745.28-5745.302" - cell $or $or$ls180.v:5745$1078 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5745$1076_Y - connect \B $and$ls180.v:5745$1077_Y - connect \Y $or$ls180.v:5745$1078_Y - end - attribute \src "ls180.v:5745.27-5745.373" - cell $or $or$ls180.v:5745$1080 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5745$1078_Y - connect \B $and$ls180.v:5745$1079_Y - connect \Y $or$ls180.v:5745$1080_Y - end - attribute \src "ls180.v:6499.55-6499.124" - cell $or $or$ls180.v:6499$2226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A \builder_interface0_bank_bus_dat_r - connect \B \builder_interface1_bank_bus_dat_r - connect \Y $or$ls180.v:6499$2226_Y - end - attribute \src "ls180.v:6499.54-6499.161" - cell $or $or$ls180.v:6499$2227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6499$2226_Y - connect \B \builder_interface2_bank_bus_dat_r - connect \Y $or$ls180.v:6499$2227_Y - end - attribute \src "ls180.v:6499.53-6499.198" - cell $or $or$ls180.v:6499$2228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6499$2227_Y - connect \B \builder_interface3_bank_bus_dat_r - connect \Y $or$ls180.v:6499$2228_Y - end - attribute \src "ls180.v:6499.52-6499.235" - cell $or $or$ls180.v:6499$2229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6499$2228_Y - connect \B \builder_interface4_bank_bus_dat_r - connect \Y $or$ls180.v:6499$2229_Y - end - attribute \src "ls180.v:6499.51-6499.272" - cell $or $or$ls180.v:6499$2230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6499$2229_Y - connect \B \builder_interface5_bank_bus_dat_r - connect \Y $or$ls180.v:6499$2230_Y - end - attribute \src "ls180.v:6499.50-6499.309" - cell $or $or$ls180.v:6499$2231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6499$2230_Y - connect \B \builder_interface6_bank_bus_dat_r - connect \Y $or$ls180.v:6499$2231_Y - end - attribute \src "ls180.v:6499.49-6499.346" - cell $or $or$ls180.v:6499$2232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6499$2231_Y - connect \B \builder_interface7_bank_bus_dat_r - connect \Y $or$ls180.v:6499$2232_Y - end - attribute \src "ls180.v:6499.48-6499.383" - cell $or $or$ls180.v:6499$2233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6499$2232_Y - connect \B \builder_interface8_bank_bus_dat_r - connect \Y $or$ls180.v:6499$2233_Y - end - attribute \src "ls180.v:6499.47-6499.420" - cell $or $or$ls180.v:6499$2234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6499$2233_Y - connect \B \builder_interface9_bank_bus_dat_r - connect \Y $or$ls180.v:6499$2234_Y - end - attribute \src "ls180.v:6499.46-6499.458" - cell $or $or$ls180.v:6499$2235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6499$2234_Y - connect \B \builder_interface10_bank_bus_dat_r - connect \Y $or$ls180.v:6499$2235_Y - end - attribute \src "ls180.v:6499.45-6499.496" - cell $or $or$ls180.v:6499$2236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6499$2235_Y - connect \B \builder_interface11_bank_bus_dat_r - connect \Y $or$ls180.v:6499$2236_Y - end - attribute \src "ls180.v:6499.44-6499.534" - cell $or $or$ls180.v:6499$2237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6499$2236_Y - connect \B \builder_interface12_bank_bus_dat_r - connect \Y $or$ls180.v:6499$2237_Y - end - attribute \src "ls180.v:6499.43-6499.572" - cell $or $or$ls180.v:6499$2238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6499$2237_Y - connect \B \builder_interface13_bank_bus_dat_r - connect \Y $or$ls180.v:6499$2238_Y - end - attribute \src "ls180.v:6499.42-6499.610" - cell $or $or$ls180.v:6499$2239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6499$2238_Y - connect \B \builder_interface14_bank_bus_dat_r - connect \Y $or$ls180.v:6499$2239_Y - end - attribute \src "ls180.v:6826.90-6826.179" - cell $or $or$ls180.v:6826$2264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked0 - connect \B $and$ls180.v:6826$2263_Y - connect \Y $or$ls180.v:6826$2264_Y - end - attribute \src "ls180.v:6826.89-6826.254" - cell $or $or$ls180.v:6826$2267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6826$2264_Y - connect \B $and$ls180.v:6826$2266_Y - connect \Y $or$ls180.v:6826$2267_Y - end - attribute \src "ls180.v:6826.88-6826.329" - cell $or $or$ls180.v:6826$2270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6826$2267_Y - connect \B $and$ls180.v:6826$2269_Y - connect \Y $or$ls180.v:6826$2270_Y - end - attribute \src "ls180.v:6850.90-6850.179" - cell $or $or$ls180.v:6850$2280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked1 - connect \B $and$ls180.v:6850$2279_Y - connect \Y $or$ls180.v:6850$2280_Y - end - attribute \src "ls180.v:6850.89-6850.254" - cell $or $or$ls180.v:6850$2283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6850$2280_Y - connect \B $and$ls180.v:6850$2282_Y - connect \Y $or$ls180.v:6850$2283_Y - end - attribute \src "ls180.v:6850.88-6850.329" - cell $or $or$ls180.v:6850$2286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6850$2283_Y - connect \B $and$ls180.v:6850$2285_Y - connect \Y $or$ls180.v:6850$2286_Y - end - attribute \src "ls180.v:6874.90-6874.179" - cell $or $or$ls180.v:6874$2296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked2 - connect \B $and$ls180.v:6874$2295_Y - connect \Y $or$ls180.v:6874$2296_Y - end - attribute \src "ls180.v:6874.89-6874.254" - cell $or $or$ls180.v:6874$2299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6874$2296_Y - connect \B $and$ls180.v:6874$2298_Y - connect \Y $or$ls180.v:6874$2299_Y - end - attribute \src "ls180.v:6874.88-6874.329" - cell $or $or$ls180.v:6874$2302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6874$2299_Y - connect \B $and$ls180.v:6874$2301_Y - connect \Y $or$ls180.v:6874$2302_Y - end - attribute \src "ls180.v:6898.90-6898.179" - cell $or $or$ls180.v:6898$2312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked3 - connect \B $and$ls180.v:6898$2311_Y - connect \Y $or$ls180.v:6898$2312_Y - end - attribute \src "ls180.v:6898.89-6898.254" - cell $or $or$ls180.v:6898$2315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6898$2312_Y - connect \B $and$ls180.v:6898$2314_Y - connect \Y $or$ls180.v:6898$2315_Y - end - attribute \src "ls180.v:6898.88-6898.329" - cell $or $or$ls180.v:6898$2318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6898$2315_Y - connect \B $and$ls180.v:6898$2317_Y - connect \Y $or$ls180.v:6898$2318_Y - end - attribute \src "ls180.v:7412.20-7412.71" - cell $or $or$ls180.v:7412$2375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [0] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7412$2375_Y - end - attribute \src "ls180.v:7413.20-7413.71" - cell $or $or$ls180.v:7413$2376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [1] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7413$2376_Y - end - attribute \src "ls180.v:7414.20-7414.71" - cell $or $or$ls180.v:7414$2377 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [2] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7414$2377_Y - end - attribute \src "ls180.v:7415.20-7415.71" - cell $or $or$ls180.v:7415$2378 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [3] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7415$2378_Y - end - attribute \src "ls180.v:7416.20-7416.71" - cell $or $or$ls180.v:7416$2379 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [4] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7416$2379_Y - end - attribute \src "ls180.v:7417.20-7417.71" - cell $or $or$ls180.v:7417$2380 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [5] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7417$2380_Y - end - attribute \src "ls180.v:7418.20-7418.71" - cell $or $or$ls180.v:7418$2381 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [6] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7418$2381_Y - end - attribute \src "ls180.v:7419.20-7419.71" - cell $or $or$ls180.v:7419$2382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [7] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7419$2382_Y - end - attribute \src "ls180.v:7420.20-7420.71" - cell $or $or$ls180.v:7420$2383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [8] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7420$2383_Y - end - attribute \src "ls180.v:7421.20-7421.71" - cell $or $or$ls180.v:7421$2384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [9] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7421$2384_Y - end - attribute \src "ls180.v:7422.21-7422.73" - cell $or $or$ls180.v:7422$2385 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [10] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7422$2385_Y - end - attribute \src "ls180.v:7423.21-7423.73" - cell $or $or$ls180.v:7423$2386 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [11] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7423$2386_Y - end - attribute \src "ls180.v:7424.21-7424.73" - cell $or $or$ls180.v:7424$2387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [12] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7424$2387_Y - end - attribute \src "ls180.v:7425.21-7425.73" - cell $or $or$ls180.v:7425$2388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [13] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7425$2388_Y - end - attribute \src "ls180.v:7426.21-7426.73" - cell $or $or$ls180.v:7426$2389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [14] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7426$2389_Y - end - attribute \src "ls180.v:7427.21-7427.73" - cell $or $or$ls180.v:7427$2390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [15] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7427$2390_Y - end - attribute \src "ls180.v:7428.21-7428.73" - cell $or $or$ls180.v:7428$2391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [16] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7428$2391_Y - end - attribute \src "ls180.v:7429.21-7429.73" - cell $or $or$ls180.v:7429$2392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [17] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7429$2392_Y - end - attribute \src "ls180.v:7430.21-7430.73" - cell $or $or$ls180.v:7430$2393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [18] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7430$2393_Y - end - attribute \src "ls180.v:7431.21-7431.73" - cell $or $or$ls180.v:7431$2394 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [19] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7431$2394_Y - end - attribute \src "ls180.v:7432.21-7432.73" - cell $or $or$ls180.v:7432$2395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [20] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7432$2395_Y - end - attribute \src "ls180.v:7433.21-7433.73" - cell $or $or$ls180.v:7433$2396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [21] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7433$2396_Y - end - attribute \src "ls180.v:7434.21-7434.73" - cell $or $or$ls180.v:7434$2397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [22] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7434$2397_Y - end - attribute \src "ls180.v:7435.21-7435.73" - cell $or $or$ls180.v:7435$2398 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [23] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7435$2398_Y - end - attribute \src "ls180.v:7436.21-7436.73" - cell $or $or$ls180.v:7436$2399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [24] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7436$2399_Y - end - attribute \src "ls180.v:7437.21-7437.73" - cell $or $or$ls180.v:7437$2400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [25] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7437$2400_Y - end - attribute \src "ls180.v:7438.21-7438.73" - cell $or $or$ls180.v:7438$2401 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [26] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7438$2401_Y - end - attribute \src "ls180.v:7439.21-7439.73" - cell $or $or$ls180.v:7439$2402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [27] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7439$2402_Y - end - attribute \src "ls180.v:7440.21-7440.73" - cell $or $or$ls180.v:7440$2403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [28] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7440$2403_Y - end - attribute \src "ls180.v:7441.21-7441.73" - cell $or $or$ls180.v:7441$2404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [29] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7441$2404_Y - end - attribute \src "ls180.v:7442.21-7442.73" - cell $or $or$ls180.v:7442$2405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [30] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7442$2405_Y - end - attribute \src "ls180.v:7443.21-7443.73" - cell $or $or$ls180.v:7443$2406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [31] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7443$2406_Y - end - attribute \src "ls180.v:7444.21-7444.73" - cell $or $or$ls180.v:7444$2407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [32] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7444$2407_Y - end - attribute \src "ls180.v:7445.21-7445.73" - cell $or $or$ls180.v:7445$2408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [33] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7445$2408_Y - end - attribute \src "ls180.v:7446.21-7446.73" - cell $or $or$ls180.v:7446$2409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [34] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7446$2409_Y - end - attribute \src "ls180.v:7447.21-7447.73" - cell $or $or$ls180.v:7447$2410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [35] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7447$2410_Y - end - attribute \src "ls180.v:7448.7-7448.93" - cell $or $or$ls180.v:7448$2411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface0_converted_interface_ack - connect \B \main_libresocsim_converter0_skip - connect \Y $or$ls180.v:7448$2411_Y - end - attribute \src "ls180.v:7459.7-7459.93" - cell $or $or$ls180.v:7459$2412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface1_converted_interface_ack - connect \B \main_libresocsim_converter1_skip - connect \Y $or$ls180.v:7459$2412_Y - end - attribute \src "ls180.v:7470.7-7470.93" - cell $or $or$ls180.v:7470$2413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface2_converted_interface_ack - connect \B \main_libresocsim_converter2_skip - connect \Y $or$ls180.v:7470$2413_Y - end - attribute \src "ls180.v:7599.7-7599.107" - cell $or $or$ls180.v:7599$2449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7599$2448_Y - connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:7599$2449_Y - end - attribute \src "ls180.v:7645.7-7645.107" - cell $or $or$ls180.v:7645$2465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7645$2464_Y - connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:7645$2465_Y - end - attribute \src "ls180.v:7691.7-7691.107" - cell $or $or$ls180.v:7691$2481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7691$2480_Y - connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:7691$2481_Y - end - attribute \src "ls180.v:7737.7-7737.107" - cell $or $or$ls180.v:7737$2497 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7737$2496_Y - connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:7737$2497_Y - end - attribute \src "ls180.v:7925.40-7925.125" - cell $or $or$ls180.v:7925$2518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B $and$ls180.v:7925$2517_Y - connect \Y $or$ls180.v:7925$2518_Y - end - attribute \src "ls180.v:7925.39-7925.207" - cell $or $or$ls180.v:7925$2521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7925$2518_Y - connect \B $and$ls180.v:7925$2520_Y - connect \Y $or$ls180.v:7925$2521_Y - end - attribute \src "ls180.v:7925.38-7925.289" - cell $or $or$ls180.v:7925$2524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7925$2521_Y - connect \B $and$ls180.v:7925$2523_Y - connect \Y $or$ls180.v:7925$2524_Y - end - attribute \src "ls180.v:7925.37-7925.371" - cell $or $or$ls180.v:7925$2527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7925$2524_Y - connect \B $and$ls180.v:7925$2526_Y - connect \Y $or$ls180.v:7925$2527_Y - end - attribute \src "ls180.v:7926.41-7926.126" - cell $or $or$ls180.v:7926$2530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B $and$ls180.v:7926$2529_Y - connect \Y $or$ls180.v:7926$2530_Y - end - attribute \src "ls180.v:7926.40-7926.208" - cell $or $or$ls180.v:7926$2533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7926$2530_Y - connect \B $and$ls180.v:7926$2532_Y - connect \Y $or$ls180.v:7926$2533_Y - end - attribute \src "ls180.v:7926.39-7926.290" - cell $or $or$ls180.v:7926$2536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7926$2533_Y - connect \B $and$ls180.v:7926$2535_Y - connect \Y $or$ls180.v:7926$2536_Y - end - attribute \src "ls180.v:7926.38-7926.372" - cell $or $or$ls180.v:7926$2539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7926$2536_Y - connect \B $and$ls180.v:7926$2538_Y - connect \Y $or$ls180.v:7926$2539_Y - end - attribute \src "ls180.v:7930.7-7930.49" - cell $or $or$ls180.v:7930$2540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_ack - connect \B \main_converter_skip - connect \Y $or$ls180.v:7930$2540_Y - end - attribute \src "ls180.v:8093.22-8093.74" - cell $or $or$ls180.v:8093$2588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8093$2586_Y - connect \B $not$ls180.v:8093$2587_Y - connect \Y $or$ls180.v:8093$2588_Y - end - attribute \src "ls180.v:8161.32-8161.85" - cell $or $or$ls180.v:8161$2600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_start - connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:8161$2600_Y - end - attribute \src "ls180.v:8167.8-8167.97" - cell $or $or$ls180.v:8167$2602 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8167$2601_Y - connect \B \main_sdphy_cmdr_cmdr_converter_sink_last - connect \Y $or$ls180.v:8167$2602_Y - end - attribute \src "ls180.v:8184.52-8184.139" - cell $or $or$ls180.v:8184$2607 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_first - connect \B \main_sdphy_cmdr_cmdr_converter_source_first - connect \Y $or$ls180.v:8184$2607_Y - end - attribute \src "ls180.v:8185.51-8185.136" - cell $or $or$ls180.v:8185$2608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_last - connect \B \main_sdphy_cmdr_cmdr_converter_source_last - connect \Y $or$ls180.v:8185$2608_Y - end - attribute \src "ls180.v:8219.7-8219.87" - cell $or $or$ls180.v:8219$2611 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8219$2610_Y - connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:8219$2611_Y - end - attribute \src "ls180.v:8242.33-8242.88" - cell $or $or$ls180.v:8242$2612 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_start - connect \B \main_sdphy_dataw_crcr_run - connect \Y $or$ls180.v:8242$2612_Y - end - attribute \src "ls180.v:8248.8-8248.99" - cell $or $or$ls180.v:8248$2614 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8248$2613_Y - connect \B \main_sdphy_dataw_crcr_converter_sink_last - connect \Y $or$ls180.v:8248$2614_Y - end - attribute \src "ls180.v:8265.53-8265.142" - cell $or $or$ls180.v:8265$2619 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_first - connect \B \main_sdphy_dataw_crcr_converter_source_first - connect \Y $or$ls180.v:8265$2619_Y - end - attribute \src "ls180.v:8266.52-8266.139" - cell $or $or$ls180.v:8266$2620 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_last - connect \B \main_sdphy_dataw_crcr_converter_source_last - connect \Y $or$ls180.v:8266$2620_Y - end - attribute \src "ls180.v:8300.7-8300.89" - cell $or $or$ls180.v:8300$2623 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8300$2622_Y - connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:8300$2623_Y - end - attribute \src "ls180.v:8321.34-8321.91" - cell $or $or$ls180.v:8321$2624 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_start - connect \B \main_sdphy_datar_datar_run - connect \Y $or$ls180.v:8321$2624_Y - end - attribute \src "ls180.v:8327.8-8327.101" - cell $or $or$ls180.v:8327$2626 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8327$2625_Y - connect \B \main_sdphy_datar_datar_converter_sink_last - connect \Y $or$ls180.v:8327$2626_Y - end - attribute \src "ls180.v:8344.54-8344.145" - cell $or $or$ls180.v:8344$2631 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_first - connect \B \main_sdphy_datar_datar_converter_source_first - connect \Y $or$ls180.v:8344$2631_Y - end - attribute \src "ls180.v:8345.53-8345.142" - cell $or $or$ls180.v:8345$2632 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_last - connect \B \main_sdphy_datar_datar_converter_source_last - connect \Y $or$ls180.v:8345$2632_Y - end - attribute \src "ls180.v:8361.7-8361.91" - cell $or $or$ls180.v:8361$2635 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8361$2634_Y - connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:8361$2635_Y - end - attribute \src "ls180.v:8550.8-8550.89" - cell $or $or$ls180.v:8550$2659 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8550$2658_Y - connect \B \main_sdblock2mem_converter_sink_last - connect \Y $or$ls180.v:8550$2659_Y - end - attribute \src "ls180.v:8567.48-8567.127" - cell $or $or$ls180.v:8567$2664 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_first - connect \B \main_sdblock2mem_converter_source_first - connect \Y $or$ls180.v:8567$2664_Y - end - attribute \src "ls180.v:8568.47-8568.124" - cell $or $or$ls180.v:8568$2665 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_last - connect \B \main_sdblock2mem_converter_source_last - connect \Y $or$ls180.v:8568$2665_Y - end - attribute \src "ls180.v:8641.21-8641.65" - cell $or $or$ls180.v:8641$2683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8641$2681_Y - connect \B $not$ls180.v:8641$2682_Y - connect \Y $or$ls180.v:8641$2683_Y - end - attribute \src "ls180.v:3162.46-3162.94" - cell $sshl $sshl$ls180.v:3162$83 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine0_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3162$83_Y - end - attribute \src "ls180.v:3319.46-3319.94" - cell $sshl $sshl$ls180.v:3319$113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine1_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3319$113_Y - end - attribute \src "ls180.v:3476.46-3476.94" - cell $sshl $sshl$ls180.v:3476$143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine2_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3476$143_Y - end - attribute \src "ls180.v:3633.46-3633.94" - cell $sshl $sshl$ls180.v:3633$173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine3_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3633$173_Y - end - attribute \src "ls180.v:3193.63-3193.122" - cell $sub $sub$ls180.v:3193$96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3193$96_Y - end - attribute \src "ls180.v:3350.63-3350.122" - cell $sub $sub$ls180.v:3350$126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3350$126_Y - end - attribute \src "ls180.v:3507.63-3507.122" - cell $sub $sub$ls180.v:3507$156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3507$156_Y - end - attribute \src "ls180.v:3664.63-3664.122" - cell $sub $sub$ls180.v:3664$186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3664$186_Y - end - attribute \src "ls180.v:4070.38-4070.75" - cell $sub $sub$ls180.v:4070$540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 30 - parameter \B_SIGNED 0 - parameter \B_WIDTH 31 - parameter \Y_WIDTH 31 - connect \A \main_litedram_wb_adr - connect \B 31'1001000000000000000000000000000 - connect \Y $sub$ls180.v:4070$540_Y - end - attribute \src "ls180.v:4156.36-4156.68" - cell $sub $sub$ls180.v:4156$585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_tx_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:4156$585_Y - end - attribute \src "ls180.v:4186.36-4186.68" - cell $sub $sub$ls180.v:4186$596 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_rx_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:4186$596_Y - end - attribute \src "ls180.v:4211.69-4211.110" - cell $sub $sub$ls180.v:4211$602 - parameter \A_SIGNED 0 - parameter \A_WIDTH 15 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spi_master_clk_divider0 [15:1] - connect \B 1'1 - connect \Y $sub$ls180.v:4211$602_Y - end - attribute \src "ls180.v:4212.69-4212.104" - cell $sub $sub$ls180.v:4212$604 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spi_master_clk_divider0 - connect \B 1'1 - connect \Y $sub$ls180.v:4212$604_Y - end - attribute \src "ls180.v:4239.36-4239.66" - cell $sub $sub$ls180.v:4239$608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_spi_master_length0 - connect \B 1'1 - connect \Y $sub$ls180.v:4239$608_Y - end - attribute \src "ls180.v:4493.60-4493.90" - cell $sub $sub$ls180.v:4493$652 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_cmdr_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4493$652_Y - end - attribute \src "ls180.v:4504.62-4504.104" - cell $sub $sub$ls180.v:4504$654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdr_sink_payload_length - connect \B 1'1 - connect \Y $sub$ls180.v:4504$654_Y - end - attribute \src "ls180.v:4521.60-4521.90" - cell $sub $sub$ls180.v:4521$658 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_cmdr_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4521$658_Y - end - attribute \src "ls180.v:4750.62-4750.93" - cell $sub $sub$ls180.v:4750$688 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_datar_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4750$688_Y - end - attribute \src "ls180.v:4755.62-4755.93" - cell $sub $sub$ls180.v:4755$689 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_datar_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4755$689_Y - end - attribute \src "ls180.v:4766.64-4766.122" - cell $sub $sub$ls180.v:4766$692 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A $add$ls180.v:4766$691_Y - connect \B 1'1 - connect \Y $sub$ls180.v:4766$692_Y - end - attribute \src "ls180.v:4787.62-4787.93" - cell $sub $sub$ls180.v:4787$695 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_datar_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4787$695_Y - end - attribute \src "ls180.v:5249.37-5249.75" - cell $sub $sub$ls180.v:5249$968 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_block_count_storage - connect \B 1'1 - connect \Y $sub$ls180.v:5249$968_Y - end - attribute \src "ls180.v:5264.62-5264.100" - cell $sub $sub$ls180.v:5264$971 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_block_count_storage - connect \B 1'1 - connect \Y $sub$ls180.v:5264$971_Y - end - attribute \src "ls180.v:5275.39-5275.77" - cell $sub $sub$ls180.v:5275$976 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_block_count_storage - connect \B 1'1 - connect \Y $sub$ls180.v:5275$976_Y - end - attribute \src "ls180.v:5350.40-5350.76" - cell $sub $sub$ls180.v:5350$980 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdblock2mem_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:5350$980_Y - end - attribute \src "ls180.v:5399.56-5399.104" - cell $sub $sub$ls180.v:5399$994 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdblock2mem_wishbonedmawriter_length - connect \B 1'1 - connect \Y $sub$ls180.v:5399$994_Y - end - attribute \src "ls180.v:5489.71-5489.105" - cell $sub $sub$ls180.v:5489$1000 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdmem2block_dma_length - connect \B 1'1 - connect \Y $sub$ls180.v:5489$1000_Y - end - attribute \src "ls180.v:5558.40-5558.76" - cell $sub $sub$ls180.v:5558$1011 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdmem2block_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:5558$1011_Y - end - attribute \src "ls180.v:5577.61-5577.98" - cell $sub $sub$ls180.v:5577$1017 - parameter \A_SIGNED 0 - parameter \A_WIDTH 15 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \libresocsim_clk_divider0 [15:1] - connect \B 1'1 - connect \Y $sub$ls180.v:5577$1017_Y - end - attribute \src "ls180.v:5578.61-5578.92" - cell $sub $sub$ls180.v:5578$1019 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \libresocsim_clk_divider0 - connect \B 1'1 - connect \Y $sub$ls180.v:5578$1019_Y - end - attribute \src "ls180.v:5606.32-5606.58" - cell $sub $sub$ls180.v:5606$1023 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \libresocsim_length0 - connect \B 1'1 - connect \Y $sub$ls180.v:5606$1023_Y - end - attribute \src "ls180.v:7494.31-7494.60" - cell $sub $sub$ls180.v:7494$2420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_libresocsim_value - connect \B 1'1 - connect \Y $sub$ls180.v:7494$2420_Y - end - attribute \src "ls180.v:7515.31-7515.61" - cell $sub $sub$ls180.v:7515$2425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A \main_sdram_timer_count1 - connect \B 1'1 - connect \Y $sub$ls180.v:7515$2425_Y - end - attribute \src "ls180.v:7521.34-7521.67" - cell $sub $sub$ls180.v:7521$2426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_postponer_count - connect \B 1'1 - connect \Y $sub$ls180.v:7521$2426_Y - end - attribute \src "ls180.v:7532.36-7532.69" - cell $sub $sub$ls180.v:7532$2429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'1 - connect \Y $sub$ls180.v:7532$2429_Y - end - attribute \src "ls180.v:7596.59-7596.116" - cell $sub $sub$ls180.v:7596$2447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7596$2447_Y - end - attribute \src "ls180.v:7615.46-7615.90" - cell $sub $sub$ls180.v:7615$2451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7615$2451_Y - end - attribute \src "ls180.v:7642.59-7642.116" - cell $sub $sub$ls180.v:7642$2463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7642$2463_Y - end - attribute \src "ls180.v:7661.46-7661.90" - cell $sub $sub$ls180.v:7661$2467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7661$2467_Y - end - attribute \src "ls180.v:7688.59-7688.116" - cell $sub $sub$ls180.v:7688$2479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7688$2479_Y - end - attribute \src "ls180.v:7707.46-7707.90" - cell $sub $sub$ls180.v:7707$2483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7707$2483_Y - end - attribute \src "ls180.v:7734.59-7734.116" - cell $sub $sub$ls180.v:7734$2495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7734$2495_Y - end - attribute \src "ls180.v:7753.46-7753.90" - cell $sub $sub$ls180.v:7753$2499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7753$2499_Y - end - attribute \src "ls180.v:7764.25-7764.48" - cell $sub $sub$ls180.v:7764$2503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdram_time0 - connect \B 1'1 - connect \Y $sub$ls180.v:7764$2503_Y - end - attribute \src "ls180.v:7771.25-7771.48" - cell $sub $sub$ls180.v:7771$2506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_time1 - connect \B 1'1 - connect \Y $sub$ls180.v:7771$2506_Y - end - attribute \src "ls180.v:7903.33-7903.64" - cell $sub $sub$ls180.v:7903$2511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_tccdcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7903$2511_Y - end - attribute \src "ls180.v:7918.33-7918.64" - cell $sub $sub$ls180.v:7918$2514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_twtrcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7918$2514_Y - end - attribute \src "ls180.v:8045.33-8045.64" - cell $sub $sub$ls180.v:8045$2573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_tx_fifo_level0 - connect \B 1'1 - connect \Y $sub$ls180.v:8045$2573_Y - end - attribute \src "ls180.v:8067.33-8067.64" - cell $sub $sub$ls180.v:8067$2584 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_rx_fifo_level0 - connect \B 1'1 - connect \Y $sub$ls180.v:8067$2584_Y - end - attribute \src "ls180.v:8102.33-8102.64" - cell $sub $sub$ls180.v:8102$2589 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_spi_master_mosi_sel - connect \B 1'1 - connect \Y $sub$ls180.v:8102$2589_Y - end - attribute \src "ls180.v:8126.30-8126.53" - cell $sub $sub$ls180.v:8126$2592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_pwm0_period - connect \B 1'1 - connect \Y $sub$ls180.v:8126$2592_Y - end - attribute \src "ls180.v:8140.30-8140.53" - cell $sub $sub$ls180.v:8140$2596 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_pwm1_period - connect \B 1'1 - connect \Y $sub$ls180.v:8140$2596_Y - end - attribute \src "ls180.v:8543.36-8543.70" - cell $sub $sub$ls180.v:8543$2657 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \main_sdblock2mem_fifo_level - connect \B 1'1 - connect \Y $sub$ls180.v:8543$2657_Y - end - attribute \src "ls180.v:8629.36-8629.70" - cell $sub $sub$ls180.v:8629$2679 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \main_sdmem2block_fifo_level - connect \B 1'1 - connect \Y $sub$ls180.v:8629$2679_Y - end - attribute \src "ls180.v:8650.29-8650.56" - cell $sub $sub$ls180.v:8650$2684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \libresocsim_mosi_sel - connect \B 1'1 - connect \Y $sub$ls180.v:8650$2684_Y - end - attribute \src "ls180.v:8777.22-8777.42" - cell $sub $sub$ls180.v:8777$2691 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 20 - connect \A \builder_count - connect \B 1'1 - connect \Y $sub$ls180.v:8777$2691_Y - end - attribute \src "ls180.v:4847.353-4847.425" - cell $xor $xor$ls180.v:4847$702 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [39] - connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:4847$702_Y - end - attribute \src "ls180.v:4847.200-4847.272" - cell $xor $xor$ls180.v:4847$703 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [39] - connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:4847$703_Y - end - attribute \src "ls180.v:4847.160-4847.273" - cell $xor $xor$ls180.v:4847$704 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg0 [2] - connect \B $xor$ls180.v:4847$703_Y - connect \Y $xor$ls180.v:4847$704_Y - end - attribute \src "ls180.v:4848.353-4848.425" - cell $xor $xor$ls180.v:4848$705 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [38] - connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:4848$705_Y - end - attribute \src "ls180.v:4848.200-4848.272" - cell $xor $xor$ls180.v:4848$706 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [38] - connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:4848$706_Y - end - attribute \src "ls180.v:4848.160-4848.273" - cell $xor $xor$ls180.v:4848$707 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg1 [2] - connect \B $xor$ls180.v:4848$706_Y - connect \Y $xor$ls180.v:4848$707_Y - end - attribute \src "ls180.v:4849.353-4849.425" - cell $xor $xor$ls180.v:4849$708 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [37] - connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:4849$708_Y - end - attribute \src "ls180.v:4849.200-4849.272" - cell $xor $xor$ls180.v:4849$709 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [37] - connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:4849$709_Y - end - attribute \src "ls180.v:4849.160-4849.273" - cell $xor $xor$ls180.v:4849$710 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg2 [2] - connect \B $xor$ls180.v:4849$709_Y - connect \Y $xor$ls180.v:4849$710_Y - end - attribute \src "ls180.v:4850.353-4850.425" - cell $xor $xor$ls180.v:4850$711 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [36] - connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:4850$711_Y - end - attribute \src "ls180.v:4850.200-4850.272" - cell $xor $xor$ls180.v:4850$712 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [36] - connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:4850$712_Y - end - attribute \src "ls180.v:4850.160-4850.273" - cell $xor $xor$ls180.v:4850$713 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg3 [2] - connect \B $xor$ls180.v:4850$712_Y - connect \Y $xor$ls180.v:4850$713_Y - end - attribute \src "ls180.v:4851.353-4851.425" - cell $xor $xor$ls180.v:4851$714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [35] - connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:4851$714_Y - end - attribute \src "ls180.v:4851.200-4851.272" - cell $xor $xor$ls180.v:4851$715 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [35] - connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:4851$715_Y - end - attribute \src "ls180.v:4851.160-4851.273" - cell $xor $xor$ls180.v:4851$716 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg4 [2] - connect \B $xor$ls180.v:4851$715_Y - connect \Y $xor$ls180.v:4851$716_Y - end - attribute \src "ls180.v:4852.353-4852.425" - cell $xor $xor$ls180.v:4852$717 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [34] - connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:4852$717_Y - end - attribute \src "ls180.v:4852.200-4852.272" - cell $xor $xor$ls180.v:4852$718 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [34] - connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:4852$718_Y - end - attribute \src "ls180.v:4852.160-4852.273" - cell $xor $xor$ls180.v:4852$719 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg5 [2] - connect \B $xor$ls180.v:4852$718_Y - connect \Y $xor$ls180.v:4852$719_Y - end - attribute \src "ls180.v:4853.353-4853.425" - cell $xor $xor$ls180.v:4853$720 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [33] - connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:4853$720_Y - end - attribute \src "ls180.v:4853.200-4853.272" - cell $xor $xor$ls180.v:4853$721 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [33] - connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:4853$721_Y - end - attribute \src "ls180.v:4853.160-4853.273" - cell $xor $xor$ls180.v:4853$722 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg6 [2] - connect \B $xor$ls180.v:4853$721_Y - connect \Y $xor$ls180.v:4853$722_Y - end - attribute \src "ls180.v:4854.353-4854.425" - cell $xor $xor$ls180.v:4854$723 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [32] - connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:4854$723_Y - end - attribute \src "ls180.v:4854.200-4854.272" - cell $xor $xor$ls180.v:4854$724 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [32] - connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:4854$724_Y - end - attribute \src "ls180.v:4854.160-4854.273" - cell $xor $xor$ls180.v:4854$725 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg7 [2] - connect \B $xor$ls180.v:4854$724_Y - connect \Y $xor$ls180.v:4854$725_Y - end - attribute \src "ls180.v:4855.353-4855.425" - cell $xor $xor$ls180.v:4855$726 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [31] - connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:4855$726_Y - end - attribute \src "ls180.v:4855.200-4855.272" - cell $xor $xor$ls180.v:4855$727 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [31] - connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:4855$727_Y - end - attribute \src "ls180.v:4855.160-4855.273" - cell $xor $xor$ls180.v:4855$728 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg8 [2] - connect \B $xor$ls180.v:4855$727_Y - connect \Y $xor$ls180.v:4855$728_Y - end - attribute \src "ls180.v:4856.354-4856.426" - cell $xor $xor$ls180.v:4856$729 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [30] - connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:4856$729_Y - end - attribute \src "ls180.v:4856.201-4856.273" - cell $xor $xor$ls180.v:4856$730 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [30] - connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:4856$730_Y - end - attribute \src "ls180.v:4856.161-4856.274" - cell $xor $xor$ls180.v:4856$731 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg9 [2] - connect \B $xor$ls180.v:4856$730_Y - connect \Y $xor$ls180.v:4856$731_Y - end - attribute \src "ls180.v:4857.361-4857.434" - cell $xor $xor$ls180.v:4857$732 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [29] - connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:4857$732_Y - end - attribute \src "ls180.v:4857.205-4857.278" - cell $xor $xor$ls180.v:4857$733 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [29] - connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:4857$733_Y - end - attribute \src "ls180.v:4857.164-4857.279" - cell $xor $xor$ls180.v:4857$734 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg10 [2] - connect \B $xor$ls180.v:4857$733_Y - connect \Y $xor$ls180.v:4857$734_Y - end - attribute \src "ls180.v:4858.361-4858.434" - cell $xor $xor$ls180.v:4858$735 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [28] - connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:4858$735_Y - end - attribute \src "ls180.v:4858.205-4858.278" - cell $xor $xor$ls180.v:4858$736 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [28] - connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:4858$736_Y - end - attribute \src "ls180.v:4858.164-4858.279" - cell $xor $xor$ls180.v:4858$737 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg11 [2] - connect \B $xor$ls180.v:4858$736_Y - connect \Y $xor$ls180.v:4858$737_Y - end - attribute \src "ls180.v:4859.361-4859.434" - cell $xor $xor$ls180.v:4859$738 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [27] - connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:4859$738_Y - end - attribute \src "ls180.v:4859.205-4859.278" - cell $xor $xor$ls180.v:4859$739 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [27] - connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:4859$739_Y - end - attribute \src "ls180.v:4859.164-4859.279" - cell $xor $xor$ls180.v:4859$740 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg12 [2] - connect \B $xor$ls180.v:4859$739_Y - connect \Y $xor$ls180.v:4859$740_Y - end - attribute \src "ls180.v:4860.361-4860.434" - cell $xor $xor$ls180.v:4860$741 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [26] - connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:4860$741_Y - end - attribute \src "ls180.v:4860.205-4860.278" - cell $xor $xor$ls180.v:4860$742 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [26] - connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:4860$742_Y - end - attribute \src "ls180.v:4860.164-4860.279" - cell $xor $xor$ls180.v:4860$743 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg13 [2] - connect \B $xor$ls180.v:4860$742_Y - connect \Y $xor$ls180.v:4860$743_Y - end - attribute \src "ls180.v:4861.361-4861.434" - cell $xor $xor$ls180.v:4861$744 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [25] - connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:4861$744_Y - end - attribute \src "ls180.v:4861.205-4861.278" - cell $xor $xor$ls180.v:4861$745 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [25] - connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:4861$745_Y - end - attribute \src "ls180.v:4861.164-4861.279" - cell $xor $xor$ls180.v:4861$746 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg14 [2] - connect \B $xor$ls180.v:4861$745_Y - connect \Y $xor$ls180.v:4861$746_Y - end - attribute \src "ls180.v:4862.361-4862.434" - cell $xor $xor$ls180.v:4862$747 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [24] - connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:4862$747_Y - end - attribute \src "ls180.v:4862.205-4862.278" - cell $xor $xor$ls180.v:4862$748 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [24] - connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:4862$748_Y - end - attribute \src "ls180.v:4862.164-4862.279" - cell $xor $xor$ls180.v:4862$749 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg15 [2] - connect \B $xor$ls180.v:4862$748_Y - connect \Y $xor$ls180.v:4862$749_Y - end - attribute \src "ls180.v:4863.361-4863.434" - cell $xor $xor$ls180.v:4863$750 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [23] - connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:4863$750_Y - end - attribute \src "ls180.v:4863.205-4863.278" - cell $xor $xor$ls180.v:4863$751 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [23] - connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:4863$751_Y - end - attribute \src "ls180.v:4863.164-4863.279" - cell $xor $xor$ls180.v:4863$752 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg16 [2] - connect \B $xor$ls180.v:4863$751_Y - connect \Y $xor$ls180.v:4863$752_Y - end - attribute \src "ls180.v:4864.361-4864.434" - cell $xor $xor$ls180.v:4864$753 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [22] - connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:4864$753_Y - end - attribute \src "ls180.v:4864.205-4864.278" - cell $xor $xor$ls180.v:4864$754 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [22] - connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:4864$754_Y - end - attribute \src "ls180.v:4864.164-4864.279" - cell $xor $xor$ls180.v:4864$755 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg17 [2] - connect \B $xor$ls180.v:4864$754_Y - connect \Y $xor$ls180.v:4864$755_Y - end - attribute \src "ls180.v:4865.361-4865.434" - cell $xor $xor$ls180.v:4865$756 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [21] - connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:4865$756_Y - end - attribute \src "ls180.v:4865.205-4865.278" - cell $xor $xor$ls180.v:4865$757 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [21] - connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:4865$757_Y - end - attribute \src "ls180.v:4865.164-4865.279" - cell $xor $xor$ls180.v:4865$758 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg18 [2] - connect \B $xor$ls180.v:4865$757_Y - connect \Y $xor$ls180.v:4865$758_Y - end - attribute \src "ls180.v:4866.361-4866.434" - cell $xor $xor$ls180.v:4866$759 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [20] - connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:4866$759_Y - end - attribute \src "ls180.v:4866.205-4866.278" - cell $xor $xor$ls180.v:4866$760 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [20] - connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:4866$760_Y - end - attribute \src "ls180.v:4866.164-4866.279" - cell $xor $xor$ls180.v:4866$761 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg19 [2] - connect \B $xor$ls180.v:4866$760_Y - connect \Y $xor$ls180.v:4866$761_Y - end - attribute \src "ls180.v:4867.361-4867.434" - cell $xor $xor$ls180.v:4867$762 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [19] - connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:4867$762_Y - end - attribute \src "ls180.v:4867.205-4867.278" - cell $xor $xor$ls180.v:4867$763 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [19] - connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:4867$763_Y - end - attribute \src "ls180.v:4867.164-4867.279" - cell $xor $xor$ls180.v:4867$764 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg20 [2] - connect \B $xor$ls180.v:4867$763_Y - connect \Y $xor$ls180.v:4867$764_Y - end - attribute \src "ls180.v:4868.361-4868.434" - cell $xor $xor$ls180.v:4868$765 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [18] - connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:4868$765_Y - end - attribute \src "ls180.v:4868.205-4868.278" - cell $xor $xor$ls180.v:4868$766 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [18] - connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:4868$766_Y - end - attribute \src "ls180.v:4868.164-4868.279" - cell $xor $xor$ls180.v:4868$767 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg21 [2] - connect \B $xor$ls180.v:4868$766_Y - connect \Y $xor$ls180.v:4868$767_Y - end - attribute \src "ls180.v:4869.361-4869.434" - cell $xor $xor$ls180.v:4869$768 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [17] - connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:4869$768_Y - end - attribute \src "ls180.v:4869.205-4869.278" - cell $xor $xor$ls180.v:4869$769 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [17] - connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:4869$769_Y - end - attribute \src "ls180.v:4869.164-4869.279" - cell $xor $xor$ls180.v:4869$770 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg22 [2] - connect \B $xor$ls180.v:4869$769_Y - connect \Y $xor$ls180.v:4869$770_Y - end - attribute \src "ls180.v:4870.361-4870.434" - cell $xor $xor$ls180.v:4870$771 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [16] - connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:4870$771_Y - end - attribute \src "ls180.v:4870.205-4870.278" - cell $xor $xor$ls180.v:4870$772 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [16] - connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:4870$772_Y - end - attribute \src "ls180.v:4870.164-4870.279" - cell $xor $xor$ls180.v:4870$773 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg23 [2] - connect \B $xor$ls180.v:4870$772_Y - connect \Y $xor$ls180.v:4870$773_Y - end - attribute \src "ls180.v:4871.361-4871.434" - cell $xor $xor$ls180.v:4871$774 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [15] - connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:4871$774_Y - end - attribute \src "ls180.v:4871.205-4871.278" - cell $xor $xor$ls180.v:4871$775 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [15] - connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:4871$775_Y - end - attribute \src "ls180.v:4871.164-4871.279" - cell $xor $xor$ls180.v:4871$776 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg24 [2] - connect \B $xor$ls180.v:4871$775_Y - connect \Y $xor$ls180.v:4871$776_Y - end - attribute \src "ls180.v:4872.361-4872.434" - cell $xor $xor$ls180.v:4872$777 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [14] - connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:4872$777_Y - end - attribute \src "ls180.v:4872.205-4872.278" - cell $xor $xor$ls180.v:4872$778 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [14] - connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:4872$778_Y - end - attribute \src "ls180.v:4872.164-4872.279" - cell $xor $xor$ls180.v:4872$779 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg25 [2] - connect \B $xor$ls180.v:4872$778_Y - connect \Y $xor$ls180.v:4872$779_Y - end - attribute \src "ls180.v:4873.361-4873.434" - cell $xor $xor$ls180.v:4873$780 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [13] - connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:4873$780_Y - end - attribute \src "ls180.v:4873.205-4873.278" - cell $xor $xor$ls180.v:4873$781 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [13] - connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:4873$781_Y - end - attribute \src "ls180.v:4873.164-4873.279" - cell $xor $xor$ls180.v:4873$782 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg26 [2] - connect \B $xor$ls180.v:4873$781_Y - connect \Y $xor$ls180.v:4873$782_Y - end - attribute \src "ls180.v:4874.361-4874.434" - cell $xor $xor$ls180.v:4874$783 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [12] - connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:4874$783_Y - end - attribute \src "ls180.v:4874.205-4874.278" - cell $xor $xor$ls180.v:4874$784 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [12] - connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:4874$784_Y - end - attribute \src "ls180.v:4874.164-4874.279" - cell $xor $xor$ls180.v:4874$785 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg27 [2] - connect \B $xor$ls180.v:4874$784_Y - connect \Y $xor$ls180.v:4874$785_Y - end - attribute \src "ls180.v:4875.361-4875.434" - cell $xor $xor$ls180.v:4875$786 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [11] - connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:4875$786_Y - end - attribute \src "ls180.v:4875.205-4875.278" - cell $xor $xor$ls180.v:4875$787 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [11] - connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:4875$787_Y - end - attribute \src "ls180.v:4875.164-4875.279" - cell $xor $xor$ls180.v:4875$788 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg28 [2] - connect \B $xor$ls180.v:4875$787_Y - connect \Y $xor$ls180.v:4875$788_Y - end - attribute \src "ls180.v:4876.361-4876.434" - cell $xor $xor$ls180.v:4876$789 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [10] - connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:4876$789_Y - end - attribute \src "ls180.v:4876.205-4876.278" - cell $xor $xor$ls180.v:4876$790 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [10] - connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:4876$790_Y - end - attribute \src "ls180.v:4876.164-4876.279" - cell $xor $xor$ls180.v:4876$791 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg29 [2] - connect \B $xor$ls180.v:4876$790_Y - connect \Y $xor$ls180.v:4876$791_Y - end - attribute \src "ls180.v:4877.360-4877.432" - cell $xor $xor$ls180.v:4877$792 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [9] - connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:4877$792_Y - end - attribute \src "ls180.v:4877.205-4877.277" - cell $xor $xor$ls180.v:4877$793 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [9] - connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:4877$793_Y - end - attribute \src "ls180.v:4877.164-4877.278" - cell $xor $xor$ls180.v:4877$794 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg30 [2] - connect \B $xor$ls180.v:4877$793_Y - connect \Y $xor$ls180.v:4877$794_Y - end - attribute \src "ls180.v:4878.360-4878.432" - cell $xor $xor$ls180.v:4878$795 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [8] - connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:4878$795_Y - end - attribute \src "ls180.v:4878.205-4878.277" - cell $xor $xor$ls180.v:4878$796 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [8] - connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:4878$796_Y - end - attribute \src "ls180.v:4878.164-4878.278" - cell $xor $xor$ls180.v:4878$797 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg31 [2] - connect \B $xor$ls180.v:4878$796_Y - connect \Y $xor$ls180.v:4878$797_Y - end - attribute \src "ls180.v:4879.360-4879.432" - cell $xor $xor$ls180.v:4879$798 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [7] - connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:4879$798_Y - end - attribute \src "ls180.v:4879.205-4879.277" - cell $xor $xor$ls180.v:4879$799 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [7] - connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:4879$799_Y - end - attribute \src "ls180.v:4879.164-4879.278" - cell $xor $xor$ls180.v:4879$800 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg32 [2] - connect \B $xor$ls180.v:4879$799_Y - connect \Y $xor$ls180.v:4879$800_Y - end - attribute \src "ls180.v:4880.360-4880.432" - cell $xor $xor$ls180.v:4880$801 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [6] - connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:4880$801_Y - end - attribute \src "ls180.v:4880.205-4880.277" - cell $xor $xor$ls180.v:4880$802 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [6] - connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:4880$802_Y - end - attribute \src "ls180.v:4880.164-4880.278" - cell $xor $xor$ls180.v:4880$803 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg33 [2] - connect \B $xor$ls180.v:4880$802_Y - connect \Y $xor$ls180.v:4880$803_Y - end - attribute \src "ls180.v:4881.360-4881.432" - cell $xor $xor$ls180.v:4881$804 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [5] - connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:4881$804_Y - end - attribute \src "ls180.v:4881.205-4881.277" - cell $xor $xor$ls180.v:4881$805 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [5] - connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:4881$805_Y - end - attribute \src "ls180.v:4881.164-4881.278" - cell $xor $xor$ls180.v:4881$806 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg34 [2] - connect \B $xor$ls180.v:4881$805_Y - connect \Y $xor$ls180.v:4881$806_Y - end - attribute \src "ls180.v:4882.360-4882.432" - cell $xor $xor$ls180.v:4882$807 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [4] - connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:4882$807_Y - end - attribute \src "ls180.v:4882.205-4882.277" - cell $xor $xor$ls180.v:4882$808 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [4] - connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:4882$808_Y - end - attribute \src "ls180.v:4882.164-4882.278" - cell $xor $xor$ls180.v:4882$809 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg35 [2] - connect \B $xor$ls180.v:4882$808_Y - connect \Y $xor$ls180.v:4882$809_Y - end - attribute \src "ls180.v:4883.360-4883.432" - cell $xor $xor$ls180.v:4883$810 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [3] - connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:4883$810_Y - end - attribute \src "ls180.v:4883.205-4883.277" - cell $xor $xor$ls180.v:4883$811 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [3] - connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:4883$811_Y - end - attribute \src "ls180.v:4883.164-4883.278" - cell $xor $xor$ls180.v:4883$812 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg36 [2] - connect \B $xor$ls180.v:4883$811_Y - connect \Y $xor$ls180.v:4883$812_Y - end - attribute \src "ls180.v:4884.360-4884.432" - cell $xor $xor$ls180.v:4884$813 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [2] - connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:4884$813_Y - end - attribute \src "ls180.v:4884.205-4884.277" - cell $xor $xor$ls180.v:4884$814 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [2] - connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:4884$814_Y - end - attribute \src "ls180.v:4884.164-4884.278" - cell $xor $xor$ls180.v:4884$815 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg37 [2] - connect \B $xor$ls180.v:4884$814_Y - connect \Y $xor$ls180.v:4884$815_Y - end - attribute \src "ls180.v:4885.360-4885.432" - cell $xor $xor$ls180.v:4885$816 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [1] - connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:4885$816_Y - end - attribute \src "ls180.v:4885.205-4885.277" - cell $xor $xor$ls180.v:4885$817 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [1] - connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:4885$817_Y - end - attribute \src "ls180.v:4885.164-4885.278" - cell $xor $xor$ls180.v:4885$818 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg38 [2] - connect \B $xor$ls180.v:4885$817_Y - connect \Y $xor$ls180.v:4885$818_Y - end - attribute \src "ls180.v:4886.360-4886.432" - cell $xor $xor$ls180.v:4886$819 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [0] - connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:4886$819_Y - end - attribute \src "ls180.v:4886.205-4886.277" - cell $xor $xor$ls180.v:4886$820 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [0] - connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:4886$820_Y - end - attribute \src "ls180.v:4886.164-4886.278" - cell $xor $xor$ls180.v:4886$821 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg39 [2] - connect \B $xor$ls180.v:4886$820_Y - connect \Y $xor$ls180.v:4886$821_Y - end - attribute \src "ls180.v:4907.899-4907.983" - cell $xor $xor$ls180.v:4907$835 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [1] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:4907$835_Y - end - attribute \src "ls180.v:4907.634-4907.718" - cell $xor $xor$ls180.v:4907$836 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [1] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:4907$836_Y - end - attribute \src "ls180.v:4907.588-4907.719" - cell $xor $xor$ls180.v:4907$837 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4] - connect \B $xor$ls180.v:4907$836_Y - connect \Y $xor$ls180.v:4907$837_Y - end - attribute \src "ls180.v:4907.234-4907.318" - cell $xor $xor$ls180.v:4907$838 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [1] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:4907$838_Y - end - attribute \src "ls180.v:4907.187-4907.319" - cell $xor $xor$ls180.v:4907$839 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11] - connect \B $xor$ls180.v:4907$838_Y - connect \Y $xor$ls180.v:4907$839_Y - end - attribute \src "ls180.v:4908.899-4908.983" - cell $xor $xor$ls180.v:4908$840 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [0] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:4908$840_Y - end - attribute \src "ls180.v:4908.634-4908.718" - cell $xor $xor$ls180.v:4908$841 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [0] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:4908$841_Y - end - attribute \src "ls180.v:4908.588-4908.719" - cell $xor $xor$ls180.v:4908$842 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] - connect \B $xor$ls180.v:4908$841_Y - connect \Y $xor$ls180.v:4908$842_Y - end - attribute \src "ls180.v:4908.234-4908.318" - cell $xor $xor$ls180.v:4908$843 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [0] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:4908$843_Y - end - attribute \src "ls180.v:4908.187-4908.319" - cell $xor $xor$ls180.v:4908$844 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] - connect \B $xor$ls180.v:4908$843_Y - connect \Y $xor$ls180.v:4908$844_Y - end - attribute \src "ls180.v:4917.899-4917.983" - cell $xor $xor$ls180.v:4917$846 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [1] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:4917$846_Y - end - attribute \src "ls180.v:4917.634-4917.718" - cell $xor $xor$ls180.v:4917$847 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [1] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:4917$847_Y - end - attribute \src "ls180.v:4917.588-4917.719" - cell $xor $xor$ls180.v:4917$848 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4] - connect \B $xor$ls180.v:4917$847_Y - connect \Y $xor$ls180.v:4917$848_Y - end - attribute \src "ls180.v:4917.234-4917.318" - cell $xor $xor$ls180.v:4917$849 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [1] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:4917$849_Y - end - attribute \src "ls180.v:4917.187-4917.319" - cell $xor $xor$ls180.v:4917$850 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11] - connect \B $xor$ls180.v:4917$849_Y - connect \Y $xor$ls180.v:4917$850_Y - end - attribute \src "ls180.v:4918.899-4918.983" - cell $xor $xor$ls180.v:4918$851 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [0] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:4918$851_Y - end - attribute \src "ls180.v:4918.634-4918.718" - cell $xor $xor$ls180.v:4918$852 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [0] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:4918$852_Y - end - attribute \src "ls180.v:4918.588-4918.719" - cell $xor $xor$ls180.v:4918$853 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4] - connect \B $xor$ls180.v:4918$852_Y - connect \Y $xor$ls180.v:4918$853_Y - end - attribute \src "ls180.v:4918.234-4918.318" - cell $xor $xor$ls180.v:4918$854 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [0] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:4918$854_Y - end - attribute \src "ls180.v:4918.187-4918.319" - cell $xor $xor$ls180.v:4918$855 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11] - connect \B $xor$ls180.v:4918$854_Y - connect \Y $xor$ls180.v:4918$855_Y - end - attribute \src "ls180.v:4927.899-4927.983" - cell $xor $xor$ls180.v:4927$857 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [1] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:4927$857_Y - end - attribute \src "ls180.v:4927.634-4927.718" - cell $xor $xor$ls180.v:4927$858 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [1] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:4927$858_Y - end - attribute \src "ls180.v:4927.588-4927.719" - cell $xor $xor$ls180.v:4927$859 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4] - connect \B $xor$ls180.v:4927$858_Y - connect \Y $xor$ls180.v:4927$859_Y - end - attribute \src "ls180.v:4927.234-4927.318" - cell $xor $xor$ls180.v:4927$860 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [1] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:4927$860_Y - end - attribute \src "ls180.v:4927.187-4927.319" - cell $xor $xor$ls180.v:4927$861 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11] - connect \B $xor$ls180.v:4927$860_Y - connect \Y $xor$ls180.v:4927$861_Y - end - attribute \src "ls180.v:4928.899-4928.983" - cell $xor $xor$ls180.v:4928$862 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [0] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:4928$862_Y - end - attribute \src "ls180.v:4928.634-4928.718" - cell $xor $xor$ls180.v:4928$863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [0] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:4928$863_Y - end - attribute \src "ls180.v:4928.588-4928.719" - cell $xor $xor$ls180.v:4928$864 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4] - connect \B $xor$ls180.v:4928$863_Y - connect \Y $xor$ls180.v:4928$864_Y - end - attribute \src "ls180.v:4928.234-4928.318" - cell $xor $xor$ls180.v:4928$865 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [0] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:4928$865_Y - end - attribute \src "ls180.v:4928.187-4928.319" - cell $xor $xor$ls180.v:4928$866 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11] - connect \B $xor$ls180.v:4928$865_Y - connect \Y $xor$ls180.v:4928$866_Y - end - attribute \src "ls180.v:4937.899-4937.983" - cell $xor $xor$ls180.v:4937$868 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [1] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:4937$868_Y - end - attribute \src "ls180.v:4937.634-4937.718" - cell $xor $xor$ls180.v:4937$869 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [1] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:4937$869_Y - end - attribute \src "ls180.v:4937.588-4937.719" - cell $xor $xor$ls180.v:4937$870 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4] - connect \B $xor$ls180.v:4937$869_Y - connect \Y $xor$ls180.v:4937$870_Y - end - attribute \src "ls180.v:4937.234-4937.318" - cell $xor $xor$ls180.v:4937$871 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [1] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:4937$871_Y - end - attribute \src "ls180.v:4937.187-4937.319" - cell $xor $xor$ls180.v:4937$872 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11] - connect \B $xor$ls180.v:4937$871_Y - connect \Y $xor$ls180.v:4937$872_Y - end - attribute \src "ls180.v:4938.899-4938.983" - cell $xor $xor$ls180.v:4938$873 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [0] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:4938$873_Y - end - attribute \src "ls180.v:4938.634-4938.718" - cell $xor $xor$ls180.v:4938$874 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [0] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:4938$874_Y - end - attribute \src "ls180.v:4938.588-4938.719" - cell $xor $xor$ls180.v:4938$875 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4] - connect \B $xor$ls180.v:4938$874_Y - connect \Y $xor$ls180.v:4938$875_Y - end - attribute \src "ls180.v:4938.234-4938.318" - cell $xor $xor$ls180.v:4938$876 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [0] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:4938$876_Y - end - attribute \src "ls180.v:4938.187-4938.319" - cell $xor $xor$ls180.v:4938$877 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] - connect \B $xor$ls180.v:4938$876_Y - connect \Y $xor$ls180.v:4938$877_Y - end - attribute \src "ls180.v:5089.879-5089.961" - cell $xor $xor$ls180.v:5089$910 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [1] - connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5089$910_Y - end - attribute \src "ls180.v:5089.620-5089.702" - cell $xor $xor$ls180.v:5089$911 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [1] - connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5089$911_Y - end - attribute \src "ls180.v:5089.575-5089.703" - cell $xor $xor$ls180.v:5089$912 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4] - connect \B $xor$ls180.v:5089$911_Y - connect \Y $xor$ls180.v:5089$912_Y - end - attribute \src "ls180.v:5089.229-5089.311" - cell $xor $xor$ls180.v:5089$913 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [1] - connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5089$913_Y - end - attribute \src "ls180.v:5089.183-5089.312" - cell $xor $xor$ls180.v:5089$914 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11] - connect \B $xor$ls180.v:5089$913_Y - connect \Y $xor$ls180.v:5089$914_Y - end - attribute \src "ls180.v:5090.879-5090.961" - cell $xor $xor$ls180.v:5090$915 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [0] - connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5090$915_Y - end - attribute \src "ls180.v:5090.620-5090.702" - cell $xor $xor$ls180.v:5090$916 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [0] - connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5090$916_Y - end - attribute \src "ls180.v:5090.575-5090.703" - cell $xor $xor$ls180.v:5090$917 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4] - connect \B $xor$ls180.v:5090$916_Y - connect \Y $xor$ls180.v:5090$917_Y - end - attribute \src "ls180.v:5090.229-5090.311" - cell $xor $xor$ls180.v:5090$918 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [0] - connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5090$918_Y - end - attribute \src "ls180.v:5090.183-5090.312" - cell $xor $xor$ls180.v:5090$919 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11] - connect \B $xor$ls180.v:5090$918_Y - connect \Y $xor$ls180.v:5090$919_Y - end - attribute \src "ls180.v:5099.879-5099.961" - cell $xor $xor$ls180.v:5099$921 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [1] - connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5099$921_Y - end - attribute \src "ls180.v:5099.620-5099.702" - cell $xor $xor$ls180.v:5099$922 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [1] - connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5099$922_Y - end - attribute \src "ls180.v:5099.575-5099.703" - cell $xor $xor$ls180.v:5099$923 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4] - connect \B $xor$ls180.v:5099$922_Y - connect \Y $xor$ls180.v:5099$923_Y - end - attribute \src "ls180.v:5099.229-5099.311" - cell $xor $xor$ls180.v:5099$924 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [1] - connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5099$924_Y - end - attribute \src "ls180.v:5099.183-5099.312" - cell $xor $xor$ls180.v:5099$925 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11] - connect \B $xor$ls180.v:5099$924_Y - connect \Y $xor$ls180.v:5099$925_Y - end - attribute \src "ls180.v:5100.879-5100.961" - cell $xor $xor$ls180.v:5100$926 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [0] - connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5100$926_Y - end - attribute \src "ls180.v:5100.620-5100.702" - cell $xor $xor$ls180.v:5100$927 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [0] - connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5100$927_Y - end - attribute \src "ls180.v:5100.575-5100.703" - cell $xor $xor$ls180.v:5100$928 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4] - connect \B $xor$ls180.v:5100$927_Y - connect \Y $xor$ls180.v:5100$928_Y - end - attribute \src "ls180.v:5100.229-5100.311" - cell $xor $xor$ls180.v:5100$929 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [0] - connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5100$929_Y - end - attribute \src "ls180.v:5100.183-5100.312" - cell $xor $xor$ls180.v:5100$930 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11] - connect \B $xor$ls180.v:5100$929_Y - connect \Y $xor$ls180.v:5100$930_Y - end - attribute \src "ls180.v:5109.879-5109.961" - cell $xor $xor$ls180.v:5109$932 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [1] - connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5109$932_Y - end - attribute \src "ls180.v:5109.620-5109.702" - cell $xor $xor$ls180.v:5109$933 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [1] - connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5109$933_Y - end - attribute \src "ls180.v:5109.575-5109.703" - cell $xor $xor$ls180.v:5109$934 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4] - connect \B $xor$ls180.v:5109$933_Y - connect \Y $xor$ls180.v:5109$934_Y - end - attribute \src "ls180.v:5109.229-5109.311" - cell $xor $xor$ls180.v:5109$935 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [1] - connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5109$935_Y - end - attribute \src "ls180.v:5109.183-5109.312" - cell $xor $xor$ls180.v:5109$936 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11] - connect \B $xor$ls180.v:5109$935_Y - connect \Y $xor$ls180.v:5109$936_Y - end - attribute \src "ls180.v:5110.879-5110.961" - cell $xor $xor$ls180.v:5110$937 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [0] - connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5110$937_Y - end - attribute \src "ls180.v:5110.620-5110.702" - cell $xor $xor$ls180.v:5110$938 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [0] - connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5110$938_Y - end - attribute \src "ls180.v:5110.575-5110.703" - cell $xor $xor$ls180.v:5110$939 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] - connect \B $xor$ls180.v:5110$938_Y - connect \Y $xor$ls180.v:5110$939_Y - end - attribute \src "ls180.v:5110.229-5110.311" - cell $xor $xor$ls180.v:5110$940 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [0] - connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5110$940_Y - end - attribute \src "ls180.v:5110.183-5110.312" - cell $xor $xor$ls180.v:5110$941 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] - connect \B $xor$ls180.v:5110$940_Y - connect \Y $xor$ls180.v:5110$941_Y - end - attribute \src "ls180.v:5119.879-5119.961" - cell $xor $xor$ls180.v:5119$943 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [1] - connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5119$943_Y - end - attribute \src "ls180.v:5119.620-5119.702" - cell $xor $xor$ls180.v:5119$944 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [1] - connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5119$944_Y - end - attribute \src "ls180.v:5119.575-5119.703" - cell $xor $xor$ls180.v:5119$945 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4] - connect \B $xor$ls180.v:5119$944_Y - connect \Y $xor$ls180.v:5119$945_Y - end - attribute \src "ls180.v:5119.229-5119.311" - cell $xor $xor$ls180.v:5119$946 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [1] - connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5119$946_Y - end - attribute \src "ls180.v:5119.183-5119.312" - cell $xor $xor$ls180.v:5119$947 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11] - connect \B $xor$ls180.v:5119$946_Y - connect \Y $xor$ls180.v:5119$947_Y - end - attribute \src "ls180.v:5120.879-5120.961" - cell $xor $xor$ls180.v:5120$948 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [0] - connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5120$948_Y - end - attribute \src "ls180.v:5120.620-5120.702" - cell $xor $xor$ls180.v:5120$949 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [0] - connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5120$949_Y - end - attribute \src "ls180.v:5120.575-5120.703" - cell $xor $xor$ls180.v:5120$950 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4] - connect \B $xor$ls180.v:5120$949_Y - connect \Y $xor$ls180.v:5120$950_Y - end - attribute \src "ls180.v:5120.229-5120.311" - cell $xor $xor$ls180.v:5120$951 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [0] - connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5120$951_Y - end - attribute \src "ls180.v:5120.183-5120.312" - cell $xor $xor$ls180.v:5120$952 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11] - connect \B $xor$ls180.v:5120$951_Y - connect \Y $xor$ls180.v:5120$952_Y - end - attribute \module_not_derived 1 - attribute \src "ls180.v:10176.13-10345.2" - cell \test_issuer \test_issuer - connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck - connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi - connect \TAP_bus__tdo \main_libresocsim_libresoc_jtag_tdo - connect \TAP_bus__tms \main_libresocsim_libresoc_jtag_tms - connect \busy_o \main_libresocsim_libresoc0 - connect \clk \sys_clk_1 - connect \clk_sel_i \main_libresocsim_libresoc_clk_sel - connect \core_bigendian_i 1'0 - connect \dbus__ack \main_libresocsim_libresoc_dbus_ack - connect \dbus__adr \main_libresocsim_libresoc_dbus_adr - connect \dbus__bte \main_libresocsim_libresoc_dbus_bte - connect \dbus__cti \main_libresocsim_libresoc_dbus_cti - connect \dbus__cyc \main_libresocsim_libresoc_dbus_cyc - connect \dbus__dat_r \main_libresocsim_libresoc_dbus_dat_r - connect \dbus__dat_w \main_libresocsim_libresoc_dbus_dat_w - connect \dbus__err \main_libresocsim_libresoc_dbus_err - connect \dbus__sel \main_libresocsim_libresoc_dbus_sel - connect \dbus__stb \main_libresocsim_libresoc_dbus_stb - connect \dbus__we \main_libresocsim_libresoc_dbus_we - connect \gpio_gpio0__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [0] - connect \gpio_gpio0__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [0] - connect \gpio_gpio0__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [0] - connect \gpio_gpio0__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [0] - connect \gpio_gpio0__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [0] - connect \gpio_gpio0__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [0] - connect \gpio_gpio10__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [10] - connect \gpio_gpio10__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [10] - connect \gpio_gpio10__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [10] - connect \gpio_gpio10__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [10] - connect \gpio_gpio10__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [10] - connect \gpio_gpio10__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [10] - connect \gpio_gpio11__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [11] - connect \gpio_gpio11__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [11] - connect \gpio_gpio11__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [11] - connect \gpio_gpio11__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [11] - connect \gpio_gpio11__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [11] - connect \gpio_gpio11__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [11] - connect \gpio_gpio12__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [12] - connect \gpio_gpio12__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [12] - connect \gpio_gpio12__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [12] - connect \gpio_gpio12__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [12] - connect \gpio_gpio12__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [12] - connect \gpio_gpio12__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [12] - connect \gpio_gpio13__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [13] - connect \gpio_gpio13__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [13] - connect \gpio_gpio13__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [13] - connect \gpio_gpio13__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [13] - connect \gpio_gpio13__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [13] - connect \gpio_gpio13__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [13] - connect \gpio_gpio14__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [14] - connect \gpio_gpio14__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [14] - connect \gpio_gpio14__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [14] - connect \gpio_gpio14__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [14] - connect \gpio_gpio14__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [14] - connect \gpio_gpio14__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [14] - connect \gpio_gpio15__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [15] - connect \gpio_gpio15__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [15] - connect \gpio_gpio15__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [15] - connect \gpio_gpio15__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [15] - connect \gpio_gpio15__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [15] - connect \gpio_gpio15__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [15] - connect \gpio_gpio1__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [1] - connect \gpio_gpio1__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [1] - connect \gpio_gpio1__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [1] - connect \gpio_gpio1__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [1] - connect \gpio_gpio1__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [1] - connect \gpio_gpio1__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [1] - connect \gpio_gpio2__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [2] - connect \gpio_gpio2__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [2] - connect \gpio_gpio2__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [2] - connect \gpio_gpio2__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [2] - connect \gpio_gpio2__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [2] - connect \gpio_gpio2__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [2] - connect \gpio_gpio3__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [3] - connect \gpio_gpio3__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [3] - connect \gpio_gpio3__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [3] - connect \gpio_gpio3__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [3] - connect \gpio_gpio3__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [3] - connect \gpio_gpio3__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [3] - connect \gpio_gpio4__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [4] - connect \gpio_gpio4__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [4] - connect \gpio_gpio4__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [4] - connect \gpio_gpio4__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [4] - connect \gpio_gpio4__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [4] - connect \gpio_gpio4__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [4] - connect \gpio_gpio5__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [5] - connect \gpio_gpio5__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [5] - connect \gpio_gpio5__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [5] - connect \gpio_gpio5__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [5] - connect \gpio_gpio5__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [5] - connect \gpio_gpio5__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [5] - connect \gpio_gpio6__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [6] - connect \gpio_gpio6__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [6] - connect \gpio_gpio6__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [6] - connect \gpio_gpio6__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [6] - connect \gpio_gpio6__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [6] - connect \gpio_gpio6__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [6] - connect \gpio_gpio7__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [7] - connect \gpio_gpio7__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [7] - connect \gpio_gpio7__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [7] - connect \gpio_gpio7__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [7] - connect \gpio_gpio7__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [7] - connect \gpio_gpio7__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [7] - connect \gpio_gpio8__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [8] - connect \gpio_gpio8__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [8] - connect \gpio_gpio8__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [8] - connect \gpio_gpio8__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [8] - connect \gpio_gpio8__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [8] - connect \gpio_gpio8__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [8] - connect \gpio_gpio9__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [9] - connect \gpio_gpio9__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [9] - connect \gpio_gpio9__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [9] - connect \gpio_gpio9__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [9] - connect \gpio_gpio9__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [9] - connect \gpio_gpio9__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [9] - connect \ibus__ack \main_libresocsim_libresoc_ibus_ack - connect \ibus__adr \main_libresocsim_libresoc_ibus_adr - connect \ibus__bte \main_libresocsim_libresoc_ibus_bte - connect \ibus__cti \main_libresocsim_libresoc_ibus_cti - connect \ibus__cyc \main_libresocsim_libresoc_ibus_cyc - connect \ibus__dat_r \main_libresocsim_libresoc_ibus_dat_r - connect \ibus__dat_w \main_libresocsim_libresoc_ibus_dat_w - connect \ibus__err \main_libresocsim_libresoc_ibus_err - connect \ibus__sel \main_libresocsim_libresoc_ibus_sel - connect \ibus__stb \main_libresocsim_libresoc_ibus_stb - connect \ibus__we \main_libresocsim_libresoc_ibus_we - connect \icp_wb__ack \main_libresocsim_libresoc_xics_icp_ack - connect \icp_wb__adr \main_libresocsim_libresoc_xics_icp_adr - connect \icp_wb__bte \main_libresocsim_libresoc_xics_icp_bte - connect \icp_wb__cti \main_libresocsim_libresoc_xics_icp_cti - connect \icp_wb__cyc \main_libresocsim_libresoc_xics_icp_cyc - connect \icp_wb__dat_r \main_libresocsim_libresoc_xics_icp_dat_r - connect \icp_wb__dat_w \main_libresocsim_libresoc_xics_icp_dat_w - connect \icp_wb__err \main_libresocsim_libresoc_xics_icp_err - connect \icp_wb__sel \main_libresocsim_libresoc_xics_icp_sel - connect \icp_wb__stb \main_libresocsim_libresoc_xics_icp_stb - connect \icp_wb__we \main_libresocsim_libresoc_xics_icp_we - connect \ics_wb__ack \main_libresocsim_libresoc_xics_ics_ack - connect \ics_wb__adr \main_libresocsim_libresoc_xics_ics_adr - connect \ics_wb__bte \main_libresocsim_libresoc_xics_ics_bte - connect \ics_wb__cti \main_libresocsim_libresoc_xics_ics_cti - connect \ics_wb__cyc \main_libresocsim_libresoc_xics_ics_cyc - connect \ics_wb__dat_r \main_libresocsim_libresoc_xics_ics_dat_r - connect \ics_wb__dat_w \main_libresocsim_libresoc_xics_ics_dat_w - connect \ics_wb__err \main_libresocsim_libresoc_xics_ics_err - connect \ics_wb__sel \main_libresocsim_libresoc_xics_ics_sel - connect \ics_wb__stb \main_libresocsim_libresoc_xics_ics_stb - connect \ics_wb__we \main_libresocsim_libresoc_xics_ics_we - connect \int_level_i \main_libresocsim_libresoc_interrupt - connect \jtag_wb__ack \main_libresocsim_libresoc_jtag_wb_ack - connect \jtag_wb__adr \main_libresocsim_libresoc_jtag_wb_adr - connect \jtag_wb__cyc \main_libresocsim_libresoc_jtag_wb_cyc - connect \jtag_wb__dat_r \main_libresocsim_libresoc_jtag_wb_dat_r - connect \jtag_wb__dat_w \main_libresocsim_libresoc_jtag_wb_dat_w - connect \jtag_wb__err \main_libresocsim_libresoc_jtag_wb_err - connect \jtag_wb__sel \main_libresocsim_libresoc_jtag_wb_sel - connect \jtag_wb__stb \main_libresocsim_libresoc_jtag_wb_stb - connect \jtag_wb__we \main_libresocsim_libresoc_jtag_wb_we - connect \memerr_o \main_libresocsim_libresoc1 - connect \pc_i 1'0 - connect \pc_i_ok 1'0 - connect \pc_o \main_libresocsim_libresoc2 - connect \pll_48_o \main_libresocsim_libresoc_pll_48_o - connect \rst $or$ls180.v:10259$2762_Y - connect \uart_rx__core__i \main_libresocsim_libresoc_constraintmanager0_uart0_rx - connect \uart_rx__pad__i \main_libresocsim_libresoc_constraintmanager1_uart0_rx - connect \uart_tx__core__o \main_libresocsim_libresoc_constraintmanager0_uart0_tx - connect \uart_tx__pad__o \main_libresocsim_libresoc_constraintmanager1_uart0_tx - end - attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$3714 - sync always - sync init - end - attribute \src "ls180.v:1001.11-1001.43" - process $proc$ls180.v:1001$3156 - assign { } { } - assign $1\main_spi_master_mosi_data[7:0] 8'00000000 - sync always - sync init - update \main_spi_master_mosi_data $1\main_spi_master_mosi_data[7:0] - end - attribute \src "ls180.v:1002.11-1002.42" - process $proc$ls180.v:1002$3157 - assign { } { } - assign $1\main_spi_master_mosi_sel[2:0] 3'000 - sync always - sync init - update \main_spi_master_mosi_sel $1\main_spi_master_mosi_sel[2:0] - end - attribute \src "ls180.v:1003.11-1003.43" - process $proc$ls180.v:1003$3158 - assign { } { } - assign $1\main_spi_master_miso_data[7:0] 8'00000000 - sync always - sync init - update \main_spi_master_miso_data $1\main_spi_master_miso_data[7:0] - end - attribute \src "ls180.v:10040.1-10050.4" - process $proc$ls180.v:10040$2692 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\mem$ls180.v:10048$4_ADDR[6:0]$2702 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:10048$4_DATA[31:0]$2703 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10048$4_EN[31:0]$2704 0 - assign $0$memwr$\mem$ls180.v:10046$3_ADDR[6:0]$2699 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:10046$3_DATA[31:0]$2700 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10046$3_EN[31:0]$2701 0 - assign $0$memwr$\mem$ls180.v:10044$2_ADDR[6:0]$2696 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:10044$2_DATA[31:0]$2697 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10044$2_EN[31:0]$2698 0 - assign $0$memwr$\mem$ls180.v:10042$1_ADDR[6:0]$2693 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:10042$1_DATA[31:0]$2694 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10042$1_EN[31:0]$2695 0 - assign $0\memadr[6:0] \main_libresocsim_adr - attribute \src "ls180.v:10041.2-10042.65" - switch \main_libresocsim_we [0] - attribute \src "ls180.v:10041.6-10041.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10042$1_ADDR[6:0]$2693 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10042$1_DATA[31:0]$2694 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] } - assign $0$memwr$\mem$ls180.v:10042$1_EN[31:0]$2695 255 - case - end - attribute \src "ls180.v:10043.2-10044.67" - switch \main_libresocsim_we [1] - attribute \src "ls180.v:10043.6-10043.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10044$2_ADDR[6:0]$2696 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10044$2_DATA[31:0]$2697 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem$ls180.v:10044$2_EN[31:0]$2698 65280 - case - end - attribute \src "ls180.v:10045.2-10046.69" - switch \main_libresocsim_we [2] - attribute \src "ls180.v:10045.6-10045.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10046$3_ADDR[6:0]$2699 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10046$3_DATA[31:0]$2700 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10046$3_EN[31:0]$2701 16711680 - case - end - attribute \src "ls180.v:10047.2-10048.69" - switch \main_libresocsim_we [3] - attribute \src "ls180.v:10047.6-10047.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10048$4_ADDR[6:0]$2702 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10048$4_DATA[31:0]$2703 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10048$4_EN[31:0]$2704 32'11111111000000000000000000000000 - case - end - sync posedge \sys_clk_1 - update \memadr $0\memadr[6:0] - update $memwr$\mem$ls180.v:10042$1_ADDR $0$memwr$\mem$ls180.v:10042$1_ADDR[6:0]$2693 - update $memwr$\mem$ls180.v:10042$1_DATA $0$memwr$\mem$ls180.v:10042$1_DATA[31:0]$2694 - update $memwr$\mem$ls180.v:10042$1_EN $0$memwr$\mem$ls180.v:10042$1_EN[31:0]$2695 - update $memwr$\mem$ls180.v:10044$2_ADDR $0$memwr$\mem$ls180.v:10044$2_ADDR[6:0]$2696 - update $memwr$\mem$ls180.v:10044$2_DATA $0$memwr$\mem$ls180.v:10044$2_DATA[31:0]$2697 - update $memwr$\mem$ls180.v:10044$2_EN $0$memwr$\mem$ls180.v:10044$2_EN[31:0]$2698 - update $memwr$\mem$ls180.v:10046$3_ADDR $0$memwr$\mem$ls180.v:10046$3_ADDR[6:0]$2699 - update $memwr$\mem$ls180.v:10046$3_DATA $0$memwr$\mem$ls180.v:10046$3_DATA[31:0]$2700 - update $memwr$\mem$ls180.v:10046$3_EN $0$memwr$\mem$ls180.v:10046$3_EN[31:0]$2701 - update $memwr$\mem$ls180.v:10048$4_ADDR $0$memwr$\mem$ls180.v:10048$4_ADDR[6:0]$2702 - update $memwr$\mem$ls180.v:10048$4_DATA $0$memwr$\mem$ls180.v:10048$4_DATA[31:0]$2703 - update $memwr$\mem$ls180.v:10048$4_EN $0$memwr$\mem$ls180.v:10048$4_EN[31:0]$2704 - end - attribute \src "ls180.v:1005.12-1005.30" - process $proc$ls180.v:1005$3159 - assign { } { } - assign $1\main_dummy[35:0] 36'000000000000000000000000000000000000 - sync always - sync init - update \main_dummy $1\main_dummy[35:0] - end - attribute \src "ls180.v:10060.1-10064.4" - process $proc$ls180.v:10060$2706 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage$ls180.v:10062$5_ADDR[2:0]$2707 3'xxx - assign $0$memwr$\storage$ls180.v:10062$5_DATA[24:0]$2708 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage$ls180.v:10062$5_EN[24:0]$2709 25'0000000000000000000000000 - assign $0\memdat[24:0] $memrd$\storage$ls180.v:10063$2710_DATA - attribute \src "ls180.v:10061.2-10062.129" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10061.6-10061.60" - case 1'1 - assign $0$memwr$\storage$ls180.v:10062$5_ADDR[2:0]$2707 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage$ls180.v:10062$5_DATA[24:0]$2708 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage$ls180.v:10062$5_EN[24:0]$2709 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat $0\memdat[24:0] - update $memwr$\storage$ls180.v:10062$5_ADDR $0$memwr$\storage$ls180.v:10062$5_ADDR[2:0]$2707 - update $memwr$\storage$ls180.v:10062$5_DATA $0$memwr$\storage$ls180.v:10062$5_DATA[24:0]$2708 - update $memwr$\storage$ls180.v:10062$5_EN $0$memwr$\storage$ls180.v:10062$5_EN[24:0]$2709 - end - attribute \src "ls180.v:10066.1-10067.4" - process $proc$ls180.v:10066$2711 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:10074.1-10078.4" - process $proc$ls180.v:10074$2713 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_1$ls180.v:10076$6_ADDR[2:0]$2714 3'xxx - assign $0$memwr$\storage_1$ls180.v:10076$6_DATA[24:0]$2715 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_1$ls180.v:10076$6_EN[24:0]$2716 25'0000000000000000000000000 - assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10077$2717_DATA - attribute \src "ls180.v:10075.2-10076.131" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10075.6-10075.60" - case 1'1 - assign $0$memwr$\storage_1$ls180.v:10076$6_ADDR[2:0]$2714 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_1$ls180.v:10076$6_DATA[24:0]$2715 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_1$ls180.v:10076$6_EN[24:0]$2716 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_1 $0\memdat_1[24:0] - update $memwr$\storage_1$ls180.v:10076$6_ADDR $0$memwr$\storage_1$ls180.v:10076$6_ADDR[2:0]$2714 - update $memwr$\storage_1$ls180.v:10076$6_DATA $0$memwr$\storage_1$ls180.v:10076$6_DATA[24:0]$2715 - update $memwr$\storage_1$ls180.v:10076$6_EN $0$memwr$\storage_1$ls180.v:10076$6_EN[24:0]$2716 - end - attribute \src "ls180.v:10080.1-10081.4" - process $proc$ls180.v:10080$2718 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:10088.1-10092.4" - process $proc$ls180.v:10088$2720 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_2$ls180.v:10090$7_ADDR[2:0]$2721 3'xxx - assign $0$memwr$\storage_2$ls180.v:10090$7_DATA[24:0]$2722 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_2$ls180.v:10090$7_EN[24:0]$2723 25'0000000000000000000000000 - assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10091$2724_DATA - attribute \src "ls180.v:10089.2-10090.131" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10089.6-10089.60" - case 1'1 - assign $0$memwr$\storage_2$ls180.v:10090$7_ADDR[2:0]$2721 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_2$ls180.v:10090$7_DATA[24:0]$2722 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_2$ls180.v:10090$7_EN[24:0]$2723 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_2 $0\memdat_2[24:0] - update $memwr$\storage_2$ls180.v:10090$7_ADDR $0$memwr$\storage_2$ls180.v:10090$7_ADDR[2:0]$2721 - update $memwr$\storage_2$ls180.v:10090$7_DATA $0$memwr$\storage_2$ls180.v:10090$7_DATA[24:0]$2722 - update $memwr$\storage_2$ls180.v:10090$7_EN $0$memwr$\storage_2$ls180.v:10090$7_EN[24:0]$2723 - end - attribute \src "ls180.v:1009.12-1009.37" - process $proc$ls180.v:1009$3160 - assign { } { } - assign $1\main_pwm0_counter[31:0] 0 - sync always - sync init - update \main_pwm0_counter $1\main_pwm0_counter[31:0] - end - attribute \src "ls180.v:10094.1-10095.4" - process $proc$ls180.v:10094$2725 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:1010.5-1010.36" - process $proc$ls180.v:1010$3161 - assign { } { } - assign $1\main_pwm0_enable_storage[0:0] 1'0 - sync always - sync init - update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] - end - attribute \src "ls180.v:10102.1-10106.4" - process $proc$ls180.v:10102$2727 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_3$ls180.v:10104$8_ADDR[2:0]$2728 3'xxx - assign $0$memwr$\storage_3$ls180.v:10104$8_DATA[24:0]$2729 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_3$ls180.v:10104$8_EN[24:0]$2730 25'0000000000000000000000000 - assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10105$2731_DATA - attribute \src "ls180.v:10103.2-10104.131" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10103.6-10103.60" - case 1'1 - assign $0$memwr$\storage_3$ls180.v:10104$8_ADDR[2:0]$2728 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_3$ls180.v:10104$8_DATA[24:0]$2729 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_3$ls180.v:10104$8_EN[24:0]$2730 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_3 $0\memdat_3[24:0] - update $memwr$\storage_3$ls180.v:10104$8_ADDR $0$memwr$\storage_3$ls180.v:10104$8_ADDR[2:0]$2728 - update $memwr$\storage_3$ls180.v:10104$8_DATA $0$memwr$\storage_3$ls180.v:10104$8_DATA[24:0]$2729 - update $memwr$\storage_3$ls180.v:10104$8_EN $0$memwr$\storage_3$ls180.v:10104$8_EN[24:0]$2730 - end - attribute \src "ls180.v:10108.1-10109.4" - process $proc$ls180.v:10108$2732 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:1011.5-1011.31" - process $proc$ls180.v:1011$3162 - assign { } { } - assign $1\main_pwm0_enable_re[0:0] 1'0 - sync always - sync init - update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] - end - attribute \src "ls180.v:10117.1-10121.4" - process $proc$ls180.v:10117$2734 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_4$ls180.v:10119$9_ADDR[3:0]$2735 4'xxxx - assign $0$memwr$\storage_4$ls180.v:10119$9_DATA[9:0]$2736 10'xxxxxxxxxx - assign $0$memwr$\storage_4$ls180.v:10119$9_EN[9:0]$2737 10'0000000000 - assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10120$2738_DATA - attribute \src "ls180.v:10118.2-10119.77" - switch \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:10118.6-10118.33" - case 1'1 - assign $0$memwr$\storage_4$ls180.v:10119$9_ADDR[3:0]$2735 \main_uart_tx_fifo_wrport_adr - assign $0$memwr$\storage_4$ls180.v:10119$9_DATA[9:0]$2736 \main_uart_tx_fifo_wrport_dat_w - assign $0$memwr$\storage_4$ls180.v:10119$9_EN[9:0]$2737 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_4 $0\memdat_4[9:0] - update $memwr$\storage_4$ls180.v:10119$9_ADDR $0$memwr$\storage_4$ls180.v:10119$9_ADDR[3:0]$2735 - update $memwr$\storage_4$ls180.v:10119$9_DATA $0$memwr$\storage_4$ls180.v:10119$9_DATA[9:0]$2736 - update $memwr$\storage_4$ls180.v:10119$9_EN $0$memwr$\storage_4$ls180.v:10119$9_EN[9:0]$2737 - end - attribute \src "ls180.v:1012.12-1012.43" - process $proc$ls180.v:1012$3163 - assign { } { } - assign $1\main_pwm0_width_storage[31:0] 0 - sync always - sync init - update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] - end - attribute \src "ls180.v:10123.1-10126.4" - process $proc$ls180.v:10123$2739 - assign $0\memdat_5[9:0] \memdat_5 - attribute \src "ls180.v:10124.2-10125.55" - switch \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:10124.6-10124.33" - case 1'1 - assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10125$2740_DATA - case - end - sync posedge \sys_clk_1 - update \memdat_5 $0\memdat_5[9:0] - end - attribute \src "ls180.v:1013.5-1013.30" - process $proc$ls180.v:1013$3164 - assign { } { } - assign $1\main_pwm0_width_re[0:0] 1'0 - sync always - sync init - update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] - end - attribute \src "ls180.v:10134.1-10138.4" - process $proc$ls180.v:10134$2741 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_5$ls180.v:10136$10_ADDR[3:0]$2742 4'xxxx - assign $0$memwr$\storage_5$ls180.v:10136$10_DATA[9:0]$2743 10'xxxxxxxxxx - assign $0$memwr$\storage_5$ls180.v:10136$10_EN[9:0]$2744 10'0000000000 - assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10137$2745_DATA - attribute \src "ls180.v:10135.2-10136.77" - switch \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:10135.6-10135.33" - case 1'1 - assign $0$memwr$\storage_5$ls180.v:10136$10_ADDR[3:0]$2742 \main_uart_rx_fifo_wrport_adr - assign $0$memwr$\storage_5$ls180.v:10136$10_DATA[9:0]$2743 \main_uart_rx_fifo_wrport_dat_w - assign $0$memwr$\storage_5$ls180.v:10136$10_EN[9:0]$2744 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_6 $0\memdat_6[9:0] - update $memwr$\storage_5$ls180.v:10136$10_ADDR $0$memwr$\storage_5$ls180.v:10136$10_ADDR[3:0]$2742 - update $memwr$\storage_5$ls180.v:10136$10_DATA $0$memwr$\storage_5$ls180.v:10136$10_DATA[9:0]$2743 - update $memwr$\storage_5$ls180.v:10136$10_EN $0$memwr$\storage_5$ls180.v:10136$10_EN[9:0]$2744 - end - attribute \src "ls180.v:1014.12-1014.44" - process $proc$ls180.v:1014$3165 - assign { } { } - assign $1\main_pwm0_period_storage[31:0] 0 - sync always - sync init - update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] - end - attribute \src "ls180.v:10140.1-10143.4" - process $proc$ls180.v:10140$2746 - assign $0\memdat_7[9:0] \memdat_7 - attribute \src "ls180.v:10141.2-10142.55" - switch \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:10141.6-10141.33" - case 1'1 - assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10142$2747_DATA - case - end - sync posedge \sys_clk_1 - update \memdat_7 $0\memdat_7[9:0] - end - attribute \src "ls180.v:1015.5-1015.31" - process $proc$ls180.v:1015$3166 - assign { } { } - assign $1\main_pwm0_period_re[0:0] 1'0 - sync always - sync init - update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] - end - attribute \src "ls180.v:10150.1-10154.4" - process $proc$ls180.v:10150$2748 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_6$ls180.v:10152$11_ADDR[4:0]$2749 5'xxxxx - assign $0$memwr$\storage_6$ls180.v:10152$11_DATA[9:0]$2750 10'xxxxxxxxxx - assign $0$memwr$\storage_6$ls180.v:10152$11_EN[9:0]$2751 10'0000000000 - assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10153$2752_DATA - attribute \src "ls180.v:10151.2-10152.85" - switch \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:10151.6-10151.37" - case 1'1 - assign $0$memwr$\storage_6$ls180.v:10152$11_ADDR[4:0]$2749 \main_sdblock2mem_fifo_wrport_adr - assign $0$memwr$\storage_6$ls180.v:10152$11_DATA[9:0]$2750 \main_sdblock2mem_fifo_wrport_dat_w - assign $0$memwr$\storage_6$ls180.v:10152$11_EN[9:0]$2751 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_8 $0\memdat_8[9:0] - update $memwr$\storage_6$ls180.v:10152$11_ADDR $0$memwr$\storage_6$ls180.v:10152$11_ADDR[4:0]$2749 - update $memwr$\storage_6$ls180.v:10152$11_DATA $0$memwr$\storage_6$ls180.v:10152$11_DATA[9:0]$2750 - update $memwr$\storage_6$ls180.v:10152$11_EN $0$memwr$\storage_6$ls180.v:10152$11_EN[9:0]$2751 - end - attribute \src "ls180.v:10156.1-10157.4" - process $proc$ls180.v:10156$2753 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:10164.1-10168.4" - process $proc$ls180.v:10164$2755 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_7$ls180.v:10166$12_ADDR[4:0]$2756 5'xxxxx - assign $0$memwr$\storage_7$ls180.v:10166$12_DATA[9:0]$2757 10'xxxxxxxxxx - assign $0$memwr$\storage_7$ls180.v:10166$12_EN[9:0]$2758 10'0000000000 - assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10167$2759_DATA - attribute \src "ls180.v:10165.2-10166.85" - switch \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:10165.6-10165.37" - case 1'1 - assign $0$memwr$\storage_7$ls180.v:10166$12_ADDR[4:0]$2756 \main_sdmem2block_fifo_wrport_adr - assign $0$memwr$\storage_7$ls180.v:10166$12_DATA[9:0]$2757 \main_sdmem2block_fifo_wrport_dat_w - assign $0$memwr$\storage_7$ls180.v:10166$12_EN[9:0]$2758 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_9 $0\memdat_9[9:0] - update $memwr$\storage_7$ls180.v:10166$12_ADDR $0$memwr$\storage_7$ls180.v:10166$12_ADDR[4:0]$2756 - update $memwr$\storage_7$ls180.v:10166$12_DATA $0$memwr$\storage_7$ls180.v:10166$12_DATA[9:0]$2757 - update $memwr$\storage_7$ls180.v:10166$12_EN $0$memwr$\storage_7$ls180.v:10166$12_EN[9:0]$2758 - end - attribute \src "ls180.v:10170.1-10171.4" - process $proc$ls180.v:10170$2760 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:1019.12-1019.37" - process $proc$ls180.v:1019$3167 - assign { } { } - assign $1\main_pwm1_counter[31:0] 0 - sync always - sync init - update \main_pwm1_counter $1\main_pwm1_counter[31:0] - end - attribute \src "ls180.v:1020.5-1020.36" - process $proc$ls180.v:1020$3168 - assign { } { } - assign $1\main_pwm1_enable_storage[0:0] 1'0 - sync always - sync init - update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] - end - attribute \src "ls180.v:1021.5-1021.31" - process $proc$ls180.v:1021$3169 - assign { } { } - assign $1\main_pwm1_enable_re[0:0] 1'0 - sync always - sync init - update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] - end - attribute \src "ls180.v:1022.12-1022.43" - process $proc$ls180.v:1022$3170 - assign { } { } - assign $1\main_pwm1_width_storage[31:0] 0 - sync always - sync init - update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] - end - attribute \src "ls180.v:1023.5-1023.30" - process $proc$ls180.v:1023$3171 - assign { } { } - assign $1\main_pwm1_width_re[0:0] 1'0 - sync always - sync init - update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] - end - attribute \src "ls180.v:1024.12-1024.44" - process $proc$ls180.v:1024$3172 - assign { } { } - assign $1\main_pwm1_period_storage[31:0] 0 - sync always - sync init - update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] - end - attribute \src "ls180.v:1025.5-1025.31" - process $proc$ls180.v:1025$3173 - assign { } { } - assign $1\main_pwm1_period_re[0:0] 1'0 - sync always - sync init - update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] - end - attribute \src "ls180.v:1029.11-1029.34" - process $proc$ls180.v:1029$3174 - assign { } { } - assign $1\main_i2c_storage[2:0] 3'000 - sync always - sync init - update \main_i2c_storage $1\main_i2c_storage[2:0] - end - attribute \src "ls180.v:1030.5-1030.23" - process $proc$ls180.v:1030$3175 - assign { } { } - assign $1\main_i2c_re[0:0] 1'0 - sync always - sync init - update \main_i2c_re $1\main_i2c_re[0:0] - end - attribute \src "ls180.v:1036.11-1036.46" - process $proc$ls180.v:1036$3176 - assign { } { } - assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 - sync always - sync init - update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] - end - attribute \src "ls180.v:1037.5-1037.33" - process $proc$ls180.v:1037$3177 - assign { } { } - assign $1\main_sdphy_clocker_re[0:0] 1'0 - sync always - sync init - update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] - end - attribute \src "ls180.v:1039.5-1039.35" - process $proc$ls180.v:1039$3178 - assign { } { } - assign $1\main_sdphy_clocker_clk0[0:0] 1'0 - sync always - sync init - update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] - end - attribute \src "ls180.v:1041.11-1041.41" - process $proc$ls180.v:1041$3179 - assign { } { } - assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 - sync always - sync init - update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] - end - attribute \src "ls180.v:1042.5-1042.35" - process $proc$ls180.v:1042$3180 - assign { } { } - assign $1\main_sdphy_clocker_clk1[0:0] 1'0 - sync always - sync init - update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] - end - attribute \src "ls180.v:1043.5-1043.36" - process $proc$ls180.v:1043$3181 - assign { } { } - assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 - sync always - sync init - update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] - end - attribute \src "ls180.v:1047.5-1047.40" - process $proc$ls180.v:1047$3182 - assign { } { } - assign $0\main_sdphy_init_initialize_w[0:0] 1'0 - sync always - update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0] - sync init - end - attribute \src "ls180.v:1052.5-1052.48" - process $proc$ls180.v:1052$3183 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1053.5-1053.50" - process $proc$ls180.v:1053$3184 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] - end - attribute \src "ls180.v:1054.5-1054.51" - process $proc$ls180.v:1054$3185 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - end - attribute \src "ls180.v:1055.11-1055.57" - process $proc$ls180.v:1055$3186 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 - sync always - sync init - update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] - end - attribute \src "ls180.v:1056.5-1056.52" - process $proc$ls180.v:1056$3187 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] - end - attribute \src "ls180.v:1057.11-1057.39" - process $proc$ls180.v:1057$3188 - assign { } { } - assign $1\main_sdphy_init_count[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] - end - attribute \src "ls180.v:1062.5-1062.48" - process $proc$ls180.v:1062$3189 - assign { } { } - assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1063.5-1063.50" - process $proc$ls180.v:1063$3190 - assign { } { } - assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - end - attribute \src "ls180.v:1064.5-1064.51" - process $proc$ls180.v:1064$3191 - assign { } { } - assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - end - attribute \src "ls180.v:1065.11-1065.57" - process $proc$ls180.v:1065$3192 - assign { } { } - assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1066.5-1066.52" - process $proc$ls180.v:1066$3193 - assign { } { } - assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1067.5-1067.38" - process $proc$ls180.v:1067$3194 - assign { } { } - assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] - end - attribute \src "ls180.v:1068.5-1068.38" - process $proc$ls180.v:1068$3195 - assign { } { } - assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] - end - attribute \src "ls180.v:1069.5-1069.37" - process $proc$ls180.v:1069$3196 - assign { } { } - assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] - end - attribute \src "ls180.v:1070.11-1070.51" - process $proc$ls180.v:1070$3197 - assign { } { } - assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] - end - attribute \src "ls180.v:1071.5-1071.32" - process $proc$ls180.v:1071$3198 - assign { } { } - assign $1\main_sdphy_cmdw_done[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] - end - attribute \src "ls180.v:1072.11-1072.39" - process $proc$ls180.v:1072$3199 - assign { } { } - assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] - end - attribute \src "ls180.v:1075.5-1075.49" - process $proc$ls180.v:1075$3200 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] - sync init - end - attribute \src "ls180.v:1076.5-1076.48" - process $proc$ls180.v:1076$3201 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] - sync init - end - attribute \src "ls180.v:1077.5-1077.55" - process $proc$ls180.v:1077$3202 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] - sync init - end - attribute \src "ls180.v:1079.5-1079.57" - process $proc$ls180.v:1079$3203 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1080.5-1080.58" - process $proc$ls180.v:1080$3204 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1082.11-1082.64" - process $proc$ls180.v:1082$3205 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1083.5-1083.59" - process $proc$ls180.v:1083$3206 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1085.5-1085.48" - process $proc$ls180.v:1085$3207 - assign { } { } - assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1086.5-1086.50" - process $proc$ls180.v:1086$3208 - assign { } { } - assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - end - attribute \src "ls180.v:1087.5-1087.51" - process $proc$ls180.v:1087$3209 - assign { } { } - assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - end - attribute \src "ls180.v:1088.11-1088.57" - process $proc$ls180.v:1088$3210 - assign { } { } - assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1089.5-1089.52" - process $proc$ls180.v:1089$3211 - assign { } { } - assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1090.5-1090.38" - process $proc$ls180.v:1090$3212 - assign { } { } - assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] - end - attribute \src "ls180.v:1091.5-1091.38" - process $proc$ls180.v:1091$3213 - assign { } { } - assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] - end - attribute \src "ls180.v:1092.5-1092.37" - process $proc$ls180.v:1092$3214 - assign { } { } - assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] - end - attribute \src "ls180.v:1093.11-1093.53" - process $proc$ls180.v:1093$3215 - assign { } { } - assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] - end - attribute \src "ls180.v:1094.5-1094.40" - process $proc$ls180.v:1094$3216 - assign { } { } - assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] - end - attribute \src "ls180.v:1095.5-1095.40" - process $proc$ls180.v:1095$3217 - assign { } { } - assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] - end - attribute \src "ls180.v:1096.5-1096.39" - process $proc$ls180.v:1096$3218 - assign { } { } - assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] - end - attribute \src "ls180.v:1097.11-1097.53" - process $proc$ls180.v:1097$3219 - assign { } { } - assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] - end - attribute \src "ls180.v:1098.11-1098.55" - process $proc$ls180.v:1098$3220 - assign { } { } - assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - sync always - sync init - update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] - end - attribute \src "ls180.v:1099.12-1099.48" - process $proc$ls180.v:1099$3221 - assign { } { } - assign $1\main_sdphy_cmdr_timeout[31:0] 500000 - sync always - sync init - update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] - end - attribute \src "ls180.v:1100.11-1100.39" - process $proc$ls180.v:1100$3222 - assign { } { } - assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] - end - attribute \src "ls180.v:1102.5-1102.46" - process $proc$ls180.v:1102$3223 - assign { } { } - assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 - sync always - update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] - sync init - end - attribute \src "ls180.v:1113.5-1113.53" - process $proc$ls180.v:1113$3224 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - end - attribute \src "ls180.v:1118.5-1118.36" - process $proc$ls180.v:1118$3225 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] - end - attribute \src "ls180.v:1121.5-1121.53" - process $proc$ls180.v:1121$3226 - assign { } { } - assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 - sync always - update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] - sync init - end - attribute \src "ls180.v:1122.5-1122.52" - process $proc$ls180.v:1122$3227 - assign { } { } - assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 - sync always - update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] - sync init - end - attribute \src "ls180.v:1126.5-1126.55" - process $proc$ls180.v:1126$3228 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - end - attribute \src "ls180.v:1127.5-1127.54" - process $proc$ls180.v:1127$3229 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - end - attribute \src "ls180.v:1128.11-1128.68" - process $proc$ls180.v:1128$3230 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1129.11-1129.81" - process $proc$ls180.v:1129$3231 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - end - attribute \src "ls180.v:1130.11-1130.54" - process $proc$ls180.v:1130$3232 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] - end - attribute \src "ls180.v:1132.5-1132.53" - process $proc$ls180.v:1132$3233 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - end - attribute \src "ls180.v:1143.5-1143.49" - process $proc$ls180.v:1143$3234 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - end - attribute \src "ls180.v:1145.5-1145.49" - process $proc$ls180.v:1145$3235 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - end - attribute \src "ls180.v:1146.5-1146.48" - process $proc$ls180.v:1146$3236 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - end - attribute \src "ls180.v:1147.11-1147.62" - process $proc$ls180.v:1147$3237 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - end - attribute \src "ls180.v:1148.5-1148.38" - process $proc$ls180.v:1148$3238 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] - end - attribute \src "ls180.v:1153.5-1153.49" - process $proc$ls180.v:1153$3239 - assign { } { } - assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1154.5-1154.51" - process $proc$ls180.v:1154$3240 - assign { } { } - assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1155.5-1155.52" - process $proc$ls180.v:1155$3241 - assign { } { } - assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1156.11-1156.58" - process $proc$ls180.v:1156$3242 - assign { } { } - assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - sync always - sync init - update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] - end - attribute \src "ls180.v:1157.5-1157.53" - process $proc$ls180.v:1157$3243 - assign { } { } - assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - end - attribute \src "ls180.v:1158.5-1158.39" - process $proc$ls180.v:1158$3244 - assign { } { } - assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] - end - attribute \src "ls180.v:1159.5-1159.39" - process $proc$ls180.v:1159$3245 - assign { } { } - assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] - end - attribute \src "ls180.v:116.5-116.49" - process $proc$ls180.v:116$2785 - assign { } { } - assign $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] - end - attribute \src "ls180.v:1160.5-1160.39" - process $proc$ls180.v:1160$3246 - assign { } { } - assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] - end - attribute \src "ls180.v:1161.5-1161.38" - process $proc$ls180.v:1161$3247 - assign { } { } - assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] - end - attribute \src "ls180.v:1162.11-1162.52" - process $proc$ls180.v:1162$3248 - assign { } { } - assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] - end - attribute \src "ls180.v:1163.5-1163.33" - process $proc$ls180.v:1163$3249 - assign { } { } - assign $1\main_sdphy_dataw_stop[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] - end - attribute \src "ls180.v:1164.11-1164.40" - process $proc$ls180.v:1164$3250 - assign { } { } - assign $1\main_sdphy_dataw_count[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] - end - attribute \src "ls180.v:1165.5-1165.50" - process $proc$ls180.v:1165$3251 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] - sync init - end - attribute \src "ls180.v:1167.5-1167.50" - process $proc$ls180.v:1167$3252 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] - sync init - end - attribute \src "ls180.v:1168.5-1168.49" - process $proc$ls180.v:1168$3253 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] - sync init - end - attribute \src "ls180.v:1169.5-1169.56" - process $proc$ls180.v:1169$3254 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] - sync init - end - attribute \src "ls180.v:1170.5-1170.58" - process $proc$ls180.v:1170$3255 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] - sync init - end - attribute \src "ls180.v:1171.5-1171.58" - process $proc$ls180.v:1171$3256 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1172.5-1172.59" - process $proc$ls180.v:1172$3257 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1173.11-1173.65" - process $proc$ls180.v:1173$3258 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] - sync init - end - attribute \src "ls180.v:1174.11-1174.65" - process $proc$ls180.v:1174$3259 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1175.5-1175.60" - process $proc$ls180.v:1175$3260 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1176.5-1176.34" - process $proc$ls180.v:1176$3261 - assign { } { } - assign $1\main_sdphy_dataw_start[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] - end - attribute \src "ls180.v:1177.5-1177.34" - process $proc$ls180.v:1177$3262 - assign { } { } - assign $1\main_sdphy_dataw_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] - end - attribute \src "ls180.v:1178.5-1178.34" - process $proc$ls180.v:1178$3263 - assign { } { } - assign $1\main_sdphy_dataw_error[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] - end - attribute \src "ls180.v:118.5-118.49" - process $proc$ls180.v:118$2786 - assign { } { } - assign $0\main_libresocsim_libresoc_jtag_wb_err[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_jtag_wb_err $0\main_libresocsim_libresoc_jtag_wb_err[0:0] - sync init - end - attribute \src "ls180.v:1180.5-1180.47" - process $proc$ls180.v:1180$3264 - assign { } { } - assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 - sync always - update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] - sync init - end - attribute \src "ls180.v:1191.5-1191.54" - process $proc$ls180.v:1191$3265 - assign { } { } - assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] - end - attribute \src "ls180.v:1196.5-1196.37" - process $proc$ls180.v:1196$3266 - assign { } { } - assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] - end - attribute \src "ls180.v:1199.5-1199.54" - process $proc$ls180.v:1199$3267 - assign { } { } - assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 - sync always - update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] - sync init - end - attribute \src "ls180.v:1200.5-1200.53" - process $proc$ls180.v:1200$3268 - assign { } { } - assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 - sync always - update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] - sync init - end - attribute \src "ls180.v:1204.5-1204.56" - process $proc$ls180.v:1204$3269 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] - end - attribute \src "ls180.v:1205.5-1205.55" - process $proc$ls180.v:1205$3270 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] - end - attribute \src "ls180.v:1206.11-1206.69" - process $proc$ls180.v:1206$3271 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1207.11-1207.82" - process $proc$ls180.v:1207$3272 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - end - attribute \src "ls180.v:1208.11-1208.55" - process $proc$ls180.v:1208$3273 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] - end - attribute \src "ls180.v:1210.5-1210.54" - process $proc$ls180.v:1210$3274 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - end - attribute \src "ls180.v:1221.5-1221.50" - process $proc$ls180.v:1221$3275 - assign { } { } - assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] - end - attribute \src "ls180.v:1223.5-1223.50" - process $proc$ls180.v:1223$3276 - assign { } { } - assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] - end - attribute \src "ls180.v:1224.5-1224.49" - process $proc$ls180.v:1224$3277 - assign { } { } - assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] - end - attribute \src "ls180.v:1225.11-1225.63" - process $proc$ls180.v:1225$3278 - assign { } { } - assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - end - attribute \src "ls180.v:1226.5-1226.39" - process $proc$ls180.v:1226$3279 - assign { } { } - assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] - end - attribute \src "ls180.v:1229.5-1229.50" - process $proc$ls180.v:1229$3280 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0] - sync init - end - attribute \src "ls180.v:1230.5-1230.49" - process $proc$ls180.v:1230$3281 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0] - sync init - end - attribute \src "ls180.v:1231.5-1231.56" - process $proc$ls180.v:1231$3282 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] - sync init - end - attribute \src "ls180.v:1233.5-1233.58" - process $proc$ls180.v:1233$3283 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1234.5-1234.59" - process $proc$ls180.v:1234$3284 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1236.11-1236.65" - process $proc$ls180.v:1236$3285 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1237.5-1237.60" - process $proc$ls180.v:1237$3286 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1239.5-1239.49" - process $proc$ls180.v:1239$3287 - assign { } { } - assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1240.5-1240.51" - process $proc$ls180.v:1240$3288 - assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1241.5-1241.52" - process $proc$ls180.v:1241$3289 - assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1242.11-1242.58" - process $proc$ls180.v:1242$3290 - assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1243.5-1243.53" - process $proc$ls180.v:1243$3291 - assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1244.5-1244.39" - process $proc$ls180.v:1244$3292 - assign { } { } - assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] - end - attribute \src "ls180.v:1245.5-1245.39" - process $proc$ls180.v:1245$3293 - assign { } { } - assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] - end - attribute \src "ls180.v:1246.5-1246.38" - process $proc$ls180.v:1246$3294 - assign { } { } - assign $1\main_sdphy_datar_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] - end - attribute \src "ls180.v:1247.11-1247.61" - process $proc$ls180.v:1247$3295 - assign { } { } - assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 - sync always - sync init - update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] - end - attribute \src "ls180.v:1248.5-1248.41" - process $proc$ls180.v:1248$3296 - assign { } { } - assign $1\main_sdphy_datar_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] - end - attribute \src "ls180.v:1249.5-1249.41" - process $proc$ls180.v:1249$3297 - assign { } { } - assign $1\main_sdphy_datar_source_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] - end - attribute \src "ls180.v:1250.5-1250.41" - process $proc$ls180.v:1250$3298 - assign { } { } - assign $0\main_sdphy_datar_source_first[0:0] 1'0 - sync always - update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0] - sync init - end - attribute \src "ls180.v:1251.5-1251.40" - process $proc$ls180.v:1251$3299 - assign { } { } - assign $1\main_sdphy_datar_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] - end - attribute \src "ls180.v:1252.11-1252.54" - process $proc$ls180.v:1252$3300 - assign { } { } - assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] - end - attribute \src "ls180.v:1253.11-1253.56" - process $proc$ls180.v:1253$3301 - assign { } { } - assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 - sync always - sync init - update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] - end - attribute \src "ls180.v:1254.5-1254.33" - process $proc$ls180.v:1254$3302 - assign { } { } - assign $1\main_sdphy_datar_stop[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] - end - attribute \src "ls180.v:1255.12-1255.49" - process $proc$ls180.v:1255$3303 - assign { } { } - assign $1\main_sdphy_datar_timeout[31:0] 500000 - sync always - sync init - update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] - end - attribute \src "ls180.v:1256.11-1256.41" - process $proc$ls180.v:1256$3304 - assign { } { } - assign $1\main_sdphy_datar_count[9:0] 10'0000000000 - sync always - sync init - update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] - end - attribute \src "ls180.v:1258.5-1258.48" - process $proc$ls180.v:1258$3305 - assign { } { } - assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 - sync always - update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0] - sync init - end - attribute \src "ls180.v:1269.5-1269.55" - process $proc$ls180.v:1269$3306 - assign { } { } - assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] - end - attribute \src "ls180.v:1274.5-1274.38" - process $proc$ls180.v:1274$3307 - assign { } { } - assign $1\main_sdphy_datar_datar_run[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] - end - attribute \src "ls180.v:1277.5-1277.55" - process $proc$ls180.v:1277$3308 - assign { } { } - assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 - sync always - update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0] - sync init - end - attribute \src "ls180.v:1278.5-1278.54" - process $proc$ls180.v:1278$3309 - assign { } { } - assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 - sync always - update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0] - sync init - end - attribute \src "ls180.v:128.5-128.65" - process $proc$ls180.v:128$2787 - assign { } { } - assign $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 - sync always - sync init - update \main_libresocsim_libresoc_constraintmanager0_uart0_tx $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] - end - attribute \src "ls180.v:1282.5-1282.57" - process $proc$ls180.v:1282$3310 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] - end - attribute \src "ls180.v:1283.5-1283.56" - process $proc$ls180.v:1283$3311 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] - end - attribute \src "ls180.v:1284.11-1284.70" - process $proc$ls180.v:1284$3312 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1285.11-1285.83" - process $proc$ls180.v:1285$3313 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 - sync always - sync init - update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - end - attribute \src "ls180.v:1286.5-1286.50" - process $proc$ls180.v:1286$3314 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] - end - attribute \src "ls180.v:1288.5-1288.55" - process $proc$ls180.v:1288$3315 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] - end - attribute \src "ls180.v:1299.5-1299.51" - process $proc$ls180.v:1299$3316 - assign { } { } - assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] - end - attribute \src "ls180.v:1301.5-1301.51" - process $proc$ls180.v:1301$3317 - assign { } { } - assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] - end - attribute \src "ls180.v:1302.5-1302.50" - process $proc$ls180.v:1302$3318 - assign { } { } - assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] - end - attribute \src "ls180.v:1303.11-1303.64" - process $proc$ls180.v:1303$3319 - assign { } { } - assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] - end - attribute \src "ls180.v:1304.5-1304.40" - process $proc$ls180.v:1304$3320 - assign { } { } - assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] - end - attribute \src "ls180.v:1306.5-1306.35" - process $proc$ls180.v:1306$3321 - assign { } { } - assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 - sync always - sync init - update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] - end - attribute \src "ls180.v:1309.11-1309.42" - process $proc$ls180.v:1309$3322 - assign { } { } - assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 - sync always - sync init - update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] - end - attribute \src "ls180.v:1322.12-1322.52" - process $proc$ls180.v:1322$3323 - assign { } { } - assign $1\main_sdcore_cmd_argument_storage[31:0] 0 - sync always - sync init - update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] - end - attribute \src "ls180.v:1323.5-1323.39" - process $proc$ls180.v:1323$3324 - assign { } { } - assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] - end - attribute \src "ls180.v:1324.12-1324.51" - process $proc$ls180.v:1324$3325 - assign { } { } - assign $1\main_sdcore_cmd_command_storage[31:0] 0 - sync always - sync init - update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] - end - attribute \src "ls180.v:1325.5-1325.38" - process $proc$ls180.v:1325$3326 - assign { } { } - assign $1\main_sdcore_cmd_command_re[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] - end - attribute \src "ls180.v:1329.5-1329.34" - process $proc$ls180.v:1329$3327 - assign { } { } - assign $0\main_sdcore_cmd_send_w[0:0] 1'0 - sync always - update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0] - sync init - end - attribute \src "ls180.v:1330.13-1330.53" - process $proc$ls180.v:1330$3328 - assign { } { } - assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] - end - attribute \src "ls180.v:1336.11-1336.51" - process $proc$ls180.v:1336$3329 - assign { } { } - assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 - sync always - sync init - update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] - end - attribute \src "ls180.v:1337.5-1337.39" - process $proc$ls180.v:1337$3330 - assign { } { } - assign $1\main_sdcore_block_length_re[0:0] 1'0 - sync always - sync init - update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] - end - attribute \src "ls180.v:1338.12-1338.51" - process $proc$ls180.v:1338$3331 - assign { } { } - assign $1\main_sdcore_block_count_storage[31:0] 0 - sync always - sync init - update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] - end - attribute \src "ls180.v:1339.5-1339.38" - process $proc$ls180.v:1339$3332 - assign { } { } - assign $1\main_sdcore_block_count_re[0:0] 1'0 - sync always - sync init - update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] - end - attribute \src "ls180.v:1340.11-1340.51" - process $proc$ls180.v:1340$3333 - assign { } { } - assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - sync always - sync init - update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] - end - attribute \src "ls180.v:138.12-138.71" - process $proc$ls180.v:138$2788 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0] - end - attribute \src "ls180.v:1382.11-1382.47" - process $proc$ls180.v:1382$3334 - assign { } { } - assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 - sync always - sync init - update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] - end - attribute \src "ls180.v:1386.5-1386.49" - process $proc$ls180.v:1386$3335 - assign { } { } - assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] - end - attribute \src "ls180.v:139.12-139.73" - process $proc$ls180.v:139$2789 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:1390.5-1390.51" - process $proc$ls180.v:1390$3336 - assign { } { } - assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] - end - attribute \src "ls180.v:1391.5-1391.51" - process $proc$ls180.v:1391$3337 - assign { } { } - assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] - end - attribute \src "ls180.v:1392.5-1392.51" - process $proc$ls180.v:1392$3338 - assign { } { } - assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 - sync always - update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0] - sync init - end - attribute \src "ls180.v:1393.5-1393.50" - process $proc$ls180.v:1393$3339 - assign { } { } - assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] - end - attribute \src "ls180.v:1394.11-1394.64" - process $proc$ls180.v:1394$3340 - assign { } { } - assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] - end - attribute \src "ls180.v:1395.11-1395.48" - process $proc$ls180.v:1395$3341 - assign { } { } - assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 - sync always - sync init - update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] - end - attribute \src "ls180.v:1396.12-1396.59" - process $proc$ls180.v:1396$3342 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - end - attribute \src "ls180.v:1400.12-1400.55" - process $proc$ls180.v:1400$3343 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] - end - attribute \src "ls180.v:1403.12-1403.59" - process $proc$ls180.v:1403$3344 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - end - attribute \src "ls180.v:1407.12-1407.55" - process $proc$ls180.v:1407$3345 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] - end - attribute \src "ls180.v:141.11-141.69" - process $proc$ls180.v:141$2790 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0] - end - attribute \src "ls180.v:1410.12-1410.59" - process $proc$ls180.v:1410$3346 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - end - attribute \src "ls180.v:1414.12-1414.55" - process $proc$ls180.v:1414$3347 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] - end - attribute \src "ls180.v:1417.12-1417.59" - process $proc$ls180.v:1417$3348 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - end - attribute \src "ls180.v:142.5-142.63" - process $proc$ls180.v:142$2791 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0] - end - attribute \src "ls180.v:1421.12-1421.55" - process $proc$ls180.v:1421$3349 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] - end - attribute \src "ls180.v:1424.12-1424.54" - process $proc$ls180.v:1424$3350 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] - end - attribute \src "ls180.v:1425.12-1425.54" - process $proc$ls180.v:1425$3351 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] - end - attribute \src "ls180.v:1426.12-1426.54" - process $proc$ls180.v:1426$3352 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] - end - attribute \src "ls180.v:1427.12-1427.54" - process $proc$ls180.v:1427$3353 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] - end - attribute \src "ls180.v:1428.5-1428.48" - process $proc$ls180.v:1428$3354 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] - end - attribute \src "ls180.v:1429.5-1429.48" - process $proc$ls180.v:1429$3355 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] - end - attribute \src "ls180.v:143.5-143.63" - process $proc$ls180.v:143$2792 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0] - end - attribute \src "ls180.v:1430.5-1430.48" - process $proc$ls180.v:1430$3356 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] - end - attribute \src "ls180.v:1431.5-1431.47" - process $proc$ls180.v:1431$3357 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] - end - attribute \src "ls180.v:1432.11-1432.61" - process $proc$ls180.v:1432$3358 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] - end - attribute \src "ls180.v:1433.5-1433.50" - process $proc$ls180.v:1433$3359 - assign { } { } - assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] - end - attribute \src "ls180.v:1435.5-1435.50" - process $proc$ls180.v:1435$3360 - assign { } { } - assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 - sync always - update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0] - sync init - end - attribute \src "ls180.v:1438.11-1438.47" - process $proc$ls180.v:1438$3361 - assign { } { } - assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 - sync always - sync init - update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] - end - attribute \src "ls180.v:1439.11-1439.47" - process $proc$ls180.v:1439$3362 - assign { } { } - assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - sync always - sync init - update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] - end - attribute \src "ls180.v:1440.12-1440.58" - process $proc$ls180.v:1440$3363 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - end - attribute \src "ls180.v:1444.12-1444.54" - process $proc$ls180.v:1444$3364 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] - end - attribute \src "ls180.v:1445.5-1445.46" - process $proc$ls180.v:1445$3365 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] - end - attribute \src "ls180.v:1447.12-1447.58" - process $proc$ls180.v:1447$3366 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - end - attribute \src "ls180.v:145.5-145.62" - process $proc$ls180.v:145$2793 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0] - end - attribute \src "ls180.v:1451.12-1451.54" - process $proc$ls180.v:1451$3367 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] - end - attribute \src "ls180.v:1452.5-1452.46" - process $proc$ls180.v:1452$3368 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] - end - attribute \src "ls180.v:1454.12-1454.58" - process $proc$ls180.v:1454$3369 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - end - attribute \src "ls180.v:1458.12-1458.54" - process $proc$ls180.v:1458$3370 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] - end - attribute \src "ls180.v:1459.5-1459.46" - process $proc$ls180.v:1459$3371 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] - end - attribute \src "ls180.v:146.11-146.69" - process $proc$ls180.v:146$2794 - assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000 - sync always - update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0] - sync init - end - attribute \src "ls180.v:1461.12-1461.58" - process $proc$ls180.v:1461$3372 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - end - attribute \src "ls180.v:1465.12-1465.54" - process $proc$ls180.v:1465$3373 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] - end - attribute \src "ls180.v:1466.5-1466.46" - process $proc$ls180.v:1466$3374 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] - end - attribute \src "ls180.v:1468.12-1468.53" - process $proc$ls180.v:1468$3375 - assign { } { } - assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] - end - attribute \src "ls180.v:1469.12-1469.53" - process $proc$ls180.v:1469$3376 - assign { } { } - assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] - end - attribute \src "ls180.v:147.11-147.69" - process $proc$ls180.v:147$2795 - assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00 - sync always - update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0] - sync init - end - attribute \src "ls180.v:1470.12-1470.53" - process $proc$ls180.v:1470$3377 - assign { } { } - assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] - end - attribute \src "ls180.v:1471.12-1471.53" - process $proc$ls180.v:1471$3378 - assign { } { } - assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] - end - attribute \src "ls180.v:1472.5-1472.43" - process $proc$ls180.v:1472$3379 - assign { } { } - assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] - end - attribute \src "ls180.v:1473.12-1473.51" - process $proc$ls180.v:1473$3380 - assign { } { } - assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] - end - attribute \src "ls180.v:1474.12-1474.51" - process $proc$ls180.v:1474$3381 - assign { } { } - assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] - end - attribute \src "ls180.v:1475.12-1475.51" - process $proc$ls180.v:1475$3382 - assign { } { } - assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] - end - attribute \src "ls180.v:1476.12-1476.51" - process $proc$ls180.v:1476$3383 - assign { } { } - assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] - end - attribute \src "ls180.v:1478.11-1478.39" - process $proc$ls180.v:1478$3384 - assign { } { } - assign $1\main_sdcore_cmd_count[2:0] 3'000 - sync always - sync init - update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] - end - attribute \src "ls180.v:1479.5-1479.32" - process $proc$ls180.v:1479$3385 - assign { } { } - assign $1\main_sdcore_cmd_done[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] - end - attribute \src "ls180.v:1480.5-1480.33" - process $proc$ls180.v:1480$3386 - assign { } { } - assign $1\main_sdcore_cmd_error[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] - end - attribute \src "ls180.v:1481.5-1481.35" - process $proc$ls180.v:1481$3387 - assign { } { } - assign $1\main_sdcore_cmd_timeout[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] - end - attribute \src "ls180.v:1483.12-1483.42" - process $proc$ls180.v:1483$3388 - assign { } { } - assign $1\main_sdcore_data_count[31:0] 0 - sync always - sync init - update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] - end - attribute \src "ls180.v:1484.5-1484.33" - process $proc$ls180.v:1484$3389 - assign { } { } - assign $1\main_sdcore_data_done[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] - end - attribute \src "ls180.v:1485.5-1485.34" - process $proc$ls180.v:1485$3390 - assign { } { } - assign $1\main_sdcore_data_error[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] - end - attribute \src "ls180.v:1486.5-1486.36" - process $proc$ls180.v:1486$3391 - assign { } { } - assign $1\main_sdcore_data_timeout[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] - end - attribute \src "ls180.v:149.5-149.44" - process $proc$ls180.v:149$2796 - assign { } { } - assign $1\main_libresocsim_converter0_skip[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0] - end - attribute \src "ls180.v:1495.11-1495.41" - process $proc$ls180.v:1495$3392 - assign { } { } - assign $0\main_interface0_bus_cti[2:0] 3'000 - sync always - update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0] - sync init - end - attribute \src "ls180.v:1496.11-1496.41" - process $proc$ls180.v:1496$3393 - assign { } { } - assign $0\main_interface0_bus_bte[1:0] 2'00 - sync always - update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0] - sync init - end - attribute \src "ls180.v:150.5-150.47" - process $proc$ls180.v:150$2797 - assign { } { } - assign $1\main_libresocsim_converter0_counter[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0] - end - attribute \src "ls180.v:1519.11-1519.45" - process $proc$ls180.v:1519$3394 - assign { } { } - assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 - sync always - sync init - update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] - end - attribute \src "ls180.v:152.12-152.53" - process $proc$ls180.v:152$2798 - assign { } { } - assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0] - end - attribute \src "ls180.v:1520.5-1520.41" - process $proc$ls180.v:1520$3395 - assign { } { } - assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 - sync always - update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:1521.11-1521.47" - process $proc$ls180.v:1521$3396 - assign { } { } - assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 - sync always - sync init - update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] - end - attribute \src "ls180.v:1522.11-1522.47" - process $proc$ls180.v:1522$3397 - assign { } { } - assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 - sync always - sync init - update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] - end - attribute \src "ls180.v:1523.11-1523.50" - process $proc$ls180.v:1523$3398 - assign { } { } - assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 - sync always - sync init - update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:153.12-153.71" - process $proc$ls180.v:153$2799 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0] - end - attribute \src "ls180.v:154.12-154.73" - process $proc$ls180.v:154$2800 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:1543.5-1543.51" - process $proc$ls180.v:1543$3399 - assign { } { } - assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] - end - attribute \src "ls180.v:1544.5-1544.50" - process $proc$ls180.v:1544$3400 - assign { } { } - assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] - end - attribute \src "ls180.v:1545.12-1545.66" - process $proc$ls180.v:1545$3401 - assign { } { } - assign $1\main_sdblock2mem_converter_source_payload_data[31:0] 0 - sync always - sync init - update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[31:0] - end - attribute \src "ls180.v:1546.11-1546.77" - process $proc$ls180.v:1546$3402 - assign { } { } - assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] 3'000 - sync always - sync init - update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] - end - attribute \src "ls180.v:1547.11-1547.50" - process $proc$ls180.v:1547$3403 - assign { } { } - assign $1\main_sdblock2mem_converter_demux[1:0] 2'00 - sync always - sync init - update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[1:0] - end - attribute \src "ls180.v:1549.5-1549.49" - process $proc$ls180.v:1549$3404 - assign { } { } - assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] - end - attribute \src "ls180.v:1555.5-1555.45" - process $proc$ls180.v:1555$3405 - assign { } { } - assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] - end - attribute \src "ls180.v:1557.12-1557.62" - process $proc$ls180.v:1557$3406 - assign { } { } - assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 - sync always - sync init - update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] - end - attribute \src "ls180.v:1558.12-1558.60" - process $proc$ls180.v:1558$3407 - assign { } { } - assign $1\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 - sync always - sync init - update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] - end - attribute \src "ls180.v:156.11-156.69" - process $proc$ls180.v:156$2801 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0] - end - attribute \src "ls180.v:1560.5-1560.57" - process $proc$ls180.v:1560$3408 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - end - attribute \src "ls180.v:1564.12-1564.67" - process $proc$ls180.v:1564$3409 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - end - attribute \src "ls180.v:1565.5-1565.54" - process $proc$ls180.v:1565$3410 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - end - attribute \src "ls180.v:1566.12-1566.69" - process $proc$ls180.v:1566$3411 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - end - attribute \src "ls180.v:1567.5-1567.56" - process $proc$ls180.v:1567$3412 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - end - attribute \src "ls180.v:1568.5-1568.61" - process $proc$ls180.v:1568$3413 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - end - attribute \src "ls180.v:1569.5-1569.56" - process $proc$ls180.v:1569$3414 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - end - attribute \src "ls180.v:157.5-157.63" - process $proc$ls180.v:157$2802 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0] - end - attribute \src "ls180.v:1570.5-1570.53" - process $proc$ls180.v:1570$3415 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] - end - attribute \src "ls180.v:1572.5-1572.59" - process $proc$ls180.v:1572$3416 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - end - attribute \src "ls180.v:1573.5-1573.54" - process $proc$ls180.v:1573$3417 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - end - attribute \src "ls180.v:1575.12-1575.61" - process $proc$ls180.v:1575$3418 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] - end - attribute \src "ls180.v:1578.12-1578.43" - process $proc$ls180.v:1578$3419 - assign { } { } - assign $1\main_interface1_bus_adr[31:0] 0 - sync always - sync init - update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] - end - attribute \src "ls180.v:1579.12-1579.45" - process $proc$ls180.v:1579$3420 - assign { } { } - assign $0\main_interface1_bus_dat_w[31:0] 0 - sync always - update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[31:0] - sync init - end - attribute \src "ls180.v:158.5-158.63" - process $proc$ls180.v:158$2803 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0] - end - attribute \src "ls180.v:1581.11-1581.41" - process $proc$ls180.v:1581$3421 - assign { } { } - assign $1\main_interface1_bus_sel[3:0] 4'0000 - sync always - sync init - update \main_interface1_bus_sel $1\main_interface1_bus_sel[3:0] - end - attribute \src "ls180.v:1582.5-1582.35" - process $proc$ls180.v:1582$3422 - assign { } { } - assign $1\main_interface1_bus_cyc[0:0] 1'0 - sync always - sync init - update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] - end - attribute \src "ls180.v:1583.5-1583.35" - process $proc$ls180.v:1583$3423 - assign { } { } - assign $1\main_interface1_bus_stb[0:0] 1'0 - sync always - sync init - update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] - end - attribute \src "ls180.v:1585.5-1585.34" - process $proc$ls180.v:1585$3424 - assign { } { } - assign $1\main_interface1_bus_we[0:0] 1'0 - sync always - sync init - update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] - end - attribute \src "ls180.v:1586.11-1586.41" - process $proc$ls180.v:1586$3425 - assign { } { } - assign $0\main_interface1_bus_cti[2:0] 3'000 - sync always - update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0] - sync init - end - attribute \src "ls180.v:1587.11-1587.41" - process $proc$ls180.v:1587$3426 - assign { } { } - assign $0\main_interface1_bus_bte[1:0] 2'00 - sync always - update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] - sync init - end - attribute \src "ls180.v:1594.5-1594.43" - process $proc$ls180.v:1594$3427 - assign { } { } - assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] - end - attribute \src "ls180.v:1595.5-1595.43" - process $proc$ls180.v:1595$3428 - assign { } { } - assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] - end - attribute \src "ls180.v:1596.5-1596.42" - process $proc$ls180.v:1596$3429 - assign { } { } - assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] - end - attribute \src "ls180.v:1597.12-1597.61" - process $proc$ls180.v:1597$3430 - assign { } { } - assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] - end - attribute \src "ls180.v:1598.5-1598.45" - process $proc$ls180.v:1598$3431 - assign { } { } - assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] - end - attribute \src "ls180.v:160.5-160.62" - process $proc$ls180.v:160$2804 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0] - end - attribute \src "ls180.v:1600.5-1600.45" - process $proc$ls180.v:1600$3432 - assign { } { } - assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 - sync always - update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0] - sync init - end - attribute \src "ls180.v:1601.5-1601.44" - process $proc$ls180.v:1601$3433 - assign { } { } - assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] - end - attribute \src "ls180.v:1602.12-1602.60" - process $proc$ls180.v:1602$3434 - assign { } { } - assign $1\main_sdmem2block_dma_source_payload_data[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[31:0] - end - attribute \src "ls180.v:1603.12-1603.45" - process $proc$ls180.v:1603$3435 - assign { } { } - assign $1\main_sdmem2block_dma_data[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[31:0] - end - attribute \src "ls180.v:1604.12-1604.53" - process $proc$ls180.v:1604$3436 - assign { } { } - assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] - end - attribute \src "ls180.v:1605.5-1605.40" - process $proc$ls180.v:1605$3437 - assign { } { } - assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] - end - attribute \src "ls180.v:1606.12-1606.55" - process $proc$ls180.v:1606$3438 - assign { } { } - assign $1\main_sdmem2block_dma_length_storage[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] - end - attribute \src "ls180.v:1607.5-1607.42" - process $proc$ls180.v:1607$3439 - assign { } { } - assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] - end - attribute \src "ls180.v:1608.5-1608.47" - process $proc$ls180.v:1608$3440 - assign { } { } - assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] - end - attribute \src "ls180.v:1609.5-1609.42" - process $proc$ls180.v:1609$3441 - assign { } { } - assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] - end - attribute \src "ls180.v:161.11-161.69" - process $proc$ls180.v:161$2805 - assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000 - sync always - update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0] - sync init - end - attribute \src "ls180.v:1610.5-1610.44" - process $proc$ls180.v:1610$3442 - assign { } { } - assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] - end - attribute \src "ls180.v:1612.5-1612.45" - process $proc$ls180.v:1612$3443 - assign { } { } - assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] - end - attribute \src "ls180.v:1613.5-1613.40" - process $proc$ls180.v:1613$3444 - assign { } { } - assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] - end - attribute \src "ls180.v:1617.12-1617.47" - process $proc$ls180.v:1617$3445 - assign { } { } - assign $1\main_sdmem2block_dma_offset[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] - end - attribute \src "ls180.v:162.11-162.69" - process $proc$ls180.v:162$2806 - assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00 - sync always - update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0] - sync init - end - attribute \src "ls180.v:1629.11-1629.64" - process $proc$ls180.v:1629$3446 - assign { } { } - assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1631.11-1631.48" - process $proc$ls180.v:1631$3447 - assign { } { } - assign $1\main_sdmem2block_converter_mux[1:0] 2'00 - sync always - sync init - update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[1:0] - end - attribute \src "ls180.v:164.5-164.44" - process $proc$ls180.v:164$2807 - assign { } { } - assign $1\main_libresocsim_converter1_skip[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0] - end - attribute \src "ls180.v:165.5-165.47" - process $proc$ls180.v:165$2808 - assign { } { } - assign $1\main_libresocsim_converter1_counter[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0] - end - attribute \src "ls180.v:1655.11-1655.45" - process $proc$ls180.v:1655$3448 - assign { } { } - assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 - sync always - sync init - update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] - end - attribute \src "ls180.v:1656.5-1656.41" - process $proc$ls180.v:1656$3449 - assign { } { } - assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 - sync always - update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:1657.11-1657.47" - process $proc$ls180.v:1657$3450 - assign { } { } - assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 - sync always - sync init - update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] - end - attribute \src "ls180.v:1658.11-1658.47" - process $proc$ls180.v:1658$3451 - assign { } { } - assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 - sync always - sync init - update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] - end - attribute \src "ls180.v:1659.11-1659.50" - process $proc$ls180.v:1659$3452 - assign { } { } - assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 - sync always - sync init - update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:167.12-167.53" - process $proc$ls180.v:167$2809 - assign { } { } - assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0] - end - attribute \src "ls180.v:1674.5-1674.29" - process $proc$ls180.v:1674$3453 - assign { } { } - assign $1\libresocsim_done0[0:0] 1'0 - sync always - sync init - update \libresocsim_done0 $1\libresocsim_done0[0:0] - end - attribute \src "ls180.v:1675.5-1675.27" - process $proc$ls180.v:1675$3454 - assign { } { } - assign $1\libresocsim_irq[0:0] 1'0 - sync always - sync init - update \libresocsim_irq $1\libresocsim_irq[0:0] - end - attribute \src "ls180.v:1677.11-1677.34" - process $proc$ls180.v:1677$3455 - assign { } { } - assign $1\libresocsim_miso[7:0] 8'00000000 - sync always - sync init - update \libresocsim_miso $1\libresocsim_miso[7:0] - end - attribute \src "ls180.v:168.12-168.71" - process $proc$ls180.v:168$2810 - assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0] - end - attribute \src "ls180.v:1681.5-1681.30" - process $proc$ls180.v:1681$3456 - assign { } { } - assign $1\libresocsim_start1[0:0] 1'0 - sync always - sync init - update \libresocsim_start1 $1\libresocsim_start1[0:0] - end - attribute \src "ls180.v:1683.12-1683.47" - process $proc$ls180.v:1683$3457 - assign { } { } - assign $1\libresocsim_control_storage[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_control_storage $1\libresocsim_control_storage[15:0] - end - attribute \src "ls180.v:1684.5-1684.34" - process $proc$ls180.v:1684$3458 - assign { } { } - assign $1\libresocsim_control_re[0:0] 1'0 - sync always - sync init - update \libresocsim_control_re $1\libresocsim_control_re[0:0] - end - attribute \src "ls180.v:1688.11-1688.42" - process $proc$ls180.v:1688$3459 - assign { } { } - assign $1\libresocsim_mosi_storage[7:0] 8'00000000 - sync always - sync init - update \libresocsim_mosi_storage $1\libresocsim_mosi_storage[7:0] - end - attribute \src "ls180.v:1689.5-1689.31" - process $proc$ls180.v:1689$3460 - assign { } { } - assign $1\libresocsim_mosi_re[0:0] 1'0 - sync always - sync init - update \libresocsim_mosi_re $1\libresocsim_mosi_re[0:0] - end - attribute \src "ls180.v:169.12-169.73" - process $proc$ls180.v:169$2811 - assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 - sync always - sync init - update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:1693.5-1693.34" - process $proc$ls180.v:1693$3461 - assign { } { } - assign $1\libresocsim_cs_storage[0:0] 1'1 - sync always - sync init - update \libresocsim_cs_storage $1\libresocsim_cs_storage[0:0] - end - attribute \src "ls180.v:1694.5-1694.29" - process $proc$ls180.v:1694$3462 - assign { } { } - assign $1\libresocsim_cs_re[0:0] 1'0 - sync always - sync init - update \libresocsim_cs_re $1\libresocsim_cs_re[0:0] - end - attribute \src "ls180.v:1695.5-1695.40" - process $proc$ls180.v:1695$3463 - assign { } { } - assign $1\libresocsim_loopback_storage[0:0] 1'0 - sync always - sync init - update \libresocsim_loopback_storage $1\libresocsim_loopback_storage[0:0] - end - attribute \src "ls180.v:1696.5-1696.35" - process $proc$ls180.v:1696$3464 - assign { } { } - assign $1\libresocsim_loopback_re[0:0] 1'0 - sync always - sync init - update \libresocsim_loopback_re $1\libresocsim_loopback_re[0:0] - end - attribute \src "ls180.v:1697.5-1697.34" - process $proc$ls180.v:1697$3465 - assign { } { } - assign $1\libresocsim_clk_enable[0:0] 1'0 - sync always - sync init - update \libresocsim_clk_enable $1\libresocsim_clk_enable[0:0] - end - attribute \src "ls180.v:1698.5-1698.33" - process $proc$ls180.v:1698$3466 - assign { } { } - assign $1\libresocsim_cs_enable[0:0] 1'0 - sync always - sync init - update \libresocsim_cs_enable $1\libresocsim_cs_enable[0:0] - end - attribute \src "ls180.v:1699.11-1699.35" - process $proc$ls180.v:1699$3467 - assign { } { } - assign $1\libresocsim_count[2:0] 3'000 - sync always - sync init - update \libresocsim_count $1\libresocsim_count[2:0] - end - attribute \src "ls180.v:1700.5-1700.34" - process $proc$ls180.v:1700$3468 - assign { } { } - assign $1\libresocsim_mosi_latch[0:0] 1'0 - sync always - sync init - update \libresocsim_mosi_latch $1\libresocsim_mosi_latch[0:0] - end - attribute \src "ls180.v:1701.5-1701.34" - process $proc$ls180.v:1701$3469 - assign { } { } - assign $1\libresocsim_miso_latch[0:0] 1'0 - sync always - sync init - update \libresocsim_miso_latch $1\libresocsim_miso_latch[0:0] - end - attribute \src "ls180.v:1702.12-1702.44" - process $proc$ls180.v:1702$3470 - assign { } { } - assign $1\libresocsim_clk_divider1[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_clk_divider1 $1\libresocsim_clk_divider1[15:0] - end - attribute \src "ls180.v:1705.11-1705.39" - process $proc$ls180.v:1705$3471 - assign { } { } - assign $1\libresocsim_mosi_data[7:0] 8'00000000 - sync always - sync init - update \libresocsim_mosi_data $1\libresocsim_mosi_data[7:0] - end - attribute \src "ls180.v:1706.11-1706.38" - process $proc$ls180.v:1706$3472 - assign { } { } - assign $1\libresocsim_mosi_sel[2:0] 3'000 - sync always - sync init - update \libresocsim_mosi_sel $1\libresocsim_mosi_sel[2:0] - end - attribute \src "ls180.v:1707.11-1707.39" - process $proc$ls180.v:1707$3473 - assign { } { } - assign $1\libresocsim_miso_data[7:0] 8'00000000 - sync always - sync init - update \libresocsim_miso_data $1\libresocsim_miso_data[7:0] - end - attribute \src "ls180.v:1708.12-1708.41" - process $proc$ls180.v:1708$3474 - assign { } { } - assign $1\libresocsim_storage[15:0] 16'0000000001111101 - sync always - sync init - update \libresocsim_storage $1\libresocsim_storage[15:0] - end - attribute \src "ls180.v:1709.5-1709.26" - process $proc$ls180.v:1709$3475 - assign { } { } - assign $1\libresocsim_re[0:0] 1'0 - sync always - sync init - update \libresocsim_re $1\libresocsim_re[0:0] - end - attribute \src "ls180.v:171.11-171.69" - process $proc$ls180.v:171$2812 - assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_interface2_converted_interface_sel $1\main_libresocsim_interface2_converted_interface_sel[3:0] - end - attribute \src "ls180.v:1710.5-1710.36" - process $proc$ls180.v:1710$3476 - assign { } { } - assign $1\builder_converter0_state[0:0] 1'0 - sync always - sync init - update \builder_converter0_state $1\builder_converter0_state[0:0] - end - attribute \src "ls180.v:1711.5-1711.41" - process $proc$ls180.v:1711$3477 - assign { } { } - assign $1\builder_converter0_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] - end - attribute \src "ls180.v:1712.5-1712.69" - process $proc$ls180.v:1712$3478 - assign { } { } - assign $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter0_counter_converter0_next_value $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] - end - attribute \src "ls180.v:1713.5-1713.72" - process $proc$ls180.v:1713$3479 - assign { } { } - assign $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter0_counter_converter0_next_value_ce $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - end - attribute \src "ls180.v:1714.5-1714.36" - process $proc$ls180.v:1714$3480 - assign { } { } - assign $1\builder_converter1_state[0:0] 1'0 - sync always - sync init - update \builder_converter1_state $1\builder_converter1_state[0:0] - end - attribute \src "ls180.v:1715.5-1715.41" - process $proc$ls180.v:1715$3481 - assign { } { } - assign $1\builder_converter1_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] - end - attribute \src "ls180.v:1716.5-1716.69" - process $proc$ls180.v:1716$3482 - assign { } { } - assign $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter1_counter_converter1_next_value $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] - end - attribute \src "ls180.v:1717.5-1717.72" - process $proc$ls180.v:1717$3483 - assign { } { } - assign $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter1_counter_converter1_next_value_ce $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] - end - attribute \src "ls180.v:1718.5-1718.36" - process $proc$ls180.v:1718$3484 - assign { } { } - assign $1\builder_converter2_state[0:0] 1'0 - sync always - sync init - update \builder_converter2_state $1\builder_converter2_state[0:0] - end - attribute \src "ls180.v:1719.5-1719.41" - process $proc$ls180.v:1719$3485 - assign { } { } - assign $1\builder_converter2_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] - end - attribute \src "ls180.v:172.5-172.63" - process $proc$ls180.v:172$2813 - assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0] - end - attribute \src "ls180.v:1720.5-1720.69" - process $proc$ls180.v:1720$3486 - assign { } { } - assign $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter2_counter_converter2_next_value $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] - end - attribute \src "ls180.v:1721.5-1721.72" - process $proc$ls180.v:1721$3487 - assign { } { } - assign $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter2_counter_converter2_next_value_ce $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] - end - attribute \src "ls180.v:1722.11-1722.41" - process $proc$ls180.v:1722$3488 - assign { } { } - assign $1\builder_refresher_state[1:0] 2'00 - sync always - sync init - update \builder_refresher_state $1\builder_refresher_state[1:0] - end - attribute \src "ls180.v:1723.11-1723.46" - process $proc$ls180.v:1723$3489 - assign { } { } - assign $1\builder_refresher_next_state[1:0] 2'00 - sync always - sync init - update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] - end - attribute \src "ls180.v:1724.11-1724.44" - process $proc$ls180.v:1724$3490 - assign { } { } - assign $1\builder_bankmachine0_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] - end - attribute \src "ls180.v:1725.11-1725.49" - process $proc$ls180.v:1725$3491 - assign { } { } - assign $1\builder_bankmachine0_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] - end - attribute \src "ls180.v:1726.11-1726.44" - process $proc$ls180.v:1726$3492 - assign { } { } - assign $1\builder_bankmachine1_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] - end - attribute \src "ls180.v:1727.11-1727.49" - process $proc$ls180.v:1727$3493 - assign { } { } - assign $1\builder_bankmachine1_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] - end - attribute \src "ls180.v:1728.11-1728.44" - process $proc$ls180.v:1728$3494 - assign { } { } - assign $1\builder_bankmachine2_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] - end - attribute \src "ls180.v:1729.11-1729.49" - process $proc$ls180.v:1729$3495 - assign { } { } - assign $1\builder_bankmachine2_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] - end - attribute \src "ls180.v:173.5-173.63" - process $proc$ls180.v:173$2814 - assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface2_converted_interface_stb $1\main_libresocsim_interface2_converted_interface_stb[0:0] - end - attribute \src "ls180.v:1730.11-1730.44" - process $proc$ls180.v:1730$3496 - assign { } { } - assign $1\builder_bankmachine3_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] - end - attribute \src "ls180.v:1731.11-1731.49" - process $proc$ls180.v:1731$3497 - assign { } { } - assign $1\builder_bankmachine3_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] - end - attribute \src "ls180.v:1732.11-1732.43" - process $proc$ls180.v:1732$3498 - assign { } { } - assign $1\builder_multiplexer_state[2:0] 3'000 - sync always - sync init - update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] - end - attribute \src "ls180.v:1733.11-1733.48" - process $proc$ls180.v:1733$3499 - assign { } { } - assign $1\builder_multiplexer_next_state[2:0] 3'000 - sync always - sync init - update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] - end - attribute \src "ls180.v:1746.5-1746.27" - process $proc$ls180.v:1746$3500 - assign { } { } - assign $0\builder_locked0[0:0] 1'0 - sync always - update \builder_locked0 $0\builder_locked0[0:0] - sync init - end - attribute \src "ls180.v:1747.5-1747.27" - process $proc$ls180.v:1747$3501 - assign { } { } - assign $0\builder_locked1[0:0] 1'0 - sync always - update \builder_locked1 $0\builder_locked1[0:0] - sync init - end - attribute \src "ls180.v:1748.5-1748.27" - process $proc$ls180.v:1748$3502 - assign { } { } - assign $0\builder_locked2[0:0] 1'0 - sync always - update \builder_locked2 $0\builder_locked2[0:0] - sync init - end - attribute \src "ls180.v:1749.5-1749.27" - process $proc$ls180.v:1749$3503 - assign { } { } - assign $0\builder_locked3[0:0] 1'0 - sync always - update \builder_locked3 $0\builder_locked3[0:0] - sync init - end - attribute \src "ls180.v:175.5-175.62" - process $proc$ls180.v:175$2815 - assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface2_converted_interface_we $1\main_libresocsim_interface2_converted_interface_we[0:0] - end - attribute \src "ls180.v:1750.5-1750.42" - process $proc$ls180.v:1750$3504 - assign { } { } - assign $1\builder_new_master_wdata_ready[0:0] 1'0 - sync always - sync init - update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] - end - attribute \src "ls180.v:1751.5-1751.43" - process $proc$ls180.v:1751$3505 - assign { } { } - assign $1\builder_new_master_rdata_valid0[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] - end - attribute \src "ls180.v:1752.5-1752.43" - process $proc$ls180.v:1752$3506 - assign { } { } - assign $1\builder_new_master_rdata_valid1[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] - end - attribute \src "ls180.v:1753.5-1753.43" - process $proc$ls180.v:1753$3507 - assign { } { } - assign $1\builder_new_master_rdata_valid2[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] - end - attribute \src "ls180.v:1754.5-1754.43" - process $proc$ls180.v:1754$3508 - assign { } { } - assign $1\builder_new_master_rdata_valid3[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] - end - attribute \src "ls180.v:1755.5-1755.35" - process $proc$ls180.v:1755$3509 - assign { } { } - assign $1\builder_converter_state[0:0] 1'0 - sync always - sync init - update \builder_converter_state $1\builder_converter_state[0:0] - end - attribute \src "ls180.v:1756.5-1756.40" - process $proc$ls180.v:1756$3510 - assign { } { } - assign $1\builder_converter_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter_next_state $1\builder_converter_next_state[0:0] - end - attribute \src "ls180.v:1757.5-1757.55" - process $proc$ls180.v:1757$3511 - assign { } { } - assign $1\main_converter_counter_converter_next_value[0:0] 1'0 - sync always - sync init - update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] - end - attribute \src "ls180.v:1758.5-1758.58" - process $proc$ls180.v:1758$3512 - assign { } { } - assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] - end - attribute \src "ls180.v:1759.11-1759.42" - process $proc$ls180.v:1759$3513 - assign { } { } - assign $1\builder_spimaster0_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] - end - attribute \src "ls180.v:176.11-176.69" - process $proc$ls180.v:176$2816 - assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_cti[2:0] 3'000 - sync always - update \main_libresocsim_interface2_converted_interface_cti $0\main_libresocsim_interface2_converted_interface_cti[2:0] - sync init - end - attribute \src "ls180.v:1760.11-1760.47" - process $proc$ls180.v:1760$3514 - assign { } { } - assign $1\builder_spimaster0_next_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] - end - attribute \src "ls180.v:1761.11-1761.61" - process $proc$ls180.v:1761$3515 - assign { } { } - assign $1\main_spi_master_count_spimaster0_next_value[2:0] 3'000 - sync always - sync init - update \main_spi_master_count_spimaster0_next_value $1\main_spi_master_count_spimaster0_next_value[2:0] - end - attribute \src "ls180.v:1762.5-1762.58" - process $proc$ls180.v:1762$3516 - assign { } { } - assign $1\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_spi_master_count_spimaster0_next_value_ce $1\main_spi_master_count_spimaster0_next_value_ce[0:0] - end - attribute \src "ls180.v:1763.5-1763.41" - process $proc$ls180.v:1763$3517 - assign { } { } - assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] - end - attribute \src "ls180.v:1764.5-1764.46" - process $proc$ls180.v:1764$3518 - assign { } { } - assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] - end - attribute \src "ls180.v:1765.11-1765.66" - process $proc$ls180.v:1765$3519 - assign { } { } - assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - end - attribute \src "ls180.v:1766.5-1766.63" - process $proc$ls180.v:1766$3520 - assign { } { } - assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - end - attribute \src "ls180.v:1767.11-1767.47" - process $proc$ls180.v:1767$3521 - assign { } { } - assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 - sync always - sync init - update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] - end - attribute \src "ls180.v:1768.11-1768.52" - process $proc$ls180.v:1768$3522 - assign { } { } - assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 - sync always - sync init - update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] - end - attribute \src "ls180.v:1769.11-1769.66" - process $proc$ls180.v:1769$3523 - assign { } { } - assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - end - attribute \src "ls180.v:177.11-177.69" - process $proc$ls180.v:177$2817 - assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_bte[1:0] 2'00 - sync always - update \main_libresocsim_interface2_converted_interface_bte $0\main_libresocsim_interface2_converted_interface_bte[1:0] - sync init - end - attribute \src "ls180.v:1770.5-1770.63" - process $proc$ls180.v:1770$3524 - assign { } { } - assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - end - attribute \src "ls180.v:1771.11-1771.47" - process $proc$ls180.v:1771$3525 - assign { } { } - assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] - end - attribute \src "ls180.v:1772.11-1772.52" - process $proc$ls180.v:1772$3526 - assign { } { } - assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] - end - attribute \src "ls180.v:1773.11-1773.67" - process $proc$ls180.v:1773$3527 - assign { } { } - assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - end - attribute \src "ls180.v:1774.5-1774.64" - process $proc$ls180.v:1774$3528 - assign { } { } - assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - end - attribute \src "ls180.v:1775.12-1775.71" - process $proc$ls180.v:1775$3529 - assign { } { } - assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 - sync always - sync init - update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - end - attribute \src "ls180.v:1776.5-1776.66" - process $proc$ls180.v:1776$3530 - assign { } { } - assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - end - attribute \src "ls180.v:1777.5-1777.66" - process $proc$ls180.v:1777$3531 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - end - attribute \src "ls180.v:1778.5-1778.69" - process $proc$ls180.v:1778$3532 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - end - attribute \src "ls180.v:1779.5-1779.41" - process $proc$ls180.v:1779$3533 - assign { } { } - assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] - end - attribute \src "ls180.v:1780.5-1780.46" - process $proc$ls180.v:1780$3534 - assign { } { } - assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] - end - attribute \src "ls180.v:1781.5-1781.66" - process $proc$ls180.v:1781$3535 - assign { } { } - assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - end - attribute \src "ls180.v:1782.5-1782.69" - process $proc$ls180.v:1782$3536 - assign { } { } - assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - end - attribute \src "ls180.v:1783.11-1783.41" - process $proc$ls180.v:1783$3537 - assign { } { } - assign $1\builder_sdphy_fsm_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] - end - attribute \src "ls180.v:1784.11-1784.46" - process $proc$ls180.v:1784$3538 - assign { } { } - assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] - end - attribute \src "ls180.v:1785.11-1785.61" - process $proc$ls180.v:1785$3539 - assign { } { } - assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - end - attribute \src "ls180.v:1786.5-1786.58" - process $proc$ls180.v:1786$3540 - assign { } { } - assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:1787.11-1787.48" - process $proc$ls180.v:1787$3541 - assign { } { } - assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] - end - attribute \src "ls180.v:1788.11-1788.53" - process $proc$ls180.v:1788$3542 - assign { } { } - assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] - end - attribute \src "ls180.v:1789.11-1789.70" - process $proc$ls180.v:1789$3543 - assign { } { } - assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - sync always - sync init - update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - end - attribute \src "ls180.v:179.5-179.44" - process $proc$ls180.v:179$2818 - assign { } { } - assign $1\main_libresocsim_converter2_skip[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter2_skip $1\main_libresocsim_converter2_skip[0:0] - end - attribute \src "ls180.v:1790.5-1790.66" - process $proc$ls180.v:1790$3544 - assign { } { } - assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - end - attribute \src "ls180.v:1791.12-1791.73" - process $proc$ls180.v:1791$3545 - assign { } { } - assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 - sync always - sync init - update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - end - attribute \src "ls180.v:1792.5-1792.68" - process $proc$ls180.v:1792$3546 - assign { } { } - assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - end - attribute \src "ls180.v:1793.5-1793.69" - process $proc$ls180.v:1793$3547 - assign { } { } - assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - end - attribute \src "ls180.v:1794.5-1794.72" - process $proc$ls180.v:1794$3548 - assign { } { } - assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - end - attribute \src "ls180.v:1795.5-1795.52" - process $proc$ls180.v:1795$3549 - assign { } { } - assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 - sync always - sync init - update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] - end - attribute \src "ls180.v:1796.5-1796.57" - process $proc$ls180.v:1796$3550 - assign { } { } - assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] - end - attribute \src "ls180.v:1797.12-1797.93" - process $proc$ls180.v:1797$3551 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - end - attribute \src "ls180.v:1798.5-1798.88" - process $proc$ls180.v:1798$3552 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - end - attribute \src "ls180.v:1799.12-1799.93" - process $proc$ls180.v:1799$3553 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - end - attribute \src "ls180.v:180.5-180.47" - process $proc$ls180.v:180$2819 - assign { } { } - assign $1\main_libresocsim_converter2_counter[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter2_counter $1\main_libresocsim_converter2_counter[0:0] - end - attribute \src "ls180.v:1800.5-1800.88" - process $proc$ls180.v:1800$3554 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - end - attribute \src "ls180.v:1801.12-1801.93" - process $proc$ls180.v:1801$3555 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - end - attribute \src "ls180.v:1802.5-1802.88" - process $proc$ls180.v:1802$3556 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - end - attribute \src "ls180.v:1803.12-1803.93" - process $proc$ls180.v:1803$3557 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - end - attribute \src "ls180.v:1804.5-1804.88" - process $proc$ls180.v:1804$3558 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - end - attribute \src "ls180.v:1805.11-1805.87" - process $proc$ls180.v:1805$3559 - assign { } { } - assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 - sync always - sync init - update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - end - attribute \src "ls180.v:1806.5-1806.84" - process $proc$ls180.v:1806$3560 - assign { } { } - assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - end - attribute \src "ls180.v:1807.11-1807.42" - process $proc$ls180.v:1807$3561 - assign { } { } - assign $1\builder_sdcore_fsm_state[2:0] 3'000 - sync always - sync init - update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] - end - attribute \src "ls180.v:1808.11-1808.47" - process $proc$ls180.v:1808$3562 - assign { } { } - assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] - end - attribute \src "ls180.v:1809.5-1809.55" - process $proc$ls180.v:1809$3563 - assign { } { } - assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - end - attribute \src "ls180.v:1810.5-1810.58" - process $proc$ls180.v:1810$3564 - assign { } { } - assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - end - attribute \src "ls180.v:1811.5-1811.56" - process $proc$ls180.v:1811$3565 - assign { } { } - assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - end - attribute \src "ls180.v:1812.5-1812.59" - process $proc$ls180.v:1812$3566 - assign { } { } - assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - end - attribute \src "ls180.v:1813.11-1813.62" - process $proc$ls180.v:1813$3567 - assign { } { } - assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 - sync always - sync init - update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - end - attribute \src "ls180.v:1814.5-1814.59" - process $proc$ls180.v:1814$3568 - assign { } { } - assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - end - attribute \src "ls180.v:1815.12-1815.65" - process $proc$ls180.v:1815$3569 - assign { } { } - assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - sync always - sync init - update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - end - attribute \src "ls180.v:1816.5-1816.60" - process $proc$ls180.v:1816$3570 - assign { } { } - assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - end - attribute \src "ls180.v:1817.5-1817.56" - process $proc$ls180.v:1817$3571 - assign { } { } - assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - end - attribute \src "ls180.v:1818.5-1818.59" - process $proc$ls180.v:1818$3572 - assign { } { } - assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - end - attribute \src "ls180.v:1819.5-1819.58" - process $proc$ls180.v:1819$3573 - assign { } { } - assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - end - attribute \src "ls180.v:182.12-182.53" - process $proc$ls180.v:182$2820 - assign { } { } - assign $1\main_libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_converter2_dat_r $1\main_libresocsim_converter2_dat_r[63:0] - end - attribute \src "ls180.v:1820.5-1820.61" - process $proc$ls180.v:1820$3574 - assign { } { } - assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - end - attribute \src "ls180.v:1821.5-1821.57" - process $proc$ls180.v:1821$3575 - assign { } { } - assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - end - attribute \src "ls180.v:1822.5-1822.60" - process $proc$ls180.v:1822$3576 - assign { } { } - assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - end - attribute \src "ls180.v:1823.5-1823.59" - process $proc$ls180.v:1823$3577 - assign { } { } - assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - end - attribute \src "ls180.v:1824.5-1824.62" - process $proc$ls180.v:1824$3578 - assign { } { } - assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - end - attribute \src "ls180.v:1825.13-1825.76" - process $proc$ls180.v:1825$3579 - assign { } { } - assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - end - attribute \src "ls180.v:1826.5-1826.69" - process $proc$ls180.v:1826$3580 - assign { } { } - assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - end - attribute \src "ls180.v:1827.11-1827.46" - process $proc$ls180.v:1827$3581 - assign { } { } - assign $1\builder_sdblock2memdma_state[1:0] 2'00 - sync always - sync init - update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] - end - attribute \src "ls180.v:1828.11-1828.51" - process $proc$ls180.v:1828$3582 - assign { } { } - assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 - sync always - sync init - update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] - end - attribute \src "ls180.v:1829.12-1829.87" - process $proc$ls180.v:1829$3583 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - end - attribute \src "ls180.v:1830.5-1830.82" - process $proc$ls180.v:1830$3584 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - end - attribute \src "ls180.v:1831.5-1831.44" - process $proc$ls180.v:1831$3585 - assign { } { } - assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 - sync always - sync init - update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] - end - attribute \src "ls180.v:1832.5-1832.49" - process $proc$ls180.v:1832$3586 - assign { } { } - assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] - end - attribute \src "ls180.v:1833.12-1833.75" - process $proc$ls180.v:1833$3587 - assign { } { } - assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - end - attribute \src "ls180.v:1834.5-1834.70" - process $proc$ls180.v:1834$3588 - assign { } { } - assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:1835.11-1835.60" - process $proc$ls180.v:1835$3589 - assign { } { } - assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 - sync always - sync init - update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] - end - attribute \src "ls180.v:1836.11-1836.65" - process $proc$ls180.v:1836$3590 - assign { } { } - assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 - sync always - sync init - update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] - end - attribute \src "ls180.v:1837.12-1837.87" - process $proc$ls180.v:1837$3591 - assign { } { } - assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - end - attribute \src "ls180.v:1838.5-1838.82" - process $proc$ls180.v:1838$3592 - assign { } { } - assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - end - attribute \src "ls180.v:1839.11-1839.42" - process $proc$ls180.v:1839$3593 - assign { } { } - assign $1\builder_spimaster1_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] - end - attribute \src "ls180.v:1840.11-1840.47" - process $proc$ls180.v:1840$3594 - assign { } { } - assign $1\builder_spimaster1_next_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] - end - attribute \src "ls180.v:1841.11-1841.57" - process $proc$ls180.v:1841$3595 - assign { } { } - assign $1\libresocsim_count_spimaster1_next_value[2:0] 3'000 - sync always - sync init - update \libresocsim_count_spimaster1_next_value $1\libresocsim_count_spimaster1_next_value[2:0] - end - attribute \src "ls180.v:1842.5-1842.54" - process $proc$ls180.v:1842$3596 - assign { } { } - assign $1\libresocsim_count_spimaster1_next_value_ce[0:0] 1'0 - sync always - sync init - update \libresocsim_count_spimaster1_next_value_ce $1\libresocsim_count_spimaster1_next_value_ce[0:0] - end - attribute \src "ls180.v:1843.12-1843.43" - process $proc$ls180.v:1843$3597 - assign { } { } - assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 - sync always - sync init - update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] - end - attribute \src "ls180.v:1844.5-1844.34" - process $proc$ls180.v:1844$3598 - assign { } { } - assign $1\builder_libresocsim_we[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] - end - attribute \src "ls180.v:1845.11-1845.43" - process $proc$ls180.v:1845$3599 - assign { } { } - assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 - sync always - sync init - update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] - end - attribute \src "ls180.v:1849.12-1849.54" - process $proc$ls180.v:1849$3600 - assign { } { } - assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 - sync always - sync init - update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] - end - attribute \src "ls180.v:1853.5-1853.44" - process $proc$ls180.v:1853$3601 - assign { } { } - assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] - end - attribute \src "ls180.v:1857.5-1857.44" - process $proc$ls180.v:1857$3602 - assign { } { } - assign $0\builder_libresocsim_wishbone_err[0:0] 1'0 - sync always - update \builder_libresocsim_wishbone_err $0\builder_libresocsim_wishbone_err[0:0] - sync init - end - attribute \src "ls180.v:1860.12-1860.40" - process $proc$ls180.v:1860$3603 - assign { } { } - assign $1\builder_shared_dat_r[31:0] 0 - sync always - sync init - update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] - end - attribute \src "ls180.v:1864.5-1864.30" - process $proc$ls180.v:1864$3604 - assign { } { } - assign $1\builder_shared_ack[0:0] 1'0 - sync always - sync init - update \builder_shared_ack $1\builder_shared_ack[0:0] - end - attribute \src "ls180.v:1870.11-1870.31" - process $proc$ls180.v:1870$3605 - assign { } { } - assign $1\builder_grant[2:0] 3'000 - sync always - sync init - update \builder_grant $1\builder_grant[2:0] - end - attribute \src "ls180.v:1871.11-1871.35" - process $proc$ls180.v:1871$3606 - assign { } { } - assign $1\builder_slave_sel[4:0] 5'00000 - sync always - sync init - update \builder_slave_sel $1\builder_slave_sel[4:0] - end - attribute \src "ls180.v:1872.11-1872.37" - process $proc$ls180.v:1872$3607 - assign { } { } - assign $1\builder_slave_sel_r[4:0] 5'00000 - sync always - sync init - update \builder_slave_sel_r $1\builder_slave_sel_r[4:0] - end - attribute \src "ls180.v:1873.5-1873.25" - process $proc$ls180.v:1873$3608 - assign { } { } - assign $1\builder_error[0:0] 1'0 - sync always - sync init - update \builder_error $1\builder_error[0:0] - end - attribute \src "ls180.v:1876.12-1876.39" - process $proc$ls180.v:1876$3609 - assign { } { } - assign $1\builder_count[19:0] 20'11110100001001000000 - sync always - sync init - update \builder_count $1\builder_count[19:0] - end - attribute \src "ls180.v:1880.11-1880.51" - process $proc$ls180.v:1880$3610 - assign { } { } - assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:189.5-189.40" - process $proc$ls180.v:189$2821 - assign { } { } - assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] - end - attribute \src "ls180.v:1921.11-1921.51" - process $proc$ls180.v:1921$3611 - assign { } { } - assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:193.5-193.40" - process $proc$ls180.v:193$2822 - assign { } { } - assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 - sync always - update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] - sync init - end - attribute \src "ls180.v:1950.11-1950.51" - process $proc$ls180.v:1950$3612 - assign { } { } - assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:196.11-196.37" - process $proc$ls180.v:196$2823 - assign { } { } - assign $1\main_libresocsim_we[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_we $1\main_libresocsim_we[3:0] - end - attribute \src "ls180.v:1963.11-1963.51" - process $proc$ls180.v:1963$3613 - assign { } { } - assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:198.12-198.49" - process $proc$ls180.v:198$2824 - assign { } { } - assign $1\main_libresocsim_load_storage[31:0] 0 - sync always - sync init - update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] - end - attribute \src "ls180.v:199.5-199.36" - process $proc$ls180.v:199$2825 - assign { } { } - assign $1\main_libresocsim_load_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] - end - attribute \src "ls180.v:200.12-200.51" - process $proc$ls180.v:200$2826 - assign { } { } - assign $1\main_libresocsim_reload_storage[31:0] 0 - sync always - sync init - update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] - end - attribute \src "ls180.v:2004.11-2004.51" - process $proc$ls180.v:2004$3614 - assign { } { } - assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:201.5-201.38" - process $proc$ls180.v:201$2827 - assign { } { } - assign $1\main_libresocsim_reload_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] - end - attribute \src "ls180.v:202.5-202.39" - process $proc$ls180.v:202$2828 - assign { } { } - assign $1\main_libresocsim_en_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] - end - attribute \src "ls180.v:203.5-203.34" - process $proc$ls180.v:203$2829 - assign { } { } - assign $1\main_libresocsim_en_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] - end - attribute \src "ls180.v:204.5-204.49" - process $proc$ls180.v:204$2830 - assign { } { } - assign $1\main_libresocsim_update_value_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] - end - attribute \src "ls180.v:2045.11-2045.51" - process $proc$ls180.v:2045$3615 - assign { } { } - assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:205.5-205.44" - process $proc$ls180.v:205$2831 - assign { } { } - assign $1\main_libresocsim_update_value_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] - end - attribute \src "ls180.v:206.12-206.49" - process $proc$ls180.v:206$2832 - assign { } { } - assign $1\main_libresocsim_value_status[31:0] 0 - sync always - sync init - update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] - end - attribute \src "ls180.v:210.5-210.41" - process $proc$ls180.v:210$2833 - assign { } { } - assign $1\main_libresocsim_zero_pending[0:0] 1'0 - sync always - sync init - update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] - end - attribute \src "ls180.v:2110.11-2110.51" - process $proc$ls180.v:2110$3616 - assign { } { } - assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:212.5-212.39" - process $proc$ls180.v:212$2834 - assign { } { } - assign $1\main_libresocsim_zero_clear[0:0] 1'0 - sync always - sync init - update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] - end - attribute \src "ls180.v:213.5-213.45" - process $proc$ls180.v:213$2835 - assign { } { } - assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 - sync always - sync init - update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] - end - attribute \src "ls180.v:222.5-222.49" - process $proc$ls180.v:222$2836 - assign { } { } - assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] - end - attribute \src "ls180.v:223.5-223.44" - process $proc$ls180.v:223$2837 - assign { } { } - assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] - end - attribute \src "ls180.v:224.12-224.42" - process $proc$ls180.v:224$2838 - assign { } { } - assign $1\main_libresocsim_value[31:0] 0 - sync always - sync init - update \main_libresocsim_value $1\main_libresocsim_value[31:0] - end - attribute \src "ls180.v:2243.11-2243.51" - process $proc$ls180.v:2243$3617 - assign { } { } - assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:228.5-228.24" - process $proc$ls180.v:228$2839 - assign { } { } - assign $1\main_int_rst[0:0] 1'1 - sync always - sync init - update \main_int_rst $1\main_int_rst[0:0] - end - attribute \src "ls180.v:2324.11-2324.51" - process $proc$ls180.v:2324$3618 - assign { } { } - assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2341.11-2341.51" - process $proc$ls180.v:2341$3619 - assign { } { } - assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2382.11-2382.52" - process $proc$ls180.v:2382$3620 - assign { } { } - assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2415.11-2415.52" - process $proc$ls180.v:2415$3621 - assign { } { } - assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:243.12-243.38" - process $proc$ls180.v:243$2840 - assign { } { } - assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] - end - attribute \src "ls180.v:244.5-244.36" - process $proc$ls180.v:244$2841 - assign { } { } - assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:245.11-245.32" - process $proc$ls180.v:245$2842 - assign { } { } - assign $1\main_rddata_en[2:0] 3'000 - sync always - sync init - update \main_rddata_en $1\main_rddata_en[2:0] - end - attribute \src "ls180.v:2456.11-2456.52" - process $proc$ls180.v:2456$3622 - assign { } { } - assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:248.5-248.36" - process $proc$ls180.v:248$2843 - assign { } { } - assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] - end - attribute \src "ls180.v:249.5-249.35" - process $proc$ls180.v:249$2844 - assign { } { } - assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] - end - attribute \src "ls180.v:250.5-250.36" - process $proc$ls180.v:250$2845 - assign { } { } - assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] - end - attribute \src "ls180.v:251.5-251.35" - process $proc$ls180.v:251$2846 - assign { } { } - assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] - end - attribute \src "ls180.v:2521.11-2521.52" - process $proc$ls180.v:2521$3623 - assign { } { } - assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2546.11-2546.52" - process $proc$ls180.v:2546$3624 - assign { } { } - assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:255.5-255.36" - process $proc$ls180.v:255$2847 - assign { } { } - assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 - sync always - update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] - sync init - end - attribute \src "ls180.v:2568.11-2568.31" - process $proc$ls180.v:2568$3625 - assign { } { } - assign $1\builder_state[1:0] 2'00 - sync always - sync init - update \builder_state $1\builder_state[1:0] - end - attribute \src "ls180.v:2569.11-2569.36" - process $proc$ls180.v:2569$3626 - assign { } { } - assign $1\builder_next_state[1:0] 2'00 - sync always - sync init - update \builder_next_state $1\builder_next_state[1:0] - end - attribute \src "ls180.v:2570.11-2570.55" - process $proc$ls180.v:2570$3627 - assign { } { } - assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 - sync always - sync init - update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] - end - attribute \src "ls180.v:2571.5-2571.52" - process $proc$ls180.v:2571$3628 - assign { } { } - assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] - end - attribute \src "ls180.v:2572.12-2572.55" - process $proc$ls180.v:2572$3629 - assign { } { } - assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 - sync always - sync init - update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] - end - attribute \src "ls180.v:2573.5-2573.50" - process $proc$ls180.v:2573$3630 - assign { } { } - assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] - end - attribute \src "ls180.v:2574.5-2574.46" - process $proc$ls180.v:2574$3631 - assign { } { } - assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] - end - attribute \src "ls180.v:2575.5-2575.49" - process $proc$ls180.v:2575$3632 - assign { } { } - assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] - end - attribute \src "ls180.v:2576.5-2576.41" - process $proc$ls180.v:2576$3633 - assign { } { } - assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] - end - attribute \src "ls180.v:2577.12-2577.49" - process $proc$ls180.v:2577$3634 - assign { } { } - assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] - end - attribute \src "ls180.v:2578.11-2578.47" - process $proc$ls180.v:2578$3635 - assign { } { } - assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 - sync always - sync init - update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] - end - attribute \src "ls180.v:2579.5-2579.41" - process $proc$ls180.v:2579$3636 - assign { } { } - assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] - end - attribute \src "ls180.v:2580.5-2580.41" - process $proc$ls180.v:2580$3637 - assign { } { } - assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] - end - attribute \src "ls180.v:2581.5-2581.41" - process $proc$ls180.v:2581$3638 - assign { } { } - assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] - end - attribute \src "ls180.v:2582.5-2582.39" - process $proc$ls180.v:2582$3639 - assign { } { } - assign $1\builder_comb_t_array_muxed0[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] - end - attribute \src "ls180.v:2583.5-2583.39" - process $proc$ls180.v:2583$3640 - assign { } { } - assign $1\builder_comb_t_array_muxed1[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] - end - attribute \src "ls180.v:2584.5-2584.39" - process $proc$ls180.v:2584$3641 - assign { } { } - assign $1\builder_comb_t_array_muxed2[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] - end - attribute \src "ls180.v:2585.5-2585.41" - process $proc$ls180.v:2585$3642 - assign { } { } - assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] - end - attribute \src "ls180.v:2586.12-2586.49" - process $proc$ls180.v:2586$3643 - assign { } { } - assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] - end - attribute \src "ls180.v:2587.11-2587.47" - process $proc$ls180.v:2587$3644 - assign { } { } - assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 - sync always - sync init - update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] - end - attribute \src "ls180.v:2588.5-2588.41" - process $proc$ls180.v:2588$3645 - assign { } { } - assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] - end - attribute \src "ls180.v:2589.5-2589.42" - process $proc$ls180.v:2589$3646 - assign { } { } - assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] - end - attribute \src "ls180.v:2590.5-2590.42" - process $proc$ls180.v:2590$3647 - assign { } { } - assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] - end - attribute \src "ls180.v:2591.5-2591.39" - process $proc$ls180.v:2591$3648 - assign { } { } - assign $1\builder_comb_t_array_muxed3[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] - end - attribute \src "ls180.v:2592.5-2592.39" - process $proc$ls180.v:2592$3649 - assign { } { } - assign $1\builder_comb_t_array_muxed4[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] - end - attribute \src "ls180.v:2593.5-2593.39" - process $proc$ls180.v:2593$3650 - assign { } { } - assign $1\builder_comb_t_array_muxed5[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] - end - attribute \src "ls180.v:2594.12-2594.50" - process $proc$ls180.v:2594$3651 - assign { } { } - assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] - end - attribute \src "ls180.v:2595.5-2595.42" - process $proc$ls180.v:2595$3652 - assign { } { } - assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] - end - attribute \src "ls180.v:2596.5-2596.42" - process $proc$ls180.v:2596$3653 - assign { } { } - assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] - end - attribute \src "ls180.v:2597.12-2597.50" - process $proc$ls180.v:2597$3654 - assign { } { } - assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] - end - attribute \src "ls180.v:2598.5-2598.42" - process $proc$ls180.v:2598$3655 - assign { } { } - assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] - end - attribute \src "ls180.v:2599.5-2599.42" - process $proc$ls180.v:2599$3656 - assign { } { } - assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] - end - attribute \src "ls180.v:260.12-260.45" - process $proc$ls180.v:260$2848 - assign { } { } - assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] - end - attribute \src "ls180.v:2600.12-2600.50" - process $proc$ls180.v:2600$3657 - assign { } { } - assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] - end - attribute \src "ls180.v:2601.5-2601.42" - process $proc$ls180.v:2601$3658 - assign { } { } - assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] - end - attribute \src "ls180.v:2602.5-2602.42" - process $proc$ls180.v:2602$3659 - assign { } { } - assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] - end - attribute \src "ls180.v:2603.12-2603.50" - process $proc$ls180.v:2603$3660 - assign { } { } - assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] - end - attribute \src "ls180.v:2604.5-2604.42" - process $proc$ls180.v:2604$3661 - assign { } { } - assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] - end - attribute \src "ls180.v:2605.5-2605.42" - process $proc$ls180.v:2605$3662 - assign { } { } - assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] - end - attribute \src "ls180.v:2606.12-2606.50" - process $proc$ls180.v:2606$3663 - assign { } { } - assign $1\builder_comb_rhs_array_muxed24[31:0] 0 - sync always - sync init - update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] - end - attribute \src "ls180.v:2607.12-2607.50" - process $proc$ls180.v:2607$3664 - assign { } { } - assign $1\builder_comb_rhs_array_muxed25[31:0] 0 - sync always - sync init - update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[31:0] - end - attribute \src "ls180.v:2608.11-2608.48" - process $proc$ls180.v:2608$3665 - assign { } { } - assign $1\builder_comb_rhs_array_muxed26[3:0] 4'0000 - sync always - sync init - update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[3:0] - end - attribute \src "ls180.v:2609.5-2609.42" - process $proc$ls180.v:2609$3666 - assign { } { } - assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] - end - attribute \src "ls180.v:261.5-261.43" - process $proc$ls180.v:261$2849 - assign { } { } - assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:2610.5-2610.42" - process $proc$ls180.v:2610$3667 - assign { } { } - assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] - end - attribute \src "ls180.v:2611.5-2611.42" - process $proc$ls180.v:2611$3668 - assign { } { } - assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] - end - attribute \src "ls180.v:2612.11-2612.48" - process $proc$ls180.v:2612$3669 - assign { } { } - assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 - sync always - sync init - update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] - end - attribute \src "ls180.v:2613.11-2613.48" - process $proc$ls180.v:2613$3670 - assign { } { } - assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 - sync always - sync init - update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] - end - attribute \src "ls180.v:2614.11-2614.47" - process $proc$ls180.v:2614$3671 - assign { } { } - assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 - sync always - sync init - update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] - end - attribute \src "ls180.v:2615.12-2615.49" - process $proc$ls180.v:2615$3672 - assign { } { } - assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 - sync always - sync init - update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] - end - attribute \src "ls180.v:2616.5-2616.41" - process $proc$ls180.v:2616$3673 - assign { } { } - assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 - sync always - sync init - update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] - end - attribute \src "ls180.v:2617.5-2617.41" - process $proc$ls180.v:2617$3674 - assign { } { } - assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 - sync always - sync init - update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] - end - attribute \src "ls180.v:2618.5-2618.41" - process $proc$ls180.v:2618$3675 - assign { } { } - assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 - sync always - sync init - update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] - end - attribute \src "ls180.v:2619.5-2619.41" - process $proc$ls180.v:2619$3676 - assign { } { } - assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 - sync always - sync init - update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] - end - attribute \src "ls180.v:2620.5-2620.41" - process $proc$ls180.v:2620$3677 - assign { } { } - assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 - sync always - sync init - update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] - end - attribute \src "ls180.v:2621.5-2621.39" - process $proc$ls180.v:2621$3678 - assign { } { } - assign $1\builder_sync_f_array_muxed0[0:0] 1'0 - sync always - sync init - update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] - end - attribute \src "ls180.v:2622.5-2622.39" - process $proc$ls180.v:2622$3679 - assign { } { } - assign $1\builder_sync_f_array_muxed1[0:0] 1'0 - sync always - sync init - update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] - end - attribute \src "ls180.v:2679.32-2679.66" - process $proc$ls180.v:2679$3680 - assign { } { } - assign $1\builder_multiregimpl0_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] - end - attribute \src "ls180.v:2680.32-2680.66" - process $proc$ls180.v:2680$3681 - assign { } { } - assign $1\builder_multiregimpl0_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] - end - attribute \src "ls180.v:2681.32-2681.66" - process $proc$ls180.v:2681$3682 - assign { } { } - assign $1\builder_multiregimpl1_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] - end - attribute \src "ls180.v:2682.32-2682.66" - process $proc$ls180.v:2682$3683 - assign { } { } - assign $1\builder_multiregimpl1_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] - end - attribute \src "ls180.v:2683.32-2683.66" - process $proc$ls180.v:2683$3684 - assign { } { } - assign $1\builder_multiregimpl2_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] - end - attribute \src "ls180.v:2684.32-2684.66" - process $proc$ls180.v:2684$3685 - assign { } { } - assign $1\builder_multiregimpl2_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] - end - attribute \src "ls180.v:2685.32-2685.66" - process $proc$ls180.v:2685$3686 - assign { } { } - assign $1\builder_multiregimpl3_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] - end - attribute \src "ls180.v:2686.32-2686.66" - process $proc$ls180.v:2686$3687 - assign { } { } - assign $1\builder_multiregimpl3_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] - end - attribute \src "ls180.v:2687.32-2687.66" - process $proc$ls180.v:2687$3688 - assign { } { } - assign $1\builder_multiregimpl4_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] - end - attribute \src "ls180.v:2688.32-2688.66" - process $proc$ls180.v:2688$3689 - assign { } { } - assign $1\builder_multiregimpl4_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] - end - attribute \src "ls180.v:2689.32-2689.66" - process $proc$ls180.v:2689$3690 - assign { } { } - assign $1\builder_multiregimpl5_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] - end - attribute \src "ls180.v:2690.32-2690.66" - process $proc$ls180.v:2690$3691 - assign { } { } - assign $1\builder_multiregimpl5_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] - end - attribute \src "ls180.v:2691.32-2691.66" - process $proc$ls180.v:2691$3692 - assign { } { } - assign $1\builder_multiregimpl6_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] - end - attribute \src "ls180.v:2692.32-2692.66" - process $proc$ls180.v:2692$3693 - assign { } { } - assign $1\builder_multiregimpl6_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] - end - attribute \src "ls180.v:2693.32-2693.66" - process $proc$ls180.v:2693$3694 - assign { } { } - assign $1\builder_multiregimpl7_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] - end - attribute \src "ls180.v:2694.32-2694.66" - process $proc$ls180.v:2694$3695 - assign { } { } - assign $1\builder_multiregimpl7_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] - end - attribute \src "ls180.v:2695.32-2695.66" - process $proc$ls180.v:2695$3696 - assign { } { } - assign $1\builder_multiregimpl8_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] - end - attribute \src "ls180.v:2696.32-2696.66" - process $proc$ls180.v:2696$3697 - assign { } { } - assign $1\builder_multiregimpl8_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] - end - attribute \src "ls180.v:2697.32-2697.66" - process $proc$ls180.v:2697$3698 - assign { } { } - assign $1\builder_multiregimpl9_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] - end - attribute \src "ls180.v:2698.32-2698.66" - process $proc$ls180.v:2698$3699 - assign { } { } - assign $1\builder_multiregimpl9_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] - end - attribute \src "ls180.v:2699.32-2699.67" - process $proc$ls180.v:2699$3700 - assign { } { } - assign $1\builder_multiregimpl10_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] - end - attribute \src "ls180.v:2700.32-2700.67" - process $proc$ls180.v:2700$3701 - assign { } { } - assign $1\builder_multiregimpl10_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] - end - attribute \src "ls180.v:2701.32-2701.67" - process $proc$ls180.v:2701$3702 - assign { } { } - assign $1\builder_multiregimpl11_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] - end - attribute \src "ls180.v:2702.32-2702.67" - process $proc$ls180.v:2702$3703 - assign { } { } - assign $1\builder_multiregimpl11_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] - end - attribute \src "ls180.v:2703.32-2703.67" - process $proc$ls180.v:2703$3704 - assign { } { } - assign $1\builder_multiregimpl12_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] - end - attribute \src "ls180.v:2704.32-2704.67" - process $proc$ls180.v:2704$3705 - assign { } { } - assign $1\builder_multiregimpl12_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] - end - attribute \src "ls180.v:2705.32-2705.67" - process $proc$ls180.v:2705$3706 - assign { } { } - assign $1\builder_multiregimpl13_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] - end - attribute \src "ls180.v:2706.32-2706.67" - process $proc$ls180.v:2706$3707 - assign { } { } - assign $1\builder_multiregimpl13_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] - end - attribute \src "ls180.v:2707.32-2707.67" - process $proc$ls180.v:2707$3708 - assign { } { } - assign $1\builder_multiregimpl14_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] - end - attribute \src "ls180.v:2708.32-2708.67" - process $proc$ls180.v:2708$3709 - assign { } { } - assign $1\builder_multiregimpl14_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] - end - attribute \src "ls180.v:2709.32-2709.67" - process $proc$ls180.v:2709$3710 - assign { } { } - assign $1\builder_multiregimpl15_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] - end - attribute \src "ls180.v:2710.32-2710.67" - process $proc$ls180.v:2710$3711 - assign { } { } - assign $1\builder_multiregimpl15_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] - end - attribute \src "ls180.v:2711.32-2711.67" - process $proc$ls180.v:2711$3712 - assign { } { } - assign $1\builder_multiregimpl16_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] - end - attribute \src "ls180.v:2712.32-2712.67" - process $proc$ls180.v:2712$3713 - assign { } { } - assign $1\builder_multiregimpl16_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0] - end - attribute \src "ls180.v:2751.1-2756.4" - process $proc$ls180.v:2751$13 - assign { } { } - assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 - assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } - assign $0\main_libresocsim_libresoc_interrupt[15:0] [0] \main_libresocsim_irq - assign $0\main_libresocsim_libresoc_interrupt[15:0] [1] \main_uart_irq - sync always - update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] - end - attribute \src "ls180.v:2758.1-2768.4" - process $proc$ls180.v:2758$15 - assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2760.2-2767.9" - switch \main_libresocsim_converter0_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [31:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [63:32] - case - end - sync always - update \main_libresocsim_interface0_converted_interface_dat_w $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:276.12-276.46" - process $proc$ls180.v:276$2850 - assign { } { } - assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] - end - attribute \src "ls180.v:277.5-277.44" - process $proc$ls180.v:277$2851 - assign { } { } - assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:2770.1-2816.4" - process $proc$ls180.v:2770$16 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 - assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 - assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 - assign $0\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 - assign $0\main_libresocsim_converter0_skip[0:0] 1'0 - assign { } { } - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 - assign $0\builder_converter0_next_state[0:0] \builder_converter0_state - attribute \src "ls180.v:2782.2-2815.9" - switch \builder_converter0_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] { \main_libresocsim_libresoc_ibus_adr \main_libresocsim_converter0_counter } - attribute \src "ls180.v:2785.4-2792.11" - switch \main_libresocsim_converter0_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [3:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [7:4] - case - end - attribute \src "ls180.v:2793.4-2806.7" - switch $and$ls180.v:2793$17_Y - attribute \src "ls180.v:2793.8-2793.81" - case 1'1 - assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2794$18_Y - assign $0\main_libresocsim_interface0_converted_interface_we[0:0] \main_libresocsim_libresoc_ibus_we - assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2796$19_Y - assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2797$20_Y - attribute \src "ls180.v:2798.5-2805.8" - switch $or$ls180.v:2798$21_Y - attribute \src "ls180.v:2798.9-2798.97" - case 1'1 - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2799$22_Y - assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2801.6-2804.9" - switch $eq$ls180.v:2801$23_Y - attribute \src "ls180.v:2801.10-2801.55" - case 1'1 - assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'1 - assign $0\builder_converter0_next_state[0:0] 1'0 - case - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2811.4-2813.7" - switch $and$ls180.v:2811$24_Y - attribute \src "ls180.v:2811.8-2811.81" - case 1'1 - assign $0\builder_converter0_next_state[0:0] 1'1 - case - end - end - sync always - update \main_libresocsim_libresoc_ibus_ack $0\main_libresocsim_libresoc_ibus_ack[0:0] - update \main_libresocsim_interface0_converted_interface_adr $0\main_libresocsim_interface0_converted_interface_adr[29:0] - update \main_libresocsim_interface0_converted_interface_sel $0\main_libresocsim_interface0_converted_interface_sel[3:0] - update \main_libresocsim_interface0_converted_interface_cyc $0\main_libresocsim_interface0_converted_interface_cyc[0:0] - update \main_libresocsim_interface0_converted_interface_stb $0\main_libresocsim_interface0_converted_interface_stb[0:0] - update \main_libresocsim_interface0_converted_interface_we $0\main_libresocsim_interface0_converted_interface_we[0:0] - update \main_libresocsim_converter0_skip $0\main_libresocsim_converter0_skip[0:0] - update \builder_converter0_next_state $0\builder_converter0_next_state[0:0] - update \main_libresocsim_converter0_counter_converter0_next_value $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] - update \main_libresocsim_converter0_counter_converter0_next_value_ce $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - end - attribute \src "ls180.v:278.12-278.48" - process $proc$ls180.v:278$2852 - assign { } { } - assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] - end - attribute \src "ls180.v:279.11-279.43" - process $proc$ls180.v:279$2853 - assign { } { } - assign $1\main_sdram_master_p0_bank[1:0] 2'00 - sync always - sync init - update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] - end - attribute \src "ls180.v:280.5-280.38" - process $proc$ls180.v:280$2854 - assign { } { } - assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] - end - attribute \src "ls180.v:281.5-281.37" - process $proc$ls180.v:281$2855 - assign { } { } - assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] - end - attribute \src "ls180.v:2818.1-2828.4" - process $proc$ls180.v:2818$26 - assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2820.2-2827.9" - switch \main_libresocsim_converter1_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [31:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [63:32] - case - end - sync always - update \main_libresocsim_interface1_converted_interface_dat_w $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:282.5-282.38" - process $proc$ls180.v:282$2856 - assign { } { } - assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] - end - attribute \src "ls180.v:283.5-283.37" - process $proc$ls180.v:283$2857 - assign { } { } - assign $1\main_sdram_master_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] - end - attribute \src "ls180.v:2830.1-2876.4" - process $proc$ls180.v:2830$27 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_libresocsim_converter1_skip[0:0] 1'0 - assign { } { } - assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 - assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 - assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 - assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 - assign $0\builder_converter1_next_state[0:0] \builder_converter1_state - attribute \src "ls180.v:2842.2-2875.9" - switch \builder_converter1_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] { \main_libresocsim_libresoc_dbus_adr \main_libresocsim_converter1_counter } - attribute \src "ls180.v:2845.4-2852.11" - switch \main_libresocsim_converter1_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [3:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [7:4] - case - end - attribute \src "ls180.v:2853.4-2866.7" - switch $and$ls180.v:2853$28_Y - attribute \src "ls180.v:2853.8-2853.81" - case 1'1 - assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2854$29_Y - assign $0\main_libresocsim_interface1_converted_interface_we[0:0] \main_libresocsim_libresoc_dbus_we - assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2856$30_Y - assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2857$31_Y - attribute \src "ls180.v:2858.5-2865.8" - switch $or$ls180.v:2858$32_Y - attribute \src "ls180.v:2858.9-2858.97" - case 1'1 - assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2859$33_Y - assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2861.6-2864.9" - switch $eq$ls180.v:2861$34_Y - attribute \src "ls180.v:2861.10-2861.55" - case 1'1 - assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'1 - assign $0\builder_converter1_next_state[0:0] 1'0 - case - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2871.4-2873.7" - switch $and$ls180.v:2871$35_Y - attribute \src "ls180.v:2871.8-2871.81" - case 1'1 - assign $0\builder_converter1_next_state[0:0] 1'1 - case - end - end - sync always - update \main_libresocsim_libresoc_dbus_ack $0\main_libresocsim_libresoc_dbus_ack[0:0] - update \main_libresocsim_interface1_converted_interface_adr $0\main_libresocsim_interface1_converted_interface_adr[29:0] - update \main_libresocsim_interface1_converted_interface_sel $0\main_libresocsim_interface1_converted_interface_sel[3:0] - update \main_libresocsim_interface1_converted_interface_cyc $0\main_libresocsim_interface1_converted_interface_cyc[0:0] - update \main_libresocsim_interface1_converted_interface_stb $0\main_libresocsim_interface1_converted_interface_stb[0:0] - update \main_libresocsim_interface1_converted_interface_we $0\main_libresocsim_interface1_converted_interface_we[0:0] - update \main_libresocsim_converter1_skip $0\main_libresocsim_converter1_skip[0:0] - update \builder_converter1_next_state $0\builder_converter1_next_state[0:0] - update \main_libresocsim_converter1_counter_converter1_next_value $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] - update \main_libresocsim_converter1_counter_converter1_next_value_ce $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] - end - attribute \src "ls180.v:284.5-284.36" - process $proc$ls180.v:284$2858 - assign { } { } - assign $1\main_sdram_master_p0_cke[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] - end - attribute \src "ls180.v:285.5-285.36" - process $proc$ls180.v:285$2859 - assign { } { } - assign $1\main_sdram_master_p0_odt[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] - end - attribute \src "ls180.v:286.5-286.40" - process $proc$ls180.v:286$2860 - assign { } { } - assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] - end - attribute \src "ls180.v:287.5-287.38" - process $proc$ls180.v:287$2861 - assign { } { } - assign $1\main_sdram_master_p0_act_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] - end - attribute \src "ls180.v:2878.1-2888.4" - process $proc$ls180.v:2878$37 - assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2880.2-2887.9" - switch \main_libresocsim_converter2_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [31:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [63:32] - case - end - sync always - update \main_libresocsim_interface2_converted_interface_dat_w $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:288.12-288.47" - process $proc$ls180.v:288$2862 - assign { } { } - assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] - end - attribute \src "ls180.v:289.5-289.42" - process $proc$ls180.v:289$2863 - assign { } { } - assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] - end - attribute \src "ls180.v:2890.1-2936.4" - process $proc$ls180.v:2890$38 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 - assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 - assign { } { } - assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 - assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 - assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 - assign $0\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 - assign $0\main_libresocsim_converter2_skip[0:0] 1'0 - assign $0\builder_converter2_next_state[0:0] \builder_converter2_state - attribute \src "ls180.v:2902.2-2935.9" - switch \builder_converter2_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] { \main_libresocsim_libresoc_jtag_wb_adr \main_libresocsim_converter2_counter } - attribute \src "ls180.v:2905.4-2912.11" - switch \main_libresocsim_converter2_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [3:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [7:4] - case - end - attribute \src "ls180.v:2913.4-2926.7" - switch $and$ls180.v:2913$39_Y - attribute \src "ls180.v:2913.8-2913.87" - case 1'1 - assign $0\main_libresocsim_converter2_skip[0:0] $eq$ls180.v:2914$40_Y - assign $0\main_libresocsim_interface2_converted_interface_we[0:0] \main_libresocsim_libresoc_jtag_wb_we - assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:2916$41_Y - assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:2917$42_Y - attribute \src "ls180.v:2918.5-2925.8" - switch $or$ls180.v:2918$43_Y - attribute \src "ls180.v:2918.9-2918.97" - case 1'1 - assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] $add$ls180.v:2919$44_Y - assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2921.6-2924.9" - switch $eq$ls180.v:2921$45_Y - attribute \src "ls180.v:2921.10-2921.55" - case 1'1 - assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'1 - assign $0\builder_converter2_next_state[0:0] 1'0 - case - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2931.4-2933.7" - switch $and$ls180.v:2931$46_Y - attribute \src "ls180.v:2931.8-2931.87" - case 1'1 - assign $0\builder_converter2_next_state[0:0] 1'1 - case - end - end - sync always - update \main_libresocsim_libresoc_jtag_wb_ack $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] - update \main_libresocsim_interface2_converted_interface_adr $0\main_libresocsim_interface2_converted_interface_adr[29:0] - update \main_libresocsim_interface2_converted_interface_sel $0\main_libresocsim_interface2_converted_interface_sel[3:0] - update \main_libresocsim_interface2_converted_interface_cyc $0\main_libresocsim_interface2_converted_interface_cyc[0:0] - update \main_libresocsim_interface2_converted_interface_stb $0\main_libresocsim_interface2_converted_interface_stb[0:0] - update \main_libresocsim_interface2_converted_interface_we $0\main_libresocsim_interface2_converted_interface_we[0:0] - update \main_libresocsim_converter2_skip $0\main_libresocsim_converter2_skip[0:0] - update \builder_converter2_next_state $0\builder_converter2_next_state[0:0] - update \main_libresocsim_converter2_counter_converter2_next_value $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] - update \main_libresocsim_converter2_counter_converter2_next_value_ce $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] - end - attribute \src "ls180.v:290.11-290.50" - process $proc$ls180.v:290$2864 - assign { } { } - assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 - sync always - sync init - update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] - end - attribute \src "ls180.v:291.5-291.42" - process $proc$ls180.v:291$2865 - assign { } { } - assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] - end - attribute \src "ls180.v:2939.1-2945.4" - process $proc$ls180.v:2939$47 - assign { } { } - assign { } { } - assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:2941$50_Y - assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:2942$53_Y - assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:2943$56_Y - assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:2944$59_Y - sync always - update \main_libresocsim_we $0\main_libresocsim_we[3:0] - end - attribute \src "ls180.v:2951.1-2956.4" - process $proc$ls180.v:2951$61 - assign { } { } - assign $0\main_libresocsim_zero_clear[0:0] 1'0 - attribute \src "ls180.v:2953.2-2955.5" - switch $and$ls180.v:2953$62_Y - attribute \src "ls180.v:2953.6-2953.90" - case 1'1 - assign $0\main_libresocsim_zero_clear[0:0] 1'1 - case - end - sync always - update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] - end - attribute \src "ls180.v:298.11-298.36" - process $proc$ls180.v:298$2866 - assign { } { } - assign $1\main_sdram_storage[3:0] 4'0001 - sync always - sync init - update \main_sdram_storage $1\main_sdram_storage[3:0] - end - attribute \src "ls180.v:299.5-299.25" - process $proc$ls180.v:299$2867 - assign { } { } - assign $1\main_sdram_re[0:0] 1'0 - sync always - sync init - update \main_sdram_re $1\main_sdram_re[0:0] - end - attribute \src "ls180.v:2995.1-3049.4" - process $proc$ls180.v:2995$64 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0 - assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 - assign $0\main_sdram_master_p0_bank[1:0] 2'00 - assign $0\main_sdram_master_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_master_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_master_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_master_p0_we_n[0:0] 1'1 - assign $0\main_sdram_master_p0_cke[0:0] 1'0 - assign $0\main_sdram_master_p0_odt[0:0] 1'0 - assign $0\main_sdram_master_p0_reset_n[0:0] 1'0 - assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 - assign $0\main_sdram_master_p0_act_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0 - assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 - assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 - assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 - assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 - assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 - attribute \src "ls180.v:3014.2-3048.5" - switch \main_sdram_sel - attribute \src "ls180.v:3014.6-3014.20" - case 1'1 - assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address - assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank - assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_slave_p0_cas_n - assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_slave_p0_cs_n - assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_slave_p0_ras_n - assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_slave_p0_we_n - assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_slave_p0_cke - assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_slave_p0_odt - assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_slave_p0_reset_n - assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_slave_p0_act_n - assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_slave_p0_wrdata - assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_slave_p0_wrdata_en - assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_slave_p0_wrdata_mask - assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en - assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata - assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:3031.6-3031.10" - case - assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address - assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank - assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_inti_p0_cas_n - assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_inti_p0_cs_n - assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_inti_p0_ras_n - assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_inti_p0_we_n - assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_inti_p0_cke - assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_inti_p0_odt - assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_inti_p0_reset_n - assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_inti_p0_act_n - assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_inti_p0_wrdata - assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_inti_p0_wrdata_en - assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_inti_p0_wrdata_mask - assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_inti_p0_rddata_en - assign $0\main_sdram_inti_p0_rddata[15:0] \main_sdram_master_p0_rddata - assign $0\main_sdram_inti_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid - end - sync always - update \main_sdram_inti_p0_rddata $0\main_sdram_inti_p0_rddata[15:0] - update \main_sdram_inti_p0_rddata_valid $0\main_sdram_inti_p0_rddata_valid[0:0] - update \main_sdram_slave_p0_rddata $0\main_sdram_slave_p0_rddata[15:0] - update \main_sdram_slave_p0_rddata_valid $0\main_sdram_slave_p0_rddata_valid[0:0] - update \main_sdram_master_p0_address $0\main_sdram_master_p0_address[12:0] - update \main_sdram_master_p0_bank $0\main_sdram_master_p0_bank[1:0] - update \main_sdram_master_p0_cas_n $0\main_sdram_master_p0_cas_n[0:0] - update \main_sdram_master_p0_cs_n $0\main_sdram_master_p0_cs_n[0:0] - update \main_sdram_master_p0_ras_n $0\main_sdram_master_p0_ras_n[0:0] - update \main_sdram_master_p0_we_n $0\main_sdram_master_p0_we_n[0:0] - update \main_sdram_master_p0_cke $0\main_sdram_master_p0_cke[0:0] - update \main_sdram_master_p0_odt $0\main_sdram_master_p0_odt[0:0] - update \main_sdram_master_p0_reset_n $0\main_sdram_master_p0_reset_n[0:0] - update \main_sdram_master_p0_act_n $0\main_sdram_master_p0_act_n[0:0] - update \main_sdram_master_p0_wrdata $0\main_sdram_master_p0_wrdata[15:0] - update \main_sdram_master_p0_wrdata_en $0\main_sdram_master_p0_wrdata_en[0:0] - update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] - update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] - end - attribute \src "ls180.v:300.11-300.44" - process $proc$ls180.v:300$2868 - assign { } { } - assign $1\main_sdram_command_storage[5:0] 6'000000 - sync always - sync init - update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] - end - attribute \src "ls180.v:301.5-301.33" - process $proc$ls180.v:301$2869 - assign { } { } - assign $1\main_sdram_command_re[0:0] 1'0 - sync always - sync init - update \main_sdram_command_re $1\main_sdram_command_re[0:0] - end - attribute \src "ls180.v:305.5-305.38" - process $proc$ls180.v:305$2870 - assign { } { } - assign $0\main_sdram_command_issue_w[0:0] 1'0 - sync always - update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] - sync init - end - attribute \src "ls180.v:3053.1-3069.4" - process $proc$ls180.v:3053$65 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 - attribute \src "ls180.v:3058.2-3068.5" - switch \main_sdram_command_issue_re - attribute \src "ls180.v:3058.6-3058.33" - case 1'1 - assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3059$66_Y - assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3060$67_Y - assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3061$68_Y - assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3062$69_Y - attribute \src "ls180.v:3063.6-3063.10" - case - assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 - end - sync always - update \main_sdram_inti_p0_cas_n $0\main_sdram_inti_p0_cas_n[0:0] - update \main_sdram_inti_p0_cs_n $0\main_sdram_inti_p0_cs_n[0:0] - update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] - update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] - end - attribute \src "ls180.v:306.12-306.46" - process $proc$ls180.v:306$2871 - assign { } { } - assign $1\main_sdram_address_storage[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] - end - attribute \src "ls180.v:307.5-307.33" - process $proc$ls180.v:307$2872 - assign { } { } - assign $1\main_sdram_address_re[0:0] 1'0 - sync always - sync init - update \main_sdram_address_re $1\main_sdram_address_re[0:0] - end - attribute \src "ls180.v:308.11-308.45" - process $proc$ls180.v:308$2873 - assign { } { } - assign $1\main_sdram_baddress_storage[1:0] 2'00 - sync always - sync init - update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] - end - attribute \src "ls180.v:309.5-309.34" - process $proc$ls180.v:309$2874 - assign { } { } - assign $1\main_sdram_baddress_re[0:0] 1'0 - sync always - sync init - update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] - end - attribute \src "ls180.v:310.12-310.45" - process $proc$ls180.v:310$2875 - assign { } { } - assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] - end - attribute \src "ls180.v:311.5-311.32" - process $proc$ls180.v:311$2876 - assign { } { } - assign $1\main_sdram_wrdata_re[0:0] 1'0 - sync always - sync init - update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] - end - attribute \src "ls180.v:3112.1-3142.4" - process $proc$ls180.v:3112$78 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_sequencer_start0[0:0] 1'0 - assign $0\main_sdram_cmd_valid[0:0] 1'0 - assign { } { } - assign $0\main_sdram_cmd_last[0:0] 1'0 - assign $0\builder_refresher_next_state[1:0] \builder_refresher_state - attribute \src "ls180.v:3118.2-3141.9" - switch \builder_refresher_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3121.4-3124.7" - switch \main_sdram_cmd_ready - attribute \src "ls180.v:3121.8-3121.28" - case 1'1 - assign $0\main_sdram_sequencer_start0[0:0] 1'1 - assign $0\builder_refresher_next_state[1:0] 2'10 - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3128.4-3132.7" - switch \main_sdram_sequencer_done0 - attribute \src "ls180.v:3128.8-3128.34" - case 1'1 - assign $0\main_sdram_cmd_valid[0:0] 1'0 - assign $0\main_sdram_cmd_last[0:0] 1'1 - assign $0\builder_refresher_next_state[1:0] 2'00 - case - end - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3135.4-3139.7" - switch 1'1 - attribute \src "ls180.v:3135.8-3135.12" - case 1'1 - attribute \src "ls180.v:3136.5-3138.8" - switch \main_sdram_wants_refresh - attribute \src "ls180.v:3136.9-3136.33" - case 1'1 - assign $0\builder_refresher_next_state[1:0] 2'01 - case - end - case - end - end - sync always - update \main_sdram_cmd_valid $0\main_sdram_cmd_valid[0:0] - update \main_sdram_cmd_last $0\main_sdram_cmd_last[0:0] - update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] - update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] - end - attribute \src "ls180.v:312.12-312.37" - process $proc$ls180.v:312$2877 - assign { } { } - assign $1\main_sdram_status[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_status $1\main_sdram_status[15:0] - end - attribute \src "ls180.v:3157.1-3164.4" - process $proc$ls180.v:3157$82 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3159.2-3163.5" - switch \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:3159.6-3159.48" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3161.6-3161.10" - case - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3162$84_Y - end - sync always - update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] - end - attribute \src "ls180.v:3168.1-3175.4" - process $proc$ls180.v:3168$91 - assign { } { } - assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3170.2-3174.5" - switch $and$ls180.v:3170$92_Y - attribute \src "ls180.v:3170.6-3170.115" - case 1'1 - attribute \src "ls180.v:3171.3-3173.6" - switch $ne$ls180.v:3171$93_Y - attribute \src "ls180.v:3171.7-3171.143" - case 1'1 - assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3172$94_Y - case - end - case - end - sync always - update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] - end - attribute \src "ls180.v:3190.1-3197.4" - process $proc$ls180.v:3190$95 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3192.2-3196.5" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3192.6-3192.58" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3193$96_Y - attribute \src "ls180.v:3194.6-3194.10" - case - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:3206.1-3299.4" - process $proc$ls180.v:3206$104 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 - assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state - attribute \src "ls180.v:3222.2-3298.9" - switch \builder_bankmachine0_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3224.4-3232.7" - switch $and$ls180.v:3224$105_Y - attribute \src "ls180.v:3224.8-3224.87" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3226.5-3228.8" - switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3226.9-3226.42" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3236.4-3238.7" - switch $and$ls180.v:3236$106_Y - attribute \src "ls180.v:3236.8-3236.87" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3242.4-3251.7" - switch \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:3242.8-3242.44" - case 1'1 - assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3247.5-3249.8" - switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3247.9-3247.42" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3254.4-3256.7" - switch \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:3254.8-3254.45" - case 1'1 - assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3259.4-3261.7" - switch $not$ls180.v:3259$107_Y - attribute \src "ls180.v:3259.8-3259.46" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine0_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine0_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3270.4-3296.7" - switch \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:3270.8-3270.43" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'100 - attribute \src "ls180.v:3272.8-3272.12" - case - attribute \src "ls180.v:3273.5-3295.8" - switch \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:3273.9-3273.56" - case 1'1 - attribute \src "ls180.v:3274.6-3294.9" - switch \main_sdram_bankmachine0_row_opened - attribute \src "ls180.v:3274.10-3274.44" - case 1'1 - attribute \src "ls180.v:3275.7-3291.10" - switch \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:3275.11-3275.42" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3277.8-3284.11" - switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:3277.12-3277.64" - case 1'1 - assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready - assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3281.12-3281.16" - case - assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready - assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3286.8-3288.11" - switch $and$ls180.v:3286$108_Y - attribute \src "ls180.v:3286.12-3286.88" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3289.11-3289.15" - case - assign $0\builder_bankmachine0_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3292.10-3292.14" - case - assign $0\builder_bankmachine0_next_state[2:0] 3'011 - end - case - end - end - end - sync always - update \main_sdram_bankmachine0_req_wdata_ready $0\main_sdram_bankmachine0_req_wdata_ready[0:0] - update \main_sdram_bankmachine0_req_rdata_valid $0\main_sdram_bankmachine0_req_rdata_valid[0:0] - update \main_sdram_bankmachine0_refresh_gnt $0\main_sdram_bankmachine0_refresh_gnt[0:0] - update \main_sdram_bankmachine0_cmd_valid $0\main_sdram_bankmachine0_cmd_valid[0:0] - update \main_sdram_bankmachine0_cmd_payload_cas $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] - update \main_sdram_bankmachine0_cmd_payload_ras $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] - update \main_sdram_bankmachine0_cmd_payload_we $0\main_sdram_bankmachine0_cmd_payload_we[0:0] - update \main_sdram_bankmachine0_cmd_payload_is_cmd $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine0_cmd_payload_is_read $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine0_cmd_payload_is_write $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine0_row_open $0\main_sdram_bankmachine0_row_open[0:0] - update \main_sdram_bankmachine0_row_close $0\main_sdram_bankmachine0_row_close[0:0] - update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] - end - attribute \src "ls180.v:3314.1-3321.4" - process $proc$ls180.v:3314$112 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3316.2-3320.5" - switch \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:3316.6-3316.48" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3318.6-3318.10" - case - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3319$114_Y - end - sync always - update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] - end - attribute \src "ls180.v:3325.1-3332.4" - process $proc$ls180.v:3325$121 - assign { } { } - assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3327.2-3331.5" - switch $and$ls180.v:3327$122_Y - attribute \src "ls180.v:3327.6-3327.115" - case 1'1 - attribute \src "ls180.v:3328.3-3330.6" - switch $ne$ls180.v:3328$123_Y - attribute \src "ls180.v:3328.7-3328.143" - case 1'1 - assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3329$124_Y - case - end - case - end - sync always - update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] - end - attribute \src "ls180.v:3347.1-3354.4" - process $proc$ls180.v:3347$125 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3349.2-3353.5" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3349.6-3349.58" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3350$126_Y - attribute \src "ls180.v:3351.6-3351.10" - case - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:3363.1-3456.4" - process $proc$ls180.v:3363$134 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 - assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state - attribute \src "ls180.v:3379.2-3455.9" - switch \builder_bankmachine1_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3381.4-3389.7" - switch $and$ls180.v:3381$135_Y - attribute \src "ls180.v:3381.8-3381.87" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3383.5-3385.8" - switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3383.9-3383.42" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3393.4-3395.7" - switch $and$ls180.v:3393$136_Y - attribute \src "ls180.v:3393.8-3393.87" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3399.4-3408.7" - switch \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:3399.8-3399.44" - case 1'1 - assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3404.5-3406.8" - switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3404.9-3404.42" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3411.4-3413.7" - switch \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:3411.8-3411.45" - case 1'1 - assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3416.4-3418.7" - switch $not$ls180.v:3416$137_Y - attribute \src "ls180.v:3416.8-3416.46" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine1_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine1_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3427.4-3453.7" - switch \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:3427.8-3427.43" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'100 - attribute \src "ls180.v:3429.8-3429.12" - case - attribute \src "ls180.v:3430.5-3452.8" - switch \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:3430.9-3430.56" - case 1'1 - attribute \src "ls180.v:3431.6-3451.9" - switch \main_sdram_bankmachine1_row_opened - attribute \src "ls180.v:3431.10-3431.44" - case 1'1 - attribute \src "ls180.v:3432.7-3448.10" - switch \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:3432.11-3432.42" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3434.8-3441.11" - switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:3434.12-3434.64" - case 1'1 - assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready - assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3438.12-3438.16" - case - assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready - assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3443.8-3445.11" - switch $and$ls180.v:3443$138_Y - attribute \src "ls180.v:3443.12-3443.88" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3446.11-3446.15" - case - assign $0\builder_bankmachine1_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3449.10-3449.14" - case - assign $0\builder_bankmachine1_next_state[2:0] 3'011 - end - case - end - end - end - sync always - update \main_sdram_bankmachine1_req_wdata_ready $0\main_sdram_bankmachine1_req_wdata_ready[0:0] - update \main_sdram_bankmachine1_req_rdata_valid $0\main_sdram_bankmachine1_req_rdata_valid[0:0] - update \main_sdram_bankmachine1_refresh_gnt $0\main_sdram_bankmachine1_refresh_gnt[0:0] - update \main_sdram_bankmachine1_cmd_valid $0\main_sdram_bankmachine1_cmd_valid[0:0] - update \main_sdram_bankmachine1_cmd_payload_cas $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] - update \main_sdram_bankmachine1_cmd_payload_ras $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] - update \main_sdram_bankmachine1_cmd_payload_we $0\main_sdram_bankmachine1_cmd_payload_we[0:0] - update \main_sdram_bankmachine1_cmd_payload_is_cmd $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine1_cmd_payload_is_read $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine1_cmd_payload_is_write $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine1_row_open $0\main_sdram_bankmachine1_row_open[0:0] - update \main_sdram_bankmachine1_row_close $0\main_sdram_bankmachine1_row_close[0:0] - update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] - end - attribute \src "ls180.v:342.12-342.46" - process $proc$ls180.v:342$2878 - assign { } { } - assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] - end - attribute \src "ls180.v:343.11-343.47" - process $proc$ls180.v:343$2879 - assign { } { } - assign $1\main_sdram_interface_wdata_we[1:0] 2'00 - sync always - sync init - update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] - end - attribute \src "ls180.v:345.12-345.45" - process $proc$ls180.v:345$2880 - assign { } { } - assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] - end - attribute \src "ls180.v:346.11-346.40" - process $proc$ls180.v:346$2881 - assign { } { } - assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 - sync always - sync init - update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] - end - attribute \src "ls180.v:347.5-347.35" - process $proc$ls180.v:347$2882 - assign { } { } - assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] - end - attribute \src "ls180.v:3471.1-3478.4" - process $proc$ls180.v:3471$142 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3473.2-3477.5" - switch \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:3473.6-3473.48" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3475.6-3475.10" - case - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3476$144_Y - end - sync always - update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] - end - attribute \src "ls180.v:348.5-348.34" - process $proc$ls180.v:348$2883 - assign { } { } - assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] - end - attribute \src "ls180.v:3482.1-3489.4" - process $proc$ls180.v:3482$151 - assign { } { } - assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3484.2-3488.5" - switch $and$ls180.v:3484$152_Y - attribute \src "ls180.v:3484.6-3484.115" - case 1'1 - attribute \src "ls180.v:3485.3-3487.6" - switch $ne$ls180.v:3485$153_Y - attribute \src "ls180.v:3485.7-3485.143" - case 1'1 - assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3486$154_Y - case - end - case - end - sync always - update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] - end - attribute \src "ls180.v:349.5-349.35" - process $proc$ls180.v:349$2884 - assign { } { } - assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] - end - attribute \src "ls180.v:350.5-350.34" - process $proc$ls180.v:350$2885 - assign { } { } - assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] - end - attribute \src "ls180.v:3504.1-3511.4" - process $proc$ls180.v:3504$155 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3506.2-3510.5" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3506.6-3506.58" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3507$156_Y - attribute \src "ls180.v:3508.6-3508.10" - case - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:3520.1-3613.4" - process $proc$ls180.v:3520$164 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 - assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state - attribute \src "ls180.v:3536.2-3612.9" - switch \builder_bankmachine2_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3538.4-3546.7" - switch $and$ls180.v:3538$165_Y - attribute \src "ls180.v:3538.8-3538.87" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3540.5-3542.8" - switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3540.9-3540.42" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3550.4-3552.7" - switch $and$ls180.v:3550$166_Y - attribute \src "ls180.v:3550.8-3550.87" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3556.4-3565.7" - switch \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:3556.8-3556.44" - case 1'1 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3561.5-3563.8" - switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3561.9-3561.42" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3568.4-3570.7" - switch \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:3568.8-3568.45" - case 1'1 - assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3573.4-3575.7" - switch $not$ls180.v:3573$167_Y - attribute \src "ls180.v:3573.8-3573.46" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine2_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine2_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3584.4-3610.7" - switch \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:3584.8-3584.43" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'100 - attribute \src "ls180.v:3586.8-3586.12" - case - attribute \src "ls180.v:3587.5-3609.8" - switch \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:3587.9-3587.56" - case 1'1 - attribute \src "ls180.v:3588.6-3608.9" - switch \main_sdram_bankmachine2_row_opened - attribute \src "ls180.v:3588.10-3588.44" - case 1'1 - attribute \src "ls180.v:3589.7-3605.10" - switch \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:3589.11-3589.42" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3591.8-3598.11" - switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:3591.12-3591.64" - case 1'1 - assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready - assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3595.12-3595.16" - case - assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready - assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3600.8-3602.11" - switch $and$ls180.v:3600$168_Y - attribute \src "ls180.v:3600.12-3600.88" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3603.11-3603.15" - case - assign $0\builder_bankmachine2_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3606.10-3606.14" - case - assign $0\builder_bankmachine2_next_state[2:0] 3'011 - end - case - end - end - end - sync always - update \main_sdram_bankmachine2_req_wdata_ready $0\main_sdram_bankmachine2_req_wdata_ready[0:0] - update \main_sdram_bankmachine2_req_rdata_valid $0\main_sdram_bankmachine2_req_rdata_valid[0:0] - update \main_sdram_bankmachine2_refresh_gnt $0\main_sdram_bankmachine2_refresh_gnt[0:0] - update \main_sdram_bankmachine2_cmd_valid $0\main_sdram_bankmachine2_cmd_valid[0:0] - update \main_sdram_bankmachine2_cmd_payload_cas $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] - update \main_sdram_bankmachine2_cmd_payload_ras $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] - update \main_sdram_bankmachine2_cmd_payload_we $0\main_sdram_bankmachine2_cmd_payload_we[0:0] - update \main_sdram_bankmachine2_cmd_payload_is_cmd $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine2_cmd_payload_is_read $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine2_cmd_payload_is_write $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine2_row_open $0\main_sdram_bankmachine2_row_open[0:0] - update \main_sdram_bankmachine2_row_close $0\main_sdram_bankmachine2_row_close[0:0] - update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] - end - attribute \src "ls180.v:354.5-354.35" - process $proc$ls180.v:354$2886 - assign { } { } - assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 - sync always - update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] - sync init - end - attribute \src "ls180.v:356.5-356.39" - process $proc$ls180.v:356$2887 - assign { } { } - assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] - end - attribute \src "ls180.v:358.5-358.39" - process $proc$ls180.v:358$2888 - assign { } { } - assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] - end - attribute \src "ls180.v:361.5-361.32" - process $proc$ls180.v:361$2889 - assign { } { } - assign $1\main_sdram_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] - end - attribute \src "ls180.v:362.5-362.32" - process $proc$ls180.v:362$2890 - assign { } { } - assign $1\main_sdram_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] - end - attribute \src "ls180.v:3628.1-3635.4" - process $proc$ls180.v:3628$172 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3630.2-3634.5" - switch \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:3630.6-3630.48" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3632.6-3632.10" - case - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3633$174_Y - end - sync always - update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] - end - attribute \src "ls180.v:363.5-363.31" - process $proc$ls180.v:363$2891 - assign { } { } - assign $1\main_sdram_cmd_last[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] - end - attribute \src "ls180.v:3639.1-3646.4" - process $proc$ls180.v:3639$181 - assign { } { } - assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3641.2-3645.5" - switch $and$ls180.v:3641$182_Y - attribute \src "ls180.v:3641.6-3641.115" - case 1'1 - attribute \src "ls180.v:3642.3-3644.6" - switch $ne$ls180.v:3642$183_Y - attribute \src "ls180.v:3642.7-3642.143" - case 1'1 - assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3643$184_Y - case - end - case - end - sync always - update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] - end - attribute \src "ls180.v:364.12-364.44" - process $proc$ls180.v:364$2892 - assign { } { } - assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] - end - attribute \src "ls180.v:365.11-365.43" - process $proc$ls180.v:365$2893 - assign { } { } - assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 - sync always - sync init - update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] - end - attribute \src "ls180.v:366.5-366.38" - process $proc$ls180.v:366$2894 - assign { } { } - assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:3661.1-3668.4" - process $proc$ls180.v:3661$185 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3663.2-3667.5" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3663.6-3663.58" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3664$186_Y - attribute \src "ls180.v:3665.6-3665.10" - case - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:367.5-367.38" - process $proc$ls180.v:367$2895 - assign { } { } - assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:3677.1-3770.4" - process $proc$ls180.v:3677$194 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 - assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state - attribute \src "ls180.v:3693.2-3769.9" - switch \builder_bankmachine3_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3695.4-3703.7" - switch $and$ls180.v:3695$195_Y - attribute \src "ls180.v:3695.8-3695.87" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3697.5-3699.8" - switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3697.9-3697.42" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3707.4-3709.7" - switch $and$ls180.v:3707$196_Y - attribute \src "ls180.v:3707.8-3707.87" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3713.4-3722.7" - switch \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:3713.8-3713.44" - case 1'1 - assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3718.5-3720.8" - switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3718.9-3718.42" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3725.4-3727.7" - switch \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:3725.8-3725.45" - case 1'1 - assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3730.4-3732.7" - switch $not$ls180.v:3730$197_Y - attribute \src "ls180.v:3730.8-3730.46" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine3_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine3_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3741.4-3767.7" - switch \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:3741.8-3741.43" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'100 - attribute \src "ls180.v:3743.8-3743.12" - case - attribute \src "ls180.v:3744.5-3766.8" - switch \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:3744.9-3744.56" - case 1'1 - attribute \src "ls180.v:3745.6-3765.9" - switch \main_sdram_bankmachine3_row_opened - attribute \src "ls180.v:3745.10-3745.44" - case 1'1 - attribute \src "ls180.v:3746.7-3762.10" - switch \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:3746.11-3746.42" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3748.8-3755.11" - switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:3748.12-3748.64" - case 1'1 - assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready - assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3752.12-3752.16" - case - assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready - assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3757.8-3759.11" - switch $and$ls180.v:3757$198_Y - attribute \src "ls180.v:3757.12-3757.88" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3760.11-3760.15" - case - assign $0\builder_bankmachine3_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3763.10-3763.14" - case - assign $0\builder_bankmachine3_next_state[2:0] 3'011 - end - case - end - end - end - sync always - update \main_sdram_bankmachine3_req_wdata_ready $0\main_sdram_bankmachine3_req_wdata_ready[0:0] - update \main_sdram_bankmachine3_req_rdata_valid $0\main_sdram_bankmachine3_req_rdata_valid[0:0] - update \main_sdram_bankmachine3_refresh_gnt $0\main_sdram_bankmachine3_refresh_gnt[0:0] - update \main_sdram_bankmachine3_cmd_valid $0\main_sdram_bankmachine3_cmd_valid[0:0] - update \main_sdram_bankmachine3_cmd_payload_cas $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] - update \main_sdram_bankmachine3_cmd_payload_ras $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] - update \main_sdram_bankmachine3_cmd_payload_we $0\main_sdram_bankmachine3_cmd_payload_we[0:0] - update \main_sdram_bankmachine3_cmd_payload_is_cmd $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine3_cmd_payload_is_read $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine3_cmd_payload_is_write $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine3_row_open $0\main_sdram_bankmachine3_row_open[0:0] - update \main_sdram_bankmachine3_row_close $0\main_sdram_bankmachine3_row_close[0:0] - update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] - end - attribute \src "ls180.v:368.5-368.37" - process $proc$ls180.v:368$2896 - assign { } { } - assign $1\main_sdram_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] - end - attribute \src "ls180.v:369.5-369.42" - process $proc$ls180.v:369$2897 - assign { } { } - assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 - sync always - update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] - sync init - end - attribute \src "ls180.v:370.5-370.43" - process $proc$ls180.v:370$2898 - assign { } { } - assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 - sync always - update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] - sync init - end - attribute \src "ls180.v:376.11-376.44" - process $proc$ls180.v:376$2899 - assign { } { } - assign $1\main_sdram_timer_count1[9:0] 10'1100001101 - sync always - sync init - update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] - end - attribute \src "ls180.v:378.5-378.38" - process $proc$ls180.v:378$2900 - assign { } { } - assign $1\main_sdram_postponer_req_o[0:0] 1'0 - sync always - sync init - update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] - end - attribute \src "ls180.v:379.5-379.38" - process $proc$ls180.v:379$2901 - assign { } { } - assign $1\main_sdram_postponer_count[0:0] 1'0 - sync always - sync init - update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] - end - attribute \src "ls180.v:3790.1-3796.4" - process $proc$ls180.v:3790$237 - assign { } { } - assign { } { } - assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3792$250_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3793$263_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3794$276_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3795$289_Y - sync always - update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] - end - attribute \src "ls180.v:380.5-380.39" - process $proc$ls180.v:380$2902 - assign { } { } - assign $1\main_sdram_sequencer_start0[0:0] 1'0 - sync always - sync init - update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] - end - attribute \src "ls180.v:3804.1-3809.4" - process $proc$ls180.v:3804$290 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:3806.2-3808.5" - switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3806.6-3806.37" - case 1'1 - assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 - case - end - sync always - update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:3810.1-3815.4" - process $proc$ls180.v:3810$291 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:3812.2-3814.5" - switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3812.6-3812.37" - case 1'1 - assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 - case - end - sync always - update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:3816.1-3821.4" - process $proc$ls180.v:3816$292 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:3818.2-3820.5" - switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3818.6-3818.37" - case 1'1 - assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 - case - end - sync always - update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] - end - attribute \src "ls180.v:3823.1-3829.4" - process $proc$ls180.v:3823$295 - assign { } { } - assign { } { } - assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3825$308_Y - assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3826$321_Y - assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3827$334_Y - assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3828$347_Y - sync always - update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] - end - attribute \src "ls180.v:383.5-383.38" - process $proc$ls180.v:383$2903 - assign { } { } - assign $1\main_sdram_sequencer_done1[0:0] 1'0 - sync always - sync init - update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] - end - attribute \src "ls180.v:3837.1-3842.4" - process $proc$ls180.v:3837$348 - assign { } { } - assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:3839.2-3841.5" - switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3839.6-3839.37" - case 1'1 - assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 - case - end - sync always - update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:384.11-384.46" - process $proc$ls180.v:384$2904 - assign { } { } - assign $1\main_sdram_sequencer_counter[3:0] 4'0000 - sync always - sync init - update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] - end - attribute \src "ls180.v:3843.1-3848.4" - process $proc$ls180.v:3843$349 - assign { } { } - assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:3845.2-3847.5" - switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3845.6-3845.37" - case 1'1 - assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 - case - end - sync always - update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:3849.1-3854.4" - process $proc$ls180.v:3849$350 - assign { } { } - assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:3851.2-3853.5" - switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3851.6-3851.37" - case 1'1 - assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 - case - end - sync always - update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] - end - attribute \src "ls180.v:385.5-385.38" - process $proc$ls180.v:385$2905 - assign { } { } - assign $1\main_sdram_sequencer_count[0:0] 1'0 - sync always - sync init - update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] - end - attribute \src "ls180.v:3855.1-3863.4" - process $proc$ls180.v:3855$351 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3857.2-3859.5" - switch $and$ls180.v:3857$354_Y - attribute \src "ls180.v:3857.6-3857.115" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:3860.2-3862.5" - switch $and$ls180.v:3860$357_Y - attribute \src "ls180.v:3860.6-3860.115" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] - end - attribute \src "ls180.v:3864.1-3872.4" - process $proc$ls180.v:3864$358 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3866.2-3868.5" - switch $and$ls180.v:3866$361_Y - attribute \src "ls180.v:3866.6-3866.115" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:3869.2-3871.5" - switch $and$ls180.v:3869$364_Y - attribute \src "ls180.v:3869.6-3869.115" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] - end - attribute \src "ls180.v:3873.1-3881.4" - process $proc$ls180.v:3873$365 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3875.2-3877.5" - switch $and$ls180.v:3875$368_Y - attribute \src "ls180.v:3875.6-3875.115" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:3878.2-3880.5" - switch $and$ls180.v:3878$371_Y - attribute \src "ls180.v:3878.6-3878.115" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] - end - attribute \src "ls180.v:3882.1-3890.4" - process $proc$ls180.v:3882$372 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3884.2-3886.5" - switch $and$ls180.v:3884$375_Y - attribute \src "ls180.v:3884.6-3884.115" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:3887.2-3889.5" - switch $and$ls180.v:3887$378_Y - attribute \src "ls180.v:3887.6-3887.115" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] - end - attribute \src "ls180.v:3895.1-3967.4" - process $proc$ls180.v:3895$381 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 - assign $0\main_sdram_en0[0:0] 1'0 - assign { } { } - assign $0\main_sdram_en1[0:0] 1'0 - assign $0\main_sdram_choose_req_want_reads[0:0] 1'0 - assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 - assign $0\main_sdram_cmd_ready[0:0] 1'0 - assign { } { } - assign $0\main_sdram_steerer_sel[1:0] 2'00 - assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed - assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state - attribute \src "ls180.v:3907.2-3966.9" - switch \builder_multiplexer_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_en1[0:0] 1'1 - assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 - assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:3911.4-3917.7" - switch 1'1 - attribute \src "ls180.v:3911.8-3911.12" - case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3912$388_Y - case - end - attribute \src "ls180.v:3919.4-3923.7" - switch \main_sdram_read_available - attribute \src "ls180.v:3919.8-3919.33" - case 1'1 - attribute \src "ls180.v:3920.5-3922.8" - switch $or$ls180.v:3920$390_Y - attribute \src "ls180.v:3920.9-3920.63" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'011 - case - end - case - end - attribute \src "ls180.v:3924.4-3926.7" - switch \main_sdram_go_to_refresh - attribute \src "ls180.v:3924.8-3924.32" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_steerer_sel[1:0] 2'11 - assign $0\main_sdram_cmd_ready[0:0] 1'1 - attribute \src "ls180.v:3931.4-3933.7" - switch \main_sdram_cmd_last - attribute \src "ls180.v:3931.8-3931.27" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3936.4-3938.7" - switch \main_sdram_twtrcon_ready - attribute \src "ls180.v:3936.8-3936.32" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_multiplexer_next_state[2:0] 3'101 - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_multiplexer_next_state[2:0] 3'001 - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdram_en0[0:0] 1'1 - assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 - assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:3949.4-3955.7" - switch 1'1 - attribute \src "ls180.v:3949.8-3949.12" - case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3950$397_Y - case - end - attribute \src "ls180.v:3957.4-3961.7" - switch \main_sdram_write_available - attribute \src "ls180.v:3957.8-3957.34" - case 1'1 - attribute \src "ls180.v:3958.5-3960.8" - switch $or$ls180.v:3958$399_Y - attribute \src "ls180.v:3958.9-3958.62" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'100 - case - end - case - end - attribute \src "ls180.v:3962.4-3964.7" - switch \main_sdram_go_to_refresh - attribute \src "ls180.v:3962.8-3962.32" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'010 - case - end - end - sync always - update \main_sdram_cmd_ready $0\main_sdram_cmd_ready[0:0] - update \main_sdram_choose_req_want_reads $0\main_sdram_choose_req_want_reads[0:0] - update \main_sdram_choose_req_want_writes $0\main_sdram_choose_req_want_writes[0:0] - update \main_sdram_choose_req_want_activates $0\main_sdram_choose_req_want_activates[0:0] - update \main_sdram_choose_req_cmd_ready $0\main_sdram_choose_req_cmd_ready[0:0] - update \main_sdram_steerer_sel $0\main_sdram_steerer_sel[1:0] - update \main_sdram_en0 $0\main_sdram_en0[0:0] - update \main_sdram_en1 $0\main_sdram_en1[0:0] - update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] - end - attribute \src "ls180.v:391.5-391.51" - process $proc$ls180.v:391$2906 - assign { } { } - assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] - end - attribute \src "ls180.v:392.5-392.51" - process $proc$ls180.v:392$2907 - assign { } { } - assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] - end - attribute \src "ls180.v:394.5-394.47" - process $proc$ls180.v:394$2908 - assign { } { } - assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] - end - attribute \src "ls180.v:395.5-395.45" - process $proc$ls180.v:395$2909 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] - end - attribute \src "ls180.v:396.5-396.45" - process $proc$ls180.v:396$2910 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] - end - attribute \src "ls180.v:397.12-397.57" - process $proc$ls180.v:397$2911 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] - end - attribute \src "ls180.v:399.5-399.51" - process $proc$ls180.v:399$2912 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:3991.1-4004.4" - process $proc$ls180.v:3991$528 - assign { } { } - assign { } { } - assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 - assign $0\main_sdram_interface_wdata_we[1:0] 2'00 - attribute \src "ls180.v:3994.2-4003.9" - switch \builder_new_master_wdata_ready - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdram_interface_wdata[15:0] \main_port_wdata_payload_data - assign $0\main_sdram_interface_wdata_we[1:0] \main_port_wdata_payload_we - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 - assign $0\main_sdram_interface_wdata_we[1:0] 2'00 - end - sync always - update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] - update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] - end - attribute \src "ls180.v:400.5-400.51" - process $proc$ls180.v:400$2913 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:401.5-401.50" - process $proc$ls180.v:401$2914 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] - end - attribute \src "ls180.v:4011.1-4021.4" - process $proc$ls180.v:4011$530 - assign { } { } - assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 - attribute \src "ls180.v:4013.2-4020.9" - switch \main_converter_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [15:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [31:16] - case - end - sync always - update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] - end - attribute \src "ls180.v:402.5-402.54" - process $proc$ls180.v:402$2915 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:4023.1-4069.4" - process $proc$ls180.v:4023$531 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_converter_skip[0:0] 1'0 - assign $0\main_wb_sdram_ack[0:0] 1'0 - assign { } { } - assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_converter_counter_converter_next_value[0:0] 1'0 - assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0 - assign $0\main_litedram_wb_sel[1:0] 2'00 - assign $0\main_litedram_wb_cyc[0:0] 1'0 - assign $0\main_litedram_wb_stb[0:0] 1'0 - assign $0\main_litedram_wb_we[0:0] 1'0 - assign $0\builder_converter_next_state[0:0] \builder_converter_state - attribute \src "ls180.v:4035.2-4068.9" - switch \builder_converter_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } - attribute \src "ls180.v:4038.4-4045.11" - switch \main_converter_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [1:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] - case - end - attribute \src "ls180.v:4046.4-4059.7" - switch $and$ls180.v:4046$532_Y - attribute \src "ls180.v:4046.8-4046.47" - case 1'1 - assign $0\main_converter_skip[0:0] $eq$ls180.v:4047$533_Y - assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we - assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4049$534_Y - assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4050$535_Y - attribute \src "ls180.v:4051.5-4058.8" - switch $or$ls180.v:4051$536_Y - attribute \src "ls180.v:4051.9-4051.53" - case 1'1 - assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4052$537_Y - assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4054.6-4057.9" - switch $eq$ls180.v:4054$538_Y - attribute \src "ls180.v:4054.10-4054.42" - case 1'1 - assign $0\main_wb_sdram_ack[0:0] 1'1 - assign $0\builder_converter_next_state[0:0] 1'0 - case - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_converter_counter_converter_next_value[0:0] 1'0 - assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4064.4-4066.7" - switch $and$ls180.v:4064$539_Y - attribute \src "ls180.v:4064.8-4064.47" - case 1'1 - assign $0\builder_converter_next_state[0:0] 1'1 - case - end - end - sync always - update \main_wb_sdram_ack $0\main_wb_sdram_ack[0:0] - update \main_litedram_wb_adr $0\main_litedram_wb_adr[29:0] - update \main_litedram_wb_sel $0\main_litedram_wb_sel[1:0] - update \main_litedram_wb_cyc $0\main_litedram_wb_cyc[0:0] - update \main_litedram_wb_stb $0\main_litedram_wb_stb[0:0] - update \main_litedram_wb_we $0\main_litedram_wb_we[0:0] - update \main_converter_skip $0\main_converter_skip[0:0] - update \builder_converter_next_state $0\builder_converter_next_state[0:0] - update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] - update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] - end - attribute \src "ls180.v:403.5-403.55" - process $proc$ls180.v:403$2916 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:404.5-404.56" - process $proc$ls180.v:404$2917 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:405.5-405.50" - process $proc$ls180.v:405$2918 - assign { } { } - assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] - end - attribute \src "ls180.v:408.5-408.67" - process $proc$ls180.v:408$2919 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:409.5-409.66" - process $proc$ls180.v:409$2920 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:4114.1-4119.4" - process $proc$ls180.v:4114$571 - assign { } { } - assign $0\main_uart_tx_clear[0:0] 1'0 - attribute \src "ls180.v:4116.2-4118.5" - switch $and$ls180.v:4116$572_Y - attribute \src "ls180.v:4116.6-4116.79" - case 1'1 - assign $0\main_uart_tx_clear[0:0] 1'1 - case - end - sync always - update \main_uart_tx_clear $0\main_uart_tx_clear[0:0] - end - attribute \src "ls180.v:4120.1-4124.4" - process $proc$ls180.v:4120$573 - assign { } { } - assign { } { } - assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status - assign $0\main_uart_eventmanager_status_w[1:0] [1] \main_uart_rx_status - sync always - update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0] - end - attribute \src "ls180.v:4125.1-4130.4" - process $proc$ls180.v:4125$574 - assign { } { } - assign $0\main_uart_rx_clear[0:0] 1'0 - attribute \src "ls180.v:4127.2-4129.5" - switch $and$ls180.v:4127$575_Y - attribute \src "ls180.v:4127.6-4127.79" - case 1'1 - assign $0\main_uart_rx_clear[0:0] 1'1 - case - end - sync always - update \main_uart_rx_clear $0\main_uart_rx_clear[0:0] - end - attribute \src "ls180.v:4131.1-4135.4" - process $proc$ls180.v:4131$576 - assign { } { } - assign { } { } - assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending - assign $0\main_uart_eventmanager_pending_w[1:0] [1] \main_uart_rx_pending - sync always - update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0] - end - attribute \src "ls180.v:4153.1-4160.4" - process $proc$ls180.v:4153$584 - assign { } { } - assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4155.2-4159.5" - switch \main_uart_tx_fifo_replace - attribute \src "ls180.v:4155.6-4155.31" - case 1'1 - assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4156$585_Y - attribute \src "ls180.v:4157.6-4157.10" - case - assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce - end - sync always - update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:4183.1-4190.4" - process $proc$ls180.v:4183$595 - assign { } { } - assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4185.2-4189.5" - switch \main_uart_rx_fifo_replace - attribute \src "ls180.v:4185.6-4185.31" - case 1'1 - assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4186$596_Y - attribute \src "ls180.v:4187.6-4187.10" - case - assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce - end - sync always - update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:4213.1-4261.4" - process $proc$ls180.v:4213$606 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_spi_master_done0[0:0] 1'0 - assign $0\main_spi_master_miso_latch[0:0] 1'0 - assign $0\main_spi_master_irq[0:0] 1'0 - assign { } { } - assign $0\main_spi_master_count_spimaster0_next_value[2:0] 3'000 - assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'0 - assign $0\main_spi_master_clk_enable[0:0] 1'0 - assign $0\main_spi_master_cs_enable[0:0] 1'0 - assign $0\main_spi_master_mosi_latch[0:0] 1'0 - assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state - attribute \src "ls180.v:4224.2-4260.9" - switch \builder_spimaster0_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_spi_master_count_spimaster0_next_value[2:0] 3'000 - assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4228.4-4231.7" - switch \main_spi_master_clk_fall - attribute \src "ls180.v:4228.8-4228.32" - case 1'1 - assign $0\main_spi_master_cs_enable[0:0] 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'10 - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_spi_master_clk_enable[0:0] 1'1 - assign $0\main_spi_master_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4236.4-4242.7" - switch \main_spi_master_clk_fall - attribute \src "ls180.v:4236.8-4236.32" - case 1'1 - assign $0\main_spi_master_count_spimaster0_next_value[2:0] $add$ls180.v:4237$607_Y - assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4239.5-4241.8" - switch $eq$ls180.v:4239$609_Y - attribute \src "ls180.v:4239.9-4239.68" - case 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'11 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\main_spi_master_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4246.4-4250.7" - switch \main_spi_master_clk_rise - attribute \src "ls180.v:4246.8-4246.32" - case 1'1 - assign $0\main_spi_master_miso_latch[0:0] 1'1 - assign $0\main_spi_master_irq[0:0] 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'00 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_spi_master_done0[0:0] 1'1 - attribute \src "ls180.v:4254.4-4258.7" - switch \main_spi_master_start0 - attribute \src "ls180.v:4254.8-4254.30" - case 1'1 - assign $0\main_spi_master_done0[0:0] 1'0 - assign $0\main_spi_master_mosi_latch[0:0] 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'01 - case - end - end - sync always - update \main_spi_master_done0 $0\main_spi_master_done0[0:0] - update \main_spi_master_irq $0\main_spi_master_irq[0:0] - update \main_spi_master_clk_enable $0\main_spi_master_clk_enable[0:0] - update \main_spi_master_cs_enable $0\main_spi_master_cs_enable[0:0] - update \main_spi_master_mosi_latch $0\main_spi_master_mosi_latch[0:0] - update \main_spi_master_miso_latch $0\main_spi_master_miso_latch[0:0] - update \builder_spimaster0_next_state $0\builder_spimaster0_next_state[1:0] - update \main_spi_master_count_spimaster0_next_value $0\main_spi_master_count_spimaster0_next_value[2:0] - update \main_spi_master_count_spimaster0_next_value_ce $0\main_spi_master_count_spimaster0_next_value_ce[0:0] - end - attribute \src "ls180.v:424.11-424.68" - process $proc$ls180.v:424$2921 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:425.5-425.64" - process $proc$ls180.v:425$2922 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:426.11-426.70" - process $proc$ls180.v:426$2923 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:427.11-427.70" - process $proc$ls180.v:427$2924 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:428.11-428.73" - process $proc$ls180.v:428$2925 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:4293.1-4321.4" - process $proc$ls180.v:4293$631 - assign { } { } - assign $0\main_sdphy_clocker_clk1[0:0] 1'0 - attribute \src "ls180.v:4295.2-4320.9" - switch \main_sdphy_clocker_storage - attribute \src "ls180.v:0.0-0.0" - case 9'000000100 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [1] - attribute \src "ls180.v:0.0-0.0" - case 9'000001000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [2] - attribute \src "ls180.v:0.0-0.0" - case 9'000010000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [3] - attribute \src "ls180.v:0.0-0.0" - case 9'000100000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [4] - attribute \src "ls180.v:0.0-0.0" - case 9'001000000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [5] - attribute \src "ls180.v:0.0-0.0" - case 9'010000000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [6] - attribute \src "ls180.v:0.0-0.0" - case 9'100000000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [7] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [0] - end - sync always - update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] - end - attribute \src "ls180.v:4323.1-4356.4" - process $proc$ls180.v:4323$634 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 - assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 - assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:4333.2-4355.9" - switch \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'1 - assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1 - assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1 - assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4340.4-4346.7" - switch \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:4340.8-4340.38" - case 1'1 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4341$635_Y - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4343.5-4345.8" - switch $eq$ls180.v:4343$636_Y - attribute \src "ls180.v:4343.9-4343.41" - case 1'1 - assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4351.4-4353.7" - switch \main_sdphy_init_initialize_re - attribute \src "ls180.v:4351.8-4351.37" - case 1'1 - assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 - case - end - end - sync always - update \main_sdphy_init_pads_out_payload_clk $0\main_sdphy_init_pads_out_payload_clk[0:0] - update \main_sdphy_init_pads_out_payload_cmd_o $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] - update \main_sdphy_init_pads_out_payload_cmd_oe $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - update \main_sdphy_init_pads_out_payload_data_o $0\main_sdphy_init_pads_out_payload_data_o[3:0] - update \main_sdphy_init_pads_out_payload_data_oe $0\main_sdphy_init_pads_out_payload_data_oe[0:0] - update \builder_sdphy_sdphyinit_next_state $0\builder_sdphy_sdphyinit_next_state[0:0] - update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - end - attribute \src "ls180.v:4357.1-4433.4" - process $proc$ls180.v:4357$637 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 - assign { } { } - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 - assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_cmdw_done[0:0] 1'0 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:4367.2-4432.9" - switch \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 - attribute \src "ls180.v:4371.4-4396.11" - switch \main_sdphy_cmdw_count - attribute \src "ls180.v:0.0-0.0" - case 8'00000000 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [7] - attribute \src "ls180.v:0.0-0.0" - case 8'00000001 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [6] - attribute \src "ls180.v:0.0-0.0" - case 8'00000010 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [5] - attribute \src "ls180.v:0.0-0.0" - case 8'00000011 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [4] - attribute \src "ls180.v:0.0-0.0" - case 8'00000100 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [3] - attribute \src "ls180.v:0.0-0.0" - case 8'00000101 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [2] - attribute \src "ls180.v:0.0-0.0" - case 8'00000110 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [1] - attribute \src "ls180.v:0.0-0.0" - case 8'00000111 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0] - case - end - attribute \src "ls180.v:4397.4-4408.7" - switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4397.8-4397.38" - case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4398$638_Y - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4400.5-4407.8" - switch $eq$ls180.v:4400$639_Y - attribute \src "ls180.v:4400.9-4400.40" - case 1'1 - attribute \src "ls180.v:4401.6-4406.9" - switch \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:4401.10-4401.35" - case 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 - attribute \src "ls180.v:4403.10-4403.14" - case - assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4414.4-4421.7" - switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4414.8-4414.38" - case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4415$640_Y - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4417.5-4420.8" - switch $eq$ls180.v:4417$641_Y - attribute \src "ls180.v:4417.9-4417.40" - case 1'1 - assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4426.4-4430.7" - switch $and$ls180.v:4426$642_Y - attribute \src "ls180.v:4426.8-4426.69" - case 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 - attribute \src "ls180.v:4428.8-4428.12" - case - assign $0\main_sdphy_cmdw_done[0:0] 1'1 - end - end - sync always - update \main_sdphy_cmdw_pads_out_payload_clk $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] - update \main_sdphy_cmdw_pads_out_payload_cmd_o $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - update \main_sdphy_cmdw_pads_out_payload_cmd_oe $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - update \main_sdphy_cmdw_sink_ready $0\main_sdphy_cmdw_sink_ready[0:0] - update \main_sdphy_cmdw_done $0\main_sdphy_cmdw_done[0:0] - update \builder_sdphy_sdphycmdw_next_state $0\builder_sdphy_sdphycmdw_next_state[1:0] - update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - end - attribute \src "ls180.v:4467.1-4560.4" - process $proc$ls180.v:4467$651 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 - assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0 - assign { } { } - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 - assign $0\main_sdphy_cmdr_source_last[0:0] 1'0 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:4485.2-4559.9" - switch \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4493$652_Y - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4490.4-4492.7" - switch \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:4490.8-4490.49" - case 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:4495.4-4498.7" - switch $eq$ls180.v:4495$653_Y - attribute \src "ls180.v:4495.8-4495.41" - case 1'1 - assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0 - assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4504$655_Y - assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4521$658_Y - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4506.4-4520.7" - switch $and$ls180.v:4506$656_Y - attribute \src "ls180.v:4506.8-4506.69" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4508$657_Y - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4510.5-4519.8" - switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:4510.9-4510.36" - case 1'1 - assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4512.6-4518.9" - switch \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:4512.10-4512.35" - case 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 - attribute \src "ls180.v:4516.10-4516.14" - case - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 - end - case - end - case - end - attribute \src "ls180.v:4523.4-4526.7" - switch $eq$ls180.v:4523$659_Y - attribute \src "ls180.v:4523.8-4523.41" - case 1'1 - assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4532.4-4538.7" - switch \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:4532.8-4532.38" - case 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4533$660_Y - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4535.5-4537.8" - switch $eq$ls180.v:4535$661_Y - attribute \src "ls180.v:4535.9-4535.40" - case 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1 - assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001 - assign $0\main_sdphy_cmdr_source_last[0:0] 1'1 - attribute \src "ls180.v:4544.4-4546.7" - switch $and$ls180.v:4544$662_Y - attribute \src "ls180.v:4544.8-4544.69" - case 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4553.4-4557.7" - switch $and$ls180.v:4553$664_Y - attribute \src "ls180.v:4553.8-4553.94" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'001 - case - end - end - sync always - update \main_sdphy_cmdr_pads_out_payload_clk $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] - update \main_sdphy_cmdr_pads_out_payload_cmd_o $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - update \main_sdphy_cmdr_pads_out_payload_cmd_oe $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - update \main_sdphy_cmdr_sink_ready $0\main_sdphy_cmdr_sink_ready[0:0] - update \main_sdphy_cmdr_source_valid $0\main_sdphy_cmdr_source_valid[0:0] - update \main_sdphy_cmdr_source_last $0\main_sdphy_cmdr_source_last[0:0] - update \main_sdphy_cmdr_source_payload_data $0\main_sdphy_cmdr_source_payload_data[7:0] - update \main_sdphy_cmdr_source_payload_status $0\main_sdphy_cmdr_source_payload_status[2:0] - update \main_sdphy_cmdr_cmdr_source_source_ready0 $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - update \builder_sdphy_sdphycmdr_next_state $0\builder_sdphy_sdphycmdr_next_state[2:0] - update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - end - attribute \src "ls180.v:449.5-449.59" - process $proc$ls180.v:449$2926 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:451.5-451.59" - process $proc$ls180.v:451$2927 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:452.5-452.58" - process $proc$ls180.v:452$2928 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:453.5-453.64" - process $proc$ls180.v:453$2929 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:454.12-454.74" - process $proc$ls180.v:454$2930 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:455.12-455.47" - process $proc$ls180.v:455$2931 - assign { } { } - assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] - end - attribute \src "ls180.v:456.5-456.46" - process $proc$ls180.v:456$2932 - assign { } { } - assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] - end - attribute \src "ls180.v:458.5-458.44" - process $proc$ls180.v:458$2933 - assign { } { } - assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] - end - attribute \src "ls180.v:459.5-459.45" - process $proc$ls180.v:459$2934 - assign { } { } - assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] - end - attribute \src "ls180.v:4594.1-4621.4" - process $proc$ls180.v:4594$672 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_dataw_valid[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 - assign { } { } - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - assign $0\main_sdphy_dataw_error[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 - assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:4602.2-4620.9" - switch \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 - assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1 - attribute \src "ls180.v:4607.4-4611.7" - switch \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:4607.8-4607.50" - case 1'1 - assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4608$673_Y - assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4609$674_Y - assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 - case - end - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:4614.4-4618.7" - switch \main_sdphy_dataw_start - attribute \src "ls180.v:4614.8-4614.30" - case 1'1 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 - assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'1 - case - end - end - sync always - update \main_sdphy_dataw_valid $0\main_sdphy_dataw_valid[0:0] - update \main_sdphy_dataw_error $0\main_sdphy_dataw_error[0:0] - update \main_sdphy_dataw_crcr_source_source_ready0 $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] - update \builder_sdphy_sdphycrcr_next_state $0\builder_sdphy_sdphycrcr_next_state[0:0] - update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - end - attribute \src "ls180.v:460.5-460.54" - process $proc$ls180.v:460$2935 - assign { } { } - assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:462.32-462.76" - process $proc$ls180.v:462$2936 - assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] - end - attribute \src "ls180.v:4622.1-4694.4" - process $proc$ls180.v:4622$675 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 - assign $0\main_sdphy_dataw_start[0:0] 1'0 - assign $0\main_sdphy_dataw_stop[0:0] 1'0 - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 - assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state - attribute \src "ls180.v:4633.2-4693.9" - switch \builder_sdphy_fsm_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - attribute \src "ls180.v:4638.4-4640.7" - switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4638.8-4638.39" - case 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4643$676_Y - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - attribute \src "ls180.v:4646.4-4653.11" - switch \main_sdphy_dataw_count - attribute \src "ls180.v:0.0-0.0" - case 8'00000000 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [7:4] - attribute \src "ls180.v:0.0-0.0" - case 8'00000001 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0] - case - end - attribute \src "ls180.v:4654.4-4666.7" - switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4654.8-4654.39" - case 1'1 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4655$677_Y - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4657.5-4665.8" - switch $eq$ls180.v:4657$678_Y - attribute \src "ls180.v:4657.9-4657.41" - case 1'1 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4660.6-4664.9" - switch \main_sdphy_dataw_sink_last - attribute \src "ls180.v:4660.10-4660.36" - case 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:4662.10-4662.14" - case - assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4672.4-4675.7" - switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4672.8-4672.39" - case 1'1 - assign $0\main_sdphy_dataw_start[0:0] 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4679.4-4684.7" - switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4679.8-4679.39" - case 1'1 - attribute \src "ls180.v:4680.5-4683.8" - switch \main_sdphy_dataw_pads_in_payload_data_i [0] - attribute \src "ls180.v:4680.9-4680.51" - case 1'1 - assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4689.4-4691.7" - switch $and$ls180.v:4689$679_Y - attribute \src "ls180.v:4689.8-4689.71" - case 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 - case - end - end - sync always - update \main_sdphy_dataw_pads_out_payload_clk $0\main_sdphy_dataw_pads_out_payload_clk[0:0] - update \main_sdphy_dataw_pads_out_payload_data_o $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] - update \main_sdphy_dataw_pads_out_payload_data_oe $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - update \main_sdphy_dataw_sink_ready $0\main_sdphy_dataw_sink_ready[0:0] - update \main_sdphy_dataw_stop $0\main_sdphy_dataw_stop[0:0] - update \main_sdphy_dataw_start $0\main_sdphy_dataw_start[0:0] - update \builder_sdphy_fsm_next_state $0\builder_sdphy_fsm_next_state[2:0] - update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:463.11-463.55" - process $proc$ls180.v:463$2937 - assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] - end - attribute \src "ls180.v:465.32-465.75" - process $proc$ls180.v:465$2938 - assign { } { } - assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:467.32-467.76" - process $proc$ls180.v:467$2939 - assign { } { } - assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:4728.1-4829.4" - process $proc$ls180.v:4728$687 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 - assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 - assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 - assign $0\main_sdphy_datar_source_valid[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 - assign $0\main_sdphy_datar_source_last[0:0] 1'0 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_datar_stop[0:0] 1'0 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:4745.2-4828.9" - switch \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 - assign { } { } - assign { } { } - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4755$689_Y - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4752.4-4754.7" - switch \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:4752.8-4752.51" - case 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:4757.4-4760.7" - switch $eq$ls180.v:4757$690_Y - attribute \src "ls180.v:4757.8-4757.42" - case 1'1 - assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4766$693_Y - assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4787$695_Y - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4768.4-4786.7" - switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:4768.8-4768.37" - case 1'1 - attribute \src "ls180.v:4769.5-4785.8" - switch \main_sdphy_datar_source_ready - attribute \src "ls180.v:4769.9-4769.38" - case 1'1 - assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4771$694_Y - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4773.6-4782.9" - switch \main_sdphy_datar_source_last - attribute \src "ls180.v:4773.10-4773.38" - case 1'1 - assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4775.7-4781.10" - switch \main_sdphy_datar_sink_last - attribute \src "ls180.v:4775.11-4775.37" - case 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 - attribute \src "ls180.v:4779.11-4779.15" - case - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 - end - case - end - attribute \src "ls180.v:4783.9-4783.13" - case - assign $0\main_sdphy_datar_stop[0:0] 1'1 - end - case - end - attribute \src "ls180.v:4789.4-4792.7" - switch $eq$ls180.v:4789$696_Y - attribute \src "ls180.v:4789.8-4789.42" - case 1'1 - assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4796.4-4802.7" - switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:4796.8-4796.39" - case 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4797$697_Y - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4799.5-4801.8" - switch $eq$ls180.v:4799$698_Y - attribute \src "ls180.v:4799.9-4799.42" - case 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_datar_source_valid[0:0] 1'1 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001 - assign $0\main_sdphy_datar_source_last[0:0] 1'1 - attribute \src "ls180.v:4808.4-4810.7" - switch $and$ls180.v:4808$699_Y - attribute \src "ls180.v:4808.8-4808.71" - case 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4815.4-4826.7" - switch $and$ls180.v:4815$700_Y - attribute \src "ls180.v:4815.8-4815.71" - case 1'1 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4817.5-4825.8" - switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:4817.9-4817.40" - case 1'1 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'1 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'001 - case - end - case - end - end - sync always - update \main_sdphy_datar_pads_out_payload_clk $0\main_sdphy_datar_pads_out_payload_clk[0:0] - update \main_sdphy_datar_sink_ready $0\main_sdphy_datar_sink_ready[0:0] - update \main_sdphy_datar_source_valid $0\main_sdphy_datar_source_valid[0:0] - update \main_sdphy_datar_source_last $0\main_sdphy_datar_source_last[0:0] - update \main_sdphy_datar_source_payload_data $0\main_sdphy_datar_source_payload_data[7:0] - update \main_sdphy_datar_source_payload_status $0\main_sdphy_datar_source_payload_status[2:0] - update \main_sdphy_datar_stop $0\main_sdphy_datar_stop[0:0] - update \main_sdphy_datar_datar_source_source_ready0 $0\main_sdphy_datar_datar_source_source_ready0[0:0] - update \builder_sdphy_sdphydatar_next_state $0\builder_sdphy_sdphydatar_next_state[2:0] - update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - end - attribute \src "ls180.v:473.5-473.51" - process $proc$ls180.v:473$2940 - assign { } { } - assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] - end - attribute \src "ls180.v:474.5-474.51" - process $proc$ls180.v:474$2941 - assign { } { } - assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] - end - attribute \src "ls180.v:476.5-476.47" - process $proc$ls180.v:476$2942 - assign { } { } - assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] - end - attribute \src "ls180.v:477.5-477.45" - process $proc$ls180.v:477$2943 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] - end - attribute \src "ls180.v:478.5-478.45" - process $proc$ls180.v:478$2944 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] - end - attribute \src "ls180.v:479.12-479.57" - process $proc$ls180.v:479$2945 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] - end - attribute \src "ls180.v:481.5-481.51" - process $proc$ls180.v:481$2946 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:482.5-482.51" - process $proc$ls180.v:482$2947 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:483.5-483.50" - process $proc$ls180.v:483$2948 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] - end - attribute \src "ls180.v:484.5-484.54" - process $proc$ls180.v:484$2949 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:485.5-485.55" - process $proc$ls180.v:485$2950 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:486.5-486.56" - process $proc$ls180.v:486$2951 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:487.5-487.50" - process $proc$ls180.v:487$2952 - assign { } { } - assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] - end - attribute \src "ls180.v:4887.1-4894.4" - process $proc$ls180.v:4887$822 - assign { } { } - assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 - attribute \src "ls180.v:4889.2-4893.5" - switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:4889.6-4889.38" - case 1'1 - assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:4891.6-4891.10" - case - assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0 - end - sync always - update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] - end - attribute \src "ls180.v:490.5-490.67" - process $proc$ls180.v:490$2953 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:4909.1-4916.4" - process $proc$ls180.v:4909$845 - assign { } { } - assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4911.2-4915.5" - switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:4911.6-4911.44" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:4913.6-4913.10" - case - assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 - end - sync always - update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] - end - attribute \src "ls180.v:491.5-491.66" - process $proc$ls180.v:491$2954 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:4919.1-4926.4" - process $proc$ls180.v:4919$856 - assign { } { } - assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4921.2-4925.5" - switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:4921.6-4921.44" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:4923.6-4923.10" - case - assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 - end - sync always - update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] - end - attribute \src "ls180.v:4929.1-4936.4" - process $proc$ls180.v:4929$867 - assign { } { } - assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4931.2-4935.5" - switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:4931.6-4931.44" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:4933.6-4933.10" - case - assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 - end - sync always - update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0] - end - attribute \src "ls180.v:4939.1-4946.4" - process $proc$ls180.v:4939$878 - assign { } { } - assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4941.2-4945.5" - switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:4941.6-4941.44" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:4943.6-4943.10" - case - assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 - end - sync always - update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0] - end - attribute \src "ls180.v:4947.1-5026.4" - process $proc$ls180.v:4947$879 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 - assign { } { } - assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 - assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:4964.2-5025.9" - switch \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1 - attribute \src "ls180.v:4968.4-4970.7" - switch $eq$ls180.v:4968$880_Y - attribute \src "ls180.v:4968.8-4968.48" - case 1'1 - assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1 - case - end - attribute \src "ls180.v:4971.4-4996.11" - switch \main_sdcore_crc16_inserter_cnt - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [15] \main_sdcore_crc16_inserter_crctmp2 [15] \main_sdcore_crc16_inserter_crctmp1 [15] \main_sdcore_crc16_inserter_crctmp0 [15] \main_sdcore_crc16_inserter_crctmp3 [14] \main_sdcore_crc16_inserter_crctmp2 [14] \main_sdcore_crc16_inserter_crctmp1 [14] \main_sdcore_crc16_inserter_crctmp0 [14] } - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [13] \main_sdcore_crc16_inserter_crctmp2 [13] \main_sdcore_crc16_inserter_crctmp1 [13] \main_sdcore_crc16_inserter_crctmp0 [13] \main_sdcore_crc16_inserter_crctmp3 [12] \main_sdcore_crc16_inserter_crctmp2 [12] \main_sdcore_crc16_inserter_crctmp1 [12] \main_sdcore_crc16_inserter_crctmp0 [12] } - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [11] \main_sdcore_crc16_inserter_crctmp2 [11] \main_sdcore_crc16_inserter_crctmp1 [11] \main_sdcore_crc16_inserter_crctmp0 [11] \main_sdcore_crc16_inserter_crctmp3 [10] \main_sdcore_crc16_inserter_crctmp2 [10] \main_sdcore_crc16_inserter_crctmp1 [10] \main_sdcore_crc16_inserter_crctmp0 [10] } - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [9] \main_sdcore_crc16_inserter_crctmp2 [9] \main_sdcore_crc16_inserter_crctmp1 [9] \main_sdcore_crc16_inserter_crctmp0 [9] \main_sdcore_crc16_inserter_crctmp3 [8] \main_sdcore_crc16_inserter_crctmp2 [8] \main_sdcore_crc16_inserter_crctmp1 [8] \main_sdcore_crc16_inserter_crctmp0 [8] } - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [7] \main_sdcore_crc16_inserter_crctmp2 [7] \main_sdcore_crc16_inserter_crctmp1 [7] \main_sdcore_crc16_inserter_crctmp0 [7] \main_sdcore_crc16_inserter_crctmp3 [6] \main_sdcore_crc16_inserter_crctmp2 [6] \main_sdcore_crc16_inserter_crctmp1 [6] \main_sdcore_crc16_inserter_crctmp0 [6] } - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [5] \main_sdcore_crc16_inserter_crctmp2 [5] \main_sdcore_crc16_inserter_crctmp1 [5] \main_sdcore_crc16_inserter_crctmp0 [5] \main_sdcore_crc16_inserter_crctmp3 [4] \main_sdcore_crc16_inserter_crctmp2 [4] \main_sdcore_crc16_inserter_crctmp1 [4] \main_sdcore_crc16_inserter_crctmp0 [4] } - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [3] \main_sdcore_crc16_inserter_crctmp2 [3] \main_sdcore_crc16_inserter_crctmp1 [3] \main_sdcore_crc16_inserter_crctmp0 [3] \main_sdcore_crc16_inserter_crctmp3 [2] \main_sdcore_crc16_inserter_crctmp2 [2] \main_sdcore_crc16_inserter_crctmp1 [2] \main_sdcore_crc16_inserter_crctmp0 [2] } - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] } - case - end - attribute \src "ls180.v:4997.4-5004.7" - switch \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:4997.8-4997.47" - case 1'1 - attribute \src "ls180.v:4998.5-5003.8" - switch $eq$ls180.v:4998$881_Y - attribute \src "ls180.v:4998.9-4998.49" - case 1'1 - assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 - attribute \src "ls180.v:5000.9-5000.13" - case - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5001$882_Y - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] \main_sdcore_crc16_inserter_sink_payload_data - assign $0\main_sdcore_crc16_inserter_source_valid[0:0] \main_sdcore_crc16_inserter_sink_valid - assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] \main_sdcore_crc16_inserter_source_ready - assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] \main_sdcore_crc16_inserter_crc0_crc - assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] \main_sdcore_crc16_inserter_crc1_crc - assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] \main_sdcore_crc16_inserter_crc2_crc - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5019.4-5023.7" - switch $and$ls180.v:5019$884_Y - attribute \src "ls180.v:5019.8-5019.128" - case 1'1 - assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 - case - end - end - sync always - update \main_sdcore_crc16_inserter_sink_ready $0\main_sdcore_crc16_inserter_sink_ready[0:0] - update \main_sdcore_crc16_inserter_source_valid $0\main_sdcore_crc16_inserter_source_valid[0:0] - update \main_sdcore_crc16_inserter_source_last $0\main_sdcore_crc16_inserter_source_last[0:0] - update \main_sdcore_crc16_inserter_source_payload_data $0\main_sdcore_crc16_inserter_source_payload_data[7:0] - update \builder_sdcore_crcupstreaminserter_next_state $0\builder_sdcore_crcupstreaminserter_next_state[0:0] - update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - end - attribute \src "ls180.v:5027.1-5032.4" - process $proc$ls180.v:5027$885 - assign { } { } - assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0 - attribute \src "ls180.v:5029.2-5031.5" - switch $and$ls180.v:5029$892_Y - attribute \src "ls180.v:5029.6-5029.301" - case 1'1 - assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1 - case - end - sync always - update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0] - end - attribute \src "ls180.v:5035.1-5042.4" - process $proc$ls180.v:5035$894 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - attribute \src "ls180.v:5037.2-5041.5" - switch $eq$ls180.v:5037$895_Y - attribute \src "ls180.v:5037.6-5037.45" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1 - attribute \src "ls180.v:5039.6-5039.10" - case - assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - end - sync always - update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0] - end - attribute \src "ls180.v:5045.1-5052.4" - process $proc$ls180.v:5045$897 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - attribute \src "ls180.v:5047.2-5051.5" - switch $eq$ls180.v:5047$898_Y - attribute \src "ls180.v:5047.6-5047.45" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1 - attribute \src "ls180.v:5049.6-5049.10" - case - assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - end - sync always - update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0] - end - attribute \src "ls180.v:5055.1-5062.4" - process $proc$ls180.v:5055$900 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - attribute \src "ls180.v:5057.2-5061.5" - switch $eq$ls180.v:5057$901_Y - attribute \src "ls180.v:5057.6-5057.45" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1 - attribute \src "ls180.v:5059.6-5059.10" - case - assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - end - sync always - update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0] - end - attribute \src "ls180.v:506.11-506.68" - process $proc$ls180.v:506$2955 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:5065.1-5072.4" - process $proc$ls180.v:5065$903 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - attribute \src "ls180.v:5067.2-5071.5" - switch $eq$ls180.v:5067$904_Y - attribute \src "ls180.v:5067.6-5067.45" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1 - attribute \src "ls180.v:5069.6-5069.10" - case - assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - end - sync always - update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0] - end - attribute \src "ls180.v:507.5-507.64" - process $proc$ls180.v:507$2956 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:5074.1-5079.4" - process $proc$ls180.v:5074$905 - assign { } { } - assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0 - attribute \src "ls180.v:5076.2-5078.5" - switch $and$ls180.v:5076$907_Y - attribute \src "ls180.v:5076.6-5076.85" - case 1'1 - assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1 - case - end - sync always - update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0] - end - attribute \src "ls180.v:508.11-508.70" - process $proc$ls180.v:508$2957 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:5080.1-5087.4" - process $proc$ls180.v:5080$908 - assign { } { } - assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 - attribute \src "ls180.v:5082.2-5086.5" - switch $lt$ls180.v:5082$909_Y - attribute \src "ls180.v:5082.6-5082.44" - case 1'1 - assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1 - attribute \src "ls180.v:5084.6-5084.10" - case - assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready - end - sync always - update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0] - end - attribute \src "ls180.v:509.11-509.70" - process $proc$ls180.v:509$2958 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:5091.1-5098.4" - process $proc$ls180.v:5091$920 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5093.2-5097.5" - switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:5093.6-5093.43" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:5095.6-5095.10" - case - assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 - end - sync always - update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0] - end - attribute \src "ls180.v:510.11-510.73" - process $proc$ls180.v:510$2959 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:5101.1-5108.4" - process $proc$ls180.v:5101$931 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5103.2-5107.5" - switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:5103.6-5103.43" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:5105.6-5105.10" - case - assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 - end - sync always - update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0] - end - attribute \src "ls180.v:5111.1-5118.4" - process $proc$ls180.v:5111$942 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5113.2-5117.5" - switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:5113.6-5113.43" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:5115.6-5115.10" - case - assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 - end - sync always - update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] - end - attribute \src "ls180.v:5121.1-5128.4" - process $proc$ls180.v:5121$953 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5123.2-5127.5" - switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:5123.6-5123.43" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:5125.6-5125.10" - case - assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 - end - sync always - update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] - end - attribute \src "ls180.v:5129.1-5319.4" - process $proc$ls180.v:5129$954 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 - assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 - assign $0\main_sdphy_datar_sink_valid[0:0] 1'0 - assign $0\main_sdphy_dataw_sink_valid[0:0] 1'0 - assign $0\main_sdphy_dataw_sink_first[0:0] 1'0 - assign $0\main_sdphy_datar_sink_last[0:0] 1'0 - assign $0\main_sdphy_dataw_sink_last[0:0] 1'0 - assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 - assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 - assign $0\main_sdphy_datar_source_ready[0:0] 1'0 - assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 - assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 - assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state - attribute \src "ls180.v:5170.2-5318.9" - switch \builder_sdcore_fsm_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1 - attribute \src "ls180.v:5173.4-5193.11" - switch \main_sdcore_cmd_count - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { 2'01 \main_sdcore_cmd_command_storage [13:8] } - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [31:24] - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [23:16] - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [15:8] - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [7:0] - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 } - assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5191$955_Y - case - end - attribute \src "ls180.v:5194.4-5206.7" - switch $and$ls180.v:5194$956_Y - attribute \src "ls180.v:5194.8-5194.65" - case 1'1 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5195$957_Y - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 - attribute \src "ls180.v:5197.5-5205.8" - switch $eq$ls180.v:5197$958_Y - attribute \src "ls180.v:5197.9-5197.40" - case 1'1 - attribute \src "ls180.v:5198.6-5204.9" - switch $eq$ls180.v:5198$959_Y - attribute \src "ls180.v:5198.10-5198.40" - case 1'1 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5202.10-5202.14" - case - assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1 - assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5210$960_Y - assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1 - attribute \src "ls180.v:5211.4-5215.7" - switch $eq$ls180.v:5211$961_Y - attribute \src "ls180.v:5211.8-5211.38" - case 1'1 - assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001 - attribute \src "ls180.v:5213.8-5213.12" - case - assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110 - end - attribute \src "ls180.v:5217.4-5238.7" - switch \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:5217.8-5217.36" - case 1'1 - attribute \src "ls180.v:5218.5-5237.8" - switch $eq$ls180.v:5218$962_Y - attribute \src "ls180.v:5218.9-5218.56" - case 1'1 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5222.9-5222.13" - case - attribute \src "ls180.v:5223.6-5236.9" - switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:5223.10-5223.37" - case 1'1 - attribute \src "ls180.v:5224.7-5232.10" - switch $eq$ls180.v:5224$963_Y - attribute \src "ls180.v:5224.11-5224.42" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:5226.11-5226.15" - case - attribute \src "ls180.v:5227.8-5231.11" - switch $eq$ls180.v:5227$964_Y - attribute \src "ls180.v:5227.12-5227.43" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 - attribute \src "ls180.v:5229.12-5229.16" - case - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - end - end - attribute \src "ls180.v:5233.10-5233.14" - case - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data } - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_dataw_sink_valid[0:0] \main_sdcore_crc16_inserter_source_valid - assign $0\main_sdcore_crc16_inserter_source_ready[0:0] \main_sdphy_dataw_sink_ready - assign $0\main_sdphy_dataw_sink_first[0:0] \main_sdcore_crc16_inserter_source_first - assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last - assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data - assign $0\main_sdphy_datar_source_ready[0:0] 1'1 - attribute \src "ls180.v:5246.4-5252.7" - switch $and$ls180.v:5246$966_Y - attribute \src "ls180.v:5246.8-5246.98" - case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5247$967_Y - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5249.5-5251.8" - switch $eq$ls180.v:5249$969_Y - attribute \src "ls180.v:5249.9-5249.77" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - case - end - case - end - attribute \src "ls180.v:5254.4-5259.7" - switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5254.8-5254.37" - case 1'1 - attribute \src "ls180.v:5255.5-5258.8" - switch $ne$ls180.v:5255$970_Y - attribute \src "ls180.v:5255.9-5255.57" - case 1'1 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_datar_sink_valid[0:0] 1'1 - assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage - assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5264$972_Y - attribute \src "ls180.v:5265.4-5291.7" - switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5265.8-5265.37" - case 1'1 - attribute \src "ls180.v:5266.5-5290.8" - switch $eq$ls180.v:5266$973_Y - attribute \src "ls180.v:5266.9-5266.57" - case 1'1 - assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid - assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready - assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first - assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last - assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:5272.6-5280.9" - switch $and$ls180.v:5272$974_Y - attribute \src "ls180.v:5272.10-5272.72" - case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5273$975_Y - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5275.7-5279.10" - switch $eq$ls180.v:5275$977_Y - attribute \src "ls180.v:5275.11-5275.79" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5277.11-5277.15" - case - assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 - end - case - end - attribute \src "ls180.v:5281.9-5281.13" - case - attribute \src "ls180.v:5282.6-5289.9" - switch $eq$ls180.v:5282$978_Y - attribute \src "ls180.v:5282.10-5282.58" - case 1'1 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - assign $0\main_sdphy_datar_source_ready[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - case - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'1 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5302.4-5316.7" - switch \main_sdcore_cmd_send_re - attribute \src "ls180.v:5302.8-5302.31" - case 1'1 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'1 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'001 - case - end - end - sync always - update \main_sdphy_cmdw_sink_valid $0\main_sdphy_cmdw_sink_valid[0:0] - update \main_sdphy_cmdw_sink_last $0\main_sdphy_cmdw_sink_last[0:0] - update \main_sdphy_cmdw_sink_payload_data $0\main_sdphy_cmdw_sink_payload_data[7:0] - update \main_sdphy_cmdr_sink_valid $0\main_sdphy_cmdr_sink_valid[0:0] - update \main_sdphy_cmdr_sink_last $0\main_sdphy_cmdr_sink_last[0:0] - update \main_sdphy_cmdr_sink_payload_length $0\main_sdphy_cmdr_sink_payload_length[7:0] - update \main_sdphy_cmdr_source_ready $0\main_sdphy_cmdr_source_ready[0:0] - update \main_sdphy_dataw_sink_valid $0\main_sdphy_dataw_sink_valid[0:0] - update \main_sdphy_dataw_sink_first $0\main_sdphy_dataw_sink_first[0:0] - update \main_sdphy_dataw_sink_last $0\main_sdphy_dataw_sink_last[0:0] - update \main_sdphy_dataw_sink_payload_data $0\main_sdphy_dataw_sink_payload_data[7:0] - update \main_sdphy_datar_sink_valid $0\main_sdphy_datar_sink_valid[0:0] - update \main_sdphy_datar_sink_last $0\main_sdphy_datar_sink_last[0:0] - update \main_sdphy_datar_sink_payload_block_length $0\main_sdphy_datar_sink_payload_block_length[9:0] - update \main_sdphy_datar_source_ready $0\main_sdphy_datar_source_ready[0:0] - update \main_sdcore_crc16_inserter_source_ready $0\main_sdcore_crc16_inserter_source_ready[0:0] - update \main_sdcore_crc16_checker_sink_valid $0\main_sdcore_crc16_checker_sink_valid[0:0] - update \main_sdcore_crc16_checker_sink_first $0\main_sdcore_crc16_checker_sink_first[0:0] - update \main_sdcore_crc16_checker_sink_last $0\main_sdcore_crc16_checker_sink_last[0:0] - update \main_sdcore_crc16_checker_sink_payload_data $0\main_sdcore_crc16_checker_sink_payload_data[7:0] - update \builder_sdcore_fsm_next_state $0\builder_sdcore_fsm_next_state[2:0] - update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - update \main_sdcore_data_done_sdcore_fsm_next_value1 $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - update \main_sdcore_data_count_sdcore_fsm_next_value3 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - update \main_sdcore_data_error_sdcore_fsm_next_value6 $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - end - attribute \src "ls180.v:531.5-531.59" - process $proc$ls180.v:531$2960 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:533.5-533.59" - process $proc$ls180.v:533$2961 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:534.5-534.58" - process $proc$ls180.v:534$2962 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:5347.1-5354.4" - process $proc$ls180.v:5347$979 - assign { } { } - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5349.2-5353.5" - switch \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:5349.6-5349.35" - case 1'1 - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5350$980_Y - attribute \src "ls180.v:5351.6-5351.10" - case - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce - end - sync always - update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:535.5-535.64" - process $proc$ls180.v:535$2963 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:536.12-536.74" - process $proc$ls180.v:536$2964 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:537.12-537.47" - process $proc$ls180.v:537$2965 - assign { } { } - assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] - end - attribute \src "ls180.v:538.5-538.46" - process $proc$ls180.v:538$2966 - assign { } { } - assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] - end - attribute \src "ls180.v:5380.1-5419.4" - process $proc$ls180.v:5380$990 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 - assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 - assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0 - assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 - assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state - attribute \src "ls180.v:5390.2-5418.9" - switch \builder_sdblock2memdma_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid - assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data - assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5394$991_Y - assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:5396.4-5407.7" - switch $and$ls180.v:5396$992_Y - attribute \src "ls180.v:5396.8-5396.103" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5397$993_Y - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5399.5-5406.8" - switch $eq$ls180.v:5399$995_Y - attribute \src "ls180.v:5399.9-5399.106" - case 1'1 - attribute \src "ls180.v:5400.6-5405.9" - switch \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:5400.10-5400.57" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5403.10-5403.14" - case - assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'1 - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - assign $0\builder_sdblock2memdma_next_state[1:0] 2'01 - end - sync always - update \main_sdblock2mem_sink_sink_valid1 $0\main_sdblock2mem_sink_sink_valid1[0:0] - update \main_sdblock2mem_sink_sink_payload_address $0\main_sdblock2mem_sink_sink_payload_address[31:0] - update \main_sdblock2mem_sink_sink_payload_data1 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] - update \main_sdblock2mem_wishbonedmawriter_sink_ready $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - update \main_sdblock2mem_wishbonedmawriter_status $0\main_sdblock2mem_wishbonedmawriter_status[0:0] - update \builder_sdblock2memdma_next_state $0\builder_sdblock2memdma_next_state[1:0] - update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - end - attribute \src "ls180.v:540.5-540.44" - process $proc$ls180.v:540$2967 - assign { } { } - assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] - end - attribute \src "ls180.v:541.5-541.45" - process $proc$ls180.v:541$2968 - assign { } { } - assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] - end - attribute \src "ls180.v:542.5-542.54" - process $proc$ls180.v:542$2969 - assign { } { } - assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:5439.1-5476.4" - process $proc$ls180.v:5439$997 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_interface1_bus_stb[0:0] 1'0 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 - assign $0\main_interface1_bus_we[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_payload_data[31:0] 0 - assign $0\main_interface1_bus_adr[31:0] 0 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 - assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0 - assign { } { } - assign $0\main_interface1_bus_sel[3:0] 4'0000 - assign $0\main_interface1_bus_cyc[0:0] 1'0 - assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:5453.2-5475.9" - switch \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1 - assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last - assign $0\main_sdmem2block_dma_source_payload_data[31:0] \main_sdmem2block_dma_data - attribute \src "ls180.v:5458.4-5461.7" - switch \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:5458.8-5458.41" - case 1'1 - assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1 - assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_interface1_bus_stb[0:0] \main_sdmem2block_dma_sink_valid - assign $0\main_interface1_bus_cyc[0:0] \main_sdmem2block_dma_sink_valid - assign $0\main_interface1_bus_we[0:0] 1'0 - assign $0\main_interface1_bus_sel[3:0] 4'1111 - assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:5469.4-5473.7" - switch $and$ls180.v:5469$998_Y - attribute \src "ls180.v:5469.8-5469.59" - case 1'1 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] } - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 - assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'1 - case - end - end - sync always - update \main_interface1_bus_adr $0\main_interface1_bus_adr[31:0] - update \main_interface1_bus_sel $0\main_interface1_bus_sel[3:0] - update \main_interface1_bus_cyc $0\main_interface1_bus_cyc[0:0] - update \main_interface1_bus_stb $0\main_interface1_bus_stb[0:0] - update \main_interface1_bus_we $0\main_interface1_bus_we[0:0] - update \main_sdmem2block_dma_sink_ready $0\main_sdmem2block_dma_sink_ready[0:0] - update \main_sdmem2block_dma_source_valid $0\main_sdmem2block_dma_source_valid[0:0] - update \main_sdmem2block_dma_source_last $0\main_sdmem2block_dma_source_last[0:0] - update \main_sdmem2block_dma_source_payload_data $0\main_sdmem2block_dma_source_payload_data[31:0] - update \builder_sdmem2blockdma_fsm_next_state $0\builder_sdmem2blockdma_fsm_next_state[0:0] - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:544.32-544.76" - process $proc$ls180.v:544$2970 - assign { } { } - assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] - end - attribute \src "ls180.v:545.11-545.55" - process $proc$ls180.v:545$2971 - assign { } { } - assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] - end - attribute \src "ls180.v:547.32-547.75" - process $proc$ls180.v:547$2972 - assign { } { } - assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:5477.1-5513.4" - process $proc$ls180.v:5477$999 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 - assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 - assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 - assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 - assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 - assign { } { } - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:5486.2-5512.9" - switch \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1 - assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5489$1001_Y - assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5490$1002_Y - attribute \src "ls180.v:5491.4-5502.7" - switch \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:5491.8-5491.39" - case 1'1 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5492$1003_Y - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5494.5-5501.8" - switch \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:5494.9-5494.39" - case 1'1 - attribute \src "ls180.v:5495.6-5500.9" - switch \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:5495.10-5495.43" - case 1'1 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5498.10-5498.14" - case - assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdmem2block_dma_done_status[0:0] 1'1 - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'01 - end - sync always - update \main_sdmem2block_dma_sink_valid $0\main_sdmem2block_dma_sink_valid[0:0] - update \main_sdmem2block_dma_sink_last $0\main_sdmem2block_dma_sink_last[0:0] - update \main_sdmem2block_dma_sink_payload_address $0\main_sdmem2block_dma_sink_payload_address[31:0] - update \main_sdmem2block_dma_done_status $0\main_sdmem2block_dma_done_status[0:0] - update \builder_sdmem2blockdma_resetinserter_next_state $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] - update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - end - attribute \src "ls180.v:549.32-549.76" - process $proc$ls180.v:549$2973 - assign { } { } - assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:55.5-55.42" - process $proc$ls180.v:55$2775 - assign { } { } - assign $1\main_libresocsim_reset_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] - end - attribute \src "ls180.v:5525.1-5541.4" - process $proc$ls180.v:5525$1009 - assign { } { } - assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 - attribute \src "ls180.v:5527.2-5540.9" - switch \main_sdmem2block_converter_mux - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [31:24] - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [23:16] - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [15:8] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [7:0] - end - sync always - update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:555.5-555.51" - process $proc$ls180.v:555$2974 - assign { } { } - assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] - end - attribute \src "ls180.v:5555.1-5562.4" - process $proc$ls180.v:5555$1010 - assign { } { } - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5557.2-5561.5" - switch \main_sdmem2block_fifo_replace - attribute \src "ls180.v:5557.6-5557.35" - case 1'1 - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5558$1011_Y - attribute \src "ls180.v:5559.6-5559.10" - case - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce - end - sync always - update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:556.5-556.51" - process $proc$ls180.v:556$2975 - assign { } { } - assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] - end - attribute \src "ls180.v:558.5-558.47" - process $proc$ls180.v:558$2976 - assign { } { } - assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] - end - attribute \src "ls180.v:5580.1-5628.4" - process $proc$ls180.v:5580$1021 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\libresocsim_clk_enable[0:0] 1'0 - assign $0\libresocsim_count_spimaster1_next_value[2:0] 3'000 - assign $0\libresocsim_cs_enable[0:0] 1'0 - assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'0 - assign $0\libresocsim_mosi_latch[0:0] 1'0 - assign $0\libresocsim_done0[0:0] 1'0 - assign $0\libresocsim_miso_latch[0:0] 1'0 - assign $0\libresocsim_irq[0:0] 1'0 - assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state - attribute \src "ls180.v:5591.2-5627.9" - switch \builder_spimaster1_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\libresocsim_count_spimaster1_next_value[2:0] 3'000 - assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5595.4-5598.7" - switch \libresocsim_clk_fall - attribute \src "ls180.v:5595.8-5595.28" - case 1'1 - assign $0\libresocsim_cs_enable[0:0] 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'10 - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\libresocsim_clk_enable[0:0] 1'1 - assign $0\libresocsim_cs_enable[0:0] 1'1 - attribute \src "ls180.v:5603.4-5609.7" - switch \libresocsim_clk_fall - attribute \src "ls180.v:5603.8-5603.28" - case 1'1 - assign $0\libresocsim_count_spimaster1_next_value[2:0] $add$ls180.v:5604$1022_Y - assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5606.5-5608.8" - switch $eq$ls180.v:5606$1024_Y - attribute \src "ls180.v:5606.9-5606.60" - case 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'11 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\libresocsim_cs_enable[0:0] 1'1 - attribute \src "ls180.v:5613.4-5617.7" - switch \libresocsim_clk_rise - attribute \src "ls180.v:5613.8-5613.28" - case 1'1 - assign $0\libresocsim_miso_latch[0:0] 1'1 - assign $0\libresocsim_irq[0:0] 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'00 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\libresocsim_done0[0:0] 1'1 - attribute \src "ls180.v:5621.4-5625.7" - switch \libresocsim_start0 - attribute \src "ls180.v:5621.8-5621.26" - case 1'1 - assign $0\libresocsim_done0[0:0] 1'0 - assign $0\libresocsim_mosi_latch[0:0] 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'01 - case - end - end - sync always - update \libresocsim_done0 $0\libresocsim_done0[0:0] - update \libresocsim_irq $0\libresocsim_irq[0:0] - update \libresocsim_clk_enable $0\libresocsim_clk_enable[0:0] - update \libresocsim_cs_enable $0\libresocsim_cs_enable[0:0] - update \libresocsim_mosi_latch $0\libresocsim_mosi_latch[0:0] - update \libresocsim_miso_latch $0\libresocsim_miso_latch[0:0] - update \builder_spimaster1_next_state $0\builder_spimaster1_next_state[1:0] - update \libresocsim_count_spimaster1_next_value $0\libresocsim_count_spimaster1_next_value[2:0] - update \libresocsim_count_spimaster1_next_value_ce $0\libresocsim_count_spimaster1_next_value_ce[0:0] - end - attribute \src "ls180.v:559.5-559.45" - process $proc$ls180.v:559$2977 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] - end - attribute \src "ls180.v:56.5-56.37" - process $proc$ls180.v:56$2776 - assign { } { } - assign $1\main_libresocsim_reset_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] - end - attribute \src "ls180.v:560.5-560.45" - process $proc$ls180.v:560$2978 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] - end - attribute \src "ls180.v:561.12-561.57" - process $proc$ls180.v:561$2979 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] - end - attribute \src "ls180.v:5629.1-5665.4" - process $proc$ls180.v:5629$1025 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 - assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 - assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 - assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 - assign { } { } - assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 - assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 - assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 - assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 - assign $0\builder_next_state[1:0] \builder_state - attribute \src "ls180.v:5640.2-5664.9" - switch \builder_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 - assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 - assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 - assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 - assign $0\builder_next_state[1:0] 2'10 - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_libresocsim_wishbone_ack[0:0] 1'1 - assign $0\builder_libresocsim_wishbone_dat_r[31:0] { 24'000000000000000000000000 \builder_libresocsim_dat_r } - assign $0\builder_next_state[1:0] 2'00 - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] - assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5656.4-5662.7" - switch $and$ls180.v:5656$1026_Y - attribute \src "ls180.v:5656.8-5656.77" - case 1'1 - assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] - assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 - assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5659$1028_Y - assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 - assign $0\builder_next_state[1:0] 2'01 - case - end - end - sync always - update \builder_libresocsim_wishbone_dat_r $0\builder_libresocsim_wishbone_dat_r[31:0] - update \builder_libresocsim_wishbone_ack $0\builder_libresocsim_wishbone_ack[0:0] - update \builder_next_state $0\builder_next_state[1:0] - update \builder_libresocsim_dat_w_next_value0 $0\builder_libresocsim_dat_w_next_value0[7:0] - update \builder_libresocsim_dat_w_next_value_ce0 $0\builder_libresocsim_dat_w_next_value_ce0[0:0] - update \builder_libresocsim_adr_next_value1 $0\builder_libresocsim_adr_next_value1[13:0] - update \builder_libresocsim_adr_next_value_ce1 $0\builder_libresocsim_adr_next_value_ce1[0:0] - update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] - update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] - end - attribute \src "ls180.v:563.5-563.51" - process $proc$ls180.v:563$2980 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:564.5-564.51" - process $proc$ls180.v:564$2981 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:565.5-565.50" - process $proc$ls180.v:565$2982 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] - end - attribute \src "ls180.v:566.5-566.54" - process $proc$ls180.v:566$2983 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:567.5-567.55" - process $proc$ls180.v:567$2984 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:568.5-568.56" - process $proc$ls180.v:568$2985 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:569.5-569.50" - process $proc$ls180.v:569$2986 - assign { } { } - assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] - end - attribute \src "ls180.v:5690.1-5697.4" - process $proc$ls180.v:5690$1049 - assign { } { } - assign { } { } - assign $0\builder_slave_sel[4:0] [0] $eq$ls180.v:5692$1050_Y - assign $0\builder_slave_sel[4:0] [1] $eq$ls180.v:5693$1051_Y - assign $0\builder_slave_sel[4:0] [2] $eq$ls180.v:5694$1052_Y - assign $0\builder_slave_sel[4:0] [3] $eq$ls180.v:5695$1053_Y - assign $0\builder_slave_sel[4:0] [4] $eq$ls180.v:5696$1054_Y - sync always - update \builder_slave_sel $0\builder_slave_sel[4:0] - end - attribute \src "ls180.v:57.12-57.60" - process $proc$ls180.v:57$2777 - assign { } { } - assign $1\main_libresocsim_scratch_storage[31:0] 305419896 - sync always - sync init - update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] - end - attribute \src "ls180.v:572.5-572.67" - process $proc$ls180.v:572$2987 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:573.5-573.66" - process $proc$ls180.v:573$2988 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:5740.1-5751.4" - process $proc$ls180.v:5740$1067 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\builder_error[0:0] 1'0 - assign $0\builder_shared_ack[0:0] $or$ls180.v:5744$1071_Y - assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5745$1080_Y - attribute \src "ls180.v:5746.2-5750.5" - switch \builder_done - attribute \src "ls180.v:5746.6-5746.18" - case 1'1 - assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 - assign $0\builder_shared_ack[0:0] 1'1 - assign $0\builder_error[0:0] 1'1 - case - end - sync always - update \builder_shared_dat_r $0\builder_shared_dat_r[31:0] - update \builder_shared_ack $0\builder_shared_ack[0:0] - update \builder_error $0\builder_error[0:0] - end - attribute \src "ls180.v:58.5-58.39" - process $proc$ls180.v:58$2778 - assign { } { } - assign $1\main_libresocsim_scratch_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] - end - attribute \src "ls180.v:588.11-588.68" - process $proc$ls180.v:588$2989 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:589.5-589.64" - process $proc$ls180.v:589$2990 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:590.11-590.70" - process $proc$ls180.v:590$2991 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:591.11-591.70" - process $proc$ls180.v:591$2992 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:592.11-592.73" - process $proc$ls180.v:592$2993 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:613.5-613.59" - process $proc$ls180.v:613$2994 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:615.5-615.59" - process $proc$ls180.v:615$2995 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:616.5-616.58" - process $proc$ls180.v:616$2996 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:617.5-617.64" - process $proc$ls180.v:617$2997 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:618.12-618.74" - process $proc$ls180.v:618$2998 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:619.12-619.47" - process $proc$ls180.v:619$2999 - assign { } { } - assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] - end - attribute \src "ls180.v:620.5-620.46" - process $proc$ls180.v:620$3000 - assign { } { } - assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] - end - attribute \src "ls180.v:622.5-622.44" - process $proc$ls180.v:622$3001 - assign { } { } - assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] - end - attribute \src "ls180.v:623.5-623.45" - process $proc$ls180.v:623$3002 - assign { } { } - assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] - end - attribute \src "ls180.v:624.5-624.54" - process $proc$ls180.v:624$3003 - assign { } { } - assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:626.32-626.76" - process $proc$ls180.v:626$3004 - assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] - end - attribute \src "ls180.v:6265.1-6270.4" - process $proc$ls180.v:6265$1954 - assign { } { } - assign $0\main_spi_master_start1[0:0] 1'0 - attribute \src "ls180.v:6267.2-6269.5" - switch \main_spi_master_control_re - attribute \src "ls180.v:6267.6-6267.32" - case 1'1 - assign $0\main_spi_master_start1[0:0] \main_spi_master_control_storage [0] - case - end - sync always - update \main_spi_master_start1 $0\main_spi_master_start1[0:0] - end - attribute \src "ls180.v:627.11-627.55" - process $proc$ls180.v:627$3005 - assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] - end - attribute \src "ls180.v:629.32-629.75" - process $proc$ls180.v:629$3006 - assign { } { } - assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:63.12-63.47" - process $proc$ls180.v:63$2779 - assign { } { } - assign $1\main_libresocsim_bus_errors[31:0] 0 - sync always - sync init - update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] - end - attribute \src "ls180.v:631.32-631.76" - process $proc$ls180.v:631$3007 - assign { } { } - assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:6311.1-6316.4" - process $proc$ls180.v:6311$2019 - assign { } { } - assign $0\libresocsim_start1[0:0] 1'0 - attribute \src "ls180.v:6313.2-6315.5" - switch \libresocsim_control_re - attribute \src "ls180.v:6313.6-6313.28" - case 1'1 - assign $0\libresocsim_start1[0:0] \libresocsim_control_storage [0] - case - end - sync always - update \libresocsim_start1 $0\libresocsim_start1[0:0] - end - attribute \src "ls180.v:637.5-637.51" - process $proc$ls180.v:637$3008 - assign { } { } - assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] - end - attribute \src "ls180.v:638.5-638.51" - process $proc$ls180.v:638$3009 - assign { } { } - assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] - end - attribute \src "ls180.v:640.5-640.47" - process $proc$ls180.v:640$3010 - assign { } { } - assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] - end - attribute \src "ls180.v:641.5-641.45" - process $proc$ls180.v:641$3011 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] - end - attribute \src "ls180.v:642.5-642.45" - process $proc$ls180.v:642$3012 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] - end - attribute \src "ls180.v:643.12-643.57" - process $proc$ls180.v:643$3013 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] - end - attribute \src "ls180.v:645.5-645.51" - process $proc$ls180.v:645$3014 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:646.5-646.51" - process $proc$ls180.v:646$3015 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:647.5-647.50" - process $proc$ls180.v:647$3016 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] - end - attribute \src "ls180.v:648.5-648.54" - process $proc$ls180.v:648$3017 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:649.5-649.55" - process $proc$ls180.v:649$3018 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:65.12-65.55" - process $proc$ls180.v:65$2780 - assign { } { } - assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 - sync always - sync init - update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] - end - attribute \src "ls180.v:650.5-650.56" - process $proc$ls180.v:650$3019 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:6500.1-6516.4" - process $proc$ls180.v:6500$2240 - assign { } { } - assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6502.2-6515.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [0] - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [1] - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [2] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [3] - end - sync always - update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] - end - attribute \src "ls180.v:651.5-651.50" - process $proc$ls180.v:651$3020 - assign { } { } - assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] - end - attribute \src "ls180.v:6517.1-6533.4" - process $proc$ls180.v:6517$2241 - assign { } { } - assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:6519.2-6532.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine3_cmd_payload_a - end - sync always - update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] - end - attribute \src "ls180.v:6534.1-6550.4" - process $proc$ls180.v:6534$2242 - assign { } { } - assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 - attribute \src "ls180.v:6536.2-6549.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine3_cmd_payload_ba - end - sync always - update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] - end - attribute \src "ls180.v:654.5-654.67" - process $proc$ls180.v:654$3021 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:655.5-655.66" - process $proc$ls180.v:655$3022 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:6551.1-6567.4" - process $proc$ls180.v:6551$2243 - assign { } { } - assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6553.2-6566.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_is_read - end - sync always - update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] - end - attribute \src "ls180.v:6568.1-6584.4" - process $proc$ls180.v:6568$2244 - assign { } { } - assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6570.2-6583.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_is_write - end - sync always - update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] - end - attribute \src "ls180.v:6585.1-6601.4" - process $proc$ls180.v:6585$2245 - assign { } { } - assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6587.2-6600.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd - end - sync always - update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] - end - attribute \src "ls180.v:6602.1-6618.4" - process $proc$ls180.v:6602$2246 - assign { } { } - assign $0\builder_comb_t_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6604.2-6617.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine3_cmd_payload_cas - end - sync always - update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] - end - attribute \src "ls180.v:6619.1-6635.4" - process $proc$ls180.v:6619$2247 - assign { } { } - assign $0\builder_comb_t_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:6621.2-6634.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine3_cmd_payload_ras - end - sync always - update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] - end - attribute \src "ls180.v:6636.1-6652.4" - process $proc$ls180.v:6636$2248 - assign { } { } - assign $0\builder_comb_t_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:6638.2-6651.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine3_cmd_payload_we - end - sync always - update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] - end - attribute \src "ls180.v:6653.1-6669.4" - process $proc$ls180.v:6653$2249 - assign { } { } - assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:6655.2-6668.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [0] - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [1] - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [2] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [3] - end - sync always - update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] - end - attribute \src "ls180.v:6670.1-6686.4" - process $proc$ls180.v:6670$2250 - assign { } { } - assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 - attribute \src "ls180.v:6672.2-6685.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine3_cmd_payload_a - end - sync always - update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] - end - attribute \src "ls180.v:6687.1-6703.4" - process $proc$ls180.v:6687$2251 - assign { } { } - assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 - attribute \src "ls180.v:6689.2-6702.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine3_cmd_payload_ba - end - sync always - update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] - end - attribute \src "ls180.v:670.11-670.68" - process $proc$ls180.v:670$3023 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:6704.1-6720.4" - process $proc$ls180.v:6704$2252 - assign { } { } - assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 - attribute \src "ls180.v:6706.2-6719.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine3_cmd_payload_is_read - end - sync always - update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] - end - attribute \src "ls180.v:671.5-671.64" - process $proc$ls180.v:671$3024 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:672.11-672.70" - process $proc$ls180.v:672$3025 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:6721.1-6737.4" - process $proc$ls180.v:6721$2253 - assign { } { } - assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 - attribute \src "ls180.v:6723.2-6736.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine3_cmd_payload_is_write - end - sync always - update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] - end - attribute \src "ls180.v:673.11-673.70" - process $proc$ls180.v:673$3026 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:6738.1-6754.4" - process $proc$ls180.v:6738$2254 - assign { } { } - assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 - attribute \src "ls180.v:6740.2-6753.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd - end - sync always - update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] - end - attribute \src "ls180.v:674.11-674.73" - process $proc$ls180.v:674$3027 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:6755.1-6771.4" - process $proc$ls180.v:6755$2255 - assign { } { } - assign $0\builder_comb_t_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6757.2-6770.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_cas - end - sync always - update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] - end - attribute \src "ls180.v:6772.1-6788.4" - process $proc$ls180.v:6772$2256 - assign { } { } - assign $0\builder_comb_t_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6774.2-6787.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_ras - end - sync always - update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] - end - attribute \src "ls180.v:6789.1-6805.4" - process $proc$ls180.v:6789$2257 - assign { } { } - assign $0\builder_comb_t_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6791.2-6804.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_we - end - sync always - update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] - end - attribute \src "ls180.v:6806.1-6813.4" - process $proc$ls180.v:6806$2258 - assign { } { } - assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6808.2-6812.9" - switch \builder_roundrobin0_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed12[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } - end - sync always - update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] - end - attribute \src "ls180.v:6814.1-6821.4" - process $proc$ls180.v:6814$2259 - assign { } { } - assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 - attribute \src "ls180.v:6816.2-6820.9" - switch \builder_roundrobin0_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed13[0:0] \main_port_cmd_payload_we - end - sync always - update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] - end - attribute \src "ls180.v:6822.1-6829.4" - process $proc$ls180.v:6822$2260 - assign { } { } - assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 - attribute \src "ls180.v:6824.2-6828.9" - switch \builder_roundrobin0_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6826$2273_Y - end - sync always - update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] - end - attribute \src "ls180.v:6830.1-6837.4" - process $proc$ls180.v:6830$2274 - assign { } { } - assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6832.2-6836.9" - switch \builder_roundrobin1_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed15[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } - end - sync always - update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] - end - attribute \src "ls180.v:6838.1-6845.4" - process $proc$ls180.v:6838$2275 - assign { } { } - assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 - attribute \src "ls180.v:6840.2-6844.9" - switch \builder_roundrobin1_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed16[0:0] \main_port_cmd_payload_we - end - sync always - update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] - end - attribute \src "ls180.v:6846.1-6853.4" - process $proc$ls180.v:6846$2276 - assign { } { } - assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 - attribute \src "ls180.v:6848.2-6852.9" - switch \builder_roundrobin1_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6850$2289_Y - end - sync always - update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] - end - attribute \src "ls180.v:6854.1-6861.4" - process $proc$ls180.v:6854$2290 - assign { } { } - assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6856.2-6860.9" - switch \builder_roundrobin2_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed18[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } - end - sync always - update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] - end - attribute \src "ls180.v:6862.1-6869.4" - process $proc$ls180.v:6862$2291 - assign { } { } - assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 - attribute \src "ls180.v:6864.2-6868.9" - switch \builder_roundrobin2_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed19[0:0] \main_port_cmd_payload_we - end - sync always - update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] - end - attribute \src "ls180.v:6870.1-6877.4" - process $proc$ls180.v:6870$2292 - assign { } { } - assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 - attribute \src "ls180.v:6872.2-6876.9" - switch \builder_roundrobin2_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6874$2305_Y - end - sync always - update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] - end - attribute \src "ls180.v:6878.1-6885.4" - process $proc$ls180.v:6878$2306 - assign { } { } - assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6880.2-6884.9" - switch \builder_roundrobin3_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed21[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } - end - sync always - update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] - end - attribute \src "ls180.v:6886.1-6893.4" - process $proc$ls180.v:6886$2307 - assign { } { } - assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 - attribute \src "ls180.v:6888.2-6892.9" - switch \builder_roundrobin3_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed22[0:0] \main_port_cmd_payload_we - end - sync always - update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] - end - attribute \src "ls180.v:6894.1-6901.4" - process $proc$ls180.v:6894$2308 - assign { } { } - assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 - attribute \src "ls180.v:6896.2-6900.9" - switch \builder_roundrobin3_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:6898$2321_Y - end - sync always - update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] - end - attribute \src "ls180.v:6902.1-6921.4" - process $proc$ls180.v:6902$2322 - assign { } { } - assign $0\builder_comb_rhs_array_muxed24[31:0] 0 - attribute \src "ls180.v:6904.2-6920.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface0_converted_interface_adr } - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface1_converted_interface_adr } - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface2_converted_interface_adr } - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface0_bus_adr - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface1_bus_adr - end - sync always - update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] - end - attribute \src "ls180.v:6922.1-6941.4" - process $proc$ls180.v:6922$2323 - assign { } { } - assign $0\builder_comb_rhs_array_muxed25[31:0] 0 - attribute \src "ls180.v:6924.2-6940.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface0_converted_interface_dat_w - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface1_converted_interface_dat_w - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface2_converted_interface_dat_w - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface0_bus_dat_w - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface1_bus_dat_w - end - sync always - update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[31:0] - end - attribute \src "ls180.v:6942.1-6961.4" - process $proc$ls180.v:6942$2324 - assign { } { } - assign $0\builder_comb_rhs_array_muxed26[3:0] 4'0000 - attribute \src "ls180.v:6944.2-6960.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface0_converted_interface_sel - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface1_converted_interface_sel - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface2_converted_interface_sel - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface0_bus_sel - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface1_bus_sel - end - sync always - update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[3:0] - end - attribute \src "ls180.v:695.5-695.59" - process $proc$ls180.v:695$3028 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:6962.1-6981.4" - process $proc$ls180.v:6962$2325 - assign { } { } - assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 - attribute \src "ls180.v:6964.2-6980.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface0_converted_interface_cyc - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface1_converted_interface_cyc - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface2_converted_interface_cyc - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface0_bus_cyc - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface1_bus_cyc - end - sync always - update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] - end - attribute \src "ls180.v:697.5-697.59" - process $proc$ls180.v:697$3029 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:698.5-698.58" - process $proc$ls180.v:698$3030 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:6982.1-7001.4" - process $proc$ls180.v:6982$2326 - assign { } { } - assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 - attribute \src "ls180.v:6984.2-7000.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface0_converted_interface_stb - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface1_converted_interface_stb - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface2_converted_interface_stb - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface0_bus_stb - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface1_bus_stb - end - sync always - update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] - end - attribute \src "ls180.v:699.5-699.64" - process $proc$ls180.v:699$3031 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:700.12-700.74" - process $proc$ls180.v:700$3032 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:7002.1-7021.4" - process $proc$ls180.v:7002$2327 - assign { } { } - assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 - attribute \src "ls180.v:7004.2-7020.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface0_converted_interface_we - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface1_converted_interface_we - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface2_converted_interface_we - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface0_bus_we - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface1_bus_we - end - sync always - update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] - end - attribute \src "ls180.v:701.12-701.47" - process $proc$ls180.v:701$3033 - assign { } { } - assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] - end - attribute \src "ls180.v:702.5-702.46" - process $proc$ls180.v:702$3034 - assign { } { } - assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] - end - attribute \src "ls180.v:7022.1-7041.4" - process $proc$ls180.v:7022$2328 - assign { } { } - assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 - attribute \src "ls180.v:7024.2-7040.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface0_converted_interface_cti - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface1_converted_interface_cti - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface2_converted_interface_cti - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface0_bus_cti - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface1_bus_cti - end - sync always - update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] - end - attribute \src "ls180.v:704.5-704.44" - process $proc$ls180.v:704$3035 - assign { } { } - assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] - end - attribute \src "ls180.v:7042.1-7061.4" - process $proc$ls180.v:7042$2329 - assign { } { } - assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 - attribute \src "ls180.v:7044.2-7060.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface0_converted_interface_bte - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface1_converted_interface_bte - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface2_converted_interface_bte - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface0_bus_bte - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface1_bus_bte - end - sync always - update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] - end - attribute \src "ls180.v:705.5-705.45" - process $proc$ls180.v:705$3036 - assign { } { } - assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] - end - attribute \src "ls180.v:706.5-706.54" - process $proc$ls180.v:706$3037 - assign { } { } - assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:7062.1-7078.4" - process $proc$ls180.v:7062$2330 - assign { } { } - assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 - attribute \src "ls180.v:7064.2-7077.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_nop_ba - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_cmd_payload_ba - end - sync always - update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] - end - attribute \src "ls180.v:7079.1-7095.4" - process $proc$ls180.v:7079$2331 - assign { } { } - assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:7081.2-7094.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_nop_a - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_cmd_payload_a - end - sync always - update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] - end - attribute \src "ls180.v:708.32-708.76" - process $proc$ls180.v:708$3038 - assign { } { } - assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] - end - attribute \src "ls180.v:709.11-709.55" - process $proc$ls180.v:709$3039 - assign { } { } - assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] - end - attribute \src "ls180.v:7096.1-7112.4" - process $proc$ls180.v:7096$2332 - assign { } { } - assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:7098.2-7111.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7103$2334_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7106$2336_Y - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7109$2338_Y - end - sync always - update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] - end - attribute \src "ls180.v:711.32-711.75" - process $proc$ls180.v:711$3040 - assign { } { } - assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:7113.1-7129.4" - process $proc$ls180.v:7113$2339 - assign { } { } - assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:7115.2-7128.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7120$2341_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7123$2343_Y - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7126$2345_Y - end - sync always - update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] - end - attribute \src "ls180.v:713.32-713.76" - process $proc$ls180.v:713$3041 - assign { } { } - assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:7130.1-7146.4" - process $proc$ls180.v:7130$2346 - assign { } { } - assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:7132.2-7145.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7137$2348_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7140$2350_Y - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7143$2352_Y - end - sync always - update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] - end - attribute \src "ls180.v:7147.1-7163.4" - process $proc$ls180.v:7147$2353 - assign { } { } - assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:7149.2-7162.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7154$2355_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7157$2357_Y - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7160$2359_Y - end - sync always - update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] - end - attribute \src "ls180.v:716.5-716.44" - process $proc$ls180.v:716$3042 - assign { } { } - assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] - sync init - end - attribute \src "ls180.v:7164.1-7180.4" - process $proc$ls180.v:7164$2360 - assign { } { } - assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:7166.2-7179.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7171$2362_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7174$2364_Y - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7177$2366_Y - end - sync always - update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] - end - attribute \src "ls180.v:717.5-717.45" - process $proc$ls180.v:717$3043 - assign { } { } - assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] - sync init - end - attribute \src "ls180.v:718.5-718.43" - process $proc$ls180.v:718$3044 - assign { } { } - assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] - sync init - end - attribute \src "ls180.v:7181.1-7209.4" - process $proc$ls180.v:7181$2367 - assign { } { } - assign $0\builder_sync_f_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:7183.2-7208.9" - switch \main_spi_master_mosi_sel - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [0] - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [1] - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [2] - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [3] - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [4] - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [5] - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [6] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [7] - end - sync always - update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] - end - attribute \src "ls180.v:719.5-719.48" - process $proc$ls180.v:719$3045 - assign { } { } - assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] - sync init - end - attribute \src "ls180.v:72.5-72.46" - process $proc$ls180.v:72$2781 - assign { } { } - assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0] - end - attribute \src "ls180.v:721.5-721.43" - process $proc$ls180.v:721$3046 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] - sync init - end - attribute \src "ls180.v:7210.1-7238.4" - process $proc$ls180.v:7210$2368 - assign { } { } - assign $0\builder_sync_f_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:7212.2-7237.9" - switch \libresocsim_mosi_sel - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [0] - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [1] - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [2] - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [3] - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [4] - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [5] - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [6] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [7] - end - sync always - update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] - end - attribute \src "ls180.v:724.5-724.49" - process $proc$ls180.v:724$3047 - assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:725.5-725.49" - process $proc$ls180.v:725$3048 - assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:726.5-726.48" - process $proc$ls180.v:726$3049 - assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] - end - attribute \src "ls180.v:7296.1-7314.4" - process $proc$ls180.v:7296$2369 - assign { } { } - assign { } { } - assign $0\main_gpio_status[15:0] [0] \builder_multiregimpl1_regs1 - assign $0\main_gpio_status[15:0] [1] \builder_multiregimpl2_regs1 - assign $0\main_gpio_status[15:0] [2] \builder_multiregimpl3_regs1 - assign $0\main_gpio_status[15:0] [3] \builder_multiregimpl4_regs1 - assign $0\main_gpio_status[15:0] [4] \builder_multiregimpl5_regs1 - assign $0\main_gpio_status[15:0] [5] \builder_multiregimpl6_regs1 - assign $0\main_gpio_status[15:0] [6] \builder_multiregimpl7_regs1 - assign $0\main_gpio_status[15:0] [7] \builder_multiregimpl8_regs1 - assign $0\main_gpio_status[15:0] [8] \builder_multiregimpl9_regs1 - assign $0\main_gpio_status[15:0] [9] \builder_multiregimpl10_regs1 - assign $0\main_gpio_status[15:0] [10] \builder_multiregimpl11_regs1 - assign $0\main_gpio_status[15:0] [11] \builder_multiregimpl12_regs1 - assign $0\main_gpio_status[15:0] [12] \builder_multiregimpl13_regs1 - assign $0\main_gpio_status[15:0] [13] \builder_multiregimpl14_regs1 - assign $0\main_gpio_status[15:0] [14] \builder_multiregimpl15_regs1 - assign $0\main_gpio_status[15:0] [15] \builder_multiregimpl16_regs1 - sync always - update \main_gpio_status $0\main_gpio_status[15:0] - end - attribute \src "ls180.v:730.11-730.46" - process $proc$ls180.v:730$3050 - assign { } { } - assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 - sync always - sync init - update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] - end - attribute \src "ls180.v:732.11-732.45" - process $proc$ls180.v:732$3051 - assign { } { } - assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 - sync always - sync init - update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] - end - attribute \src "ls180.v:7335.1-7337.4" - process $proc$ls180.v:7335$2370 - assign { } { } - assign $0\main_int_rst[0:0] \sys_rst - sync posedge \por_clk - update \main_int_rst $0\main_int_rst[0:0] - end - attribute \src "ls180.v:7339.1-7409.4" - process $proc$ls180.v:7339$2371 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\sdram_a[12:0] [0] \main_dfi_p0_address [0] - assign $0\sdram_a[12:0] [1] \main_dfi_p0_address [1] - assign $0\sdram_a[12:0] [2] \main_dfi_p0_address [2] - assign $0\sdram_a[12:0] [3] \main_dfi_p0_address [3] - assign $0\sdram_a[12:0] [4] \main_dfi_p0_address [4] - assign $0\sdram_a[12:0] [5] \main_dfi_p0_address [5] - assign $0\sdram_a[12:0] [6] \main_dfi_p0_address [6] - assign $0\sdram_a[12:0] [7] \main_dfi_p0_address [7] - assign $0\sdram_a[12:0] [8] \main_dfi_p0_address [8] - assign $0\sdram_a[12:0] [9] \main_dfi_p0_address [9] - assign $0\sdram_a[12:0] [10] \main_dfi_p0_address [10] - assign $0\sdram_a[12:0] [11] \main_dfi_p0_address [11] - assign $0\sdram_a[12:0] [12] \main_dfi_p0_address [12] - assign $0\sdram_ba[1:0] [0] \main_dfi_p0_bank [0] - assign $0\sdram_ba[1:0] [1] \main_dfi_p0_bank [1] - assign $0\sdram_cas_n[0:0] \main_dfi_p0_cas_n - assign $0\sdram_ras_n[0:0] \main_dfi_p0_ras_n - assign $0\sdram_we_n[0:0] \main_dfi_p0_we_n - assign $0\sdram_cke[0:0] \main_dfi_p0_cke - assign $0\sdram_cs_n[0:0] \main_dfi_p0_cs_n - assign $0\sdram_dq_oe[0:0] \main_dfi_p0_wrdata_en - assign $0\sdram_dq_o[15:0] [0] \main_dfi_p0_wrdata [0] - assign $0\main_dfi_p0_rddata[15:0] [0] \sdram_dq_i [0] - assign $0\sdram_dq_o[15:0] [1] \main_dfi_p0_wrdata [1] - assign $0\main_dfi_p0_rddata[15:0] [1] \sdram_dq_i [1] - assign $0\sdram_dq_o[15:0] [2] \main_dfi_p0_wrdata [2] - assign $0\main_dfi_p0_rddata[15:0] [2] \sdram_dq_i [2] - assign $0\sdram_dq_o[15:0] [3] \main_dfi_p0_wrdata [3] - assign $0\main_dfi_p0_rddata[15:0] [3] \sdram_dq_i [3] - assign $0\sdram_dq_o[15:0] [4] \main_dfi_p0_wrdata [4] - assign $0\main_dfi_p0_rddata[15:0] [4] \sdram_dq_i [4] - assign $0\sdram_dq_o[15:0] [5] \main_dfi_p0_wrdata [5] - assign $0\main_dfi_p0_rddata[15:0] [5] \sdram_dq_i [5] - assign $0\sdram_dq_o[15:0] [6] \main_dfi_p0_wrdata [6] - assign $0\main_dfi_p0_rddata[15:0] [6] \sdram_dq_i [6] - assign $0\sdram_dq_o[15:0] [7] \main_dfi_p0_wrdata [7] - assign $0\main_dfi_p0_rddata[15:0] [7] \sdram_dq_i [7] - assign $0\sdram_dq_o[15:0] [8] \main_dfi_p0_wrdata [8] - assign $0\main_dfi_p0_rddata[15:0] [8] \sdram_dq_i [8] - assign $0\sdram_dq_o[15:0] [9] \main_dfi_p0_wrdata [9] - assign $0\main_dfi_p0_rddata[15:0] [9] \sdram_dq_i [9] - assign $0\sdram_dq_o[15:0] [10] \main_dfi_p0_wrdata [10] - assign $0\main_dfi_p0_rddata[15:0] [10] \sdram_dq_i [10] - assign $0\sdram_dq_o[15:0] [11] \main_dfi_p0_wrdata [11] - assign $0\main_dfi_p0_rddata[15:0] [11] \sdram_dq_i [11] - assign $0\sdram_dq_o[15:0] [12] \main_dfi_p0_wrdata [12] - assign $0\main_dfi_p0_rddata[15:0] [12] \sdram_dq_i [12] - assign $0\sdram_dq_o[15:0] [13] \main_dfi_p0_wrdata [13] - assign $0\main_dfi_p0_rddata[15:0] [13] \sdram_dq_i [13] - assign $0\sdram_dq_o[15:0] [14] \main_dfi_p0_wrdata [14] - assign $0\main_dfi_p0_rddata[15:0] [14] \sdram_dq_i [14] - assign $0\sdram_dq_o[15:0] [15] \main_dfi_p0_wrdata [15] - assign $0\main_dfi_p0_rddata[15:0] [15] \sdram_dq_i [15] - assign $0\sdram_dm[1:0] [0] \main_dfi_p0_wrdata_mask [0] - assign $0\sdram_dm[1:0] [1] \main_dfi_p0_wrdata_mask [1] - assign $0\sdram_clock[0:0] \sys_clk_1 - assign $0\sdcard_clk[0:0] $and$ls180.v:7396$2373_Y - assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe - assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o - assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i - assign $0\sdcard_data_oe[0:0] \main_sdphy_sdpads_data_oe - assign $0\sdcard_data_o[3:0] [0] \main_sdphy_sdpads_data_o [0] - assign $0\main_sdphy_sdpads_data_i[3:0] [0] \sdcard_data_i [0] - assign $0\sdcard_data_o[3:0] [1] \main_sdphy_sdpads_data_o [1] - assign $0\main_sdphy_sdpads_data_i[3:0] [1] \sdcard_data_i [1] - assign $0\sdcard_data_o[3:0] [2] \main_sdphy_sdpads_data_o [2] - assign $0\main_sdphy_sdpads_data_i[3:0] [2] \sdcard_data_i [2] - assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3] - assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3] - sync posedge \sdrio_clk - update \sdram_a $0\sdram_a[12:0] - update \sdram_dq_o $0\sdram_dq_o[15:0] - update \sdram_dq_oe $0\sdram_dq_oe[0:0] - update \sdram_we_n $0\sdram_we_n[0:0] - update \sdram_ras_n $0\sdram_ras_n[0:0] - update \sdram_cas_n $0\sdram_cas_n[0:0] - update \sdram_cs_n $0\sdram_cs_n[0:0] - update \sdram_cke $0\sdram_cke[0:0] - update \sdram_ba $0\sdram_ba[1:0] - update \sdram_dm $0\sdram_dm[1:0] - update \sdram_clock $0\sdram_clock[0:0] - update \sdcard_clk $0\sdcard_clk[0:0] - update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] - update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] - update \sdcard_data_o $0\sdcard_data_o[3:0] - update \sdcard_data_oe $0\sdcard_data_oe[0:0] - update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] - update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] - update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] - end - attribute \src "ls180.v:734.5-734.44" - process $proc$ls180.v:734$3052 - assign { } { } - assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] - end - attribute \src "ls180.v:735.5-735.45" - process $proc$ls180.v:735$3053 - assign { } { } - assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] - end - attribute \src "ls180.v:737.5-737.48" - process $proc$ls180.v:737$3054 - assign { } { } - assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] - end - attribute \src "ls180.v:739.5-739.43" - process $proc$ls180.v:739$3055 - assign { } { } - assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] - end - attribute \src "ls180.v:7411.1-10036.4" - process $proc$ls180.v:7411$2374 - assign $0\spi_master_clk[0:0] \spi_master_clk - assign $0\spi_master_mosi[0:0] \spi_master_mosi - assign { } { } - assign $0\pwm0[0:0] \pwm0 - assign $0\pwm1[0:0] \pwm1 - assign $0\spisdcard_clk[0:0] \spisdcard_clk - assign $0\spisdcard_mosi[0:0] \spisdcard_mosi - assign { } { } - assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage - assign { } { } - assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage - assign { } { } - assign $0\main_libresocsim_bus_errors[31:0] \main_libresocsim_bus_errors - assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] \main_libresocsim_libresoc_constraintmanager0_uart0_tx - assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter - assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_converter0_dat_r - assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter - assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_converter1_dat_r - assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter - assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_converter2_dat_r - assign { } { } - assign $0\main_libresocsim_load_storage[31:0] \main_libresocsim_load_storage - assign { } { } - assign $0\main_libresocsim_reload_storage[31:0] \main_libresocsim_reload_storage - assign { } { } - assign $0\main_libresocsim_en_storage[0:0] \main_libresocsim_en_storage - assign { } { } - assign $0\main_libresocsim_update_value_storage[0:0] \main_libresocsim_update_value_storage - assign { } { } - assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value_status - assign $0\main_libresocsim_zero_pending[0:0] \main_libresocsim_zero_pending - assign { } { } - assign $0\main_libresocsim_eventmanager_storage[0:0] \main_libresocsim_eventmanager_storage - assign { } { } - assign $0\main_libresocsim_value[31:0] \main_libresocsim_value - assign { } { } - assign { } { } - assign $0\main_sdram_storage[3:0] \main_sdram_storage - assign { } { } - assign $0\main_sdram_command_storage[5:0] \main_sdram_command_storage - assign { } { } - assign $0\main_sdram_address_storage[12:0] \main_sdram_address_storage - assign { } { } - assign $0\main_sdram_baddress_storage[1:0] \main_sdram_baddress_storage - assign { } { } - assign $0\main_sdram_wrdata_storage[15:0] \main_sdram_wrdata_storage - assign { } { } - assign $0\main_sdram_status[15:0] \main_sdram_status - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_timer_count1[9:0] \main_sdram_timer_count1 - assign { } { } - assign $0\main_sdram_postponer_count[0:0] \main_sdram_postponer_count - assign { } { } - assign $0\main_sdram_sequencer_counter[3:0] \main_sdram_sequencer_counter - assign $0\main_sdram_sequencer_count[0:0] \main_sdram_sequencer_count - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_source_first - assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_source_last - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_row - assign $0\main_sdram_bankmachine0_row_opened[0:0] \main_sdram_bankmachine0_row_opened - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] \main_sdram_bankmachine0_twtpcon_ready - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] \main_sdram_bankmachine0_twtpcon_count - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_source_first - assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_source_last - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_row - assign $0\main_sdram_bankmachine1_row_opened[0:0] \main_sdram_bankmachine1_row_opened - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] \main_sdram_bankmachine1_twtpcon_ready - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] \main_sdram_bankmachine1_twtpcon_count - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_source_first - assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_source_last - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_row - assign $0\main_sdram_bankmachine2_row_opened[0:0] \main_sdram_bankmachine2_row_opened - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] \main_sdram_bankmachine2_twtpcon_ready - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] \main_sdram_bankmachine2_twtpcon_count - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_source_first - assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_source_last - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_row - assign $0\main_sdram_bankmachine3_row_opened[0:0] \main_sdram_bankmachine3_row_opened - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] \main_sdram_bankmachine3_twtpcon_ready - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] \main_sdram_bankmachine3_twtpcon_count - assign $0\main_sdram_choose_cmd_grant[1:0] \main_sdram_choose_cmd_grant - assign $0\main_sdram_choose_req_grant[1:0] \main_sdram_choose_req_grant - assign $0\main_sdram_tccdcon_ready[0:0] \main_sdram_tccdcon_ready - assign $0\main_sdram_tccdcon_count[0:0] \main_sdram_tccdcon_count - assign $0\main_sdram_twtrcon_ready[0:0] \main_sdram_twtrcon_ready - assign $0\main_sdram_twtrcon_count[2:0] \main_sdram_twtrcon_count - assign $0\main_sdram_time0[4:0] \main_sdram_time0 - assign $0\main_sdram_time1[3:0] \main_sdram_time1 - assign $0\main_converter_counter[0:0] \main_converter_counter - assign $0\main_converter_dat_r[31:0] \main_converter_dat_r - assign $0\main_cmd_consumed[0:0] \main_cmd_consumed - assign $0\main_wdata_consumed[0:0] \main_wdata_consumed - assign $0\main_uart_phy_storage[31:0] \main_uart_phy_storage - assign { } { } - assign { } { } - assign $0\main_uart_phy_uart_clk_txen[0:0] \main_uart_phy_uart_clk_txen - assign $0\main_uart_phy_phase_accumulator_tx[31:0] \main_uart_phy_phase_accumulator_tx - assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_tx_reg - assign $0\main_uart_phy_tx_bitcount[3:0] \main_uart_phy_tx_bitcount - assign $0\main_uart_phy_tx_busy[0:0] \main_uart_phy_tx_busy - assign { } { } - assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_source_payload_data - assign $0\main_uart_phy_uart_clk_rxen[0:0] \main_uart_phy_uart_clk_rxen - assign $0\main_uart_phy_phase_accumulator_rx[31:0] \main_uart_phy_phase_accumulator_rx - assign { } { } - assign $0\main_uart_phy_rx_reg[7:0] \main_uart_phy_rx_reg - assign $0\main_uart_phy_rx_bitcount[3:0] \main_uart_phy_rx_bitcount - assign $0\main_uart_phy_rx_busy[0:0] \main_uart_phy_rx_busy - assign $0\main_uart_tx_pending[0:0] \main_uart_tx_pending - assign { } { } - assign $0\main_uart_rx_pending[0:0] \main_uart_rx_pending - assign { } { } - assign $0\main_uart_eventmanager_storage[1:0] \main_uart_eventmanager_storage - assign { } { } - assign $0\main_uart_tx_fifo_readable[0:0] \main_uart_tx_fifo_readable - assign $0\main_uart_tx_fifo_level0[4:0] \main_uart_tx_fifo_level0 - assign $0\main_uart_tx_fifo_produce[3:0] \main_uart_tx_fifo_produce - assign $0\main_uart_tx_fifo_consume[3:0] \main_uart_tx_fifo_consume - assign $0\main_uart_rx_fifo_readable[0:0] \main_uart_rx_fifo_readable - assign $0\main_uart_rx_fifo_level0[4:0] \main_uart_rx_fifo_level0 - assign $0\main_uart_rx_fifo_produce[3:0] \main_uart_rx_fifo_produce - assign $0\main_uart_rx_fifo_consume[3:0] \main_uart_rx_fifo_consume - assign $0\main_gpio_oe_storage[15:0] \main_gpio_oe_storage - assign { } { } - assign $0\main_gpio_out_storage[15:0] \main_gpio_out_storage - assign { } { } - assign $0\main_spi_master_miso[7:0] \main_spi_master_miso - assign $0\main_spi_master_control_storage[15:0] \main_spi_master_control_storage - assign { } { } - assign $0\main_spi_master_mosi_storage[7:0] \main_spi_master_mosi_storage - assign { } { } - assign $0\main_spi_master_cs_storage[0:0] \main_spi_master_cs_storage - assign { } { } - assign $0\main_spi_master_loopback_storage[0:0] \main_spi_master_loopback_storage - assign { } { } - assign $0\main_spi_master_count[2:0] \main_spi_master_count - assign { } { } - assign $0\main_spi_master_mosi_data[7:0] \main_spi_master_mosi_data - assign $0\main_spi_master_mosi_sel[2:0] \main_spi_master_mosi_sel - assign $0\main_spi_master_miso_data[7:0] \main_spi_master_miso_data - assign { } { } - assign $0\main_pwm0_counter[31:0] \main_pwm0_counter - assign $0\main_pwm0_enable_storage[0:0] \main_pwm0_enable_storage - assign { } { } - assign $0\main_pwm0_width_storage[31:0] \main_pwm0_width_storage - assign { } { } - assign $0\main_pwm0_period_storage[31:0] \main_pwm0_period_storage - assign { } { } - assign $0\main_pwm1_counter[31:0] \main_pwm1_counter - assign $0\main_pwm1_enable_storage[0:0] \main_pwm1_enable_storage - assign { } { } - assign $0\main_pwm1_width_storage[31:0] \main_pwm1_width_storage - assign { } { } - assign $0\main_pwm1_period_storage[31:0] \main_pwm1_period_storage - assign { } { } - assign $0\main_i2c_storage[2:0] \main_i2c_storage - assign { } { } - assign $0\main_sdphy_clocker_storage[8:0] \main_sdphy_clocker_storage - assign { } { } - assign { } { } - assign $0\main_sdphy_clocker_clks[8:0] \main_sdphy_clocker_clks - assign { } { } - assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count - assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count - assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout - assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count - assign $0\main_sdphy_cmdr_cmdr_run[0:0] \main_sdphy_cmdr_cmdr_run - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_source_first - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_source_last - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_converter_source_payload_data - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] \main_sdphy_cmdr_cmdr_converter_demux - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] \main_sdphy_cmdr_cmdr_converter_strobe_all - assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_source_valid - assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_source_first - assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_source_last - assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_source_payload_data - assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset - assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count - assign $0\main_sdphy_dataw_crcr_run[0:0] \main_sdphy_dataw_crcr_run - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_source_first - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_source_last - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] \main_sdphy_dataw_crcr_converter_source_payload_data - assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] \main_sdphy_dataw_crcr_converter_demux - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] \main_sdphy_dataw_crcr_converter_strobe_all - assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_source_valid - assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_source_first - assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_source_last - assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_source_payload_data - assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset - assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout - assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count - assign $0\main_sdphy_datar_datar_run[0:0] \main_sdphy_datar_datar_run - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_source_first - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_source_last - assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] \main_sdphy_datar_datar_converter_source_payload_data - assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] \main_sdphy_datar_datar_converter_source_payload_valid_token_count - assign $0\main_sdphy_datar_datar_converter_demux[0:0] \main_sdphy_datar_datar_converter_demux - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] \main_sdphy_datar_datar_converter_strobe_all - assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_source_valid - assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_source_first - assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_source_last - assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_source_payload_data - assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset - assign $0\main_sdcore_cmd_argument_storage[31:0] \main_sdcore_cmd_argument_storage - assign { } { } - assign $0\main_sdcore_cmd_command_storage[31:0] \main_sdcore_cmd_command_storage - assign { } { } - assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status - assign $0\main_sdcore_block_length_storage[9:0] \main_sdcore_block_length_storage - assign { } { } - assign $0\main_sdcore_block_count_storage[31:0] \main_sdcore_block_count_storage - assign { } { } - assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg0 - assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt - assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 - assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 - assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 - assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 - assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0 - assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1 - assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2 - assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3 - assign $0\main_sdcore_crc16_checker_val[7:0] \main_sdcore_crc16_checker_val - assign $0\main_sdcore_crc16_checker_cnt[3:0] \main_sdcore_crc16_checker_cnt - assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 - assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 - assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 - assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 - assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crctmp0 - assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crctmp1 - assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crctmp2 - assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crctmp3 - assign $0\main_sdcore_crc16_checker_fifo0[15:0] \main_sdcore_crc16_checker_fifo0 - assign $0\main_sdcore_crc16_checker_fifo1[15:0] \main_sdcore_crc16_checker_fifo1 - assign $0\main_sdcore_crc16_checker_fifo2[15:0] \main_sdcore_crc16_checker_fifo2 - assign $0\main_sdcore_crc16_checker_fifo3[15:0] \main_sdcore_crc16_checker_fifo3 - assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count - assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done - assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error - assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout - assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count - assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done - assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error - assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout - assign $0\main_sdblock2mem_fifo_level[5:0] \main_sdblock2mem_fifo_level - assign $0\main_sdblock2mem_fifo_produce[4:0] \main_sdblock2mem_fifo_produce - assign $0\main_sdblock2mem_fifo_consume[4:0] \main_sdblock2mem_fifo_consume - assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_source_first - assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_source_last - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] \main_sdblock2mem_converter_source_payload_data - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] \main_sdblock2mem_converter_source_payload_valid_token_count - assign $0\main_sdblock2mem_converter_demux[1:0] \main_sdblock2mem_converter_demux - assign $0\main_sdblock2mem_converter_strobe_all[0:0] \main_sdblock2mem_converter_strobe_all - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] \main_sdblock2mem_wishbonedmawriter_base_storage - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] \main_sdblock2mem_wishbonedmawriter_length_storage - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \main_sdblock2mem_wishbonedmawriter_enable_storage - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \main_sdblock2mem_wishbonedmawriter_loop_storage - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset - assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data - assign $0\main_sdmem2block_dma_base_storage[63:0] \main_sdmem2block_dma_base_storage - assign { } { } - assign $0\main_sdmem2block_dma_length_storage[31:0] \main_sdmem2block_dma_length_storage - assign { } { } - assign $0\main_sdmem2block_dma_enable_storage[0:0] \main_sdmem2block_dma_enable_storage - assign { } { } - assign $0\main_sdmem2block_dma_loop_storage[0:0] \main_sdmem2block_dma_loop_storage - assign { } { } - assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset - assign $0\main_sdmem2block_converter_mux[1:0] \main_sdmem2block_converter_mux - assign $0\main_sdmem2block_fifo_level[5:0] \main_sdmem2block_fifo_level - assign $0\main_sdmem2block_fifo_produce[4:0] \main_sdmem2block_fifo_produce - assign $0\main_sdmem2block_fifo_consume[4:0] \main_sdmem2block_fifo_consume - assign $0\libresocsim_miso[7:0] \libresocsim_miso - assign $0\libresocsim_control_storage[15:0] \libresocsim_control_storage - assign { } { } - assign $0\libresocsim_mosi_storage[7:0] \libresocsim_mosi_storage - assign { } { } - assign $0\libresocsim_cs_storage[0:0] \libresocsim_cs_storage - assign { } { } - assign $0\libresocsim_loopback_storage[0:0] \libresocsim_loopback_storage - assign { } { } - assign $0\libresocsim_count[2:0] \libresocsim_count - assign { } { } - assign $0\libresocsim_mosi_data[7:0] \libresocsim_mosi_data - assign $0\libresocsim_mosi_sel[2:0] \libresocsim_mosi_sel - assign $0\libresocsim_miso_data[7:0] \libresocsim_miso_data - assign $0\libresocsim_storage[15:0] \libresocsim_storage - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr - assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we - assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w - assign $0\builder_grant[2:0] \builder_grant - assign { } { } - assign $0\builder_count[19:0] \builder_count - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_dummy[35:0] [0] $or$ls180.v:7412$2375_Y - assign $0\main_dummy[35:0] [1] $or$ls180.v:7413$2376_Y - assign $0\main_dummy[35:0] [2] $or$ls180.v:7414$2377_Y - assign $0\main_dummy[35:0] [3] $or$ls180.v:7415$2378_Y - assign $0\main_dummy[35:0] [4] $or$ls180.v:7416$2379_Y - assign $0\main_dummy[35:0] [5] $or$ls180.v:7417$2380_Y - assign $0\main_dummy[35:0] [6] $or$ls180.v:7418$2381_Y - assign $0\main_dummy[35:0] [7] $or$ls180.v:7419$2382_Y - assign $0\main_dummy[35:0] [8] $or$ls180.v:7420$2383_Y - assign $0\main_dummy[35:0] [9] $or$ls180.v:7421$2384_Y - assign $0\main_dummy[35:0] [10] $or$ls180.v:7422$2385_Y - assign $0\main_dummy[35:0] [11] $or$ls180.v:7423$2386_Y - assign $0\main_dummy[35:0] [12] $or$ls180.v:7424$2387_Y - assign $0\main_dummy[35:0] [13] $or$ls180.v:7425$2388_Y - assign $0\main_dummy[35:0] [14] $or$ls180.v:7426$2389_Y - assign $0\main_dummy[35:0] [15] $or$ls180.v:7427$2390_Y - assign $0\main_dummy[35:0] [16] $or$ls180.v:7428$2391_Y - assign $0\main_dummy[35:0] [17] $or$ls180.v:7429$2392_Y - assign $0\main_dummy[35:0] [18] $or$ls180.v:7430$2393_Y - assign $0\main_dummy[35:0] [19] $or$ls180.v:7431$2394_Y - assign $0\main_dummy[35:0] [20] $or$ls180.v:7432$2395_Y - assign $0\main_dummy[35:0] [21] $or$ls180.v:7433$2396_Y - assign $0\main_dummy[35:0] [22] $or$ls180.v:7434$2397_Y - assign $0\main_dummy[35:0] [23] $or$ls180.v:7435$2398_Y - assign $0\main_dummy[35:0] [24] $or$ls180.v:7436$2399_Y - assign $0\main_dummy[35:0] [25] $or$ls180.v:7437$2400_Y - assign $0\main_dummy[35:0] [26] $or$ls180.v:7438$2401_Y - assign $0\main_dummy[35:0] [27] $or$ls180.v:7439$2402_Y - assign $0\main_dummy[35:0] [28] $or$ls180.v:7440$2403_Y - assign $0\main_dummy[35:0] [29] $or$ls180.v:7441$2404_Y - assign $0\main_dummy[35:0] [30] $or$ls180.v:7442$2405_Y - assign $0\main_dummy[35:0] [31] $or$ls180.v:7443$2406_Y - assign $0\main_dummy[35:0] [32] $or$ls180.v:7444$2407_Y - assign $0\main_dummy[35:0] [33] $or$ls180.v:7445$2408_Y - assign $0\main_dummy[35:0] [34] $or$ls180.v:7446$2409_Y - assign $0\main_dummy[35:0] [35] $or$ls180.v:7447$2410_Y - assign $0\builder_converter0_state[0:0] \builder_converter0_next_state - assign $0\builder_converter1_state[0:0] \builder_converter1_next_state - assign $0\builder_converter2_state[0:0] \builder_converter2_next_state - assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 - assign $0\main_libresocsim_zero_old_trigger[0:0] \main_libresocsim_zero_trigger - assign $0\main_rddata_en[2:0] { \main_rddata_en [1:0] \main_dfi_p0_rddata_en } - assign $0\main_dfi_p0_rddata_valid[0:0] \main_rddata_en [2] - assign $0\main_sdram_postponer_req_o[0:0] 1'0 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_sequencer_done1[0:0] 1'0 - assign $0\builder_refresher_state[1:0] \builder_refresher_next_state - assign $0\builder_bankmachine0_state[2:0] \builder_bankmachine0_next_state - assign $0\builder_bankmachine1_state[2:0] \builder_bankmachine1_next_state - assign $0\builder_bankmachine2_state[2:0] \builder_bankmachine2_next_state - assign $0\builder_bankmachine3_state[2:0] \builder_bankmachine3_next_state - assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 - assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 - assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 - assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7889$2507_Y - assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7890$2508_Y - assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7891$2509_Y - assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 - assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 - assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state - assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:7925$2527_Y - assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:7926$2539_Y - assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 - assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 - assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 - assign $0\builder_converter_state[0:0] \builder_converter_next_state - assign $0\main_uart_phy_sink_ready[0:0] 1'0 - assign $0\main_uart_phy_source_valid[0:0] 1'0 - assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx - assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger - assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger - assign $0\main_spi_master_clk_divider1[15:0] $add$ls180.v:8084$2585_Y - assign $0\spi_master_cs_n[0:0] $or$ls180.v:8093$2588_Y - assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state - assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 - assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 - assign $0\builder_sdphy_sdphyinit_state[0:0] \builder_sdphy_sdphyinit_next_state - assign $0\builder_sdphy_sdphycmdw_state[1:0] \builder_sdphy_sdphycmdw_next_state - assign $0\builder_sdphy_sdphycmdr_state[2:0] \builder_sdphy_sdphycmdr_next_state - assign $0\builder_sdphy_sdphycrcr_state[0:0] \builder_sdphy_sdphycrcr_next_state - assign $0\builder_sdphy_fsm_state[2:0] \builder_sdphy_fsm_next_state - assign $0\builder_sdphy_sdphydatar_state[2:0] \builder_sdphy_sdphydatar_next_state - assign $0\builder_sdcore_crcupstreaminserter_state[0:0] \builder_sdcore_crcupstreaminserter_next_state - assign $0\builder_sdcore_fsm_state[2:0] \builder_sdcore_fsm_next_state - assign $0\builder_sdblock2memdma_state[1:0] \builder_sdblock2memdma_next_state - assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state - assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state - assign $0\libresocsim_clk_divider1[15:0] $add$ls180.v:8632$2680_Y - assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8641$2683_Y - assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state - assign $0\builder_state[1:0] \builder_next_state - assign $0\builder_slave_sel_r[4:0] \builder_slave_sel - assign $0\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_libresocsim_reset_re[0:0] \builder_csrbank0_reset0_re - assign $0\main_libresocsim_scratch_re[0:0] \builder_csrbank0_scratch0_re - assign $0\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_gpio_oe_re[0:0] \builder_csrbank1_oe0_re - assign $0\main_gpio_out_re[0:0] \builder_csrbank1_out0_re - assign $0\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_i2c_re[0:0] \builder_csrbank2_w0_re - assign $0\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_pwm0_enable_re[0:0] \builder_csrbank3_enable0_re - assign $0\main_pwm0_width_re[0:0] \builder_csrbank3_width0_re - assign $0\main_pwm0_period_re[0:0] \builder_csrbank3_period0_re - assign $0\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_pwm1_enable_re[0:0] \builder_csrbank4_enable0_re - assign $0\main_pwm1_width_re[0:0] \builder_csrbank4_width0_re - assign $0\main_pwm1_period_re[0:0] \builder_csrbank4_period0_re - assign $0\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] \builder_csrbank5_dma_base0_re - assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] \builder_csrbank5_dma_length0_re - assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] \builder_csrbank5_dma_enable0_re - assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] \builder_csrbank5_dma_loop0_re - assign $0\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdcore_cmd_argument_re[0:0] \builder_csrbank6_cmd_argument0_re - assign $0\main_sdcore_cmd_command_re[0:0] \builder_csrbank6_cmd_command0_re - assign $0\main_sdcore_block_length_re[0:0] \builder_csrbank6_block_length0_re - assign $0\main_sdcore_block_count_re[0:0] \builder_csrbank6_block_count0_re - assign $0\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdmem2block_dma_base_re[0:0] \builder_csrbank7_dma_base0_re - assign $0\main_sdmem2block_dma_length_re[0:0] \builder_csrbank7_dma_length0_re - assign $0\main_sdmem2block_dma_enable_re[0:0] \builder_csrbank7_dma_enable0_re - assign $0\main_sdmem2block_dma_loop_re[0:0] \builder_csrbank7_dma_loop0_re - assign $0\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdphy_clocker_re[0:0] \builder_csrbank8_clocker_divider0_re - assign $0\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdram_re[0:0] \builder_csrbank9_dfii_control0_re - assign $0\main_sdram_command_re[0:0] \builder_csrbank9_dfii_pi0_command0_re - assign $0\main_sdram_address_re[0:0] \builder_csrbank9_dfii_pi0_address0_re - assign $0\main_sdram_baddress_re[0:0] \builder_csrbank9_dfii_pi0_baddress0_re - assign $0\main_sdram_wrdata_re[0:0] \builder_csrbank9_dfii_pi0_wrdata0_re - assign $0\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_spi_master_control_re[0:0] \builder_csrbank10_control0_re - assign $0\main_spi_master_mosi_re[0:0] \builder_csrbank10_mosi0_re - assign $0\main_spi_master_cs_re[0:0] \builder_csrbank10_cs0_re - assign $0\main_spi_master_loopback_re[0:0] \builder_csrbank10_loopback0_re - assign $0\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 - assign $0\libresocsim_control_re[0:0] \builder_csrbank11_control0_re - assign $0\libresocsim_mosi_re[0:0] \builder_csrbank11_mosi0_re - assign $0\libresocsim_cs_re[0:0] \builder_csrbank11_cs0_re - assign $0\libresocsim_loopback_re[0:0] \builder_csrbank11_loopback0_re - assign $0\libresocsim_re[0:0] \builder_csrbank11_clk_divider0_re - assign $0\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_libresocsim_load_re[0:0] \builder_csrbank12_load0_re - assign $0\main_libresocsim_reload_re[0:0] \builder_csrbank12_reload0_re - assign $0\main_libresocsim_en_re[0:0] \builder_csrbank12_en0_re - assign $0\main_libresocsim_update_value_re[0:0] \builder_csrbank12_update_value0_re - assign $0\main_libresocsim_eventmanager_re[0:0] \builder_csrbank12_ev_enable0_re - assign $0\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_uart_eventmanager_re[0:0] \builder_csrbank13_ev_enable0_re - assign $0\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_uart_phy_re[0:0] \builder_csrbank14_tuning_word0_re - assign $0\builder_multiregimpl0_regs0[0:0] \main_libresocsim_libresoc_constraintmanager0_uart0_rx - assign $0\builder_multiregimpl0_regs1[0:0] \builder_multiregimpl0_regs0 - assign $0\builder_multiregimpl1_regs0[0:0] \main_gpio_pads_i [0] - assign $0\builder_multiregimpl1_regs1[0:0] \builder_multiregimpl1_regs0 - assign $0\builder_multiregimpl2_regs0[0:0] \main_gpio_pads_i [1] - assign $0\builder_multiregimpl2_regs1[0:0] \builder_multiregimpl2_regs0 - assign $0\builder_multiregimpl3_regs0[0:0] \main_gpio_pads_i [2] - assign $0\builder_multiregimpl3_regs1[0:0] \builder_multiregimpl3_regs0 - assign $0\builder_multiregimpl4_regs0[0:0] \main_gpio_pads_i [3] - assign $0\builder_multiregimpl4_regs1[0:0] \builder_multiregimpl4_regs0 - assign $0\builder_multiregimpl5_regs0[0:0] \main_gpio_pads_i [4] - assign $0\builder_multiregimpl5_regs1[0:0] \builder_multiregimpl5_regs0 - assign $0\builder_multiregimpl6_regs0[0:0] \main_gpio_pads_i [5] - assign $0\builder_multiregimpl6_regs1[0:0] \builder_multiregimpl6_regs0 - assign $0\builder_multiregimpl7_regs0[0:0] \main_gpio_pads_i [6] - assign $0\builder_multiregimpl7_regs1[0:0] \builder_multiregimpl7_regs0 - assign $0\builder_multiregimpl8_regs0[0:0] \main_gpio_pads_i [7] - assign $0\builder_multiregimpl8_regs1[0:0] \builder_multiregimpl8_regs0 - assign $0\builder_multiregimpl9_regs0[0:0] \main_gpio_pads_i [8] - assign $0\builder_multiregimpl9_regs1[0:0] \builder_multiregimpl9_regs0 - assign $0\builder_multiregimpl10_regs0[0:0] \main_gpio_pads_i [9] - assign $0\builder_multiregimpl10_regs1[0:0] \builder_multiregimpl10_regs0 - assign $0\builder_multiregimpl11_regs0[0:0] \main_gpio_pads_i [10] - assign $0\builder_multiregimpl11_regs1[0:0] \builder_multiregimpl11_regs0 - assign $0\builder_multiregimpl12_regs0[0:0] \main_gpio_pads_i [11] - assign $0\builder_multiregimpl12_regs1[0:0] \builder_multiregimpl12_regs0 - assign $0\builder_multiregimpl13_regs0[0:0] \main_gpio_pads_i [12] - assign $0\builder_multiregimpl13_regs1[0:0] \builder_multiregimpl13_regs0 - assign $0\builder_multiregimpl14_regs0[0:0] \main_gpio_pads_i [13] - assign $0\builder_multiregimpl14_regs1[0:0] \builder_multiregimpl14_regs0 - assign $0\builder_multiregimpl15_regs0[0:0] \main_gpio_pads_i [14] - assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0 - assign $0\builder_multiregimpl16_regs0[0:0] \main_gpio_pads_i [15] - assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 - attribute \src "ls180.v:7448.2-7450.5" - switch $or$ls180.v:7448$2411_Y - attribute \src "ls180.v:7448.6-7448.94" - case 1'1 - assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_libresoc_ibus_dat_r - case - end - attribute \src "ls180.v:7452.2-7454.5" - switch \main_libresocsim_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:7452.6-7452.66" - case 1'1 - assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter_converter0_next_value - case - end - attribute \src "ls180.v:7455.2-7458.5" - switch \main_libresocsim_converter0_reset - attribute \src "ls180.v:7455.6-7455.39" - case 1'1 - assign $0\main_libresocsim_converter0_counter[0:0] 1'0 - assign $0\builder_converter0_state[0:0] 1'0 - case - end - attribute \src "ls180.v:7459.2-7461.5" - switch $or$ls180.v:7459$2412_Y - attribute \src "ls180.v:7459.6-7459.94" - case 1'1 - assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_libresoc_dbus_dat_r - case - end - attribute \src "ls180.v:7463.2-7465.5" - switch \main_libresocsim_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:7463.6-7463.66" - case 1'1 - assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter_converter1_next_value - case - end - attribute \src "ls180.v:7466.2-7469.5" - switch \main_libresocsim_converter1_reset - attribute \src "ls180.v:7466.6-7466.39" - case 1'1 - assign $0\main_libresocsim_converter1_counter[0:0] 1'0 - assign $0\builder_converter1_state[0:0] 1'0 - case - end - attribute \src "ls180.v:7470.2-7472.5" - switch $or$ls180.v:7470$2413_Y - attribute \src "ls180.v:7470.6-7470.94" - case 1'1 - assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_libresoc_jtag_wb_dat_r - case - end - attribute \src "ls180.v:7474.2-7476.5" - switch \main_libresocsim_converter2_counter_converter2_next_value_ce - attribute \src "ls180.v:7474.6-7474.66" - case 1'1 - assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter_converter2_next_value - case - end - attribute \src "ls180.v:7477.2-7480.5" - switch \main_libresocsim_converter2_reset - attribute \src "ls180.v:7477.6-7477.39" - case 1'1 - assign $0\main_libresocsim_converter2_counter[0:0] 1'0 - assign $0\builder_converter2_state[0:0] 1'0 - case - end - attribute \src "ls180.v:7481.2-7485.5" - switch $ne$ls180.v:7481$2414_Y - attribute \src "ls180.v:7481.6-7481.53" - case 1'1 - attribute \src "ls180.v:7482.3-7484.6" - switch \main_libresocsim_bus_error - attribute \src "ls180.v:7482.7-7482.33" - case 1'1 - assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7483$2415_Y - case - end - case - end - attribute \src "ls180.v:7487.2-7489.5" - switch $and$ls180.v:7487$2418_Y - attribute \src "ls180.v:7487.6-7487.103" - case 1'1 - assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 - case - end - attribute \src "ls180.v:7490.2-7498.5" - switch \main_libresocsim_en_storage - attribute \src "ls180.v:7490.6-7490.33" - case 1'1 - attribute \src "ls180.v:7491.3-7495.6" - switch $eq$ls180.v:7491$2419_Y - attribute \src "ls180.v:7491.7-7491.39" - case 1'1 - assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage - attribute \src "ls180.v:7493.7-7493.11" - case - assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7494$2420_Y - end - attribute \src "ls180.v:7496.6-7496.10" - case - assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage - end - attribute \src "ls180.v:7499.2-7501.5" - switch \main_libresocsim_update_value_re - attribute \src "ls180.v:7499.6-7499.38" - case 1'1 - assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value - case - end - attribute \src "ls180.v:7502.2-7504.5" - switch \main_libresocsim_zero_clear - attribute \src "ls180.v:7502.6-7502.33" - case 1'1 - assign $0\main_libresocsim_zero_pending[0:0] 1'0 - case - end - attribute \src "ls180.v:7506.2-7508.5" - switch $and$ls180.v:7506$2422_Y - attribute \src "ls180.v:7506.6-7506.76" - case 1'1 - assign $0\main_libresocsim_zero_pending[0:0] 1'1 - case - end - attribute \src "ls180.v:7511.2-7513.5" - switch \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:7511.6-7511.37" - case 1'1 - assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata - case - end - attribute \src "ls180.v:7514.2-7518.5" - switch $and$ls180.v:7514$2424_Y - attribute \src "ls180.v:7514.6-7514.57" - case 1'1 - assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7515$2425_Y - attribute \src "ls180.v:7516.6-7516.10" - case - assign $0\main_sdram_timer_count1[9:0] 10'1100001101 - end - attribute \src "ls180.v:7520.2-7526.5" - switch \main_sdram_postponer_req_i - attribute \src "ls180.v:7520.6-7520.32" - case 1'1 - assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7521$2426_Y - attribute \src "ls180.v:7522.3-7525.6" - switch $eq$ls180.v:7522$2427_Y - attribute \src "ls180.v:7522.7-7522.43" - case 1'1 - assign $0\main_sdram_postponer_count[0:0] 1'0 - assign $0\main_sdram_postponer_req_o[0:0] 1'1 - case - end - case - end - attribute \src "ls180.v:7527.2-7535.5" - switch \main_sdram_sequencer_start0 - attribute \src "ls180.v:7527.6-7527.33" - case 1'1 - assign $0\main_sdram_sequencer_count[0:0] 1'0 - attribute \src "ls180.v:7529.6-7529.10" - case - attribute \src "ls180.v:7530.3-7534.6" - switch \main_sdram_sequencer_done1 - attribute \src "ls180.v:7530.7-7530.33" - case 1'1 - attribute \src "ls180.v:7531.4-7533.7" - switch $ne$ls180.v:7531$2428_Y - attribute \src "ls180.v:7531.8-7531.44" - case 1'1 - assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7532$2429_Y - case - end - case - end - end - attribute \src "ls180.v:7542.2-7548.5" - switch $and$ls180.v:7542$2431_Y - attribute \src "ls180.v:7542.6-7542.76" - case 1'1 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_cmd_payload_we[0:0] 1'1 - case - end - attribute \src "ls180.v:7549.2-7555.5" - switch $eq$ls180.v:7549$2432_Y - attribute \src "ls180.v:7549.6-7549.44" - case 1'1 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'1 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_cmd_payload_we[0:0] 1'0 - case - end - attribute \src "ls180.v:7556.2-7563.5" - switch $eq$ls180.v:7556$2433_Y - attribute \src "ls180.v:7556.6-7556.44" - case 1'1 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_sequencer_done1[0:0] 1'1 - case - end - attribute \src "ls180.v:7564.2-7574.5" - switch $eq$ls180.v:7564$2434_Y - attribute \src "ls180.v:7564.6-7564.44" - case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] 4'0000 - attribute \src "ls180.v:7566.6-7566.10" - case - attribute \src "ls180.v:7567.3-7573.6" - switch $ne$ls180.v:7567$2435_Y - attribute \src "ls180.v:7567.7-7567.45" - case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7568$2436_Y - attribute \src "ls180.v:7569.7-7569.11" - case - attribute \src "ls180.v:7570.4-7572.7" - switch \main_sdram_sequencer_start1 - attribute \src "ls180.v:7570.8-7570.35" - case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] 4'0001 - case - end - end - end - attribute \src "ls180.v:7576.2-7583.5" - switch \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:7576.6-7576.39" - case 1'1 - assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 - attribute \src "ls180.v:7578.6-7578.10" - case - attribute \src "ls180.v:7579.3-7582.6" - switch \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:7579.7-7579.39" - case 1'1 - assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - case - end - end - attribute \src "ls180.v:7584.2-7586.5" - switch $and$ls180.v:7584$2439_Y - attribute \src "ls180.v:7584.6-7584.191" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7585$2440_Y - case - end - attribute \src "ls180.v:7587.2-7589.5" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7587.6-7587.58" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7588$2441_Y - case - end - attribute \src "ls180.v:7590.2-7598.5" - switch $and$ls180.v:7590$2444_Y - attribute \src "ls180.v:7590.6-7590.191" - case 1'1 - attribute \src "ls180.v:7591.3-7593.6" - switch $not$ls180.v:7591$2445_Y - attribute \src "ls180.v:7591.7-7591.62" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7592$2446_Y - case - end - attribute \src "ls180.v:7594.6-7594.10" - case - attribute \src "ls180.v:7595.3-7597.6" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7595.7-7595.59" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7596$2447_Y - case - end - end - attribute \src "ls180.v:7599.2-7605.5" - switch $or$ls180.v:7599$2449_Y - attribute \src "ls180.v:7599.6-7599.108" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr - case - end - attribute \src "ls180.v:7606.2-7620.5" - switch \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:7606.6-7606.43" - case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7608.3-7612.6" - switch 1'0 - attribute \src "ls180.v:7610.7-7610.11" - case - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 - end - attribute \src "ls180.v:7613.6-7613.10" - case - attribute \src "ls180.v:7614.3-7619.6" - switch $not$ls180.v:7614$2450_Y - attribute \src "ls180.v:7614.7-7614.47" - case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7615$2451_Y - attribute \src "ls180.v:7616.4-7618.7" - switch $eq$ls180.v:7616$2452_Y - attribute \src "ls180.v:7616.8-7616.55" - case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:7622.2-7629.5" - switch \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:7622.6-7622.39" - case 1'1 - assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 - attribute \src "ls180.v:7624.6-7624.10" - case - attribute \src "ls180.v:7625.3-7628.6" - switch \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:7625.7-7625.39" - case 1'1 - assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - case - end - end - attribute \src "ls180.v:7630.2-7632.5" - switch $and$ls180.v:7630$2455_Y - attribute \src "ls180.v:7630.6-7630.191" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7631$2456_Y - case - end - attribute \src "ls180.v:7633.2-7635.5" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7633.6-7633.58" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7634$2457_Y - case - end - attribute \src "ls180.v:7636.2-7644.5" - switch $and$ls180.v:7636$2460_Y - attribute \src "ls180.v:7636.6-7636.191" - case 1'1 - attribute \src "ls180.v:7637.3-7639.6" - switch $not$ls180.v:7637$2461_Y - attribute \src "ls180.v:7637.7-7637.62" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7638$2462_Y - case - end - attribute \src "ls180.v:7640.6-7640.10" - case - attribute \src "ls180.v:7641.3-7643.6" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7641.7-7641.59" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7642$2463_Y - case - end - end - attribute \src "ls180.v:7645.2-7651.5" - switch $or$ls180.v:7645$2465_Y - attribute \src "ls180.v:7645.6-7645.108" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr - case - end - attribute \src "ls180.v:7652.2-7666.5" - switch \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:7652.6-7652.43" - case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7654.3-7658.6" - switch 1'0 - attribute \src "ls180.v:7656.7-7656.11" - case - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 - end - attribute \src "ls180.v:7659.6-7659.10" - case - attribute \src "ls180.v:7660.3-7665.6" - switch $not$ls180.v:7660$2466_Y - attribute \src "ls180.v:7660.7-7660.47" - case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7661$2467_Y - attribute \src "ls180.v:7662.4-7664.7" - switch $eq$ls180.v:7662$2468_Y - attribute \src "ls180.v:7662.8-7662.55" - case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:7668.2-7675.5" - switch \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:7668.6-7668.39" - case 1'1 - assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 - attribute \src "ls180.v:7670.6-7670.10" - case - attribute \src "ls180.v:7671.3-7674.6" - switch \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:7671.7-7671.39" - case 1'1 - assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - case - end - end - attribute \src "ls180.v:7676.2-7678.5" - switch $and$ls180.v:7676$2471_Y - attribute \src "ls180.v:7676.6-7676.191" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7677$2472_Y - case - end - attribute \src "ls180.v:7679.2-7681.5" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7679.6-7679.58" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7680$2473_Y - case - end - attribute \src "ls180.v:7682.2-7690.5" - switch $and$ls180.v:7682$2476_Y - attribute \src "ls180.v:7682.6-7682.191" - case 1'1 - attribute \src "ls180.v:7683.3-7685.6" - switch $not$ls180.v:7683$2477_Y - attribute \src "ls180.v:7683.7-7683.62" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7684$2478_Y - case - end - attribute \src "ls180.v:7686.6-7686.10" - case - attribute \src "ls180.v:7687.3-7689.6" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7687.7-7687.59" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7688$2479_Y - case - end - end - attribute \src "ls180.v:7691.2-7697.5" - switch $or$ls180.v:7691$2481_Y - attribute \src "ls180.v:7691.6-7691.108" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr - case - end - attribute \src "ls180.v:7698.2-7712.5" - switch \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:7698.6-7698.43" - case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7700.3-7704.6" - switch 1'0 - attribute \src "ls180.v:7702.7-7702.11" - case - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 - end - attribute \src "ls180.v:7705.6-7705.10" - case - attribute \src "ls180.v:7706.3-7711.6" - switch $not$ls180.v:7706$2482_Y - attribute \src "ls180.v:7706.7-7706.47" - case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7707$2483_Y - attribute \src "ls180.v:7708.4-7710.7" - switch $eq$ls180.v:7708$2484_Y - attribute \src "ls180.v:7708.8-7708.55" - case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:7714.2-7721.5" - switch \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:7714.6-7714.39" - case 1'1 - assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 - attribute \src "ls180.v:7716.6-7716.10" - case - attribute \src "ls180.v:7717.3-7720.6" - switch \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:7717.7-7717.39" - case 1'1 - assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - case - end - end - attribute \src "ls180.v:7722.2-7724.5" - switch $and$ls180.v:7722$2487_Y - attribute \src "ls180.v:7722.6-7722.191" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7723$2488_Y - case - end - attribute \src "ls180.v:7725.2-7727.5" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7725.6-7725.58" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7726$2489_Y - case - end - attribute \src "ls180.v:7728.2-7736.5" - switch $and$ls180.v:7728$2492_Y - attribute \src "ls180.v:7728.6-7728.191" - case 1'1 - attribute \src "ls180.v:7729.3-7731.6" - switch $not$ls180.v:7729$2493_Y - attribute \src "ls180.v:7729.7-7729.62" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7730$2494_Y - case - end - attribute \src "ls180.v:7732.6-7732.10" - case - attribute \src "ls180.v:7733.3-7735.6" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7733.7-7733.59" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7734$2495_Y - case - end - end - attribute \src "ls180.v:7737.2-7743.5" - switch $or$ls180.v:7737$2497_Y - attribute \src "ls180.v:7737.6-7737.108" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr - case - end - attribute \src "ls180.v:7744.2-7758.5" - switch \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:7744.6-7744.43" - case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7746.3-7750.6" - switch 1'0 - attribute \src "ls180.v:7748.7-7748.11" - case - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 - end - attribute \src "ls180.v:7751.6-7751.10" - case - attribute \src "ls180.v:7752.3-7757.6" - switch $not$ls180.v:7752$2498_Y - attribute \src "ls180.v:7752.7-7752.47" - case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7753$2499_Y - attribute \src "ls180.v:7754.4-7756.7" - switch $eq$ls180.v:7754$2500_Y - attribute \src "ls180.v:7754.8-7754.55" - case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:7760.2-7766.5" - switch $not$ls180.v:7760$2501_Y - attribute \src "ls180.v:7760.6-7760.23" - case 1'1 - assign $0\main_sdram_time0[4:0] 5'11111 - attribute \src "ls180.v:7762.6-7762.10" - case - attribute \src "ls180.v:7763.3-7765.6" - switch $not$ls180.v:7763$2502_Y - attribute \src "ls180.v:7763.7-7763.30" - case 1'1 - assign $0\main_sdram_time0[4:0] $sub$ls180.v:7764$2503_Y - case - end - end - attribute \src "ls180.v:7767.2-7773.5" - switch $not$ls180.v:7767$2504_Y - attribute \src "ls180.v:7767.6-7767.23" - case 1'1 - assign $0\main_sdram_time1[3:0] 4'1111 - attribute \src "ls180.v:7769.6-7769.10" - case - attribute \src "ls180.v:7770.3-7772.6" - switch $not$ls180.v:7770$2505_Y - attribute \src "ls180.v:7770.7-7770.30" - case 1'1 - assign $0\main_sdram_time1[3:0] $sub$ls180.v:7771$2506_Y - case - end - end - attribute \src "ls180.v:7774.2-7829.5" - switch \main_sdram_choose_cmd_ce - attribute \src "ls180.v:7774.6-7774.30" - case 1'1 - attribute \src "ls180.v:7775.3-7828.10" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - attribute \src "ls180.v:7777.5-7787.8" - switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7777.9-7777.41" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:7779.9-7779.13" - case - attribute \src "ls180.v:7780.6-7786.9" - switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7780.10-7780.42" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:7782.10-7782.14" - case - attribute \src "ls180.v:7783.7-7785.10" - switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7783.11-7783.43" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'01 - attribute \src "ls180.v:7790.5-7800.8" - switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7790.9-7790.41" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:7792.9-7792.13" - case - attribute \src "ls180.v:7793.6-7799.9" - switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7793.10-7793.42" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:7795.10-7795.14" - case - attribute \src "ls180.v:7796.7-7798.10" - switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7796.11-7796.43" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - attribute \src "ls180.v:7803.5-7813.8" - switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7803.9-7803.41" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:7805.9-7805.13" - case - attribute \src "ls180.v:7806.6-7812.9" - switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7806.10-7806.42" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:7808.10-7808.14" - case - attribute \src "ls180.v:7809.7-7811.10" - switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7809.11-7809.43" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - attribute \src "ls180.v:7816.5-7826.8" - switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7816.9-7816.41" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:7818.9-7818.13" - case - attribute \src "ls180.v:7819.6-7825.9" - switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7819.10-7819.42" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:7821.10-7821.14" - case - attribute \src "ls180.v:7822.7-7824.10" - switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7822.11-7822.43" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - case - end - end - end - case - end - case - end - attribute \src "ls180.v:7830.2-7885.5" - switch \main_sdram_choose_req_ce - attribute \src "ls180.v:7830.6-7830.30" - case 1'1 - attribute \src "ls180.v:7831.3-7884.10" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - attribute \src "ls180.v:7833.5-7843.8" - switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7833.9-7833.41" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:7835.9-7835.13" - case - attribute \src "ls180.v:7836.6-7842.9" - switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7836.10-7836.42" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:7838.10-7838.14" - case - attribute \src "ls180.v:7839.7-7841.10" - switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7839.11-7839.43" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'11 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'01 - attribute \src "ls180.v:7846.5-7856.8" - switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7846.9-7846.41" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:7848.9-7848.13" - case - attribute \src "ls180.v:7849.6-7855.9" - switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7849.10-7849.42" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:7851.10-7851.14" - case - attribute \src "ls180.v:7852.7-7854.10" - switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7852.11-7852.43" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - attribute \src "ls180.v:7859.5-7869.8" - switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7859.9-7859.41" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:7861.9-7861.13" - case - attribute \src "ls180.v:7862.6-7868.9" - switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7862.10-7862.42" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:7864.10-7864.14" - case - attribute \src "ls180.v:7865.7-7867.10" - switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7865.11-7865.43" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'01 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - attribute \src "ls180.v:7872.5-7882.8" - switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7872.9-7872.41" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:7874.9-7874.13" - case - attribute \src "ls180.v:7875.6-7881.9" - switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7875.10-7875.42" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:7877.10-7877.14" - case - attribute \src "ls180.v:7878.7-7880.10" - switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7878.11-7878.43" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'10 - case - end - end - end - case - end - case - end - attribute \src "ls180.v:7894.2-7908.5" - switch \main_sdram_tccdcon_valid - attribute \src "ls180.v:7894.6-7894.30" - case 1'1 - assign $0\main_sdram_tccdcon_count[0:0] 1'0 - attribute \src "ls180.v:7896.3-7900.6" - switch 1'1 - attribute \src "ls180.v:7896.7-7896.11" - case 1'1 - assign $0\main_sdram_tccdcon_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:7901.6-7901.10" - case - attribute \src "ls180.v:7902.3-7907.6" - switch $not$ls180.v:7902$2510_Y - attribute \src "ls180.v:7902.7-7902.34" - case 1'1 - assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7903$2511_Y - attribute \src "ls180.v:7904.4-7906.7" - switch $eq$ls180.v:7904$2512_Y - attribute \src "ls180.v:7904.8-7904.42" - case 1'1 - assign $0\main_sdram_tccdcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:7909.2-7923.5" - switch \main_sdram_twtrcon_valid - attribute \src "ls180.v:7909.6-7909.30" - case 1'1 - assign $0\main_sdram_twtrcon_count[2:0] 3'100 - attribute \src "ls180.v:7911.3-7915.6" - switch 1'0 - attribute \src "ls180.v:7913.7-7913.11" - case - assign $0\main_sdram_twtrcon_ready[0:0] 1'0 - end - attribute \src "ls180.v:7916.6-7916.10" - case - attribute \src "ls180.v:7917.3-7922.6" - switch $not$ls180.v:7917$2513_Y - attribute \src "ls180.v:7917.7-7917.34" - case 1'1 - assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:7918$2514_Y - attribute \src "ls180.v:7919.4-7921.7" - switch $eq$ls180.v:7919$2515_Y - attribute \src "ls180.v:7919.8-7919.42" - case 1'1 - assign $0\main_sdram_twtrcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:7930.2-7932.5" - switch $or$ls180.v:7930$2540_Y - attribute \src "ls180.v:7930.6-7930.50" - case 1'1 - assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r - case - end - attribute \src "ls180.v:7934.2-7936.5" - switch \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:7934.6-7934.52" - case 1'1 - assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value - case - end - attribute \src "ls180.v:7937.2-7940.5" - switch \main_converter_reset - attribute \src "ls180.v:7937.6-7937.26" - case 1'1 - assign $0\main_converter_counter[0:0] 1'0 - assign $0\builder_converter_state[0:0] 1'0 - case - end - attribute \src "ls180.v:7941.2-7951.5" - switch \main_litedram_wb_ack - attribute \src "ls180.v:7941.6-7941.26" - case 1'1 - assign $0\main_cmd_consumed[0:0] 1'0 - assign $0\main_wdata_consumed[0:0] 1'0 - attribute \src "ls180.v:7944.6-7944.10" - case - attribute \src "ls180.v:7945.3-7947.6" - switch $and$ls180.v:7945$2541_Y - attribute \src "ls180.v:7945.7-7945.50" - case 1'1 - assign $0\main_cmd_consumed[0:0] 1'1 - case - end - attribute \src "ls180.v:7948.3-7950.6" - switch $and$ls180.v:7948$2542_Y - attribute \src "ls180.v:7948.7-7948.54" - case 1'1 - assign $0\main_wdata_consumed[0:0] 1'1 - case - end - end - attribute \src "ls180.v:7953.2-7974.5" - switch $and$ls180.v:7953$2546_Y - attribute \src "ls180.v:7953.6-7953.91" - case 1'1 - assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data - assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000 - assign $0\main_uart_phy_tx_busy[0:0] 1'1 - assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'0 - attribute \src "ls180.v:7958.6-7958.10" - case - attribute \src "ls180.v:7959.3-7973.6" - switch $and$ls180.v:7959$2547_Y - attribute \src "ls180.v:7959.7-7959.60" - case 1'1 - assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:7960$2548_Y - attribute \src "ls180.v:7961.4-7972.7" - switch $eq$ls180.v:7961$2549_Y - attribute \src "ls180.v:7961.8-7961.43" - case 1'1 - assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 - attribute \src "ls180.v:7963.8-7963.12" - case - attribute \src "ls180.v:7964.5-7971.8" - switch $eq$ls180.v:7964$2550_Y - attribute \src "ls180.v:7964.9-7964.44" - case 1'1 - assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 - assign $0\main_uart_phy_tx_busy[0:0] 1'0 - assign $0\main_uart_phy_sink_ready[0:0] 1'1 - attribute \src "ls180.v:7968.9-7968.13" - case - assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] \main_uart_phy_tx_reg [0] - assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] } - end - end - case - end - end - attribute \src "ls180.v:7975.2-7979.5" - switch \main_uart_phy_tx_busy - attribute \src "ls180.v:7975.6-7975.27" - case 1'1 - assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:7976$2551_Y - attribute \src "ls180.v:7977.6-7977.10" - case - assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage } - end - attribute \src "ls180.v:7982.2-8006.5" - switch $not$ls180.v:7982$2552_Y - attribute \src "ls180.v:7982.6-7982.30" - case 1'1 - attribute \src "ls180.v:7983.3-7986.6" - switch $and$ls180.v:7983$2554_Y - attribute \src "ls180.v:7983.7-7983.49" - case 1'1 - assign $0\main_uart_phy_rx_busy[0:0] 1'1 - assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000 - case - end - attribute \src "ls180.v:7987.6-7987.10" - case - attribute \src "ls180.v:7988.3-8005.6" - switch \main_uart_phy_uart_clk_rxen - attribute \src "ls180.v:7988.7-7988.34" - case 1'1 - assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:7989$2555_Y - attribute \src "ls180.v:7990.4-8004.7" - switch $eq$ls180.v:7990$2556_Y - attribute \src "ls180.v:7990.8-7990.43" - case 1'1 - attribute \src "ls180.v:7991.5-7993.8" - switch \main_uart_phy_rx - attribute \src "ls180.v:7991.9-7991.25" - case 1'1 - assign $0\main_uart_phy_rx_busy[0:0] 1'0 - case - end - attribute \src "ls180.v:7994.8-7994.12" - case - attribute \src "ls180.v:7995.5-8003.8" - switch $eq$ls180.v:7995$2557_Y - attribute \src "ls180.v:7995.9-7995.44" - case 1'1 - assign $0\main_uart_phy_rx_busy[0:0] 1'0 - attribute \src "ls180.v:7997.6-8000.9" - switch \main_uart_phy_rx - attribute \src "ls180.v:7997.10-7997.26" - case 1'1 - assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg - assign $0\main_uart_phy_source_valid[0:0] 1'1 - case - end - attribute \src "ls180.v:8001.9-8001.13" - case - assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] } - end - end - case - end - end - attribute \src "ls180.v:8007.2-8011.5" - switch \main_uart_phy_rx_busy - attribute \src "ls180.v:8007.6-8007.27" - case 1'1 - assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8008$2558_Y - attribute \src "ls180.v:8009.6-8009.10" - case - assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 - end - attribute \src "ls180.v:8012.2-8014.5" - switch \main_uart_tx_clear - attribute \src "ls180.v:8012.6-8012.24" - case 1'1 - assign $0\main_uart_tx_pending[0:0] 1'0 - case - end - attribute \src "ls180.v:8016.2-8018.5" - switch $and$ls180.v:8016$2560_Y - attribute \src "ls180.v:8016.6-8016.58" - case 1'1 - assign $0\main_uart_tx_pending[0:0] 1'1 - case - end - attribute \src "ls180.v:8019.2-8021.5" - switch \main_uart_rx_clear - attribute \src "ls180.v:8019.6-8019.24" - case 1'1 - assign $0\main_uart_rx_pending[0:0] 1'0 - case - end - attribute \src "ls180.v:8023.2-8025.5" - switch $and$ls180.v:8023$2562_Y - attribute \src "ls180.v:8023.6-8023.58" - case 1'1 - assign $0\main_uart_rx_pending[0:0] 1'1 - case - end - attribute \src "ls180.v:8026.2-8032.5" - switch \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:8026.6-8026.35" - case 1'1 - assign $0\main_uart_tx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8028.6-8028.10" - case - attribute \src "ls180.v:8029.3-8031.6" - switch \main_uart_tx_fifo_re - attribute \src "ls180.v:8029.7-8029.27" - case 1'1 - assign $0\main_uart_tx_fifo_readable[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8033.2-8035.5" - switch $and$ls180.v:8033$2565_Y - attribute \src "ls180.v:8033.6-8033.108" - case 1'1 - assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8034$2566_Y - case - end - attribute \src "ls180.v:8036.2-8038.5" - switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:8036.6-8036.31" - case 1'1 - assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8037$2567_Y - case - end - attribute \src "ls180.v:8039.2-8047.5" - switch $and$ls180.v:8039$2570_Y - attribute \src "ls180.v:8039.6-8039.108" - case 1'1 - attribute \src "ls180.v:8040.3-8042.6" - switch $not$ls180.v:8040$2571_Y - attribute \src "ls180.v:8040.7-8040.35" - case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8041$2572_Y - case - end - attribute \src "ls180.v:8043.6-8043.10" - case - attribute \src "ls180.v:8044.3-8046.6" - switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:8044.7-8044.32" - case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8045$2573_Y - case - end - end - attribute \src "ls180.v:8048.2-8054.5" - switch \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:8048.6-8048.35" - case 1'1 - assign $0\main_uart_rx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8050.6-8050.10" - case - attribute \src "ls180.v:8051.3-8053.6" - switch \main_uart_rx_fifo_re - attribute \src "ls180.v:8051.7-8051.27" - case 1'1 - assign $0\main_uart_rx_fifo_readable[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8055.2-8057.5" - switch $and$ls180.v:8055$2576_Y - attribute \src "ls180.v:8055.6-8055.108" - case 1'1 - assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8056$2577_Y - case - end - attribute \src "ls180.v:8058.2-8060.5" - switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8058.6-8058.31" - case 1'1 - assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8059$2578_Y - case - end - attribute \src "ls180.v:8061.2-8069.5" - switch $and$ls180.v:8061$2581_Y - attribute \src "ls180.v:8061.6-8061.108" - case 1'1 - attribute \src "ls180.v:8062.3-8064.6" - switch $not$ls180.v:8062$2582_Y - attribute \src "ls180.v:8062.7-8062.35" - case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8063$2583_Y - case - end - attribute \src "ls180.v:8065.6-8065.10" - case - attribute \src "ls180.v:8066.3-8068.6" - switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8066.7-8066.32" - case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8067$2584_Y - case - end - end - attribute \src "ls180.v:8070.2-8083.5" - switch \main_uart_reset - attribute \src "ls180.v:8070.6-8070.21" - case 1'1 - assign $0\main_uart_tx_pending[0:0] 1'0 - assign $0\main_uart_tx_old_trigger[0:0] 1'0 - assign $0\main_uart_rx_pending[0:0] 1'0 - assign $0\main_uart_rx_old_trigger[0:0] 1'0 - assign $0\main_uart_tx_fifo_readable[0:0] 1'0 - assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 - assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 - assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 - assign $0\main_uart_rx_fifo_readable[0:0] 1'0 - assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 - assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 - assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 - case - end - attribute \src "ls180.v:8085.2-8092.5" - switch \main_spi_master_clk_rise - attribute \src "ls180.v:8085.6-8085.30" - case 1'1 - assign $0\spi_master_clk[0:0] \main_spi_master_clk_enable - attribute \src "ls180.v:8087.6-8087.10" - case - attribute \src "ls180.v:8088.3-8091.6" - switch \main_spi_master_clk_fall - attribute \src "ls180.v:8088.7-8088.31" - case 1'1 - assign $0\main_spi_master_clk_divider1[15:0] 16'0000000000000000 - assign $0\spi_master_clk[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8094.2-8104.5" - switch \main_spi_master_mosi_latch - attribute \src "ls180.v:8094.6-8094.32" - case 1'1 - assign $0\main_spi_master_mosi_data[7:0] \main_spi_master_mosi - assign $0\main_spi_master_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8097.6-8097.10" - case - attribute \src "ls180.v:8098.3-8103.6" - switch \main_spi_master_clk_fall - attribute \src "ls180.v:8098.7-8098.31" - case 1'1 - assign $0\main_spi_master_mosi_sel[2:0] $sub$ls180.v:8102$2589_Y - attribute \src "ls180.v:8099.4-8101.7" - switch \main_spi_master_cs_enable - attribute \src "ls180.v:8099.8-8099.33" - case 1'1 - assign $0\spi_master_mosi[0:0] \builder_sync_f_array_muxed0 - case - end - case - end - end - attribute \src "ls180.v:8105.2-8111.5" - switch \main_spi_master_clk_rise - attribute \src "ls180.v:8105.6-8105.30" - case 1'1 - attribute \src "ls180.v:8106.3-8110.6" - switch \main_spi_master_loopback - attribute \src "ls180.v:8106.7-8106.31" - case 1'1 - assign $0\main_spi_master_miso_data[7:0] { \main_spi_master_miso_data [6:0] \spi_master_mosi } - attribute \src "ls180.v:8108.7-8108.11" - case - assign $0\main_spi_master_miso_data[7:0] { \main_spi_master_miso_data [6:0] \spi_master_miso } - end - case - end - attribute \src "ls180.v:8112.2-8114.5" - switch \main_spi_master_miso_latch - attribute \src "ls180.v:8112.6-8112.32" - case 1'1 - assign $0\main_spi_master_miso[7:0] \main_spi_master_miso_data - case - end - attribute \src "ls180.v:8116.2-8118.5" - switch \main_spi_master_count_spimaster0_next_value_ce - attribute \src "ls180.v:8116.6-8116.52" - case 1'1 - assign $0\main_spi_master_count[2:0] \main_spi_master_count_spimaster0_next_value - case - end - attribute \src "ls180.v:8119.2-8132.5" - switch \main_pwm0_enable - attribute \src "ls180.v:8119.6-8119.22" - case 1'1 - assign $0\main_pwm0_counter[31:0] $add$ls180.v:8120$2590_Y - attribute \src "ls180.v:8121.3-8125.6" - switch $lt$ls180.v:8121$2591_Y - attribute \src "ls180.v:8121.7-8121.44" - case 1'1 - assign $0\pwm0[0:0] 1'1 - attribute \src "ls180.v:8123.7-8123.11" - case - assign $0\pwm0[0:0] 1'0 - end - attribute \src "ls180.v:8126.3-8128.6" - switch $ge$ls180.v:8126$2593_Y - attribute \src "ls180.v:8126.7-8126.55" - case 1'1 - assign $0\main_pwm0_counter[31:0] 0 - case - end - attribute \src "ls180.v:8129.6-8129.10" - case - assign $0\main_pwm0_counter[31:0] 0 - assign $0\pwm0[0:0] 1'0 - end - attribute \src "ls180.v:8133.2-8146.5" - switch \main_pwm1_enable - attribute \src "ls180.v:8133.6-8133.22" - case 1'1 - assign $0\main_pwm1_counter[31:0] $add$ls180.v:8134$2594_Y - attribute \src "ls180.v:8135.3-8139.6" - switch $lt$ls180.v:8135$2595_Y - attribute \src "ls180.v:8135.7-8135.44" - case 1'1 - assign $0\pwm1[0:0] 1'1 - attribute \src "ls180.v:8137.7-8137.11" - case - assign $0\pwm1[0:0] 1'0 - end - attribute \src "ls180.v:8140.3-8142.6" - switch $ge$ls180.v:8140$2597_Y - attribute \src "ls180.v:8140.7-8140.55" - case 1'1 - assign $0\main_pwm1_counter[31:0] 0 - case - end - attribute \src "ls180.v:8143.6-8143.10" - case - assign $0\main_pwm1_counter[31:0] 0 - assign $0\pwm1[0:0] 1'0 - end - attribute \src "ls180.v:8147.2-8149.5" - switch $not$ls180.v:8147$2598_Y - attribute \src "ls180.v:8147.6-8147.32" - case 1'1 - assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8148$2599_Y - case - end - attribute \src "ls180.v:8153.2-8155.5" - switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:8153.6-8153.57" - case 1'1 - assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value - case - end - attribute \src "ls180.v:8157.2-8159.5" - switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:8157.6-8157.57" - case 1'1 - assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value - case - end - attribute \src "ls180.v:8160.2-8162.5" - switch \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:8160.6-8160.40" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8161$2600_Y - case - end - attribute \src "ls180.v:8163.2-8165.5" - switch \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:8163.6-8163.49" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:8166.2-8173.5" - switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8166.6-8166.46" - case 1'1 - attribute \src "ls180.v:8167.3-8172.6" - switch $or$ls180.v:8167$2602_Y - attribute \src "ls180.v:8167.7-8167.98" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8170.7-8170.11" - case - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8171$2603_Y - end - case - end - attribute \src "ls180.v:8174.2-8187.5" - switch $and$ls180.v:8174$2604_Y - attribute \src "ls180.v:8174.6-8174.97" - case 1'1 - attribute \src "ls180.v:8175.3-8181.6" - switch $and$ls180.v:8175$2605_Y - attribute \src "ls180.v:8175.7-8175.94" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:8178.7-8178.11" - case - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:8182.6-8182.10" - case - attribute \src "ls180.v:8183.3-8186.6" - switch $and$ls180.v:8183$2606_Y - attribute \src "ls180.v:8183.7-8183.94" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8184$2607_Y - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8185$2608_Y - case - end - end - attribute \src "ls180.v:8188.2-8215.5" - switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8188.6-8188.46" - case 1'1 - attribute \src "ls180.v:8189.3-8214.10" - switch \main_sdphy_cmdr_cmdr_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [7] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [6] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [5] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [4] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [3] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [2] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [1] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [0] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:8216.2-8218.5" - switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8216.6-8216.46" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8217$2609_Y - case - end - attribute \src "ls180.v:8219.2-8224.5" - switch $or$ls180.v:8219$2611_Y - attribute \src "ls180.v:8219.6-8219.88" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid - assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first - assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_sink_last - assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data - case - end - attribute \src "ls180.v:8225.2-8230.5" - switch \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:8225.6-8225.32" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 - case - end - attribute \src "ls180.v:8232.2-8234.5" - switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:8232.6-8232.58" - case 1'1 - assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 - case - end - attribute \src "ls180.v:8235.2-8237.5" - switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:8235.6-8235.60" - case 1'1 - assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 - case - end - attribute \src "ls180.v:8238.2-8240.5" - switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:8238.6-8238.63" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 - case - end - attribute \src "ls180.v:8241.2-8243.5" - switch \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:8241.6-8241.41" - case 1'1 - assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8242$2612_Y - case - end - attribute \src "ls180.v:8244.2-8246.5" - switch \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:8244.6-8244.50" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:8247.2-8254.5" - switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8247.6-8247.47" - case 1'1 - attribute \src "ls180.v:8248.3-8253.6" - switch $or$ls180.v:8248$2614_Y - attribute \src "ls180.v:8248.7-8248.100" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8251.7-8251.11" - case - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8252$2615_Y - end - case - end - attribute \src "ls180.v:8255.2-8268.5" - switch $and$ls180.v:8255$2616_Y - attribute \src "ls180.v:8255.6-8255.99" - case 1'1 - attribute \src "ls180.v:8256.3-8262.6" - switch $and$ls180.v:8256$2617_Y - attribute \src "ls180.v:8256.7-8256.96" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:8259.7-8259.11" - case - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:8263.6-8263.10" - case - attribute \src "ls180.v:8264.3-8267.6" - switch $and$ls180.v:8264$2618_Y - attribute \src "ls180.v:8264.7-8264.96" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8265$2619_Y - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8266$2620_Y - case - end - end - attribute \src "ls180.v:8269.2-8296.5" - switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8269.6-8269.47" - case 1'1 - attribute \src "ls180.v:8270.3-8295.10" - switch \main_sdphy_dataw_crcr_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [7] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [6] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [5] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [4] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [3] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [2] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [1] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [0] \main_sdphy_dataw_crcr_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:8297.2-8299.5" - switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8297.6-8297.47" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8298$2621_Y - case - end - attribute \src "ls180.v:8300.2-8305.5" - switch $or$ls180.v:8300$2623_Y - attribute \src "ls180.v:8300.6-8300.90" - case 1'1 - assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid - assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first - assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_sink_last - assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data - case - end - attribute \src "ls180.v:8306.2-8311.5" - switch \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:8306.6-8306.33" - case 1'1 - assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 - case - end - attribute \src "ls180.v:8313.2-8315.5" - switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:8313.6-8313.63" - case 1'1 - assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value - case - end - attribute \src "ls180.v:8317.2-8319.5" - switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:8317.6-8317.52" - case 1'1 - assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value - case - end - attribute \src "ls180.v:8320.2-8322.5" - switch \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:8320.6-8320.42" - case 1'1 - assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8321$2624_Y - case - end - attribute \src "ls180.v:8323.2-8325.5" - switch \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:8323.6-8323.51" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:8326.2-8333.5" - switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8326.6-8326.48" - case 1'1 - attribute \src "ls180.v:8327.3-8332.6" - switch $or$ls180.v:8327$2626_Y - attribute \src "ls180.v:8327.7-8327.102" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8330.7-8330.11" - case - assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8331$2627_Y - end - case - end - attribute \src "ls180.v:8334.2-8347.5" - switch $and$ls180.v:8334$2628_Y - attribute \src "ls180.v:8334.6-8334.101" - case 1'1 - attribute \src "ls180.v:8335.3-8341.6" - switch $and$ls180.v:8335$2629_Y - attribute \src "ls180.v:8335.7-8335.98" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:8338.7-8338.11" - case - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:8342.6-8342.10" - case - attribute \src "ls180.v:8343.3-8346.6" - switch $and$ls180.v:8343$2630_Y - attribute \src "ls180.v:8343.7-8343.98" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8344$2631_Y - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8345$2632_Y - case - end - end - attribute \src "ls180.v:8348.2-8357.5" - switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8348.6-8348.48" - case 1'1 - attribute \src "ls180.v:8349.3-8356.10" - switch \main_sdphy_datar_datar_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [7:4] \main_sdphy_datar_datar_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [3:0] \main_sdphy_datar_datar_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:8358.2-8360.5" - switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8358.6-8358.48" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8359$2633_Y - case - end - attribute \src "ls180.v:8361.2-8366.5" - switch $or$ls180.v:8361$2635_Y - attribute \src "ls180.v:8361.6-8361.92" - case 1'1 - assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid - assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first - assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_sink_last - assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data - case - end - attribute \src "ls180.v:8367.2-8372.5" - switch \main_sdphy_datar_datar_reset - attribute \src "ls180.v:8367.6-8367.34" - case 1'1 - assign $0\main_sdphy_datar_datar_run[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 - case - end - attribute \src "ls180.v:8374.2-8376.5" - switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:8374.6-8374.60" - case 1'1 - assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 - case - end - attribute \src "ls180.v:8377.2-8379.5" - switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:8377.6-8377.62" - case 1'1 - assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 - case - end - attribute \src "ls180.v:8380.2-8382.5" - switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:8380.6-8380.66" - case 1'1 - assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 - case - end - attribute \src "ls180.v:8383.2-8389.5" - switch \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:8383.6-8383.35" - case 1'1 - assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - attribute \src "ls180.v:8385.6-8385.10" - case - attribute \src "ls180.v:8386.3-8388.6" - switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:8386.7-8386.39" - case 1'1 - assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40 - case - end - end - attribute \src "ls180.v:8390.2-8396.5" - switch \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:8390.6-8390.41" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8392.6-8392.10" - case - attribute \src "ls180.v:8393.3-8395.6" - switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:8393.7-8393.45" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 - case - end - end - attribute \src "ls180.v:8397.2-8403.5" - switch \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:8397.6-8397.41" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8399.6-8399.10" - case - attribute \src "ls180.v:8400.3-8402.6" - switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:8400.7-8400.45" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 - case - end - end - attribute \src "ls180.v:8404.2-8410.5" - switch \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:8404.6-8404.41" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8406.6-8406.10" - case - attribute \src "ls180.v:8407.3-8409.6" - switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:8407.7-8407.45" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 - case - end - end - attribute \src "ls180.v:8411.2-8417.5" - switch \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:8411.6-8411.41" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8413.6-8413.10" - case - attribute \src "ls180.v:8414.3-8416.6" - switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:8414.7-8414.45" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 - case - end - end - attribute \src "ls180.v:8419.2-8421.5" - switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:8419.6-8419.82" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 - case - end - attribute \src "ls180.v:8422.2-8424.5" - switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:8422.6-8422.82" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 - case - end - attribute \src "ls180.v:8425.2-8427.5" - switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:8425.6-8425.82" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 - case - end - attribute \src "ls180.v:8428.2-8430.5" - switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:8428.6-8428.82" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 - case - end - attribute \src "ls180.v:8431.2-8433.5" - switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:8431.6-8431.78" - case 1'1 - assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 - case - end - attribute \src "ls180.v:8434.2-8436.5" - switch $and$ls180.v:8434$2636_Y - attribute \src "ls180.v:8434.6-8434.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc - case - end - attribute \src "ls180.v:8437.2-8439.5" - switch $and$ls180.v:8437$2637_Y - attribute \src "ls180.v:8437.6-8437.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc - case - end - attribute \src "ls180.v:8440.2-8442.5" - switch $and$ls180.v:8440$2638_Y - attribute \src "ls180.v:8440.6-8440.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc - case - end - attribute \src "ls180.v:8443.2-8445.5" - switch $and$ls180.v:8443$2639_Y - attribute \src "ls180.v:8443.6-8443.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc - case - end - attribute \src "ls180.v:8446.2-8450.5" - switch $and$ls180.v:8446$2640_Y - attribute \src "ls180.v:8446.6-8446.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } - assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13] - assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12] - case - end - attribute \src "ls180.v:8451.2-8455.5" - switch $and$ls180.v:8451$2641_Y - attribute \src "ls180.v:8451.6-8451.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } - assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13] - assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12] - case - end - attribute \src "ls180.v:8456.2-8460.5" - switch $and$ls180.v:8456$2642_Y - attribute \src "ls180.v:8456.6-8456.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } - assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13] - assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12] - case - end - attribute \src "ls180.v:8461.2-8465.5" - switch $and$ls180.v:8461$2643_Y - attribute \src "ls180.v:8461.6-8461.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } - assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13] - assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12] - case - end - attribute \src "ls180.v:8466.2-8474.5" - switch $and$ls180.v:8466$2644_Y - attribute \src "ls180.v:8466.6-8466.83" - case 1'1 - attribute \src "ls180.v:8467.3-8473.6" - switch \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:8467.7-8467.42" - case 1'1 - assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - attribute \src "ls180.v:8469.7-8469.11" - case - attribute \src "ls180.v:8470.4-8472.7" - switch $ne$ls180.v:8470$2645_Y - attribute \src "ls180.v:8470.8-8470.48" - case 1'1 - assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8471$2646_Y - case - end - end - case - end - attribute \src "ls180.v:8475.2-8481.5" - switch \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:8475.6-8475.40" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8477.6-8477.10" - case - attribute \src "ls180.v:8478.3-8480.6" - switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:8478.7-8478.44" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 - case - end - end - attribute \src "ls180.v:8482.2-8488.5" - switch \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:8482.6-8482.40" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8484.6-8484.10" - case - attribute \src "ls180.v:8485.3-8487.6" - switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:8485.7-8485.44" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 - case - end - end - attribute \src "ls180.v:8489.2-8495.5" - switch \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:8489.6-8489.40" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8491.6-8491.10" - case - attribute \src "ls180.v:8492.3-8494.6" - switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:8492.7-8492.44" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 - case - end - end - attribute \src "ls180.v:8496.2-8502.5" - switch \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:8496.6-8496.40" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8498.6-8498.10" - case - attribute \src "ls180.v:8499.3-8501.6" - switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:8499.7-8499.44" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 - case - end - end - attribute \src "ls180.v:8504.2-8506.5" - switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:8504.6-8504.52" - case 1'1 - assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0 - case - end - attribute \src "ls180.v:8507.2-8509.5" - switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:8507.6-8507.53" - case 1'1 - assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1 - case - end - attribute \src "ls180.v:8510.2-8512.5" - switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:8510.6-8510.53" - case 1'1 - assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2 - case - end - attribute \src "ls180.v:8513.2-8515.5" - switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:8513.6-8513.54" - case 1'1 - assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3 - case - end - attribute \src "ls180.v:8516.2-8518.5" - switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:8516.6-8516.53" - case 1'1 - assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4 - case - end - attribute \src "ls180.v:8519.2-8521.5" - switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:8519.6-8519.55" - case 1'1 - assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 - case - end - attribute \src "ls180.v:8522.2-8524.5" - switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:8522.6-8522.54" - case 1'1 - assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6 - case - end - attribute \src "ls180.v:8525.2-8527.5" - switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:8525.6-8525.56" - case 1'1 - assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7 - case - end - attribute \src "ls180.v:8528.2-8530.5" - switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:8528.6-8528.63" - case 1'1 - assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 - case - end - attribute \src "ls180.v:8531.2-8533.5" - switch $and$ls180.v:8531$2649_Y - attribute \src "ls180.v:8531.6-8531.120" - case 1'1 - assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8532$2650_Y - case - end - attribute \src "ls180.v:8534.2-8536.5" - switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8534.6-8534.35" - case 1'1 - assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8535$2651_Y - case - end - attribute \src "ls180.v:8537.2-8545.5" - switch $and$ls180.v:8537$2654_Y - attribute \src "ls180.v:8537.6-8537.120" - case 1'1 - attribute \src "ls180.v:8538.3-8540.6" - switch $not$ls180.v:8538$2655_Y - attribute \src "ls180.v:8538.7-8538.39" - case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8539$2656_Y - case - end - attribute \src "ls180.v:8541.6-8541.10" - case - attribute \src "ls180.v:8542.3-8544.6" - switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8542.7-8542.36" - case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8543$2657_Y - case - end - end - attribute \src "ls180.v:8546.2-8548.5" - switch \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:8546.6-8546.45" - case 1'1 - assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:8549.2-8556.5" - switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8549.6-8549.42" - case 1'1 - attribute \src "ls180.v:8550.3-8555.6" - switch $or$ls180.v:8550$2659_Y - attribute \src "ls180.v:8550.7-8550.90" - case 1'1 - assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 - assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8553.7-8553.11" - case - assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8554$2660_Y - end - case - end - attribute \src "ls180.v:8557.2-8570.5" - switch $and$ls180.v:8557$2661_Y - attribute \src "ls180.v:8557.6-8557.89" - case 1'1 - attribute \src "ls180.v:8558.3-8564.6" - switch $and$ls180.v:8558$2662_Y - attribute \src "ls180.v:8558.7-8558.86" - case 1'1 - assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first - assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:8561.7-8561.11" - case - assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0 - assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:8565.6-8565.10" - case - attribute \src "ls180.v:8566.3-8569.6" - switch $and$ls180.v:8566$2663_Y - attribute \src "ls180.v:8566.7-8566.86" - case 1'1 - assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8567$2664_Y - assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8568$2665_Y - case - end - end - attribute \src "ls180.v:8571.2-8586.5" - switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8571.6-8571.42" - case 1'1 - attribute \src "ls180.v:8572.3-8585.10" - switch \main_sdblock2mem_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [31:24] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [23:16] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [15:8] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [7:0] \main_sdblock2mem_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:8587.2-8589.5" - switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8587.6-8587.42" - case 1'1 - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8588$2666_Y - case - end - attribute \src "ls180.v:8591.2-8593.5" - switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:8591.6-8591.76" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value - case - end - attribute \src "ls180.v:8594.2-8597.5" - switch \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:8594.6-8594.46" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 - assign $0\builder_sdblock2memdma_state[1:0] 2'00 - case - end - attribute \src "ls180.v:8599.2-8601.5" - switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:8599.6-8599.64" - case 1'1 - assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value - case - end - attribute \src "ls180.v:8603.2-8605.5" - switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:8603.6-8603.76" - case 1'1 - assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value - case - end - attribute \src "ls180.v:8606.2-8609.5" - switch \main_sdmem2block_dma_reset - attribute \src "ls180.v:8606.6-8606.32" - case 1'1 - assign $0\main_sdmem2block_dma_offset[31:0] 0 - assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 - case - end - attribute \src "ls180.v:8610.2-8616.5" - switch $and$ls180.v:8610$2667_Y - attribute \src "ls180.v:8610.6-8610.89" - case 1'1 - attribute \src "ls180.v:8611.3-8615.6" - switch \main_sdmem2block_converter_last - attribute \src "ls180.v:8611.7-8611.38" - case 1'1 - assign $0\main_sdmem2block_converter_mux[1:0] 2'00 - attribute \src "ls180.v:8613.7-8613.11" - case - assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8614$2668_Y - end - case - end - attribute \src "ls180.v:8617.2-8619.5" - switch $and$ls180.v:8617$2671_Y - attribute \src "ls180.v:8617.6-8617.120" - case 1'1 - assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8618$2672_Y - case - end - attribute \src "ls180.v:8620.2-8622.5" - switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8620.6-8620.35" - case 1'1 - assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8621$2673_Y - case - end - attribute \src "ls180.v:8623.2-8631.5" - switch $and$ls180.v:8623$2676_Y - attribute \src "ls180.v:8623.6-8623.120" - case 1'1 - attribute \src "ls180.v:8624.3-8626.6" - switch $not$ls180.v:8624$2677_Y - attribute \src "ls180.v:8624.7-8624.39" - case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8625$2678_Y - case - end - attribute \src "ls180.v:8627.6-8627.10" - case - attribute \src "ls180.v:8628.3-8630.6" - switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8628.7-8628.36" - case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8629$2679_Y - case - end - end - attribute \src "ls180.v:8633.2-8640.5" - switch \libresocsim_clk_rise - attribute \src "ls180.v:8633.6-8633.26" - case 1'1 - assign $0\spisdcard_clk[0:0] \libresocsim_clk_enable - attribute \src "ls180.v:8635.6-8635.10" - case - attribute \src "ls180.v:8636.3-8639.6" - switch \libresocsim_clk_fall - attribute \src "ls180.v:8636.7-8636.27" - case 1'1 - assign $0\libresocsim_clk_divider1[15:0] 16'0000000000000000 - assign $0\spisdcard_clk[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8642.2-8652.5" - switch \libresocsim_mosi_latch - attribute \src "ls180.v:8642.6-8642.28" - case 1'1 - assign $0\libresocsim_mosi_data[7:0] \libresocsim_mosi - assign $0\libresocsim_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8645.6-8645.10" - case - attribute \src "ls180.v:8646.3-8651.6" - switch \libresocsim_clk_fall - attribute \src "ls180.v:8646.7-8646.27" - case 1'1 - assign $0\libresocsim_mosi_sel[2:0] $sub$ls180.v:8650$2684_Y - attribute \src "ls180.v:8647.4-8649.7" - switch \libresocsim_cs_enable - attribute \src "ls180.v:8647.8-8647.29" - case 1'1 - assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed1 - case - end - case - end - end - attribute \src "ls180.v:8653.2-8659.5" - switch \libresocsim_clk_rise - attribute \src "ls180.v:8653.6-8653.26" - case 1'1 - attribute \src "ls180.v:8654.3-8658.6" - switch \libresocsim_loopback - attribute \src "ls180.v:8654.7-8654.27" - case 1'1 - assign $0\libresocsim_miso_data[7:0] { \libresocsim_miso_data [6:0] \spisdcard_mosi } - attribute \src "ls180.v:8656.7-8656.11" - case - assign $0\libresocsim_miso_data[7:0] { \libresocsim_miso_data [6:0] \spisdcard_miso } - end - case - end - attribute \src "ls180.v:8660.2-8662.5" - switch \libresocsim_miso_latch - attribute \src "ls180.v:8660.6-8660.28" - case 1'1 - assign $0\libresocsim_miso[7:0] \libresocsim_miso_data - case - end - attribute \src "ls180.v:8664.2-8666.5" - switch \libresocsim_count_spimaster1_next_value_ce - attribute \src "ls180.v:8664.6-8664.48" - case 1'1 - assign $0\libresocsim_count[2:0] \libresocsim_count_spimaster1_next_value - case - end - attribute \src "ls180.v:8668.2-8670.5" - switch \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:8668.6-8668.46" - case 1'1 - assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 - case - end - attribute \src "ls180.v:8671.2-8673.5" - switch \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:8671.6-8671.44" - case 1'1 - assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 - case - end - attribute \src "ls180.v:8674.2-8676.5" - switch \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:8674.6-8674.43" - case 1'1 - assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 - case - end - attribute \src "ls180.v:8677.2-8773.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - attribute \src "ls180.v:8679.4-8695.7" - switch $not$ls180.v:8679$2685_Y - attribute \src "ls180.v:8679.8-8679.29" - case 1'1 - attribute \src "ls180.v:8680.5-8694.8" - switch \builder_request [1] - attribute \src "ls180.v:8680.9-8680.27" - case 1'1 - assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8682.9-8682.13" - case - attribute \src "ls180.v:8683.6-8693.9" - switch \builder_request [2] - attribute \src "ls180.v:8683.10-8683.28" - case 1'1 - assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8685.10-8685.14" - case - attribute \src "ls180.v:8686.7-8692.10" - switch \builder_request [3] - attribute \src "ls180.v:8686.11-8686.29" - case 1'1 - assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8688.11-8688.15" - case - attribute \src "ls180.v:8689.8-8691.11" - switch \builder_request [4] - attribute \src "ls180.v:8689.12-8689.30" - case 1'1 - assign $0\builder_grant[2:0] 3'100 - case - end - end - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'001 - attribute \src "ls180.v:8698.4-8714.7" - switch $not$ls180.v:8698$2686_Y - attribute \src "ls180.v:8698.8-8698.29" - case 1'1 - attribute \src "ls180.v:8699.5-8713.8" - switch \builder_request [2] - attribute \src "ls180.v:8699.9-8699.27" - case 1'1 - assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8701.9-8701.13" - case - attribute \src "ls180.v:8702.6-8712.9" - switch \builder_request [3] - attribute \src "ls180.v:8702.10-8702.28" - case 1'1 - assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8704.10-8704.14" - case - attribute \src "ls180.v:8705.7-8711.10" - switch \builder_request [4] - attribute \src "ls180.v:8705.11-8705.29" - case 1'1 - assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8707.11-8707.15" - case - attribute \src "ls180.v:8708.8-8710.11" - switch \builder_request [0] - attribute \src "ls180.v:8708.12-8708.30" - case 1'1 - assign $0\builder_grant[2:0] 3'000 - case - end - end - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - attribute \src "ls180.v:8717.4-8733.7" - switch $not$ls180.v:8717$2687_Y - attribute \src "ls180.v:8717.8-8717.29" - case 1'1 - attribute \src "ls180.v:8718.5-8732.8" - switch \builder_request [3] - attribute \src "ls180.v:8718.9-8718.27" - case 1'1 - assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8720.9-8720.13" - case - attribute \src "ls180.v:8721.6-8731.9" - switch \builder_request [4] - attribute \src "ls180.v:8721.10-8721.28" - case 1'1 - assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8723.10-8723.14" - case - attribute \src "ls180.v:8724.7-8730.10" - switch \builder_request [0] - attribute \src "ls180.v:8724.11-8724.29" - case 1'1 - assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8726.11-8726.15" - case - attribute \src "ls180.v:8727.8-8729.11" - switch \builder_request [1] - attribute \src "ls180.v:8727.12-8727.30" - case 1'1 - assign $0\builder_grant[2:0] 3'001 - case - end - end - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:8736.4-8752.7" - switch $not$ls180.v:8736$2688_Y - attribute \src "ls180.v:8736.8-8736.29" - case 1'1 - attribute \src "ls180.v:8737.5-8751.8" - switch \builder_request [4] - attribute \src "ls180.v:8737.9-8737.27" - case 1'1 - assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8739.9-8739.13" - case - attribute \src "ls180.v:8740.6-8750.9" - switch \builder_request [0] - attribute \src "ls180.v:8740.10-8740.28" - case 1'1 - assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8742.10-8742.14" - case - attribute \src "ls180.v:8743.7-8749.10" - switch \builder_request [1] - attribute \src "ls180.v:8743.11-8743.29" - case 1'1 - assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8745.11-8745.15" - case - attribute \src "ls180.v:8746.8-8748.11" - switch \builder_request [2] - attribute \src "ls180.v:8746.12-8746.30" - case 1'1 - assign $0\builder_grant[2:0] 3'010 - case - end - end - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - attribute \src "ls180.v:8755.4-8771.7" - switch $not$ls180.v:8755$2689_Y - attribute \src "ls180.v:8755.8-8755.29" - case 1'1 - attribute \src "ls180.v:8756.5-8770.8" - switch \builder_request [0] - attribute \src "ls180.v:8756.9-8756.27" - case 1'1 - assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8758.9-8758.13" - case - attribute \src "ls180.v:8759.6-8769.9" - switch \builder_request [1] - attribute \src "ls180.v:8759.10-8759.28" - case 1'1 - assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8761.10-8761.14" - case - attribute \src "ls180.v:8762.7-8768.10" - switch \builder_request [2] - attribute \src "ls180.v:8762.11-8762.29" - case 1'1 - assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8764.11-8764.15" - case - attribute \src "ls180.v:8765.8-8767.11" - switch \builder_request [3] - attribute \src "ls180.v:8765.12-8765.30" - case 1'1 - assign $0\builder_grant[2:0] 3'011 - case - end - end - end - end - case - end - case - end - attribute \src "ls180.v:8775.2-8781.5" - switch \builder_wait - attribute \src "ls180.v:8775.6-8775.18" - case 1'1 - attribute \src "ls180.v:8776.3-8778.6" - switch $not$ls180.v:8776$2690_Y - attribute \src "ls180.v:8776.7-8776.22" - case 1'1 - assign $0\builder_count[19:0] $sub$ls180.v:8777$2691_Y - case - end - attribute \src "ls180.v:8779.6-8779.10" - case - assign $0\builder_count[19:0] 20'11110100001001000000 - end - attribute \src "ls180.v:8783.2-8813.5" - switch \builder_csrbank0_sel - attribute \src "ls180.v:8783.6-8783.26" - case 1'1 - attribute \src "ls180.v:8784.3-8812.10" - switch \builder_interface0_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface0_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank0_reset0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors0_w - case - end - case - end - attribute \src "ls180.v:8814.2-8816.5" - switch \builder_csrbank0_reset0_re - attribute \src "ls180.v:8814.6-8814.32" - case 1'1 - assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r - case - end - attribute \src "ls180.v:8818.2-8820.5" - switch \builder_csrbank0_scratch3_re - attribute \src "ls180.v:8818.6-8818.34" - case 1'1 - assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r - case - end - attribute \src "ls180.v:8821.2-8823.5" - switch \builder_csrbank0_scratch2_re - attribute \src "ls180.v:8821.6-8821.34" - case 1'1 - assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r - case - end - attribute \src "ls180.v:8824.2-8826.5" - switch \builder_csrbank0_scratch1_re - attribute \src "ls180.v:8824.6-8824.34" - case 1'1 - assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r - case - end - attribute \src "ls180.v:8827.2-8829.5" - switch \builder_csrbank0_scratch0_re - attribute \src "ls180.v:8827.6-8827.34" - case 1'1 - assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r - case - end - attribute \src "ls180.v:8832.2-8853.5" - switch \builder_csrbank1_sel - attribute \src "ls180.v:8832.6-8832.26" - case 1'1 - attribute \src "ls180.v:8833.3-8852.10" - switch \builder_interface1_bank_bus_adr [2:0] - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe1_w - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe0_w - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in1_w - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in0_w - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out1_w - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out0_w - case - end - case - end - attribute \src "ls180.v:8854.2-8856.5" - switch \builder_csrbank1_oe1_re - attribute \src "ls180.v:8854.6-8854.29" - case 1'1 - assign $0\main_gpio_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r - case - end - attribute \src "ls180.v:8857.2-8859.5" - switch \builder_csrbank1_oe0_re - attribute \src "ls180.v:8857.6-8857.29" - case 1'1 - assign $0\main_gpio_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r - case - end - attribute \src "ls180.v:8861.2-8863.5" - switch \builder_csrbank1_out1_re - attribute \src "ls180.v:8861.6-8861.30" - case 1'1 - assign $0\main_gpio_out_storage[15:0] [15:8] \builder_csrbank1_out1_r - case - end - attribute \src "ls180.v:8864.2-8866.5" - switch \builder_csrbank1_out0_re - attribute \src "ls180.v:8864.6-8864.30" - case 1'1 - assign $0\main_gpio_out_storage[15:0] [7:0] \builder_csrbank1_out0_r - case - end - attribute \src "ls180.v:8869.2-8878.5" - switch \builder_csrbank2_sel - attribute \src "ls180.v:8869.6-8869.26" - case 1'1 - attribute \src "ls180.v:8870.3-8877.10" - switch \builder_interface2_bank_bus_adr [0] - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\builder_interface2_bank_bus_dat_r[7:0] { 5'00000 \builder_csrbank2_w0_w } - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\builder_interface2_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank2_r_w } - case - end - case - end - attribute \src "ls180.v:8879.2-8881.5" - switch \builder_csrbank2_w0_re - attribute \src "ls180.v:8879.6-8879.28" - case 1'1 - assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r - case - end - attribute \src "ls180.v:8884.2-8914.5" - switch \builder_csrbank3_sel - attribute \src "ls180.v:8884.6-8884.26" - case 1'1 - attribute \src "ls180.v:8885.3-8913.10" - switch \builder_interface3_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period0_w - case - end - case - end - attribute \src "ls180.v:8915.2-8917.5" - switch \builder_csrbank3_enable0_re - attribute \src "ls180.v:8915.6-8915.33" - case 1'1 - assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r - case - end - attribute \src "ls180.v:8919.2-8921.5" - switch \builder_csrbank3_width3_re - attribute \src "ls180.v:8919.6-8919.32" - case 1'1 - assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r - case - end - attribute \src "ls180.v:8922.2-8924.5" - switch \builder_csrbank3_width2_re - attribute \src "ls180.v:8922.6-8922.32" - case 1'1 - assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r - case - end - attribute \src "ls180.v:8925.2-8927.5" - switch \builder_csrbank3_width1_re - attribute \src "ls180.v:8925.6-8925.32" - case 1'1 - assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r - case - end - attribute \src "ls180.v:8928.2-8930.5" - switch \builder_csrbank3_width0_re - attribute \src "ls180.v:8928.6-8928.32" - case 1'1 - assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r - case - end - attribute \src "ls180.v:8932.2-8934.5" - switch \builder_csrbank3_period3_re - attribute \src "ls180.v:8932.6-8932.33" - case 1'1 - assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r - case - end - attribute \src "ls180.v:8935.2-8937.5" - switch \builder_csrbank3_period2_re - attribute \src "ls180.v:8935.6-8935.33" - case 1'1 - assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r - case - end - attribute \src "ls180.v:8938.2-8940.5" - switch \builder_csrbank3_period1_re - attribute \src "ls180.v:8938.6-8938.33" - case 1'1 - assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r - case - end - attribute \src "ls180.v:8941.2-8943.5" - switch \builder_csrbank3_period0_re - attribute \src "ls180.v:8941.6-8941.33" - case 1'1 - assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r - case - end - attribute \src "ls180.v:8946.2-8976.5" - switch \builder_csrbank4_sel - attribute \src "ls180.v:8946.6-8946.26" - case 1'1 - attribute \src "ls180.v:8947.3-8975.10" - switch \builder_interface4_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period0_w - case - end - case - end - attribute \src "ls180.v:8977.2-8979.5" - switch \builder_csrbank4_enable0_re - attribute \src "ls180.v:8977.6-8977.33" - case 1'1 - assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r - case - end - attribute \src "ls180.v:8981.2-8983.5" - switch \builder_csrbank4_width3_re - attribute \src "ls180.v:8981.6-8981.32" - case 1'1 - assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r - case - end - attribute \src "ls180.v:8984.2-8986.5" - switch \builder_csrbank4_width2_re - attribute \src "ls180.v:8984.6-8984.32" - case 1'1 - assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r - case - end - attribute \src "ls180.v:8987.2-8989.5" - switch \builder_csrbank4_width1_re - attribute \src "ls180.v:8987.6-8987.32" - case 1'1 - assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r - case - end - attribute \src "ls180.v:8990.2-8992.5" - switch \builder_csrbank4_width0_re - attribute \src "ls180.v:8990.6-8990.32" - case 1'1 - assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r - case - end - attribute \src "ls180.v:8994.2-8996.5" - switch \builder_csrbank4_period3_re - attribute \src "ls180.v:8994.6-8994.33" - case 1'1 - assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r - case - end - attribute \src "ls180.v:8997.2-8999.5" - switch \builder_csrbank4_period2_re - attribute \src "ls180.v:8997.6-8997.33" - case 1'1 - assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r - case - end - attribute \src "ls180.v:9000.2-9002.5" - switch \builder_csrbank4_period1_re - attribute \src "ls180.v:9000.6-9000.33" - case 1'1 - assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r - case - end - attribute \src "ls180.v:9003.2-9005.5" - switch \builder_csrbank4_period0_re - attribute \src "ls180.v:9003.6-9003.33" - case 1'1 - assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r - case - end - attribute \src "ls180.v:9008.2-9056.5" - switch \builder_csrbank5_sel - attribute \src "ls180.v:9008.6-9008.26" - case 1'1 - attribute \src "ls180.v:9009.3-9055.10" - switch \builder_interface5_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base7_w - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base6_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base5_w - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base4_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base0_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length3_w - attribute \src "ls180.v:0.0-0.0" - case 4'1001 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length2_w - attribute \src "ls180.v:0.0-0.0" - case 4'1010 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1011 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length0_w - attribute \src "ls180.v:0.0-0.0" - case 4'1100 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'1101 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_done_w } - attribute \src "ls180.v:0.0-0.0" - case 4'1110 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_loop0_w } - case - end - case - end - attribute \src "ls180.v:9057.2-9059.5" - switch \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:9057.6-9057.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r - case - end - attribute \src "ls180.v:9060.2-9062.5" - switch \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:9060.6-9060.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r - case - end - attribute \src "ls180.v:9063.2-9065.5" - switch \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:9063.6-9063.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r - case - end - attribute \src "ls180.v:9066.2-9068.5" - switch \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:9066.6-9066.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r - case - end - attribute \src "ls180.v:9069.2-9071.5" - switch \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:9069.6-9069.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r - case - end - attribute \src "ls180.v:9072.2-9074.5" - switch \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:9072.6-9072.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r - case - end - attribute \src "ls180.v:9075.2-9077.5" - switch \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:9075.6-9075.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r - case - end - attribute \src "ls180.v:9078.2-9080.5" - switch \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:9078.6-9078.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r - case - end - attribute \src "ls180.v:9082.2-9084.5" - switch \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:9082.6-9082.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r - case - end - attribute \src "ls180.v:9085.2-9087.5" - switch \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:9085.6-9085.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r - case - end - attribute \src "ls180.v:9088.2-9090.5" - switch \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:9088.6-9088.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r - case - end - attribute \src "ls180.v:9091.2-9093.5" - switch \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:9091.6-9091.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r - case - end - attribute \src "ls180.v:9095.2-9097.5" - switch \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:9095.6-9095.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r - case - end - attribute \src "ls180.v:9099.2-9101.5" - switch \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:9099.6-9099.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r - case - end - attribute \src "ls180.v:9104.2-9206.5" - switch \builder_csrbank6_sel - attribute \src "ls180.v:9104.6-9104.26" - case 1'1 - attribute \src "ls180.v:9105.3-9205.10" - switch \builder_interface6_bank_bus_adr [5:0] - attribute \src "ls180.v:0.0-0.0" - case 6'000000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument3_w - attribute \src "ls180.v:0.0-0.0" - case 6'000001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument2_w - attribute \src "ls180.v:0.0-0.0" - case 6'000010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument1_w - attribute \src "ls180.v:0.0-0.0" - case 6'000011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument0_w - attribute \src "ls180.v:0.0-0.0" - case 6'000100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command3_w - attribute \src "ls180.v:0.0-0.0" - case 6'000101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command2_w - attribute \src "ls180.v:0.0-0.0" - case 6'000110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command1_w - attribute \src "ls180.v:0.0-0.0" - case 6'000111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command0_w - attribute \src "ls180.v:0.0-0.0" - case 6'001000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \main_sdcore_cmd_send_w } - attribute \src "ls180.v:0.0-0.0" - case 6'001001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response15_w - attribute \src "ls180.v:0.0-0.0" - case 6'001010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response14_w - attribute \src "ls180.v:0.0-0.0" - case 6'001011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response13_w - attribute \src "ls180.v:0.0-0.0" - case 6'001100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response12_w - attribute \src "ls180.v:0.0-0.0" - case 6'001101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response11_w - attribute \src "ls180.v:0.0-0.0" - case 6'001110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response10_w - attribute \src "ls180.v:0.0-0.0" - case 6'001111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response9_w - attribute \src "ls180.v:0.0-0.0" - case 6'010000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response8_w - attribute \src "ls180.v:0.0-0.0" - case 6'010001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response7_w - attribute \src "ls180.v:0.0-0.0" - case 6'010010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response6_w - attribute \src "ls180.v:0.0-0.0" - case 6'010011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response5_w - attribute \src "ls180.v:0.0-0.0" - case 6'010100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response4_w - attribute \src "ls180.v:0.0-0.0" - case 6'010101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response3_w - attribute \src "ls180.v:0.0-0.0" - case 6'010110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response2_w - attribute \src "ls180.v:0.0-0.0" - case 6'010111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response1_w - attribute \src "ls180.v:0.0-0.0" - case 6'011000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response0_w - attribute \src "ls180.v:0.0-0.0" - case 6'011001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_cmd_event_w } - attribute \src "ls180.v:0.0-0.0" - case 6'011010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_data_event_w } - attribute \src "ls180.v:0.0-0.0" - case 6'011011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank6_block_length1_w } - attribute \src "ls180.v:0.0-0.0" - case 6'011100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_length0_w - attribute \src "ls180.v:0.0-0.0" - case 6'011101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count3_w - attribute \src "ls180.v:0.0-0.0" - case 6'011110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count2_w - attribute \src "ls180.v:0.0-0.0" - case 6'011111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count1_w - attribute \src "ls180.v:0.0-0.0" - case 6'100000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count0_w - case - end - case - end - attribute \src "ls180.v:9207.2-9209.5" - switch \builder_csrbank6_cmd_argument3_re - attribute \src "ls180.v:9207.6-9207.39" - case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r - case - end - attribute \src "ls180.v:9210.2-9212.5" - switch \builder_csrbank6_cmd_argument2_re - attribute \src "ls180.v:9210.6-9210.39" - case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r - case - end - attribute \src "ls180.v:9213.2-9215.5" - switch \builder_csrbank6_cmd_argument1_re - attribute \src "ls180.v:9213.6-9213.39" - case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r - case - end - attribute \src "ls180.v:9216.2-9218.5" - switch \builder_csrbank6_cmd_argument0_re - attribute \src "ls180.v:9216.6-9216.39" - case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r - case - end - attribute \src "ls180.v:9220.2-9222.5" - switch \builder_csrbank6_cmd_command3_re - attribute \src "ls180.v:9220.6-9220.38" - case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r - case - end - attribute \src "ls180.v:9223.2-9225.5" - switch \builder_csrbank6_cmd_command2_re - attribute \src "ls180.v:9223.6-9223.38" - case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r - case - end - attribute \src "ls180.v:9226.2-9228.5" - switch \builder_csrbank6_cmd_command1_re - attribute \src "ls180.v:9226.6-9226.38" - case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r - case - end - attribute \src "ls180.v:9229.2-9231.5" - switch \builder_csrbank6_cmd_command0_re - attribute \src "ls180.v:9229.6-9229.38" - case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r - case - end - attribute \src "ls180.v:9233.2-9235.5" - switch \builder_csrbank6_block_length1_re - attribute \src "ls180.v:9233.6-9233.39" - case 1'1 - assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r - case - end - attribute \src "ls180.v:9236.2-9238.5" - switch \builder_csrbank6_block_length0_re - attribute \src "ls180.v:9236.6-9236.39" - case 1'1 - assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r - case - end - attribute \src "ls180.v:9240.2-9242.5" - switch \builder_csrbank6_block_count3_re - attribute \src "ls180.v:9240.6-9240.38" - case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r - case - end - attribute \src "ls180.v:9243.2-9245.5" - switch \builder_csrbank6_block_count2_re - attribute \src "ls180.v:9243.6-9243.38" - case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r - case - end - attribute \src "ls180.v:9246.2-9248.5" - switch \builder_csrbank6_block_count1_re - attribute \src "ls180.v:9246.6-9246.38" - case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r - case - end - attribute \src "ls180.v:9249.2-9251.5" - switch \builder_csrbank6_block_count0_re - attribute \src "ls180.v:9249.6-9249.38" - case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r - case - end - attribute \src "ls180.v:9254.2-9314.5" - switch \builder_csrbank7_sel - attribute \src "ls180.v:9254.6-9254.26" - case 1'1 - attribute \src "ls180.v:9255.3-9313.10" - switch \builder_interface7_bank_bus_adr [4:0] - attribute \src "ls180.v:0.0-0.0" - case 5'00000 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base7_w - attribute \src "ls180.v:0.0-0.0" - case 5'00001 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base6_w - attribute \src "ls180.v:0.0-0.0" - case 5'00010 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base5_w - attribute \src "ls180.v:0.0-0.0" - case 5'00011 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base4_w - attribute \src "ls180.v:0.0-0.0" - case 5'00100 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base3_w - attribute \src "ls180.v:0.0-0.0" - case 5'00101 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base2_w - attribute \src "ls180.v:0.0-0.0" - case 5'00110 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base1_w - attribute \src "ls180.v:0.0-0.0" - case 5'00111 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base0_w - attribute \src "ls180.v:0.0-0.0" - case 5'01000 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length3_w - attribute \src "ls180.v:0.0-0.0" - case 5'01001 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length2_w - attribute \src "ls180.v:0.0-0.0" - case 5'01010 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length1_w - attribute \src "ls180.v:0.0-0.0" - case 5'01011 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length0_w - attribute \src "ls180.v:0.0-0.0" - case 5'01100 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01101 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_done_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01110 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_loop0_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01111 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset3_w - attribute \src "ls180.v:0.0-0.0" - case 5'10000 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset2_w - attribute \src "ls180.v:0.0-0.0" - case 5'10001 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset1_w - attribute \src "ls180.v:0.0-0.0" - case 5'10010 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset0_w - case - end - case - end - attribute \src "ls180.v:9315.2-9317.5" - switch \builder_csrbank7_dma_base7_re - attribute \src "ls180.v:9315.6-9315.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r - case - end - attribute \src "ls180.v:9318.2-9320.5" - switch \builder_csrbank7_dma_base6_re - attribute \src "ls180.v:9318.6-9318.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r - case - end - attribute \src "ls180.v:9321.2-9323.5" - switch \builder_csrbank7_dma_base5_re - attribute \src "ls180.v:9321.6-9321.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r - case - end - attribute \src "ls180.v:9324.2-9326.5" - switch \builder_csrbank7_dma_base4_re - attribute \src "ls180.v:9324.6-9324.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r - case - end - attribute \src "ls180.v:9327.2-9329.5" - switch \builder_csrbank7_dma_base3_re - attribute \src "ls180.v:9327.6-9327.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r - case - end - attribute \src "ls180.v:9330.2-9332.5" - switch \builder_csrbank7_dma_base2_re - attribute \src "ls180.v:9330.6-9330.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r - case - end - attribute \src "ls180.v:9333.2-9335.5" - switch \builder_csrbank7_dma_base1_re - attribute \src "ls180.v:9333.6-9333.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r - case - end - attribute \src "ls180.v:9336.2-9338.5" - switch \builder_csrbank7_dma_base0_re - attribute \src "ls180.v:9336.6-9336.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r - case - end - attribute \src "ls180.v:9340.2-9342.5" - switch \builder_csrbank7_dma_length3_re - attribute \src "ls180.v:9340.6-9340.37" - case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r - case - end - attribute \src "ls180.v:9343.2-9345.5" - switch \builder_csrbank7_dma_length2_re - attribute \src "ls180.v:9343.6-9343.37" - case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r - case - end - attribute \src "ls180.v:9346.2-9348.5" - switch \builder_csrbank7_dma_length1_re - attribute \src "ls180.v:9346.6-9346.37" - case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r - case - end - attribute \src "ls180.v:9349.2-9351.5" - switch \builder_csrbank7_dma_length0_re - attribute \src "ls180.v:9349.6-9349.37" - case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r - case - end - attribute \src "ls180.v:9353.2-9355.5" - switch \builder_csrbank7_dma_enable0_re - attribute \src "ls180.v:9353.6-9353.37" - case 1'1 - assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r - case - end - attribute \src "ls180.v:9357.2-9359.5" - switch \builder_csrbank7_dma_loop0_re - attribute \src "ls180.v:9357.6-9357.35" - case 1'1 - assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r - case - end - attribute \src "ls180.v:9362.2-9377.5" - switch \builder_csrbank8_sel - attribute \src "ls180.v:9362.6-9362.26" - case 1'1 - attribute \src "ls180.v:9363.3-9376.10" - switch \builder_interface8_bank_bus_adr [1:0] - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_card_detect_w } - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_clocker_divider1_w } - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_clocker_divider0_w - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \main_sdphy_init_initialize_w } - case - end - case - end - attribute \src "ls180.v:9378.2-9380.5" - switch \builder_csrbank8_clocker_divider1_re - attribute \src "ls180.v:9378.6-9378.42" - case 1'1 - assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r - case - end - attribute \src "ls180.v:9381.2-9383.5" - switch \builder_csrbank8_clocker_divider0_re - attribute \src "ls180.v:9381.6-9381.42" - case 1'1 - assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r - case - end - attribute \src "ls180.v:9386.2-9419.5" - switch \builder_csrbank9_sel - attribute \src "ls180.v:9386.6-9386.26" - case 1'1 - attribute \src "ls180.v:9387.3-9418.10" - switch \builder_interface9_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank9_dfii_control0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 2'00 \builder_csrbank9_dfii_pi0_command0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \main_sdram_command_issue_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 3'000 \builder_csrbank9_dfii_pi0_address1_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_address0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank9_dfii_pi0_baddress0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata0_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1001 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata0_w - case - end - case - end - attribute \src "ls180.v:9420.2-9422.5" - switch \builder_csrbank9_dfii_control0_re - attribute \src "ls180.v:9420.6-9420.39" - case 1'1 - assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r - case - end - attribute \src "ls180.v:9424.2-9426.5" - switch \builder_csrbank9_dfii_pi0_command0_re - attribute \src "ls180.v:9424.6-9424.43" - case 1'1 - assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r - case - end - attribute \src "ls180.v:9428.2-9430.5" - switch \builder_csrbank9_dfii_pi0_address1_re - attribute \src "ls180.v:9428.6-9428.43" - case 1'1 - assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r - case - end - attribute \src "ls180.v:9431.2-9433.5" - switch \builder_csrbank9_dfii_pi0_address0_re - attribute \src "ls180.v:9431.6-9431.43" - case 1'1 - assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r - case - end - attribute \src "ls180.v:9435.2-9437.5" - switch \builder_csrbank9_dfii_pi0_baddress0_re - attribute \src "ls180.v:9435.6-9435.44" - case 1'1 - assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r - case - end - attribute \src "ls180.v:9439.2-9441.5" - switch \builder_csrbank9_dfii_pi0_wrdata1_re - attribute \src "ls180.v:9439.6-9439.42" - case 1'1 - assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r - case - end - attribute \src "ls180.v:9442.2-9444.5" - switch \builder_csrbank9_dfii_pi0_wrdata0_re - attribute \src "ls180.v:9442.6-9442.42" - case 1'1 - assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r - case - end - attribute \src "ls180.v:9447.2-9471.5" - switch \builder_csrbank10_sel - attribute \src "ls180.v:9447.6-9447.27" - case 1'1 - attribute \src "ls180.v:9448.3-9470.10" - switch \builder_interface10_bank_bus_adr [2:0] - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control1_w - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control0_w - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_status_w } - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_mosi0_w - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_miso_w - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_cs0_w } - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_loopback0_w } - case - end - case - end - attribute \src "ls180.v:9472.2-9474.5" - switch \builder_csrbank10_control1_re - attribute \src "ls180.v:9472.6-9472.35" - case 1'1 - assign $0\main_spi_master_control_storage[15:0] [15:8] \builder_csrbank10_control1_r - case - end - attribute \src "ls180.v:9475.2-9477.5" - switch \builder_csrbank10_control0_re - attribute \src "ls180.v:9475.6-9475.35" - case 1'1 - assign $0\main_spi_master_control_storage[15:0] [7:0] \builder_csrbank10_control0_r - case - end - attribute \src "ls180.v:9479.2-9481.5" - switch \builder_csrbank10_mosi0_re - attribute \src "ls180.v:9479.6-9479.32" - case 1'1 - assign $0\main_spi_master_mosi_storage[7:0] \builder_csrbank10_mosi0_r - case - end - attribute \src "ls180.v:9483.2-9485.5" - switch \builder_csrbank10_cs0_re - attribute \src "ls180.v:9483.6-9483.30" - case 1'1 - assign $0\main_spi_master_cs_storage[0:0] \builder_csrbank10_cs0_r - case - end - attribute \src "ls180.v:9487.2-9489.5" - switch \builder_csrbank10_loopback0_re - attribute \src "ls180.v:9487.6-9487.36" - case 1'1 - assign $0\main_spi_master_loopback_storage[0:0] \builder_csrbank10_loopback0_r - case - end - attribute \src "ls180.v:9492.2-9522.5" - switch \builder_csrbank11_sel - attribute \src "ls180.v:9492.6-9492.27" - case 1'1 - attribute \src "ls180.v:9493.3-9521.10" - switch \builder_interface11_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_status_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_mosi0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_miso_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_cs0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_loopback0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider0_w - case - end - case - end - attribute \src "ls180.v:9523.2-9525.5" - switch \builder_csrbank11_control1_re - attribute \src "ls180.v:9523.6-9523.35" - case 1'1 - assign $0\libresocsim_control_storage[15:0] [15:8] \builder_csrbank11_control1_r - case - end - attribute \src "ls180.v:9526.2-9528.5" - switch \builder_csrbank11_control0_re - attribute \src "ls180.v:9526.6-9526.35" - case 1'1 - assign $0\libresocsim_control_storage[15:0] [7:0] \builder_csrbank11_control0_r - case - end - attribute \src "ls180.v:9530.2-9532.5" - switch \builder_csrbank11_mosi0_re - attribute \src "ls180.v:9530.6-9530.32" - case 1'1 - assign $0\libresocsim_mosi_storage[7:0] \builder_csrbank11_mosi0_r - case - end - attribute \src "ls180.v:9534.2-9536.5" - switch \builder_csrbank11_cs0_re - attribute \src "ls180.v:9534.6-9534.30" - case 1'1 - assign $0\libresocsim_cs_storage[0:0] \builder_csrbank11_cs0_r - case - end - attribute \src "ls180.v:9538.2-9540.5" - switch \builder_csrbank11_loopback0_re - attribute \src "ls180.v:9538.6-9538.36" - case 1'1 - assign $0\libresocsim_loopback_storage[0:0] \builder_csrbank11_loopback0_r - case - end - attribute \src "ls180.v:9542.2-9544.5" - switch \builder_csrbank11_clk_divider1_re - attribute \src "ls180.v:9542.6-9542.39" - case 1'1 - assign $0\libresocsim_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r - case - end - attribute \src "ls180.v:9545.2-9547.5" - switch \builder_csrbank11_clk_divider0_re - attribute \src "ls180.v:9545.6-9545.39" - case 1'1 - assign $0\libresocsim_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r - case - end - attribute \src "ls180.v:9550.2-9604.5" - switch \builder_csrbank12_sel - attribute \src "ls180.v:9550.6-9550.27" - case 1'1 - attribute \src "ls180.v:9551.3-9603.10" - switch \builder_interface12_bank_bus_adr [4:0] - attribute \src "ls180.v:0.0-0.0" - case 5'00000 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load3_w - attribute \src "ls180.v:0.0-0.0" - case 5'00001 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load2_w - attribute \src "ls180.v:0.0-0.0" - case 5'00010 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load1_w - attribute \src "ls180.v:0.0-0.0" - case 5'00011 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load0_w - attribute \src "ls180.v:0.0-0.0" - case 5'00100 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload3_w - attribute \src "ls180.v:0.0-0.0" - case 5'00101 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload2_w - attribute \src "ls180.v:0.0-0.0" - case 5'00110 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload1_w - attribute \src "ls180.v:0.0-0.0" - case 5'00111 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload0_w - attribute \src "ls180.v:0.0-0.0" - case 5'01000 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_en0_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01001 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_update_value0_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01010 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value3_w - attribute \src "ls180.v:0.0-0.0" - case 5'01011 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value2_w - attribute \src "ls180.v:0.0-0.0" - case 5'01100 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value1_w - attribute \src "ls180.v:0.0-0.0" - case 5'01101 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value0_w - attribute \src "ls180.v:0.0-0.0" - case 5'01110 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_status_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01111 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_pending_w } - attribute \src "ls180.v:0.0-0.0" - case 5'10000 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_ev_enable0_w } - case - end - case - end - attribute \src "ls180.v:9605.2-9607.5" - switch \builder_csrbank12_load3_re - attribute \src "ls180.v:9605.6-9605.32" - case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r - case - end - attribute \src "ls180.v:9608.2-9610.5" - switch \builder_csrbank12_load2_re - attribute \src "ls180.v:9608.6-9608.32" - case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r - case - end - attribute \src "ls180.v:9611.2-9613.5" - switch \builder_csrbank12_load1_re - attribute \src "ls180.v:9611.6-9611.32" - case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r - case - end - attribute \src "ls180.v:9614.2-9616.5" - switch \builder_csrbank12_load0_re - attribute \src "ls180.v:9614.6-9614.32" - case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r - case - end - attribute \src "ls180.v:9618.2-9620.5" - switch \builder_csrbank12_reload3_re - attribute \src "ls180.v:9618.6-9618.34" - case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r - case - end - attribute \src "ls180.v:9621.2-9623.5" - switch \builder_csrbank12_reload2_re - attribute \src "ls180.v:9621.6-9621.34" - case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r - case - end - attribute \src "ls180.v:9624.2-9626.5" - switch \builder_csrbank12_reload1_re - attribute \src "ls180.v:9624.6-9624.34" - case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r - case - end - attribute \src "ls180.v:9627.2-9629.5" - switch \builder_csrbank12_reload0_re - attribute \src "ls180.v:9627.6-9627.34" - case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r - case - end - attribute \src "ls180.v:9631.2-9633.5" - switch \builder_csrbank12_en0_re - attribute \src "ls180.v:9631.6-9631.30" - case 1'1 - assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r - case - end - attribute \src "ls180.v:9635.2-9637.5" - switch \builder_csrbank12_update_value0_re - attribute \src "ls180.v:9635.6-9635.40" - case 1'1 - assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r - case - end - attribute \src "ls180.v:9639.2-9641.5" - switch \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:9639.6-9639.37" - case 1'1 - assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r - case - end - attribute \src "ls180.v:9644.2-9671.5" - switch \builder_csrbank13_sel - attribute \src "ls180.v:9644.6-9644.27" - case 1'1 - attribute \src "ls180.v:9645.3-9670.10" - switch \builder_interface13_bank_bus_adr [2:0] - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_interface13_bank_bus_dat_r[7:0] \main_uart_rxtx_w - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txfull_w } - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxempty_w } - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_status_w } - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_pending_w } - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank13_ev_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txempty_w } - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxfull_w } - case - end - case - end - attribute \src "ls180.v:9672.2-9674.5" - switch \builder_csrbank13_ev_enable0_re - attribute \src "ls180.v:9672.6-9672.37" - case 1'1 - assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r - case - end - attribute \src "ls180.v:9677.2-9692.5" - switch \builder_csrbank14_sel - attribute \src "ls180.v:9677.6-9677.27" - case 1'1 - attribute \src "ls180.v:9678.3-9691.10" - switch \builder_interface14_bank_bus_adr [1:0] - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word3_w - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word2_w - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word1_w - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word0_w - case - end - case - end - attribute \src "ls180.v:9693.2-9695.5" - switch \builder_csrbank14_tuning_word3_re - attribute \src "ls180.v:9693.6-9693.39" - case 1'1 - assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r - case - end - attribute \src "ls180.v:9696.2-9698.5" - switch \builder_csrbank14_tuning_word2_re - attribute \src "ls180.v:9696.6-9696.39" - case 1'1 - assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r - case - end - attribute \src "ls180.v:9699.2-9701.5" - switch \builder_csrbank14_tuning_word1_re - attribute \src "ls180.v:9699.6-9699.39" - case 1'1 - assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r - case - end - attribute \src "ls180.v:9702.2-9704.5" - switch \builder_csrbank14_tuning_word0_re - attribute \src "ls180.v:9702.6-9702.39" - case 1'1 - assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r - case - end - attribute \src "ls180.v:9706.2-10001.5" - switch \sys_rst_1 - attribute \src "ls180.v:9706.6-9706.15" - case 1'1 - assign $0\main_libresocsim_reset_storage[0:0] 1'0 - assign $0\main_libresocsim_reset_re[0:0] 1'0 - assign $0\main_libresocsim_scratch_storage[31:0] 305419896 - assign $0\main_libresocsim_scratch_re[0:0] 1'0 - assign $0\main_libresocsim_bus_errors[31:0] 0 - assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 - assign $0\main_libresocsim_converter0_counter[0:0] 1'0 - assign $0\main_libresocsim_converter1_counter[0:0] 1'0 - assign $0\main_libresocsim_converter2_counter[0:0] 1'0 - assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 - assign $0\main_libresocsim_load_storage[31:0] 0 - assign $0\main_libresocsim_load_re[0:0] 1'0 - assign $0\main_libresocsim_reload_storage[31:0] 0 - assign $0\main_libresocsim_reload_re[0:0] 1'0 - assign $0\main_libresocsim_en_storage[0:0] 1'0 - assign $0\main_libresocsim_en_re[0:0] 1'0 - assign $0\main_libresocsim_update_value_storage[0:0] 1'0 - assign $0\main_libresocsim_update_value_re[0:0] 1'0 - assign $0\main_libresocsim_value_status[31:0] 0 - assign $0\main_libresocsim_zero_pending[0:0] 1'0 - assign $0\main_libresocsim_zero_old_trigger[0:0] 1'0 - assign $0\main_libresocsim_eventmanager_storage[0:0] 1'0 - assign $0\main_libresocsim_eventmanager_re[0:0] 1'0 - assign $0\main_libresocsim_value[31:0] 0 - assign $0\main_dfi_p0_rddata_valid[0:0] 1'0 - assign $0\main_rddata_en[2:0] 3'000 - assign $0\main_sdram_storage[3:0] 4'0001 - assign $0\main_sdram_re[0:0] 1'0 - assign $0\main_sdram_command_storage[5:0] 6'000000 - assign $0\main_sdram_command_re[0:0] 1'0 - assign $0\main_sdram_address_re[0:0] 1'0 - assign $0\main_sdram_baddress_re[0:0] 1'0 - assign $0\main_sdram_wrdata_re[0:0] 1'0 - assign $0\main_sdram_status[15:0] 16'0000000000000000 - assign $0\main_sdram_dfi_p0_address[12:0] 13'0000000000000 - assign $0\main_sdram_dfi_p0_bank[1:0] 2'00 - assign $0\main_sdram_dfi_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_we_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 - assign $0\main_sdram_dfi_p0_rddata_en[0:0] 1'0 - assign $0\main_sdram_timer_count1[9:0] 10'1100001101 - assign $0\main_sdram_postponer_req_o[0:0] 1'0 - assign $0\main_sdram_postponer_count[0:0] 1'0 - assign $0\main_sdram_sequencer_done1[0:0] 1'0 - assign $0\main_sdram_sequencer_counter[3:0] 4'0000 - assign $0\main_sdram_sequencer_count[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - assign $0\main_sdram_tccdcon_ready[0:0] 1'0 - assign $0\main_sdram_tccdcon_count[0:0] 1'0 - assign $0\main_sdram_twtrcon_ready[0:0] 1'0 - assign $0\main_sdram_twtrcon_count[2:0] 3'000 - assign $0\main_sdram_time0[4:0] 5'00000 - assign $0\main_sdram_time1[3:0] 4'0000 - assign $0\main_converter_counter[0:0] 1'0 - assign $0\main_cmd_consumed[0:0] 1'0 - assign $0\main_wdata_consumed[0:0] 1'0 - assign $0\main_uart_phy_storage[31:0] 9895604 - assign $0\main_uart_phy_re[0:0] 1'0 - assign $0\main_uart_phy_sink_ready[0:0] 1'0 - assign $0\main_uart_phy_uart_clk_txen[0:0] 1'0 - assign $0\main_uart_phy_tx_busy[0:0] 1'0 - assign $0\main_uart_phy_source_valid[0:0] 1'0 - assign $0\main_uart_phy_uart_clk_rxen[0:0] 1'0 - assign $0\main_uart_phy_rx_r[0:0] 1'0 - assign $0\main_uart_phy_rx_busy[0:0] 1'0 - assign $0\main_uart_tx_pending[0:0] 1'0 - assign $0\main_uart_tx_old_trigger[0:0] 1'0 - assign $0\main_uart_rx_pending[0:0] 1'0 - assign $0\main_uart_rx_old_trigger[0:0] 1'0 - assign $0\main_uart_eventmanager_storage[1:0] 2'00 - assign $0\main_uart_eventmanager_re[0:0] 1'0 - assign $0\main_uart_tx_fifo_readable[0:0] 1'0 - assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 - assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 - assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 - assign $0\main_uart_rx_fifo_readable[0:0] 1'0 - assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 - assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 - assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 - assign $0\main_gpio_oe_storage[15:0] 16'0000000000000000 - assign $0\main_gpio_oe_re[0:0] 1'0 - assign $0\main_gpio_out_storage[15:0] 16'0000000000000000 - assign $0\main_gpio_out_re[0:0] 1'0 - assign $0\spi_master_clk[0:0] 1'0 - assign $0\spi_master_mosi[0:0] 1'0 - assign $0\spi_master_cs_n[0:0] 1'0 - assign $0\main_spi_master_miso[7:0] 8'00000000 - assign $0\main_spi_master_control_storage[15:0] 16'0000000000000000 - assign $0\main_spi_master_control_re[0:0] 1'0 - assign $0\main_spi_master_mosi_re[0:0] 1'0 - assign $0\main_spi_master_cs_storage[0:0] 1'1 - assign $0\main_spi_master_cs_re[0:0] 1'0 - assign $0\main_spi_master_loopback_storage[0:0] 1'0 - assign $0\main_spi_master_loopback_re[0:0] 1'0 - assign $0\main_spi_master_count[2:0] 3'000 - assign $0\main_spi_master_clk_divider1[15:0] 16'0000000000000000 - assign $0\main_spi_master_mosi_data[7:0] 8'00000000 - assign $0\main_spi_master_mosi_sel[2:0] 3'000 - assign $0\main_spi_master_miso_data[7:0] 8'00000000 - assign $0\main_dummy[35:0] 36'000000000000000000000000000000000000 - assign $0\pwm0[0:0] 1'0 - assign $0\main_pwm0_enable_storage[0:0] 1'0 - assign $0\main_pwm0_enable_re[0:0] 1'0 - assign $0\main_pwm0_width_re[0:0] 1'0 - assign $0\main_pwm0_period_re[0:0] 1'0 - assign $0\pwm1[0:0] 1'0 - assign $0\main_pwm1_enable_storage[0:0] 1'0 - assign $0\main_pwm1_enable_re[0:0] 1'0 - assign $0\main_pwm1_width_re[0:0] 1'0 - assign $0\main_pwm1_period_re[0:0] 1'0 - assign $0\main_i2c_storage[2:0] 3'000 - assign $0\main_i2c_re[0:0] 1'0 - assign $0\main_sdphy_clocker_storage[8:0] 9'100000000 - assign $0\main_sdphy_clocker_re[0:0] 1'0 - assign $0\main_sdphy_clocker_clk0[0:0] 1'0 - assign $0\main_sdphy_clocker_clks[8:0] 9'000000000 - assign $0\main_sdphy_clocker_clk_d[0:0] 1'0 - assign $0\main_sdphy_init_count[7:0] 8'00000000 - assign $0\main_sdphy_cmdw_count[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_timeout[31:0] 500000 - assign $0\main_sdphy_cmdr_count[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 - assign $0\main_sdphy_dataw_count[7:0] 8'00000000 - assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_reset[0:0] 1'0 - assign $0\main_sdphy_datar_timeout[31:0] 500000 - assign $0\main_sdphy_datar_count[9:0] 10'0000000000 - assign $0\main_sdphy_datar_datar_run[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset[0:0] 1'0 - assign $0\main_sdcore_cmd_argument_storage[31:0] 0 - assign $0\main_sdcore_cmd_argument_re[0:0] 1'0 - assign $0\main_sdcore_cmd_command_storage[31:0] 0 - assign $0\main_sdcore_cmd_command_re[0:0] 1'0 - assign $0\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdcore_block_length_storage[9:0] 10'0000000000 - assign $0\main_sdcore_block_length_re[0:0] 1'0 - assign $0\main_sdcore_block_count_storage[31:0] 0 - assign $0\main_sdcore_block_count_re[0:0] 1'0 - assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - assign $0\main_sdcore_crc16_inserter_cnt[2:0] 3'000 - assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_val[7:0] 8'00000000 - assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 - assign $0\main_sdcore_cmd_count[2:0] 3'000 - assign $0\main_sdcore_cmd_done[0:0] 1'0 - assign $0\main_sdcore_cmd_error[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout[0:0] 1'0 - assign $0\main_sdcore_data_count[31:0] 0 - assign $0\main_sdcore_data_done[0:0] 1'0 - assign $0\main_sdcore_data_error[0:0] 1'0 - assign $0\main_sdcore_data_timeout[0:0] 1'0 - assign $0\main_sdblock2mem_fifo_level[5:0] 6'000000 - assign $0\main_sdblock2mem_fifo_produce[4:0] 5'00000 - assign $0\main_sdblock2mem_fifo_consume[4:0] 5'00000 - assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 - assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 - assign $0\main_sdmem2block_dma_data[31:0] 0 - assign $0\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdmem2block_dma_base_re[0:0] 1'0 - assign $0\main_sdmem2block_dma_length_storage[31:0] 0 - assign $0\main_sdmem2block_dma_length_re[0:0] 1'0 - assign $0\main_sdmem2block_dma_enable_storage[0:0] 1'0 - assign $0\main_sdmem2block_dma_enable_re[0:0] 1'0 - assign $0\main_sdmem2block_dma_loop_storage[0:0] 1'0 - assign $0\main_sdmem2block_dma_loop_re[0:0] 1'0 - assign $0\main_sdmem2block_dma_offset[31:0] 0 - assign $0\main_sdmem2block_converter_mux[1:0] 2'00 - assign $0\main_sdmem2block_fifo_level[5:0] 6'000000 - assign $0\main_sdmem2block_fifo_produce[4:0] 5'00000 - assign $0\main_sdmem2block_fifo_consume[4:0] 5'00000 - assign $0\spisdcard_clk[0:0] 1'0 - assign $0\spisdcard_mosi[0:0] 1'0 - assign $0\spisdcard_cs_n[0:0] 1'0 - assign $0\libresocsim_miso[7:0] 8'00000000 - assign $0\libresocsim_control_storage[15:0] 16'0000000000000000 - assign $0\libresocsim_control_re[0:0] 1'0 - assign $0\libresocsim_mosi_re[0:0] 1'0 - assign $0\libresocsim_cs_storage[0:0] 1'1 - assign $0\libresocsim_cs_re[0:0] 1'0 - assign $0\libresocsim_loopback_storage[0:0] 1'0 - assign $0\libresocsim_loopback_re[0:0] 1'0 - assign $0\libresocsim_count[2:0] 3'000 - assign $0\libresocsim_clk_divider1[15:0] 16'0000000000000000 - assign $0\libresocsim_mosi_data[7:0] 8'00000000 - assign $0\libresocsim_mosi_sel[2:0] 3'000 - assign $0\libresocsim_miso_data[7:0] 8'00000000 - assign $0\libresocsim_storage[15:0] 16'0000000001111101 - assign $0\libresocsim_re[0:0] 1'0 - assign $0\builder_converter0_state[0:0] 1'0 - assign $0\builder_converter1_state[0:0] 1'0 - assign $0\builder_converter2_state[0:0] 1'0 - assign $0\builder_refresher_state[1:0] 2'00 - assign $0\builder_bankmachine0_state[2:0] 3'000 - assign $0\builder_bankmachine1_state[2:0] 3'000 - assign $0\builder_bankmachine2_state[2:0] 3'000 - assign $0\builder_bankmachine3_state[2:0] 3'000 - assign $0\builder_multiplexer_state[2:0] 3'000 - assign $0\builder_new_master_wdata_ready[0:0] 1'0 - assign $0\builder_new_master_rdata_valid0[0:0] 1'0 - assign $0\builder_new_master_rdata_valid1[0:0] 1'0 - assign $0\builder_new_master_rdata_valid2[0:0] 1'0 - assign $0\builder_new_master_rdata_valid3[0:0] 1'0 - assign $0\builder_converter_state[0:0] 1'0 - assign $0\builder_spimaster0_state[1:0] 2'00 - assign $0\builder_sdphy_sdphyinit_state[0:0] 1'0 - assign $0\builder_sdphy_sdphycmdw_state[1:0] 2'00 - assign $0\builder_sdphy_sdphycmdr_state[2:0] 3'000 - assign $0\builder_sdphy_sdphycrcr_state[0:0] 1'0 - assign $0\builder_sdphy_fsm_state[2:0] 3'000 - assign $0\builder_sdphy_sdphydatar_state[2:0] 3'000 - assign $0\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 - assign $0\builder_sdcore_fsm_state[2:0] 3'000 - assign $0\builder_sdblock2memdma_state[1:0] 2'00 - assign $0\builder_sdmem2blockdma_fsm_state[0:0] 1'0 - assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 - assign $0\builder_spimaster1_state[1:0] 2'00 - assign $0\builder_libresocsim_we[0:0] 1'0 - assign $0\builder_grant[2:0] 3'000 - assign $0\builder_slave_sel_r[4:0] 5'00000 - assign $0\builder_count[19:0] 20'11110100001001000000 - assign $0\builder_state[1:0] 2'00 - case - end - sync posedge \sys_clk_1 - update \spi_master_clk $0\spi_master_clk[0:0] - update \spi_master_mosi $0\spi_master_mosi[0:0] - update \spi_master_cs_n $0\spi_master_cs_n[0:0] - update \pwm0 $0\pwm0[0:0] - update \pwm1 $0\pwm1[0:0] - update \spisdcard_clk $0\spisdcard_clk[0:0] - update \spisdcard_mosi $0\spisdcard_mosi[0:0] - update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] - update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] - update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] - update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] - update \main_libresocsim_scratch_re $0\main_libresocsim_scratch_re[0:0] - update \main_libresocsim_bus_errors $0\main_libresocsim_bus_errors[31:0] - update \main_libresocsim_libresoc_constraintmanager0_uart0_tx $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] - update \main_libresocsim_converter0_counter $0\main_libresocsim_converter0_counter[0:0] - update \main_libresocsim_converter0_dat_r $0\main_libresocsim_converter0_dat_r[63:0] - update \main_libresocsim_converter1_counter $0\main_libresocsim_converter1_counter[0:0] - update \main_libresocsim_converter1_dat_r $0\main_libresocsim_converter1_dat_r[63:0] - update \main_libresocsim_converter2_counter $0\main_libresocsim_converter2_counter[0:0] - update \main_libresocsim_converter2_dat_r $0\main_libresocsim_converter2_dat_r[63:0] - update \main_libresocsim_ram_bus_ack $0\main_libresocsim_ram_bus_ack[0:0] - update \main_libresocsim_load_storage $0\main_libresocsim_load_storage[31:0] - update \main_libresocsim_load_re $0\main_libresocsim_load_re[0:0] - update \main_libresocsim_reload_storage $0\main_libresocsim_reload_storage[31:0] - update \main_libresocsim_reload_re $0\main_libresocsim_reload_re[0:0] - update \main_libresocsim_en_storage $0\main_libresocsim_en_storage[0:0] - update \main_libresocsim_en_re $0\main_libresocsim_en_re[0:0] - update \main_libresocsim_update_value_storage $0\main_libresocsim_update_value_storage[0:0] - update \main_libresocsim_update_value_re $0\main_libresocsim_update_value_re[0:0] - update \main_libresocsim_value_status $0\main_libresocsim_value_status[31:0] - update \main_libresocsim_zero_pending $0\main_libresocsim_zero_pending[0:0] - update \main_libresocsim_zero_old_trigger $0\main_libresocsim_zero_old_trigger[0:0] - update \main_libresocsim_eventmanager_storage $0\main_libresocsim_eventmanager_storage[0:0] - update \main_libresocsim_eventmanager_re $0\main_libresocsim_eventmanager_re[0:0] - update \main_libresocsim_value $0\main_libresocsim_value[31:0] - update \main_dfi_p0_rddata_valid $0\main_dfi_p0_rddata_valid[0:0] - update \main_rddata_en $0\main_rddata_en[2:0] - update \main_sdram_storage $0\main_sdram_storage[3:0] - update \main_sdram_re $0\main_sdram_re[0:0] - update \main_sdram_command_storage $0\main_sdram_command_storage[5:0] - update \main_sdram_command_re $0\main_sdram_command_re[0:0] - update \main_sdram_address_storage $0\main_sdram_address_storage[12:0] - update \main_sdram_address_re $0\main_sdram_address_re[0:0] - update \main_sdram_baddress_storage $0\main_sdram_baddress_storage[1:0] - update \main_sdram_baddress_re $0\main_sdram_baddress_re[0:0] - update \main_sdram_wrdata_storage $0\main_sdram_wrdata_storage[15:0] - update \main_sdram_wrdata_re $0\main_sdram_wrdata_re[0:0] - update \main_sdram_status $0\main_sdram_status[15:0] - update \main_sdram_dfi_p0_address $0\main_sdram_dfi_p0_address[12:0] - update \main_sdram_dfi_p0_bank $0\main_sdram_dfi_p0_bank[1:0] - update \main_sdram_dfi_p0_cas_n $0\main_sdram_dfi_p0_cas_n[0:0] - update \main_sdram_dfi_p0_cs_n $0\main_sdram_dfi_p0_cs_n[0:0] - update \main_sdram_dfi_p0_ras_n $0\main_sdram_dfi_p0_ras_n[0:0] - update \main_sdram_dfi_p0_we_n $0\main_sdram_dfi_p0_we_n[0:0] - update \main_sdram_dfi_p0_wrdata_en $0\main_sdram_dfi_p0_wrdata_en[0:0] - update \main_sdram_dfi_p0_rddata_en $0\main_sdram_dfi_p0_rddata_en[0:0] - update \main_sdram_cmd_payload_a $0\main_sdram_cmd_payload_a[12:0] - update \main_sdram_cmd_payload_ba $0\main_sdram_cmd_payload_ba[1:0] - update \main_sdram_cmd_payload_cas $0\main_sdram_cmd_payload_cas[0:0] - update \main_sdram_cmd_payload_ras $0\main_sdram_cmd_payload_ras[0:0] - update \main_sdram_cmd_payload_we $0\main_sdram_cmd_payload_we[0:0] - update \main_sdram_timer_count1 $0\main_sdram_timer_count1[9:0] - update \main_sdram_postponer_req_o $0\main_sdram_postponer_req_o[0:0] - update \main_sdram_postponer_count $0\main_sdram_postponer_count[0:0] - update \main_sdram_sequencer_done1 $0\main_sdram_sequencer_done1[0:0] - update \main_sdram_sequencer_counter $0\main_sdram_sequencer_counter[3:0] - update \main_sdram_sequencer_count $0\main_sdram_sequencer_count[0:0] - update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine0_cmd_buffer_source_valid $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_first $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_last $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine0_row $0\main_sdram_bankmachine0_row[12:0] - update \main_sdram_bankmachine0_row_opened $0\main_sdram_bankmachine0_row_opened[0:0] - update \main_sdram_bankmachine0_twtpcon_ready $0\main_sdram_bankmachine0_twtpcon_ready[0:0] - update \main_sdram_bankmachine0_twtpcon_count $0\main_sdram_bankmachine0_twtpcon_count[2:0] - update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine1_cmd_buffer_source_valid $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_first $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_last $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine1_row $0\main_sdram_bankmachine1_row[12:0] - update \main_sdram_bankmachine1_row_opened $0\main_sdram_bankmachine1_row_opened[0:0] - update \main_sdram_bankmachine1_twtpcon_ready $0\main_sdram_bankmachine1_twtpcon_ready[0:0] - update \main_sdram_bankmachine1_twtpcon_count $0\main_sdram_bankmachine1_twtpcon_count[2:0] - update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine2_cmd_buffer_source_valid $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_first $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_last $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine2_row $0\main_sdram_bankmachine2_row[12:0] - update \main_sdram_bankmachine2_row_opened $0\main_sdram_bankmachine2_row_opened[0:0] - update \main_sdram_bankmachine2_twtpcon_ready $0\main_sdram_bankmachine2_twtpcon_ready[0:0] - update \main_sdram_bankmachine2_twtpcon_count $0\main_sdram_bankmachine2_twtpcon_count[2:0] - update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine3_cmd_buffer_source_valid $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_first $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_last $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine3_row $0\main_sdram_bankmachine3_row[12:0] - update \main_sdram_bankmachine3_row_opened $0\main_sdram_bankmachine3_row_opened[0:0] - update \main_sdram_bankmachine3_twtpcon_ready $0\main_sdram_bankmachine3_twtpcon_ready[0:0] - update \main_sdram_bankmachine3_twtpcon_count $0\main_sdram_bankmachine3_twtpcon_count[2:0] - update \main_sdram_choose_cmd_grant $0\main_sdram_choose_cmd_grant[1:0] - update \main_sdram_choose_req_grant $0\main_sdram_choose_req_grant[1:0] - update \main_sdram_tccdcon_ready $0\main_sdram_tccdcon_ready[0:0] - update \main_sdram_tccdcon_count $0\main_sdram_tccdcon_count[0:0] - update \main_sdram_twtrcon_ready $0\main_sdram_twtrcon_ready[0:0] - update \main_sdram_twtrcon_count $0\main_sdram_twtrcon_count[2:0] - update \main_sdram_time0 $0\main_sdram_time0[4:0] - update \main_sdram_time1 $0\main_sdram_time1[3:0] - update \main_converter_counter $0\main_converter_counter[0:0] - update \main_converter_dat_r $0\main_converter_dat_r[31:0] - update \main_cmd_consumed $0\main_cmd_consumed[0:0] - update \main_wdata_consumed $0\main_wdata_consumed[0:0] - update \main_uart_phy_storage $0\main_uart_phy_storage[31:0] - update \main_uart_phy_re $0\main_uart_phy_re[0:0] - update \main_uart_phy_sink_ready $0\main_uart_phy_sink_ready[0:0] - update \main_uart_phy_uart_clk_txen $0\main_uart_phy_uart_clk_txen[0:0] - update \main_uart_phy_phase_accumulator_tx $0\main_uart_phy_phase_accumulator_tx[31:0] - update \main_uart_phy_tx_reg $0\main_uart_phy_tx_reg[7:0] - update \main_uart_phy_tx_bitcount $0\main_uart_phy_tx_bitcount[3:0] - update \main_uart_phy_tx_busy $0\main_uart_phy_tx_busy[0:0] - update \main_uart_phy_source_valid $0\main_uart_phy_source_valid[0:0] - update \main_uart_phy_source_payload_data $0\main_uart_phy_source_payload_data[7:0] - update \main_uart_phy_uart_clk_rxen $0\main_uart_phy_uart_clk_rxen[0:0] - update \main_uart_phy_phase_accumulator_rx $0\main_uart_phy_phase_accumulator_rx[31:0] - update \main_uart_phy_rx_r $0\main_uart_phy_rx_r[0:0] - update \main_uart_phy_rx_reg $0\main_uart_phy_rx_reg[7:0] - update \main_uart_phy_rx_bitcount $0\main_uart_phy_rx_bitcount[3:0] - update \main_uart_phy_rx_busy $0\main_uart_phy_rx_busy[0:0] - update \main_uart_tx_pending $0\main_uart_tx_pending[0:0] - update \main_uart_tx_old_trigger $0\main_uart_tx_old_trigger[0:0] - update \main_uart_rx_pending $0\main_uart_rx_pending[0:0] - update \main_uart_rx_old_trigger $0\main_uart_rx_old_trigger[0:0] - update \main_uart_eventmanager_storage $0\main_uart_eventmanager_storage[1:0] - update \main_uart_eventmanager_re $0\main_uart_eventmanager_re[0:0] - update \main_uart_tx_fifo_readable $0\main_uart_tx_fifo_readable[0:0] - update \main_uart_tx_fifo_level0 $0\main_uart_tx_fifo_level0[4:0] - update \main_uart_tx_fifo_produce $0\main_uart_tx_fifo_produce[3:0] - update \main_uart_tx_fifo_consume $0\main_uart_tx_fifo_consume[3:0] - update \main_uart_rx_fifo_readable $0\main_uart_rx_fifo_readable[0:0] - update \main_uart_rx_fifo_level0 $0\main_uart_rx_fifo_level0[4:0] - update \main_uart_rx_fifo_produce $0\main_uart_rx_fifo_produce[3:0] - update \main_uart_rx_fifo_consume $0\main_uart_rx_fifo_consume[3:0] - update \main_gpio_oe_storage $0\main_gpio_oe_storage[15:0] - update \main_gpio_oe_re $0\main_gpio_oe_re[0:0] - update \main_gpio_out_storage $0\main_gpio_out_storage[15:0] - update \main_gpio_out_re $0\main_gpio_out_re[0:0] - update \main_spi_master_miso $0\main_spi_master_miso[7:0] - update \main_spi_master_control_storage $0\main_spi_master_control_storage[15:0] - update \main_spi_master_control_re $0\main_spi_master_control_re[0:0] - update \main_spi_master_mosi_storage $0\main_spi_master_mosi_storage[7:0] - update \main_spi_master_mosi_re $0\main_spi_master_mosi_re[0:0] - update \main_spi_master_cs_storage $0\main_spi_master_cs_storage[0:0] - update \main_spi_master_cs_re $0\main_spi_master_cs_re[0:0] - update \main_spi_master_loopback_storage $0\main_spi_master_loopback_storage[0:0] - update \main_spi_master_loopback_re $0\main_spi_master_loopback_re[0:0] - update \main_spi_master_count $0\main_spi_master_count[2:0] - update \main_spi_master_clk_divider1 $0\main_spi_master_clk_divider1[15:0] - update \main_spi_master_mosi_data $0\main_spi_master_mosi_data[7:0] - update \main_spi_master_mosi_sel $0\main_spi_master_mosi_sel[2:0] - update \main_spi_master_miso_data $0\main_spi_master_miso_data[7:0] - update \main_dummy $0\main_dummy[35:0] - update \main_pwm0_counter $0\main_pwm0_counter[31:0] - update \main_pwm0_enable_storage $0\main_pwm0_enable_storage[0:0] - update \main_pwm0_enable_re $0\main_pwm0_enable_re[0:0] - update \main_pwm0_width_storage $0\main_pwm0_width_storage[31:0] - update \main_pwm0_width_re $0\main_pwm0_width_re[0:0] - update \main_pwm0_period_storage $0\main_pwm0_period_storage[31:0] - update \main_pwm0_period_re $0\main_pwm0_period_re[0:0] - update \main_pwm1_counter $0\main_pwm1_counter[31:0] - update \main_pwm1_enable_storage $0\main_pwm1_enable_storage[0:0] - update \main_pwm1_enable_re $0\main_pwm1_enable_re[0:0] - update \main_pwm1_width_storage $0\main_pwm1_width_storage[31:0] - update \main_pwm1_width_re $0\main_pwm1_width_re[0:0] - update \main_pwm1_period_storage $0\main_pwm1_period_storage[31:0] - update \main_pwm1_period_re $0\main_pwm1_period_re[0:0] - update \main_i2c_storage $0\main_i2c_storage[2:0] - update \main_i2c_re $0\main_i2c_re[0:0] - update \main_sdphy_clocker_storage $0\main_sdphy_clocker_storage[8:0] - update \main_sdphy_clocker_re $0\main_sdphy_clocker_re[0:0] - update \main_sdphy_clocker_clk0 $0\main_sdphy_clocker_clk0[0:0] - update \main_sdphy_clocker_clks $0\main_sdphy_clocker_clks[8:0] - update \main_sdphy_clocker_clk_d $0\main_sdphy_clocker_clk_d[0:0] - update \main_sdphy_init_count $0\main_sdphy_init_count[7:0] - update \main_sdphy_cmdw_count $0\main_sdphy_cmdw_count[7:0] - update \main_sdphy_cmdr_timeout $0\main_sdphy_cmdr_timeout[31:0] - update \main_sdphy_cmdr_count $0\main_sdphy_cmdr_count[7:0] - update \main_sdphy_cmdr_cmdr_run $0\main_sdphy_cmdr_cmdr_run[0:0] - update \main_sdphy_cmdr_cmdr_converter_source_first $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - update \main_sdphy_cmdr_cmdr_converter_source_last $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - update \main_sdphy_cmdr_cmdr_converter_source_payload_data $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - update \main_sdphy_cmdr_cmdr_converter_demux $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] - update \main_sdphy_cmdr_cmdr_converter_strobe_all $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - update \main_sdphy_cmdr_cmdr_buf_source_valid $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - update \main_sdphy_cmdr_cmdr_buf_source_first $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - update \main_sdphy_cmdr_cmdr_buf_source_last $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - update \main_sdphy_cmdr_cmdr_buf_source_payload_data $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - update \main_sdphy_cmdr_cmdr_reset $0\main_sdphy_cmdr_cmdr_reset[0:0] - update \main_sdphy_dataw_count $0\main_sdphy_dataw_count[7:0] - update \main_sdphy_dataw_crcr_run $0\main_sdphy_dataw_crcr_run[0:0] - update \main_sdphy_dataw_crcr_converter_source_first $0\main_sdphy_dataw_crcr_converter_source_first[0:0] - update \main_sdphy_dataw_crcr_converter_source_last $0\main_sdphy_dataw_crcr_converter_source_last[0:0] - update \main_sdphy_dataw_crcr_converter_source_payload_data $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - update \main_sdphy_dataw_crcr_converter_demux $0\main_sdphy_dataw_crcr_converter_demux[2:0] - update \main_sdphy_dataw_crcr_converter_strobe_all $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - update \main_sdphy_dataw_crcr_buf_source_valid $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] - update \main_sdphy_dataw_crcr_buf_source_first $0\main_sdphy_dataw_crcr_buf_source_first[0:0] - update \main_sdphy_dataw_crcr_buf_source_last $0\main_sdphy_dataw_crcr_buf_source_last[0:0] - update \main_sdphy_dataw_crcr_buf_source_payload_data $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - update \main_sdphy_dataw_crcr_reset $0\main_sdphy_dataw_crcr_reset[0:0] - update \main_sdphy_datar_timeout $0\main_sdphy_datar_timeout[31:0] - update \main_sdphy_datar_count $0\main_sdphy_datar_count[9:0] - update \main_sdphy_datar_datar_run $0\main_sdphy_datar_datar_run[0:0] - update \main_sdphy_datar_datar_converter_source_first $0\main_sdphy_datar_datar_converter_source_first[0:0] - update \main_sdphy_datar_datar_converter_source_last $0\main_sdphy_datar_datar_converter_source_last[0:0] - update \main_sdphy_datar_datar_converter_source_payload_data $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] - update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - update \main_sdphy_datar_datar_converter_demux $0\main_sdphy_datar_datar_converter_demux[0:0] - update \main_sdphy_datar_datar_converter_strobe_all $0\main_sdphy_datar_datar_converter_strobe_all[0:0] - update \main_sdphy_datar_datar_buf_source_valid $0\main_sdphy_datar_datar_buf_source_valid[0:0] - update \main_sdphy_datar_datar_buf_source_first $0\main_sdphy_datar_datar_buf_source_first[0:0] - update \main_sdphy_datar_datar_buf_source_last $0\main_sdphy_datar_datar_buf_source_last[0:0] - update \main_sdphy_datar_datar_buf_source_payload_data $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] - update \main_sdphy_datar_datar_reset $0\main_sdphy_datar_datar_reset[0:0] - update \main_sdcore_cmd_argument_storage $0\main_sdcore_cmd_argument_storage[31:0] - update \main_sdcore_cmd_argument_re $0\main_sdcore_cmd_argument_re[0:0] - update \main_sdcore_cmd_command_storage $0\main_sdcore_cmd_command_storage[31:0] - update \main_sdcore_cmd_command_re $0\main_sdcore_cmd_command_re[0:0] - update \main_sdcore_cmd_response_status $0\main_sdcore_cmd_response_status[127:0] - update \main_sdcore_block_length_storage $0\main_sdcore_block_length_storage[9:0] - update \main_sdcore_block_length_re $0\main_sdcore_block_length_re[0:0] - update \main_sdcore_block_count_storage $0\main_sdcore_block_count_storage[31:0] - update \main_sdcore_block_count_re $0\main_sdcore_block_count_re[0:0] - update \main_sdcore_crc7_inserter_crcreg0 $0\main_sdcore_crc7_inserter_crcreg0[6:0] - update \main_sdcore_crc16_inserter_cnt $0\main_sdcore_crc16_inserter_cnt[2:0] - update \main_sdcore_crc16_inserter_crc0_crcreg0 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - update \main_sdcore_crc16_inserter_crc1_crcreg0 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - update \main_sdcore_crc16_inserter_crc2_crcreg0 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - update \main_sdcore_crc16_inserter_crc3_crcreg0 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - update \main_sdcore_crc16_inserter_crctmp0 $0\main_sdcore_crc16_inserter_crctmp0[15:0] - update \main_sdcore_crc16_inserter_crctmp1 $0\main_sdcore_crc16_inserter_crctmp1[15:0] - update \main_sdcore_crc16_inserter_crctmp2 $0\main_sdcore_crc16_inserter_crctmp2[15:0] - update \main_sdcore_crc16_inserter_crctmp3 $0\main_sdcore_crc16_inserter_crctmp3[15:0] - update \main_sdcore_crc16_checker_val $0\main_sdcore_crc16_checker_val[7:0] - update \main_sdcore_crc16_checker_cnt $0\main_sdcore_crc16_checker_cnt[3:0] - update \main_sdcore_crc16_checker_crc0_crcreg0 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - update \main_sdcore_crc16_checker_crc1_crcreg0 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - update \main_sdcore_crc16_checker_crc2_crcreg0 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - update \main_sdcore_crc16_checker_crc3_crcreg0 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - update \main_sdcore_crc16_checker_crctmp0 $0\main_sdcore_crc16_checker_crctmp0[15:0] - update \main_sdcore_crc16_checker_crctmp1 $0\main_sdcore_crc16_checker_crctmp1[15:0] - update \main_sdcore_crc16_checker_crctmp2 $0\main_sdcore_crc16_checker_crctmp2[15:0] - update \main_sdcore_crc16_checker_crctmp3 $0\main_sdcore_crc16_checker_crctmp3[15:0] - update \main_sdcore_crc16_checker_fifo0 $0\main_sdcore_crc16_checker_fifo0[15:0] - update \main_sdcore_crc16_checker_fifo1 $0\main_sdcore_crc16_checker_fifo1[15:0] - update \main_sdcore_crc16_checker_fifo2 $0\main_sdcore_crc16_checker_fifo2[15:0] - update \main_sdcore_crc16_checker_fifo3 $0\main_sdcore_crc16_checker_fifo3[15:0] - update \main_sdcore_cmd_count $0\main_sdcore_cmd_count[2:0] - update \main_sdcore_cmd_done $0\main_sdcore_cmd_done[0:0] - update \main_sdcore_cmd_error $0\main_sdcore_cmd_error[0:0] - update \main_sdcore_cmd_timeout $0\main_sdcore_cmd_timeout[0:0] - update \main_sdcore_data_count $0\main_sdcore_data_count[31:0] - update \main_sdcore_data_done $0\main_sdcore_data_done[0:0] - update \main_sdcore_data_error $0\main_sdcore_data_error[0:0] - update \main_sdcore_data_timeout $0\main_sdcore_data_timeout[0:0] - update \main_sdblock2mem_fifo_level $0\main_sdblock2mem_fifo_level[5:0] - update \main_sdblock2mem_fifo_produce $0\main_sdblock2mem_fifo_produce[4:0] - update \main_sdblock2mem_fifo_consume $0\main_sdblock2mem_fifo_consume[4:0] - update \main_sdblock2mem_converter_source_first $0\main_sdblock2mem_converter_source_first[0:0] - update \main_sdblock2mem_converter_source_last $0\main_sdblock2mem_converter_source_last[0:0] - update \main_sdblock2mem_converter_source_payload_data $0\main_sdblock2mem_converter_source_payload_data[31:0] - update \main_sdblock2mem_converter_source_payload_valid_token_count $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] - update \main_sdblock2mem_converter_demux $0\main_sdblock2mem_converter_demux[1:0] - update \main_sdblock2mem_converter_strobe_all $0\main_sdblock2mem_converter_strobe_all[0:0] - update \main_sdblock2mem_wishbonedmawriter_base_storage $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - update \main_sdblock2mem_wishbonedmawriter_base_re $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - update \main_sdblock2mem_wishbonedmawriter_length_storage $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - update \main_sdblock2mem_wishbonedmawriter_length_re $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - update \main_sdblock2mem_wishbonedmawriter_enable_storage $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - update \main_sdblock2mem_wishbonedmawriter_enable_re $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - update \main_sdblock2mem_wishbonedmawriter_loop_storage $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - update \main_sdblock2mem_wishbonedmawriter_loop_re $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - update \main_sdblock2mem_wishbonedmawriter_offset $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] - update \main_sdmem2block_dma_data $0\main_sdmem2block_dma_data[31:0] - update \main_sdmem2block_dma_base_storage $0\main_sdmem2block_dma_base_storage[63:0] - update \main_sdmem2block_dma_base_re $0\main_sdmem2block_dma_base_re[0:0] - update \main_sdmem2block_dma_length_storage $0\main_sdmem2block_dma_length_storage[31:0] - update \main_sdmem2block_dma_length_re $0\main_sdmem2block_dma_length_re[0:0] - update \main_sdmem2block_dma_enable_storage $0\main_sdmem2block_dma_enable_storage[0:0] - update \main_sdmem2block_dma_enable_re $0\main_sdmem2block_dma_enable_re[0:0] - update \main_sdmem2block_dma_loop_storage $0\main_sdmem2block_dma_loop_storage[0:0] - update \main_sdmem2block_dma_loop_re $0\main_sdmem2block_dma_loop_re[0:0] - update \main_sdmem2block_dma_offset $0\main_sdmem2block_dma_offset[31:0] - update \main_sdmem2block_converter_mux $0\main_sdmem2block_converter_mux[1:0] - update \main_sdmem2block_fifo_level $0\main_sdmem2block_fifo_level[5:0] - update \main_sdmem2block_fifo_produce $0\main_sdmem2block_fifo_produce[4:0] - update \main_sdmem2block_fifo_consume $0\main_sdmem2block_fifo_consume[4:0] - update \libresocsim_miso $0\libresocsim_miso[7:0] - update \libresocsim_control_storage $0\libresocsim_control_storage[15:0] - update \libresocsim_control_re $0\libresocsim_control_re[0:0] - update \libresocsim_mosi_storage $0\libresocsim_mosi_storage[7:0] - update \libresocsim_mosi_re $0\libresocsim_mosi_re[0:0] - update \libresocsim_cs_storage $0\libresocsim_cs_storage[0:0] - update \libresocsim_cs_re $0\libresocsim_cs_re[0:0] - update \libresocsim_loopback_storage $0\libresocsim_loopback_storage[0:0] - update \libresocsim_loopback_re $0\libresocsim_loopback_re[0:0] - update \libresocsim_count $0\libresocsim_count[2:0] - update \libresocsim_clk_divider1 $0\libresocsim_clk_divider1[15:0] - update \libresocsim_mosi_data $0\libresocsim_mosi_data[7:0] - update \libresocsim_mosi_sel $0\libresocsim_mosi_sel[2:0] - update \libresocsim_miso_data $0\libresocsim_miso_data[7:0] - update \libresocsim_storage $0\libresocsim_storage[15:0] - update \libresocsim_re $0\libresocsim_re[0:0] - update \builder_converter0_state $0\builder_converter0_state[0:0] - update \builder_converter1_state $0\builder_converter1_state[0:0] - update \builder_converter2_state $0\builder_converter2_state[0:0] - update \builder_refresher_state $0\builder_refresher_state[1:0] - update \builder_bankmachine0_state $0\builder_bankmachine0_state[2:0] - update \builder_bankmachine1_state $0\builder_bankmachine1_state[2:0] - update \builder_bankmachine2_state $0\builder_bankmachine2_state[2:0] - update \builder_bankmachine3_state $0\builder_bankmachine3_state[2:0] - update \builder_multiplexer_state $0\builder_multiplexer_state[2:0] - update \builder_new_master_wdata_ready $0\builder_new_master_wdata_ready[0:0] - update \builder_new_master_rdata_valid0 $0\builder_new_master_rdata_valid0[0:0] - update \builder_new_master_rdata_valid1 $0\builder_new_master_rdata_valid1[0:0] - update \builder_new_master_rdata_valid2 $0\builder_new_master_rdata_valid2[0:0] - update \builder_new_master_rdata_valid3 $0\builder_new_master_rdata_valid3[0:0] - update \builder_converter_state $0\builder_converter_state[0:0] - update \builder_spimaster0_state $0\builder_spimaster0_state[1:0] - update \builder_sdphy_sdphyinit_state $0\builder_sdphy_sdphyinit_state[0:0] - update \builder_sdphy_sdphycmdw_state $0\builder_sdphy_sdphycmdw_state[1:0] - update \builder_sdphy_sdphycmdr_state $0\builder_sdphy_sdphycmdr_state[2:0] - update \builder_sdphy_sdphycrcr_state $0\builder_sdphy_sdphycrcr_state[0:0] - update \builder_sdphy_fsm_state $0\builder_sdphy_fsm_state[2:0] - update \builder_sdphy_sdphydatar_state $0\builder_sdphy_sdphydatar_state[2:0] - update \builder_sdcore_crcupstreaminserter_state $0\builder_sdcore_crcupstreaminserter_state[0:0] - update \builder_sdcore_fsm_state $0\builder_sdcore_fsm_state[2:0] - update \builder_sdblock2memdma_state $0\builder_sdblock2memdma_state[1:0] - update \builder_sdmem2blockdma_fsm_state $0\builder_sdmem2blockdma_fsm_state[0:0] - update \builder_sdmem2blockdma_resetinserter_state $0\builder_sdmem2blockdma_resetinserter_state[1:0] - update \builder_spimaster1_state $0\builder_spimaster1_state[1:0] - update \builder_libresocsim_adr $0\builder_libresocsim_adr[13:0] - update \builder_libresocsim_we $0\builder_libresocsim_we[0:0] - update \builder_libresocsim_dat_w $0\builder_libresocsim_dat_w[7:0] - update \builder_grant $0\builder_grant[2:0] - update \builder_slave_sel_r $0\builder_slave_sel_r[4:0] - update \builder_count $0\builder_count[19:0] - update \builder_interface0_bank_bus_dat_r $0\builder_interface0_bank_bus_dat_r[7:0] - update \builder_interface1_bank_bus_dat_r $0\builder_interface1_bank_bus_dat_r[7:0] - update \builder_interface2_bank_bus_dat_r $0\builder_interface2_bank_bus_dat_r[7:0] - update \builder_interface3_bank_bus_dat_r $0\builder_interface3_bank_bus_dat_r[7:0] - update \builder_interface4_bank_bus_dat_r $0\builder_interface4_bank_bus_dat_r[7:0] - update \builder_interface5_bank_bus_dat_r $0\builder_interface5_bank_bus_dat_r[7:0] - update \builder_interface6_bank_bus_dat_r $0\builder_interface6_bank_bus_dat_r[7:0] - update \builder_interface7_bank_bus_dat_r $0\builder_interface7_bank_bus_dat_r[7:0] - update \builder_interface8_bank_bus_dat_r $0\builder_interface8_bank_bus_dat_r[7:0] - update \builder_interface9_bank_bus_dat_r $0\builder_interface9_bank_bus_dat_r[7:0] - update \builder_interface10_bank_bus_dat_r $0\builder_interface10_bank_bus_dat_r[7:0] - update \builder_interface11_bank_bus_dat_r $0\builder_interface11_bank_bus_dat_r[7:0] - update \builder_interface12_bank_bus_dat_r $0\builder_interface12_bank_bus_dat_r[7:0] - update \builder_interface13_bank_bus_dat_r $0\builder_interface13_bank_bus_dat_r[7:0] - update \builder_interface14_bank_bus_dat_r $0\builder_interface14_bank_bus_dat_r[7:0] - update \builder_state $0\builder_state[1:0] - update \builder_multiregimpl0_regs0 $0\builder_multiregimpl0_regs0[0:0] - update \builder_multiregimpl0_regs1 $0\builder_multiregimpl0_regs1[0:0] - update \builder_multiregimpl1_regs0 $0\builder_multiregimpl1_regs0[0:0] - update \builder_multiregimpl1_regs1 $0\builder_multiregimpl1_regs1[0:0] - update \builder_multiregimpl2_regs0 $0\builder_multiregimpl2_regs0[0:0] - update \builder_multiregimpl2_regs1 $0\builder_multiregimpl2_regs1[0:0] - update \builder_multiregimpl3_regs0 $0\builder_multiregimpl3_regs0[0:0] - update \builder_multiregimpl3_regs1 $0\builder_multiregimpl3_regs1[0:0] - update \builder_multiregimpl4_regs0 $0\builder_multiregimpl4_regs0[0:0] - update \builder_multiregimpl4_regs1 $0\builder_multiregimpl4_regs1[0:0] - update \builder_multiregimpl5_regs0 $0\builder_multiregimpl5_regs0[0:0] - update \builder_multiregimpl5_regs1 $0\builder_multiregimpl5_regs1[0:0] - update \builder_multiregimpl6_regs0 $0\builder_multiregimpl6_regs0[0:0] - update \builder_multiregimpl6_regs1 $0\builder_multiregimpl6_regs1[0:0] - update \builder_multiregimpl7_regs0 $0\builder_multiregimpl7_regs0[0:0] - update \builder_multiregimpl7_regs1 $0\builder_multiregimpl7_regs1[0:0] - update \builder_multiregimpl8_regs0 $0\builder_multiregimpl8_regs0[0:0] - update \builder_multiregimpl8_regs1 $0\builder_multiregimpl8_regs1[0:0] - update \builder_multiregimpl9_regs0 $0\builder_multiregimpl9_regs0[0:0] - update \builder_multiregimpl9_regs1 $0\builder_multiregimpl9_regs1[0:0] - update \builder_multiregimpl10_regs0 $0\builder_multiregimpl10_regs0[0:0] - update \builder_multiregimpl10_regs1 $0\builder_multiregimpl10_regs1[0:0] - update \builder_multiregimpl11_regs0 $0\builder_multiregimpl11_regs0[0:0] - update \builder_multiregimpl11_regs1 $0\builder_multiregimpl11_regs1[0:0] - update \builder_multiregimpl12_regs0 $0\builder_multiregimpl12_regs0[0:0] - update \builder_multiregimpl12_regs1 $0\builder_multiregimpl12_regs1[0:0] - update \builder_multiregimpl13_regs0 $0\builder_multiregimpl13_regs0[0:0] - update \builder_multiregimpl13_regs1 $0\builder_multiregimpl13_regs1[0:0] - update \builder_multiregimpl14_regs0 $0\builder_multiregimpl14_regs0[0:0] - update \builder_multiregimpl14_regs1 $0\builder_multiregimpl14_regs1[0:0] - update \builder_multiregimpl15_regs0 $0\builder_multiregimpl15_regs0[0:0] - update \builder_multiregimpl15_regs1 $0\builder_multiregimpl15_regs1[0:0] - update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0] - update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] - end - attribute \src "ls180.v:742.5-742.49" - process $proc$ls180.v:742$3056 - assign { } { } - assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:743.5-743.49" - process $proc$ls180.v:743$3057 - assign { } { } - assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:744.5-744.48" - process $proc$ls180.v:744$3058 - assign { } { } - assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] - end - attribute \src "ls180.v:748.11-748.46" - process $proc$ls180.v:748$3059 - assign { } { } - assign $1\main_sdram_choose_req_valids[3:0] 4'0000 - sync always - sync init - update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] - end - attribute \src "ls180.v:750.11-750.45" - process $proc$ls180.v:750$3060 - assign { } { } - assign $1\main_sdram_choose_req_grant[1:0] 2'00 - sync always - sync init - update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] - end - attribute \src "ls180.v:752.12-752.36" - process $proc$ls180.v:752$3061 - assign { } { } - assign $0\main_sdram_nop_a[12:0] 13'0000000000000 - sync always - update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] - sync init - end - attribute \src "ls180.v:753.11-753.35" - process $proc$ls180.v:753$3062 - assign { } { } - assign $0\main_sdram_nop_ba[1:0] 2'00 - sync always - update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] - sync init - end - attribute \src "ls180.v:754.11-754.40" - process $proc$ls180.v:754$3063 - assign { } { } - assign $1\main_sdram_steerer_sel[1:0] 2'00 - sync always - sync init - update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] - end - attribute \src "ls180.v:755.5-755.31" - process $proc$ls180.v:755$3064 - assign { } { } - assign $0\main_sdram_steerer0[0:0] 1'1 - sync always - update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] - sync init - end - attribute \src "ls180.v:756.5-756.31" - process $proc$ls180.v:756$3065 - assign { } { } - assign $0\main_sdram_steerer1[0:0] 1'1 - sync always - update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0] - sync init - end - attribute \src "ls180.v:758.32-758.63" - process $proc$ls180.v:758$3066 - assign { } { } - assign $0\main_sdram_trrdcon_ready[0:0] 1'1 - sync always - update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0] - sync init - end - attribute \src "ls180.v:76.5-76.46" - process $proc$ls180.v:76$2782 - assign { } { } - assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0] - sync init - end - attribute \src "ls180.v:760.32-760.63" - process $proc$ls180.v:760$3067 - assign { } { } - assign $0\main_sdram_tfawcon_ready[0:0] 1'1 - sync always - update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0] - sync init - end - attribute \src "ls180.v:762.32-762.63" - process $proc$ls180.v:762$3068 - assign { } { } - assign $1\main_sdram_tccdcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] - end - attribute \src "ls180.v:763.5-763.36" - process $proc$ls180.v:763$3069 - assign { } { } - assign $1\main_sdram_tccdcon_count[0:0] 1'0 - sync always - sync init - update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] - end - attribute \src "ls180.v:765.32-765.63" - process $proc$ls180.v:765$3070 - assign { } { } - assign $1\main_sdram_twtrcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] - end - attribute \src "ls180.v:766.11-766.42" - process $proc$ls180.v:766$3071 - assign { } { } - assign $1\main_sdram_twtrcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] - end - attribute \src "ls180.v:769.5-769.26" - process $proc$ls180.v:769$3072 - assign { } { } - assign $1\main_sdram_en0[0:0] 1'0 - sync always - sync init - update \main_sdram_en0 $1\main_sdram_en0[0:0] - end - attribute \src "ls180.v:771.11-771.34" - process $proc$ls180.v:771$3073 - assign { } { } - assign $1\main_sdram_time0[4:0] 5'00000 - sync always - sync init - update \main_sdram_time0 $1\main_sdram_time0[4:0] - end - attribute \src "ls180.v:772.5-772.26" - process $proc$ls180.v:772$3074 - assign { } { } - assign $1\main_sdram_en1[0:0] 1'0 - sync always - sync init - update \main_sdram_en1 $1\main_sdram_en1[0:0] - end - attribute \src "ls180.v:774.11-774.34" - process $proc$ls180.v:774$3075 - assign { } { } - assign $1\main_sdram_time1[3:0] 4'0000 - sync always - sync init - update \main_sdram_time1 $1\main_sdram_time1[3:0] - end - attribute \src "ls180.v:795.5-795.29" - process $proc$ls180.v:795$3076 - assign { } { } - assign $1\main_wb_sdram_ack[0:0] 1'0 - sync always - sync init - update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] - end - attribute \src "ls180.v:799.5-799.29" - process $proc$ls180.v:799$3077 - assign { } { } - assign $0\main_wb_sdram_err[0:0] 1'0 - sync always - update \main_wb_sdram_err $0\main_wb_sdram_err[0:0] - sync init - end - attribute \src "ls180.v:800.12-800.40" - process $proc$ls180.v:800$3078 - assign { } { } - assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] - end - attribute \src "ls180.v:801.12-801.42" - process $proc$ls180.v:801$3079 - assign { } { } - assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 - sync always - sync init - update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] - end - attribute \src "ls180.v:803.11-803.38" - process $proc$ls180.v:803$3080 - assign { } { } - assign $1\main_litedram_wb_sel[1:0] 2'00 - sync always - sync init - update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] - end - attribute \src "ls180.v:804.5-804.32" - process $proc$ls180.v:804$3081 - assign { } { } - assign $1\main_litedram_wb_cyc[0:0] 1'0 - sync always - sync init - update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] - end - attribute \src "ls180.v:805.5-805.32" - process $proc$ls180.v:805$3082 - assign { } { } - assign $1\main_litedram_wb_stb[0:0] 1'0 - sync always - sync init - update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] - end - attribute \src "ls180.v:807.5-807.31" - process $proc$ls180.v:807$3083 - assign { } { } - assign $1\main_litedram_wb_we[0:0] 1'0 - sync always - sync init - update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] - end - attribute \src "ls180.v:808.5-808.31" - process $proc$ls180.v:808$3084 - assign { } { } - assign $1\main_converter_skip[0:0] 1'0 - sync always - sync init - update \main_converter_skip $1\main_converter_skip[0:0] - end - attribute \src "ls180.v:809.5-809.34" - process $proc$ls180.v:809$3085 - assign { } { } - assign $1\main_converter_counter[0:0] 1'0 - sync always - sync init - update \main_converter_counter $1\main_converter_counter[0:0] - end - attribute \src "ls180.v:811.12-811.40" - process $proc$ls180.v:811$3086 - assign { } { } - assign $1\main_converter_dat_r[31:0] 0 - sync always - sync init - update \main_converter_dat_r $1\main_converter_dat_r[31:0] - end - attribute \src "ls180.v:812.5-812.29" - process $proc$ls180.v:812$3087 - assign { } { } - assign $1\main_cmd_consumed[0:0] 1'0 - sync always - sync init - update \main_cmd_consumed $1\main_cmd_consumed[0:0] - end - attribute \src "ls180.v:813.5-813.31" - process $proc$ls180.v:813$3088 - assign { } { } - assign $1\main_wdata_consumed[0:0] 1'0 - sync always - sync init - update \main_wdata_consumed $1\main_wdata_consumed[0:0] - end - attribute \src "ls180.v:817.12-817.47" - process $proc$ls180.v:817$3089 - assign { } { } - assign $1\main_uart_phy_storage[31:0] 9895604 - sync always - sync init - update \main_uart_phy_storage $1\main_uart_phy_storage[31:0] - end - attribute \src "ls180.v:818.5-818.28" - process $proc$ls180.v:818$3090 - assign { } { } - assign $1\main_uart_phy_re[0:0] 1'0 - sync always - sync init - update \main_uart_phy_re $1\main_uart_phy_re[0:0] - end - attribute \src "ls180.v:820.5-820.36" - process $proc$ls180.v:820$3091 - assign { } { } - assign $1\main_uart_phy_sink_ready[0:0] 1'0 - sync always - sync init - update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0] - end - attribute \src "ls180.v:824.5-824.39" - process $proc$ls180.v:824$3092 - assign { } { } - assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0 - sync always - sync init - update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0] - end - attribute \src "ls180.v:825.12-825.54" - process $proc$ls180.v:825$3093 - assign { } { } - assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0 - sync always - sync init - update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0] - end - attribute \src "ls180.v:826.11-826.38" - process $proc$ls180.v:826$3094 - assign { } { } - assign $1\main_uart_phy_tx_reg[7:0] 8'00000000 - sync always - sync init - update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0] - end - attribute \src "ls180.v:827.11-827.43" - process $proc$ls180.v:827$3095 - assign { } { } - assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000 - sync always - sync init - update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0] - end - attribute \src "ls180.v:828.5-828.33" - process $proc$ls180.v:828$3096 - assign { } { } - assign $1\main_uart_phy_tx_busy[0:0] 1'0 - sync always - sync init - update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0] - end - attribute \src "ls180.v:829.5-829.38" - process $proc$ls180.v:829$3097 - assign { } { } - assign $1\main_uart_phy_source_valid[0:0] 1'0 - sync always - sync init - update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0] - end - attribute \src "ls180.v:83.5-83.46" - process $proc$ls180.v:83$2783 - assign { } { } - assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0] - end - attribute \src "ls180.v:831.5-831.38" - process $proc$ls180.v:831$3098 - assign { } { } - assign $0\main_uart_phy_source_first[0:0] 1'0 - sync always - update \main_uart_phy_source_first $0\main_uart_phy_source_first[0:0] - sync init - end - attribute \src "ls180.v:832.5-832.37" - process $proc$ls180.v:832$3099 - assign { } { } - assign $0\main_uart_phy_source_last[0:0] 1'0 - sync always - update \main_uart_phy_source_last $0\main_uart_phy_source_last[0:0] - sync init - end - attribute \src "ls180.v:833.11-833.51" - process $proc$ls180.v:833$3100 - assign { } { } - assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0] - end - attribute \src "ls180.v:834.5-834.39" - process $proc$ls180.v:834$3101 - assign { } { } - assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0 - sync always - sync init - update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0] - end - attribute \src "ls180.v:835.12-835.54" - process $proc$ls180.v:835$3102 - assign { } { } - assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0 - sync always - sync init - update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0] - end - attribute \src "ls180.v:837.5-837.30" - process $proc$ls180.v:837$3103 - assign { } { } - assign $1\main_uart_phy_rx_r[0:0] 1'0 - sync always - sync init - update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0] - end - attribute \src "ls180.v:838.11-838.38" - process $proc$ls180.v:838$3104 - assign { } { } - assign $1\main_uart_phy_rx_reg[7:0] 8'00000000 - sync always - sync init - update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0] - end - attribute \src "ls180.v:839.11-839.43" - process $proc$ls180.v:839$3105 - assign { } { } - assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000 - sync always - sync init - update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0] - end - attribute \src "ls180.v:840.5-840.33" - process $proc$ls180.v:840$3106 - assign { } { } - assign $1\main_uart_phy_rx_busy[0:0] 1'0 - sync always - sync init - update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0] - end - attribute \src "ls180.v:851.5-851.32" - process $proc$ls180.v:851$3107 - assign { } { } - assign $1\main_uart_tx_pending[0:0] 1'0 - sync always - sync init - update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] - end - attribute \src "ls180.v:853.5-853.30" - process $proc$ls180.v:853$3108 - assign { } { } - assign $1\main_uart_tx_clear[0:0] 1'0 - sync always - sync init - update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] - end - attribute \src "ls180.v:854.5-854.36" - process $proc$ls180.v:854$3109 - assign { } { } - assign $1\main_uart_tx_old_trigger[0:0] 1'0 - sync always - sync init - update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] - end - attribute \src "ls180.v:856.5-856.32" - process $proc$ls180.v:856$3110 - assign { } { } - assign $1\main_uart_rx_pending[0:0] 1'0 - sync always - sync init - update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] - end - attribute \src "ls180.v:858.5-858.30" - process $proc$ls180.v:858$3111 - assign { } { } - assign $1\main_uart_rx_clear[0:0] 1'0 - sync always - sync init - update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] - end - attribute \src "ls180.v:859.5-859.36" - process $proc$ls180.v:859$3112 - assign { } { } - assign $1\main_uart_rx_old_trigger[0:0] 1'0 - sync always - sync init - update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] - end - attribute \src "ls180.v:863.11-863.49" - process $proc$ls180.v:863$3113 - assign { } { } - assign $1\main_uart_eventmanager_status_w[1:0] 2'00 - sync always - sync init - update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] - end - attribute \src "ls180.v:867.11-867.50" - process $proc$ls180.v:867$3114 - assign { } { } - assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 - sync always - sync init - update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] - end - attribute \src "ls180.v:868.11-868.48" - process $proc$ls180.v:868$3115 - assign { } { } - assign $1\main_uart_eventmanager_storage[1:0] 2'00 - sync always - sync init - update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] - end - attribute \src "ls180.v:869.5-869.37" - process $proc$ls180.v:869$3116 - assign { } { } - assign $1\main_uart_eventmanager_re[0:0] 1'0 - sync always - sync init - update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0] - end - attribute \src "ls180.v:87.5-87.46" - process $proc$ls180.v:87$2784 - assign { } { } - assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0] - sync init - end - attribute \src "ls180.v:886.5-886.40" - process $proc$ls180.v:886$3117 - assign { } { } - assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 - sync always - update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] - sync init - end - attribute \src "ls180.v:887.5-887.39" - process $proc$ls180.v:887$3118 - assign { } { } - assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 - sync always - update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] - sync init - end - attribute \src "ls180.v:895.5-895.38" - process $proc$ls180.v:895$3119 - assign { } { } - assign $1\main_uart_tx_fifo_readable[0:0] 1'0 - sync always - sync init - update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] - end - attribute \src "ls180.v:902.11-902.42" - process $proc$ls180.v:902$3120 - assign { } { } - assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 - sync always - sync init - update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] - end - attribute \src "ls180.v:903.5-903.37" - process $proc$ls180.v:903$3121 - assign { } { } - assign $0\main_uart_tx_fifo_replace[0:0] 1'0 - sync always - update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:904.11-904.43" - process $proc$ls180.v:904$3122 - assign { } { } - assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 - sync always - sync init - update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] - end - attribute \src "ls180.v:905.11-905.43" - process $proc$ls180.v:905$3123 - assign { } { } - assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 - sync always - sync init - update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] - end - attribute \src "ls180.v:906.11-906.46" - process $proc$ls180.v:906$3124 - assign { } { } - assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 - sync always - sync init - update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:932.5-932.38" - process $proc$ls180.v:932$3125 - assign { } { } - assign $1\main_uart_rx_fifo_readable[0:0] 1'0 - sync always - sync init - update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] - end - attribute \src "ls180.v:939.11-939.42" - process $proc$ls180.v:939$3126 - assign { } { } - assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 - sync always - sync init - update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] - end - attribute \src "ls180.v:940.5-940.37" - process $proc$ls180.v:940$3127 - assign { } { } - assign $0\main_uart_rx_fifo_replace[0:0] 1'0 - sync always - update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:941.11-941.43" - process $proc$ls180.v:941$3128 - assign { } { } - assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 - sync always - sync init - update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] - end - attribute \src "ls180.v:942.11-942.43" - process $proc$ls180.v:942$3129 - assign { } { } - assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 - sync always - sync init - update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] - end - attribute \src "ls180.v:943.11-943.46" - process $proc$ls180.v:943$3130 - assign { } { } - assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 - sync always - sync init - update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:958.5-958.27" - process $proc$ls180.v:958$3131 - assign { } { } - assign $0\main_uart_reset[0:0] 1'0 - sync always - update \main_uart_reset $0\main_uart_reset[0:0] - sync init - end - attribute \src "ls180.v:959.12-959.40" - process $proc$ls180.v:959$3132 - assign { } { } - assign $1\main_gpio_oe_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpio_oe_storage $1\main_gpio_oe_storage[15:0] - end - attribute \src "ls180.v:960.5-960.27" - process $proc$ls180.v:960$3133 - assign { } { } - assign $1\main_gpio_oe_re[0:0] 1'0 - sync always - sync init - update \main_gpio_oe_re $1\main_gpio_oe_re[0:0] - end - attribute \src "ls180.v:961.12-961.36" - process $proc$ls180.v:961$3134 - assign { } { } - assign $1\main_gpio_status[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpio_status $1\main_gpio_status[15:0] - end - attribute \src "ls180.v:963.12-963.41" - process $proc$ls180.v:963$3135 - assign { } { } - assign $1\main_gpio_out_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpio_out_storage $1\main_gpio_out_storage[15:0] - end - attribute \src "ls180.v:964.5-964.28" - process $proc$ls180.v:964$3136 - assign { } { } - assign $1\main_gpio_out_re[0:0] 1'0 - sync always - sync init - update \main_gpio_out_re $1\main_gpio_out_re[0:0] - end - attribute \src "ls180.v:970.5-970.33" - process $proc$ls180.v:970$3137 - assign { } { } - assign $1\main_spi_master_done0[0:0] 1'0 - sync always - sync init - update \main_spi_master_done0 $1\main_spi_master_done0[0:0] - end - attribute \src "ls180.v:971.5-971.31" - process $proc$ls180.v:971$3138 - assign { } { } - assign $1\main_spi_master_irq[0:0] 1'0 - sync always - sync init - update \main_spi_master_irq $1\main_spi_master_irq[0:0] - end - attribute \src "ls180.v:973.11-973.38" - process $proc$ls180.v:973$3139 - assign { } { } - assign $1\main_spi_master_miso[7:0] 8'00000000 - sync always - sync init - update \main_spi_master_miso $1\main_spi_master_miso[7:0] - end - attribute \src "ls180.v:976.12-976.48" - process $proc$ls180.v:976$3140 - assign { } { } - assign $0\main_spi_master_clk_divider0[15:0] 16'0000000000000111 - sync always - update \main_spi_master_clk_divider0 $0\main_spi_master_clk_divider0[15:0] - sync init - end - attribute \src "ls180.v:977.5-977.34" - process $proc$ls180.v:977$3141 - assign { } { } - assign $1\main_spi_master_start1[0:0] 1'0 - sync always - sync init - update \main_spi_master_start1 $1\main_spi_master_start1[0:0] - end - attribute \src "ls180.v:979.12-979.51" - process $proc$ls180.v:979$3142 - assign { } { } - assign $1\main_spi_master_control_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_spi_master_control_storage $1\main_spi_master_control_storage[15:0] - end - attribute \src "ls180.v:980.5-980.38" - process $proc$ls180.v:980$3143 - assign { } { } - assign $1\main_spi_master_control_re[0:0] 1'0 - sync always - sync init - update \main_spi_master_control_re $1\main_spi_master_control_re[0:0] - end - attribute \src "ls180.v:984.11-984.46" - process $proc$ls180.v:984$3144 - assign { } { } - assign $1\main_spi_master_mosi_storage[7:0] 8'00000000 - sync always - sync init - update \main_spi_master_mosi_storage $1\main_spi_master_mosi_storage[7:0] - end - attribute \src "ls180.v:985.5-985.35" - process $proc$ls180.v:985$3145 - assign { } { } - assign $1\main_spi_master_mosi_re[0:0] 1'0 - sync always - sync init - update \main_spi_master_mosi_re $1\main_spi_master_mosi_re[0:0] - end - attribute \src "ls180.v:989.5-989.38" - process $proc$ls180.v:989$3146 - assign { } { } - assign $1\main_spi_master_cs_storage[0:0] 1'1 - sync always - sync init - update \main_spi_master_cs_storage $1\main_spi_master_cs_storage[0:0] - end - attribute \src "ls180.v:990.5-990.33" - process $proc$ls180.v:990$3147 - assign { } { } - assign $1\main_spi_master_cs_re[0:0] 1'0 - sync always - sync init - update \main_spi_master_cs_re $1\main_spi_master_cs_re[0:0] - end - attribute \src "ls180.v:991.5-991.44" - process $proc$ls180.v:991$3148 - assign { } { } - assign $1\main_spi_master_loopback_storage[0:0] 1'0 - sync always - sync init - update \main_spi_master_loopback_storage $1\main_spi_master_loopback_storage[0:0] - end - attribute \src "ls180.v:992.5-992.39" - process $proc$ls180.v:992$3149 - assign { } { } - assign $1\main_spi_master_loopback_re[0:0] 1'0 - sync always - sync init - update \main_spi_master_loopback_re $1\main_spi_master_loopback_re[0:0] - end - attribute \src "ls180.v:993.5-993.38" - process $proc$ls180.v:993$3150 - assign { } { } - assign $1\main_spi_master_clk_enable[0:0] 1'0 - sync always - sync init - update \main_spi_master_clk_enable $1\main_spi_master_clk_enable[0:0] - end - attribute \src "ls180.v:994.5-994.37" - process $proc$ls180.v:994$3151 - assign { } { } - assign $1\main_spi_master_cs_enable[0:0] 1'0 - sync always - sync init - update \main_spi_master_cs_enable $1\main_spi_master_cs_enable[0:0] - end - attribute \src "ls180.v:995.11-995.39" - process $proc$ls180.v:995$3152 - assign { } { } - assign $1\main_spi_master_count[2:0] 3'000 - sync always - sync init - update \main_spi_master_count $1\main_spi_master_count[2:0] - end - attribute \src "ls180.v:996.5-996.38" - process $proc$ls180.v:996$3153 - assign { } { } - assign $1\main_spi_master_mosi_latch[0:0] 1'0 - sync always - sync init - update \main_spi_master_mosi_latch $1\main_spi_master_mosi_latch[0:0] - end - attribute \src "ls180.v:997.5-997.38" - process $proc$ls180.v:997$3154 - assign { } { } - assign $1\main_spi_master_miso_latch[0:0] 1'0 - sync always - sync init - update \main_spi_master_miso_latch $1\main_spi_master_miso_latch[0:0] - end - attribute \src "ls180.v:998.12-998.48" - process $proc$ls180.v:998$3155 - assign { } { } - assign $1\main_spi_master_clk_divider1[15:0] 16'0000000000000000 - sync always - sync init - update \main_spi_master_clk_divider1 $1\main_spi_master_clk_divider1[15:0] - end - connect \main_libresocsim_libresoc_reset \main_libresocsim_reset - connect \main_libresocsim_libresoc_clk_sel \sys_clksel_i - connect \sys_pll_48_o \main_libresocsim_libresoc_pll_48_o - connect \uart_tx \main_libresocsim_libresoc_constraintmanager1_uart0_tx - connect \main_libresocsim_libresoc_constraintmanager1_uart0_rx \uart_rx - connect \main_libresocsim_libresoc_constraintmanager1_gpio0_i \gpio_i - connect \gpio_o \main_libresocsim_libresoc_constraintmanager1_gpio0_o - connect \gpio_oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe - connect \main_libresocsim_libresoc_jtag_tck \jtag_tck - connect \main_libresocsim_libresoc_jtag_tms \jtag_tms - connect \main_libresocsim_libresoc_jtag_tdi \jtag_tdi - connect \jtag_tdo \main_libresocsim_libresoc_jtag_tdo - connect \main_nc \nc - connect \main_sdblock2mem_sink_sink_valid0 \main_sdcore_source_source_valid - connect \main_sdcore_source_source_ready \main_sdblock2mem_sink_sink_ready0 - connect \main_sdblock2mem_sink_sink_first \main_sdcore_source_source_first - connect \main_sdblock2mem_sink_sink_last \main_sdcore_source_source_last - connect \main_sdblock2mem_sink_sink_payload_data0 \main_sdcore_source_source_payload_data - connect \main_sdcore_sink_sink_valid \main_sdmem2block_source_source_valid0 - connect \main_sdmem2block_source_source_ready0 \main_sdcore_sink_sink_ready - connect \main_sdcore_sink_sink_first \main_sdmem2block_source_source_first0 - connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0 - connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0 - connect \main_libresocsim_bus_error \builder_error - connect \main_libresocsim_converter0_reset $not$ls180.v:2757$14_Y - connect \main_libresocsim_libresoc_ibus_dat_r { \main_libresocsim_interface0_converted_interface_dat_r \main_libresocsim_converter0_dat_r [63:32] } - connect \main_libresocsim_converter1_reset $not$ls180.v:2817$25_Y - connect \main_libresocsim_libresoc_dbus_dat_r { \main_libresocsim_interface1_converted_interface_dat_r \main_libresocsim_converter1_dat_r [63:32] } - connect \main_libresocsim_converter2_reset $not$ls180.v:2877$36_Y - connect \main_libresocsim_libresoc_jtag_wb_dat_r { \main_libresocsim_interface2_converted_interface_dat_r \main_libresocsim_converter2_dat_r [63:32] } - connect \main_libresocsim_reset \main_libresocsim_reset_re - connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors - connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [6:0] - connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r - connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w - connect \main_libresocsim_zero_trigger $ne$ls180.v:2949$60_Y - connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status - connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending - connect \main_libresocsim_irq $and$ls180.v:2958$63_Y - connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger - connect \sys_clk_1 \sys_clk - connect \por_clk \sys_clk - connect \sys_rst_1 \main_int_rst - connect \main_dfi_p0_address \main_sdram_master_p0_address - connect \main_dfi_p0_bank \main_sdram_master_p0_bank - connect \main_dfi_p0_cas_n \main_sdram_master_p0_cas_n - connect \main_dfi_p0_cs_n \main_sdram_master_p0_cs_n - connect \main_dfi_p0_ras_n \main_sdram_master_p0_ras_n - connect \main_dfi_p0_we_n \main_sdram_master_p0_we_n - connect \main_dfi_p0_cke \main_sdram_master_p0_cke - connect \main_dfi_p0_odt \main_sdram_master_p0_odt - connect \main_dfi_p0_reset_n \main_sdram_master_p0_reset_n - connect \main_dfi_p0_act_n \main_sdram_master_p0_act_n - connect \main_dfi_p0_wrdata \main_sdram_master_p0_wrdata - connect \main_dfi_p0_wrdata_en \main_sdram_master_p0_wrdata_en - connect \main_dfi_p0_wrdata_mask \main_sdram_master_p0_wrdata_mask - connect \main_dfi_p0_rddata_en \main_sdram_master_p0_rddata_en - connect \main_sdram_master_p0_rddata \main_dfi_p0_rddata - connect \main_sdram_master_p0_rddata_valid \main_dfi_p0_rddata_valid - connect \main_sdram_slave_p0_address \main_sdram_dfi_p0_address - connect \main_sdram_slave_p0_bank \main_sdram_dfi_p0_bank - connect \main_sdram_slave_p0_cas_n \main_sdram_dfi_p0_cas_n - connect \main_sdram_slave_p0_cs_n \main_sdram_dfi_p0_cs_n - connect \main_sdram_slave_p0_ras_n \main_sdram_dfi_p0_ras_n - connect \main_sdram_slave_p0_we_n \main_sdram_dfi_p0_we_n - connect \main_sdram_slave_p0_cke \main_sdram_dfi_p0_cke - connect \main_sdram_slave_p0_odt \main_sdram_dfi_p0_odt - connect \main_sdram_slave_p0_reset_n \main_sdram_dfi_p0_reset_n - connect \main_sdram_slave_p0_act_n \main_sdram_dfi_p0_act_n - connect \main_sdram_slave_p0_wrdata \main_sdram_dfi_p0_wrdata - connect \main_sdram_slave_p0_wrdata_en \main_sdram_dfi_p0_wrdata_en - connect \main_sdram_slave_p0_wrdata_mask \main_sdram_dfi_p0_wrdata_mask - connect \main_sdram_slave_p0_rddata_en \main_sdram_dfi_p0_rddata_en - connect \main_sdram_dfi_p0_rddata \main_sdram_slave_p0_rddata - connect \main_sdram_dfi_p0_rddata_valid \main_sdram_slave_p0_rddata_valid - connect \main_sdram_inti_p0_cke \main_sdram_cke - connect \main_sdram_inti_p0_odt \main_sdram_odt - connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n - connect \main_sdram_inti_p0_address \main_sdram_address_storage - connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage - connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3072$70_Y - connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3073$71_Y - connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage - connect \main_sdram_inti_p0_wrdata_mask 2'00 - connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid - connect \main_sdram_interface_bank0_ready \main_sdram_bankmachine0_req_ready - connect \main_sdram_bankmachine0_req_we \main_sdram_interface_bank0_we - connect \main_sdram_bankmachine0_req_addr \main_sdram_interface_bank0_addr - connect \main_sdram_interface_bank0_lock \main_sdram_bankmachine0_req_lock - connect \main_sdram_interface_bank0_wdata_ready \main_sdram_bankmachine0_req_wdata_ready - connect \main_sdram_interface_bank0_rdata_valid \main_sdram_bankmachine0_req_rdata_valid - connect \main_sdram_bankmachine1_req_valid \main_sdram_interface_bank1_valid - connect \main_sdram_interface_bank1_ready \main_sdram_bankmachine1_req_ready - connect \main_sdram_bankmachine1_req_we \main_sdram_interface_bank1_we - connect \main_sdram_bankmachine1_req_addr \main_sdram_interface_bank1_addr - connect \main_sdram_interface_bank1_lock \main_sdram_bankmachine1_req_lock - connect \main_sdram_interface_bank1_wdata_ready \main_sdram_bankmachine1_req_wdata_ready - connect \main_sdram_interface_bank1_rdata_valid \main_sdram_bankmachine1_req_rdata_valid - connect \main_sdram_bankmachine2_req_valid \main_sdram_interface_bank2_valid - connect \main_sdram_interface_bank2_ready \main_sdram_bankmachine2_req_ready - connect \main_sdram_bankmachine2_req_we \main_sdram_interface_bank2_we - connect \main_sdram_bankmachine2_req_addr \main_sdram_interface_bank2_addr - connect \main_sdram_interface_bank2_lock \main_sdram_bankmachine2_req_lock - connect \main_sdram_interface_bank2_wdata_ready \main_sdram_bankmachine2_req_wdata_ready - connect \main_sdram_interface_bank2_rdata_valid \main_sdram_bankmachine2_req_rdata_valid - connect \main_sdram_bankmachine3_req_valid \main_sdram_interface_bank3_valid - connect \main_sdram_interface_bank3_ready \main_sdram_bankmachine3_req_ready - connect \main_sdram_bankmachine3_req_we \main_sdram_interface_bank3_we - connect \main_sdram_bankmachine3_req_addr \main_sdram_interface_bank3_addr - connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock - connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready - connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid - connect \main_sdram_timer_wait $not$ls180.v:3104$72_Y - connect \main_sdram_postponer_req_i \main_sdram_timer_done0 - connect \main_sdram_wants_refresh \main_sdram_postponer_req_o - connect \main_sdram_timer_done1 $eq$ls180.v:3107$73_Y - connect \main_sdram_timer_done0 \main_sdram_timer_done1 - connect \main_sdram_timer_count0 \main_sdram_timer_count1 - connect \main_sdram_sequencer_start1 $or$ls180.v:3110$75_Y - connect \main_sdram_sequencer_done0 $and$ls180.v:3111$77_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid - connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine0_req_addr - connect \main_sdram_bankmachine0_cmd_buffer_sink_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine0_cmd_buffer_sink_ready - connect \main_sdram_bankmachine0_cmd_buffer_sink_first \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3153$79_Y - connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3154$80_Y - connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3155$81_Y - connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 - connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3165$86_Y - connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3166$88_Y - connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3167$90_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3199$98_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3200$99_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3203$100_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3204$101_Y - connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3205$103_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid - connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine1_req_addr - connect \main_sdram_bankmachine1_cmd_buffer_sink_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine1_cmd_buffer_sink_ready - connect \main_sdram_bankmachine1_cmd_buffer_sink_first \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3310$109_Y - connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3311$110_Y - connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3312$111_Y - connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 - connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3322$116_Y - connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3323$118_Y - connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3324$120_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3356$128_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3357$129_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3360$130_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3361$131_Y - connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3362$133_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid - connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine2_req_addr - connect \main_sdram_bankmachine2_cmd_buffer_sink_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine2_cmd_buffer_sink_ready - connect \main_sdram_bankmachine2_cmd_buffer_sink_first \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3467$139_Y - connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3468$140_Y - connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3469$141_Y - connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 - connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3479$146_Y - connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3480$148_Y - connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3481$150_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3513$158_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3514$159_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3517$160_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3518$161_Y - connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3519$163_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid - connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine3_req_addr - connect \main_sdram_bankmachine3_cmd_buffer_sink_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine3_cmd_buffer_sink_ready - connect \main_sdram_bankmachine3_cmd_buffer_sink_first \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3624$169_Y - connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3625$170_Y - connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3626$171_Y - connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 - connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3636$176_Y - connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3637$178_Y - connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3638$180_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3670$188_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3671$189_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3674$190_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3675$191_Y - connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3676$193_Y - connect \main_sdram_choose_req_want_cmds 1'1 - connect \main_sdram_trrdcon_valid $and$ls180.v:3772$204_Y - connect \main_sdram_tfawcon_valid $and$ls180.v:3773$210_Y - connect \main_sdram_ras_allowed $and$ls180.v:3774$211_Y - connect \main_sdram_tccdcon_valid $and$ls180.v:3775$214_Y - connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready - connect \main_sdram_twtrcon_valid $and$ls180.v:3777$216_Y - connect \main_sdram_read_available $or$ls180.v:3778$223_Y - connect \main_sdram_write_available $or$ls180.v:3779$230_Y - connect \main_sdram_max_time0 $eq$ls180.v:3780$231_Y - connect \main_sdram_max_time1 $eq$ls180.v:3781$232_Y - connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid - connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid - connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid - connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid - connect \main_sdram_go_to_refresh $and$ls180.v:3786$235_Y - connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata - connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata - connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3789$236_Y - connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids - connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 - connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 - connect \main_sdram_choose_cmd_cmd_payload_ba \builder_comb_rhs_array_muxed2 - connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 - connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 - connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 - connect \main_sdram_choose_cmd_ce $or$ls180.v:3822$294_Y - connect \main_sdram_choose_req_request \main_sdram_choose_req_valids - connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 - connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 - connect \main_sdram_choose_req_cmd_payload_ba \builder_comb_rhs_array_muxed8 - connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 - connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 - connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 - connect \main_sdram_choose_req_ce $or$ls180.v:3891$380_Y - connect \main_sdram_dfi_p0_reset_n 1'1 - connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 - connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 - connect \builder_roundrobin0_request $and$ls180.v:3968$412_Y - connect \builder_roundrobin0_ce $and$ls180.v:3969$415_Y - connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 - connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 - connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 - connect \builder_roundrobin1_request $and$ls180.v:3973$428_Y - connect \builder_roundrobin1_ce $and$ls180.v:3974$431_Y - connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 - connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 - connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 - connect \builder_roundrobin2_request $and$ls180.v:3978$444_Y - connect \builder_roundrobin2_ce $and$ls180.v:3979$447_Y - connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 - connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 - connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 - connect \builder_roundrobin3_request $and$ls180.v:3983$460_Y - connect \builder_roundrobin3_ce $and$ls180.v:3984$463_Y - connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 - connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 - connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 - connect \main_port_cmd_ready $or$ls180.v:3988$527_Y - connect \main_port_wdata_ready \builder_new_master_wdata_ready - connect \main_port_rdata_valid \builder_new_master_rdata_valid3 - connect \main_port_rdata_payload_data \main_sdram_interface_rdata - connect \builder_roundrobin0_grant 1'0 - connect \builder_roundrobin1_grant 1'0 - connect \builder_roundrobin2_grant 1'0 - connect \builder_roundrobin3_grant 1'0 - connect \main_converter_reset $not$ls180.v:4010$529_Y - connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } - connect \main_port_cmd_payload_addr $sub$ls180.v:4070$540_Y [23:0] - connect \main_port_cmd_payload_we \main_litedram_wb_we - connect \main_port_wdata_payload_data \main_litedram_wb_dat_w - connect \main_port_wdata_payload_we \main_litedram_wb_sel - connect \main_litedram_wb_dat_r \main_port_rdata_payload_data - connect \main_port_flush $not$ls180.v:4075$541_Y - connect \main_port_cmd_last $not$ls180.v:4076$542_Y - connect \main_port_cmd_valid $and$ls180.v:4077$545_Y - connect \main_port_wdata_valid $and$ls180.v:4078$549_Y - connect \main_port_rdata_ready $and$ls180.v:4079$552_Y - connect \main_litedram_wb_ack $and$ls180.v:4080$557_Y - connect \main_ack_cmd $or$ls180.v:4081$559_Y - connect \main_ack_wdata $or$ls180.v:4082$561_Y - connect \main_ack_rdata $and$ls180.v:4083$562_Y - connect \main_uart_uart_sink_valid \main_uart_phy_source_valid - connect \main_uart_phy_source_ready \main_uart_uart_sink_ready - connect \main_uart_uart_sink_first \main_uart_phy_source_first - connect \main_uart_uart_sink_last \main_uart_phy_source_last - connect \main_uart_uart_sink_payload_data \main_uart_phy_source_payload_data - connect \main_uart_phy_sink_valid \main_uart_uart_source_valid - connect \main_uart_uart_source_ready \main_uart_phy_sink_ready - connect \main_uart_phy_sink_first \main_uart_uart_source_first - connect \main_uart_phy_sink_last \main_uart_uart_source_last - connect \main_uart_phy_sink_payload_data \main_uart_uart_source_payload_data - connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re - connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r - connect \main_uart_txfull_status $not$ls180.v:4096$563_Y - connect \main_uart_txempty_status $not$ls180.v:4097$564_Y - connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid - connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready - connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first - connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last - connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data - connect \main_uart_tx_trigger $not$ls180.v:4103$565_Y - connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid - connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready - connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first - connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last - connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data - connect \main_uart_rxempty_status $not$ls180.v:4109$566_Y - connect \main_uart_rxfull_status $not$ls180.v:4110$567_Y - connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data - connect \main_uart_rx_fifo_source_ready $or$ls180.v:4112$569_Y - connect \main_uart_rx_trigger $not$ls180.v:4113$570_Y - connect \main_uart_irq $or$ls180.v:4136$579_Y - connect \main_uart_tx_status \main_uart_tx_trigger - connect \main_uart_rx_status \main_uart_rx_trigger - connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data } - connect { \main_uart_tx_fifo_fifo_out_last \main_uart_tx_fifo_fifo_out_first \main_uart_tx_fifo_fifo_out_payload_data } \main_uart_tx_fifo_syncfifo_dout - connect \main_uart_tx_fifo_sink_ready \main_uart_tx_fifo_syncfifo_writable - connect \main_uart_tx_fifo_syncfifo_we \main_uart_tx_fifo_sink_valid - connect \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_sink_first - connect \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_sink_last - connect \main_uart_tx_fifo_fifo_in_payload_data \main_uart_tx_fifo_sink_payload_data - connect \main_uart_tx_fifo_source_valid \main_uart_tx_fifo_readable - connect \main_uart_tx_fifo_source_first \main_uart_tx_fifo_fifo_out_first - connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last - connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data - connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready - connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4151$582_Y - connect \main_uart_tx_fifo_level1 $add$ls180.v:4152$583_Y - connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din - connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4162$587_Y - connect \main_uart_tx_fifo_do_read $and$ls180.v:4163$588_Y - connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume - connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r - connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read - connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4167$589_Y - connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4168$590_Y - connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data } - connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout - connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable - connect \main_uart_rx_fifo_syncfifo_we \main_uart_rx_fifo_sink_valid - connect \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_sink_first - connect \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_sink_last - connect \main_uart_rx_fifo_fifo_in_payload_data \main_uart_rx_fifo_sink_payload_data - connect \main_uart_rx_fifo_source_valid \main_uart_rx_fifo_readable - connect \main_uart_rx_fifo_source_first \main_uart_rx_fifo_fifo_out_first - connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last - connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data - connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready - connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4181$593_Y - connect \main_uart_rx_fifo_level1 $add$ls180.v:4182$594_Y - connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din - connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4192$598_Y - connect \main_uart_rx_fifo_do_read $and$ls180.v:4193$599_Y - connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume - connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r - connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read - connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4197$600_Y - connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4198$601_Y - connect \main_gpio_pads_i \main_libresocsim_libresoc_constraintmanager0_gpio0_i - connect \main_libresocsim_libresoc_constraintmanager0_gpio0_o \main_gpio_pads_o - connect \main_libresocsim_libresoc_constraintmanager0_gpio0_oe \main_gpio_pads_oe - connect \main_gpio_pads_oe \main_gpio_oe_storage - connect \main_gpio_pads_o \main_gpio_out_storage - connect \main_spi_master_start0 \main_spi_master_start1 - connect \main_spi_master_length0 \main_spi_master_length1 - connect \main_spi_master_mosi \main_spi_master_mosi_storage - connect \main_spi_master_done1 \main_spi_master_done0 - connect \main_spi_master_miso_status \main_spi_master_miso - connect \main_spi_master_cs \main_spi_master_cs_storage - connect \main_spi_master_loopback \main_spi_master_loopback_storage - connect \main_spi_master_clk_rise $eq$ls180.v:4211$603_Y - connect \main_spi_master_clk_fall $eq$ls180.v:4212$605_Y - connect \i2c_scl \main_i2c_scl - connect \i2c_sda_oe \main_i2c_oe - connect \i2c_sda_o \main_i2c_sda0 - connect \main_i2c_sda1 \i2c_sda_i - connect \main_sdphy_status 1'0 - connect \main_sdphy_sdpads_clk $or$ls180.v:4267$613_Y - connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4268$617_Y - connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4269$621_Y - connect \main_sdphy_sdpads_data_oe $or$ls180.v:4270$625_Y - connect \main_sdphy_sdpads_data_o $or$ls180.v:4271$629_Y - connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_dataw_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_datar_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_init_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_init_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_init_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_cmdw_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_cmdw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_cmdw_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_cmdr_pads_in_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_cmdr_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_dataw_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_dataw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_dataw_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_clocker_stop $or$ls180.v:4292$630_Y - connect \main_sdphy_clocker_ce $and$ls180.v:4322$633_Y - connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid - connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready - connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first - connect \main_sdphy_cmdr_cmdr_pads_in_last \main_sdphy_cmdr_pads_in_pads_in_last - connect \main_sdphy_cmdr_cmdr_pads_in_payload_clk \main_sdphy_cmdr_pads_in_pads_in_payload_clk - connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i - connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o - connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe - connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i - connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o - connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4445$643_Y - connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4446$645_Y - connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1 - connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready - connect \main_sdphy_cmdr_cmdr_buf_sink_first \main_sdphy_cmdr_cmdr_source_source_first1 - connect \main_sdphy_cmdr_cmdr_buf_sink_last \main_sdphy_cmdr_cmdr_source_source_last1 - connect \main_sdphy_cmdr_cmdr_buf_sink_payload_data \main_sdphy_cmdr_cmdr_source_source_payload_data1 - connect \main_sdphy_cmdr_cmdr_source_source_valid0 \main_sdphy_cmdr_cmdr_buf_source_valid - connect \main_sdphy_cmdr_cmdr_buf_source_ready \main_sdphy_cmdr_cmdr_source_source_ready0 - connect \main_sdphy_cmdr_cmdr_source_source_first0 \main_sdphy_cmdr_cmdr_buf_source_first - connect \main_sdphy_cmdr_cmdr_source_source_last0 \main_sdphy_cmdr_cmdr_buf_source_last - connect \main_sdphy_cmdr_cmdr_source_source_payload_data0 \main_sdphy_cmdr_cmdr_buf_source_payload_data - connect \main_sdphy_cmdr_cmdr_source_source_valid1 \main_sdphy_cmdr_cmdr_converter_source_valid - connect \main_sdphy_cmdr_cmdr_converter_source_ready \main_sdphy_cmdr_cmdr_source_source_ready1 - connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first - connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last - connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data - connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4463$647_Y - connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4465$648_Y - connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4466$650_Y - connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid - connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready - connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first - connect \main_sdphy_dataw_crcr_pads_in_last \main_sdphy_dataw_pads_in_pads_in_last - connect \main_sdphy_dataw_crcr_pads_in_payload_clk \main_sdphy_dataw_pads_in_pads_in_payload_clk - connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_i \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i - connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_o \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o - connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe - connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i - connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o - connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4572$665_Y - connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4573$666_Y - connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] - connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1 - connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready - connect \main_sdphy_dataw_crcr_buf_sink_first \main_sdphy_dataw_crcr_source_source_first1 - connect \main_sdphy_dataw_crcr_buf_sink_last \main_sdphy_dataw_crcr_source_source_last1 - connect \main_sdphy_dataw_crcr_buf_sink_payload_data \main_sdphy_dataw_crcr_source_source_payload_data1 - connect \main_sdphy_dataw_crcr_source_source_valid0 \main_sdphy_dataw_crcr_buf_source_valid - connect \main_sdphy_dataw_crcr_buf_source_ready \main_sdphy_dataw_crcr_source_source_ready0 - connect \main_sdphy_dataw_crcr_source_source_first0 \main_sdphy_dataw_crcr_buf_source_first - connect \main_sdphy_dataw_crcr_source_source_last0 \main_sdphy_dataw_crcr_buf_source_last - connect \main_sdphy_dataw_crcr_source_source_payload_data0 \main_sdphy_dataw_crcr_buf_source_payload_data - connect \main_sdphy_dataw_crcr_source_source_valid1 \main_sdphy_dataw_crcr_converter_source_valid - connect \main_sdphy_dataw_crcr_converter_source_ready \main_sdphy_dataw_crcr_source_source_ready1 - connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first - connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last - connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data - connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4590$668_Y - connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all - connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4592$669_Y - connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4593$671_Y - connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid - connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready - connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first - connect \main_sdphy_datar_datar_pads_in_last \main_sdphy_datar_pads_in_pads_in_last - connect \main_sdphy_datar_datar_pads_in_payload_clk \main_sdphy_datar_pads_in_pads_in_payload_clk - connect \main_sdphy_datar_datar_pads_in_payload_cmd_i \main_sdphy_datar_pads_in_pads_in_payload_cmd_i - connect \main_sdphy_datar_datar_pads_in_payload_cmd_o \main_sdphy_datar_pads_in_pads_in_payload_cmd_o - connect \main_sdphy_datar_datar_pads_in_payload_cmd_oe \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe - connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i - connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o - connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe - connect \main_sdphy_datar_datar_start $eq$ls180.v:4706$680_Y - connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4707$681_Y - connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i - connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1 - connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready - connect \main_sdphy_datar_datar_buf_sink_first \main_sdphy_datar_datar_source_source_first1 - connect \main_sdphy_datar_datar_buf_sink_last \main_sdphy_datar_datar_source_source_last1 - connect \main_sdphy_datar_datar_buf_sink_payload_data \main_sdphy_datar_datar_source_source_payload_data1 - connect \main_sdphy_datar_datar_source_source_valid0 \main_sdphy_datar_datar_buf_source_valid - connect \main_sdphy_datar_datar_buf_source_ready \main_sdphy_datar_datar_source_source_ready0 - connect \main_sdphy_datar_datar_source_source_first0 \main_sdphy_datar_datar_buf_source_first - connect \main_sdphy_datar_datar_source_source_last0 \main_sdphy_datar_datar_buf_source_last - connect \main_sdphy_datar_datar_source_source_payload_data0 \main_sdphy_datar_datar_buf_source_payload_data - connect \main_sdphy_datar_datar_source_source_valid1 \main_sdphy_datar_datar_converter_source_valid - connect \main_sdphy_datar_datar_converter_source_ready \main_sdphy_datar_datar_source_source_ready1 - connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first - connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last - connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data - connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4724$683_Y - connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all - connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4726$684_Y - connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4727$686_Y - connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid - connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready - connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first - connect \main_sdcore_crc16_inserter_sink_last \main_sdcore_sink_sink_last - connect \main_sdcore_crc16_inserter_sink_payload_data \main_sdcore_sink_sink_payload_data - connect \main_sdcore_source_source_valid \main_sdcore_crc16_checker_source_valid - connect \main_sdcore_crc16_checker_source_ready \main_sdcore_source_source_ready - connect \main_sdcore_source_source_first \main_sdcore_crc16_checker_source_first - connect \main_sdcore_source_source_last \main_sdcore_crc16_checker_source_last - connect \main_sdcore_source_source_payload_data \main_sdcore_crc16_checker_source_payload_data - connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0] - connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5] - connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done } - connect \main_sdcore_data_event_status { $not$ls180.v:4843$701_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } - connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage } - connect \main_sdcore_crc7_inserter_clr 1'1 - connect \main_sdcore_crc7_inserter_enable 1'1 - connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4847$704_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4847$702_Y } - connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4848$707_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4848$705_Y } - connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4849$710_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4849$708_Y } - connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:4850$713_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:4850$711_Y } - connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:4851$716_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:4851$714_Y } - connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:4852$719_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:4852$717_Y } - connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:4853$722_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:4853$720_Y } - connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:4854$725_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:4854$723_Y } - connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:4855$728_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:4855$726_Y } - connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:4856$731_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:4856$729_Y } - connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:4857$734_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:4857$732_Y } - connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:4858$737_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:4858$735_Y } - connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:4859$740_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:4859$738_Y } - connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:4860$743_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:4860$741_Y } - connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:4861$746_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:4861$744_Y } - connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:4862$749_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:4862$747_Y } - connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:4863$752_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:4863$750_Y } - connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:4864$755_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:4864$753_Y } - connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:4865$758_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:4865$756_Y } - connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:4866$761_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:4866$759_Y } - connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:4867$764_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:4867$762_Y } - connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:4868$767_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:4868$765_Y } - connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:4869$770_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:4869$768_Y } - connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:4870$773_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:4870$771_Y } - connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:4871$776_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:4871$774_Y } - connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:4872$779_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:4872$777_Y } - connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:4873$782_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:4873$780_Y } - connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:4874$785_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:4874$783_Y } - connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:4875$788_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:4875$786_Y } - connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:4876$791_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:4876$789_Y } - connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:4877$794_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:4877$792_Y } - connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:4878$797_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:4878$795_Y } - connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:4879$800_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:4879$798_Y } - connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:4880$803_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:4880$801_Y } - connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:4881$806_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:4881$804_Y } - connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:4882$809_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:4882$807_Y } - connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:4883$812_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:4883$810_Y } - connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:4884$815_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:4884$813_Y } - connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:4885$818_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:4885$816_Y } - connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:4886$821_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:4886$819_Y } - connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] } - connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:4896$824_Y - connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:4897$825_Y - connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] } - connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:4899$827_Y - connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:4900$828_Y - connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] } - connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:4902$830_Y - connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:4903$831_Y - connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] } - connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:4905$833_Y - connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:4906$834_Y - connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:4907$839_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:4907$837_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:4907$835_Y } - connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:4908$844_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:4908$842_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:4908$840_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:4917$850_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:4917$848_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:4917$846_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:4918$855_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:4918$853_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:4918$851_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:4927$861_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:4927$859_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:4927$857_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:4928$866_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:4928$864_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:4928$862_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:4937$872_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:4937$870_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:4937$868_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:4938$877_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:4938$875_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:4938$873_Y } - connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] } - connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5034$893_Y - connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] } - connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5044$896_Y - connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] } - connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5054$899_Y - connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] } - connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5064$902_Y - connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val - connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last - connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5089$914_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5089$912_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5089$910_Y } - connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5090$919_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5090$917_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5090$915_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5099$925_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5099$923_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5099$921_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5100$930_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5100$928_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5100$926_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5109$936_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5109$934_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5109$932_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5110$941_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5110$939_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5110$937_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5119$947_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5119$945_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5119$943_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5120$952_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5120$950_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5120$948_Y } - connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0 - connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready - connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first - connect \main_sdblock2mem_fifo_sink_last \main_sdblock2mem_sink_sink_last - connect \main_sdblock2mem_fifo_sink_payload_data \main_sdblock2mem_sink_sink_payload_data0 - connect \main_sdblock2mem_converter_sink_valid \main_sdblock2mem_fifo_source_valid - connect \main_sdblock2mem_fifo_source_ready \main_sdblock2mem_converter_sink_ready - connect \main_sdblock2mem_converter_sink_first \main_sdblock2mem_fifo_source_first - connect \main_sdblock2mem_converter_sink_last \main_sdblock2mem_fifo_source_last - connect \main_sdblock2mem_converter_sink_payload_data \main_sdblock2mem_fifo_source_payload_data - connect \main_sdblock2mem_wishbonedmawriter_sink_valid \main_sdblock2mem_source_source_valid - connect \main_sdblock2mem_source_source_ready \main_sdblock2mem_wishbonedmawriter_sink_ready - connect \main_sdblock2mem_wishbonedmawriter_sink_first \main_sdblock2mem_source_source_first - connect \main_sdblock2mem_wishbonedmawriter_sink_last \main_sdblock2mem_source_source_last - connect \main_sdblock2mem_wishbonedmawriter_sink_payload_data \main_sdblock2mem_source_source_payload_data - connect \main_sdblock2mem_fifo_syncfifo_din { \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_fifo_in_payload_data } - connect { \main_sdblock2mem_fifo_fifo_out_last \main_sdblock2mem_fifo_fifo_out_first \main_sdblock2mem_fifo_fifo_out_payload_data } \main_sdblock2mem_fifo_syncfifo_dout - connect \main_sdblock2mem_fifo_sink_ready \main_sdblock2mem_fifo_syncfifo_writable - connect \main_sdblock2mem_fifo_syncfifo_we \main_sdblock2mem_fifo_sink_valid - connect \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_sink_first - connect \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_sink_last - connect \main_sdblock2mem_fifo_fifo_in_payload_data \main_sdblock2mem_fifo_sink_payload_data - connect \main_sdblock2mem_fifo_source_valid \main_sdblock2mem_fifo_syncfifo_readable - connect \main_sdblock2mem_fifo_source_first \main_sdblock2mem_fifo_fifo_out_first - connect \main_sdblock2mem_fifo_source_last \main_sdblock2mem_fifo_fifo_out_last - connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data - connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready - connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din - connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5356$982_Y - connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5357$983_Y - connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume - connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r - connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5360$984_Y - connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5361$985_Y - connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid - connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready - connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first - connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last - connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data - connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5367$987_Y - connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all - connect \main_sdblock2mem_converter_load_part $and$ls180.v:5369$988_Y - connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1 - connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1 - connect \main_interface0_bus_we 1'1 - connect \main_interface0_bus_sel 4'1111 - connect \main_interface0_bus_adr \main_sdblock2mem_sink_sink_payload_address - connect \main_interface0_bus_dat_w { \main_sdblock2mem_sink_sink_payload_data1 [7:0] \main_sdblock2mem_sink_sink_payload_data1 [15:8] \main_sdblock2mem_sink_sink_payload_data1 [23:16] \main_sdblock2mem_sink_sink_payload_data1 [31:24] } - connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack - connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [33:2] - connect \main_sdblock2mem_wishbonedmawriter_length { 2'00 \main_sdblock2mem_wishbonedmawriter_length_storage [31:2] } - connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5379$989_Y - connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid - connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready - connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first - connect \main_sdmem2block_converter_sink_last \main_sdmem2block_dma_source_last - connect \main_sdmem2block_converter_sink_payload_data \main_sdmem2block_dma_source_payload_data - connect \main_sdmem2block_fifo_sink_valid \main_sdmem2block_source_source_valid1 - connect \main_sdmem2block_source_source_ready1 \main_sdmem2block_fifo_sink_ready - connect \main_sdmem2block_fifo_sink_first \main_sdmem2block_source_source_first1 - connect \main_sdmem2block_fifo_sink_last \main_sdmem2block_source_source_last1 - connect \main_sdmem2block_fifo_sink_payload_data \main_sdmem2block_source_source_payload_data1 - connect \main_sdmem2block_source_source_valid0 \main_sdmem2block_fifo_source_valid - connect \main_sdmem2block_fifo_source_ready \main_sdmem2block_source_source_ready0 - connect \main_sdmem2block_source_source_first0 \main_sdmem2block_fifo_source_first - connect \main_sdmem2block_source_source_last0 \main_sdmem2block_fifo_source_last - connect \main_sdmem2block_source_source_payload_data0 \main_sdmem2block_fifo_source_payload_data - connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [33:2] - connect \main_sdmem2block_dma_length { 2'00 \main_sdmem2block_dma_length_storage [31:2] } - connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset - connect \main_sdmem2block_dma_reset $not$ls180.v:5438$996_Y - connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid - connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1 - connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first - connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last - connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data - connect \main_sdmem2block_converter_first $eq$ls180.v:5519$1004_Y - connect \main_sdmem2block_converter_last $eq$ls180.v:5520$1005_Y - connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid - connect \main_sdmem2block_converter_source_first $and$ls180.v:5522$1006_Y - connect \main_sdmem2block_converter_source_last $and$ls180.v:5523$1007_Y - connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5524$1008_Y - connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last - connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data } - connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout - connect \main_sdmem2block_fifo_sink_ready \main_sdmem2block_fifo_syncfifo_writable - connect \main_sdmem2block_fifo_syncfifo_we \main_sdmem2block_fifo_sink_valid - connect \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_sink_first - connect \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_sink_last - connect \main_sdmem2block_fifo_fifo_in_payload_data \main_sdmem2block_fifo_sink_payload_data - connect \main_sdmem2block_fifo_source_valid \main_sdmem2block_fifo_syncfifo_readable - connect \main_sdmem2block_fifo_source_first \main_sdmem2block_fifo_fifo_out_first - connect \main_sdmem2block_fifo_source_last \main_sdmem2block_fifo_fifo_out_last - connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data - connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready - connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din - connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5564$1013_Y - connect \main_sdmem2block_fifo_do_read $and$ls180.v:5565$1014_Y - connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume - connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r - connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5568$1015_Y - connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5569$1016_Y - connect \libresocsim_start0 \libresocsim_start1 - connect \libresocsim_length0 \libresocsim_length1 - connect \libresocsim_mosi \libresocsim_mosi_storage - connect \libresocsim_done1 \libresocsim_done0 - connect \libresocsim_miso_status \libresocsim_miso - connect \libresocsim_cs \libresocsim_cs_storage - connect \libresocsim_loopback \libresocsim_loopback_storage - connect \libresocsim_clk_rise $eq$ls180.v:5577$1018_Y - connect \libresocsim_clk_fall $eq$ls180.v:5578$1020_Y - connect \libresocsim_clk_divider0 \libresocsim_storage - connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] - connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 - connect \builder_shared_sel \builder_comb_rhs_array_muxed26 - connect \builder_shared_cyc \builder_comb_rhs_array_muxed27 - connect \builder_shared_stb \builder_comb_rhs_array_muxed28 - connect \builder_shared_we \builder_comb_rhs_array_muxed29 - connect \builder_shared_cti \builder_comb_rhs_array_muxed30 - connect \builder_shared_bte \builder_comb_rhs_array_muxed31 - connect \main_libresocsim_interface0_converted_interface_dat_r \builder_shared_dat_r - connect \main_libresocsim_interface1_converted_interface_dat_r \builder_shared_dat_r - connect \main_libresocsim_interface2_converted_interface_dat_r \builder_shared_dat_r - connect \main_interface0_bus_dat_r \builder_shared_dat_r - connect \main_interface1_bus_dat_r \builder_shared_dat_r - connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5679$1030_Y - connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5680$1032_Y - connect \main_libresocsim_interface2_converted_interface_ack $and$ls180.v:5681$1034_Y - connect \main_interface0_bus_ack $and$ls180.v:5682$1036_Y - connect \main_interface1_bus_ack $and$ls180.v:5683$1038_Y - connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5684$1040_Y - connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5685$1042_Y - connect \main_libresocsim_interface2_converted_interface_err $and$ls180.v:5686$1044_Y - connect \main_interface0_bus_err $and$ls180.v:5687$1046_Y - connect \main_interface1_bus_err $and$ls180.v:5688$1048_Y - connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_interface2_converted_interface_cyc \main_libresocsim_interface1_converted_interface_cyc \main_libresocsim_interface0_converted_interface_cyc } - connect \main_libresocsim_ram_bus_adr \builder_shared_adr - connect \main_libresocsim_ram_bus_dat_w \builder_shared_dat_w - connect \main_libresocsim_ram_bus_sel \builder_shared_sel - connect \main_libresocsim_ram_bus_stb \builder_shared_stb - connect \main_libresocsim_ram_bus_we \builder_shared_we - connect \main_libresocsim_ram_bus_cti \builder_shared_cti - connect \main_libresocsim_ram_bus_bte \builder_shared_bte - connect \main_libresocsim_libresoc_xics_icp_adr \builder_shared_adr - connect \main_libresocsim_libresoc_xics_icp_dat_w \builder_shared_dat_w - connect \main_libresocsim_libresoc_xics_icp_sel \builder_shared_sel - connect \main_libresocsim_libresoc_xics_icp_stb \builder_shared_stb - connect \main_libresocsim_libresoc_xics_icp_we \builder_shared_we - connect \main_libresocsim_libresoc_xics_icp_cti \builder_shared_cti - connect \main_libresocsim_libresoc_xics_icp_bte \builder_shared_bte - connect \main_libresocsim_libresoc_xics_ics_adr \builder_shared_adr - connect \main_libresocsim_libresoc_xics_ics_dat_w \builder_shared_dat_w - connect \main_libresocsim_libresoc_xics_ics_sel \builder_shared_sel - connect \main_libresocsim_libresoc_xics_ics_stb \builder_shared_stb - connect \main_libresocsim_libresoc_xics_ics_we \builder_shared_we - connect \main_libresocsim_libresoc_xics_ics_cti \builder_shared_cti - connect \main_libresocsim_libresoc_xics_ics_bte \builder_shared_bte - connect \main_wb_sdram_adr \builder_shared_adr - connect \main_wb_sdram_dat_w \builder_shared_dat_w - connect \main_wb_sdram_sel \builder_shared_sel - connect \main_wb_sdram_stb \builder_shared_stb - connect \main_wb_sdram_we \builder_shared_we - connect \main_wb_sdram_cti \builder_shared_cti - connect \main_wb_sdram_bte \builder_shared_bte - connect \builder_libresocsim_wishbone_adr \builder_shared_adr - connect \builder_libresocsim_wishbone_dat_w \builder_shared_dat_w - connect \builder_libresocsim_wishbone_sel \builder_shared_sel - connect \builder_libresocsim_wishbone_stb \builder_shared_stb - connect \builder_libresocsim_wishbone_we \builder_shared_we - connect \builder_libresocsim_wishbone_cti \builder_shared_cti - connect \builder_libresocsim_wishbone_bte \builder_shared_bte - connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5733$1055_Y - connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5734$1056_Y - connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5735$1057_Y - connect \main_wb_sdram_cyc $and$ls180.v:5736$1058_Y - connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5737$1059_Y - connect \builder_shared_err $or$ls180.v:5738$1063_Y - connect \builder_wait $and$ls180.v:5739$1066_Y - connect \builder_done $eq$ls180.v:5752$1081_Y - connect \builder_csrbank0_sel $eq$ls180.v:5753$1082_Y - connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] - connect \builder_csrbank0_reset0_re $and$ls180.v:5755$1085_Y - connect \builder_csrbank0_reset0_we $and$ls180.v:5756$1089_Y - connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch3_re $and$ls180.v:5758$1092_Y - connect \builder_csrbank0_scratch3_we $and$ls180.v:5759$1096_Y - connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch2_re $and$ls180.v:5761$1099_Y - connect \builder_csrbank0_scratch2_we $and$ls180.v:5762$1103_Y - connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch1_re $and$ls180.v:5764$1106_Y - connect \builder_csrbank0_scratch1_we $and$ls180.v:5765$1110_Y - connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch0_re $and$ls180.v:5767$1113_Y - connect \builder_csrbank0_scratch0_we $and$ls180.v:5768$1117_Y - connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5770$1120_Y - connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5771$1124_Y - connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5773$1127_Y - connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5774$1131_Y - connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5776$1134_Y - connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5777$1138_Y - connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5779$1141_Y - connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5780$1145_Y - connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage - connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24] - connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16] - connect \builder_csrbank0_scratch1_w \main_libresocsim_scratch_storage [15:8] - connect \builder_csrbank0_scratch0_w \main_libresocsim_scratch_storage [7:0] - connect \builder_csrbank0_bus_errors3_w \main_libresocsim_bus_errors_status [31:24] - connect \builder_csrbank0_bus_errors2_w \main_libresocsim_bus_errors_status [23:16] - connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8] - connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0] - connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we - connect \builder_csrbank1_sel $eq$ls180.v:5791$1146_Y - connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe1_re $and$ls180.v:5793$1149_Y - connect \builder_csrbank1_oe1_we $and$ls180.v:5794$1153_Y - connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe0_re $and$ls180.v:5796$1156_Y - connect \builder_csrbank1_oe0_we $and$ls180.v:5797$1160_Y - connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in1_re $and$ls180.v:5799$1163_Y - connect \builder_csrbank1_in1_we $and$ls180.v:5800$1167_Y - connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in0_re $and$ls180.v:5802$1170_Y - connect \builder_csrbank1_in0_we $and$ls180.v:5803$1174_Y - connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out1_re $and$ls180.v:5805$1177_Y - connect \builder_csrbank1_out1_we $and$ls180.v:5806$1181_Y - connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out0_re $and$ls180.v:5808$1184_Y - connect \builder_csrbank1_out0_we $and$ls180.v:5809$1188_Y - connect \builder_csrbank1_oe1_w \main_gpio_oe_storage [15:8] - connect \builder_csrbank1_oe0_w \main_gpio_oe_storage [7:0] - connect \builder_csrbank1_in1_w \main_gpio_status [15:8] - connect \builder_csrbank1_in0_w \main_gpio_status [7:0] - connect \main_gpio_we \builder_csrbank1_in0_we - connect \builder_csrbank1_out1_w \main_gpio_out_storage [15:8] - connect \builder_csrbank1_out0_w \main_gpio_out_storage [7:0] - connect \builder_csrbank2_sel $eq$ls180.v:5817$1189_Y - connect \builder_csrbank2_w0_r \builder_interface2_bank_bus_dat_w [2:0] - connect \builder_csrbank2_w0_re $and$ls180.v:5819$1192_Y - connect \builder_csrbank2_w0_we $and$ls180.v:5820$1196_Y - connect \builder_csrbank2_r_r \builder_interface2_bank_bus_dat_w [0] - connect \builder_csrbank2_r_re $and$ls180.v:5822$1199_Y - connect \builder_csrbank2_r_we $and$ls180.v:5823$1203_Y - connect \main_i2c_scl \main_i2c_storage [0] - connect \main_i2c_oe \main_i2c_storage [1] - connect \main_i2c_sda0 \main_i2c_storage [2] - connect \builder_csrbank2_w0_w \main_i2c_storage - connect \main_i2c_status \main_i2c_sda1 - connect \builder_csrbank2_r_w \main_i2c_status - connect \main_i2c_we \builder_csrbank2_r_we - connect \builder_csrbank3_sel $eq$ls180.v:5831$1204_Y - connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0] - connect \builder_csrbank3_enable0_re $and$ls180.v:5833$1207_Y - connect \builder_csrbank3_enable0_we $and$ls180.v:5834$1211_Y - connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width3_re $and$ls180.v:5836$1214_Y - connect \builder_csrbank3_width3_we $and$ls180.v:5837$1218_Y - connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width2_re $and$ls180.v:5839$1221_Y - connect \builder_csrbank3_width2_we $and$ls180.v:5840$1225_Y - connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width1_re $and$ls180.v:5842$1228_Y - connect \builder_csrbank3_width1_we $and$ls180.v:5843$1232_Y - connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width0_re $and$ls180.v:5845$1235_Y - connect \builder_csrbank3_width0_we $and$ls180.v:5846$1239_Y - connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period3_re $and$ls180.v:5848$1242_Y - connect \builder_csrbank3_period3_we $and$ls180.v:5849$1246_Y - connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period2_re $and$ls180.v:5851$1249_Y - connect \builder_csrbank3_period2_we $and$ls180.v:5852$1253_Y - connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period1_re $and$ls180.v:5854$1256_Y - connect \builder_csrbank3_period1_we $and$ls180.v:5855$1260_Y - connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period0_re $and$ls180.v:5857$1263_Y - connect \builder_csrbank3_period0_we $and$ls180.v:5858$1267_Y - connect \builder_csrbank3_enable0_w \main_pwm0_enable_storage - connect \builder_csrbank3_width3_w \main_pwm0_width_storage [31:24] - connect \builder_csrbank3_width2_w \main_pwm0_width_storage [23:16] - connect \builder_csrbank3_width1_w \main_pwm0_width_storage [15:8] - connect \builder_csrbank3_width0_w \main_pwm0_width_storage [7:0] - connect \builder_csrbank3_period3_w \main_pwm0_period_storage [31:24] - connect \builder_csrbank3_period2_w \main_pwm0_period_storage [23:16] - connect \builder_csrbank3_period1_w \main_pwm0_period_storage [15:8] - connect \builder_csrbank3_period0_w \main_pwm0_period_storage [7:0] - connect \builder_csrbank4_sel $eq$ls180.v:5868$1268_Y - connect \builder_csrbank4_enable0_r \builder_interface4_bank_bus_dat_w [0] - connect \builder_csrbank4_enable0_re $and$ls180.v:5870$1271_Y - connect \builder_csrbank4_enable0_we $and$ls180.v:5871$1275_Y - connect \builder_csrbank4_width3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width3_re $and$ls180.v:5873$1278_Y - connect \builder_csrbank4_width3_we $and$ls180.v:5874$1282_Y - connect \builder_csrbank4_width2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width2_re $and$ls180.v:5876$1285_Y - connect \builder_csrbank4_width2_we $and$ls180.v:5877$1289_Y - connect \builder_csrbank4_width1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width1_re $and$ls180.v:5879$1292_Y - connect \builder_csrbank4_width1_we $and$ls180.v:5880$1296_Y - connect \builder_csrbank4_width0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width0_re $and$ls180.v:5882$1299_Y - connect \builder_csrbank4_width0_we $and$ls180.v:5883$1303_Y - connect \builder_csrbank4_period3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period3_re $and$ls180.v:5885$1306_Y - connect \builder_csrbank4_period3_we $and$ls180.v:5886$1310_Y - connect \builder_csrbank4_period2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period2_re $and$ls180.v:5888$1313_Y - connect \builder_csrbank4_period2_we $and$ls180.v:5889$1317_Y - connect \builder_csrbank4_period1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period1_re $and$ls180.v:5891$1320_Y - connect \builder_csrbank4_period1_we $and$ls180.v:5892$1324_Y - connect \builder_csrbank4_period0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period0_re $and$ls180.v:5894$1327_Y - connect \builder_csrbank4_period0_we $and$ls180.v:5895$1331_Y - connect \builder_csrbank4_enable0_w \main_pwm1_enable_storage - connect \builder_csrbank4_width3_w \main_pwm1_width_storage [31:24] - connect \builder_csrbank4_width2_w \main_pwm1_width_storage [23:16] - connect \builder_csrbank4_width1_w \main_pwm1_width_storage [15:8] - connect \builder_csrbank4_width0_w \main_pwm1_width_storage [7:0] - connect \builder_csrbank4_period3_w \main_pwm1_period_storage [31:24] - connect \builder_csrbank4_period2_w \main_pwm1_period_storage [23:16] - connect \builder_csrbank4_period1_w \main_pwm1_period_storage [15:8] - connect \builder_csrbank4_period0_w \main_pwm1_period_storage [7:0] - connect \builder_csrbank5_sel $eq$ls180.v:5905$1332_Y - connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base7_re $and$ls180.v:5907$1335_Y - connect \builder_csrbank5_dma_base7_we $and$ls180.v:5908$1339_Y - connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base6_re $and$ls180.v:5910$1342_Y - connect \builder_csrbank5_dma_base6_we $and$ls180.v:5911$1346_Y - connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base5_re $and$ls180.v:5913$1349_Y - connect \builder_csrbank5_dma_base5_we $and$ls180.v:5914$1353_Y - connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base4_re $and$ls180.v:5916$1356_Y - connect \builder_csrbank5_dma_base4_we $and$ls180.v:5917$1360_Y - connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base3_re $and$ls180.v:5919$1363_Y - connect \builder_csrbank5_dma_base3_we $and$ls180.v:5920$1367_Y - connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base2_re $and$ls180.v:5922$1370_Y - connect \builder_csrbank5_dma_base2_we $and$ls180.v:5923$1374_Y - connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base1_re $and$ls180.v:5925$1377_Y - connect \builder_csrbank5_dma_base1_we $and$ls180.v:5926$1381_Y - connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base0_re $and$ls180.v:5928$1384_Y - connect \builder_csrbank5_dma_base0_we $and$ls180.v:5929$1388_Y - connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length3_re $and$ls180.v:5931$1391_Y - connect \builder_csrbank5_dma_length3_we $and$ls180.v:5932$1395_Y - connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length2_re $and$ls180.v:5934$1398_Y - connect \builder_csrbank5_dma_length2_we $and$ls180.v:5935$1402_Y - connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length1_re $and$ls180.v:5937$1405_Y - connect \builder_csrbank5_dma_length1_we $and$ls180.v:5938$1409_Y - connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length0_re $and$ls180.v:5940$1412_Y - connect \builder_csrbank5_dma_length0_we $and$ls180.v:5941$1416_Y - connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_enable0_re $and$ls180.v:5943$1419_Y - connect \builder_csrbank5_dma_enable0_we $and$ls180.v:5944$1423_Y - connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_done_re $and$ls180.v:5946$1426_Y - connect \builder_csrbank5_dma_done_we $and$ls180.v:5947$1430_Y - connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_loop0_re $and$ls180.v:5949$1433_Y - connect \builder_csrbank5_dma_loop0_we $and$ls180.v:5950$1437_Y - connect \builder_csrbank5_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56] - connect \builder_csrbank5_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48] - connect \builder_csrbank5_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40] - connect \builder_csrbank5_dma_base4_w \main_sdblock2mem_wishbonedmawriter_base_storage [39:32] - connect \builder_csrbank5_dma_base3_w \main_sdblock2mem_wishbonedmawriter_base_storage [31:24] - connect \builder_csrbank5_dma_base2_w \main_sdblock2mem_wishbonedmawriter_base_storage [23:16] - connect \builder_csrbank5_dma_base1_w \main_sdblock2mem_wishbonedmawriter_base_storage [15:8] - connect \builder_csrbank5_dma_base0_w \main_sdblock2mem_wishbonedmawriter_base_storage [7:0] - connect \builder_csrbank5_dma_length3_w \main_sdblock2mem_wishbonedmawriter_length_storage [31:24] - connect \builder_csrbank5_dma_length2_w \main_sdblock2mem_wishbonedmawriter_length_storage [23:16] - connect \builder_csrbank5_dma_length1_w \main_sdblock2mem_wishbonedmawriter_length_storage [15:8] - connect \builder_csrbank5_dma_length0_w \main_sdblock2mem_wishbonedmawriter_length_storage [7:0] - connect \builder_csrbank5_dma_enable0_w \main_sdblock2mem_wishbonedmawriter_enable_storage - connect \builder_csrbank5_dma_done_w \main_sdblock2mem_wishbonedmawriter_status - connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank5_dma_done_we - connect \builder_csrbank5_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage - connect \builder_csrbank6_sel $eq$ls180.v:5967$1438_Y - connect \builder_csrbank6_cmd_argument3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:5969$1441_Y - connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:5970$1445_Y - connect \builder_csrbank6_cmd_argument2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:5972$1448_Y - connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:5973$1452_Y - connect \builder_csrbank6_cmd_argument1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:5975$1455_Y - connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:5976$1459_Y - connect \builder_csrbank6_cmd_argument0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:5978$1462_Y - connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:5979$1466_Y - connect \builder_csrbank6_cmd_command3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command3_re $and$ls180.v:5981$1469_Y - connect \builder_csrbank6_cmd_command3_we $and$ls180.v:5982$1473_Y - connect \builder_csrbank6_cmd_command2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command2_re $and$ls180.v:5984$1476_Y - connect \builder_csrbank6_cmd_command2_we $and$ls180.v:5985$1480_Y - connect \builder_csrbank6_cmd_command1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command1_re $and$ls180.v:5987$1483_Y - connect \builder_csrbank6_cmd_command1_we $and$ls180.v:5988$1487_Y - connect \builder_csrbank6_cmd_command0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command0_re $and$ls180.v:5990$1490_Y - connect \builder_csrbank6_cmd_command0_we $and$ls180.v:5991$1494_Y - connect \main_sdcore_cmd_send_r \builder_interface6_bank_bus_dat_w [0] - connect \main_sdcore_cmd_send_re $and$ls180.v:5993$1497_Y - connect \main_sdcore_cmd_send_we $and$ls180.v:5994$1501_Y - connect \builder_csrbank6_cmd_response15_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response15_re $and$ls180.v:5996$1504_Y - connect \builder_csrbank6_cmd_response15_we $and$ls180.v:5997$1508_Y - connect \builder_csrbank6_cmd_response14_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response14_re $and$ls180.v:5999$1511_Y - connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6000$1515_Y - connect \builder_csrbank6_cmd_response13_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6002$1518_Y - connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6003$1522_Y - connect \builder_csrbank6_cmd_response12_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6005$1525_Y - connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6006$1529_Y - connect \builder_csrbank6_cmd_response11_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6008$1532_Y - connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6009$1536_Y - connect \builder_csrbank6_cmd_response10_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6011$1539_Y - connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6012$1543_Y - connect \builder_csrbank6_cmd_response9_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6014$1546_Y - connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6015$1550_Y - connect \builder_csrbank6_cmd_response8_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6017$1553_Y - connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6018$1557_Y - connect \builder_csrbank6_cmd_response7_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6020$1560_Y - connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6021$1564_Y - connect \builder_csrbank6_cmd_response6_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6023$1567_Y - connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6024$1571_Y - connect \builder_csrbank6_cmd_response5_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6026$1574_Y - connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6027$1578_Y - connect \builder_csrbank6_cmd_response4_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6029$1581_Y - connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6030$1585_Y - connect \builder_csrbank6_cmd_response3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6032$1588_Y - connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6033$1592_Y - connect \builder_csrbank6_cmd_response2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6035$1595_Y - connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6036$1599_Y - connect \builder_csrbank6_cmd_response1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6038$1602_Y - connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6039$1606_Y - connect \builder_csrbank6_cmd_response0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6041$1609_Y - connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6042$1613_Y - connect \builder_csrbank6_cmd_event_r \builder_interface6_bank_bus_dat_w [3:0] - connect \builder_csrbank6_cmd_event_re $and$ls180.v:6044$1616_Y - connect \builder_csrbank6_cmd_event_we $and$ls180.v:6045$1620_Y - connect \builder_csrbank6_data_event_r \builder_interface6_bank_bus_dat_w [3:0] - connect \builder_csrbank6_data_event_re $and$ls180.v:6047$1623_Y - connect \builder_csrbank6_data_event_we $and$ls180.v:6048$1627_Y - connect \builder_csrbank6_block_length1_r \builder_interface6_bank_bus_dat_w [1:0] - connect \builder_csrbank6_block_length1_re $and$ls180.v:6050$1630_Y - connect \builder_csrbank6_block_length1_we $and$ls180.v:6051$1634_Y - connect \builder_csrbank6_block_length0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_length0_re $and$ls180.v:6053$1637_Y - connect \builder_csrbank6_block_length0_we $and$ls180.v:6054$1641_Y - connect \builder_csrbank6_block_count3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count3_re $and$ls180.v:6056$1644_Y - connect \builder_csrbank6_block_count3_we $and$ls180.v:6057$1648_Y - connect \builder_csrbank6_block_count2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count2_re $and$ls180.v:6059$1651_Y - connect \builder_csrbank6_block_count2_we $and$ls180.v:6060$1655_Y - connect \builder_csrbank6_block_count1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count1_re $and$ls180.v:6062$1658_Y - connect \builder_csrbank6_block_count1_we $and$ls180.v:6063$1662_Y - connect \builder_csrbank6_block_count0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count0_re $and$ls180.v:6065$1665_Y - connect \builder_csrbank6_block_count0_we $and$ls180.v:6066$1669_Y - connect \builder_csrbank6_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24] - connect \builder_csrbank6_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16] - connect \builder_csrbank6_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8] - connect \builder_csrbank6_cmd_argument0_w \main_sdcore_cmd_argument_storage [7:0] - connect \builder_csrbank6_cmd_command3_w \main_sdcore_cmd_command_storage [31:24] - connect \builder_csrbank6_cmd_command2_w \main_sdcore_cmd_command_storage [23:16] - connect \builder_csrbank6_cmd_command1_w \main_sdcore_cmd_command_storage [15:8] - connect \builder_csrbank6_cmd_command0_w \main_sdcore_cmd_command_storage [7:0] - connect \builder_csrbank6_cmd_response15_w \main_sdcore_cmd_response_status [127:120] - connect \builder_csrbank6_cmd_response14_w \main_sdcore_cmd_response_status [119:112] - connect \builder_csrbank6_cmd_response13_w \main_sdcore_cmd_response_status [111:104] - connect \builder_csrbank6_cmd_response12_w \main_sdcore_cmd_response_status [103:96] - connect \builder_csrbank6_cmd_response11_w \main_sdcore_cmd_response_status [95:88] - connect \builder_csrbank6_cmd_response10_w \main_sdcore_cmd_response_status [87:80] - connect \builder_csrbank6_cmd_response9_w \main_sdcore_cmd_response_status [79:72] - connect \builder_csrbank6_cmd_response8_w \main_sdcore_cmd_response_status [71:64] - connect \builder_csrbank6_cmd_response7_w \main_sdcore_cmd_response_status [63:56] - connect \builder_csrbank6_cmd_response6_w \main_sdcore_cmd_response_status [55:48] - connect \builder_csrbank6_cmd_response5_w \main_sdcore_cmd_response_status [47:40] - connect \builder_csrbank6_cmd_response4_w \main_sdcore_cmd_response_status [39:32] - connect \builder_csrbank6_cmd_response3_w \main_sdcore_cmd_response_status [31:24] - connect \builder_csrbank6_cmd_response2_w \main_sdcore_cmd_response_status [23:16] - connect \builder_csrbank6_cmd_response1_w \main_sdcore_cmd_response_status [15:8] - connect \builder_csrbank6_cmd_response0_w \main_sdcore_cmd_response_status [7:0] - connect \main_sdcore_cmd_response_we \builder_csrbank6_cmd_response0_we - connect \builder_csrbank6_cmd_event_w \main_sdcore_cmd_event_status - connect \main_sdcore_cmd_event_we \builder_csrbank6_cmd_event_we - connect \builder_csrbank6_data_event_w \main_sdcore_data_event_status - connect \main_sdcore_data_event_we \builder_csrbank6_data_event_we - connect \builder_csrbank6_block_length1_w \main_sdcore_block_length_storage [9:8] - connect \builder_csrbank6_block_length0_w \main_sdcore_block_length_storage [7:0] - connect \builder_csrbank6_block_count3_w \main_sdcore_block_count_storage [31:24] - connect \builder_csrbank6_block_count2_w \main_sdcore_block_count_storage [23:16] - connect \builder_csrbank6_block_count1_w \main_sdcore_block_count_storage [15:8] - connect \builder_csrbank6_block_count0_w \main_sdcore_block_count_storage [7:0] - connect \builder_csrbank7_sel $eq$ls180.v:6102$1670_Y - connect \builder_csrbank7_dma_base7_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base7_re $and$ls180.v:6104$1673_Y - connect \builder_csrbank7_dma_base7_we $and$ls180.v:6105$1677_Y - connect \builder_csrbank7_dma_base6_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base6_re $and$ls180.v:6107$1680_Y - connect \builder_csrbank7_dma_base6_we $and$ls180.v:6108$1684_Y - connect \builder_csrbank7_dma_base5_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base5_re $and$ls180.v:6110$1687_Y - connect \builder_csrbank7_dma_base5_we $and$ls180.v:6111$1691_Y - connect \builder_csrbank7_dma_base4_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base4_re $and$ls180.v:6113$1694_Y - connect \builder_csrbank7_dma_base4_we $and$ls180.v:6114$1698_Y - connect \builder_csrbank7_dma_base3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base3_re $and$ls180.v:6116$1701_Y - connect \builder_csrbank7_dma_base3_we $and$ls180.v:6117$1705_Y - connect \builder_csrbank7_dma_base2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base2_re $and$ls180.v:6119$1708_Y - connect \builder_csrbank7_dma_base2_we $and$ls180.v:6120$1712_Y - connect \builder_csrbank7_dma_base1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base1_re $and$ls180.v:6122$1715_Y - connect \builder_csrbank7_dma_base1_we $and$ls180.v:6123$1719_Y - connect \builder_csrbank7_dma_base0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base0_re $and$ls180.v:6125$1722_Y - connect \builder_csrbank7_dma_base0_we $and$ls180.v:6126$1726_Y - connect \builder_csrbank7_dma_length3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length3_re $and$ls180.v:6128$1729_Y - connect \builder_csrbank7_dma_length3_we $and$ls180.v:6129$1733_Y - connect \builder_csrbank7_dma_length2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length2_re $and$ls180.v:6131$1736_Y - connect \builder_csrbank7_dma_length2_we $and$ls180.v:6132$1740_Y - connect \builder_csrbank7_dma_length1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length1_re $and$ls180.v:6134$1743_Y - connect \builder_csrbank7_dma_length1_we $and$ls180.v:6135$1747_Y - connect \builder_csrbank7_dma_length0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length0_re $and$ls180.v:6137$1750_Y - connect \builder_csrbank7_dma_length0_we $and$ls180.v:6138$1754_Y - connect \builder_csrbank7_dma_enable0_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6140$1757_Y - connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6141$1761_Y - connect \builder_csrbank7_dma_done_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_done_re $and$ls180.v:6143$1764_Y - connect \builder_csrbank7_dma_done_we $and$ls180.v:6144$1768_Y - connect \builder_csrbank7_dma_loop0_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6146$1771_Y - connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6147$1775_Y - connect \builder_csrbank7_dma_offset3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6149$1778_Y - connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6150$1782_Y - connect \builder_csrbank7_dma_offset2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6152$1785_Y - connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6153$1789_Y - connect \builder_csrbank7_dma_offset1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6155$1792_Y - connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6156$1796_Y - connect \builder_csrbank7_dma_offset0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6158$1799_Y - connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6159$1803_Y - connect \builder_csrbank7_dma_base7_w \main_sdmem2block_dma_base_storage [63:56] - connect \builder_csrbank7_dma_base6_w \main_sdmem2block_dma_base_storage [55:48] - connect \builder_csrbank7_dma_base5_w \main_sdmem2block_dma_base_storage [47:40] - connect \builder_csrbank7_dma_base4_w \main_sdmem2block_dma_base_storage [39:32] - connect \builder_csrbank7_dma_base3_w \main_sdmem2block_dma_base_storage [31:24] - connect \builder_csrbank7_dma_base2_w \main_sdmem2block_dma_base_storage [23:16] - connect \builder_csrbank7_dma_base1_w \main_sdmem2block_dma_base_storage [15:8] - connect \builder_csrbank7_dma_base0_w \main_sdmem2block_dma_base_storage [7:0] - connect \builder_csrbank7_dma_length3_w \main_sdmem2block_dma_length_storage [31:24] - connect \builder_csrbank7_dma_length2_w \main_sdmem2block_dma_length_storage [23:16] - connect \builder_csrbank7_dma_length1_w \main_sdmem2block_dma_length_storage [15:8] - connect \builder_csrbank7_dma_length0_w \main_sdmem2block_dma_length_storage [7:0] - connect \builder_csrbank7_dma_enable0_w \main_sdmem2block_dma_enable_storage - connect \builder_csrbank7_dma_done_w \main_sdmem2block_dma_done_status - connect \main_sdmem2block_dma_done_we \builder_csrbank7_dma_done_we - connect \builder_csrbank7_dma_loop0_w \main_sdmem2block_dma_loop_storage - connect \builder_csrbank7_dma_offset3_w \main_sdmem2block_dma_offset_status [31:24] - connect \builder_csrbank7_dma_offset2_w \main_sdmem2block_dma_offset_status [23:16] - connect \builder_csrbank7_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8] - connect \builder_csrbank7_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0] - connect \main_sdmem2block_dma_offset_we \builder_csrbank7_dma_offset0_we - connect \builder_csrbank8_sel $eq$ls180.v:6181$1804_Y - connect \builder_csrbank8_card_detect_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_card_detect_re $and$ls180.v:6183$1807_Y - connect \builder_csrbank8_card_detect_we $and$ls180.v:6184$1811_Y - connect \builder_csrbank8_clocker_divider1_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6186$1814_Y - connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6187$1818_Y - connect \builder_csrbank8_clocker_divider0_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6189$1821_Y - connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6190$1825_Y - connect \main_sdphy_init_initialize_r \builder_interface8_bank_bus_dat_w [0] - connect \main_sdphy_init_initialize_re $and$ls180.v:6192$1828_Y - connect \main_sdphy_init_initialize_we $and$ls180.v:6193$1832_Y - connect \builder_csrbank8_card_detect_w \main_sdphy_status - connect \main_sdphy_we \builder_csrbank8_card_detect_we - connect \builder_csrbank8_clocker_divider1_w \main_sdphy_clocker_storage [8] - connect \builder_csrbank8_clocker_divider0_w \main_sdphy_clocker_storage [7:0] - connect \builder_csrbank9_sel $eq$ls180.v:6198$1833_Y - connect \builder_csrbank9_dfii_control0_r \builder_interface9_bank_bus_dat_w [3:0] - connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6200$1836_Y - connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6201$1840_Y - connect \builder_csrbank9_dfii_pi0_command0_r \builder_interface9_bank_bus_dat_w [5:0] - connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6203$1843_Y - connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6204$1847_Y - connect \main_sdram_command_issue_r \builder_interface9_bank_bus_dat_w [0] - connect \main_sdram_command_issue_re $and$ls180.v:6206$1850_Y - connect \main_sdram_command_issue_we $and$ls180.v:6207$1854_Y - connect \builder_csrbank9_dfii_pi0_address1_r \builder_interface9_bank_bus_dat_w [4:0] - connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6209$1857_Y - connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6210$1861_Y - connect \builder_csrbank9_dfii_pi0_address0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6212$1864_Y - connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6213$1868_Y - connect \builder_csrbank9_dfii_pi0_baddress0_r \builder_interface9_bank_bus_dat_w [1:0] - connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6215$1871_Y - connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6216$1875_Y - connect \builder_csrbank9_dfii_pi0_wrdata1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6218$1878_Y - connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6219$1882_Y - connect \builder_csrbank9_dfii_pi0_wrdata0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6221$1885_Y - connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6222$1889_Y - connect \builder_csrbank9_dfii_pi0_rddata1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6224$1892_Y - connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6225$1896_Y - connect \builder_csrbank9_dfii_pi0_rddata0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6227$1899_Y - connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6228$1903_Y - connect \main_sdram_sel \main_sdram_storage [0] - connect \main_sdram_cke \main_sdram_storage [1] - connect \main_sdram_odt \main_sdram_storage [2] - connect \main_sdram_reset_n \main_sdram_storage [3] - connect \builder_csrbank9_dfii_control0_w \main_sdram_storage - connect \builder_csrbank9_dfii_pi0_command0_w \main_sdram_command_storage - connect \builder_csrbank9_dfii_pi0_address1_w \main_sdram_address_storage [12:8] - connect \builder_csrbank9_dfii_pi0_address0_w \main_sdram_address_storage [7:0] - connect \builder_csrbank9_dfii_pi0_baddress0_w \main_sdram_baddress_storage - connect \builder_csrbank9_dfii_pi0_wrdata1_w \main_sdram_wrdata_storage [15:8] - connect \builder_csrbank9_dfii_pi0_wrdata0_w \main_sdram_wrdata_storage [7:0] - connect \builder_csrbank9_dfii_pi0_rddata1_w \main_sdram_status [15:8] - connect \builder_csrbank9_dfii_pi0_rddata0_w \main_sdram_status [7:0] - connect \main_sdram_we \builder_csrbank9_dfii_pi0_rddata0_we - connect \builder_csrbank10_sel $eq$ls180.v:6243$1904_Y - connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control1_re $and$ls180.v:6245$1907_Y - connect \builder_csrbank10_control1_we $and$ls180.v:6246$1911_Y - connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control0_re $and$ls180.v:6248$1914_Y - connect \builder_csrbank10_control0_we $and$ls180.v:6249$1918_Y - connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_status_re $and$ls180.v:6251$1921_Y - connect \builder_csrbank10_status_we $and$ls180.v:6252$1925_Y - connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_mosi0_re $and$ls180.v:6254$1928_Y - connect \builder_csrbank10_mosi0_we $and$ls180.v:6255$1932_Y - connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_miso_re $and$ls180.v:6257$1935_Y - connect \builder_csrbank10_miso_we $and$ls180.v:6258$1939_Y - connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_cs0_re $and$ls180.v:6260$1942_Y - connect \builder_csrbank10_cs0_we $and$ls180.v:6261$1946_Y - connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_loopback0_re $and$ls180.v:6263$1949_Y - connect \builder_csrbank10_loopback0_we $and$ls180.v:6264$1953_Y - connect \main_spi_master_length1 \main_spi_master_control_storage [15:8] - connect \builder_csrbank10_control1_w \main_spi_master_control_storage [15:8] - connect \builder_csrbank10_control0_w \main_spi_master_control_storage [7:0] - connect \main_spi_master_status_status \main_spi_master_done1 - connect \builder_csrbank10_status_w \main_spi_master_status_status - connect \main_spi_master_status_we \builder_csrbank10_status_we - connect \builder_csrbank10_mosi0_w \main_spi_master_mosi_storage - connect \builder_csrbank10_miso_w \main_spi_master_miso_status - connect \main_spi_master_miso_we \builder_csrbank10_miso_we - connect \main_spi_master_sel \main_spi_master_cs_storage - connect \builder_csrbank10_cs0_w \main_spi_master_cs_storage - connect \builder_csrbank10_loopback0_w \main_spi_master_loopback_storage - connect \builder_csrbank11_sel $eq$ls180.v:6283$1955_Y - connect \builder_csrbank11_control1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_control1_re $and$ls180.v:6285$1958_Y - connect \builder_csrbank11_control1_we $and$ls180.v:6286$1962_Y - connect \builder_csrbank11_control0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_control0_re $and$ls180.v:6288$1965_Y - connect \builder_csrbank11_control0_we $and$ls180.v:6289$1969_Y - connect \builder_csrbank11_status_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_status_re $and$ls180.v:6291$1972_Y - connect \builder_csrbank11_status_we $and$ls180.v:6292$1976_Y - connect \builder_csrbank11_mosi0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_mosi0_re $and$ls180.v:6294$1979_Y - connect \builder_csrbank11_mosi0_we $and$ls180.v:6295$1983_Y - connect \builder_csrbank11_miso_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_miso_re $and$ls180.v:6297$1986_Y - connect \builder_csrbank11_miso_we $and$ls180.v:6298$1990_Y - connect \builder_csrbank11_cs0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_cs0_re $and$ls180.v:6300$1993_Y - connect \builder_csrbank11_cs0_we $and$ls180.v:6301$1997_Y - connect \builder_csrbank11_loopback0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_loopback0_re $and$ls180.v:6303$2000_Y - connect \builder_csrbank11_loopback0_we $and$ls180.v:6304$2004_Y - connect \builder_csrbank11_clk_divider1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6306$2007_Y - connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6307$2011_Y - connect \builder_csrbank11_clk_divider0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6309$2014_Y - connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6310$2018_Y - connect \libresocsim_length1 \libresocsim_control_storage [15:8] - connect \builder_csrbank11_control1_w \libresocsim_control_storage [15:8] - connect \builder_csrbank11_control0_w \libresocsim_control_storage [7:0] - connect \libresocsim_status_status \libresocsim_done1 - connect \builder_csrbank11_status_w \libresocsim_status_status - connect \libresocsim_status_we \builder_csrbank11_status_we - connect \builder_csrbank11_mosi0_w \libresocsim_mosi_storage - connect \builder_csrbank11_miso_w \libresocsim_miso_status - connect \libresocsim_miso_we \builder_csrbank11_miso_we - connect \libresocsim_sel \libresocsim_cs_storage - connect \builder_csrbank11_cs0_w \libresocsim_cs_storage - connect \builder_csrbank11_loopback0_w \libresocsim_loopback_storage - connect \builder_csrbank11_clk_divider1_w \libresocsim_storage [15:8] - connect \builder_csrbank11_clk_divider0_w \libresocsim_storage [7:0] - connect \builder_csrbank12_sel $eq$ls180.v:6331$2020_Y - connect \builder_csrbank12_load3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load3_re $and$ls180.v:6333$2023_Y - connect \builder_csrbank12_load3_we $and$ls180.v:6334$2027_Y - connect \builder_csrbank12_load2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load2_re $and$ls180.v:6336$2030_Y - connect \builder_csrbank12_load2_we $and$ls180.v:6337$2034_Y - connect \builder_csrbank12_load1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load1_re $and$ls180.v:6339$2037_Y - connect \builder_csrbank12_load1_we $and$ls180.v:6340$2041_Y - connect \builder_csrbank12_load0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load0_re $and$ls180.v:6342$2044_Y - connect \builder_csrbank12_load0_we $and$ls180.v:6343$2048_Y - connect \builder_csrbank12_reload3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload3_re $and$ls180.v:6345$2051_Y - connect \builder_csrbank12_reload3_we $and$ls180.v:6346$2055_Y - connect \builder_csrbank12_reload2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload2_re $and$ls180.v:6348$2058_Y - connect \builder_csrbank12_reload2_we $and$ls180.v:6349$2062_Y - connect \builder_csrbank12_reload1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload1_re $and$ls180.v:6351$2065_Y - connect \builder_csrbank12_reload1_we $and$ls180.v:6352$2069_Y - connect \builder_csrbank12_reload0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload0_re $and$ls180.v:6354$2072_Y - connect \builder_csrbank12_reload0_we $and$ls180.v:6355$2076_Y - connect \builder_csrbank12_en0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_en0_re $and$ls180.v:6357$2079_Y - connect \builder_csrbank12_en0_we $and$ls180.v:6358$2083_Y - connect \builder_csrbank12_update_value0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_update_value0_re $and$ls180.v:6360$2086_Y - connect \builder_csrbank12_update_value0_we $and$ls180.v:6361$2090_Y - connect \builder_csrbank12_value3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value3_re $and$ls180.v:6363$2093_Y - connect \builder_csrbank12_value3_we $and$ls180.v:6364$2097_Y - connect \builder_csrbank12_value2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value2_re $and$ls180.v:6366$2100_Y - connect \builder_csrbank12_value2_we $and$ls180.v:6367$2104_Y - connect \builder_csrbank12_value1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value1_re $and$ls180.v:6369$2107_Y - connect \builder_csrbank12_value1_we $and$ls180.v:6370$2111_Y - connect \builder_csrbank12_value0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value0_re $and$ls180.v:6372$2114_Y - connect \builder_csrbank12_value0_we $and$ls180.v:6373$2118_Y - connect \main_libresocsim_eventmanager_status_r \builder_interface12_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6375$2121_Y - connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6376$2125_Y - connect \main_libresocsim_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6378$2128_Y - connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6379$2132_Y - connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6381$2135_Y - connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6382$2139_Y - connect \builder_csrbank12_load3_w \main_libresocsim_load_storage [31:24] - connect \builder_csrbank12_load2_w \main_libresocsim_load_storage [23:16] - connect \builder_csrbank12_load1_w \main_libresocsim_load_storage [15:8] - connect \builder_csrbank12_load0_w \main_libresocsim_load_storage [7:0] - connect \builder_csrbank12_reload3_w \main_libresocsim_reload_storage [31:24] - connect \builder_csrbank12_reload2_w \main_libresocsim_reload_storage [23:16] - connect \builder_csrbank12_reload1_w \main_libresocsim_reload_storage [15:8] - connect \builder_csrbank12_reload0_w \main_libresocsim_reload_storage [7:0] - connect \builder_csrbank12_en0_w \main_libresocsim_en_storage - connect \builder_csrbank12_update_value0_w \main_libresocsim_update_value_storage - connect \builder_csrbank12_value3_w \main_libresocsim_value_status [31:24] - connect \builder_csrbank12_value2_w \main_libresocsim_value_status [23:16] - connect \builder_csrbank12_value1_w \main_libresocsim_value_status [15:8] - connect \builder_csrbank12_value0_w \main_libresocsim_value_status [7:0] - connect \main_libresocsim_value_we \builder_csrbank12_value0_we - connect \builder_csrbank12_ev_enable0_w \main_libresocsim_eventmanager_storage - connect \builder_csrbank13_sel $eq$ls180.v:6399$2140_Y - connect \main_uart_rxtx_r \builder_interface13_bank_bus_dat_w - connect \main_uart_rxtx_re $and$ls180.v:6401$2143_Y - connect \main_uart_rxtx_we $and$ls180.v:6402$2147_Y - connect \builder_csrbank13_txfull_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_txfull_re $and$ls180.v:6404$2150_Y - connect \builder_csrbank13_txfull_we $and$ls180.v:6405$2154_Y - connect \builder_csrbank13_rxempty_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_rxempty_re $and$ls180.v:6407$2157_Y - connect \builder_csrbank13_rxempty_we $and$ls180.v:6408$2161_Y - connect \main_uart_eventmanager_status_r \builder_interface13_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_status_re $and$ls180.v:6410$2164_Y - connect \main_uart_eventmanager_status_we $and$ls180.v:6411$2168_Y - connect \main_uart_eventmanager_pending_r \builder_interface13_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_pending_re $and$ls180.v:6413$2171_Y - connect \main_uart_eventmanager_pending_we $and$ls180.v:6414$2175_Y - connect \builder_csrbank13_ev_enable0_r \builder_interface13_bank_bus_dat_w [1:0] - connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6416$2178_Y - connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6417$2182_Y - connect \builder_csrbank13_txempty_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_txempty_re $and$ls180.v:6419$2185_Y - connect \builder_csrbank13_txempty_we $and$ls180.v:6420$2189_Y - connect \builder_csrbank13_rxfull_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_rxfull_re $and$ls180.v:6422$2192_Y - connect \builder_csrbank13_rxfull_we $and$ls180.v:6423$2196_Y - connect \builder_csrbank13_txfull_w \main_uart_txfull_status - connect \main_uart_txfull_we \builder_csrbank13_txfull_we - connect \builder_csrbank13_rxempty_w \main_uart_rxempty_status - connect \main_uart_rxempty_we \builder_csrbank13_rxempty_we - connect \builder_csrbank13_ev_enable0_w \main_uart_eventmanager_storage - connect \builder_csrbank13_txempty_w \main_uart_txempty_status - connect \main_uart_txempty_we \builder_csrbank13_txempty_we - connect \builder_csrbank13_rxfull_w \main_uart_rxfull_status - connect \main_uart_rxfull_we \builder_csrbank13_rxfull_we - connect \builder_csrbank14_sel $eq$ls180.v:6433$2197_Y - connect \builder_csrbank14_tuning_word3_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6435$2200_Y - connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6436$2204_Y - connect \builder_csrbank14_tuning_word2_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6438$2207_Y - connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6439$2211_Y - connect \builder_csrbank14_tuning_word1_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6441$2214_Y - connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6442$2218_Y - connect \builder_csrbank14_tuning_word0_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6444$2221_Y - connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6445$2225_Y - connect \builder_csrbank14_tuning_word3_w \main_uart_phy_storage [31:24] - connect \builder_csrbank14_tuning_word2_w \main_uart_phy_storage [23:16] - connect \builder_csrbank14_tuning_word1_w \main_uart_phy_storage [15:8] - connect \builder_csrbank14_tuning_word0_w \main_uart_phy_storage [7:0] - connect \builder_csr_interconnect_adr \builder_libresocsim_adr - connect \builder_csr_interconnect_we \builder_libresocsim_we - connect \builder_csr_interconnect_dat_w \builder_libresocsim_dat_w - connect \builder_libresocsim_dat_r \builder_csr_interconnect_dat_r - connect \builder_interface0_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface1_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface2_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface3_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface4_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface5_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface6_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface7_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface8_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface9_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface10_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface11_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface12_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface13_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface14_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface0_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface1_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface2_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface3_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface4_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface5_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface6_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface7_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface8_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface9_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface10_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface11_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface12_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface13_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface14_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface0_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface1_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface2_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface3_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface4_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface5_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface6_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface7_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface8_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface9_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface10_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface11_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface14_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_csr_interconnect_dat_r $or$ls180.v:6499$2239_Y - connect \sdrio_clk \sys_clk_1 - connect \sdrio_clk_1 \sys_clk_1 - connect \sdrio_clk_2 \sys_clk_1 - connect \sdrio_clk_3 \sys_clk_1 - connect \sdrio_clk_4 \sys_clk_1 - connect \sdrio_clk_5 \sys_clk_1 - connect \sdrio_clk_6 \sys_clk_1 - connect \sdrio_clk_7 \sys_clk_1 - connect \sdrio_clk_8 \sys_clk_1 - connect \sdrio_clk_9 \sys_clk_1 - connect \sdrio_clk_10 \sys_clk_1 - connect \sdrio_clk_11 \sys_clk_1 - connect \sdrio_clk_12 \sys_clk_1 - connect \sdrio_clk_13 \sys_clk_1 - connect \sdrio_clk_14 \sys_clk_1 - connect \sdrio_clk_15 \sys_clk_1 - connect \sdrio_clk_16 \sys_clk_1 - connect \sdrio_clk_17 \sys_clk_1 - connect \sdrio_clk_18 \sys_clk_1 - connect \sdrio_clk_19 \sys_clk_1 - connect \sdrio_clk_20 \sys_clk_1 - connect \sdrio_clk_21 \sys_clk_1 - connect \sdrio_clk_22 \sys_clk_1 - connect \sdrio_clk_23 \sys_clk_1 - connect \sdrio_clk_24 \sys_clk_1 - connect \sdrio_clk_25 \sys_clk_1 - connect \sdrio_clk_26 \sys_clk_1 - connect \sdrio_clk_27 \sys_clk_1 - connect \sdrio_clk_28 \sys_clk_1 - connect \sdrio_clk_29 \sys_clk_1 - connect \sdrio_clk_30 \sys_clk_1 - connect \sdrio_clk_31 \sys_clk_1 - connect \sdrio_clk_32 \sys_clk_1 - connect \sdrio_clk_33 \sys_clk_1 - connect \sdrio_clk_34 \sys_clk_1 - connect \sdrio_clk_35 \sys_clk_1 - connect \sdrio_clk_36 \sys_clk_1 - connect \sdrio_clk_37 \sys_clk_1 - connect \sdrio_clk_38 \sys_clk_1 - connect \sdrio_clk_39 \sys_clk_1 - connect \sdrio_clk_40 \sys_clk_1 - connect \sdrio_clk_41 \sys_clk_1 - connect \sdrio_clk_42 \sys_clk_1 - connect \sdrio_clk_43 \sys_clk_1 - connect \sdrio_clk_44 \sys_clk_1 - connect \sdrio_clk_45 \sys_clk_1 - connect \sdrio_clk_46 \sys_clk_1 - connect \sdrio_clk_47 \sys_clk_1 - connect \sdrio_clk_48 \sys_clk_1 - connect \sdrio_clk_49 \sys_clk_1 - connect \sdrio_clk_50 \sys_clk_1 - connect \sdrio_clk_51 \sys_clk_1 - connect \sdrio_clk_52 \sys_clk_1 - connect \sdrio_clk_53 \sys_clk_1 - connect \sdrio_clk_54 \sys_clk_1 - connect \sdrio_clk_55 \sys_clk_1 - connect \main_uart_phy_rx \builder_multiregimpl0_regs1 - connect \main_pwm0_enable \main_pwm0_enable_storage - connect \main_pwm0_width \main_pwm0_width_storage - connect \main_pwm0_period \main_pwm0_period_storage - connect \main_pwm1_enable \main_pwm1_enable_storage - connect \main_pwm1_width \main_pwm1_width_storage - connect \main_pwm1_period \main_pwm1_period_storage - connect \sdrio_clk_56 \sys_clk_1 - connect \sdrio_clk_57 \sys_clk_1 - connect \sdrio_clk_58 \sys_clk_1 - connect \sdrio_clk_59 \sys_clk_1 - connect \sdrio_clk_60 \sys_clk_1 - connect \sdrio_clk_61 \sys_clk_1 - connect \sdrio_clk_62 \sys_clk_1 - connect \sdrio_clk_63 \sys_clk_1 - connect \sdrio_clk_64 \sys_clk_1 - connect \sdrio_clk_65 \sys_clk_1 - connect \sdrio_clk_66 \sys_clk_1 - connect \sdrio_clk_67 \sys_clk_1 - connect \sdrio_clk_68 \sys_clk_1 - connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10052$2705_DATA - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10070$2712_DATA - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10084$2719_DATA - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10098$2726_DATA - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10112$2733_DATA - connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 - connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 - connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 - connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 - connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 - connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10160$2754_DATA - connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 - connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10174$2761_DATA -end -attribute \src "libresoc.v:44776.1-44787.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.pll" -attribute \generator "nMigen" -module \pll - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:80" - wire input 1 \clk_24_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:81" - wire output 4 \clk_pll_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:82" - wire input 2 \rst - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:527" - wire output 3 \rst$1 - connect \rst$1 \rst - connect \clk_pll_o \clk_24_i -end -attribute \src "libresoc.v:44791.1-44875.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick - attribute \src "libresoc.v:44848.17-44848.91" - wire $not$libresoc.v:44848$1401_Y - attribute \src "libresoc.v:44850.18-44850.93" - wire $not$libresoc.v:44850$1403_Y - attribute \src "libresoc.v:44852.18-44852.93" - wire $not$libresoc.v:44852$1405_Y - attribute \src "libresoc.v:44853.17-44853.138" - wire width 8 $not$libresoc.v:44853$1406_Y - attribute \src "libresoc.v:44855.18-44855.93" - wire $not$libresoc.v:44855$1408_Y - attribute \src "libresoc.v:44857.18-44857.93" - wire $not$libresoc.v:44857$1410_Y - attribute \src "libresoc.v:44859.18-44859.93" - wire $not$libresoc.v:44859$1412_Y - attribute \src "libresoc.v:44862.17-44862.91" - wire $not$libresoc.v:44862$1415_Y - attribute \src "libresoc.v:44849.18-44849.116" - wire $reduce_or$libresoc.v:44849$1402_Y - attribute \src "libresoc.v:44851.18-44851.122" - wire $reduce_or$libresoc.v:44851$1404_Y - attribute \src "libresoc.v:44854.18-44854.128" - wire $reduce_or$libresoc.v:44854$1407_Y - attribute \src "libresoc.v:44856.18-44856.134" - wire $reduce_or$libresoc.v:44856$1409_Y - attribute \src "libresoc.v:44858.18-44858.140" - wire $reduce_or$libresoc.v:44858$1411_Y - attribute \src "libresoc.v:44860.18-44860.90" - wire $reduce_or$libresoc.v:44860$1413_Y - attribute \src "libresoc.v:44861.17-44861.103" - wire $reduce_or$libresoc.v:44861$1414_Y - attribute \src "libresoc.v:44863.17-44863.109" - wire $reduce_or$libresoc.v:44863$1416_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:44848$1401 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:44848$1401_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:44850$1403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:44850$1403_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:44852$1405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:44852$1405_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:44853$1406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:44853$1406_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:44855$1408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:44855$1408_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:44857$1410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:44857$1410_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:44859$1412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:44859$1412_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:44862$1415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:44862$1415_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:44849$1402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:44849$1402_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:44851$1404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:44851$1404_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:44854$1407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:44854$1407_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:44856$1409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:44856$1409_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:44858$1411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:44858$1411_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:44860$1413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:44860$1413_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:44861$1414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:44861$1414_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:44863$1416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:44863$1416_Y - end - connect \$7 $not$libresoc.v:44848$1401_Y - connect \$12 $reduce_or$libresoc.v:44849$1402_Y - connect \$11 $not$libresoc.v:44850$1403_Y - connect \$16 $reduce_or$libresoc.v:44851$1404_Y - connect \$15 $not$libresoc.v:44852$1405_Y - connect \$1 $not$libresoc.v:44853$1406_Y - connect \$20 $reduce_or$libresoc.v:44854$1407_Y - connect \$19 $not$libresoc.v:44855$1408_Y - connect \$24 $reduce_or$libresoc.v:44856$1409_Y - connect \$23 $not$libresoc.v:44857$1410_Y - connect \$28 $reduce_or$libresoc.v:44858$1411_Y - connect \$27 $not$libresoc.v:44859$1412_Y - connect \$31 $reduce_or$libresoc.v:44860$1413_Y - connect \$4 $reduce_or$libresoc.v:44861$1414_Y - connect \$3 $not$libresoc.v:44862$1415_Y - connect \$8 $reduce_or$libresoc.v:44863$1416_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:44879.1-44963.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$1 - attribute \src "libresoc.v:44936.17-44936.91" - wire $not$libresoc.v:44936$1417_Y - attribute \src "libresoc.v:44938.18-44938.93" - wire $not$libresoc.v:44938$1419_Y - attribute \src "libresoc.v:44940.18-44940.93" - wire $not$libresoc.v:44940$1421_Y - attribute \src "libresoc.v:44941.17-44941.138" - wire width 8 $not$libresoc.v:44941$1422_Y - attribute \src "libresoc.v:44943.18-44943.93" - wire $not$libresoc.v:44943$1424_Y - attribute \src "libresoc.v:44945.18-44945.93" - wire $not$libresoc.v:44945$1426_Y - attribute \src "libresoc.v:44947.18-44947.93" - wire $not$libresoc.v:44947$1428_Y - attribute \src "libresoc.v:44950.17-44950.91" - wire $not$libresoc.v:44950$1431_Y - attribute \src "libresoc.v:44937.18-44937.116" - wire $reduce_or$libresoc.v:44937$1418_Y - attribute \src "libresoc.v:44939.18-44939.122" - wire $reduce_or$libresoc.v:44939$1420_Y - attribute \src "libresoc.v:44942.18-44942.128" - wire $reduce_or$libresoc.v:44942$1423_Y - attribute \src "libresoc.v:44944.18-44944.134" - wire $reduce_or$libresoc.v:44944$1425_Y - attribute \src "libresoc.v:44946.18-44946.140" - wire $reduce_or$libresoc.v:44946$1427_Y - attribute \src "libresoc.v:44948.18-44948.90" - wire $reduce_or$libresoc.v:44948$1429_Y - attribute \src "libresoc.v:44949.17-44949.103" - wire $reduce_or$libresoc.v:44949$1430_Y - attribute \src "libresoc.v:44951.17-44951.109" - wire $reduce_or$libresoc.v:44951$1432_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:44936$1417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:44936$1417_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:44938$1419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:44938$1419_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:44940$1421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:44940$1421_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:44941$1422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:44941$1422_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:44943$1424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:44943$1424_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:44945$1426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:44945$1426_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:44947$1428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:44947$1428_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:44950$1431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:44950$1431_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:44937$1418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:44937$1418_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:44939$1420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:44939$1420_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:44942$1423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:44942$1423_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:44944$1425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:44944$1425_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:44946$1427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:44946$1427_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:44948$1429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:44948$1429_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:44949$1430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:44949$1430_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:44951$1432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:44951$1432_Y - end - connect \$7 $not$libresoc.v:44936$1417_Y - connect \$12 $reduce_or$libresoc.v:44937$1418_Y - connect \$11 $not$libresoc.v:44938$1419_Y - connect \$16 $reduce_or$libresoc.v:44939$1420_Y - connect \$15 $not$libresoc.v:44940$1421_Y - connect \$1 $not$libresoc.v:44941$1422_Y - connect \$20 $reduce_or$libresoc.v:44942$1423_Y - connect \$19 $not$libresoc.v:44943$1424_Y - connect \$24 $reduce_or$libresoc.v:44944$1425_Y - connect \$23 $not$libresoc.v:44945$1426_Y - connect \$28 $reduce_or$libresoc.v:44946$1427_Y - connect \$27 $not$libresoc.v:44947$1428_Y - connect \$31 $reduce_or$libresoc.v:44948$1429_Y - connect \$4 $reduce_or$libresoc.v:44949$1430_Y - connect \$3 $not$libresoc.v:44950$1431_Y - connect \$8 $reduce_or$libresoc.v:44951$1432_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:44967.1-45782.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap" -attribute \generator "nMigen" -module \sprmap - attribute \src "libresoc.v:45094.3-45124.6" - wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:45125.3-45155.6" - wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:44968.7-44968.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:45156.3-45468.6" - wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:45469.3-45781.6" - wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:45094.3-45124.6" - wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:45125.3-45155.6" - wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:45156.3-45468.6" - wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:45469.3-45781.6" - wire $1\spr_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 3 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 4 \fast_o_ok - attribute \src "libresoc.v:44968.7-44968.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" - wire width 10 input 5 \spr_i - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 output 1 \spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \spr_o_ok - attribute \src "libresoc.v:44968.7-44968.20" - process $proc$libresoc.v:44968$1437 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:45094.3-45124.6" - process $proc$libresoc.v:45094$1433 - assign { } { } - assign { } { } - assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:45095.5-45095.29" - switch \initial - attribute \src "libresoc.v:45095.9-45095.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000001 - assign { } { } - assign $1\fast_o[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001000 - assign { } { } - assign $1\fast_o[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 - assign { } { } - assign $1\fast_o[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010110 - assign { } { } - assign $1\fast_o[2:0] 3'110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011010 - assign { } { } - assign $1\fast_o[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011011 - assign { } { } - assign $1\fast_o[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100001100 - assign { } { } - assign $1\fast_o[2:0] 3'111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101111 - assign { } { } - assign $1\fast_o[2:0] 3'010 - case - assign $1\fast_o[2:0] 3'000 - end - sync always - update \fast_o $0\fast_o[2:0] - end - attribute \src "libresoc.v:45125.3-45155.6" - process $proc$libresoc.v:45125$1434 - assign { } { } - assign { } { } - assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:45126.5-45126.29" - switch \initial - attribute \src "libresoc.v:45126.9-45126.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000001 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001000 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010110 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011010 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011011 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100001100 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101111 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - case - assign $1\fast_o_ok[0:0] 1'0 - end - sync always - update \fast_o_ok $0\fast_o_ok[0:0] - end - attribute \src "libresoc.v:45156.3-45468.6" - process $proc$libresoc.v:45156$1435 - assign { } { } - assign { } { } - assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:45157.5-45157.29" - switch \initial - attribute \src "libresoc.v:45157.9-45157.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000000001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001101 - assign { } { } - assign $1\spr_o[9:0] 10'0000000100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000000110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010011 - assign { } { } - assign $1\spr_o[9:0] 10'0000000111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011100 - assign { } { } - assign $1\spr_o[9:0] 10'0000001011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000001100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000110000 - assign { } { } - assign $1\spr_o[9:0] 10'0000001101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000111101 - assign { } { } - assign $1\spr_o[9:0] 10'0000001110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000000 - assign { } { } - assign $1\spr_o[9:0] 10'0000001111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\spr_o[9:0] 10'0000010000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000010 - assign { } { } - assign $1\spr_o[9:0] 10'0000010001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000010010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010001000 - assign { } { } - assign $1\spr_o[9:0] 10'0000010011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000010100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011000 - assign { } { } - assign $1\spr_o[9:0] 10'0000010101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011001 - assign { } { } - assign $1\spr_o[9:0] 10'0000010110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000010111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011110 - assign { } { } - assign $1\spr_o[9:0] 10'0000011000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011111 - assign { } { } - assign $1\spr_o[9:0] 10'0000011001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010110000 - assign { } { } - assign $1\spr_o[9:0] 10'0000011010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010110100 - assign { } { } - assign $1\spr_o[9:0] 10'0000011011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111010 - assign { } { } - assign $1\spr_o[9:0] 10'0000011100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111011 - assign { } { } - assign $1\spr_o[9:0] 10'0000011101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111100 - assign { } { } - assign $1\spr_o[9:0] 10'0000011110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111110 - assign { } { } - assign $1\spr_o[9:0] 10'0000011111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000000 - assign { } { } - assign $1\spr_o[9:0] 10'0000100000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000100001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100001101 - assign { } { } - assign $1\spr_o[9:0] 10'0000100011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000100100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000100101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000100110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010011 - assign { } { } - assign $1\spr_o[9:0] 10'0000100111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011011 - assign { } { } - assign $1\spr_o[9:0] 10'0000101000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011100 - assign { } { } - assign $1\spr_o[9:0] 10'0000101001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000101010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011110 - assign { } { } - assign $1\spr_o[9:0] 10'0000101011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011111 - assign { } { } - assign $1\spr_o[9:0] 10'0000101100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110000 - assign { } { } - assign $1\spr_o[9:0] 10'0000101101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110001 - assign { } { } - assign $1\spr_o[9:0] 10'0000101110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110010 - assign { } { } - assign $1\spr_o[9:0] 10'0000101111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110011 - assign { } { } - assign $1\spr_o[9:0] 10'0000110000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110100 - assign { } { } - assign $1\spr_o[9:0] 10'0000110001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110101 - assign { } { } - assign $1\spr_o[9:0] 10'0000110010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110110 - assign { } { } - assign $1\spr_o[9:0] 10'0000110011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111001 - assign { } { } - assign $1\spr_o[9:0] 10'0000110100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111010 - assign { } { } - assign $1\spr_o[9:0] 10'0000110101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111011 - assign { } { } - assign $1\spr_o[9:0] 10'0000110110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111110 - assign { } { } - assign $1\spr_o[9:0] 10'0000110111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111111 - assign { } { } - assign $1\spr_o[9:0] 10'0000111000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000111001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000111010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000111011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010011 - assign { } { } - assign $1\spr_o[9:0] 10'0000111100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000111101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110111110 - assign { } { } - assign $1\spr_o[9:0] 10'0000111110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000111111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000000 - assign { } { } - assign $1\spr_o[9:0] 10'0001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000001 - assign { } { } - assign $1\spr_o[9:0] 10'0001000001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000010 - assign { } { } - assign $1\spr_o[9:0] 10'0001000010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000011 - assign { } { } - assign $1\spr_o[9:0] 10'0001000011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000100 - assign { } { } - assign $1\spr_o[9:0] 10'0001000100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000101 - assign { } { } - assign $1\spr_o[9:0] 10'0001000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000110 - assign { } { } - assign $1\spr_o[9:0] 10'0001000110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000111 - assign { } { } - assign $1\spr_o[9:0] 10'0001000111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001000 - assign { } { } - assign $1\spr_o[9:0] 10'0001001000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001011 - assign { } { } - assign $1\spr_o[9:0] 10'0001001001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001100 - assign { } { } - assign $1\spr_o[9:0] 10'0001001010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001101 - assign { } { } - assign $1\spr_o[9:0] 10'0001001011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001110 - assign { } { } - assign $1\spr_o[9:0] 10'0001001100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010000 - assign { } { } - assign $1\spr_o[9:0] 10'0001001101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010001 - assign { } { } - assign $1\spr_o[9:0] 10'0001001110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010010 - assign { } { } - assign $1\spr_o[9:0] 10'0001001111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010011 - assign { } { } - assign $1\spr_o[9:0] 10'0001010000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010100 - assign { } { } - assign $1\spr_o[9:0] 10'0001010001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010101 - assign { } { } - assign $1\spr_o[9:0] 10'0001010010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010110 - assign { } { } - assign $1\spr_o[9:0] 10'0001010011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010111 - assign { } { } - assign $1\spr_o[9:0] 10'0001010100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011000 - assign { } { } - assign $1\spr_o[9:0] 10'0001010101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011011 - assign { } { } - assign $1\spr_o[9:0] 10'0001010110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011100 - assign { } { } - assign $1\spr_o[9:0] 10'0001010111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011101 - assign { } { } - assign $1\spr_o[9:0] 10'0001011000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011110 - assign { } { } - assign $1\spr_o[9:0] 10'0001011001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100000 - assign { } { } - assign $1\spr_o[9:0] 10'0001011010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100001 - assign { } { } - assign $1\spr_o[9:0] 10'0001011011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100010 - assign { } { } - assign $1\spr_o[9:0] 10'0001011100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100011 - assign { } { } - assign $1\spr_o[9:0] 10'0001011101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100100 - assign { } { } - assign $1\spr_o[9:0] 10'0001011110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100101 - assign { } { } - assign $1\spr_o[9:0] 10'0001011111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100110 - assign { } { } - assign $1\spr_o[9:0] 10'0001100000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101000 - assign { } { } - assign $1\spr_o[9:0] 10'0001100001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101001 - assign { } { } - assign $1\spr_o[9:0] 10'0001100010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101010 - assign { } { } - assign $1\spr_o[9:0] 10'0001100011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101011 - assign { } { } - assign $1\spr_o[9:0] 10'0001100100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100110000 - assign { } { } - assign $1\spr_o[9:0] 10'0001100110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100110111 - assign { } { } - assign $1\spr_o[9:0] 10'0001100111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010000 - assign { } { } - assign $1\spr_o[9:0] 10'0001101000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010001 - assign { } { } - assign $1\spr_o[9:0] 10'0001101001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010111 - assign { } { } - assign $1\spr_o[9:0] 10'0001101010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1110000000 - assign { } { } - assign $1\spr_o[9:0] 10'0001101011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1110000010 - assign { } { } - assign $1\spr_o[9:0] 10'0001101100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1111111111 - assign { } { } - assign $1\spr_o[9:0] 10'0001101101 - case - assign $1\spr_o[9:0] 10'0000000000 - end - sync always - update \spr_o $0\spr_o[9:0] - end - attribute \src "libresoc.v:45469.3-45781.6" - process $proc$libresoc.v:45469$1436 - assign { } { } - assign { } { } - assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:45470.5-45470.29" - switch \initial - attribute \src "libresoc.v:45470.9-45470.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000111101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010001000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010110100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100001101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110111110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100110111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1110000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1110000010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1111111111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - case - assign $1\spr_o_ok[0:0] 1'0 - end - sync always - update \spr_o_ok $0\spr_o_ok[0:0] - end -end -attribute \src "libresoc.v:45786.1-46601.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap" -attribute \generator "nMigen" -module \sprmap$2 - attribute \src "libresoc.v:45913.3-45943.6" - wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:45944.3-45974.6" - wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:45787.7-45787.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:45975.3-46287.6" - wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:46288.3-46600.6" - wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:45913.3-45943.6" - wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:45944.3-45974.6" - wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:45975.3-46287.6" - wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:46288.3-46600.6" - wire $1\spr_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 3 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 4 \fast_o_ok - attribute \src "libresoc.v:45787.7-45787.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" - wire width 10 input 5 \spr_i - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 output 1 \spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \spr_o_ok - attribute \src "libresoc.v:45787.7-45787.20" - process $proc$libresoc.v:45787$1442 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:45913.3-45943.6" - process $proc$libresoc.v:45913$1438 - assign { } { } - assign { } { } - assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:45914.5-45914.29" - switch \initial - attribute \src "libresoc.v:45914.9-45914.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000001 - assign { } { } - assign $1\fast_o[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001000 - assign { } { } - assign $1\fast_o[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 - assign { } { } - assign $1\fast_o[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010110 - assign { } { } - assign $1\fast_o[2:0] 3'110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011010 - assign { } { } - assign $1\fast_o[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011011 - assign { } { } - assign $1\fast_o[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100001100 - assign { } { } - assign $1\fast_o[2:0] 3'111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101111 - assign { } { } - assign $1\fast_o[2:0] 3'010 - case - assign $1\fast_o[2:0] 3'000 - end - sync always - update \fast_o $0\fast_o[2:0] - end - attribute \src "libresoc.v:45944.3-45974.6" - process $proc$libresoc.v:45944$1439 - assign { } { } - assign { } { } - assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:45945.5-45945.29" - switch \initial - attribute \src "libresoc.v:45945.9-45945.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000001 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001000 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010110 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011010 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011011 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100001100 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101111 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - case - assign $1\fast_o_ok[0:0] 1'0 - end - sync always - update \fast_o_ok $0\fast_o_ok[0:0] - end - attribute \src "libresoc.v:45975.3-46287.6" - process $proc$libresoc.v:45975$1440 - assign { } { } - assign { } { } - assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:45976.5-45976.29" - switch \initial - attribute \src "libresoc.v:45976.9-45976.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000000001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001101 - assign { } { } - assign $1\spr_o[9:0] 10'0000000100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000000110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010011 - assign { } { } - assign $1\spr_o[9:0] 10'0000000111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011100 - assign { } { } - assign $1\spr_o[9:0] 10'0000001011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000001100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000110000 - assign { } { } - assign $1\spr_o[9:0] 10'0000001101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000111101 - assign { } { } - assign $1\spr_o[9:0] 10'0000001110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000000 - assign { } { } - assign $1\spr_o[9:0] 10'0000001111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\spr_o[9:0] 10'0000010000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000010 - assign { } { } - assign $1\spr_o[9:0] 10'0000010001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000010010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010001000 - assign { } { } - assign $1\spr_o[9:0] 10'0000010011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000010100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011000 - assign { } { } - assign $1\spr_o[9:0] 10'0000010101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011001 - assign { } { } - assign $1\spr_o[9:0] 10'0000010110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000010111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011110 - assign { } { } - assign $1\spr_o[9:0] 10'0000011000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011111 - assign { } { } - assign $1\spr_o[9:0] 10'0000011001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010110000 - assign { } { } - assign $1\spr_o[9:0] 10'0000011010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010110100 - assign { } { } - assign $1\spr_o[9:0] 10'0000011011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111010 - assign { } { } - assign $1\spr_o[9:0] 10'0000011100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111011 - assign { } { } - assign $1\spr_o[9:0] 10'0000011101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111100 - assign { } { } - assign $1\spr_o[9:0] 10'0000011110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111110 - assign { } { } - assign $1\spr_o[9:0] 10'0000011111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000000 - assign { } { } - assign $1\spr_o[9:0] 10'0000100000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000100001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100001101 - assign { } { } - assign $1\spr_o[9:0] 10'0000100011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000100100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000100101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000100110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010011 - assign { } { } - assign $1\spr_o[9:0] 10'0000100111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011011 - assign { } { } - assign $1\spr_o[9:0] 10'0000101000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011100 - assign { } { } - assign $1\spr_o[9:0] 10'0000101001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000101010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011110 - assign { } { } - assign $1\spr_o[9:0] 10'0000101011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011111 - assign { } { } - assign $1\spr_o[9:0] 10'0000101100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110000 - assign { } { } - assign $1\spr_o[9:0] 10'0000101101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110001 - assign { } { } - assign $1\spr_o[9:0] 10'0000101110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110010 - assign { } { } - assign $1\spr_o[9:0] 10'0000101111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110011 - assign { } { } - assign $1\spr_o[9:0] 10'0000110000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110100 - assign { } { } - assign $1\spr_o[9:0] 10'0000110001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110101 - assign { } { } - assign $1\spr_o[9:0] 10'0000110010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110110 - assign { } { } - assign $1\spr_o[9:0] 10'0000110011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111001 - assign { } { } - assign $1\spr_o[9:0] 10'0000110100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111010 - assign { } { } - assign $1\spr_o[9:0] 10'0000110101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111011 - assign { } { } - assign $1\spr_o[9:0] 10'0000110110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111110 - assign { } { } - assign $1\spr_o[9:0] 10'0000110111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111111 - assign { } { } - assign $1\spr_o[9:0] 10'0000111000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000111001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000111010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000111011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010011 - assign { } { } - assign $1\spr_o[9:0] 10'0000111100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000111101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110111110 - assign { } { } - assign $1\spr_o[9:0] 10'0000111110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000111111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000000 - assign { } { } - assign $1\spr_o[9:0] 10'0001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000001 - assign { } { } - assign $1\spr_o[9:0] 10'0001000001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000010 - assign { } { } - assign $1\spr_o[9:0] 10'0001000010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000011 - assign { } { } - assign $1\spr_o[9:0] 10'0001000011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000100 - assign { } { } - assign $1\spr_o[9:0] 10'0001000100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000101 - assign { } { } - assign $1\spr_o[9:0] 10'0001000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000110 - assign { } { } - assign $1\spr_o[9:0] 10'0001000110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000111 - assign { } { } - assign $1\spr_o[9:0] 10'0001000111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001000 - assign { } { } - assign $1\spr_o[9:0] 10'0001001000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001011 - assign { } { } - assign $1\spr_o[9:0] 10'0001001001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001100 - assign { } { } - assign $1\spr_o[9:0] 10'0001001010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001101 - assign { } { } - assign $1\spr_o[9:0] 10'0001001011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001110 - assign { } { } - assign $1\spr_o[9:0] 10'0001001100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010000 - assign { } { } - assign $1\spr_o[9:0] 10'0001001101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010001 - assign { } { } - assign $1\spr_o[9:0] 10'0001001110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010010 - assign { } { } - assign $1\spr_o[9:0] 10'0001001111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010011 - assign { } { } - assign $1\spr_o[9:0] 10'0001010000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010100 - assign { } { } - assign $1\spr_o[9:0] 10'0001010001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010101 - assign { } { } - assign $1\spr_o[9:0] 10'0001010010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010110 - assign { } { } - assign $1\spr_o[9:0] 10'0001010011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010111 - assign { } { } - assign $1\spr_o[9:0] 10'0001010100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011000 - assign { } { } - assign $1\spr_o[9:0] 10'0001010101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011011 - assign { } { } - assign $1\spr_o[9:0] 10'0001010110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011100 - assign { } { } - assign $1\spr_o[9:0] 10'0001010111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011101 - assign { } { } - assign $1\spr_o[9:0] 10'0001011000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011110 - assign { } { } - assign $1\spr_o[9:0] 10'0001011001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100000 - assign { } { } - assign $1\spr_o[9:0] 10'0001011010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100001 - assign { } { } - assign $1\spr_o[9:0] 10'0001011011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100010 - assign { } { } - assign $1\spr_o[9:0] 10'0001011100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100011 - assign { } { } - assign $1\spr_o[9:0] 10'0001011101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100100 - assign { } { } - assign $1\spr_o[9:0] 10'0001011110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100101 - assign { } { } - assign $1\spr_o[9:0] 10'0001011111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100110 - assign { } { } - assign $1\spr_o[9:0] 10'0001100000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101000 - assign { } { } - assign $1\spr_o[9:0] 10'0001100001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101001 - assign { } { } - assign $1\spr_o[9:0] 10'0001100010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101010 - assign { } { } - assign $1\spr_o[9:0] 10'0001100011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101011 - assign { } { } - assign $1\spr_o[9:0] 10'0001100100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100110000 - assign { } { } - assign $1\spr_o[9:0] 10'0001100110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100110111 - assign { } { } - assign $1\spr_o[9:0] 10'0001100111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010000 - assign { } { } - assign $1\spr_o[9:0] 10'0001101000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010001 - assign { } { } - assign $1\spr_o[9:0] 10'0001101001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010111 - assign { } { } - assign $1\spr_o[9:0] 10'0001101010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1110000000 - assign { } { } - assign $1\spr_o[9:0] 10'0001101011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1110000010 - assign { } { } - assign $1\spr_o[9:0] 10'0001101100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1111111111 - assign { } { } - assign $1\spr_o[9:0] 10'0001101101 - case - assign $1\spr_o[9:0] 10'0000000000 - end - sync always - update \spr_o $0\spr_o[9:0] - end - attribute \src "libresoc.v:46288.3-46600.6" - process $proc$libresoc.v:46288$1441 - assign { } { } - assign { } { } - assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:46289.5-46289.29" - switch \initial - attribute \src "libresoc.v:46289.9-46289.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000111101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010001000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010110100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100001101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110111110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100110111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1110000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1110000010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1111111111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - case - assign $1\spr_o_ok[0:0] 1'0 - end - sync always - update \spr_o_ok $0\spr_o_ok[0:0] - end -end -attribute \src "libresoc.v:46606.1-47121.10" -attribute \cells_not_processed 1 -attribute \top 1 -attribute \nmigen.hierarchy "test_issuer" -attribute \generator "nMigen" -module \test_issuer - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire input 9 \TAP_bus__tck - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire input 7 \TAP_bus__tdi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire output 6 \TAP_bus__tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire input 8 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:92" - wire output 5 \busy_o - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:527" - wire input 166 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:36" - wire width 3 input 164 \clk_sel_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:34" - wire \clksel_clk_24_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:37" - wire \clksel_core_clk_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" - wire \clksel_pllclk_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:38" - wire \clksel_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:91" - wire input 4 \core_bigendian_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 136 \dbus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 input 130 \dbus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 2 input 139 \dbus__bte - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 3 input 138 \dbus__cti - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 134 \dbus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 132 \dbus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 131 \dbus__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 140 \dbus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 input 133 \dbus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 135 \dbus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 137 \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 23 \gpio_gpio0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 24 \gpio_gpio0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 25 \gpio_gpio0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 26 \gpio_gpio0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 27 \gpio_gpio0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 28 \gpio_gpio0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 83 \gpio_gpio10__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 84 \gpio_gpio10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 85 \gpio_gpio10__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 86 \gpio_gpio10__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 87 \gpio_gpio10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 88 \gpio_gpio10__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 89 \gpio_gpio11__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 90 \gpio_gpio11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 91 \gpio_gpio11__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 92 \gpio_gpio11__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 93 \gpio_gpio11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 94 \gpio_gpio11__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 95 \gpio_gpio12__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 96 \gpio_gpio12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 97 \gpio_gpio12__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 98 \gpio_gpio12__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 99 \gpio_gpio12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 100 \gpio_gpio12__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 101 \gpio_gpio13__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 102 \gpio_gpio13__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 103 \gpio_gpio13__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 104 \gpio_gpio13__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 105 \gpio_gpio13__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 106 \gpio_gpio13__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 107 \gpio_gpio14__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 108 \gpio_gpio14__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 109 \gpio_gpio14__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 110 \gpio_gpio14__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 111 \gpio_gpio14__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 112 \gpio_gpio14__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 113 \gpio_gpio15__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 114 \gpio_gpio15__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 115 \gpio_gpio15__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 116 \gpio_gpio15__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 117 \gpio_gpio15__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 118 \gpio_gpio15__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 29 \gpio_gpio1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 30 \gpio_gpio1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 31 \gpio_gpio1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 32 \gpio_gpio1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 33 \gpio_gpio1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 34 \gpio_gpio1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 35 \gpio_gpio2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 36 \gpio_gpio2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 37 \gpio_gpio2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 38 \gpio_gpio2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 39 \gpio_gpio2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 40 \gpio_gpio2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 41 \gpio_gpio3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 42 \gpio_gpio3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 43 \gpio_gpio3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 44 \gpio_gpio3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 45 \gpio_gpio3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 46 \gpio_gpio3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 47 \gpio_gpio4__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 48 \gpio_gpio4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 49 \gpio_gpio4__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 50 \gpio_gpio4__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 51 \gpio_gpio4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 52 \gpio_gpio4__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 53 \gpio_gpio5__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 54 \gpio_gpio5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 55 \gpio_gpio5__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 56 \gpio_gpio5__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 57 \gpio_gpio5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 58 \gpio_gpio5__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 59 \gpio_gpio6__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 60 \gpio_gpio6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 61 \gpio_gpio6__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 62 \gpio_gpio6__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 63 \gpio_gpio6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 64 \gpio_gpio6__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 65 \gpio_gpio7__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 66 \gpio_gpio7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 67 \gpio_gpio7__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 68 \gpio_gpio7__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 69 \gpio_gpio7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 70 \gpio_gpio7__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 71 \gpio_gpio8__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 72 \gpio_gpio8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 73 \gpio_gpio8__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 74 \gpio_gpio8__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 75 \gpio_gpio8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 76 \gpio_gpio8__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 77 \gpio_gpio9__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 78 \gpio_gpio9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 79 \gpio_gpio9__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 80 \gpio_gpio9__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 81 \gpio_gpio9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 82 \gpio_gpio9__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 125 \ibus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 output 119 \ibus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 2 input 128 \ibus__bte - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 3 input 127 \ibus__cti - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 123 \ibus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 121 \ibus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 120 \ibus__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 129 \ibus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 output 122 \ibus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 124 \ibus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 126 \ibus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 147 \icp_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 141 \icp_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 2 input 150 \icp_wb__bte - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 3 input 149 \icp_wb__cti - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 145 \icp_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 143 \icp_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 142 \icp_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 151 \icp_wb__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 144 \icp_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 146 \icp_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 148 \icp_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 158 \ics_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 152 \ics_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 2 input 161 \ics_wb__bte - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 3 input 160 \ics_wb__cti - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 156 \ics_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 154 \ics_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 153 \ics_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 162 \ics_wb__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 4 input 155 \ics_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 157 \ics_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 159 \ics_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 163 \int_level_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:457" - wire \intclk_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire input 17 \jtag_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire width 29 output 10 \jtag_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire output 14 \jtag_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire width 64 input 12 \jtag_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire width 64 output 11 \jtag_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire input 18 \jtag_wb__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire output 13 \jtag_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire output 15 \jtag_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire output 16 \jtag_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:93" - wire input 3 \memerr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 168 \pc_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 1 \pc_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:89" - wire width 64 output 2 \pc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:35" - wire output 165 \pll_48_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:80" - wire \pll_clk_24_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:81" - wire \pll_clk_pll_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:82" - wire \pll_rst - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:527" - wire output 167 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 21 \uart_rx__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 22 \uart_rx__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 19 \uart_tx__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 20 \uart_tx__pad__o - attribute \module_not_derived 1 - attribute \src "libresoc.v:46959.10-46966.4" - cell \clksel \clksel - connect \clk_24_i \clksel_clk_24_i - connect \clk_sel_i \clk_sel_i - connect \core_clk_o \clksel_core_clk_o - connect \pll_48_o \pll_48_o - connect \pllclk_clk \clksel_pllclk_clk - connect \rst \clksel_rst - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:46967.7-46972.4" - cell \pll \pll - connect \clk_24_i \pll_clk_24_i - connect \clk_pll_o \pll_clk_pll_o - connect \rst \pll_rst - connect \rst$1 \rst - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:46973.6-47114.4" - cell \ti \ti - connect \TAP_bus__tck \TAP_bus__tck - connect \TAP_bus__tdi \TAP_bus__tdi - connect \TAP_bus__tdo \TAP_bus__tdo - connect \TAP_bus__tms \TAP_bus__tms - connect \busy_o \busy_o - connect \core_bigendian_i \core_bigendian_i - connect \gpio_gpio0__core__i \gpio_gpio0__core__i - connect \gpio_gpio0__core__o \gpio_gpio0__core__o - connect \gpio_gpio0__core__oe \gpio_gpio0__core__oe - connect \gpio_gpio0__pad__i \gpio_gpio0__pad__i - connect \gpio_gpio0__pad__o \gpio_gpio0__pad__o - connect \gpio_gpio0__pad__oe \gpio_gpio0__pad__oe - connect \gpio_gpio10__core__i \gpio_gpio10__core__i - connect \gpio_gpio10__core__o \gpio_gpio10__core__o - connect \gpio_gpio10__core__oe \gpio_gpio10__core__oe - connect \gpio_gpio10__pad__i \gpio_gpio10__pad__i - connect \gpio_gpio10__pad__o \gpio_gpio10__pad__o - connect \gpio_gpio10__pad__oe \gpio_gpio10__pad__oe - connect \gpio_gpio11__core__i \gpio_gpio11__core__i - connect \gpio_gpio11__core__o \gpio_gpio11__core__o - connect \gpio_gpio11__core__oe \gpio_gpio11__core__oe - connect \gpio_gpio11__pad__i \gpio_gpio11__pad__i - connect \gpio_gpio11__pad__o \gpio_gpio11__pad__o - connect \gpio_gpio11__pad__oe \gpio_gpio11__pad__oe - connect \gpio_gpio12__core__i \gpio_gpio12__core__i - connect \gpio_gpio12__core__o \gpio_gpio12__core__o - connect \gpio_gpio12__core__oe \gpio_gpio12__core__oe - connect \gpio_gpio12__pad__i \gpio_gpio12__pad__i - connect \gpio_gpio12__pad__o \gpio_gpio12__pad__o - connect \gpio_gpio12__pad__oe \gpio_gpio12__pad__oe - connect \gpio_gpio13__core__i \gpio_gpio13__core__i - connect \gpio_gpio13__core__o \gpio_gpio13__core__o - connect \gpio_gpio13__core__oe \gpio_gpio13__core__oe - connect \gpio_gpio13__pad__i \gpio_gpio13__pad__i - connect \gpio_gpio13__pad__o \gpio_gpio13__pad__o - connect \gpio_gpio13__pad__oe \gpio_gpio13__pad__oe - connect \gpio_gpio14__core__i \gpio_gpio14__core__i - connect \gpio_gpio14__core__o \gpio_gpio14__core__o - connect \gpio_gpio14__core__oe \gpio_gpio14__core__oe - connect \gpio_gpio14__pad__i \gpio_gpio14__pad__i - connect \gpio_gpio14__pad__o \gpio_gpio14__pad__o - connect \gpio_gpio14__pad__oe \gpio_gpio14__pad__oe - connect \gpio_gpio15__core__i \gpio_gpio15__core__i - connect \gpio_gpio15__core__o \gpio_gpio15__core__o - connect \gpio_gpio15__core__oe \gpio_gpio15__core__oe - connect \gpio_gpio15__pad__i \gpio_gpio15__pad__i - connect \gpio_gpio15__pad__o \gpio_gpio15__pad__o - connect \gpio_gpio15__pad__oe \gpio_gpio15__pad__oe - connect \gpio_gpio1__core__i \gpio_gpio1__core__i - connect \gpio_gpio1__core__o \gpio_gpio1__core__o - connect \gpio_gpio1__core__oe \gpio_gpio1__core__oe - connect \gpio_gpio1__pad__i \gpio_gpio1__pad__i - connect \gpio_gpio1__pad__o \gpio_gpio1__pad__o - connect \gpio_gpio1__pad__oe \gpio_gpio1__pad__oe - connect \gpio_gpio2__core__i \gpio_gpio2__core__i - connect \gpio_gpio2__core__o \gpio_gpio2__core__o - connect \gpio_gpio2__core__oe \gpio_gpio2__core__oe - connect \gpio_gpio2__pad__i \gpio_gpio2__pad__i - connect \gpio_gpio2__pad__o \gpio_gpio2__pad__o - connect \gpio_gpio2__pad__oe \gpio_gpio2__pad__oe - connect \gpio_gpio3__core__i \gpio_gpio3__core__i - connect \gpio_gpio3__core__o \gpio_gpio3__core__o - connect \gpio_gpio3__core__oe \gpio_gpio3__core__oe - connect \gpio_gpio3__pad__i \gpio_gpio3__pad__i - connect \gpio_gpio3__pad__o \gpio_gpio3__pad__o - connect \gpio_gpio3__pad__oe \gpio_gpio3__pad__oe - connect \gpio_gpio4__core__i \gpio_gpio4__core__i - connect \gpio_gpio4__core__o \gpio_gpio4__core__o - connect \gpio_gpio4__core__oe \gpio_gpio4__core__oe - connect \gpio_gpio4__pad__i \gpio_gpio4__pad__i - connect \gpio_gpio4__pad__o \gpio_gpio4__pad__o - connect \gpio_gpio4__pad__oe \gpio_gpio4__pad__oe - connect \gpio_gpio5__core__i \gpio_gpio5__core__i - connect \gpio_gpio5__core__o \gpio_gpio5__core__o - connect \gpio_gpio5__core__oe \gpio_gpio5__core__oe - connect \gpio_gpio5__pad__i \gpio_gpio5__pad__i - connect \gpio_gpio5__pad__o \gpio_gpio5__pad__o - connect \gpio_gpio5__pad__oe \gpio_gpio5__pad__oe - connect \gpio_gpio6__core__i \gpio_gpio6__core__i - connect \gpio_gpio6__core__o \gpio_gpio6__core__o - connect \gpio_gpio6__core__oe \gpio_gpio6__core__oe - connect \gpio_gpio6__pad__i \gpio_gpio6__pad__i - connect \gpio_gpio6__pad__o \gpio_gpio6__pad__o - connect \gpio_gpio6__pad__oe \gpio_gpio6__pad__oe - connect \gpio_gpio7__core__i \gpio_gpio7__core__i - connect \gpio_gpio7__core__o \gpio_gpio7__core__o - connect \gpio_gpio7__core__oe \gpio_gpio7__core__oe - connect \gpio_gpio7__pad__i \gpio_gpio7__pad__i - connect \gpio_gpio7__pad__o \gpio_gpio7__pad__o - connect \gpio_gpio7__pad__oe \gpio_gpio7__pad__oe - connect \gpio_gpio8__core__i \gpio_gpio8__core__i - connect \gpio_gpio8__core__o \gpio_gpio8__core__o - connect \gpio_gpio8__core__oe \gpio_gpio8__core__oe - connect \gpio_gpio8__pad__i \gpio_gpio8__pad__i - connect \gpio_gpio8__pad__o \gpio_gpio8__pad__o - connect \gpio_gpio8__pad__oe \gpio_gpio8__pad__oe - connect \gpio_gpio9__core__i \gpio_gpio9__core__i - connect \gpio_gpio9__core__o \gpio_gpio9__core__o - connect \gpio_gpio9__core__oe \gpio_gpio9__core__oe - connect \gpio_gpio9__pad__i \gpio_gpio9__pad__i - connect \gpio_gpio9__pad__o \gpio_gpio9__pad__o - connect \gpio_gpio9__pad__oe \gpio_gpio9__pad__oe - connect \ibus__ack \ibus__ack - connect \ibus__adr \ibus__adr - connect \ibus__cyc \ibus__cyc - connect \ibus__dat_r \ibus__dat_r - connect \ibus__err \ibus__err - connect \ibus__sel \ibus__sel - connect \ibus__stb \ibus__stb - connect \icp_wb__ack \icp_wb__ack - connect \icp_wb__adr \icp_wb__adr - connect \icp_wb__cyc \icp_wb__cyc - connect \icp_wb__dat_r \icp_wb__dat_r - connect \icp_wb__dat_w \icp_wb__dat_w - connect \icp_wb__sel \icp_wb__sel - connect \icp_wb__stb \icp_wb__stb - connect \icp_wb__we \icp_wb__we - connect \ics_wb__ack \ics_wb__ack - connect \ics_wb__adr \ics_wb__adr - connect \ics_wb__cyc \ics_wb__cyc - connect \ics_wb__dat_r \ics_wb__dat_r - connect \ics_wb__dat_w \ics_wb__dat_w - connect \ics_wb__stb \ics_wb__stb - connect \ics_wb__we \ics_wb__we - connect \int_level_i \int_level_i - connect \jtag_wb__ack \jtag_wb__ack - connect \jtag_wb__adr \jtag_wb__adr - connect \jtag_wb__cyc \jtag_wb__cyc - connect \jtag_wb__dat_r \jtag_wb__dat_r - connect \jtag_wb__dat_w \jtag_wb__dat_w - connect \jtag_wb__sel \jtag_wb__sel - connect \jtag_wb__stb \jtag_wb__stb - connect \jtag_wb__we \jtag_wb__we - connect \pc_i \pc_i - connect \pc_i_ok \pc_i_ok - connect \pc_o \pc_o - connect \uart_rx__core__i \uart_rx__core__i - connect \uart_rx__pad__i \uart_rx__pad__i - connect \uart_tx__core__o \uart_tx__core__o - connect \uart_tx__pad__o \uart_tx__pad__o - end - connect \clksel_rst \rst - connect \pll_rst \rst - connect \pll_clk_24_i \clksel_clk_24_i - connect \clksel_clk_24_i \clk - connect \clksel_pllclk_clk \pll_clk_pll_o - connect \intclk_clk \clksel_core_clk_o -end -attribute \src "libresoc.v:47125.1-50180.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti" -attribute \generator "nMigen" -module \ti - attribute \src "libresoc.v:49784.3-49820.6" - wire $0\bigendian_i$next[0:0]$1884 - attribute \src "libresoc.v:48789.3-48790.39" - wire $0\bigendian_i[0:0] - attribute \src "libresoc.v:49508.3-49520.6" - wire width 4 $0\cia__ren[3:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 8 $0\core_asmcode$next[7:0]$1645 - attribute \src "libresoc.v:48793.3-48794.41" - wire width 8 $0\core_asmcode[7:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 64 $0\core_core_cia$next[63:0]$1646 - attribute \src "libresoc.v:48861.3-48862.43" - wire width 64 $0\core_core_cia[63:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 8 $0\core_core_cr_rd$next[7:0]$1647 - attribute \src "libresoc.v:48887.3-48888.47" - wire width 8 $0\core_core_cr_rd[7:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_core_cr_rd_ok$next[0:0]$1648 - attribute \src "libresoc.v:48889.3-48890.53" - wire $0\core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 8 $0\core_core_cr_wr$next[7:0]$1649 - attribute \src "libresoc.v:48893.3-48894.47" - wire width 8 $0\core_core_cr_wr[7:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_core_cr_wr_ok$next[0:0]$1650 - attribute \src "libresoc.v:48895.3-48896.53" - wire $0\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 12 $0\core_core_fn_unit$next[11:0]$1651 - attribute \src "libresoc.v:48867.3-48868.51" - wire width 12 $0\core_core_fn_unit[11:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 2 $0\core_core_input_carry$next[1:0]$1652 - attribute \src "libresoc.v:48881.3-48882.59" - wire width 2 $0\core_core_input_carry[1:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 32 $0\core_core_insn$next[31:0]$1653 - attribute \src "libresoc.v:48863.3-48864.45" - wire width 32 $0\core_core_insn[31:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 7 $0\core_core_insn_type$next[6:0]$1654 - attribute \src "libresoc.v:48865.3-48866.55" - wire width 7 $0\core_core_insn_type[6:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_core_is_32bit$next[0:0]$1655 - attribute \src "libresoc.v:48897.3-48898.53" - wire $0\core_core_is_32bit[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_core_lk$next[0:0]$1656 - attribute \src "libresoc.v:48871.3-48872.41" - wire $0\core_core_lk[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 64 $0\core_core_msr$next[63:0]$1657 - attribute \src "libresoc.v:48859.3-48860.43" - wire width 64 $0\core_core_msr[63:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_core_oe$next[0:0]$1658 - attribute \src "libresoc.v:48877.3-48878.41" - wire $0\core_core_oe[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_core_oe_ok$next[0:0]$1659 - attribute \src "libresoc.v:48879.3-48880.47" - wire $0\core_core_oe_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_core_rc$next[0:0]$1660 - attribute \src "libresoc.v:48873.3-48874.41" - wire $0\core_core_rc[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_core_rc_ok$next[0:0]$1661 - attribute \src "libresoc.v:48875.3-48876.47" - wire $0\core_core_rc_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 13 $0\core_core_trapaddr$next[12:0]$1662 - attribute \src "libresoc.v:48885.3-48886.53" - wire width 13 $0\core_core_trapaddr[12:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 7 $0\core_core_traptype$next[6:0]$1663 - attribute \src "libresoc.v:48883.3-48884.53" - wire width 7 $0\core_core_traptype[6:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $0\core_cr_in1$next[2:0]$1664 - attribute \src "libresoc.v:48843.3-48844.39" - wire width 3 $0\core_cr_in1[2:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_cr_in1_ok$next[0:0]$1665 - attribute \src "libresoc.v:48845.3-48846.45" - wire $0\core_cr_in1_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $0\core_cr_in2$39$next[2:0]$1666 - attribute \src "libresoc.v:48851.3-48852.47" - wire width 3 $0\core_cr_in2$39[2:0]$1543 - attribute \src "libresoc.v:47445.13-47445.36" - wire width 3 $0\core_cr_in2$39[2:0]$1969 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $0\core_cr_in2$next[2:0]$1667 - attribute \src "libresoc.v:48847.3-48848.39" - wire width 3 $0\core_cr_in2[2:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_cr_in2_ok$40$next[0:0]$1668 - attribute \src "libresoc.v:48853.3-48854.53" - wire $0\core_cr_in2_ok$40[0:0]$1545 - attribute \src "libresoc.v:47453.7-47453.33" - wire $0\core_cr_in2_ok$40[0:0]$1972 - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_cr_in2_ok$next[0:0]$1669 - attribute \src "libresoc.v:48849.3-48850.45" - wire $0\core_cr_in2_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $0\core_cr_out$next[2:0]$1670 - attribute \src "libresoc.v:48855.3-48856.39" - wire width 3 $0\core_cr_out[2:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_cr_out_ok$next[0:0]$1671 - attribute \src "libresoc.v:48857.3-48858.45" - wire $0\core_cr_out_ok[0:0] - attribute \src "libresoc.v:50072.3-50103.6" - wire width 64 $0\core_dec$next[63:0]$1922 - attribute \src "libresoc.v:48779.3-48780.33" - wire width 64 $0\core_dec[63:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 5 $0\core_ea$next[4:0]$1672 - attribute \src "libresoc.v:48799.3-48800.31" - wire width 5 $0\core_ea[4:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_ea_ok$next[0:0]$1673 - attribute \src "libresoc.v:48801.3-48802.37" - wire $0\core_ea_ok[0:0] - attribute \src "libresoc.v:50072.3-50103.6" - wire $0\core_eint$next[0:0]$1923 - attribute \src "libresoc.v:48777.3-48778.35" - wire $0\core_eint[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $0\core_fast1$next[2:0]$1674 - attribute \src "libresoc.v:48827.3-48828.37" - wire width 3 $0\core_fast1[2:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_fast1_ok$next[0:0]$1675 - attribute \src "libresoc.v:48829.3-48830.43" - wire $0\core_fast1_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $0\core_fast2$next[2:0]$1676 - attribute \src "libresoc.v:48831.3-48832.37" - wire width 3 $0\core_fast2[2:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_fast2_ok$next[0:0]$1677 - attribute \src "libresoc.v:48833.3-48834.43" - wire $0\core_fast2_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $0\core_fasto1$next[2:0]$1678 - attribute \src "libresoc.v:48835.3-48836.39" - wire width 3 $0\core_fasto1[2:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_fasto1_ok$next[0:0]$1679 - attribute \src "libresoc.v:48837.3-48838.45" - wire $0\core_fasto1_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $0\core_fasto2$next[2:0]$1680 - attribute \src "libresoc.v:48839.3-48840.39" - wire width 3 $0\core_fasto2[2:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_fasto2_ok$next[0:0]$1681 - attribute \src "libresoc.v:48841.3-48842.45" - wire $0\core_fasto2_ok[0:0] - attribute \src "libresoc.v:50072.3-50103.6" - wire width 64 $0\core_msr$next[63:0]$1924 - attribute \src "libresoc.v:48775.3-48776.33" - wire width 64 $0\core_msr[63:0] - attribute \src "libresoc.v:50072.3-50103.6" - wire width 64 $0\core_pc$next[63:0]$1925 - attribute \src "libresoc.v:48773.3-48774.31" - wire width 64 $0\core_pc[63:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 5 $0\core_reg1$next[4:0]$1682 - attribute \src "libresoc.v:48803.3-48804.35" - wire width 5 $0\core_reg1[4:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_reg1_ok$next[0:0]$1683 - attribute \src "libresoc.v:48805.3-48806.41" - wire $0\core_reg1_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 5 $0\core_reg2$next[4:0]$1684 - attribute \src "libresoc.v:48807.3-48808.35" - wire width 5 $0\core_reg2[4:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_reg2_ok$next[0:0]$1685 - attribute \src "libresoc.v:48809.3-48810.41" - wire $0\core_reg2_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 5 $0\core_reg3$next[4:0]$1686 - attribute \src "libresoc.v:48811.3-48812.35" - wire width 5 $0\core_reg3[4:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_reg3_ok$next[0:0]$1687 - attribute \src "libresoc.v:48813.3-48814.41" - wire $0\core_reg3_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 5 $0\core_rego$next[4:0]$1688 - attribute \src "libresoc.v:48795.3-48796.35" - wire width 5 $0\core_rego[4:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_rego_ok$next[0:0]$1689 - attribute \src "libresoc.v:48797.3-48798.41" - wire $0\core_rego_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 10 $0\core_spr1$next[9:0]$1690 - attribute \src "libresoc.v:48819.3-48820.35" - wire width 10 $0\core_spr1[9:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_spr1_ok$next[0:0]$1691 - attribute \src "libresoc.v:48821.3-48822.41" - wire $0\core_spr1_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 10 $0\core_spro$next[9:0]$1692 - attribute \src "libresoc.v:48815.3-48816.35" - wire width 10 $0\core_spro[9:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_spro_ok$next[0:0]$1693 - attribute \src "libresoc.v:48817.3-48818.41" - wire $0\core_spro_ok[0:0] - attribute \src "libresoc.v:49994.3-50012.6" - wire $0\core_stopped_i[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $0\core_xer_in$next[2:0]$1694 - attribute \src "libresoc.v:48823.3-48824.39" - wire width 3 $0\core_xer_in[2:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $0\core_xer_out$next[0:0]$1695 - attribute \src "libresoc.v:48825.3-48826.41" - wire $0\core_xer_out[0:0] - attribute \src "libresoc.v:48903.3-48904.30" - wire $0\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:49265.3-49273.6" - wire $0\d_cr_delay$next[0:0]$1598 - attribute \src "libresoc.v:48923.3-48924.37" - wire $0\d_cr_delay[0:0] - attribute \src "libresoc.v:49226.3-49234.6" - wire $0\d_reg_delay$next[0:0]$1592 - attribute \src "libresoc.v:48769.3-48770.39" - wire $0\d_reg_delay[0:0] - attribute \src "libresoc.v:49304.3-49312.6" - wire $0\d_xer_delay$next[0:0]$1604 - attribute \src "libresoc.v:48913.3-48914.39" - wire $0\d_xer_delay[0:0] - attribute \src "libresoc.v:49542.3-49562.6" - wire width 64 $0\data_i[63:0] - attribute \src "libresoc.v:50013.3-50031.6" - wire $0\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:49284.3-49293.6" - wire $0\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:49274.3-49283.6" - wire width 64 $0\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:49245.3-49254.6" - wire $0\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:49235.3-49244.6" - wire width 64 $0\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:49323.3-49332.6" - wire $0\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:49313.3-49322.6" - wire width 64 $0\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:49177.3-49185.6" - wire width 4 $0\dbg_dmi_addr_i$next[3:0]$1583 - attribute \src "libresoc.v:48921.3-48922.45" - wire width 4 $0\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:49579.3-49587.6" - wire width 64 $0\dbg_dmi_din$next[63:0]$1637 - attribute \src "libresoc.v:48915.3-48916.39" - wire width 64 $0\dbg_dmi_din[63:0] - attribute \src "libresoc.v:49186.3-49194.6" - wire $0\dbg_dmi_req_i$next[0:0]$1586 - attribute \src "libresoc.v:48919.3-48920.43" - wire $0\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:49474.3-49482.6" - wire $0\dbg_dmi_we_i$next[0:0]$1626 - attribute \src "libresoc.v:48917.3-48918.41" - wire $0\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:49447.3-49462.6" - wire width 64 $0\dec2_cur_dec$next[63:0]$1621 - attribute \src "libresoc.v:48869.3-48870.41" - wire width 64 $0\dec2_cur_dec[63:0] - attribute \src "libresoc.v:49738.3-49746.6" - wire $0\dec2_cur_eint$next[0:0]$1875 - attribute \src "libresoc.v:48907.3-48908.43" - wire $0\dec2_cur_eint[0:0] - attribute \src "libresoc.v:50032.3-50052.6" - wire width 64 $0\dec2_cur_msr$next[63:0]$1916 - attribute \src "libresoc.v:48781.3-48782.41" - wire width 64 $0\dec2_cur_msr[63:0] - attribute \src "libresoc.v:49887.3-49907.6" - wire width 64 $0\dec2_cur_pc$next[63:0]$1893 - attribute \src "libresoc.v:48787.3-48788.39" - wire width 64 $0\dec2_cur_pc[63:0] - attribute \src "libresoc.v:50053.3-50071.6" - wire width 32 $0\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:49984.3-49993.6" - wire width 2 $0\delay$next[1:0]$1911 - attribute \src "libresoc.v:48905.3-48906.27" - wire width 2 $0\delay[1:0] - attribute \src "libresoc.v:49206.3-49215.6" - wire width 5 $0\dmi__addr[4:0] - attribute \src "libresoc.v:49216.3-49225.6" - wire $0\dmi__ren[0:0] - attribute \src "libresoc.v:49363.3-49390.6" - wire width 2 $0\fsm_state$115$next[1:0]$1611 - attribute \src "libresoc.v:48891.3-48892.45" - wire width 2 $0\fsm_state$115[1:0]$1565 - attribute \src "libresoc.v:48338.13-48338.35" - wire width 2 $0\fsm_state$115[1:0]$2018 - attribute \src "libresoc.v:49938.3-49983.6" - wire width 2 $0\fsm_state$next[1:0]$1904 - attribute \src "libresoc.v:48783.3-48784.35" - wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:49255.3-49264.6" - wire width 8 $0\full_rd2__ren[7:0] - attribute \src "libresoc.v:49294.3-49303.6" - wire width 3 $0\full_rd__ren[2:0] - attribute \src "libresoc.v:50104.3-50127.6" - wire width 32 $0\ilatch$next[31:0]$1939 - attribute \src "libresoc.v:48771.3-48772.29" - wire width 32 $0\ilatch[31:0] - attribute \src "libresoc.v:49821.3-49836.6" - wire width 48 $0\imem_a_pc_i[47:0] - attribute \src "libresoc.v:49837.3-49861.6" - wire $0\imem_a_valid_i[0:0] - attribute \src "libresoc.v:49862.3-49886.6" - wire $0\imem_f_valid_i[0:0] - attribute \src "libresoc.v:47126.7-47126.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:49402.3-49416.6" - wire width 3 $0\issue__addr$119[2:0]$1616 - attribute \src "libresoc.v:49333.3-49347.6" - wire width 3 $0\issue__addr[2:0] - attribute \src "libresoc.v:49432.3-49446.6" - wire width 64 $0\issue__data_i[63:0] - attribute \src "libresoc.v:49348.3-49362.6" - wire $0\issue__ren[0:0] - attribute \src "libresoc.v:49417.3-49431.6" - wire $0\issue__wen[0:0] - attribute \src "libresoc.v:49195.3-49205.6" - wire $0\issue_i[0:0] - attribute \src "libresoc.v:50128.3-50147.6" - wire $0\ivalid_i[0:0] - attribute \src "libresoc.v:49720.3-49728.6" - wire $0\jtag_dmi0_ack_o$next[0:0]$1869 - attribute \src "libresoc.v:48911.3-48912.47" - wire $0\jtag_dmi0_ack_o[0:0] - attribute \src "libresoc.v:49729.3-49737.6" - wire width 64 $0\jtag_dmi0_dout$next[63:0]$1872 - attribute \src "libresoc.v:48909.3-48910.45" - wire width 64 $0\jtag_dmi0_dout[63:0] - attribute \src "libresoc.v:49563.3-49578.6" - wire width 4 $0\msr__ren[3:0] - attribute \src "libresoc.v:49908.3-49937.6" - wire $0\msr_read$next[0:0]$1898 - attribute \src "libresoc.v:48785.3-48786.33" - wire $0\msr_read[0:0] - attribute \src "libresoc.v:49391.3-49401.6" - wire width 64 $0\new_dec[63:0] - attribute \src "libresoc.v:49463.3-49473.6" - wire width 64 $0\new_tb[63:0] - attribute \src "libresoc.v:49492.3-49507.6" - wire width 64 $0\pc[63:0] - attribute \src "libresoc.v:49588.3-49612.6" - wire $0\pc_changed$next[0:0]$1640 - attribute \src "libresoc.v:48899.3-48900.37" - wire $0\pc_changed[0:0] - attribute \src "libresoc.v:49483.3-49491.6" - wire $0\pc_ok_delay$next[0:0]$1629 - attribute \src "libresoc.v:48901.3-48902.39" - wire $0\pc_ok_delay[0:0] - attribute \src "libresoc.v:49747.3-49783.6" - wire width 32 $0\raw_insn_i$next[31:0]$1878 - attribute \src "libresoc.v:48791.3-48792.37" - wire width 32 $0\raw_insn_i[31:0] - attribute \src "libresoc.v:49521.3-49541.6" - wire width 4 $0\wen[3:0] - attribute \src "libresoc.v:49784.3-49820.6" - wire $1\bigendian_i$next[0:0]$1885 - attribute \src "libresoc.v:47256.7-47256.25" - wire $1\bigendian_i[0:0] - attribute \src "libresoc.v:49508.3-49520.6" - wire width 4 $1\cia__ren[3:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 8 $1\core_asmcode$next[7:0]$1696 - attribute \src "libresoc.v:47266.13-47266.33" - wire width 8 $1\core_asmcode[7:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 64 $1\core_core_cia$next[63:0]$1697 - attribute \src "libresoc.v:47272.14-47272.50" - wire width 64 $1\core_core_cia[63:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 8 $1\core_core_cr_rd$next[7:0]$1698 - attribute \src "libresoc.v:47276.13-47276.36" - wire width 8 $1\core_core_cr_rd[7:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_core_cr_rd_ok$next[0:0]$1699 - attribute \src "libresoc.v:47280.7-47280.32" - wire $1\core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 8 $1\core_core_cr_wr$next[7:0]$1700 - attribute \src "libresoc.v:47284.13-47284.36" - wire width 8 $1\core_core_cr_wr[7:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_core_cr_wr_ok$next[0:0]$1701 - attribute \src "libresoc.v:47288.7-47288.32" - wire $1\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 12 $1\core_core_fn_unit$next[11:0]$1702 - attribute \src "libresoc.v:47305.14-47305.41" - wire width 12 $1\core_core_fn_unit[11:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 2 $1\core_core_input_carry$next[1:0]$1703 - attribute \src "libresoc.v:47313.13-47313.41" - wire width 2 $1\core_core_input_carry[1:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 32 $1\core_core_insn$next[31:0]$1704 - attribute \src "libresoc.v:47317.14-47317.36" - wire width 32 $1\core_core_insn[31:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 7 $1\core_core_insn_type$next[6:0]$1705 - attribute \src "libresoc.v:47395.13-47395.40" - wire width 7 $1\core_core_insn_type[6:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_core_is_32bit$next[0:0]$1706 - attribute \src "libresoc.v:47399.7-47399.32" - wire $1\core_core_is_32bit[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_core_lk$next[0:0]$1707 - attribute \src "libresoc.v:47403.7-47403.26" - wire $1\core_core_lk[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 64 $1\core_core_msr$next[63:0]$1708 - attribute \src "libresoc.v:47407.14-47407.50" - wire width 64 $1\core_core_msr[63:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_core_oe$next[0:0]$1709 - attribute \src "libresoc.v:47411.7-47411.26" - wire $1\core_core_oe[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_core_oe_ok$next[0:0]$1710 - attribute \src "libresoc.v:47415.7-47415.29" - wire $1\core_core_oe_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_core_rc$next[0:0]$1711 - attribute \src "libresoc.v:47419.7-47419.26" - wire $1\core_core_rc[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_core_rc_ok$next[0:0]$1712 - attribute \src "libresoc.v:47423.7-47423.29" - wire $1\core_core_rc_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 13 $1\core_core_trapaddr$next[12:0]$1713 - attribute \src "libresoc.v:47427.14-47427.43" - wire width 13 $1\core_core_trapaddr[12:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 7 $1\core_core_traptype$next[6:0]$1714 - attribute \src "libresoc.v:47431.13-47431.39" - wire width 7 $1\core_core_traptype[6:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $1\core_cr_in1$next[2:0]$1715 - attribute \src "libresoc.v:47435.13-47435.31" - wire width 3 $1\core_cr_in1[2:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_cr_in1_ok$next[0:0]$1716 - attribute \src "libresoc.v:47439.7-47439.28" - wire $1\core_cr_in1_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $1\core_cr_in2$39$next[2:0]$1717 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $1\core_cr_in2$next[2:0]$1718 - attribute \src "libresoc.v:47443.13-47443.31" - wire width 3 $1\core_cr_in2[2:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_cr_in2_ok$40$next[0:0]$1719 - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_cr_in2_ok$next[0:0]$1720 - attribute \src "libresoc.v:47451.7-47451.28" - wire $1\core_cr_in2_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $1\core_cr_out$next[2:0]$1721 - attribute \src "libresoc.v:47459.13-47459.31" - wire width 3 $1\core_cr_out[2:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_cr_out_ok$next[0:0]$1722 - attribute \src "libresoc.v:47463.7-47463.28" - wire $1\core_cr_out_ok[0:0] - attribute \src "libresoc.v:50072.3-50103.6" - wire width 64 $1\core_dec$next[63:0]$1926 - attribute \src "libresoc.v:47467.14-47467.45" - wire width 64 $1\core_dec[63:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 5 $1\core_ea$next[4:0]$1723 - attribute \src "libresoc.v:47471.13-47471.28" - wire width 5 $1\core_ea[4:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_ea_ok$next[0:0]$1724 - attribute \src "libresoc.v:47475.7-47475.24" - wire $1\core_ea_ok[0:0] - attribute \src "libresoc.v:50072.3-50103.6" - wire $1\core_eint$next[0:0]$1927 - attribute \src "libresoc.v:47479.7-47479.23" - wire $1\core_eint[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $1\core_fast1$next[2:0]$1725 - attribute \src "libresoc.v:47483.13-47483.30" - wire width 3 $1\core_fast1[2:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_fast1_ok$next[0:0]$1726 - attribute \src "libresoc.v:47487.7-47487.27" - wire $1\core_fast1_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $1\core_fast2$next[2:0]$1727 - attribute \src "libresoc.v:47491.13-47491.30" - wire width 3 $1\core_fast2[2:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_fast2_ok$next[0:0]$1728 - attribute \src "libresoc.v:47495.7-47495.27" - wire $1\core_fast2_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $1\core_fasto1$next[2:0]$1729 - attribute \src "libresoc.v:47499.13-47499.31" - wire width 3 $1\core_fasto1[2:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_fasto1_ok$next[0:0]$1730 - attribute \src "libresoc.v:47503.7-47503.28" - wire $1\core_fasto1_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $1\core_fasto2$next[2:0]$1731 - attribute \src "libresoc.v:47507.13-47507.31" - wire width 3 $1\core_fasto2[2:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_fasto2_ok$next[0:0]$1732 - attribute \src "libresoc.v:47511.7-47511.28" - wire $1\core_fasto2_ok[0:0] - attribute \src "libresoc.v:50072.3-50103.6" - wire width 64 $1\core_msr$next[63:0]$1928 - attribute \src "libresoc.v:47515.14-47515.45" - wire width 64 $1\core_msr[63:0] - attribute \src "libresoc.v:50072.3-50103.6" - wire width 64 $1\core_pc$next[63:0]$1929 - attribute \src "libresoc.v:47519.14-47519.44" - wire width 64 $1\core_pc[63:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 5 $1\core_reg1$next[4:0]$1733 - attribute \src "libresoc.v:47523.13-47523.30" - wire width 5 $1\core_reg1[4:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_reg1_ok$next[0:0]$1734 - attribute \src "libresoc.v:47527.7-47527.26" - wire $1\core_reg1_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 5 $1\core_reg2$next[4:0]$1735 - attribute \src "libresoc.v:47531.13-47531.30" - wire width 5 $1\core_reg2[4:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_reg2_ok$next[0:0]$1736 - attribute \src "libresoc.v:47535.7-47535.26" - wire $1\core_reg2_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 5 $1\core_reg3$next[4:0]$1737 - attribute \src "libresoc.v:47539.13-47539.30" - wire width 5 $1\core_reg3[4:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_reg3_ok$next[0:0]$1738 - attribute \src "libresoc.v:47543.7-47543.26" - wire $1\core_reg3_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 5 $1\core_rego$next[4:0]$1739 - attribute \src "libresoc.v:47547.13-47547.30" - wire width 5 $1\core_rego[4:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_rego_ok$next[0:0]$1740 - attribute \src "libresoc.v:47551.7-47551.26" - wire $1\core_rego_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 10 $1\core_spr1$next[9:0]$1741 - attribute \src "libresoc.v:47668.13-47668.32" - wire width 10 $1\core_spr1[9:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_spr1_ok$next[0:0]$1742 - attribute \src "libresoc.v:47672.7-47672.26" - wire $1\core_spr1_ok[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 10 $1\core_spro$next[9:0]$1743 - attribute \src "libresoc.v:47787.13-47787.32" - wire width 10 $1\core_spro[9:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_spro_ok$next[0:0]$1744 - attribute \src "libresoc.v:47791.7-47791.26" - wire $1\core_spro_ok[0:0] - attribute \src "libresoc.v:49994.3-50012.6" - wire $1\core_stopped_i[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $1\core_xer_in$next[2:0]$1745 - attribute \src "libresoc.v:47799.13-47799.31" - wire width 3 $1\core_xer_in[2:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire $1\core_xer_out$next[0:0]$1746 - attribute \src "libresoc.v:47803.7-47803.26" - wire $1\core_xer_out[0:0] - attribute \src "libresoc.v:47819.7-47819.30" - wire $1\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:49265.3-49273.6" - wire $1\d_cr_delay$next[0:0]$1599 - attribute \src "libresoc.v:47825.7-47825.24" - wire $1\d_cr_delay[0:0] - attribute \src "libresoc.v:49226.3-49234.6" - wire $1\d_reg_delay$next[0:0]$1593 - attribute \src "libresoc.v:47829.7-47829.25" - wire $1\d_reg_delay[0:0] - attribute \src "libresoc.v:49304.3-49312.6" - wire $1\d_xer_delay$next[0:0]$1605 - attribute \src "libresoc.v:47833.7-47833.25" - wire $1\d_xer_delay[0:0] - attribute \src "libresoc.v:49542.3-49562.6" - wire width 64 $1\data_i[63:0] - attribute \src "libresoc.v:50013.3-50031.6" - wire $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:49284.3-49293.6" - wire $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:49274.3-49283.6" - wire width 64 $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:49245.3-49254.6" - wire $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:49235.3-49244.6" - wire width 64 $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:49323.3-49332.6" - wire $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:49313.3-49322.6" - wire width 64 $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:49177.3-49185.6" - wire width 4 $1\dbg_dmi_addr_i$next[3:0]$1584 - attribute \src "libresoc.v:47871.13-47871.34" - wire width 4 $1\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:49579.3-49587.6" - wire width 64 $1\dbg_dmi_din$next[63:0]$1638 - attribute \src "libresoc.v:47875.14-47875.48" - wire width 64 $1\dbg_dmi_din[63:0] - attribute \src "libresoc.v:49186.3-49194.6" - wire $1\dbg_dmi_req_i$next[0:0]$1587 - attribute \src "libresoc.v:47881.7-47881.27" - wire $1\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:49474.3-49482.6" - wire $1\dbg_dmi_we_i$next[0:0]$1627 - attribute \src "libresoc.v:47885.7-47885.26" - wire $1\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:49447.3-49462.6" - wire width 64 $1\dec2_cur_dec$next[63:0]$1622 - attribute \src "libresoc.v:47921.14-47921.49" - wire width 64 $1\dec2_cur_dec[63:0] - attribute \src "libresoc.v:49738.3-49746.6" - wire $1\dec2_cur_eint$next[0:0]$1876 - attribute \src "libresoc.v:47925.7-47925.27" - wire $1\dec2_cur_eint[0:0] - attribute \src "libresoc.v:50032.3-50052.6" - wire width 64 $1\dec2_cur_msr$next[63:0]$1917 - attribute \src "libresoc.v:47929.14-47929.49" - wire width 64 $1\dec2_cur_msr[63:0] - attribute \src "libresoc.v:49887.3-49907.6" - wire width 64 $1\dec2_cur_pc$next[63:0]$1894 - attribute \src "libresoc.v:47933.14-47933.48" - wire width 64 $1\dec2_cur_pc[63:0] - attribute \src "libresoc.v:50053.3-50071.6" - wire width 32 $1\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:49984.3-49993.6" - wire width 2 $1\delay$next[1:0]$1912 - attribute \src "libresoc.v:48326.13-48326.25" - wire width 2 $1\delay[1:0] - attribute \src "libresoc.v:49206.3-49215.6" - wire width 5 $1\dmi__addr[4:0] - attribute \src "libresoc.v:49216.3-49225.6" - wire $1\dmi__ren[0:0] - attribute \src "libresoc.v:49363.3-49390.6" - wire width 2 $1\fsm_state$115$next[1:0]$1612 - attribute \src "libresoc.v:49938.3-49983.6" - wire width 2 $1\fsm_state$next[1:0]$1905 - attribute \src "libresoc.v:48336.13-48336.29" - wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:49255.3-49264.6" - wire width 8 $1\full_rd2__ren[7:0] - attribute \src "libresoc.v:49294.3-49303.6" - wire width 3 $1\full_rd__ren[2:0] - attribute \src "libresoc.v:50104.3-50127.6" - wire width 32 $1\ilatch$next[31:0]$1940 - attribute \src "libresoc.v:48588.14-48588.28" - wire width 32 $1\ilatch[31:0] - attribute \src "libresoc.v:49821.3-49836.6" - wire width 48 $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:49837.3-49861.6" - wire $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:49862.3-49886.6" - wire $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:49402.3-49416.6" - wire width 3 $1\issue__addr$119[2:0]$1617 - attribute \src "libresoc.v:49333.3-49347.6" - wire width 3 $1\issue__addr[2:0] - attribute \src "libresoc.v:49432.3-49446.6" - wire width 64 $1\issue__data_i[63:0] - attribute \src "libresoc.v:49348.3-49362.6" - wire $1\issue__ren[0:0] - attribute \src "libresoc.v:49417.3-49431.6" - wire $1\issue__wen[0:0] - attribute \src "libresoc.v:49195.3-49205.6" - wire $1\issue_i[0:0] - attribute \src "libresoc.v:50128.3-50147.6" - wire $1\ivalid_i[0:0] - attribute \src "libresoc.v:49720.3-49728.6" - wire $1\jtag_dmi0_ack_o$next[0:0]$1870 - attribute \src "libresoc.v:48624.7-48624.29" - wire $1\jtag_dmi0_ack_o[0:0] - attribute \src "libresoc.v:49729.3-49737.6" - wire width 64 $1\jtag_dmi0_dout$next[63:0]$1873 - attribute \src "libresoc.v:48632.14-48632.51" - wire width 64 $1\jtag_dmi0_dout[63:0] - attribute \src "libresoc.v:49563.3-49578.6" - wire width 4 $1\msr__ren[3:0] - attribute \src "libresoc.v:49908.3-49937.6" - wire $1\msr_read$next[0:0]$1899 - attribute \src "libresoc.v:48660.7-48660.22" - wire $1\msr_read[0:0] - attribute \src "libresoc.v:49391.3-49401.6" - wire width 64 $1\new_dec[63:0] - attribute \src "libresoc.v:49463.3-49473.6" - wire width 64 $1\new_tb[63:0] - attribute \src "libresoc.v:49492.3-49507.6" - wire width 64 $1\pc[63:0] - attribute \src "libresoc.v:49588.3-49612.6" - wire $1\pc_changed$next[0:0]$1641 - attribute \src "libresoc.v:48672.7-48672.24" - wire $1\pc_changed[0:0] - attribute \src "libresoc.v:49483.3-49491.6" - wire $1\pc_ok_delay$next[0:0]$1630 - attribute \src "libresoc.v:48682.7-48682.25" - wire $1\pc_ok_delay[0:0] - attribute \src "libresoc.v:49747.3-49783.6" - wire width 32 $1\raw_insn_i$next[31:0]$1879 - attribute \src "libresoc.v:48688.14-48688.32" - wire width 32 $1\raw_insn_i[31:0] - attribute \src "libresoc.v:49521.3-49541.6" - wire width 4 $1\wen[3:0] - attribute \src "libresoc.v:49784.3-49820.6" - wire $2\bigendian_i$next[0:0]$1886 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 8 $2\core_asmcode$next[7:0]$1747 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 64 $2\core_core_cia$next[63:0]$1748 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 8 $2\core_core_cr_rd$next[7:0]$1749 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_core_cr_rd_ok$next[0:0]$1750 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 8 $2\core_core_cr_wr$next[7:0]$1751 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_core_cr_wr_ok$next[0:0]$1752 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 12 $2\core_core_fn_unit$next[11:0]$1753 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 2 $2\core_core_input_carry$next[1:0]$1754 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 32 $2\core_core_insn$next[31:0]$1755 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 7 $2\core_core_insn_type$next[6:0]$1756 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_core_is_32bit$next[0:0]$1757 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_core_lk$next[0:0]$1758 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 64 $2\core_core_msr$next[63:0]$1759 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_core_oe$next[0:0]$1760 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_core_oe_ok$next[0:0]$1761 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_core_rc$next[0:0]$1762 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_core_rc_ok$next[0:0]$1763 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 13 $2\core_core_trapaddr$next[12:0]$1764 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 7 $2\core_core_traptype$next[6:0]$1765 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $2\core_cr_in1$next[2:0]$1766 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_cr_in1_ok$next[0:0]$1767 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $2\core_cr_in2$39$next[2:0]$1768 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $2\core_cr_in2$next[2:0]$1769 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_cr_in2_ok$40$next[0:0]$1770 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_cr_in2_ok$next[0:0]$1771 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $2\core_cr_out$next[2:0]$1772 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_cr_out_ok$next[0:0]$1773 - attribute \src "libresoc.v:50072.3-50103.6" - wire width 64 $2\core_dec$next[63:0]$1930 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 5 $2\core_ea$next[4:0]$1774 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_ea_ok$next[0:0]$1775 - attribute \src "libresoc.v:50072.3-50103.6" - wire $2\core_eint$next[0:0]$1931 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $2\core_fast1$next[2:0]$1776 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_fast1_ok$next[0:0]$1777 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $2\core_fast2$next[2:0]$1778 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_fast2_ok$next[0:0]$1779 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $2\core_fasto1$next[2:0]$1780 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_fasto1_ok$next[0:0]$1781 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $2\core_fasto2$next[2:0]$1782 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_fasto2_ok$next[0:0]$1783 - attribute \src "libresoc.v:50072.3-50103.6" - wire width 64 $2\core_msr$next[63:0]$1932 - attribute \src "libresoc.v:50072.3-50103.6" - wire width 64 $2\core_pc$next[63:0]$1933 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 5 $2\core_reg1$next[4:0]$1784 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_reg1_ok$next[0:0]$1785 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 5 $2\core_reg2$next[4:0]$1786 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_reg2_ok$next[0:0]$1787 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 5 $2\core_reg3$next[4:0]$1788 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_reg3_ok$next[0:0]$1789 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 5 $2\core_rego$next[4:0]$1790 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_rego_ok$next[0:0]$1791 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 10 $2\core_spr1$next[9:0]$1792 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_spr1_ok$next[0:0]$1793 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 10 $2\core_spro$next[9:0]$1794 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_spro_ok$next[0:0]$1795 - attribute \src "libresoc.v:49994.3-50012.6" - wire $2\core_stopped_i[0:0] - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $2\core_xer_in$next[2:0]$1796 - attribute \src "libresoc.v:49613.3-49719.6" - wire $2\core_xer_out$next[0:0]$1797 - attribute \src "libresoc.v:49542.3-49562.6" - wire width 64 $2\data_i[63:0] - attribute \src "libresoc.v:50013.3-50031.6" - wire $2\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:49447.3-49462.6" - wire width 64 $2\dec2_cur_dec$next[63:0]$1623 - attribute \src "libresoc.v:50032.3-50052.6" - wire width 64 $2\dec2_cur_msr$next[63:0]$1918 - attribute \src "libresoc.v:49887.3-49907.6" - wire width 64 $2\dec2_cur_pc$next[63:0]$1895 - attribute \src "libresoc.v:50053.3-50071.6" - wire width 32 $2\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:49363.3-49390.6" - wire width 2 $2\fsm_state$115$next[1:0]$1613 - attribute \src "libresoc.v:49938.3-49983.6" - wire width 2 $2\fsm_state$next[1:0]$1906 - attribute \src "libresoc.v:50104.3-50127.6" - wire width 32 $2\ilatch$next[31:0]$1941 - attribute \src "libresoc.v:49821.3-49836.6" - wire width 48 $2\imem_a_pc_i[47:0] - attribute \src "libresoc.v:49837.3-49861.6" - wire $2\imem_a_valid_i[0:0] - attribute \src "libresoc.v:49862.3-49886.6" - wire $2\imem_f_valid_i[0:0] - attribute \src "libresoc.v:50128.3-50147.6" - wire $2\ivalid_i[0:0] - attribute \src "libresoc.v:49563.3-49578.6" - wire width 4 $2\msr__ren[3:0] - attribute \src "libresoc.v:49908.3-49937.6" - wire $2\msr_read$next[0:0]$1900 - attribute \src "libresoc.v:49492.3-49507.6" - wire width 64 $2\pc[63:0] - attribute \src "libresoc.v:49588.3-49612.6" - wire $2\pc_changed$next[0:0]$1642 - attribute \src "libresoc.v:49747.3-49783.6" - wire width 32 $2\raw_insn_i$next[31:0]$1880 - attribute \src "libresoc.v:49521.3-49541.6" - wire width 4 $2\wen[3:0] - attribute \src "libresoc.v:49784.3-49820.6" - wire $3\bigendian_i$next[0:0]$1887 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 8 $3\core_asmcode$next[7:0]$1798 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 64 $3\core_core_cia$next[63:0]$1799 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 8 $3\core_core_cr_rd$next[7:0]$1800 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_core_cr_rd_ok$next[0:0]$1801 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 8 $3\core_core_cr_wr$next[7:0]$1802 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_core_cr_wr_ok$next[0:0]$1803 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 12 $3\core_core_fn_unit$next[11:0]$1804 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 2 $3\core_core_input_carry$next[1:0]$1805 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 32 $3\core_core_insn$next[31:0]$1806 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 7 $3\core_core_insn_type$next[6:0]$1807 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_core_is_32bit$next[0:0]$1808 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_core_lk$next[0:0]$1809 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 64 $3\core_core_msr$next[63:0]$1810 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_core_oe$next[0:0]$1811 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_core_oe_ok$next[0:0]$1812 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_core_rc$next[0:0]$1813 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_core_rc_ok$next[0:0]$1814 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 13 $3\core_core_trapaddr$next[12:0]$1815 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 7 $3\core_core_traptype$next[6:0]$1816 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $3\core_cr_in1$next[2:0]$1817 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_cr_in1_ok$next[0:0]$1818 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $3\core_cr_in2$39$next[2:0]$1819 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $3\core_cr_in2$next[2:0]$1820 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_cr_in2_ok$40$next[0:0]$1821 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_cr_in2_ok$next[0:0]$1822 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $3\core_cr_out$next[2:0]$1823 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_cr_out_ok$next[0:0]$1824 - attribute \src "libresoc.v:50072.3-50103.6" - wire width 64 $3\core_dec$next[63:0]$1934 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 5 $3\core_ea$next[4:0]$1825 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_ea_ok$next[0:0]$1826 - attribute \src "libresoc.v:50072.3-50103.6" - wire $3\core_eint$next[0:0]$1935 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $3\core_fast1$next[2:0]$1827 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_fast1_ok$next[0:0]$1828 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $3\core_fast2$next[2:0]$1829 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_fast2_ok$next[0:0]$1830 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $3\core_fasto1$next[2:0]$1831 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_fasto1_ok$next[0:0]$1832 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $3\core_fasto2$next[2:0]$1833 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_fasto2_ok$next[0:0]$1834 - attribute \src "libresoc.v:50072.3-50103.6" - wire width 64 $3\core_msr$next[63:0]$1936 - attribute \src "libresoc.v:50072.3-50103.6" - wire width 64 $3\core_pc$next[63:0]$1937 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 5 $3\core_reg1$next[4:0]$1835 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_reg1_ok$next[0:0]$1836 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 5 $3\core_reg2$next[4:0]$1837 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_reg2_ok$next[0:0]$1838 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 5 $3\core_reg3$next[4:0]$1839 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_reg3_ok$next[0:0]$1840 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 5 $3\core_rego$next[4:0]$1841 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_rego_ok$next[0:0]$1842 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 10 $3\core_spr1$next[9:0]$1843 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_spr1_ok$next[0:0]$1844 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 10 $3\core_spro$next[9:0]$1845 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_spro_ok$next[0:0]$1846 - attribute \src "libresoc.v:49613.3-49719.6" - wire width 3 $3\core_xer_in$next[2:0]$1847 - attribute \src "libresoc.v:49613.3-49719.6" - wire $3\core_xer_out$next[0:0]$1848 - attribute \src "libresoc.v:49542.3-49562.6" - wire width 64 $3\data_i[63:0] - attribute \src "libresoc.v:50032.3-50052.6" - wire width 64 $3\dec2_cur_msr$next[63:0]$1919 - attribute \src "libresoc.v:49887.3-49907.6" - wire width 64 $3\dec2_cur_pc$next[63:0]$1896 - attribute \src "libresoc.v:49938.3-49983.6" - wire width 2 $3\fsm_state$next[1:0]$1907 - attribute \src "libresoc.v:50104.3-50127.6" - wire width 32 $3\ilatch$next[31:0]$1942 - attribute \src "libresoc.v:49837.3-49861.6" - wire $3\imem_a_valid_i[0:0] - attribute \src "libresoc.v:49862.3-49886.6" - wire $3\imem_f_valid_i[0:0] - attribute \src "libresoc.v:49908.3-49937.6" - wire $3\msr_read$next[0:0]$1901 - attribute \src "libresoc.v:49588.3-49612.6" - wire $3\pc_changed$next[0:0]$1643 - attribute \src "libresoc.v:49747.3-49783.6" - wire width 32 $3\raw_insn_i$next[31:0]$1881 - attribute \src "libresoc.v:49521.3-49541.6" - wire width 4 $3\wen[3:0] - attribute \src "libresoc.v:49784.3-49820.6" - wire $4\bigendian_i$next[0:0]$1888 - attribute \src "libresoc.v:49613.3-49719.6" - wire $4\core_core_cr_rd_ok$next[0:0]$1849 - attribute \src "libresoc.v:49613.3-49719.6" - wire $4\core_core_cr_wr_ok$next[0:0]$1850 - attribute \src "libresoc.v:49613.3-49719.6" - wire $4\core_core_oe_ok$next[0:0]$1851 - attribute \src "libresoc.v:49613.3-49719.6" - wire $4\core_core_rc_ok$next[0:0]$1852 - attribute \src "libresoc.v:49613.3-49719.6" - wire $4\core_cr_in1_ok$next[0:0]$1853 - attribute \src "libresoc.v:49613.3-49719.6" - wire $4\core_cr_in2_ok$40$next[0:0]$1854 - attribute \src "libresoc.v:49613.3-49719.6" - wire $4\core_cr_in2_ok$next[0:0]$1855 - attribute \src "libresoc.v:49613.3-49719.6" - wire $4\core_cr_out_ok$next[0:0]$1856 - attribute \src "libresoc.v:49613.3-49719.6" - wire $4\core_ea_ok$next[0:0]$1857 - attribute \src "libresoc.v:49613.3-49719.6" - wire $4\core_fast1_ok$next[0:0]$1858 - attribute \src "libresoc.v:49613.3-49719.6" - wire $4\core_fast2_ok$next[0:0]$1859 - attribute \src "libresoc.v:49613.3-49719.6" - wire $4\core_fasto1_ok$next[0:0]$1860 - attribute \src "libresoc.v:49613.3-49719.6" - wire $4\core_fasto2_ok$next[0:0]$1861 - attribute \src "libresoc.v:49613.3-49719.6" - wire $4\core_reg1_ok$next[0:0]$1862 - attribute \src "libresoc.v:49613.3-49719.6" - wire $4\core_reg2_ok$next[0:0]$1863 - attribute \src "libresoc.v:49613.3-49719.6" - wire $4\core_reg3_ok$next[0:0]$1864 - attribute \src "libresoc.v:49613.3-49719.6" - wire $4\core_rego_ok$next[0:0]$1865 - attribute \src "libresoc.v:49613.3-49719.6" - wire $4\core_spr1_ok$next[0:0]$1866 - attribute \src "libresoc.v:49613.3-49719.6" - wire $4\core_spro_ok$next[0:0]$1867 - attribute \src "libresoc.v:49938.3-49983.6" - wire width 2 $4\fsm_state$next[1:0]$1908 - attribute \src "libresoc.v:49908.3-49937.6" - wire $4\msr_read$next[0:0]$1902 - attribute \src "libresoc.v:49747.3-49783.6" - wire width 32 $4\raw_insn_i$next[31:0]$1882 - attribute \src "libresoc.v:49938.3-49983.6" - wire width 2 $5\fsm_state$next[1:0]$1909 - attribute \src "libresoc.v:48723.19-48723.110" - wire width 65 $add$libresoc.v:48723$1455_Y - attribute \src "libresoc.v:48726.18-48726.107" - wire width 65 $add$libresoc.v:48726$1458_Y - attribute \src "libresoc.v:48725.18-48725.104" - wire $and$libresoc.v:48725$1457_Y - attribute \src "libresoc.v:48734.18-48734.101" - wire $and$libresoc.v:48734$1466_Y - attribute \src "libresoc.v:48735.18-48735.109" - wire width 4 $and$libresoc.v:48735$1467_Y - attribute \src "libresoc.v:48743.18-48743.101" - wire $and$libresoc.v:48743$1475_Y - attribute \src "libresoc.v:48746.18-48746.101" - wire $and$libresoc.v:48746$1478_Y - attribute \src "libresoc.v:48749.18-48749.101" - wire $and$libresoc.v:48749$1481_Y - attribute \src "libresoc.v:48753.18-48753.101" - wire $and$libresoc.v:48753$1485_Y - attribute \src "libresoc.v:48756.18-48756.101" - wire $and$libresoc.v:48756$1488_Y - attribute \src "libresoc.v:48760.18-48760.101" - wire $and$libresoc.v:48760$1492_Y - attribute \src "libresoc.v:48765.18-48765.101" - wire $and$libresoc.v:48765$1497_Y - attribute \src "libresoc.v:48768.18-48768.101" - wire $and$libresoc.v:48768$1500_Y - attribute \src "libresoc.v:48720.19-48720.109" - wire width 64 $extend$libresoc.v:48720$1450_Y - attribute \src "libresoc.v:48721.19-48721.108" - wire width 64 $extend$libresoc.v:48721$1452_Y - attribute \src "libresoc.v:48714.19-48714.111" - wire width 7 $mul$libresoc.v:48714$1444_Y - attribute \src "libresoc.v:48716.19-48716.111" - wire width 7 $mul$libresoc.v:48716$1446_Y - attribute \src "libresoc.v:48718.18-48718.101" - wire $ne$libresoc.v:48718$1448_Y - attribute \src "libresoc.v:48719.19-48719.118" - wire $ne$libresoc.v:48719$1449_Y - attribute \src "libresoc.v:48737.17-48737.101" - wire $ne$libresoc.v:48737$1469_Y - attribute \src "libresoc.v:48713.18-48713.99" - wire $not$libresoc.v:48713$1443_Y - attribute \src "libresoc.v:48724.18-48724.103" - wire $not$libresoc.v:48724$1456_Y - attribute \src "libresoc.v:48727.18-48727.98" - wire $not$libresoc.v:48727$1459_Y - attribute \src "libresoc.v:48728.18-48728.101" - wire $not$libresoc.v:48728$1460_Y - attribute \src "libresoc.v:48729.18-48729.101" - wire $not$libresoc.v:48729$1461_Y - attribute \src "libresoc.v:48730.18-48730.101" - wire $not$libresoc.v:48730$1462_Y - attribute \src "libresoc.v:48731.18-48731.101" - wire $not$libresoc.v:48731$1463_Y - attribute \src "libresoc.v:48732.18-48732.106" - wire $not$libresoc.v:48732$1464_Y - attribute \src "libresoc.v:48733.18-48733.103" - wire $not$libresoc.v:48733$1465_Y - attribute \src "libresoc.v:48738.18-48738.101" - wire $not$libresoc.v:48738$1470_Y - attribute \src "libresoc.v:48739.18-48739.101" - wire $not$libresoc.v:48739$1471_Y - attribute \src "libresoc.v:48740.18-48740.101" - wire $not$libresoc.v:48740$1472_Y - attribute \src "libresoc.v:48741.18-48741.106" - wire $not$libresoc.v:48741$1473_Y - attribute \src "libresoc.v:48742.18-48742.103" - wire $not$libresoc.v:48742$1474_Y - attribute \src "libresoc.v:48744.18-48744.106" - wire $not$libresoc.v:48744$1476_Y - attribute \src "libresoc.v:48745.18-48745.103" - wire $not$libresoc.v:48745$1477_Y - attribute \src "libresoc.v:48747.18-48747.106" - wire $not$libresoc.v:48747$1479_Y - attribute \src "libresoc.v:48748.18-48748.103" - wire $not$libresoc.v:48748$1480_Y - attribute \src "libresoc.v:48750.18-48750.106" - wire $not$libresoc.v:48750$1482_Y - attribute \src "libresoc.v:48751.18-48751.103" - wire $not$libresoc.v:48751$1483_Y - attribute \src "libresoc.v:48754.18-48754.106" - wire $not$libresoc.v:48754$1486_Y - attribute \src "libresoc.v:48755.18-48755.103" - wire $not$libresoc.v:48755$1487_Y - attribute \src "libresoc.v:48757.18-48757.99" - wire $not$libresoc.v:48757$1489_Y - attribute \src "libresoc.v:48758.18-48758.106" - wire $not$libresoc.v:48758$1490_Y - attribute \src "libresoc.v:48759.18-48759.103" - wire $not$libresoc.v:48759$1491_Y - attribute \src "libresoc.v:48761.18-48761.101" - wire $not$libresoc.v:48761$1493_Y - attribute \src "libresoc.v:48762.18-48762.106" - wire $not$libresoc.v:48762$1494_Y - attribute \src "libresoc.v:48764.18-48764.103" - wire $not$libresoc.v:48764$1496_Y - attribute \src "libresoc.v:48766.18-48766.106" - wire $not$libresoc.v:48766$1498_Y - attribute \src "libresoc.v:48767.18-48767.103" - wire $not$libresoc.v:48767$1499_Y - attribute \src "libresoc.v:48763.17-48763.109" - wire $or$libresoc.v:48763$1495_Y - attribute \src "libresoc.v:48720.19-48720.109" - wire width 64 $pos$libresoc.v:48720$1451_Y - attribute \src "libresoc.v:48721.19-48721.108" - wire width 64 $pos$libresoc.v:48721$1453_Y - attribute \src "libresoc.v:48736.18-48736.91" - wire $reduce_or$libresoc.v:48736$1468_Y - attribute \src "libresoc.v:48715.19-48715.42" - wire width 64 $shr$libresoc.v:48715$1445_Y - attribute \src "libresoc.v:48717.19-48717.42" - wire width 64 $shr$libresoc.v:48717$1447_Y - attribute \src "libresoc.v:48722.19-48722.110" - wire width 65 $sub$libresoc.v:48722$1454_Y - attribute \src "libresoc.v:48752.17-48752.100" - wire width 3 $sub$libresoc.v:48752$1484_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:163" - wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:270" - wire width 32 \$101 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - wire width 7 \$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:270" - wire width 32 \$105 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - wire width 7 \$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - wire \$109 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \$111 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" - wire width 65 \$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" - wire width 65 \$117 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:391" - wire width 65 \$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:391" - wire width 65 \$121 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:183" - wire width 65 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:183" - wire width 65 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:188" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:158" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" - wire width 4 \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" - wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" - wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:159" - wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:159" - wire width 3 \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:257" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:163" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" - wire \$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - wire \$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:257" - wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire input 122 \TAP_bus__tck - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire input 62 \TAP_bus__tdi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire output 113 \TAP_bus__tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire input 123 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" - wire \bigendian_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" - wire \bigendian_i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:92" - wire output 140 \busy_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \cia__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \cia__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" - wire width 8 \core_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" - wire width 8 \core_asmcode$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:91" - wire input 1 \core_bigendian_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" - wire width 64 \core_core_cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" - wire width 64 \core_core_cia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \core_core_cr_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \core_core_cr_rd$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_core_cr_rd_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_core_cr_rd_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \core_core_cr_wr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \core_core_cr_wr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_core_cr_wr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_core_cr_wr_ok$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" - wire width 12 \core_core_fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" - wire width 12 \core_core_fn_unit$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" - wire width 2 \core_core_input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" - wire width 2 \core_core_input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" - wire width 32 \core_core_insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" - wire width 32 \core_core_insn$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" - wire width 7 \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" - wire width 7 \core_core_insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire \core_core_is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire \core_core_is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire \core_core_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire \core_core_lk$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" - wire width 64 \core_core_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" - wire width 64 \core_core_msr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_core_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_core_oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_core_oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_core_oe_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_core_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_core_rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_core_rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_core_rc_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 13 \core_core_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 13 \core_core_trapaddr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 7 \core_core_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 7 \core_core_traptype$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_cr_in1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_cr_in1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_cr_in1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_cr_in2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_cr_in2$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_cr_in2$39$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_cr_in2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_cr_in2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_cr_in2_ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_cr_in2_ok$40$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_cr_in2_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_cr_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_cr_out_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_cr_out_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" - wire width 64 \core_dec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" - wire width 64 \core_dec$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \core_ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \core_ea$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_ea_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" - wire \core_eint - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" - wire \core_eint$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_fast1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_fast1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_fast2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_fast2_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_fasto1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_fasto1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_fasto1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_fasto1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_fasto2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \core_fasto2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_fasto2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_fasto2_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 \core_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 \core_msr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 \core_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 \core_pc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \core_reg1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \core_reg1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_reg1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_reg1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \core_reg2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \core_reg2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_reg2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_reg2_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \core_reg3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \core_reg3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_reg3_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_reg3_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \core_rego - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \core_rego$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_rego_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_rego_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" - wire \core_reset_i - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \core_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \core_spr1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_spr1_ok$next - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \core_spro - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \core_spro$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \core_spro_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" - wire \core_stopped_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:104" - wire \core_terminate_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" - wire width 3 \core_xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" - wire width 3 \core_xer_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" - wire \core_xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" - wire \core_xer_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" - wire \corebusy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:154" - wire \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire \cu_ad__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire \cu_ad__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire \cu_st__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire \cu_st__rel_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \cu_st__rel_o_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \cu_st__rel_o_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \cu_st__rel_o_rise - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" - wire \d_cr_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" - wire \d_cr_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" - wire \d_reg_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" - wire \d_reg_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335" - wire \d_xer_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335" - wire \d_xer_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 \dbg_core_dbg_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 \dbg_core_dbg_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" - wire \dbg_core_rst_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:97" - wire \dbg_core_stop_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" - wire \dbg_core_stopped_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" - wire \dbg_d_cr_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" - wire width 64 \dbg_d_cr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" - wire \dbg_d_cr_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" - wire \dbg_d_gpr_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" - wire width 7 \dbg_d_gpr_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" - wire width 64 \dbg_d_gpr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" - wire \dbg_d_gpr_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" - wire \dbg_d_xer_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" - wire width 64 \dbg_d_xer_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" - wire \dbg_d_xer_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" - wire \dbg_dmi_ack_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 4 \dbg_dmi_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 4 \dbg_dmi_addr_i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 64 \dbg_dmi_din - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 64 \dbg_dmi_din$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" - wire width 64 \dbg_dmi_dout - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" - wire \dbg_dmi_req_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" - wire \dbg_dmi_req_i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" - wire \dbg_dmi_we_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" - wire \dbg_dmi_we_i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102" - wire \dbg_terminate_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" - wire width 8 \dec2_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire \dec2_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" - wire width 64 \dec2_cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec2_cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_cr_in1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec2_cr_in2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec2_cr_in2$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_cr_in2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_cr_in2_ok$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec2_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_cr_out_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \dec2_cr_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_cr_rd_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \dec2_cr_wr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_cr_wr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" - wire width 64 \dec2_cur_dec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" - wire width 64 \dec2_cur_dec$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" - wire \dec2_cur_eint - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" - wire \dec2_cur_eint$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 \dec2_cur_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 \dec2_cur_msr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 \dec2_cur_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 \dec2_cur_pc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec2_ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec2_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec2_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec2_fasto1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_fasto1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec2_fasto2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_fasto2_ok - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" - wire width 12 \dec2_fn_unit - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" - wire width 2 \dec2_input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" - wire width 32 \dec2_insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" - wire width 7 \dec2_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire \dec2_is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire \dec2_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" - wire width 64 \dec2_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 \dec2_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec2_reg1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_reg1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec2_reg2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_reg2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec2_reg3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_reg3_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec2_rego - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_rego_ok - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \dec2_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_spr1_ok - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \dec2_spro - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 13 \dec2_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 7 \dec2_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" - wire width 3 \dec2_xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" - wire \dec2_xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:157" - wire width 2 \delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:157" - wire width 2 \delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \dmi__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \dmi__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \dmi__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - wire width 2 \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" - wire width 2 \fsm_state$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" - wire width 2 \fsm_state$115$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - wire width 2 \fsm_state$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 \full_rd2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \full_rd2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 6 \full_rd__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \full_rd__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 65 \gpio_gpio0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 15 \gpio_gpio0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 16 \gpio_gpio0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 14 \gpio_gpio0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 66 \gpio_gpio0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 67 \gpio_gpio0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 95 \gpio_gpio10__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 45 \gpio_gpio10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 46 \gpio_gpio10__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 44 \gpio_gpio10__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 96 \gpio_gpio10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 97 \gpio_gpio10__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 98 \gpio_gpio11__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 48 \gpio_gpio11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 49 \gpio_gpio11__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 47 \gpio_gpio11__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 99 \gpio_gpio11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 100 \gpio_gpio11__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 101 \gpio_gpio12__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 51 \gpio_gpio12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 52 \gpio_gpio12__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 50 \gpio_gpio12__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 102 \gpio_gpio12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 103 \gpio_gpio12__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 104 \gpio_gpio13__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 54 \gpio_gpio13__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 55 \gpio_gpio13__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 53 \gpio_gpio13__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 105 \gpio_gpio13__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 106 \gpio_gpio13__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 107 \gpio_gpio14__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 57 \gpio_gpio14__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 58 \gpio_gpio14__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 56 \gpio_gpio14__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 108 \gpio_gpio14__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 109 \gpio_gpio14__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 110 \gpio_gpio15__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 60 \gpio_gpio15__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 61 \gpio_gpio15__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 59 \gpio_gpio15__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 111 \gpio_gpio15__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 112 \gpio_gpio15__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 68 \gpio_gpio1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 18 \gpio_gpio1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 19 \gpio_gpio1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 17 \gpio_gpio1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 69 \gpio_gpio1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 70 \gpio_gpio1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 71 \gpio_gpio2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 21 \gpio_gpio2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 22 \gpio_gpio2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 20 \gpio_gpio2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 72 \gpio_gpio2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 73 \gpio_gpio2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 74 \gpio_gpio3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 24 \gpio_gpio3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 25 \gpio_gpio3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 23 \gpio_gpio3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 75 \gpio_gpio3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 76 \gpio_gpio3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 77 \gpio_gpio4__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 27 \gpio_gpio4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 28 \gpio_gpio4__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 26 \gpio_gpio4__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 78 \gpio_gpio4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 79 \gpio_gpio4__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 80 \gpio_gpio5__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 30 \gpio_gpio5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 31 \gpio_gpio5__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 29 \gpio_gpio5__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 81 \gpio_gpio5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 82 \gpio_gpio5__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 83 \gpio_gpio6__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 33 \gpio_gpio6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 34 \gpio_gpio6__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 32 \gpio_gpio6__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 84 \gpio_gpio6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 85 \gpio_gpio6__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 86 \gpio_gpio7__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 36 \gpio_gpio7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 37 \gpio_gpio7__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 35 \gpio_gpio7__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 87 \gpio_gpio7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 88 \gpio_gpio7__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 89 \gpio_gpio8__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 39 \gpio_gpio8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 40 \gpio_gpio8__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 38 \gpio_gpio8__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 90 \gpio_gpio8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 91 \gpio_gpio8__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 92 \gpio_gpio9__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 42 \gpio_gpio9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 43 \gpio_gpio9__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 41 \gpio_gpio9__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 93 \gpio_gpio9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 94 \gpio_gpio9__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 6 \ibus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 output 11 \ibus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 5 \ibus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 10 \ibus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 7 \ibus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 output 9 \ibus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 8 \ibus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 124 \icp_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 130 \icp_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 125 \icp_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 126 \icp_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 127 \icp_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 131 \icp_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 128 \icp_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 129 \icp_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 137 \ics_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 132 \ics_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 134 \ics_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 136 \ics_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 138 \ics_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 135 \ics_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 139 \ics_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:179" - wire width 32 \ilatch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:179" - wire width 32 \ilatch$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" - wire width 48 \imem_a_pc_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" - wire \imem_a_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" - wire \imem_f_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" - wire width 64 \imem_f_instr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" - wire \imem_f_valid_i - attribute \src "libresoc.v:47126.7-47126.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 133 \int_level_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" - wire \intclk_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" - wire \intclk_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \issue__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \issue__addr$119 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \issue__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \issue__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \issue__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \issue__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" - wire \issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" - wire \ivalid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" - wire \jtag_dmi0_ack_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" - wire \jtag_dmi0_ack_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 4 \jtag_dmi0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 64 \jtag_dmi0_din - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" - wire width 64 \jtag_dmi0_dout - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" - wire width 64 \jtag_dmi0_dout$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" - wire \jtag_dmi0_req_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" - wire \jtag_dmi0_we_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire input 120 \jtag_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire width 29 output 114 \jtag_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire output 116 \jtag_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire width 64 input 121 \jtag_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire width 64 output 119 \jtag_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire output 115 \jtag_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire output 117 \jtag_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire output 118 \jtag_wb__we - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \msr__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \msr__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205" - wire \msr_read - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205" - wire \msr_read$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:373" - wire width 64 \new_dec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:390" - wire width 64 \new_tb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:182" - wire width 64 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:186" - wire width 64 \pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177" - wire \pc_changed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177" - wire \pc_changed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 4 \pc_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 3 \pc_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:89" - wire width 64 output 2 \pc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:187" - wire \pc_ok_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:187" - wire \pc_ok_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire \por_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" - wire width 32 \raw_insn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" - wire width 32 \raw_insn_i$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \state_nia_wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 64 \uart_rx__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 13 \uart_rx__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 12 \uart_tx__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 63 \uart_tx__pad__o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" - wire \xics_icp_core_irq_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" - wire width 8 \xics_icp_ics_i_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" - wire width 4 \xics_icp_ics_i_src - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" - wire width 8 \xics_ics_icp_o_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" - wire width 4 \xics_ics_icp_o_src - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:391" - cell $add $add$libresoc.v:48723$1455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \issue__data_o - connect \B 1'1 - connect \Y $add$libresoc.v:48723$1455_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:183" - cell $add $add$libresoc.v:48726$1458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 65 - connect \A \dec2_cur_pc - connect \B 3'100 - connect \Y $add$libresoc.v:48726$1458_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:48725$1457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_st__rel_o - connect \B \$12 - connect \Y $and$libresoc.v:48725$1457_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $and $and$libresoc.v:48734$1466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$29 - connect \B \$31 - connect \Y $and$libresoc.v:48734$1466_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" - cell $and $and$libresoc.v:48735$1467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \state_nia_wen - connect \B 1'1 - connect \Y $and$libresoc.v:48735$1467_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $and $and$libresoc.v:48743$1475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$47 - connect \B \$49 - connect \Y $and$libresoc.v:48743$1475_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $and $and$libresoc.v:48746$1478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$53 - connect \B \$55 - connect \Y $and$libresoc.v:48746$1478_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $and $and$libresoc.v:48749$1481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$59 - connect \B \$61 - connect \Y $and$libresoc.v:48749$1481_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $and $and$libresoc.v:48753$1485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$65 - connect \B \$67 - connect \Y $and$libresoc.v:48753$1485_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $and $and$libresoc.v:48756$1488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$71 - connect \B \$73 - connect \Y $and$libresoc.v:48756$1488_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $and $and$libresoc.v:48760$1492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$79 - connect \B \$81 - connect \Y $and$libresoc.v:48760$1492_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $and $and$libresoc.v:48765$1497 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$87 - connect \B \$89 - connect \Y $and$libresoc.v:48765$1497_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $and $and$libresoc.v:48768$1500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$93 - connect \B \$95 - connect \Y $and$libresoc.v:48768$1500_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $extend$libresoc.v:48720$1450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \full_rd2__data_o - connect \Y $extend$libresoc.v:48720$1450_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $extend$libresoc.v:48721$1452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \full_rd__data_o - connect \Y $extend$libresoc.v:48721$1452_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:48714$1444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 7 - connect \A \dec2_cur_pc [2] - connect \B 6'100000 - connect \Y $mul$libresoc.v:48714$1444_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:48716$1446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 7 - connect \A \dec2_cur_pc [2] - connect \B 6'100000 - connect \Y $mul$libresoc.v:48716$1446_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:163" - cell $ne $ne$libresoc.v:48718$1448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \delay - connect \B \$8 - connect \Y $ne$libresoc.v:48718$1448_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $ne $ne$libresoc.v:48719$1449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \core_core_insn_type - connect \B 7'0000001 - connect \Y $ne$libresoc.v:48719$1449_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:158" - cell $ne $ne$libresoc.v:48737$1469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \delay - connect \B 1'0 - connect \Y $ne$libresoc.v:48737$1469_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:257" - cell $not $not$libresoc.v:48713$1443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msr_read - connect \Y $not$libresoc.v:48713$1443_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:48724$1456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_st__rel_o_dly - connect \Y $not$libresoc.v:48724$1456_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:188" - cell $not $not$libresoc.v:48727$1459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pc_i_ok - connect \Y $not$libresoc.v:48727$1459_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" - cell $not $not$libresoc.v:48728$1460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \corebusy_o - connect \Y $not$libresoc.v:48728$1460_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" - cell $not $not$libresoc.v:48729$1461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pc_changed - connect \Y $not$libresoc.v:48729$1461_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" - cell $not $not$libresoc.v:48730$1462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \corebusy_o - connect \Y $not$libresoc.v:48730$1462_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" - cell $not $not$libresoc.v:48731$1463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pc_changed - connect \Y $not$libresoc.v:48731$1463_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $not $not$libresoc.v:48732$1464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:48732$1464_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $not $not$libresoc.v:48733$1465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_reset_i - connect \Y $not$libresoc.v:48733$1465_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" - cell $not $not$libresoc.v:48738$1470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \corebusy_o - connect \Y $not$libresoc.v:48738$1470_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" - cell $not $not$libresoc.v:48739$1471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \corebusy_o - connect \Y $not$libresoc.v:48739$1471_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" - cell $not $not$libresoc.v:48740$1472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \corebusy_o - connect \Y $not$libresoc.v:48740$1472_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $not $not$libresoc.v:48741$1473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:48741$1473_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $not $not$libresoc.v:48742$1474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_reset_i - connect \Y $not$libresoc.v:48742$1474_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $not $not$libresoc.v:48744$1476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:48744$1476_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $not $not$libresoc.v:48745$1477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_reset_i - connect \Y $not$libresoc.v:48745$1477_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $not $not$libresoc.v:48747$1479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:48747$1479_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $not $not$libresoc.v:48748$1480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_reset_i - connect \Y $not$libresoc.v:48748$1480_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $not $not$libresoc.v:48750$1482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:48750$1482_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $not $not$libresoc.v:48751$1483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_reset_i - connect \Y $not$libresoc.v:48751$1483_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $not $not$libresoc.v:48754$1486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:48754$1486_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $not $not$libresoc.v:48755$1487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_reset_i - connect \Y $not$libresoc.v:48755$1487_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:257" - cell $not $not$libresoc.v:48757$1489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msr_read - connect \Y $not$libresoc.v:48757$1489_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $not $not$libresoc.v:48758$1490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:48758$1490_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $not $not$libresoc.v:48759$1491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_reset_i - connect \Y $not$libresoc.v:48759$1491_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" - cell $not $not$libresoc.v:48761$1493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \corebusy_o - connect \Y $not$libresoc.v:48761$1493_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $not $not$libresoc.v:48762$1494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:48762$1494_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $not $not$libresoc.v:48764$1496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_reset_i - connect \Y $not$libresoc.v:48764$1496_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $not $not$libresoc.v:48766$1498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:48766$1498_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - cell $not $not$libresoc.v:48767$1499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_reset_i - connect \Y $not$libresoc.v:48767$1499_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:163" - cell $or $or$libresoc.v:48763$1495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B \dbg_core_rst_o - connect \Y $or$libresoc.v:48763$1495_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $pos$libresoc.v:48720$1451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:48720$1450_Y - connect \Y $pos$libresoc.v:48720$1451_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $pos$libresoc.v:48721$1453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:48721$1452_Y - connect \Y $pos$libresoc.v:48721$1453_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:48736$1468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \$36 - connect \Y $reduce_or$libresoc.v:48736$1468_Y - end - attribute \src "libresoc.v:48715.19-48715.42" - cell $shr $shr$libresoc.v:48715$1445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 64 - connect \A \imem_f_instr_o - connect \B \$102 - connect \Y $shr$libresoc.v:48715$1445_Y - end - attribute \src "libresoc.v:48717.19-48717.42" - cell $shr $shr$libresoc.v:48717$1447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 64 - connect \A \imem_f_instr_o - connect \B \$106 - connect \Y $shr$libresoc.v:48717$1447_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" - cell $sub $sub$libresoc.v:48722$1454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \issue__data_o - connect \B 1'1 - connect \Y $sub$libresoc.v:48722$1454_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:159" - cell $sub $sub$libresoc.v:48752$1484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \delay - connect \B 1'1 - connect \Y $sub$libresoc.v:48752$1484_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:48925.7-48950.4" - cell \dbg \dbg - connect \core_dbg_msr \dbg_core_dbg_msr - connect \core_dbg_pc \dbg_core_dbg_pc - connect \core_rst_o \dbg_core_rst_o - connect \core_stop_o \dbg_core_stop_o - connect \core_stopped_i \dbg_core_stopped_i - connect \d_cr_ack \dbg_d_cr_ack - connect \d_cr_data \dbg_d_cr_data - connect \d_cr_req \dbg_d_cr_req - connect \d_gpr_ack \dbg_d_gpr_ack - connect \d_gpr_addr \dbg_d_gpr_addr - connect \d_gpr_data \dbg_d_gpr_data - connect \d_gpr_req \dbg_d_gpr_req - connect \d_xer_ack \dbg_d_xer_ack - connect \d_xer_data \dbg_d_xer_data - connect \d_xer_req \dbg_d_xer_req - connect \dmi_ack_o \dbg_dmi_ack_o - connect \dmi_addr_i \dbg_dmi_addr_i - connect \dmi_din \dbg_dmi_din - connect \dmi_dout \dbg_dmi_dout - connect \dmi_req_i \dbg_dmi_req_i - connect \dmi_we_i \dbg_dmi_we_i - connect \intclk_clk \intclk_clk - connect \intclk_rst \intclk_rst - connect \terminate_i \dbg_terminate_i - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:48951.8-49009.4" - cell \dec2 \dec2 - connect \asmcode \dec2_asmcode - connect \bigendian \dec2_bigendian - connect \cia \dec2_cia - connect \cr_in1 \dec2_cr_in1 - connect \cr_in1_ok \dec2_cr_in1_ok - connect \cr_in2 \dec2_cr_in2 - connect \cr_in2$1 \dec2_cr_in2$1 - connect \cr_in2_ok \dec2_cr_in2_ok - connect \cr_in2_ok$2 \dec2_cr_in2_ok$2 - connect \cr_out \dec2_cr_out - connect \cr_out_ok \dec2_cr_out_ok - connect \cr_rd \dec2_cr_rd - connect \cr_rd_ok \dec2_cr_rd_ok - connect \cr_wr \dec2_cr_wr - connect \cr_wr_ok \dec2_cr_wr_ok - connect \cur_dec \dec2_cur_dec - connect \cur_eint \dec2_cur_eint - connect \cur_msr \dec2_cur_msr - connect \cur_pc \dec2_cur_pc - connect \ea \dec2_ea - connect \ea_ok \dec2_ea_ok - connect \fast1 \dec2_fast1 - connect \fast1_ok \dec2_fast1_ok - connect \fast2 \dec2_fast2 - connect \fast2_ok \dec2_fast2_ok - connect \fasto1 \dec2_fasto1 - connect \fasto1_ok \dec2_fasto1_ok - connect \fasto2 \dec2_fasto2 - connect \fasto2_ok \dec2_fasto2_ok - connect \fn_unit \dec2_fn_unit - connect \input_carry \dec2_input_carry - connect \insn \dec2_insn - connect \insn_type \dec2_insn_type - connect \is_32bit \dec2_is_32bit - connect \lk \dec2_lk - connect \msr \dec2_msr - connect \oe \dec2_oe - connect \oe_ok \dec2_oe_ok - connect \raw_opcode_in \dec2_raw_opcode_in - connect \rc \dec2_rc - connect \rc_ok \dec2_rc_ok - connect \reg1 \dec2_reg1 - connect \reg1_ok \dec2_reg1_ok - connect \reg2 \dec2_reg2 - connect \reg2_ok \dec2_reg2_ok - connect \reg3 \dec2_reg3 - connect \reg3_ok \dec2_reg3_ok - connect \rego \dec2_rego - connect \rego_ok \dec2_rego_ok - connect \spr1 \dec2_spr1 - connect \spr1_ok \dec2_spr1_ok - connect \spro \dec2_spro - connect \spro_ok \dec2_spro_ok - connect \trapaddr \dec2_trapaddr - connect \traptype \dec2_traptype - connect \xer_in \dec2_xer_in - connect \xer_out \dec2_xer_out - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:49010.8-49025.4" - cell \imem \imem - connect \a_pc_i \imem_a_pc_i - connect \a_valid_i \imem_a_valid_i - connect \f_busy_o \imem_f_busy_o - connect \f_instr_o \imem_f_instr_o - connect \f_valid_i \imem_f_valid_i - connect \ibus__ack \ibus__ack - connect \ibus__adr \ibus__adr - connect \ibus__cyc \ibus__cyc - connect \ibus__dat_r \ibus__dat_r - connect \ibus__err \ibus__err - connect \ibus__sel \ibus__sel - connect \ibus__stb \ibus__stb - connect \intclk_clk \intclk_clk - connect \intclk_rst \intclk_rst - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:49026.8-49147.4" - cell \jtag \jtag - connect \TAP_bus__tck \TAP_bus__tck - connect \TAP_bus__tdi \TAP_bus__tdi - connect \TAP_bus__tdo \TAP_bus__tdo - connect \TAP_bus__tms \TAP_bus__tms - connect \dmi0_ack_o \jtag_dmi0_ack_o - connect \dmi0_addr_i \jtag_dmi0_addr_i - connect \dmi0_din \jtag_dmi0_din - connect \dmi0_dout \jtag_dmi0_dout - connect \dmi0_req_i \jtag_dmi0_req_i - connect \dmi0_we_i \jtag_dmi0_we_i - connect \gpio_gpio0__core__i \gpio_gpio0__core__i - connect \gpio_gpio0__core__o \gpio_gpio0__core__o - connect \gpio_gpio0__core__oe \gpio_gpio0__core__oe - connect \gpio_gpio0__pad__i \gpio_gpio0__pad__i - connect \gpio_gpio0__pad__o \gpio_gpio0__pad__o - connect \gpio_gpio0__pad__oe \gpio_gpio0__pad__oe - connect \gpio_gpio10__core__i \gpio_gpio10__core__i - connect \gpio_gpio10__core__o \gpio_gpio10__core__o - connect \gpio_gpio10__core__oe \gpio_gpio10__core__oe - connect \gpio_gpio10__pad__i \gpio_gpio10__pad__i - connect \gpio_gpio10__pad__o \gpio_gpio10__pad__o - connect \gpio_gpio10__pad__oe \gpio_gpio10__pad__oe - connect \gpio_gpio11__core__i \gpio_gpio11__core__i - connect \gpio_gpio11__core__o \gpio_gpio11__core__o - connect \gpio_gpio11__core__oe \gpio_gpio11__core__oe - connect \gpio_gpio11__pad__i \gpio_gpio11__pad__i - connect \gpio_gpio11__pad__o \gpio_gpio11__pad__o - connect \gpio_gpio11__pad__oe \gpio_gpio11__pad__oe - connect \gpio_gpio12__core__i \gpio_gpio12__core__i - connect \gpio_gpio12__core__o \gpio_gpio12__core__o - connect \gpio_gpio12__core__oe \gpio_gpio12__core__oe - connect \gpio_gpio12__pad__i \gpio_gpio12__pad__i - connect \gpio_gpio12__pad__o \gpio_gpio12__pad__o - connect \gpio_gpio12__pad__oe \gpio_gpio12__pad__oe - connect \gpio_gpio13__core__i \gpio_gpio13__core__i - connect \gpio_gpio13__core__o \gpio_gpio13__core__o - connect \gpio_gpio13__core__oe \gpio_gpio13__core__oe - connect \gpio_gpio13__pad__i \gpio_gpio13__pad__i - connect \gpio_gpio13__pad__o \gpio_gpio13__pad__o - connect \gpio_gpio13__pad__oe \gpio_gpio13__pad__oe - connect \gpio_gpio14__core__i \gpio_gpio14__core__i - connect \gpio_gpio14__core__o \gpio_gpio14__core__o - connect \gpio_gpio14__core__oe \gpio_gpio14__core__oe - connect \gpio_gpio14__pad__i \gpio_gpio14__pad__i - connect \gpio_gpio14__pad__o \gpio_gpio14__pad__o - connect \gpio_gpio14__pad__oe \gpio_gpio14__pad__oe - connect \gpio_gpio15__core__i \gpio_gpio15__core__i - connect \gpio_gpio15__core__o \gpio_gpio15__core__o - connect \gpio_gpio15__core__oe \gpio_gpio15__core__oe - connect \gpio_gpio15__pad__i \gpio_gpio15__pad__i - connect \gpio_gpio15__pad__o \gpio_gpio15__pad__o - connect \gpio_gpio15__pad__oe \gpio_gpio15__pad__oe - connect \gpio_gpio1__core__i \gpio_gpio1__core__i - connect \gpio_gpio1__core__o \gpio_gpio1__core__o - connect \gpio_gpio1__core__oe \gpio_gpio1__core__oe - connect \gpio_gpio1__pad__i \gpio_gpio1__pad__i - connect \gpio_gpio1__pad__o \gpio_gpio1__pad__o - connect \gpio_gpio1__pad__oe \gpio_gpio1__pad__oe - connect \gpio_gpio2__core__i \gpio_gpio2__core__i - connect \gpio_gpio2__core__o \gpio_gpio2__core__o - connect \gpio_gpio2__core__oe \gpio_gpio2__core__oe - connect \gpio_gpio2__pad__i \gpio_gpio2__pad__i - connect \gpio_gpio2__pad__o \gpio_gpio2__pad__o - connect \gpio_gpio2__pad__oe \gpio_gpio2__pad__oe - connect \gpio_gpio3__core__i \gpio_gpio3__core__i - connect \gpio_gpio3__core__o \gpio_gpio3__core__o - connect \gpio_gpio3__core__oe \gpio_gpio3__core__oe - connect \gpio_gpio3__pad__i \gpio_gpio3__pad__i - connect \gpio_gpio3__pad__o \gpio_gpio3__pad__o - connect \gpio_gpio3__pad__oe \gpio_gpio3__pad__oe - connect \gpio_gpio4__core__i \gpio_gpio4__core__i - connect \gpio_gpio4__core__o \gpio_gpio4__core__o - connect \gpio_gpio4__core__oe \gpio_gpio4__core__oe - connect \gpio_gpio4__pad__i \gpio_gpio4__pad__i - connect \gpio_gpio4__pad__o \gpio_gpio4__pad__o - connect \gpio_gpio4__pad__oe \gpio_gpio4__pad__oe - connect \gpio_gpio5__core__i \gpio_gpio5__core__i - connect \gpio_gpio5__core__o \gpio_gpio5__core__o - connect \gpio_gpio5__core__oe \gpio_gpio5__core__oe - connect \gpio_gpio5__pad__i \gpio_gpio5__pad__i - connect \gpio_gpio5__pad__o \gpio_gpio5__pad__o - connect \gpio_gpio5__pad__oe \gpio_gpio5__pad__oe - connect \gpio_gpio6__core__i \gpio_gpio6__core__i - connect \gpio_gpio6__core__o \gpio_gpio6__core__o - connect \gpio_gpio6__core__oe \gpio_gpio6__core__oe - connect \gpio_gpio6__pad__i \gpio_gpio6__pad__i - connect \gpio_gpio6__pad__o \gpio_gpio6__pad__o - connect \gpio_gpio6__pad__oe \gpio_gpio6__pad__oe - connect \gpio_gpio7__core__i \gpio_gpio7__core__i - connect \gpio_gpio7__core__o \gpio_gpio7__core__o - connect \gpio_gpio7__core__oe \gpio_gpio7__core__oe - connect \gpio_gpio7__pad__i \gpio_gpio7__pad__i - connect \gpio_gpio7__pad__o \gpio_gpio7__pad__o - connect \gpio_gpio7__pad__oe \gpio_gpio7__pad__oe - connect \gpio_gpio8__core__i \gpio_gpio8__core__i - connect \gpio_gpio8__core__o \gpio_gpio8__core__o - connect \gpio_gpio8__core__oe \gpio_gpio8__core__oe - connect \gpio_gpio8__pad__i \gpio_gpio8__pad__i - connect \gpio_gpio8__pad__o \gpio_gpio8__pad__o - connect \gpio_gpio8__pad__oe \gpio_gpio8__pad__oe - connect \gpio_gpio9__core__i \gpio_gpio9__core__i - connect \gpio_gpio9__core__o \gpio_gpio9__core__o - connect \gpio_gpio9__core__oe \gpio_gpio9__core__oe - connect \gpio_gpio9__pad__i \gpio_gpio9__pad__i - connect \gpio_gpio9__pad__o \gpio_gpio9__pad__o - connect \gpio_gpio9__pad__oe \gpio_gpio9__pad__oe - connect \intclk_clk \intclk_clk - connect \intclk_rst \intclk_rst - connect \jtag_wb__ack \jtag_wb__ack - connect \jtag_wb__adr \jtag_wb__adr - connect \jtag_wb__cyc \jtag_wb__cyc - connect \jtag_wb__dat_r \jtag_wb__dat_r - connect \jtag_wb__dat_w \jtag_wb__dat_w - connect \jtag_wb__sel \jtag_wb__sel - connect \jtag_wb__stb \jtag_wb__stb - connect \jtag_wb__we \jtag_wb__we - connect \uart_rx__core__i \uart_rx__core__i - connect \uart_rx__pad__i \uart_rx__pad__i - connect \uart_tx__core__o \uart_tx__core__o - connect \uart_tx__pad__o \uart_tx__pad__o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:49148.12-49162.4" - cell \xics_icp \xics_icp - connect \core_irq_o \xics_icp_core_irq_o - connect \icp_wb__ack \icp_wb__ack - connect \icp_wb__adr \icp_wb__adr - connect \icp_wb__cyc \icp_wb__cyc - connect \icp_wb__dat_r \icp_wb__dat_r - connect \icp_wb__dat_w \icp_wb__dat_w - connect \icp_wb__sel \icp_wb__sel - connect \icp_wb__stb \icp_wb__stb - connect \icp_wb__we \icp_wb__we - connect \ics_i_pri \xics_icp_ics_i_pri - connect \ics_i_src \xics_icp_ics_i_src - connect \intclk_clk \intclk_clk - connect \intclk_rst \intclk_rst - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:49163.12-49176.4" - cell \xics_ics \xics_ics - connect \icp_o_pri \xics_ics_icp_o_pri - connect \icp_o_src \xics_ics_icp_o_src - connect \ics_wb__ack \ics_wb__ack - connect \ics_wb__adr \ics_wb__adr - connect \ics_wb__cyc \ics_wb__cyc - connect \ics_wb__dat_r \ics_wb__dat_r - connect \ics_wb__dat_w \ics_wb__dat_w - connect \ics_wb__stb \ics_wb__stb - connect \ics_wb__we \ics_wb__we - connect \int_level_i \int_level_i - connect \intclk_clk \intclk_clk - connect \intclk_rst \intclk_rst - end - attribute \src "libresoc.v:47126.7-47126.20" - process $proc$libresoc.v:47126$1944 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:47256.7-47256.25" - process $proc$libresoc.v:47256$1945 - assign { } { } - assign $1\bigendian_i[0:0] 1'0 - sync always - sync init - update \bigendian_i $1\bigendian_i[0:0] - end - attribute \src "libresoc.v:47266.13-47266.33" - process $proc$libresoc.v:47266$1946 - assign { } { } - assign $1\core_asmcode[7:0] 8'00000000 - sync always - sync init - update \core_asmcode $1\core_asmcode[7:0] - end - attribute \src "libresoc.v:47272.14-47272.50" - process $proc$libresoc.v:47272$1947 - assign { } { } - assign $1\core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \core_core_cia $1\core_core_cia[63:0] - end - attribute \src "libresoc.v:47276.13-47276.36" - process $proc$libresoc.v:47276$1948 - assign { } { } - assign $1\core_core_cr_rd[7:0] 8'00000000 - sync always - sync init - update \core_core_cr_rd $1\core_core_cr_rd[7:0] - end - attribute \src "libresoc.v:47280.7-47280.32" - process $proc$libresoc.v:47280$1949 - assign { } { } - assign $1\core_core_cr_rd_ok[0:0] 1'0 - sync always - sync init - update \core_core_cr_rd_ok $1\core_core_cr_rd_ok[0:0] - end - attribute \src "libresoc.v:47284.13-47284.36" - process $proc$libresoc.v:47284$1950 - assign { } { } - assign $1\core_core_cr_wr[7:0] 8'00000000 - sync always - sync init - update \core_core_cr_wr $1\core_core_cr_wr[7:0] - end - attribute \src "libresoc.v:47288.7-47288.32" - process $proc$libresoc.v:47288$1951 - assign { } { } - assign $1\core_core_cr_wr_ok[0:0] 1'0 - sync always - sync init - update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] - end - attribute \src "libresoc.v:47305.14-47305.41" - process $proc$libresoc.v:47305$1952 - assign { } { } - assign $1\core_core_fn_unit[11:0] 12'000000000000 - sync always - sync init - update \core_core_fn_unit $1\core_core_fn_unit[11:0] - end - attribute \src "libresoc.v:47313.13-47313.41" - process $proc$libresoc.v:47313$1953 - assign { } { } - assign $1\core_core_input_carry[1:0] 2'00 - sync always - sync init - update \core_core_input_carry $1\core_core_input_carry[1:0] - end - attribute \src "libresoc.v:47317.14-47317.36" - process $proc$libresoc.v:47317$1954 - assign { } { } - assign $1\core_core_insn[31:0] 0 - sync always - sync init - update \core_core_insn $1\core_core_insn[31:0] - end - attribute \src "libresoc.v:47395.13-47395.40" - process $proc$libresoc.v:47395$1955 - assign { } { } - assign $1\core_core_insn_type[6:0] 7'0000000 - sync always - sync init - update \core_core_insn_type $1\core_core_insn_type[6:0] - end - attribute \src "libresoc.v:47399.7-47399.32" - process $proc$libresoc.v:47399$1956 - assign { } { } - assign $1\core_core_is_32bit[0:0] 1'0 - sync always - sync init - update \core_core_is_32bit $1\core_core_is_32bit[0:0] - end - attribute \src "libresoc.v:47403.7-47403.26" - process $proc$libresoc.v:47403$1957 - assign { } { } - assign $1\core_core_lk[0:0] 1'0 - sync always - sync init - update \core_core_lk $1\core_core_lk[0:0] - end - attribute \src "libresoc.v:47407.14-47407.50" - process $proc$libresoc.v:47407$1958 - assign { } { } - assign $1\core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \core_core_msr $1\core_core_msr[63:0] - end - attribute \src "libresoc.v:47411.7-47411.26" - process $proc$libresoc.v:47411$1959 - assign { } { } - assign $1\core_core_oe[0:0] 1'0 - sync always - sync init - update \core_core_oe $1\core_core_oe[0:0] - end - attribute \src "libresoc.v:47415.7-47415.29" - process $proc$libresoc.v:47415$1960 - assign { } { } - assign $1\core_core_oe_ok[0:0] 1'0 - sync always - sync init - update \core_core_oe_ok $1\core_core_oe_ok[0:0] - end - attribute \src "libresoc.v:47419.7-47419.26" - process $proc$libresoc.v:47419$1961 - assign { } { } - assign $1\core_core_rc[0:0] 1'0 - sync always - sync init - update \core_core_rc $1\core_core_rc[0:0] - end - attribute \src "libresoc.v:47423.7-47423.29" - process $proc$libresoc.v:47423$1962 - assign { } { } - assign $1\core_core_rc_ok[0:0] 1'0 - sync always - sync init - update \core_core_rc_ok $1\core_core_rc_ok[0:0] - end - attribute \src "libresoc.v:47427.14-47427.43" - process $proc$libresoc.v:47427$1963 - assign { } { } - assign $1\core_core_trapaddr[12:0] 13'0000000000000 - sync always - sync init - update \core_core_trapaddr $1\core_core_trapaddr[12:0] - end - attribute \src "libresoc.v:47431.13-47431.39" - process $proc$libresoc.v:47431$1964 - assign { } { } - assign $1\core_core_traptype[6:0] 7'0000000 - sync always - sync init - update \core_core_traptype $1\core_core_traptype[6:0] - end - attribute \src "libresoc.v:47435.13-47435.31" - process $proc$libresoc.v:47435$1965 - assign { } { } - assign $1\core_cr_in1[2:0] 3'000 - sync always - sync init - update \core_cr_in1 $1\core_cr_in1[2:0] - end - attribute \src "libresoc.v:47439.7-47439.28" - process $proc$libresoc.v:47439$1966 - assign { } { } - assign $1\core_cr_in1_ok[0:0] 1'0 - sync always - sync init - update \core_cr_in1_ok $1\core_cr_in1_ok[0:0] - end - attribute \src "libresoc.v:47443.13-47443.31" - process $proc$libresoc.v:47443$1967 - assign { } { } - assign $1\core_cr_in2[2:0] 3'000 - sync always - sync init - update \core_cr_in2 $1\core_cr_in2[2:0] - end - attribute \src "libresoc.v:47445.13-47445.36" - process $proc$libresoc.v:47445$1968 - assign { } { } - assign $0\core_cr_in2$39[2:0]$1969 3'000 - sync always - sync init - update \core_cr_in2$39 $0\core_cr_in2$39[2:0]$1969 - end - attribute \src "libresoc.v:47451.7-47451.28" - process $proc$libresoc.v:47451$1970 - assign { } { } - assign $1\core_cr_in2_ok[0:0] 1'0 - sync always - sync init - update \core_cr_in2_ok $1\core_cr_in2_ok[0:0] - end - attribute \src "libresoc.v:47453.7-47453.33" - process $proc$libresoc.v:47453$1971 - assign { } { } - assign $0\core_cr_in2_ok$40[0:0]$1972 1'0 - sync always - sync init - update \core_cr_in2_ok$40 $0\core_cr_in2_ok$40[0:0]$1972 - end - attribute \src "libresoc.v:47459.13-47459.31" - process $proc$libresoc.v:47459$1973 - assign { } { } - assign $1\core_cr_out[2:0] 3'000 - sync always - sync init - update \core_cr_out $1\core_cr_out[2:0] - end - attribute \src "libresoc.v:47463.7-47463.28" - process $proc$libresoc.v:47463$1974 - assign { } { } - assign $1\core_cr_out_ok[0:0] 1'0 - sync always - sync init - update \core_cr_out_ok $1\core_cr_out_ok[0:0] - end - attribute \src "libresoc.v:47467.14-47467.45" - process $proc$libresoc.v:47467$1975 - assign { } { } - assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \core_dec $1\core_dec[63:0] - end - attribute \src "libresoc.v:47471.13-47471.28" - process $proc$libresoc.v:47471$1976 - assign { } { } - assign $1\core_ea[4:0] 5'00000 - sync always - sync init - update \core_ea $1\core_ea[4:0] - end - attribute \src "libresoc.v:47475.7-47475.24" - process $proc$libresoc.v:47475$1977 - assign { } { } - assign $1\core_ea_ok[0:0] 1'0 - sync always - sync init - update \core_ea_ok $1\core_ea_ok[0:0] - end - attribute \src "libresoc.v:47479.7-47479.23" - process $proc$libresoc.v:47479$1978 - assign { } { } - assign $1\core_eint[0:0] 1'0 - sync always - sync init - update \core_eint $1\core_eint[0:0] - end - attribute \src "libresoc.v:47483.13-47483.30" - process $proc$libresoc.v:47483$1979 - assign { } { } - assign $1\core_fast1[2:0] 3'000 - sync always - sync init - update \core_fast1 $1\core_fast1[2:0] - end - attribute \src "libresoc.v:47487.7-47487.27" - process $proc$libresoc.v:47487$1980 - assign { } { } - assign $1\core_fast1_ok[0:0] 1'0 - sync always - sync init - update \core_fast1_ok $1\core_fast1_ok[0:0] - end - attribute \src "libresoc.v:47491.13-47491.30" - process $proc$libresoc.v:47491$1981 - assign { } { } - assign $1\core_fast2[2:0] 3'000 - sync always - sync init - update \core_fast2 $1\core_fast2[2:0] - end - attribute \src "libresoc.v:47495.7-47495.27" - process $proc$libresoc.v:47495$1982 - assign { } { } - assign $1\core_fast2_ok[0:0] 1'0 - sync always - sync init - update \core_fast2_ok $1\core_fast2_ok[0:0] - end - attribute \src "libresoc.v:47499.13-47499.31" - process $proc$libresoc.v:47499$1983 - assign { } { } - assign $1\core_fasto1[2:0] 3'000 - sync always - sync init - update \core_fasto1 $1\core_fasto1[2:0] - end - attribute \src "libresoc.v:47503.7-47503.28" - process $proc$libresoc.v:47503$1984 - assign { } { } - assign $1\core_fasto1_ok[0:0] 1'0 - sync always - sync init - update \core_fasto1_ok $1\core_fasto1_ok[0:0] - end - attribute \src "libresoc.v:47507.13-47507.31" - process $proc$libresoc.v:47507$1985 - assign { } { } - assign $1\core_fasto2[2:0] 3'000 - sync always - sync init - update \core_fasto2 $1\core_fasto2[2:0] - end - attribute \src "libresoc.v:47511.7-47511.28" - process $proc$libresoc.v:47511$1986 - assign { } { } - assign $1\core_fasto2_ok[0:0] 1'0 - sync always - sync init - update \core_fasto2_ok $1\core_fasto2_ok[0:0] - end - attribute \src "libresoc.v:47515.14-47515.45" - process $proc$libresoc.v:47515$1987 - assign { } { } - assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \core_msr $1\core_msr[63:0] - end - attribute \src "libresoc.v:47519.14-47519.44" - process $proc$libresoc.v:47519$1988 - assign { } { } - assign $1\core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \core_pc $1\core_pc[63:0] - end - attribute \src "libresoc.v:47523.13-47523.30" - process $proc$libresoc.v:47523$1989 - assign { } { } - assign $1\core_reg1[4:0] 5'00000 - sync always - sync init - update \core_reg1 $1\core_reg1[4:0] - end - attribute \src "libresoc.v:47527.7-47527.26" - process $proc$libresoc.v:47527$1990 - assign { } { } - assign $1\core_reg1_ok[0:0] 1'0 - sync always - sync init - update \core_reg1_ok $1\core_reg1_ok[0:0] - end - attribute \src "libresoc.v:47531.13-47531.30" - process $proc$libresoc.v:47531$1991 - assign { } { } - assign $1\core_reg2[4:0] 5'00000 - sync always - sync init - update \core_reg2 $1\core_reg2[4:0] - end - attribute \src "libresoc.v:47535.7-47535.26" - process $proc$libresoc.v:47535$1992 - assign { } { } - assign $1\core_reg2_ok[0:0] 1'0 - sync always - sync init - update \core_reg2_ok $1\core_reg2_ok[0:0] - end - attribute \src "libresoc.v:47539.13-47539.30" - process $proc$libresoc.v:47539$1993 - assign { } { } - assign $1\core_reg3[4:0] 5'00000 - sync always - sync init - update \core_reg3 $1\core_reg3[4:0] - end - attribute \src "libresoc.v:47543.7-47543.26" - process $proc$libresoc.v:47543$1994 - assign { } { } - assign $1\core_reg3_ok[0:0] 1'0 - sync always - sync init - update \core_reg3_ok $1\core_reg3_ok[0:0] - end - attribute \src "libresoc.v:47547.13-47547.30" - process $proc$libresoc.v:47547$1995 - assign { } { } - assign $1\core_rego[4:0] 5'00000 - sync always - sync init - update \core_rego $1\core_rego[4:0] - end - attribute \src "libresoc.v:47551.7-47551.26" - process $proc$libresoc.v:47551$1996 - assign { } { } - assign $1\core_rego_ok[0:0] 1'0 - sync always - sync init - update \core_rego_ok $1\core_rego_ok[0:0] - end - attribute \src "libresoc.v:47668.13-47668.32" - process $proc$libresoc.v:47668$1997 - assign { } { } - assign $1\core_spr1[9:0] 10'0000000000 - sync always - sync init - update \core_spr1 $1\core_spr1[9:0] - end - attribute \src "libresoc.v:47672.7-47672.26" - process $proc$libresoc.v:47672$1998 - assign { } { } - assign $1\core_spr1_ok[0:0] 1'0 - sync always - sync init - update \core_spr1_ok $1\core_spr1_ok[0:0] - end - attribute \src "libresoc.v:47787.13-47787.32" - process $proc$libresoc.v:47787$1999 - assign { } { } - assign $1\core_spro[9:0] 10'0000000000 - sync always - sync init - update \core_spro $1\core_spro[9:0] - end - attribute \src "libresoc.v:47791.7-47791.26" - process $proc$libresoc.v:47791$2000 - assign { } { } - assign $1\core_spro_ok[0:0] 1'0 - sync always - sync init - update \core_spro_ok $1\core_spro_ok[0:0] - end - attribute \src "libresoc.v:47799.13-47799.31" - process $proc$libresoc.v:47799$2001 - assign { } { } - assign $1\core_xer_in[2:0] 3'000 - sync always - sync init - update \core_xer_in $1\core_xer_in[2:0] - end - attribute \src "libresoc.v:47803.7-47803.26" - process $proc$libresoc.v:47803$2002 - assign { } { } - assign $1\core_xer_out[0:0] 1'0 - sync always - sync init - update \core_xer_out $1\core_xer_out[0:0] - end - attribute \src "libresoc.v:47819.7-47819.30" - process $proc$libresoc.v:47819$2003 - assign { } { } - assign $1\cu_st__rel_o_dly[0:0] 1'0 - sync always - sync init - update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] - end - attribute \src "libresoc.v:47825.7-47825.24" - process $proc$libresoc.v:47825$2004 - assign { } { } - assign $1\d_cr_delay[0:0] 1'0 - sync always - sync init - update \d_cr_delay $1\d_cr_delay[0:0] - end - attribute \src "libresoc.v:47829.7-47829.25" - process $proc$libresoc.v:47829$2005 - assign { } { } - assign $1\d_reg_delay[0:0] 1'0 - sync always - sync init - update \d_reg_delay $1\d_reg_delay[0:0] - end - attribute \src "libresoc.v:47833.7-47833.25" - process $proc$libresoc.v:47833$2006 - assign { } { } - assign $1\d_xer_delay[0:0] 1'0 - sync always - sync init - update \d_xer_delay $1\d_xer_delay[0:0] - end - attribute \src "libresoc.v:47871.13-47871.34" - process $proc$libresoc.v:47871$2007 - assign { } { } - assign $1\dbg_dmi_addr_i[3:0] 4'0000 - sync always - sync init - update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] - end - attribute \src "libresoc.v:47875.14-47875.48" - process $proc$libresoc.v:47875$2008 - assign { } { } - assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dbg_dmi_din $1\dbg_dmi_din[63:0] - end - attribute \src "libresoc.v:47881.7-47881.27" - process $proc$libresoc.v:47881$2009 - assign { } { } - assign $1\dbg_dmi_req_i[0:0] 1'0 - sync always - sync init - update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] - end - attribute \src "libresoc.v:47885.7-47885.26" - process $proc$libresoc.v:47885$2010 - assign { } { } - assign $1\dbg_dmi_we_i[0:0] 1'0 - sync always - sync init - update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] - end - attribute \src "libresoc.v:47921.14-47921.49" - process $proc$libresoc.v:47921$2011 - assign { } { } - assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dec2_cur_dec $1\dec2_cur_dec[63:0] - end - attribute \src "libresoc.v:47925.7-47925.27" - process $proc$libresoc.v:47925$2012 - assign { } { } - assign $1\dec2_cur_eint[0:0] 1'0 - sync always - sync init - update \dec2_cur_eint $1\dec2_cur_eint[0:0] - end - attribute \src "libresoc.v:47929.14-47929.49" - process $proc$libresoc.v:47929$2013 - assign { } { } - assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dec2_cur_msr $1\dec2_cur_msr[63:0] - end - attribute \src "libresoc.v:47933.14-47933.48" - process $proc$libresoc.v:47933$2014 - assign { } { } - assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dec2_cur_pc $1\dec2_cur_pc[63:0] - end - attribute \src "libresoc.v:48326.13-48326.25" - process $proc$libresoc.v:48326$2015 - assign { } { } - assign $1\delay[1:0] 2'11 - sync always - sync init - update \delay $1\delay[1:0] - end - attribute \src "libresoc.v:48336.13-48336.29" - process $proc$libresoc.v:48336$2016 - assign { } { } - assign $1\fsm_state[1:0] 2'00 - sync always - sync init - update \fsm_state $1\fsm_state[1:0] - end - attribute \src "libresoc.v:48338.13-48338.35" - process $proc$libresoc.v:48338$2017 - assign { } { } - assign $0\fsm_state$115[1:0]$2018 2'00 - sync always - sync init - update \fsm_state$115 $0\fsm_state$115[1:0]$2018 - end - attribute \src "libresoc.v:48588.14-48588.28" - process $proc$libresoc.v:48588$2019 - assign { } { } - assign $1\ilatch[31:0] 0 - sync always - sync init - update \ilatch $1\ilatch[31:0] - end - attribute \src "libresoc.v:48624.7-48624.29" - process $proc$libresoc.v:48624$2020 - assign { } { } - assign $1\jtag_dmi0_ack_o[0:0] 1'0 - sync always - sync init - update \jtag_dmi0_ack_o $1\jtag_dmi0_ack_o[0:0] - end - attribute \src "libresoc.v:48632.14-48632.51" - process $proc$libresoc.v:48632$2021 - assign { } { } - assign $1\jtag_dmi0_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \jtag_dmi0_dout $1\jtag_dmi0_dout[63:0] - end - attribute \src "libresoc.v:48660.7-48660.22" - process $proc$libresoc.v:48660$2022 - assign { } { } - assign $1\msr_read[0:0] 1'1 - sync always - sync init - update \msr_read $1\msr_read[0:0] - end - attribute \src "libresoc.v:48672.7-48672.24" - process $proc$libresoc.v:48672$2023 - assign { } { } - assign $1\pc_changed[0:0] 1'0 - sync always - sync init - update \pc_changed $1\pc_changed[0:0] - end - attribute \src "libresoc.v:48682.7-48682.25" - process $proc$libresoc.v:48682$2024 - assign { } { } - assign $1\pc_ok_delay[0:0] 1'0 - sync always - sync init - update \pc_ok_delay $1\pc_ok_delay[0:0] - end - attribute \src "libresoc.v:48688.14-48688.32" - process $proc$libresoc.v:48688$2025 - assign { } { } - assign $1\raw_insn_i[31:0] 0 - sync always - sync init - update \raw_insn_i $1\raw_insn_i[31:0] - end - attribute \src "libresoc.v:48769.3-48770.39" - process $proc$libresoc.v:48769$1501 - assign { } { } - assign $0\d_reg_delay[0:0] \d_reg_delay$next - sync posedge \intclk_clk - update \d_reg_delay $0\d_reg_delay[0:0] - end - attribute \src "libresoc.v:48771.3-48772.29" - process $proc$libresoc.v:48771$1502 - assign { } { } - assign $0\ilatch[31:0] \ilatch$next - sync posedge \intclk_clk - update \ilatch $0\ilatch[31:0] - end - attribute \src "libresoc.v:48773.3-48774.31" - process $proc$libresoc.v:48773$1503 - assign { } { } - assign $0\core_pc[63:0] \core_pc$next - sync posedge \intclk_clk - update \core_pc $0\core_pc[63:0] - end - attribute \src "libresoc.v:48775.3-48776.33" - process $proc$libresoc.v:48775$1504 - assign { } { } - assign $0\core_msr[63:0] \core_msr$next - sync posedge \intclk_clk - update \core_msr $0\core_msr[63:0] - end - attribute \src "libresoc.v:48777.3-48778.35" - process $proc$libresoc.v:48777$1505 - assign { } { } - assign $0\core_eint[0:0] \core_eint$next - sync posedge \intclk_clk - update \core_eint $0\core_eint[0:0] - end - attribute \src "libresoc.v:48779.3-48780.33" - process $proc$libresoc.v:48779$1506 - assign { } { } - assign $0\core_dec[63:0] \core_dec$next - sync posedge \intclk_clk - update \core_dec $0\core_dec[63:0] - end - attribute \src "libresoc.v:48781.3-48782.41" - process $proc$libresoc.v:48781$1507 - assign { } { } - assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next - sync posedge \intclk_clk - update \dec2_cur_msr $0\dec2_cur_msr[63:0] - end - attribute \src "libresoc.v:48783.3-48784.35" - process $proc$libresoc.v:48783$1508 - assign { } { } - assign $0\fsm_state[1:0] \fsm_state$next - sync posedge \intclk_clk - update \fsm_state $0\fsm_state[1:0] - end - attribute \src "libresoc.v:48785.3-48786.33" - process $proc$libresoc.v:48785$1509 - assign { } { } - assign $0\msr_read[0:0] \msr_read$next - sync posedge \intclk_clk - update \msr_read $0\msr_read[0:0] - end - attribute \src "libresoc.v:48787.3-48788.39" - process $proc$libresoc.v:48787$1510 - assign { } { } - assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next - sync posedge \intclk_clk - update \dec2_cur_pc $0\dec2_cur_pc[63:0] - end - attribute \src "libresoc.v:48789.3-48790.39" - process $proc$libresoc.v:48789$1511 - assign { } { } - assign $0\bigendian_i[0:0] \bigendian_i$next - sync posedge \intclk_clk - update \bigendian_i $0\bigendian_i[0:0] - end - attribute \src "libresoc.v:48791.3-48792.37" - process $proc$libresoc.v:48791$1512 - assign { } { } - assign $0\raw_insn_i[31:0] \raw_insn_i$next - sync posedge \intclk_clk - update \raw_insn_i $0\raw_insn_i[31:0] - end - attribute \src "libresoc.v:48793.3-48794.41" - process $proc$libresoc.v:48793$1513 - assign { } { } - assign $0\core_asmcode[7:0] \core_asmcode$next - sync posedge \intclk_clk - update \core_asmcode $0\core_asmcode[7:0] - end - attribute \src "libresoc.v:48795.3-48796.35" - process $proc$libresoc.v:48795$1514 - assign { } { } - assign $0\core_rego[4:0] \core_rego$next - sync posedge \intclk_clk - update \core_rego $0\core_rego[4:0] - end - attribute \src "libresoc.v:48797.3-48798.41" - process $proc$libresoc.v:48797$1515 - assign { } { } - assign $0\core_rego_ok[0:0] \core_rego_ok$next - sync posedge \intclk_clk - update \core_rego_ok $0\core_rego_ok[0:0] - end - attribute \src "libresoc.v:48799.3-48800.31" - process $proc$libresoc.v:48799$1516 - assign { } { } - assign $0\core_ea[4:0] \core_ea$next - sync posedge \intclk_clk - update \core_ea $0\core_ea[4:0] - end - attribute \src "libresoc.v:48801.3-48802.37" - process $proc$libresoc.v:48801$1517 - assign { } { } - assign $0\core_ea_ok[0:0] \core_ea_ok$next - sync posedge \intclk_clk - update \core_ea_ok $0\core_ea_ok[0:0] - end - attribute \src "libresoc.v:48803.3-48804.35" - process $proc$libresoc.v:48803$1518 - assign { } { } - assign $0\core_reg1[4:0] \core_reg1$next - sync posedge \intclk_clk - update \core_reg1 $0\core_reg1[4:0] - end - attribute \src "libresoc.v:48805.3-48806.41" - process $proc$libresoc.v:48805$1519 - assign { } { } - assign $0\core_reg1_ok[0:0] \core_reg1_ok$next - sync posedge \intclk_clk - update \core_reg1_ok $0\core_reg1_ok[0:0] - end - attribute \src "libresoc.v:48807.3-48808.35" - process $proc$libresoc.v:48807$1520 - assign { } { } - assign $0\core_reg2[4:0] \core_reg2$next - sync posedge \intclk_clk - update \core_reg2 $0\core_reg2[4:0] - end - attribute \src "libresoc.v:48809.3-48810.41" - process $proc$libresoc.v:48809$1521 - assign { } { } - assign $0\core_reg2_ok[0:0] \core_reg2_ok$next - sync posedge \intclk_clk - update \core_reg2_ok $0\core_reg2_ok[0:0] - end - attribute \src "libresoc.v:48811.3-48812.35" - process $proc$libresoc.v:48811$1522 - assign { } { } - assign $0\core_reg3[4:0] \core_reg3$next - sync posedge \intclk_clk - update \core_reg3 $0\core_reg3[4:0] - end - attribute \src "libresoc.v:48813.3-48814.41" - process $proc$libresoc.v:48813$1523 - assign { } { } - assign $0\core_reg3_ok[0:0] \core_reg3_ok$next - sync posedge \intclk_clk - update \core_reg3_ok $0\core_reg3_ok[0:0] - end - attribute \src "libresoc.v:48815.3-48816.35" - process $proc$libresoc.v:48815$1524 - assign { } { } - assign $0\core_spro[9:0] \core_spro$next - sync posedge \intclk_clk - update \core_spro $0\core_spro[9:0] - end - attribute \src "libresoc.v:48817.3-48818.41" - process $proc$libresoc.v:48817$1525 - assign { } { } - assign $0\core_spro_ok[0:0] \core_spro_ok$next - sync posedge \intclk_clk - update \core_spro_ok $0\core_spro_ok[0:0] - end - attribute \src "libresoc.v:48819.3-48820.35" - process $proc$libresoc.v:48819$1526 - assign { } { } - assign $0\core_spr1[9:0] \core_spr1$next - sync posedge \intclk_clk - update \core_spr1 $0\core_spr1[9:0] - end - attribute \src "libresoc.v:48821.3-48822.41" - process $proc$libresoc.v:48821$1527 - assign { } { } - assign $0\core_spr1_ok[0:0] \core_spr1_ok$next - sync posedge \intclk_clk - update \core_spr1_ok $0\core_spr1_ok[0:0] - end - attribute \src "libresoc.v:48823.3-48824.39" - process $proc$libresoc.v:48823$1528 - assign { } { } - assign $0\core_xer_in[2:0] \core_xer_in$next - sync posedge \intclk_clk - update \core_xer_in $0\core_xer_in[2:0] - end - attribute \src "libresoc.v:48825.3-48826.41" - process $proc$libresoc.v:48825$1529 - assign { } { } - assign $0\core_xer_out[0:0] \core_xer_out$next - sync posedge \intclk_clk - update \core_xer_out $0\core_xer_out[0:0] - end - attribute \src "libresoc.v:48827.3-48828.37" - process $proc$libresoc.v:48827$1530 - assign { } { } - assign $0\core_fast1[2:0] \core_fast1$next - sync posedge \intclk_clk - update \core_fast1 $0\core_fast1[2:0] - end - attribute \src "libresoc.v:48829.3-48830.43" - process $proc$libresoc.v:48829$1531 - assign { } { } - assign $0\core_fast1_ok[0:0] \core_fast1_ok$next - sync posedge \intclk_clk - update \core_fast1_ok $0\core_fast1_ok[0:0] - end - attribute \src "libresoc.v:48831.3-48832.37" - process $proc$libresoc.v:48831$1532 - assign { } { } - assign $0\core_fast2[2:0] \core_fast2$next - sync posedge \intclk_clk - update \core_fast2 $0\core_fast2[2:0] - end - attribute \src "libresoc.v:48833.3-48834.43" - process $proc$libresoc.v:48833$1533 - assign { } { } - assign $0\core_fast2_ok[0:0] \core_fast2_ok$next - sync posedge \intclk_clk - update \core_fast2_ok $0\core_fast2_ok[0:0] - end - attribute \src "libresoc.v:48835.3-48836.39" - process $proc$libresoc.v:48835$1534 - assign { } { } - assign $0\core_fasto1[2:0] \core_fasto1$next - sync posedge \intclk_clk - update \core_fasto1 $0\core_fasto1[2:0] - end - attribute \src "libresoc.v:48837.3-48838.45" - process $proc$libresoc.v:48837$1535 - assign { } { } - assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next - sync posedge \intclk_clk - update \core_fasto1_ok $0\core_fasto1_ok[0:0] - end - attribute \src "libresoc.v:48839.3-48840.39" - process $proc$libresoc.v:48839$1536 - assign { } { } - assign $0\core_fasto2[2:0] \core_fasto2$next - sync posedge \intclk_clk - update \core_fasto2 $0\core_fasto2[2:0] - end - attribute \src "libresoc.v:48841.3-48842.45" - process $proc$libresoc.v:48841$1537 - assign { } { } - assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next - sync posedge \intclk_clk - update \core_fasto2_ok $0\core_fasto2_ok[0:0] - end - attribute \src "libresoc.v:48843.3-48844.39" - process $proc$libresoc.v:48843$1538 - assign { } { } - assign $0\core_cr_in1[2:0] \core_cr_in1$next - sync posedge \intclk_clk - update \core_cr_in1 $0\core_cr_in1[2:0] - end - attribute \src "libresoc.v:48845.3-48846.45" - process $proc$libresoc.v:48845$1539 - assign { } { } - assign $0\core_cr_in1_ok[0:0] \core_cr_in1_ok$next - sync posedge \intclk_clk - update \core_cr_in1_ok $0\core_cr_in1_ok[0:0] - end - attribute \src "libresoc.v:48847.3-48848.39" - process $proc$libresoc.v:48847$1540 - assign { } { } - assign $0\core_cr_in2[2:0] \core_cr_in2$next - sync posedge \intclk_clk - update \core_cr_in2 $0\core_cr_in2[2:0] - end - attribute \src "libresoc.v:48849.3-48850.45" - process $proc$libresoc.v:48849$1541 - assign { } { } - assign $0\core_cr_in2_ok[0:0] \core_cr_in2_ok$next - sync posedge \intclk_clk - update \core_cr_in2_ok $0\core_cr_in2_ok[0:0] - end - attribute \src "libresoc.v:48851.3-48852.47" - process $proc$libresoc.v:48851$1542 - assign { } { } - assign $0\core_cr_in2$39[2:0]$1543 \core_cr_in2$39$next - sync posedge \intclk_clk - update \core_cr_in2$39 $0\core_cr_in2$39[2:0]$1543 - end - attribute \src "libresoc.v:48853.3-48854.53" - process $proc$libresoc.v:48853$1544 - assign { } { } - assign $0\core_cr_in2_ok$40[0:0]$1545 \core_cr_in2_ok$40$next - sync posedge \intclk_clk - update \core_cr_in2_ok$40 $0\core_cr_in2_ok$40[0:0]$1545 - end - attribute \src "libresoc.v:48855.3-48856.39" - process $proc$libresoc.v:48855$1546 - assign { } { } - assign $0\core_cr_out[2:0] \core_cr_out$next - sync posedge \intclk_clk - update \core_cr_out $0\core_cr_out[2:0] - end - attribute \src "libresoc.v:48857.3-48858.45" - process $proc$libresoc.v:48857$1547 - assign { } { } - assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next - sync posedge \intclk_clk - update \core_cr_out_ok $0\core_cr_out_ok[0:0] - end - attribute \src "libresoc.v:48859.3-48860.43" - process $proc$libresoc.v:48859$1548 - assign { } { } - assign $0\core_core_msr[63:0] \core_core_msr$next - sync posedge \intclk_clk - update \core_core_msr $0\core_core_msr[63:0] - end - attribute \src "libresoc.v:48861.3-48862.43" - process $proc$libresoc.v:48861$1549 - assign { } { } - assign $0\core_core_cia[63:0] \core_core_cia$next - sync posedge \intclk_clk - update \core_core_cia $0\core_core_cia[63:0] - end - attribute \src "libresoc.v:48863.3-48864.45" - process $proc$libresoc.v:48863$1550 - assign { } { } - assign $0\core_core_insn[31:0] \core_core_insn$next - sync posedge \intclk_clk - update \core_core_insn $0\core_core_insn[31:0] - end - attribute \src "libresoc.v:48865.3-48866.55" - process $proc$libresoc.v:48865$1551 - assign { } { } - assign $0\core_core_insn_type[6:0] \core_core_insn_type$next - sync posedge \intclk_clk - update \core_core_insn_type $0\core_core_insn_type[6:0] - end - attribute \src "libresoc.v:48867.3-48868.51" - process $proc$libresoc.v:48867$1552 - assign { } { } - assign $0\core_core_fn_unit[11:0] \core_core_fn_unit$next - sync posedge \intclk_clk - update \core_core_fn_unit $0\core_core_fn_unit[11:0] - end - attribute \src "libresoc.v:48869.3-48870.41" - process $proc$libresoc.v:48869$1553 - assign { } { } - assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next - sync posedge \intclk_clk - update \dec2_cur_dec $0\dec2_cur_dec[63:0] - end - attribute \src "libresoc.v:48871.3-48872.41" - process $proc$libresoc.v:48871$1554 - assign { } { } - assign $0\core_core_lk[0:0] \core_core_lk$next - sync posedge \intclk_clk - update \core_core_lk $0\core_core_lk[0:0] - end - attribute \src "libresoc.v:48873.3-48874.41" - process $proc$libresoc.v:48873$1555 - assign { } { } - assign $0\core_core_rc[0:0] \core_core_rc$next - sync posedge \intclk_clk - update \core_core_rc $0\core_core_rc[0:0] - end - attribute \src "libresoc.v:48875.3-48876.47" - process $proc$libresoc.v:48875$1556 - assign { } { } - assign $0\core_core_rc_ok[0:0] \core_core_rc_ok$next - sync posedge \intclk_clk - update \core_core_rc_ok $0\core_core_rc_ok[0:0] - end - attribute \src "libresoc.v:48877.3-48878.41" - process $proc$libresoc.v:48877$1557 - assign { } { } - assign $0\core_core_oe[0:0] \core_core_oe$next - sync posedge \intclk_clk - update \core_core_oe $0\core_core_oe[0:0] - end - attribute \src "libresoc.v:48879.3-48880.47" - process $proc$libresoc.v:48879$1558 - assign { } { } - assign $0\core_core_oe_ok[0:0] \core_core_oe_ok$next - sync posedge \intclk_clk - update \core_core_oe_ok $0\core_core_oe_ok[0:0] - end - attribute \src "libresoc.v:48881.3-48882.59" - process $proc$libresoc.v:48881$1559 - assign { } { } - assign $0\core_core_input_carry[1:0] \core_core_input_carry$next - sync posedge \intclk_clk - update \core_core_input_carry $0\core_core_input_carry[1:0] - end - attribute \src "libresoc.v:48883.3-48884.53" - process $proc$libresoc.v:48883$1560 - assign { } { } - assign $0\core_core_traptype[6:0] \core_core_traptype$next - sync posedge \intclk_clk - update \core_core_traptype $0\core_core_traptype[6:0] - end - attribute \src "libresoc.v:48885.3-48886.53" - process $proc$libresoc.v:48885$1561 - assign { } { } - assign $0\core_core_trapaddr[12:0] \core_core_trapaddr$next - sync posedge \intclk_clk - update \core_core_trapaddr $0\core_core_trapaddr[12:0] - end - attribute \src "libresoc.v:48887.3-48888.47" - process $proc$libresoc.v:48887$1562 - assign { } { } - assign $0\core_core_cr_rd[7:0] \core_core_cr_rd$next - sync posedge \intclk_clk - update \core_core_cr_rd $0\core_core_cr_rd[7:0] - end - attribute \src "libresoc.v:48889.3-48890.53" - process $proc$libresoc.v:48889$1563 - assign { } { } - assign $0\core_core_cr_rd_ok[0:0] \core_core_cr_rd_ok$next - sync posedge \intclk_clk - update \core_core_cr_rd_ok $0\core_core_cr_rd_ok[0:0] - end - attribute \src "libresoc.v:48891.3-48892.45" - process $proc$libresoc.v:48891$1564 - assign { } { } - assign $0\fsm_state$115[1:0]$1565 \fsm_state$115$next - sync posedge \intclk_clk - update \fsm_state$115 $0\fsm_state$115[1:0]$1565 - end - attribute \src "libresoc.v:48893.3-48894.47" - process $proc$libresoc.v:48893$1566 - assign { } { } - assign $0\core_core_cr_wr[7:0] \core_core_cr_wr$next - sync posedge \intclk_clk - update \core_core_cr_wr $0\core_core_cr_wr[7:0] - end - attribute \src "libresoc.v:48895.3-48896.53" - process $proc$libresoc.v:48895$1567 - assign { } { } - assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next - sync posedge \intclk_clk - update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] - end - attribute \src "libresoc.v:48897.3-48898.53" - process $proc$libresoc.v:48897$1568 - assign { } { } - assign $0\core_core_is_32bit[0:0] \core_core_is_32bit$next - sync posedge \intclk_clk - update \core_core_is_32bit $0\core_core_is_32bit[0:0] - end - attribute \src "libresoc.v:48899.3-48900.37" - process $proc$libresoc.v:48899$1569 - assign { } { } - assign $0\pc_changed[0:0] \pc_changed$next - sync posedge \intclk_clk - update \pc_changed $0\pc_changed[0:0] - end - attribute \src "libresoc.v:48901.3-48902.39" - process $proc$libresoc.v:48901$1570 - assign { } { } - assign $0\pc_ok_delay[0:0] \pc_ok_delay$next - sync posedge \intclk_clk - update \pc_ok_delay $0\pc_ok_delay[0:0] - end - attribute \src "libresoc.v:48903.3-48904.30" - process $proc$libresoc.v:48903$1571 - assign { } { } - assign $0\cu_st__rel_o_dly[0:0] 1'0 - sync posedge \intclk_clk - update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] - end - attribute \src "libresoc.v:48905.3-48906.27" - process $proc$libresoc.v:48905$1572 - assign { } { } - assign $0\delay[1:0] \delay$next - sync posedge \por_clk - update \delay $0\delay[1:0] - end - attribute \src "libresoc.v:48907.3-48908.43" - process $proc$libresoc.v:48907$1573 - assign { } { } - assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next - sync posedge \intclk_clk - update \dec2_cur_eint $0\dec2_cur_eint[0:0] - end - attribute \src "libresoc.v:48909.3-48910.45" - process $proc$libresoc.v:48909$1574 - assign { } { } - assign $0\jtag_dmi0_dout[63:0] \jtag_dmi0_dout$next - sync posedge \intclk_clk - update \jtag_dmi0_dout $0\jtag_dmi0_dout[63:0] - end - attribute \src "libresoc.v:48911.3-48912.47" - process $proc$libresoc.v:48911$1575 - assign { } { } - assign $0\jtag_dmi0_ack_o[0:0] \jtag_dmi0_ack_o$next - sync posedge \intclk_clk - update \jtag_dmi0_ack_o $0\jtag_dmi0_ack_o[0:0] - end - attribute \src "libresoc.v:48913.3-48914.39" - process $proc$libresoc.v:48913$1576 - assign { } { } - assign $0\d_xer_delay[0:0] \d_xer_delay$next - sync posedge \intclk_clk - update \d_xer_delay $0\d_xer_delay[0:0] - end - attribute \src "libresoc.v:48915.3-48916.39" - process $proc$libresoc.v:48915$1577 - assign { } { } - assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next - sync posedge \intclk_clk - update \dbg_dmi_din $0\dbg_dmi_din[63:0] - end - attribute \src "libresoc.v:48917.3-48918.41" - process $proc$libresoc.v:48917$1578 - assign { } { } - assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next - sync posedge \intclk_clk - update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] - end - attribute \src "libresoc.v:48919.3-48920.43" - process $proc$libresoc.v:48919$1579 - assign { } { } - assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next - sync posedge \intclk_clk - update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] - end - attribute \src "libresoc.v:48921.3-48922.45" - process $proc$libresoc.v:48921$1580 - assign { } { } - assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next - sync posedge \intclk_clk - update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] - end - attribute \src "libresoc.v:48923.3-48924.37" - process $proc$libresoc.v:48923$1581 - assign { } { } - assign $0\d_cr_delay[0:0] \d_cr_delay$next - sync posedge \intclk_clk - update \d_cr_delay $0\d_cr_delay[0:0] - end - attribute \src "libresoc.v:49177.3-49185.6" - process $proc$libresoc.v:49177$1582 - assign { } { } - assign { } { } - assign $0\dbg_dmi_addr_i$next[3:0]$1583 $1\dbg_dmi_addr_i$next[3:0]$1584 - attribute \src "libresoc.v:49178.5-49178.29" - switch \initial - attribute \src "libresoc.v:49178.9-49178.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbg_dmi_addr_i$next[3:0]$1584 4'0000 - case - assign $1\dbg_dmi_addr_i$next[3:0]$1584 \jtag_dmi0_addr_i - end - sync always - update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$1583 - end - attribute \src "libresoc.v:49186.3-49194.6" - process $proc$libresoc.v:49186$1585 - assign { } { } - assign { } { } - assign $0\dbg_dmi_req_i$next[0:0]$1586 $1\dbg_dmi_req_i$next[0:0]$1587 - attribute \src "libresoc.v:49187.5-49187.29" - switch \initial - attribute \src "libresoc.v:49187.9-49187.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbg_dmi_req_i$next[0:0]$1587 1'0 - case - assign $1\dbg_dmi_req_i$next[0:0]$1587 \jtag_dmi0_req_i - end - sync always - update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$1586 - end - attribute \src "libresoc.v:49195.3-49205.6" - process $proc$libresoc.v:49195$1588 - assign { } { } - assign { } { } - assign $0\issue_i[0:0] $1\issue_i[0:0] - attribute \src "libresoc.v:49196.5-49196.29" - switch \initial - attribute \src "libresoc.v:49196.9-49196.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\issue_i[0:0] 1'1 - case - assign $1\issue_i[0:0] 1'0 - end - sync always - update \issue_i $0\issue_i[0:0] - end - attribute \src "libresoc.v:49206.3-49215.6" - process $proc$libresoc.v:49206$1589 - assign { } { } - assign { } { } - assign $0\dmi__addr[4:0] $1\dmi__addr[4:0] - attribute \src "libresoc.v:49207.5-49207.29" - switch \initial - attribute \src "libresoc.v:49207.9-49207.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" - switch \dbg_d_gpr_req - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi__addr[4:0] \dbg_d_gpr_addr [4:0] - case - assign $1\dmi__addr[4:0] 5'00000 - end - sync always - update \dmi__addr $0\dmi__addr[4:0] - end - attribute \src "libresoc.v:49216.3-49225.6" - process $proc$libresoc.v:49216$1590 - assign { } { } - assign { } { } - assign $0\dmi__ren[0:0] $1\dmi__ren[0:0] - attribute \src "libresoc.v:49217.5-49217.29" - switch \initial - attribute \src "libresoc.v:49217.9-49217.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" - switch \dbg_d_gpr_req - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi__ren[0:0] 1'1 - case - assign $1\dmi__ren[0:0] 1'0 - end - sync always - update \dmi__ren $0\dmi__ren[0:0] - end - attribute \src "libresoc.v:49226.3-49234.6" - process $proc$libresoc.v:49226$1591 - assign { } { } - assign { } { } - assign $0\d_reg_delay$next[0:0]$1592 $1\d_reg_delay$next[0:0]$1593 - attribute \src "libresoc.v:49227.5-49227.29" - switch \initial - attribute \src "libresoc.v:49227.9-49227.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\d_reg_delay$next[0:0]$1593 1'0 - case - assign $1\d_reg_delay$next[0:0]$1593 \dbg_d_gpr_req - end - sync always - update \d_reg_delay$next $0\d_reg_delay$next[0:0]$1592 - end - attribute \src "libresoc.v:49235.3-49244.6" - process $proc$libresoc.v:49235$1594 - assign { } { } - assign { } { } - assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:49236.5-49236.29" - switch \initial - attribute \src "libresoc.v:49236.9-49236.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" - switch \d_reg_delay - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbg_d_gpr_data[63:0] \dmi__data_o - case - assign $1\dbg_d_gpr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] - end - attribute \src "libresoc.v:49245.3-49254.6" - process $proc$libresoc.v:49245$1595 - assign { } { } - assign { } { } - assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:49246.5-49246.29" - switch \initial - attribute \src "libresoc.v:49246.9-49246.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" - switch \d_reg_delay - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbg_d_gpr_ack[0:0] 1'1 - case - assign $1\dbg_d_gpr_ack[0:0] 1'0 - end - sync always - update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] - end - attribute \src "libresoc.v:49255.3-49264.6" - process $proc$libresoc.v:49255$1596 - assign { } { } - assign { } { } - assign $0\full_rd2__ren[7:0] $1\full_rd2__ren[7:0] - attribute \src "libresoc.v:49256.5-49256.29" - switch \initial - attribute \src "libresoc.v:49256.9-49256.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" - switch \dbg_d_cr_req - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\full_rd2__ren[7:0] 8'11111111 - case - assign $1\full_rd2__ren[7:0] 8'00000000 - end - sync always - update \full_rd2__ren $0\full_rd2__ren[7:0] - end - attribute \src "libresoc.v:49265.3-49273.6" - process $proc$libresoc.v:49265$1597 - assign { } { } - assign { } { } - assign $0\d_cr_delay$next[0:0]$1598 $1\d_cr_delay$next[0:0]$1599 - attribute \src "libresoc.v:49266.5-49266.29" - switch \initial - attribute \src "libresoc.v:49266.9-49266.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\d_cr_delay$next[0:0]$1599 1'0 - case - assign $1\d_cr_delay$next[0:0]$1599 \dbg_d_cr_req - end - sync always - update \d_cr_delay$next $0\d_cr_delay$next[0:0]$1598 - end - attribute \src "libresoc.v:49274.3-49283.6" - process $proc$libresoc.v:49274$1600 - assign { } { } - assign { } { } - assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:49275.5-49275.29" - switch \initial - attribute \src "libresoc.v:49275.9-49275.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - switch \d_cr_delay - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbg_d_cr_data[63:0] \$111 - case - assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] - end - attribute \src "libresoc.v:49284.3-49293.6" - process $proc$libresoc.v:49284$1601 - assign { } { } - assign { } { } - assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:49285.5-49285.29" - switch \initial - attribute \src "libresoc.v:49285.9-49285.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - switch \d_cr_delay - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbg_d_cr_ack[0:0] 1'1 - case - assign $1\dbg_d_cr_ack[0:0] 1'0 - end - sync always - update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] - end - attribute \src "libresoc.v:49294.3-49303.6" - process $proc$libresoc.v:49294$1602 - assign { } { } - assign { } { } - assign $0\full_rd__ren[2:0] $1\full_rd__ren[2:0] - attribute \src "libresoc.v:49295.5-49295.29" - switch \initial - attribute \src "libresoc.v:49295.9-49295.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:333" - switch \dbg_d_xer_req - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\full_rd__ren[2:0] 3'111 - case - assign $1\full_rd__ren[2:0] 3'000 - end - sync always - update \full_rd__ren $0\full_rd__ren[2:0] - end - attribute \src "libresoc.v:49304.3-49312.6" - process $proc$libresoc.v:49304$1603 - assign { } { } - assign { } { } - assign $0\d_xer_delay$next[0:0]$1604 $1\d_xer_delay$next[0:0]$1605 - attribute \src "libresoc.v:49305.5-49305.29" - switch \initial - attribute \src "libresoc.v:49305.9-49305.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\d_xer_delay$next[0:0]$1605 1'0 - case - assign $1\d_xer_delay$next[0:0]$1605 \dbg_d_xer_req - end - sync always - update \d_xer_delay$next $0\d_xer_delay$next[0:0]$1604 - end - attribute \src "libresoc.v:49313.3-49322.6" - process $proc$libresoc.v:49313$1606 - assign { } { } - assign { } { } - assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:49314.5-49314.29" - switch \initial - attribute \src "libresoc.v:49314.9-49314.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - switch \d_xer_delay - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbg_d_xer_data[63:0] \$113 - case - assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] - end - attribute \src "libresoc.v:49323.3-49332.6" - process $proc$libresoc.v:49323$1607 - assign { } { } - assign { } { } - assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:49324.5-49324.29" - switch \initial - attribute \src "libresoc.v:49324.9-49324.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" - switch \d_xer_delay - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbg_d_xer_ack[0:0] 1'1 - case - assign $1\dbg_d_xer_ack[0:0] 1'0 - end - sync always - update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] - end - attribute \src "libresoc.v:49333.3-49347.6" - process $proc$libresoc.v:49333$1608 - assign { } { } - assign { } { } - assign $0\issue__addr[2:0] $1\issue__addr[2:0] - attribute \src "libresoc.v:49334.5-49334.29" - switch \initial - attribute \src "libresoc.v:49334.9-49334.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" - switch \fsm_state$115 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\issue__addr[2:0] 3'110 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\issue__addr[2:0] 3'111 - case - assign $1\issue__addr[2:0] 3'000 - end - sync always - update \issue__addr $0\issue__addr[2:0] - end - attribute \src "libresoc.v:49348.3-49362.6" - process $proc$libresoc.v:49348$1609 - assign { } { } - assign { } { } - assign $0\issue__ren[0:0] $1\issue__ren[0:0] - attribute \src "libresoc.v:49349.5-49349.29" - switch \initial - attribute \src "libresoc.v:49349.9-49349.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" - switch \fsm_state$115 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\issue__ren[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\issue__ren[0:0] 1'1 - case - assign $1\issue__ren[0:0] 1'0 - end - sync always - update \issue__ren $0\issue__ren[0:0] - end - attribute \src "libresoc.v:49363.3-49390.6" - process $proc$libresoc.v:49363$1610 - assign { } { } - assign { } { } - assign { } { } - assign $0\fsm_state$115$next[1:0]$1611 $2\fsm_state$115$next[1:0]$1613 - attribute \src "libresoc.v:49364.5-49364.29" - switch \initial - attribute \src "libresoc.v:49364.9-49364.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" - switch \fsm_state$115 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\fsm_state$115$next[1:0]$1612 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\fsm_state$115$next[1:0]$1612 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\fsm_state$115$next[1:0]$1612 2'11 - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\fsm_state$115$next[1:0]$1612 2'00 - case - assign $1\fsm_state$115$next[1:0]$1612 \fsm_state$115 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fsm_state$115$next[1:0]$1613 2'00 - case - assign $2\fsm_state$115$next[1:0]$1613 $1\fsm_state$115$next[1:0]$1612 - end - sync always - update \fsm_state$115$next $0\fsm_state$115$next[1:0]$1611 - end - attribute \src "libresoc.v:49391.3-49401.6" - process $proc$libresoc.v:49391$1614 - assign { } { } - assign { } { } - assign $0\new_dec[63:0] $1\new_dec[63:0] - attribute \src "libresoc.v:49392.5-49392.29" - switch \initial - attribute \src "libresoc.v:49392.9-49392.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" - switch \fsm_state$115 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\new_dec[63:0] \$116 [63:0] - case - assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \new_dec $0\new_dec[63:0] - end - attribute \src "libresoc.v:49402.3-49416.6" - process $proc$libresoc.v:49402$1615 - assign { } { } - assign { } { } - assign $0\issue__addr$119[2:0]$1616 $1\issue__addr$119[2:0]$1617 - attribute \src "libresoc.v:49403.5-49403.29" - switch \initial - attribute \src "libresoc.v:49403.9-49403.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" - switch \fsm_state$115 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\issue__addr$119[2:0]$1617 3'110 - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\issue__addr$119[2:0]$1617 3'111 - case - assign $1\issue__addr$119[2:0]$1617 3'000 - end - sync always - update \issue__addr$119 $0\issue__addr$119[2:0]$1616 - end - attribute \src "libresoc.v:49417.3-49431.6" - process $proc$libresoc.v:49417$1618 - assign { } { } - assign { } { } - assign $0\issue__wen[0:0] $1\issue__wen[0:0] - attribute \src "libresoc.v:49418.5-49418.29" - switch \initial - attribute \src "libresoc.v:49418.9-49418.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" - switch \fsm_state$115 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\issue__wen[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\issue__wen[0:0] 1'1 - case - assign $1\issue__wen[0:0] 1'0 - end - sync always - update \issue__wen $0\issue__wen[0:0] - end - attribute \src "libresoc.v:49432.3-49446.6" - process $proc$libresoc.v:49432$1619 - assign { } { } - assign { } { } - assign $0\issue__data_i[63:0] $1\issue__data_i[63:0] - attribute \src "libresoc.v:49433.5-49433.29" - switch \initial - attribute \src "libresoc.v:49433.9-49433.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" - switch \fsm_state$115 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\issue__data_i[63:0] \new_dec - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\issue__data_i[63:0] \new_tb - case - assign $1\issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \issue__data_i $0\issue__data_i[63:0] - end - attribute \src "libresoc.v:49447.3-49462.6" - process $proc$libresoc.v:49447$1620 - assign { } { } - assign { } { } - assign { } { } - assign $0\dec2_cur_dec$next[63:0]$1621 $2\dec2_cur_dec$next[63:0]$1623 - attribute \src "libresoc.v:49448.5-49448.29" - switch \initial - attribute \src "libresoc.v:49448.9-49448.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" - switch \fsm_state$115 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec2_cur_dec$next[63:0]$1622 \new_dec - case - assign $1\dec2_cur_dec$next[63:0]$1622 \dec2_cur_dec - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dec2_cur_dec$next[63:0]$1623 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\dec2_cur_dec$next[63:0]$1623 $1\dec2_cur_dec$next[63:0]$1622 - end - sync always - update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$1621 - end - attribute \src "libresoc.v:49463.3-49473.6" - process $proc$libresoc.v:49463$1624 - assign { } { } - assign { } { } - assign $0\new_tb[63:0] $1\new_tb[63:0] - attribute \src "libresoc.v:49464.5-49464.29" - switch \initial - attribute \src "libresoc.v:49464.9-49464.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" - switch \fsm_state$115 - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\new_tb[63:0] \$120 [63:0] - case - assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \new_tb $0\new_tb[63:0] - end - attribute \src "libresoc.v:49474.3-49482.6" - process $proc$libresoc.v:49474$1625 - assign { } { } - assign { } { } - assign $0\dbg_dmi_we_i$next[0:0]$1626 $1\dbg_dmi_we_i$next[0:0]$1627 - attribute \src "libresoc.v:49475.5-49475.29" - switch \initial - attribute \src "libresoc.v:49475.9-49475.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbg_dmi_we_i$next[0:0]$1627 1'0 - case - assign $1\dbg_dmi_we_i$next[0:0]$1627 \jtag_dmi0_we_i - end - sync always - update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$1626 - end - attribute \src "libresoc.v:49483.3-49491.6" - process $proc$libresoc.v:49483$1628 - assign { } { } - assign { } { } - assign $0\pc_ok_delay$next[0:0]$1629 $1\pc_ok_delay$next[0:0]$1630 - attribute \src "libresoc.v:49484.5-49484.29" - switch \initial - attribute \src "libresoc.v:49484.9-49484.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\pc_ok_delay$next[0:0]$1630 1'0 - case - assign $1\pc_ok_delay$next[0:0]$1630 \$19 - end - sync always - update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$1629 - end - attribute \src "libresoc.v:49492.3-49507.6" - process $proc$libresoc.v:49492$1631 - assign { } { } - assign { } { } - assign { } { } - assign $0\pc[63:0] $2\pc[63:0] - attribute \src "libresoc.v:49493.5-49493.29" - switch \initial - attribute \src "libresoc.v:49493.9-49493.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:189" - switch \pc_i_ok - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\pc[63:0] \pc_i - case - assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:196" - switch \pc_ok_delay - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\pc[63:0] \cia__data_o - case - assign $2\pc[63:0] $1\pc[63:0] - end - sync always - update \pc $0\pc[63:0] - end - attribute \src "libresoc.v:49508.3-49520.6" - process $proc$libresoc.v:49508$1632 - assign { } { } - assign { } { } - assign $0\cia__ren[3:0] $1\cia__ren[3:0] - attribute \src "libresoc.v:49509.5-49509.29" - switch \initial - attribute \src "libresoc.v:49509.9-49509.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:189" - switch \pc_i_ok - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $1\cia__ren[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cia__ren[3:0] 4'0001 - end - sync always - update \cia__ren $0\cia__ren[3:0] - end - attribute \src "libresoc.v:49521.3-49541.6" - process $proc$libresoc.v:49521$1633 - assign { } { } - assign { } { } - assign $0\wen[3:0] $1\wen[3:0] - attribute \src "libresoc.v:49522.5-49522.29" - switch \initial - attribute \src "libresoc.v:49522.9-49522.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\wen[3:0] $2\wen[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" - switch \$21 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wen[3:0] $3\wen[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" - switch \$23 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wen[3:0] 4'0001 - case - assign $3\wen[3:0] 4'0000 - end - case - assign $2\wen[3:0] 4'0000 - end - case - assign $1\wen[3:0] 4'0000 - end - sync always - update \wen $0\wen[3:0] - end - attribute \src "libresoc.v:49542.3-49562.6" - process $proc$libresoc.v:49542$1634 - assign { } { } - assign { } { } - assign $0\data_i[63:0] $1\data_i[63:0] - attribute \src "libresoc.v:49543.5-49543.29" - switch \initial - attribute \src "libresoc.v:49543.9-49543.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\data_i[63:0] $2\data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" - switch \$25 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\data_i[63:0] $3\data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" - switch \$27 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_i[63:0] \nia - case - assign $3\data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $2\data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \data_i $0\data_i[63:0] - end - attribute \src "libresoc.v:49563.3-49578.6" - process $proc$libresoc.v:49563$1635 - assign { } { } - assign { } { } - assign $0\msr__ren[3:0] $1\msr__ren[3:0] - attribute \src "libresoc.v:49564.5-49564.29" - switch \initial - attribute \src "libresoc.v:49564.9-49564.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\msr__ren[3:0] $2\msr__ren[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - switch \$33 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\msr__ren[3:0] 4'0010 - case - assign $2\msr__ren[3:0] 4'0000 - end - case - assign $1\msr__ren[3:0] 4'0000 - end - sync always - update \msr__ren $0\msr__ren[3:0] - end - attribute \src "libresoc.v:49579.3-49587.6" - process $proc$libresoc.v:49579$1636 - assign { } { } - assign { } { } - assign $0\dbg_dmi_din$next[63:0]$1637 $1\dbg_dmi_din$next[63:0]$1638 - attribute \src "libresoc.v:49580.5-49580.29" - switch \initial - attribute \src "libresoc.v:49580.9-49580.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbg_dmi_din$next[63:0]$1638 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $1\dbg_dmi_din$next[63:0]$1638 \jtag_dmi0_din - end - sync always - update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$1637 - end - attribute \src "libresoc.v:49588.3-49612.6" - process $proc$libresoc.v:49588$1639 - assign { } { } - assign { } { } - assign { } { } - assign $0\pc_changed$next[0:0]$1640 $3\pc_changed$next[0:0]$1643 - attribute \src "libresoc.v:49589.5-49589.29" - switch \initial - attribute \src "libresoc.v:49589.9-49589.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\pc_changed$next[0:0]$1641 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\pc_changed$next[0:0]$1641 $2\pc_changed$next[0:0]$1642 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" - switch \$35 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\pc_changed$next[0:0]$1642 1'1 - case - assign $2\pc_changed$next[0:0]$1642 \pc_changed - end - case - assign $1\pc_changed$next[0:0]$1641 \pc_changed - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\pc_changed$next[0:0]$1643 1'0 - case - assign $3\pc_changed$next[0:0]$1643 $1\pc_changed$next[0:0]$1641 - end - sync always - update \pc_changed$next $0\pc_changed$next[0:0]$1640 - end - attribute \src "libresoc.v:49613.3-49719.6" - process $proc$libresoc.v:49613$1644 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\core_asmcode$next[7:0]$1645 $1\core_asmcode$next[7:0]$1696 - assign $0\core_core_cia$next[63:0]$1646 $1\core_core_cia$next[63:0]$1697 - assign $0\core_core_cr_rd$next[7:0]$1647 $1\core_core_cr_rd$next[7:0]$1698 - assign { } { } - assign $0\core_core_cr_wr$next[7:0]$1649 $1\core_core_cr_wr$next[7:0]$1700 - assign { } { } - assign $0\core_core_fn_unit$next[11:0]$1651 $1\core_core_fn_unit$next[11:0]$1702 - assign $0\core_core_input_carry$next[1:0]$1652 $1\core_core_input_carry$next[1:0]$1703 - assign $0\core_core_insn$next[31:0]$1653 $1\core_core_insn$next[31:0]$1704 - assign $0\core_core_insn_type$next[6:0]$1654 $1\core_core_insn_type$next[6:0]$1705 - assign $0\core_core_is_32bit$next[0:0]$1655 $1\core_core_is_32bit$next[0:0]$1706 - assign $0\core_core_lk$next[0:0]$1656 $1\core_core_lk$next[0:0]$1707 - assign $0\core_core_msr$next[63:0]$1657 $1\core_core_msr$next[63:0]$1708 - assign $0\core_core_oe$next[0:0]$1658 $1\core_core_oe$next[0:0]$1709 - assign { } { } - assign $0\core_core_rc$next[0:0]$1660 $1\core_core_rc$next[0:0]$1711 - assign { } { } - assign $0\core_core_trapaddr$next[12:0]$1662 $1\core_core_trapaddr$next[12:0]$1713 - assign $0\core_core_traptype$next[6:0]$1663 $1\core_core_traptype$next[6:0]$1714 - assign $0\core_cr_in1$next[2:0]$1664 $1\core_cr_in1$next[2:0]$1715 - assign { } { } - assign $0\core_cr_in2$39$next[2:0]$1666 $1\core_cr_in2$39$next[2:0]$1717 - assign $0\core_cr_in2$next[2:0]$1667 $1\core_cr_in2$next[2:0]$1718 - assign { } { } - assign { } { } - assign $0\core_cr_out$next[2:0]$1670 $1\core_cr_out$next[2:0]$1721 - assign { } { } - assign $0\core_ea$next[4:0]$1672 $1\core_ea$next[4:0]$1723 - assign { } { } - assign $0\core_fast1$next[2:0]$1674 $1\core_fast1$next[2:0]$1725 - assign { } { } - assign $0\core_fast2$next[2:0]$1676 $1\core_fast2$next[2:0]$1727 - assign { } { } - assign $0\core_fasto1$next[2:0]$1678 $1\core_fasto1$next[2:0]$1729 - assign { } { } - assign $0\core_fasto2$next[2:0]$1680 $1\core_fasto2$next[2:0]$1731 - assign { } { } - assign $0\core_reg1$next[4:0]$1682 $1\core_reg1$next[4:0]$1733 - assign { } { } - assign $0\core_reg2$next[4:0]$1684 $1\core_reg2$next[4:0]$1735 - assign { } { } - assign $0\core_reg3$next[4:0]$1686 $1\core_reg3$next[4:0]$1737 - assign { } { } - assign $0\core_rego$next[4:0]$1688 $1\core_rego$next[4:0]$1739 - assign { } { } - assign $0\core_spr1$next[9:0]$1690 $1\core_spr1$next[9:0]$1741 - assign { } { } - assign $0\core_spro$next[9:0]$1692 $1\core_spro$next[9:0]$1743 - assign { } { } - assign $0\core_xer_in$next[2:0]$1694 $1\core_xer_in$next[2:0]$1745 - assign $0\core_xer_out$next[0:0]$1695 $1\core_xer_out$next[0:0]$1746 - assign $0\core_core_cr_rd_ok$next[0:0]$1648 $4\core_core_cr_rd_ok$next[0:0]$1849 - assign $0\core_core_cr_wr_ok$next[0:0]$1650 $4\core_core_cr_wr_ok$next[0:0]$1850 - assign $0\core_core_oe_ok$next[0:0]$1659 $4\core_core_oe_ok$next[0:0]$1851 - assign $0\core_core_rc_ok$next[0:0]$1661 $4\core_core_rc_ok$next[0:0]$1852 - assign $0\core_cr_in1_ok$next[0:0]$1665 $4\core_cr_in1_ok$next[0:0]$1853 - assign $0\core_cr_in2_ok$40$next[0:0]$1668 $4\core_cr_in2_ok$40$next[0:0]$1854 - assign $0\core_cr_in2_ok$next[0:0]$1669 $4\core_cr_in2_ok$next[0:0]$1855 - assign $0\core_cr_out_ok$next[0:0]$1671 $4\core_cr_out_ok$next[0:0]$1856 - assign $0\core_ea_ok$next[0:0]$1673 $4\core_ea_ok$next[0:0]$1857 - assign $0\core_fast1_ok$next[0:0]$1675 $4\core_fast1_ok$next[0:0]$1858 - assign $0\core_fast2_ok$next[0:0]$1677 $4\core_fast2_ok$next[0:0]$1859 - assign $0\core_fasto1_ok$next[0:0]$1679 $4\core_fasto1_ok$next[0:0]$1860 - assign $0\core_fasto2_ok$next[0:0]$1681 $4\core_fasto2_ok$next[0:0]$1861 - assign $0\core_reg1_ok$next[0:0]$1683 $4\core_reg1_ok$next[0:0]$1862 - assign $0\core_reg2_ok$next[0:0]$1685 $4\core_reg2_ok$next[0:0]$1863 - assign $0\core_reg3_ok$next[0:0]$1687 $4\core_reg3_ok$next[0:0]$1864 - assign $0\core_rego_ok$next[0:0]$1689 $4\core_rego_ok$next[0:0]$1865 - assign $0\core_spr1_ok$next[0:0]$1691 $4\core_spr1_ok$next[0:0]$1866 - assign $0\core_spro_ok$next[0:0]$1693 $4\core_spro_ok$next[0:0]$1867 - attribute \src "libresoc.v:49614.5-49614.29" - switch \initial - attribute \src "libresoc.v:49614.9-49614.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\core_core_is_32bit$next[0:0]$1706 $1\core_core_cr_wr_ok$next[0:0]$1701 $1\core_core_cr_wr$next[7:0]$1700 $1\core_core_cr_rd_ok$next[0:0]$1699 $1\core_core_cr_rd$next[7:0]$1698 $1\core_core_trapaddr$next[12:0]$1713 $1\core_core_traptype$next[6:0]$1714 $1\core_core_input_carry$next[1:0]$1703 $1\core_core_oe_ok$next[0:0]$1710 $1\core_core_oe$next[0:0]$1709 $1\core_core_rc_ok$next[0:0]$1712 $1\core_core_rc$next[0:0]$1711 $1\core_core_lk$next[0:0]$1707 $1\core_core_fn_unit$next[11:0]$1702 $1\core_core_insn_type$next[6:0]$1705 $1\core_core_insn$next[31:0]$1704 $1\core_core_cia$next[63:0]$1697 $1\core_core_msr$next[63:0]$1708 $1\core_cr_out_ok$next[0:0]$1722 $1\core_cr_out$next[2:0]$1721 $1\core_cr_in2_ok$40$next[0:0]$1719 $1\core_cr_in2$39$next[2:0]$1717 $1\core_cr_in2_ok$next[0:0]$1720 $1\core_cr_in2$next[2:0]$1718 $1\core_cr_in1_ok$next[0:0]$1716 $1\core_cr_in1$next[2:0]$1715 $1\core_fasto2_ok$next[0:0]$1732 $1\core_fasto2$next[2:0]$1731 $1\core_fasto1_ok$next[0:0]$1730 $1\core_fasto1$next[2:0]$1729 $1\core_fast2_ok$next[0:0]$1728 $1\core_fast2$next[2:0]$1727 $1\core_fast1_ok$next[0:0]$1726 $1\core_fast1$next[2:0]$1725 $1\core_xer_out$next[0:0]$1746 $1\core_xer_in$next[2:0]$1745 $1\core_spr1_ok$next[0:0]$1742 $1\core_spr1$next[9:0]$1741 $1\core_spro_ok$next[0:0]$1744 $1\core_spro$next[9:0]$1743 $1\core_reg3_ok$next[0:0]$1738 $1\core_reg3$next[4:0]$1737 $1\core_reg2_ok$next[0:0]$1736 $1\core_reg2$next[4:0]$1735 $1\core_reg1_ok$next[0:0]$1734 $1\core_reg1$next[4:0]$1733 $1\core_ea_ok$next[0:0]$1724 $1\core_ea$next[4:0]$1723 $1\core_rego_ok$next[0:0]$1740 $1\core_rego$next[4:0]$1739 $1\core_asmcode$next[7:0]$1696 } 321'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\core_asmcode$next[7:0]$1696 $2\core_asmcode$next[7:0]$1747 - assign $1\core_core_cia$next[63:0]$1697 $2\core_core_cia$next[63:0]$1748 - assign $1\core_core_cr_rd$next[7:0]$1698 $2\core_core_cr_rd$next[7:0]$1749 - assign $1\core_core_cr_rd_ok$next[0:0]$1699 $2\core_core_cr_rd_ok$next[0:0]$1750 - assign $1\core_core_cr_wr$next[7:0]$1700 $2\core_core_cr_wr$next[7:0]$1751 - assign $1\core_core_cr_wr_ok$next[0:0]$1701 $2\core_core_cr_wr_ok$next[0:0]$1752 - assign $1\core_core_fn_unit$next[11:0]$1702 $2\core_core_fn_unit$next[11:0]$1753 - assign $1\core_core_input_carry$next[1:0]$1703 $2\core_core_input_carry$next[1:0]$1754 - assign $1\core_core_insn$next[31:0]$1704 $2\core_core_insn$next[31:0]$1755 - assign $1\core_core_insn_type$next[6:0]$1705 $2\core_core_insn_type$next[6:0]$1756 - assign $1\core_core_is_32bit$next[0:0]$1706 $2\core_core_is_32bit$next[0:0]$1757 - assign $1\core_core_lk$next[0:0]$1707 $2\core_core_lk$next[0:0]$1758 - assign $1\core_core_msr$next[63:0]$1708 $2\core_core_msr$next[63:0]$1759 - assign $1\core_core_oe$next[0:0]$1709 $2\core_core_oe$next[0:0]$1760 - assign $1\core_core_oe_ok$next[0:0]$1710 $2\core_core_oe_ok$next[0:0]$1761 - assign $1\core_core_rc$next[0:0]$1711 $2\core_core_rc$next[0:0]$1762 - assign $1\core_core_rc_ok$next[0:0]$1712 $2\core_core_rc_ok$next[0:0]$1763 - assign $1\core_core_trapaddr$next[12:0]$1713 $2\core_core_trapaddr$next[12:0]$1764 - assign $1\core_core_traptype$next[6:0]$1714 $2\core_core_traptype$next[6:0]$1765 - assign $1\core_cr_in1$next[2:0]$1715 $2\core_cr_in1$next[2:0]$1766 - assign $1\core_cr_in1_ok$next[0:0]$1716 $2\core_cr_in1_ok$next[0:0]$1767 - assign $1\core_cr_in2$39$next[2:0]$1717 $2\core_cr_in2$39$next[2:0]$1768 - assign $1\core_cr_in2$next[2:0]$1718 $2\core_cr_in2$next[2:0]$1769 - assign $1\core_cr_in2_ok$40$next[0:0]$1719 $2\core_cr_in2_ok$40$next[0:0]$1770 - assign $1\core_cr_in2_ok$next[0:0]$1720 $2\core_cr_in2_ok$next[0:0]$1771 - assign $1\core_cr_out$next[2:0]$1721 $2\core_cr_out$next[2:0]$1772 - assign $1\core_cr_out_ok$next[0:0]$1722 $2\core_cr_out_ok$next[0:0]$1773 - assign $1\core_ea$next[4:0]$1723 $2\core_ea$next[4:0]$1774 - assign $1\core_ea_ok$next[0:0]$1724 $2\core_ea_ok$next[0:0]$1775 - assign $1\core_fast1$next[2:0]$1725 $2\core_fast1$next[2:0]$1776 - assign $1\core_fast1_ok$next[0:0]$1726 $2\core_fast1_ok$next[0:0]$1777 - assign $1\core_fast2$next[2:0]$1727 $2\core_fast2$next[2:0]$1778 - assign $1\core_fast2_ok$next[0:0]$1728 $2\core_fast2_ok$next[0:0]$1779 - assign $1\core_fasto1$next[2:0]$1729 $2\core_fasto1$next[2:0]$1780 - assign $1\core_fasto1_ok$next[0:0]$1730 $2\core_fasto1_ok$next[0:0]$1781 - assign $1\core_fasto2$next[2:0]$1731 $2\core_fasto2$next[2:0]$1782 - assign $1\core_fasto2_ok$next[0:0]$1732 $2\core_fasto2_ok$next[0:0]$1783 - assign $1\core_reg1$next[4:0]$1733 $2\core_reg1$next[4:0]$1784 - assign $1\core_reg1_ok$next[0:0]$1734 $2\core_reg1_ok$next[0:0]$1785 - assign $1\core_reg2$next[4:0]$1735 $2\core_reg2$next[4:0]$1786 - assign $1\core_reg2_ok$next[0:0]$1736 $2\core_reg2_ok$next[0:0]$1787 - assign $1\core_reg3$next[4:0]$1737 $2\core_reg3$next[4:0]$1788 - assign $1\core_reg3_ok$next[0:0]$1738 $2\core_reg3_ok$next[0:0]$1789 - assign $1\core_rego$next[4:0]$1739 $2\core_rego$next[4:0]$1790 - assign $1\core_rego_ok$next[0:0]$1740 $2\core_rego_ok$next[0:0]$1791 - assign $1\core_spr1$next[9:0]$1741 $2\core_spr1$next[9:0]$1792 - assign $1\core_spr1_ok$next[0:0]$1742 $2\core_spr1_ok$next[0:0]$1793 - assign $1\core_spro$next[9:0]$1743 $2\core_spro$next[9:0]$1794 - assign $1\core_spro_ok$next[0:0]$1744 $2\core_spro_ok$next[0:0]$1795 - assign $1\core_xer_in$next[2:0]$1745 $2\core_xer_in$next[2:0]$1796 - assign $1\core_xer_out$next[0:0]$1746 $2\core_xer_out$next[0:0]$1797 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\core_asmcode$next[7:0]$1747 \core_asmcode - assign $2\core_core_cia$next[63:0]$1748 \core_core_cia - assign $2\core_core_cr_rd$next[7:0]$1749 \core_core_cr_rd - assign $2\core_core_cr_rd_ok$next[0:0]$1750 \core_core_cr_rd_ok - assign $2\core_core_cr_wr$next[7:0]$1751 \core_core_cr_wr - assign $2\core_core_cr_wr_ok$next[0:0]$1752 \core_core_cr_wr_ok - assign $2\core_core_fn_unit$next[11:0]$1753 \core_core_fn_unit - assign $2\core_core_input_carry$next[1:0]$1754 \core_core_input_carry - assign $2\core_core_insn$next[31:0]$1755 \core_core_insn - assign $2\core_core_insn_type$next[6:0]$1756 \core_core_insn_type - assign $2\core_core_is_32bit$next[0:0]$1757 \core_core_is_32bit - assign $2\core_core_lk$next[0:0]$1758 \core_core_lk - assign $2\core_core_msr$next[63:0]$1759 \core_core_msr - assign $2\core_core_oe$next[0:0]$1760 \core_core_oe - assign $2\core_core_oe_ok$next[0:0]$1761 \core_core_oe_ok - assign $2\core_core_rc$next[0:0]$1762 \core_core_rc - assign $2\core_core_rc_ok$next[0:0]$1763 \core_core_rc_ok - assign $2\core_core_trapaddr$next[12:0]$1764 \core_core_trapaddr - assign $2\core_core_traptype$next[6:0]$1765 \core_core_traptype - assign $2\core_cr_in1$next[2:0]$1766 \core_cr_in1 - assign $2\core_cr_in1_ok$next[0:0]$1767 \core_cr_in1_ok - assign $2\core_cr_in2$39$next[2:0]$1768 \core_cr_in2$39 - assign $2\core_cr_in2$next[2:0]$1769 \core_cr_in2 - assign $2\core_cr_in2_ok$40$next[0:0]$1770 \core_cr_in2_ok$40 - assign $2\core_cr_in2_ok$next[0:0]$1771 \core_cr_in2_ok - assign $2\core_cr_out$next[2:0]$1772 \core_cr_out - assign $2\core_cr_out_ok$next[0:0]$1773 \core_cr_out_ok - assign $2\core_ea$next[4:0]$1774 \core_ea - assign $2\core_ea_ok$next[0:0]$1775 \core_ea_ok - assign $2\core_fast1$next[2:0]$1776 \core_fast1 - assign $2\core_fast1_ok$next[0:0]$1777 \core_fast1_ok - assign $2\core_fast2$next[2:0]$1778 \core_fast2 - assign $2\core_fast2_ok$next[0:0]$1779 \core_fast2_ok - assign $2\core_fasto1$next[2:0]$1780 \core_fasto1 - assign $2\core_fasto1_ok$next[0:0]$1781 \core_fasto1_ok - assign $2\core_fasto2$next[2:0]$1782 \core_fasto2 - assign $2\core_fasto2_ok$next[0:0]$1783 \core_fasto2_ok - assign $2\core_reg1$next[4:0]$1784 \core_reg1 - assign $2\core_reg1_ok$next[0:0]$1785 \core_reg1_ok - assign $2\core_reg2$next[4:0]$1786 \core_reg2 - assign $2\core_reg2_ok$next[0:0]$1787 \core_reg2_ok - assign $2\core_reg3$next[4:0]$1788 \core_reg3 - assign $2\core_reg3_ok$next[0:0]$1789 \core_reg3_ok - assign $2\core_rego$next[4:0]$1790 \core_rego - assign $2\core_rego_ok$next[0:0]$1791 \core_rego_ok - assign $2\core_spr1$next[9:0]$1792 \core_spr1 - assign $2\core_spr1_ok$next[0:0]$1793 \core_spr1_ok - assign $2\core_spro$next[9:0]$1794 \core_spro - assign $2\core_spro_ok$next[0:0]$1795 \core_spro_ok - assign $2\core_xer_in$next[2:0]$1796 \core_xer_in - assign $2\core_xer_out$next[0:0]$1797 \core_xer_out - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\core_core_is_32bit$next[0:0]$1757 $2\core_core_cr_wr_ok$next[0:0]$1752 $2\core_core_cr_wr$next[7:0]$1751 $2\core_core_cr_rd_ok$next[0:0]$1750 $2\core_core_cr_rd$next[7:0]$1749 $2\core_core_trapaddr$next[12:0]$1764 $2\core_core_traptype$next[6:0]$1765 $2\core_core_input_carry$next[1:0]$1754 $2\core_core_oe_ok$next[0:0]$1761 $2\core_core_oe$next[0:0]$1760 $2\core_core_rc_ok$next[0:0]$1763 $2\core_core_rc$next[0:0]$1762 $2\core_core_lk$next[0:0]$1758 $2\core_core_fn_unit$next[11:0]$1753 $2\core_core_insn_type$next[6:0]$1756 $2\core_core_insn$next[31:0]$1755 $2\core_core_cia$next[63:0]$1748 $2\core_core_msr$next[63:0]$1759 $2\core_cr_out_ok$next[0:0]$1773 $2\core_cr_out$next[2:0]$1772 $2\core_cr_in2_ok$40$next[0:0]$1770 $2\core_cr_in2$39$next[2:0]$1768 $2\core_cr_in2_ok$next[0:0]$1771 $2\core_cr_in2$next[2:0]$1769 $2\core_cr_in1_ok$next[0:0]$1767 $2\core_cr_in1$next[2:0]$1766 $2\core_fasto2_ok$next[0:0]$1783 $2\core_fasto2$next[2:0]$1782 $2\core_fasto1_ok$next[0:0]$1781 $2\core_fasto1$next[2:0]$1780 $2\core_fast2_ok$next[0:0]$1779 $2\core_fast2$next[2:0]$1778 $2\core_fast1_ok$next[0:0]$1777 $2\core_fast1$next[2:0]$1776 $2\core_xer_out$next[0:0]$1797 $2\core_xer_in$next[2:0]$1796 $2\core_spr1_ok$next[0:0]$1793 $2\core_spr1$next[9:0]$1792 $2\core_spro_ok$next[0:0]$1795 $2\core_spro$next[9:0]$1794 $2\core_reg3_ok$next[0:0]$1789 $2\core_reg3$next[4:0]$1788 $2\core_reg2_ok$next[0:0]$1787 $2\core_reg2$next[4:0]$1786 $2\core_reg1_ok$next[0:0]$1785 $2\core_reg1$next[4:0]$1784 $2\core_ea_ok$next[0:0]$1775 $2\core_ea$next[4:0]$1774 $2\core_rego_ok$next[0:0]$1791 $2\core_rego$next[4:0]$1790 $2\core_asmcode$next[7:0]$1747 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$2 \dec2_cr_in2$1 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } - end - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\core_asmcode$next[7:0]$1696 $3\core_asmcode$next[7:0]$1798 - assign $1\core_core_cia$next[63:0]$1697 $3\core_core_cia$next[63:0]$1799 - assign $1\core_core_cr_rd$next[7:0]$1698 $3\core_core_cr_rd$next[7:0]$1800 - assign $1\core_core_cr_rd_ok$next[0:0]$1699 $3\core_core_cr_rd_ok$next[0:0]$1801 - assign $1\core_core_cr_wr$next[7:0]$1700 $3\core_core_cr_wr$next[7:0]$1802 - assign $1\core_core_cr_wr_ok$next[0:0]$1701 $3\core_core_cr_wr_ok$next[0:0]$1803 - assign $1\core_core_fn_unit$next[11:0]$1702 $3\core_core_fn_unit$next[11:0]$1804 - assign $1\core_core_input_carry$next[1:0]$1703 $3\core_core_input_carry$next[1:0]$1805 - assign $1\core_core_insn$next[31:0]$1704 $3\core_core_insn$next[31:0]$1806 - assign $1\core_core_insn_type$next[6:0]$1705 $3\core_core_insn_type$next[6:0]$1807 - assign $1\core_core_is_32bit$next[0:0]$1706 $3\core_core_is_32bit$next[0:0]$1808 - assign $1\core_core_lk$next[0:0]$1707 $3\core_core_lk$next[0:0]$1809 - assign $1\core_core_msr$next[63:0]$1708 $3\core_core_msr$next[63:0]$1810 - assign $1\core_core_oe$next[0:0]$1709 $3\core_core_oe$next[0:0]$1811 - assign $1\core_core_oe_ok$next[0:0]$1710 $3\core_core_oe_ok$next[0:0]$1812 - assign $1\core_core_rc$next[0:0]$1711 $3\core_core_rc$next[0:0]$1813 - assign $1\core_core_rc_ok$next[0:0]$1712 $3\core_core_rc_ok$next[0:0]$1814 - assign $1\core_core_trapaddr$next[12:0]$1713 $3\core_core_trapaddr$next[12:0]$1815 - assign $1\core_core_traptype$next[6:0]$1714 $3\core_core_traptype$next[6:0]$1816 - assign $1\core_cr_in1$next[2:0]$1715 $3\core_cr_in1$next[2:0]$1817 - assign $1\core_cr_in1_ok$next[0:0]$1716 $3\core_cr_in1_ok$next[0:0]$1818 - assign $1\core_cr_in2$39$next[2:0]$1717 $3\core_cr_in2$39$next[2:0]$1819 - assign $1\core_cr_in2$next[2:0]$1718 $3\core_cr_in2$next[2:0]$1820 - assign $1\core_cr_in2_ok$40$next[0:0]$1719 $3\core_cr_in2_ok$40$next[0:0]$1821 - assign $1\core_cr_in2_ok$next[0:0]$1720 $3\core_cr_in2_ok$next[0:0]$1822 - assign $1\core_cr_out$next[2:0]$1721 $3\core_cr_out$next[2:0]$1823 - assign $1\core_cr_out_ok$next[0:0]$1722 $3\core_cr_out_ok$next[0:0]$1824 - assign $1\core_ea$next[4:0]$1723 $3\core_ea$next[4:0]$1825 - assign $1\core_ea_ok$next[0:0]$1724 $3\core_ea_ok$next[0:0]$1826 - assign $1\core_fast1$next[2:0]$1725 $3\core_fast1$next[2:0]$1827 - assign $1\core_fast1_ok$next[0:0]$1726 $3\core_fast1_ok$next[0:0]$1828 - assign $1\core_fast2$next[2:0]$1727 $3\core_fast2$next[2:0]$1829 - assign $1\core_fast2_ok$next[0:0]$1728 $3\core_fast2_ok$next[0:0]$1830 - assign $1\core_fasto1$next[2:0]$1729 $3\core_fasto1$next[2:0]$1831 - assign $1\core_fasto1_ok$next[0:0]$1730 $3\core_fasto1_ok$next[0:0]$1832 - assign $1\core_fasto2$next[2:0]$1731 $3\core_fasto2$next[2:0]$1833 - assign $1\core_fasto2_ok$next[0:0]$1732 $3\core_fasto2_ok$next[0:0]$1834 - assign $1\core_reg1$next[4:0]$1733 $3\core_reg1$next[4:0]$1835 - assign $1\core_reg1_ok$next[0:0]$1734 $3\core_reg1_ok$next[0:0]$1836 - assign $1\core_reg2$next[4:0]$1735 $3\core_reg2$next[4:0]$1837 - assign $1\core_reg2_ok$next[0:0]$1736 $3\core_reg2_ok$next[0:0]$1838 - assign $1\core_reg3$next[4:0]$1737 $3\core_reg3$next[4:0]$1839 - assign $1\core_reg3_ok$next[0:0]$1738 $3\core_reg3_ok$next[0:0]$1840 - assign $1\core_rego$next[4:0]$1739 $3\core_rego$next[4:0]$1841 - assign $1\core_rego_ok$next[0:0]$1740 $3\core_rego_ok$next[0:0]$1842 - assign $1\core_spr1$next[9:0]$1741 $3\core_spr1$next[9:0]$1843 - assign $1\core_spr1_ok$next[0:0]$1742 $3\core_spr1_ok$next[0:0]$1844 - assign $1\core_spro$next[9:0]$1743 $3\core_spro$next[9:0]$1845 - assign $1\core_spro_ok$next[0:0]$1744 $3\core_spro_ok$next[0:0]$1846 - assign $1\core_xer_in$next[2:0]$1745 $3\core_xer_in$next[2:0]$1847 - assign $1\core_xer_out$next[0:0]$1746 $3\core_xer_out$next[0:0]$1848 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" - switch \$41 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $3\core_core_is_32bit$next[0:0]$1808 $3\core_core_cr_wr_ok$next[0:0]$1803 $3\core_core_cr_wr$next[7:0]$1802 $3\core_core_cr_rd_ok$next[0:0]$1801 $3\core_core_cr_rd$next[7:0]$1800 $3\core_core_trapaddr$next[12:0]$1815 $3\core_core_traptype$next[6:0]$1816 $3\core_core_input_carry$next[1:0]$1805 $3\core_core_oe_ok$next[0:0]$1812 $3\core_core_oe$next[0:0]$1811 $3\core_core_rc_ok$next[0:0]$1814 $3\core_core_rc$next[0:0]$1813 $3\core_core_lk$next[0:0]$1809 $3\core_core_fn_unit$next[11:0]$1804 $3\core_core_insn_type$next[6:0]$1807 $3\core_core_insn$next[31:0]$1806 $3\core_core_cia$next[63:0]$1799 $3\core_core_msr$next[63:0]$1810 $3\core_cr_out_ok$next[0:0]$1824 $3\core_cr_out$next[2:0]$1823 $3\core_cr_in2_ok$40$next[0:0]$1821 $3\core_cr_in2$39$next[2:0]$1819 $3\core_cr_in2_ok$next[0:0]$1822 $3\core_cr_in2$next[2:0]$1820 $3\core_cr_in1_ok$next[0:0]$1818 $3\core_cr_in1$next[2:0]$1817 $3\core_fasto2_ok$next[0:0]$1834 $3\core_fasto2$next[2:0]$1833 $3\core_fasto1_ok$next[0:0]$1832 $3\core_fasto1$next[2:0]$1831 $3\core_fast2_ok$next[0:0]$1830 $3\core_fast2$next[2:0]$1829 $3\core_fast1_ok$next[0:0]$1828 $3\core_fast1$next[2:0]$1827 $3\core_xer_out$next[0:0]$1848 $3\core_xer_in$next[2:0]$1847 $3\core_spr1_ok$next[0:0]$1844 $3\core_spr1$next[9:0]$1843 $3\core_spro_ok$next[0:0]$1846 $3\core_spro$next[9:0]$1845 $3\core_reg3_ok$next[0:0]$1840 $3\core_reg3$next[4:0]$1839 $3\core_reg2_ok$next[0:0]$1838 $3\core_reg2$next[4:0]$1837 $3\core_reg1_ok$next[0:0]$1836 $3\core_reg1$next[4:0]$1835 $3\core_ea_ok$next[0:0]$1826 $3\core_ea$next[4:0]$1825 $3\core_rego_ok$next[0:0]$1842 $3\core_rego$next[4:0]$1841 $3\core_asmcode$next[7:0]$1798 } 321'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\core_asmcode$next[7:0]$1798 \core_asmcode - assign $3\core_core_cia$next[63:0]$1799 \core_core_cia - assign $3\core_core_cr_rd$next[7:0]$1800 \core_core_cr_rd - assign $3\core_core_cr_rd_ok$next[0:0]$1801 \core_core_cr_rd_ok - assign $3\core_core_cr_wr$next[7:0]$1802 \core_core_cr_wr - assign $3\core_core_cr_wr_ok$next[0:0]$1803 \core_core_cr_wr_ok - assign $3\core_core_fn_unit$next[11:0]$1804 \core_core_fn_unit - assign $3\core_core_input_carry$next[1:0]$1805 \core_core_input_carry - assign $3\core_core_insn$next[31:0]$1806 \core_core_insn - assign $3\core_core_insn_type$next[6:0]$1807 \core_core_insn_type - assign $3\core_core_is_32bit$next[0:0]$1808 \core_core_is_32bit - assign $3\core_core_lk$next[0:0]$1809 \core_core_lk - assign $3\core_core_msr$next[63:0]$1810 \core_core_msr - assign $3\core_core_oe$next[0:0]$1811 \core_core_oe - assign $3\core_core_oe_ok$next[0:0]$1812 \core_core_oe_ok - assign $3\core_core_rc$next[0:0]$1813 \core_core_rc - assign $3\core_core_rc_ok$next[0:0]$1814 \core_core_rc_ok - assign $3\core_core_trapaddr$next[12:0]$1815 \core_core_trapaddr - assign $3\core_core_traptype$next[6:0]$1816 \core_core_traptype - assign $3\core_cr_in1$next[2:0]$1817 \core_cr_in1 - assign $3\core_cr_in1_ok$next[0:0]$1818 \core_cr_in1_ok - assign $3\core_cr_in2$39$next[2:0]$1819 \core_cr_in2$39 - assign $3\core_cr_in2$next[2:0]$1820 \core_cr_in2 - assign $3\core_cr_in2_ok$40$next[0:0]$1821 \core_cr_in2_ok$40 - assign $3\core_cr_in2_ok$next[0:0]$1822 \core_cr_in2_ok - assign $3\core_cr_out$next[2:0]$1823 \core_cr_out - assign $3\core_cr_out_ok$next[0:0]$1824 \core_cr_out_ok - assign $3\core_ea$next[4:0]$1825 \core_ea - assign $3\core_ea_ok$next[0:0]$1826 \core_ea_ok - assign $3\core_fast1$next[2:0]$1827 \core_fast1 - assign $3\core_fast1_ok$next[0:0]$1828 \core_fast1_ok - assign $3\core_fast2$next[2:0]$1829 \core_fast2 - assign $3\core_fast2_ok$next[0:0]$1830 \core_fast2_ok - assign $3\core_fasto1$next[2:0]$1831 \core_fasto1 - assign $3\core_fasto1_ok$next[0:0]$1832 \core_fasto1_ok - assign $3\core_fasto2$next[2:0]$1833 \core_fasto2 - assign $3\core_fasto2_ok$next[0:0]$1834 \core_fasto2_ok - assign $3\core_reg1$next[4:0]$1835 \core_reg1 - assign $3\core_reg1_ok$next[0:0]$1836 \core_reg1_ok - assign $3\core_reg2$next[4:0]$1837 \core_reg2 - assign $3\core_reg2_ok$next[0:0]$1838 \core_reg2_ok - assign $3\core_reg3$next[4:0]$1839 \core_reg3 - assign $3\core_reg3_ok$next[0:0]$1840 \core_reg3_ok - assign $3\core_rego$next[4:0]$1841 \core_rego - assign $3\core_rego_ok$next[0:0]$1842 \core_rego_ok - assign $3\core_spr1$next[9:0]$1843 \core_spr1 - assign $3\core_spr1_ok$next[0:0]$1844 \core_spr1_ok - assign $3\core_spro$next[9:0]$1845 \core_spro - assign $3\core_spro_ok$next[0:0]$1846 \core_spro_ok - assign $3\core_xer_in$next[2:0]$1847 \core_xer_in - assign $3\core_xer_out$next[0:0]$1848 \core_xer_out - end - case - assign $1\core_asmcode$next[7:0]$1696 \core_asmcode - assign $1\core_core_cia$next[63:0]$1697 \core_core_cia - assign $1\core_core_cr_rd$next[7:0]$1698 \core_core_cr_rd - assign $1\core_core_cr_rd_ok$next[0:0]$1699 \core_core_cr_rd_ok - assign $1\core_core_cr_wr$next[7:0]$1700 \core_core_cr_wr - assign $1\core_core_cr_wr_ok$next[0:0]$1701 \core_core_cr_wr_ok - assign $1\core_core_fn_unit$next[11:0]$1702 \core_core_fn_unit - assign $1\core_core_input_carry$next[1:0]$1703 \core_core_input_carry - assign $1\core_core_insn$next[31:0]$1704 \core_core_insn - assign $1\core_core_insn_type$next[6:0]$1705 \core_core_insn_type - assign $1\core_core_is_32bit$next[0:0]$1706 \core_core_is_32bit - assign $1\core_core_lk$next[0:0]$1707 \core_core_lk - assign $1\core_core_msr$next[63:0]$1708 \core_core_msr - assign $1\core_core_oe$next[0:0]$1709 \core_core_oe - assign $1\core_core_oe_ok$next[0:0]$1710 \core_core_oe_ok - assign $1\core_core_rc$next[0:0]$1711 \core_core_rc - assign $1\core_core_rc_ok$next[0:0]$1712 \core_core_rc_ok - assign $1\core_core_trapaddr$next[12:0]$1713 \core_core_trapaddr - assign $1\core_core_traptype$next[6:0]$1714 \core_core_traptype - assign $1\core_cr_in1$next[2:0]$1715 \core_cr_in1 - assign $1\core_cr_in1_ok$next[0:0]$1716 \core_cr_in1_ok - assign $1\core_cr_in2$39$next[2:0]$1717 \core_cr_in2$39 - assign $1\core_cr_in2$next[2:0]$1718 \core_cr_in2 - assign $1\core_cr_in2_ok$40$next[0:0]$1719 \core_cr_in2_ok$40 - assign $1\core_cr_in2_ok$next[0:0]$1720 \core_cr_in2_ok - assign $1\core_cr_out$next[2:0]$1721 \core_cr_out - assign $1\core_cr_out_ok$next[0:0]$1722 \core_cr_out_ok - assign $1\core_ea$next[4:0]$1723 \core_ea - assign $1\core_ea_ok$next[0:0]$1724 \core_ea_ok - assign $1\core_fast1$next[2:0]$1725 \core_fast1 - assign $1\core_fast1_ok$next[0:0]$1726 \core_fast1_ok - assign $1\core_fast2$next[2:0]$1727 \core_fast2 - assign $1\core_fast2_ok$next[0:0]$1728 \core_fast2_ok - assign $1\core_fasto1$next[2:0]$1729 \core_fasto1 - assign $1\core_fasto1_ok$next[0:0]$1730 \core_fasto1_ok - assign $1\core_fasto2$next[2:0]$1731 \core_fasto2 - assign $1\core_fasto2_ok$next[0:0]$1732 \core_fasto2_ok - assign $1\core_reg1$next[4:0]$1733 \core_reg1 - assign $1\core_reg1_ok$next[0:0]$1734 \core_reg1_ok - assign $1\core_reg2$next[4:0]$1735 \core_reg2 - assign $1\core_reg2_ok$next[0:0]$1736 \core_reg2_ok - assign $1\core_reg3$next[4:0]$1737 \core_reg3 - assign $1\core_reg3_ok$next[0:0]$1738 \core_reg3_ok - assign $1\core_rego$next[4:0]$1739 \core_rego - assign $1\core_rego_ok$next[0:0]$1740 \core_rego_ok - assign $1\core_spr1$next[9:0]$1741 \core_spr1 - assign $1\core_spr1_ok$next[0:0]$1742 \core_spr1_ok - assign $1\core_spro$next[9:0]$1743 \core_spro - assign $1\core_spro_ok$next[0:0]$1744 \core_spro_ok - assign $1\core_xer_in$next[2:0]$1745 \core_xer_in - assign $1\core_xer_out$next[0:0]$1746 \core_xer_out - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $4\core_rego_ok$next[0:0]$1865 1'0 - assign $4\core_ea_ok$next[0:0]$1857 1'0 - assign $4\core_reg1_ok$next[0:0]$1862 1'0 - assign $4\core_reg2_ok$next[0:0]$1863 1'0 - assign $4\core_reg3_ok$next[0:0]$1864 1'0 - assign $4\core_spro_ok$next[0:0]$1867 1'0 - assign $4\core_spr1_ok$next[0:0]$1866 1'0 - assign $4\core_fast1_ok$next[0:0]$1858 1'0 - assign $4\core_fast2_ok$next[0:0]$1859 1'0 - assign $4\core_fasto1_ok$next[0:0]$1860 1'0 - assign $4\core_fasto2_ok$next[0:0]$1861 1'0 - assign $4\core_cr_in1_ok$next[0:0]$1853 1'0 - assign $4\core_cr_in2_ok$next[0:0]$1855 1'0 - assign $4\core_cr_in2_ok$40$next[0:0]$1854 1'0 - assign $4\core_cr_out_ok$next[0:0]$1856 1'0 - assign $4\core_core_rc_ok$next[0:0]$1852 1'0 - assign $4\core_core_oe_ok$next[0:0]$1851 1'0 - assign $4\core_core_cr_rd_ok$next[0:0]$1849 1'0 - assign $4\core_core_cr_wr_ok$next[0:0]$1850 1'0 - case - assign $4\core_core_cr_rd_ok$next[0:0]$1849 $1\core_core_cr_rd_ok$next[0:0]$1699 - assign $4\core_core_cr_wr_ok$next[0:0]$1850 $1\core_core_cr_wr_ok$next[0:0]$1701 - assign $4\core_core_oe_ok$next[0:0]$1851 $1\core_core_oe_ok$next[0:0]$1710 - assign $4\core_core_rc_ok$next[0:0]$1852 $1\core_core_rc_ok$next[0:0]$1712 - assign $4\core_cr_in1_ok$next[0:0]$1853 $1\core_cr_in1_ok$next[0:0]$1716 - assign $4\core_cr_in2_ok$40$next[0:0]$1854 $1\core_cr_in2_ok$40$next[0:0]$1719 - assign $4\core_cr_in2_ok$next[0:0]$1855 $1\core_cr_in2_ok$next[0:0]$1720 - assign $4\core_cr_out_ok$next[0:0]$1856 $1\core_cr_out_ok$next[0:0]$1722 - assign $4\core_ea_ok$next[0:0]$1857 $1\core_ea_ok$next[0:0]$1724 - assign $4\core_fast1_ok$next[0:0]$1858 $1\core_fast1_ok$next[0:0]$1726 - assign $4\core_fast2_ok$next[0:0]$1859 $1\core_fast2_ok$next[0:0]$1728 - assign $4\core_fasto1_ok$next[0:0]$1860 $1\core_fasto1_ok$next[0:0]$1730 - assign $4\core_fasto2_ok$next[0:0]$1861 $1\core_fasto2_ok$next[0:0]$1732 - assign $4\core_reg1_ok$next[0:0]$1862 $1\core_reg1_ok$next[0:0]$1734 - assign $4\core_reg2_ok$next[0:0]$1863 $1\core_reg2_ok$next[0:0]$1736 - assign $4\core_reg3_ok$next[0:0]$1864 $1\core_reg3_ok$next[0:0]$1738 - assign $4\core_rego_ok$next[0:0]$1865 $1\core_rego_ok$next[0:0]$1740 - assign $4\core_spr1_ok$next[0:0]$1866 $1\core_spr1_ok$next[0:0]$1742 - assign $4\core_spro_ok$next[0:0]$1867 $1\core_spro_ok$next[0:0]$1744 - end - sync always - update \core_asmcode$next $0\core_asmcode$next[7:0]$1645 - update \core_core_cia$next $0\core_core_cia$next[63:0]$1646 - update \core_core_cr_rd$next $0\core_core_cr_rd$next[7:0]$1647 - update \core_core_cr_rd_ok$next $0\core_core_cr_rd_ok$next[0:0]$1648 - update \core_core_cr_wr$next $0\core_core_cr_wr$next[7:0]$1649 - update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$1650 - update \core_core_fn_unit$next $0\core_core_fn_unit$next[11:0]$1651 - update \core_core_input_carry$next $0\core_core_input_carry$next[1:0]$1652 - update \core_core_insn$next $0\core_core_insn$next[31:0]$1653 - update \core_core_insn_type$next $0\core_core_insn_type$next[6:0]$1654 - update \core_core_is_32bit$next $0\core_core_is_32bit$next[0:0]$1655 - update \core_core_lk$next $0\core_core_lk$next[0:0]$1656 - update \core_core_msr$next $0\core_core_msr$next[63:0]$1657 - update \core_core_oe$next $0\core_core_oe$next[0:0]$1658 - update \core_core_oe_ok$next $0\core_core_oe_ok$next[0:0]$1659 - update \core_core_rc$next $0\core_core_rc$next[0:0]$1660 - update \core_core_rc_ok$next $0\core_core_rc_ok$next[0:0]$1661 - update \core_core_trapaddr$next $0\core_core_trapaddr$next[12:0]$1662 - update \core_core_traptype$next $0\core_core_traptype$next[6:0]$1663 - update \core_cr_in1$next $0\core_cr_in1$next[2:0]$1664 - update \core_cr_in1_ok$next $0\core_cr_in1_ok$next[0:0]$1665 - update \core_cr_in2$39$next $0\core_cr_in2$39$next[2:0]$1666 - update \core_cr_in2$next $0\core_cr_in2$next[2:0]$1667 - update \core_cr_in2_ok$40$next $0\core_cr_in2_ok$40$next[0:0]$1668 - update \core_cr_in2_ok$next $0\core_cr_in2_ok$next[0:0]$1669 - update \core_cr_out$next $0\core_cr_out$next[2:0]$1670 - update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$1671 - update \core_ea$next $0\core_ea$next[4:0]$1672 - update \core_ea_ok$next $0\core_ea_ok$next[0:0]$1673 - update \core_fast1$next $0\core_fast1$next[2:0]$1674 - update \core_fast1_ok$next $0\core_fast1_ok$next[0:0]$1675 - update \core_fast2$next $0\core_fast2$next[2:0]$1676 - update \core_fast2_ok$next $0\core_fast2_ok$next[0:0]$1677 - update \core_fasto1$next $0\core_fasto1$next[2:0]$1678 - update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$1679 - update \core_fasto2$next $0\core_fasto2$next[2:0]$1680 - update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$1681 - update \core_reg1$next $0\core_reg1$next[4:0]$1682 - update \core_reg1_ok$next $0\core_reg1_ok$next[0:0]$1683 - update \core_reg2$next $0\core_reg2$next[4:0]$1684 - update \core_reg2_ok$next $0\core_reg2_ok$next[0:0]$1685 - update \core_reg3$next $0\core_reg3$next[4:0]$1686 - update \core_reg3_ok$next $0\core_reg3_ok$next[0:0]$1687 - update \core_rego$next $0\core_rego$next[4:0]$1688 - update \core_rego_ok$next $0\core_rego_ok$next[0:0]$1689 - update \core_spr1$next $0\core_spr1$next[9:0]$1690 - update \core_spr1_ok$next $0\core_spr1_ok$next[0:0]$1691 - update \core_spro$next $0\core_spro$next[9:0]$1692 - update \core_spro_ok$next $0\core_spro_ok$next[0:0]$1693 - update \core_xer_in$next $0\core_xer_in$next[2:0]$1694 - update \core_xer_out$next $0\core_xer_out$next[0:0]$1695 - end - attribute \src "libresoc.v:49720.3-49728.6" - process $proc$libresoc.v:49720$1868 - assign { } { } - assign { } { } - assign $0\jtag_dmi0_ack_o$next[0:0]$1869 $1\jtag_dmi0_ack_o$next[0:0]$1870 - attribute \src "libresoc.v:49721.5-49721.29" - switch \initial - attribute \src "libresoc.v:49721.9-49721.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_dmi0_ack_o$next[0:0]$1870 1'0 - case - assign $1\jtag_dmi0_ack_o$next[0:0]$1870 \dbg_dmi_ack_o - end - sync always - update \jtag_dmi0_ack_o$next $0\jtag_dmi0_ack_o$next[0:0]$1869 - end - attribute \src "libresoc.v:49729.3-49737.6" - process $proc$libresoc.v:49729$1871 - assign { } { } - assign { } { } - assign $0\jtag_dmi0_dout$next[63:0]$1872 $1\jtag_dmi0_dout$next[63:0]$1873 - attribute \src "libresoc.v:49730.5-49730.29" - switch \initial - attribute \src "libresoc.v:49730.9-49730.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_dmi0_dout$next[63:0]$1873 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $1\jtag_dmi0_dout$next[63:0]$1873 \dbg_dmi_dout - end - sync always - update \jtag_dmi0_dout$next $0\jtag_dmi0_dout$next[63:0]$1872 - end - attribute \src "libresoc.v:49738.3-49746.6" - process $proc$libresoc.v:49738$1874 - assign { } { } - assign { } { } - assign $0\dec2_cur_eint$next[0:0]$1875 $1\dec2_cur_eint$next[0:0]$1876 - attribute \src "libresoc.v:49739.5-49739.29" - switch \initial - attribute \src "libresoc.v:49739.9-49739.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dec2_cur_eint$next[0:0]$1876 1'0 - case - assign $1\dec2_cur_eint$next[0:0]$1876 \xics_icp_core_irq_o - end - sync always - update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$1875 - end - attribute \src "libresoc.v:49747.3-49783.6" - process $proc$libresoc.v:49747$1877 - assign { } { } - assign { } { } - assign { } { } - assign $0\raw_insn_i$next[31:0]$1878 $4\raw_insn_i$next[31:0]$1882 - attribute \src "libresoc.v:49748.5-49748.29" - switch \initial - attribute \src "libresoc.v:49748.9-49748.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\raw_insn_i$next[31:0]$1879 0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\raw_insn_i$next[31:0]$1879 $2\raw_insn_i$next[31:0]$1880 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\raw_insn_i$next[31:0]$1880 \raw_insn_i - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\raw_insn_i$next[31:0]$1880 \dec2_raw_opcode_in - end - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\raw_insn_i$next[31:0]$1879 $3\raw_insn_i$next[31:0]$1881 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" - switch \$43 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\raw_insn_i$next[31:0]$1881 0 - case - assign $3\raw_insn_i$next[31:0]$1881 \raw_insn_i - end - case - assign $1\raw_insn_i$next[31:0]$1879 \raw_insn_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\raw_insn_i$next[31:0]$1882 0 - case - assign $4\raw_insn_i$next[31:0]$1882 $1\raw_insn_i$next[31:0]$1879 - end - sync always - update \raw_insn_i$next $0\raw_insn_i$next[31:0]$1878 - end - attribute \src "libresoc.v:49784.3-49820.6" - process $proc$libresoc.v:49784$1883 - assign { } { } - assign { } { } - assign { } { } - assign $0\bigendian_i$next[0:0]$1884 $4\bigendian_i$next[0:0]$1888 - attribute \src "libresoc.v:49785.5-49785.29" - switch \initial - attribute \src "libresoc.v:49785.9-49785.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\bigendian_i$next[0:0]$1885 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\bigendian_i$next[0:0]$1885 $2\bigendian_i$next[0:0]$1886 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\bigendian_i$next[0:0]$1886 \bigendian_i - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\bigendian_i$next[0:0]$1886 \core_bigendian_i - end - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\bigendian_i$next[0:0]$1885 $3\bigendian_i$next[0:0]$1887 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" - switch \$45 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\bigendian_i$next[0:0]$1887 1'0 - case - assign $3\bigendian_i$next[0:0]$1887 \bigendian_i - end - case - assign $1\bigendian_i$next[0:0]$1885 \bigendian_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\bigendian_i$next[0:0]$1888 1'0 - case - assign $4\bigendian_i$next[0:0]$1888 $1\bigendian_i$next[0:0]$1885 - end - sync always - update \bigendian_i$next $0\bigendian_i$next[0:0]$1884 - end - attribute \src "libresoc.v:49821.3-49836.6" - process $proc$libresoc.v:49821$1889 - assign { } { } - assign { } { } - assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:49822.5-49822.29" - switch \initial - attribute \src "libresoc.v:49822.9-49822.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - switch \$51 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\imem_a_pc_i[47:0] \pc [47:0] - case - assign $2\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 - end - case - assign $1\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 - end - sync always - update \imem_a_pc_i $0\imem_a_pc_i[47:0] - end - attribute \src "libresoc.v:49837.3-49861.6" - process $proc$libresoc.v:49837$1890 - assign { } { } - assign { } { } - assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:49838.5-49838.29" - switch \initial - attribute \src "libresoc.v:49838.9-49838.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - switch \$57 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\imem_a_valid_i[0:0] 1'1 - case - assign $2\imem_a_valid_i[0:0] 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\imem_a_valid_i[0:0] 1'1 - case - assign $3\imem_a_valid_i[0:0] 1'0 - end - case - assign $1\imem_a_valid_i[0:0] 1'0 - end - sync always - update \imem_a_valid_i $0\imem_a_valid_i[0:0] - end - attribute \src "libresoc.v:49862.3-49886.6" - process $proc$libresoc.v:49862$1891 - assign { } { } - assign { } { } - assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:49863.5-49863.29" - switch \initial - attribute \src "libresoc.v:49863.9-49863.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - switch \$63 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\imem_f_valid_i[0:0] 1'1 - case - assign $2\imem_f_valid_i[0:0] 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\imem_f_valid_i[0:0] 1'1 - case - assign $3\imem_f_valid_i[0:0] 1'0 - end - case - assign $1\imem_f_valid_i[0:0] 1'0 - end - sync always - update \imem_f_valid_i $0\imem_f_valid_i[0:0] - end - attribute \src "libresoc.v:49887.3-49907.6" - process $proc$libresoc.v:49887$1892 - assign { } { } - assign { } { } - assign { } { } - assign $0\dec2_cur_pc$next[63:0]$1893 $3\dec2_cur_pc$next[63:0]$1896 - attribute \src "libresoc.v:49888.5-49888.29" - switch \initial - attribute \src "libresoc.v:49888.9-49888.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec2_cur_pc$next[63:0]$1894 $2\dec2_cur_pc$next[63:0]$1895 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - switch \$69 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dec2_cur_pc$next[63:0]$1895 \pc - case - assign $2\dec2_cur_pc$next[63:0]$1895 \dec2_cur_pc - end - case - assign $1\dec2_cur_pc$next[63:0]$1894 \dec2_cur_pc - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dec2_cur_pc$next[63:0]$1896 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\dec2_cur_pc$next[63:0]$1896 $1\dec2_cur_pc$next[63:0]$1894 - end - sync always - update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$1893 - end - attribute \src "libresoc.v:49908.3-49937.6" - process $proc$libresoc.v:49908$1897 - assign { } { } - assign { } { } - assign { } { } - assign $0\msr_read$next[0:0]$1898 $4\msr_read$next[0:0]$1902 - attribute \src "libresoc.v:49909.5-49909.29" - switch \initial - attribute \src "libresoc.v:49909.9-49909.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\msr_read$next[0:0]$1899 $2\msr_read$next[0:0]$1900 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - switch \$75 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\msr_read$next[0:0]$1900 1'0 - case - assign $2\msr_read$next[0:0]$1900 \msr_read - end - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\msr_read$next[0:0]$1899 $3\msr_read$next[0:0]$1901 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:257" - switch \$77 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\msr_read$next[0:0]$1901 1'1 - case - assign $3\msr_read$next[0:0]$1901 \msr_read - end - case - assign $1\msr_read$next[0:0]$1899 \msr_read - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\msr_read$next[0:0]$1902 1'1 - case - assign $4\msr_read$next[0:0]$1902 $1\msr_read$next[0:0]$1899 - end - sync always - update \msr_read$next $0\msr_read$next[0:0]$1898 - end - attribute \src "libresoc.v:49938.3-49983.6" - process $proc$libresoc.v:49938$1903 - assign { } { } - assign { } { } - assign { } { } - assign $0\fsm_state$next[1:0]$1904 $5\fsm_state$next[1:0]$1909 - attribute \src "libresoc.v:49939.5-49939.29" - switch \initial - attribute \src "libresoc.v:49939.9-49939.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\fsm_state$next[1:0]$1905 $2\fsm_state$next[1:0]$1906 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - switch \$83 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fsm_state$next[1:0]$1906 2'01 - case - assign $2\fsm_state$next[1:0]$1906 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\fsm_state$next[1:0]$1905 $3\fsm_state$next[1:0]$1907 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $3\fsm_state$next[1:0]$1907 \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\fsm_state$next[1:0]$1907 2'10 - end - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\fsm_state$next[1:0]$1905 2'11 - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\fsm_state$next[1:0]$1905 $4\fsm_state$next[1:0]$1908 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" - switch \$85 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$next[1:0]$1908 2'00 - case - assign $4\fsm_state$next[1:0]$1908 \fsm_state - end - case - assign $1\fsm_state$next[1:0]$1905 \fsm_state - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\fsm_state$next[1:0]$1909 2'00 - case - assign $5\fsm_state$next[1:0]$1909 $1\fsm_state$next[1:0]$1905 - end - sync always - update \fsm_state$next $0\fsm_state$next[1:0]$1904 - end - attribute \src "libresoc.v:49984.3-49993.6" - process $proc$libresoc.v:49984$1910 - assign { } { } - assign { } { } - assign $0\delay$next[1:0]$1911 $1\delay$next[1:0]$1912 - attribute \src "libresoc.v:49985.5-49985.29" - switch \initial - attribute \src "libresoc.v:49985.9-49985.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:158" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\delay$next[1:0]$1912 \$5 [1:0] - case - assign $1\delay$next[1:0]$1912 \delay - end - sync always - update \delay$next $0\delay$next[1:0]$1911 - end - attribute \src "libresoc.v:49994.3-50012.6" - process $proc$libresoc.v:49994$1913 - assign { } { } - assign { } { } - assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] - attribute \src "libresoc.v:49995.5-49995.29" - switch \initial - attribute \src "libresoc.v:49995.9-49995.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - switch \$91 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\core_stopped_i[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\core_stopped_i[0:0] 1'1 - end - case - assign $1\core_stopped_i[0:0] 1'0 - end - sync always - update \core_stopped_i $0\core_stopped_i[0:0] - end - attribute \src "libresoc.v:50013.3-50031.6" - process $proc$libresoc.v:50013$1914 - assign { } { } - assign { } { } - assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:50014.5-50014.29" - switch \initial - attribute \src "libresoc.v:50014.9-50014.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" - switch \$97 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\dbg_core_stopped_i[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\dbg_core_stopped_i[0:0] 1'1 - end - case - assign $1\dbg_core_stopped_i[0:0] 1'0 - end - sync always - update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] - end - attribute \src "libresoc.v:50032.3-50052.6" - process $proc$libresoc.v:50032$1915 - assign { } { } - assign { } { } - assign { } { } - assign $0\dec2_cur_msr$next[63:0]$1916 $3\dec2_cur_msr$next[63:0]$1919 - attribute \src "libresoc.v:50033.5-50033.29" - switch \initial - attribute \src "libresoc.v:50033.9-50033.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec2_cur_msr$next[63:0]$1917 $2\dec2_cur_msr$next[63:0]$1918 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:257" - switch \$99 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dec2_cur_msr$next[63:0]$1918 \msr__data_o - case - assign $2\dec2_cur_msr$next[63:0]$1918 \dec2_cur_msr - end - case - assign $1\dec2_cur_msr$next[63:0]$1917 \dec2_cur_msr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dec2_cur_msr$next[63:0]$1919 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\dec2_cur_msr$next[63:0]$1919 $1\dec2_cur_msr$next[63:0]$1917 - end - sync always - update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$1916 - end - attribute \src "libresoc.v:50053.3-50071.6" - process $proc$libresoc.v:50053$1920 - assign { } { } - assign { } { } - assign $0\dec2_raw_opcode_in[31:0] $1\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:50054.5-50054.29" - switch \initial - attribute \src "libresoc.v:50054.9-50054.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec2_raw_opcode_in[31:0] $2\dec2_raw_opcode_in[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\dec2_raw_opcode_in[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\dec2_raw_opcode_in[31:0] \$101 - end - case - assign $1\dec2_raw_opcode_in[31:0] 0 - end - sync always - update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] - end - attribute \src "libresoc.v:50072.3-50103.6" - process $proc$libresoc.v:50072$1921 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\core_dec$next[63:0]$1922 $3\core_dec$next[63:0]$1934 - assign $0\core_eint$next[0:0]$1923 $3\core_eint$next[0:0]$1935 - assign $0\core_msr$next[63:0]$1924 $3\core_msr$next[63:0]$1936 - assign $0\core_pc$next[63:0]$1925 $3\core_pc$next[63:0]$1937 - attribute \src "libresoc.v:50073.5-50073.29" - switch \initial - attribute \src "libresoc.v:50073.9-50073.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\core_dec$next[63:0]$1926 $2\core_dec$next[63:0]$1930 - assign $1\core_eint$next[0:0]$1927 $2\core_eint$next[0:0]$1931 - assign $1\core_msr$next[63:0]$1928 $2\core_msr$next[63:0]$1932 - assign $1\core_pc$next[63:0]$1929 $2\core_pc$next[63:0]$1933 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\core_dec$next[63:0]$1930 \core_dec - assign $2\core_eint$next[0:0]$1931 \core_eint - assign $2\core_msr$next[63:0]$1932 \core_msr - assign $2\core_pc$next[63:0]$1933 \core_pc - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\core_dec$next[63:0]$1930 $2\core_eint$next[0:0]$1931 $2\core_msr$next[63:0]$1932 $2\core_pc$next[63:0]$1933 } { \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } - end - case - assign $1\core_dec$next[63:0]$1926 \core_dec - assign $1\core_eint$next[0:0]$1927 \core_eint - assign $1\core_msr$next[63:0]$1928 \core_msr - assign $1\core_pc$next[63:0]$1929 \core_pc - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $3\core_pc$next[63:0]$1937 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_msr$next[63:0]$1936 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_eint$next[0:0]$1935 1'0 - assign $3\core_dec$next[63:0]$1934 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\core_dec$next[63:0]$1934 $1\core_dec$next[63:0]$1926 - assign $3\core_eint$next[0:0]$1935 $1\core_eint$next[0:0]$1927 - assign $3\core_msr$next[63:0]$1936 $1\core_msr$next[63:0]$1928 - assign $3\core_pc$next[63:0]$1937 $1\core_pc$next[63:0]$1929 - end - sync always - update \core_dec$next $0\core_dec$next[63:0]$1922 - update \core_eint$next $0\core_eint$next[0:0]$1923 - update \core_msr$next $0\core_msr$next[63:0]$1924 - update \core_pc$next $0\core_pc$next[63:0]$1925 - end - attribute \src "libresoc.v:50104.3-50127.6" - process $proc$libresoc.v:50104$1938 - assign { } { } - assign { } { } - assign { } { } - assign $0\ilatch$next[31:0]$1939 $3\ilatch$next[31:0]$1942 - attribute \src "libresoc.v:50105.5-50105.29" - switch \initial - attribute \src "libresoc.v:50105.9-50105.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\ilatch$next[31:0]$1940 $2\ilatch$next[31:0]$1941 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\ilatch$next[31:0]$1941 \ilatch - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\ilatch$next[31:0]$1941 \$105 - end - case - assign $1\ilatch$next[31:0]$1940 \ilatch - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ilatch$next[31:0]$1942 0 - case - assign $3\ilatch$next[31:0]$1942 $1\ilatch$next[31:0]$1940 - end - sync always - update \ilatch$next $0\ilatch$next[31:0]$1939 - end - attribute \src "libresoc.v:50128.3-50147.6" - process $proc$libresoc.v:50128$1943 - assign { } { } - assign { } { } - assign $0\ivalid_i[0:0] $1\ivalid_i[0:0] - attribute \src "libresoc.v:50129.5-50129.29" - switch \initial - attribute \src "libresoc.v:50129.9-50129.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\ivalid_i[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\ivalid_i[0:0] $2\ivalid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - switch \$109 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ivalid_i[0:0] 1'1 - case - assign $2\ivalid_i[0:0] 1'0 - end - case - assign $1\ivalid_i[0:0] 1'0 - end - sync always - update \ivalid_i $0\ivalid_i[0:0] - end - connect \$99 $not$libresoc.v:48713$1443_Y - connect \$102 $mul$libresoc.v:48714$1444_Y - connect \$101 $shr$libresoc.v:48715$1445_Y [31:0] - connect \$106 $mul$libresoc.v:48716$1446_Y - connect \$105 $shr$libresoc.v:48717$1447_Y [31:0] - connect \$10 $ne$libresoc.v:48718$1448_Y - connect \$109 $ne$libresoc.v:48719$1449_Y - connect \$111 $pos$libresoc.v:48720$1451_Y - connect \$113 $pos$libresoc.v:48721$1453_Y - connect \$117 $sub$libresoc.v:48722$1454_Y - connect \$121 $add$libresoc.v:48723$1455_Y - connect \$12 $not$libresoc.v:48724$1456_Y - connect \$14 $and$libresoc.v:48725$1457_Y - connect \$17 $add$libresoc.v:48726$1458_Y - connect \$19 $not$libresoc.v:48727$1459_Y - connect \$21 $not$libresoc.v:48728$1460_Y - connect \$23 $not$libresoc.v:48729$1461_Y - connect \$25 $not$libresoc.v:48730$1462_Y - connect \$27 $not$libresoc.v:48731$1463_Y - connect \$29 $not$libresoc.v:48732$1464_Y - connect \$31 $not$libresoc.v:48733$1465_Y - connect \$33 $and$libresoc.v:48734$1466_Y - connect \$36 $and$libresoc.v:48735$1467_Y - connect \$35 $reduce_or$libresoc.v:48736$1468_Y - connect \$3 $ne$libresoc.v:48737$1469_Y - connect \$41 $not$libresoc.v:48738$1470_Y - connect \$43 $not$libresoc.v:48739$1471_Y - connect \$45 $not$libresoc.v:48740$1472_Y - connect \$47 $not$libresoc.v:48741$1473_Y - connect \$49 $not$libresoc.v:48742$1474_Y - connect \$51 $and$libresoc.v:48743$1475_Y - connect \$53 $not$libresoc.v:48744$1476_Y - connect \$55 $not$libresoc.v:48745$1477_Y - connect \$57 $and$libresoc.v:48746$1478_Y - connect \$59 $not$libresoc.v:48747$1479_Y - connect \$61 $not$libresoc.v:48748$1480_Y - connect \$63 $and$libresoc.v:48749$1481_Y - connect \$65 $not$libresoc.v:48750$1482_Y - connect \$67 $not$libresoc.v:48751$1483_Y - connect \$6 $sub$libresoc.v:48752$1484_Y - connect \$69 $and$libresoc.v:48753$1485_Y - connect \$71 $not$libresoc.v:48754$1486_Y - connect \$73 $not$libresoc.v:48755$1487_Y - connect \$75 $and$libresoc.v:48756$1488_Y - connect \$77 $not$libresoc.v:48757$1489_Y - connect \$79 $not$libresoc.v:48758$1490_Y - connect \$81 $not$libresoc.v:48759$1491_Y - connect \$83 $and$libresoc.v:48760$1492_Y - connect \$85 $not$libresoc.v:48761$1493_Y - connect \$87 $not$libresoc.v:48762$1494_Y - connect \$8 $or$libresoc.v:48763$1495_Y - connect \$89 $not$libresoc.v:48764$1496_Y - connect \$91 $and$libresoc.v:48765$1497_Y - connect \$93 $not$libresoc.v:48766$1498_Y - connect \$95 $not$libresoc.v:48767$1499_Y - connect \$97 $and$libresoc.v:48768$1500_Y - connect \$5 \$6 - connect \$16 \$17 - connect \$116 \$117 - connect \$120 \$121 - connect \intclk_clk 1'0 - connect \intclk_rst 1'0 - connect \corebusy_o 1'0 - connect \cu_st__rel_o 1'0 - connect \cu_ad__rel_o 1'0 - connect \cia__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \core_terminate_o 1'0 - connect \state_nia_wen 4'0000 - connect \msr__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \dmi__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \full_rd2__data_o 0 - connect \full_rd__data_o 6'000000 - connect \issue__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \dbg_core_dbg_msr \dec2_cur_msr - connect \dbg_core_dbg_pc \pc - connect \dbg_terminate_i 1'0 - connect \nia \$17 [63:0] - connect \pc_o \dec2_cur_pc - connect \cu_st__go_i \cu_st__rel_o_rise - connect \cu_ad__go_i 1'0 - connect \cu_st__rel_o_rise \$14 - connect \cu_st__rel_o_dly$next 1'0 - connect \dec2_bigendian \core_bigendian_i - connect \busy_o 1'0 - connect \core_reset_i \$10 - connect \coresync_clk 1'0 - connect \por_clk 1'0 - connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src } -end -attribute \src "libresoc.v:50184.1-50498.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.xics_icp" -attribute \generator "nMigen" -module \xics_icp - attribute \src "libresoc.v:50362.3-50390.6" - wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:50413.3-50421.6" - wire $0\core_irq_o$next[0:0]$2061 - attribute \src "libresoc.v:50304.3-50305.37" - wire $0\core_irq_o[0:0] - attribute \src "libresoc.v:50432.3-50494.6" - wire width 8 $0\cppr$10[7:0]$2065 - attribute \src "libresoc.v:50318.3-50333.6" - wire width 8 $0\cppr$next[7:0]$2044 - attribute \src "libresoc.v:50308.3-50309.25" - wire width 8 $0\cppr[7:0] - attribute \src "libresoc.v:50422.3-50431.6" - wire width 32 $0\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:50185.7-50185.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:50432.3-50494.6" - wire $0\irq$12[0:0]$2066 - attribute \src "libresoc.v:50318.3-50333.6" - wire $0\irq$next[0:0]$2045 - attribute \src "libresoc.v:50312.3-50313.23" - wire $0\irq[0:0] - attribute \src "libresoc.v:50432.3-50494.6" - wire width 8 $0\mfrr$11[7:0]$2067 - attribute \src "libresoc.v:50318.3-50333.6" - wire width 8 $0\mfrr$next[7:0]$2046 - attribute \src "libresoc.v:50310.3-50311.25" - wire width 8 $0\mfrr[7:0] - attribute \src "libresoc.v:50401.3-50412.6" - wire width 8 $0\min_pri[7:0] - attribute \src "libresoc.v:50391.3-50400.6" - wire width 8 $0\pending_priority[7:0] - attribute \src "libresoc.v:50432.3-50494.6" - wire $0\wb_ack$14[0:0]$2068 - attribute \src "libresoc.v:50318.3-50333.6" - wire $0\wb_ack$next[0:0]$2047 - attribute \src "libresoc.v:50316.3-50317.29" - wire $0\wb_ack[0:0] - attribute \src "libresoc.v:50432.3-50494.6" - wire width 32 $0\wb_rd_data$13[31:0]$2069 - attribute \src "libresoc.v:50318.3-50333.6" - wire width 32 $0\wb_rd_data$next[31:0]$2048 - attribute \src "libresoc.v:50314.3-50315.37" - wire width 32 $0\wb_rd_data[31:0] - attribute \src "libresoc.v:50334.3-50361.6" - wire $0\xirr_accept_rd[0:0] - attribute \src "libresoc.v:50432.3-50494.6" - wire width 24 $0\xisr$9[23:0]$2070 - attribute \src "libresoc.v:50318.3-50333.6" - wire width 24 $0\xisr$next[23:0]$2049 - attribute \src "libresoc.v:50306.3-50307.25" - wire width 24 $0\xisr[23:0] - attribute \src "libresoc.v:50362.3-50390.6" - wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:50413.3-50421.6" - wire $1\core_irq_o$next[0:0]$2062 - attribute \src "libresoc.v:50212.7-50212.24" - wire $1\core_irq_o[0:0] - attribute \src "libresoc.v:50432.3-50494.6" - wire width 8 $1\cppr$10[7:0]$2071 - attribute \src "libresoc.v:50318.3-50333.6" - wire width 8 $1\cppr$next[7:0]$2050 - attribute \src "libresoc.v:50216.13-50216.25" - wire width 8 $1\cppr[7:0] - attribute \src "libresoc.v:50422.3-50431.6" - wire width 32 $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:50432.3-50494.6" - wire $1\irq$12[0:0]$2081 - attribute \src "libresoc.v:50318.3-50333.6" - wire $1\irq$next[0:0]$2051 - attribute \src "libresoc.v:50249.7-50249.17" - wire $1\irq[0:0] - attribute \src "libresoc.v:50432.3-50494.6" - wire width 8 $1\mfrr$11[7:0]$2072 - attribute \src "libresoc.v:50318.3-50333.6" - wire width 8 $1\mfrr$next[7:0]$2052 - attribute \src "libresoc.v:50257.13-50257.25" - wire width 8 $1\mfrr[7:0] - attribute \src "libresoc.v:50401.3-50412.6" - wire width 8 $1\min_pri[7:0] - attribute \src "libresoc.v:50391.3-50400.6" - wire width 8 $1\pending_priority[7:0] - attribute \src "libresoc.v:50432.3-50494.6" - wire $1\wb_ack$14[0:0]$2073 - attribute \src "libresoc.v:50318.3-50333.6" - wire $1\wb_ack$next[0:0]$2053 - attribute \src "libresoc.v:50269.7-50269.20" - wire $1\wb_ack[0:0] - attribute \src "libresoc.v:50318.3-50333.6" - wire width 32 $1\wb_rd_data$next[31:0]$2054 - attribute \src "libresoc.v:50277.14-50277.32" - wire width 32 $1\wb_rd_data[31:0] - attribute \src "libresoc.v:50334.3-50361.6" - wire $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:50432.3-50494.6" - wire width 24 $1\xisr$9[23:0]$2078 - attribute \src "libresoc.v:50318.3-50333.6" - wire width 24 $1\xisr$next[23:0]$2055 - attribute \src "libresoc.v:50287.14-50287.31" - wire width 24 $1\xisr[23:0] - attribute \src "libresoc.v:50362.3-50390.6" - wire width 32 $2\be_out[31:0] - attribute \src "libresoc.v:50432.3-50494.6" - wire width 8 $2\cppr$10[7:0]$2074 - attribute \src "libresoc.v:50432.3-50494.6" - wire width 8 $2\mfrr$11[7:0]$2075 - attribute \src "libresoc.v:50334.3-50361.6" - wire $2\xirr_accept_rd[0:0] - attribute \src "libresoc.v:50432.3-50494.6" - wire width 24 $2\xisr$9[23:0]$2079 - attribute \src "libresoc.v:50362.3-50390.6" - wire width 32 $3\be_out[31:0] - attribute \src "libresoc.v:50432.3-50494.6" - wire width 8 $3\cppr$10[7:0]$2076 - attribute \src "libresoc.v:50432.3-50494.6" - wire width 8 $3\mfrr$11[7:0]$2077 - attribute \src "libresoc.v:50334.3-50361.6" - wire $3\xirr_accept_rd[0:0] - attribute \src "libresoc.v:50432.3-50494.6" - wire width 8 $4\cppr$10[7:0]$2080 - attribute \src "libresoc.v:50334.3-50361.6" - wire $4\xirr_accept_rd[0:0] - attribute \src "libresoc.v:50294.18-50294.116" - wire $and$libresoc.v:50294$2026_Y - attribute \src "libresoc.v:50298.18-50298.116" - wire $and$libresoc.v:50298$2030_Y - attribute \src "libresoc.v:50300.18-50300.116" - wire $and$libresoc.v:50300$2032_Y - attribute \src "libresoc.v:50303.17-50303.109" - wire $and$libresoc.v:50303$2035_Y - attribute \src "libresoc.v:50299.18-50299.110" - wire $eq$libresoc.v:50299$2031_Y - attribute \src "libresoc.v:50296.18-50296.114" - wire $lt$libresoc.v:50296$2028_Y - attribute \src "libresoc.v:50297.18-50297.109" - wire $lt$libresoc.v:50297$2029_Y - attribute \src "libresoc.v:50302.18-50302.114" - wire $lt$libresoc.v:50302$2034_Y - attribute \src "libresoc.v:50295.18-50295.109" - wire $ne$libresoc.v:50295$2027_Y - attribute \src "libresoc.v:50301.18-50301.109" - wire $ne$libresoc.v:50301$2033_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:103" - wire width 32 \be_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" - wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" - wire output 2 \core_irq_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" - wire \core_irq_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" - wire width 8 \cppr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" - wire width 8 \cppr$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" - wire width 8 \cppr$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" - wire width 8 \cppr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 5 \icp_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 11 \icp_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 6 \icp_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 7 \icp_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 8 \icp_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 12 \icp_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 9 \icp_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 10 \icp_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" - wire width 8 input 1 \ics_i_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" - wire width 4 input 13 \ics_i_src - attribute \src "libresoc.v:50185.7-50185.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" - wire input 3 \intclk_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" - wire input 4 \intclk_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" - wire \irq - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" - wire \irq$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" - wire \irq$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" - wire \irq$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" - wire width 8 \mfrr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" - wire width 8 \mfrr$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" - wire width 8 \mfrr$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" - wire width 8 \mfrr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:107" - wire width 8 \min_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" - wire width 8 \pending_priority - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" - wire \wb_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" - wire \wb_ack$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" - wire \wb_ack$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" - wire \wb_ack$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" - wire width 32 \wb_rd_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" - wire width 32 \wb_rd_data$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" - wire width 32 \wb_rd_data$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" - wire width 32 \wb_rd_data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:101" - wire \xirr_accept_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" - wire width 24 \xisr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" - wire width 24 \xisr$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" - wire width 24 \xisr$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" - wire width 24 \xisr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:50294$2026 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \icp_wb__cyc - connect \B \icp_wb__stb - connect \Y $and$libresoc.v:50294$2026_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:50298$2030 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \icp_wb__cyc - connect \B \icp_wb__stb - connect \Y $and$libresoc.v:50298$2030_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:50300$2032 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \icp_wb__cyc - connect \B \icp_wb__stb - connect \Y $and$libresoc.v:50300$2032_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" - cell $and $and$libresoc.v:50303$2035 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wb_ack - connect \B \icp_wb__cyc - connect \Y $and$libresoc.v:50303$2035_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" - cell $eq $eq$libresoc.v:50299$2031 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \icp_wb__sel - connect \B 4'1111 - connect \Y $eq$libresoc.v:50299$2031_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:50296$2028 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \mfrr - connect \B \pending_priority - connect \Y $lt$libresoc.v:50296$2028_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" - cell $lt $lt$libresoc.v:50297$2029 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \min_pri - connect \B \cppr$10 - connect \Y $lt$libresoc.v:50297$2029_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:50302$2034 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \mfrr - connect \B \pending_priority - connect \Y $lt$libresoc.v:50302$2034_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:50295$2027 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ics_i_pri - connect \B 8'11111111 - connect \Y $ne$libresoc.v:50295$2027_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:50301$2033 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ics_i_pri - connect \B 8'11111111 - connect \Y $ne$libresoc.v:50301$2033_Y - end - attribute \src "libresoc.v:50185.7-50185.20" - process $proc$libresoc.v:50185$2082 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:50212.7-50212.24" - process $proc$libresoc.v:50212$2083 - assign { } { } - assign $1\core_irq_o[0:0] 1'0 - sync always - sync init - update \core_irq_o $1\core_irq_o[0:0] - end - attribute \src "libresoc.v:50216.13-50216.25" - process $proc$libresoc.v:50216$2084 - assign { } { } - assign $1\cppr[7:0] 8'00000000 - sync always - sync init - update \cppr $1\cppr[7:0] - end - attribute \src "libresoc.v:50249.7-50249.17" - process $proc$libresoc.v:50249$2085 - assign { } { } - assign $1\irq[0:0] 1'0 - sync always - sync init - update \irq $1\irq[0:0] - end - attribute \src "libresoc.v:50257.13-50257.25" - process $proc$libresoc.v:50257$2086 - assign { } { } - assign $1\mfrr[7:0] 8'11111111 - sync always - sync init - update \mfrr $1\mfrr[7:0] - end - attribute \src "libresoc.v:50269.7-50269.20" - process $proc$libresoc.v:50269$2087 - assign { } { } - assign $1\wb_ack[0:0] 1'0 - sync always - sync init - update \wb_ack $1\wb_ack[0:0] - end - attribute \src "libresoc.v:50277.14-50277.32" - process $proc$libresoc.v:50277$2088 - assign { } { } - assign $1\wb_rd_data[31:0] 0 - sync always - sync init - update \wb_rd_data $1\wb_rd_data[31:0] - end - attribute \src "libresoc.v:50287.14-50287.31" - process $proc$libresoc.v:50287$2089 - assign { } { } - assign $1\xisr[23:0] 24'000000000000000000000000 - sync always - sync init - update \xisr $1\xisr[23:0] - end - attribute \src "libresoc.v:50304.3-50305.37" - process $proc$libresoc.v:50304$2036 - assign { } { } - assign $0\core_irq_o[0:0] \core_irq_o$next - sync posedge \intclk_clk - update \core_irq_o $0\core_irq_o[0:0] - end - attribute \src "libresoc.v:50306.3-50307.25" - process $proc$libresoc.v:50306$2037 - assign { } { } - assign $0\xisr[23:0] \xisr$next - sync posedge \intclk_clk - update \xisr $0\xisr[23:0] - end - attribute \src "libresoc.v:50308.3-50309.25" - process $proc$libresoc.v:50308$2038 - assign { } { } - assign $0\cppr[7:0] \cppr$next - sync posedge \intclk_clk - update \cppr $0\cppr[7:0] - end - attribute \src "libresoc.v:50310.3-50311.25" - process $proc$libresoc.v:50310$2039 - assign { } { } - assign $0\mfrr[7:0] \mfrr$next - sync posedge \intclk_clk - update \mfrr $0\mfrr[7:0] - end - attribute \src "libresoc.v:50312.3-50313.23" - process $proc$libresoc.v:50312$2040 - assign { } { } - assign $0\irq[0:0] \irq$next - sync posedge \intclk_clk - update \irq $0\irq[0:0] - end - attribute \src "libresoc.v:50314.3-50315.37" - process $proc$libresoc.v:50314$2041 - assign { } { } - assign $0\wb_rd_data[31:0] \wb_rd_data$next - sync posedge \intclk_clk - update \wb_rd_data $0\wb_rd_data[31:0] - end - attribute \src "libresoc.v:50316.3-50317.29" - process $proc$libresoc.v:50316$2042 - assign { } { } - assign $0\wb_ack[0:0] \wb_ack$next - sync posedge \intclk_clk - update \wb_ack $0\wb_ack[0:0] - end - attribute \src "libresoc.v:50318.3-50333.6" - process $proc$libresoc.v:50318$2043 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cppr$next[7:0]$2044 $1\cppr$next[7:0]$2050 - assign $0\irq$next[0:0]$2045 $1\irq$next[0:0]$2051 - assign $0\mfrr$next[7:0]$2046 $1\mfrr$next[7:0]$2052 - assign $0\wb_ack$next[0:0]$2047 $1\wb_ack$next[0:0]$2053 - assign $0\wb_rd_data$next[31:0]$2048 $1\wb_rd_data$next[31:0]$2054 - assign $0\xisr$next[23:0]$2049 $1\xisr$next[23:0]$2055 - attribute \src "libresoc.v:50319.5-50319.29" - switch \initial - attribute \src "libresoc.v:50319.9-50319.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\xisr$next[23:0]$2055 24'000000000000000000000000 - assign $1\cppr$next[7:0]$2050 8'00000000 - assign $1\mfrr$next[7:0]$2052 8'11111111 - assign $1\irq$next[0:0]$2051 1'0 - assign $1\wb_rd_data$next[31:0]$2054 0 - assign $1\wb_ack$next[0:0]$2053 1'0 - case - assign $1\cppr$next[7:0]$2050 \cppr$2 - assign $1\irq$next[0:0]$2051 \irq$4 - assign $1\mfrr$next[7:0]$2052 \mfrr$3 - assign $1\wb_ack$next[0:0]$2053 \wb_ack$6 - assign $1\wb_rd_data$next[31:0]$2054 \wb_rd_data$5 - assign $1\xisr$next[23:0]$2055 \xisr$1 - end - sync always - update \cppr$next $0\cppr$next[7:0]$2044 - update \irq$next $0\irq$next[0:0]$2045 - update \mfrr$next $0\mfrr$next[7:0]$2046 - update \wb_ack$next $0\wb_ack$next[0:0]$2047 - update \wb_rd_data$next $0\wb_rd_data$next[31:0]$2048 - update \xisr$next $0\xisr$next[23:0]$2049 - end - attribute \src "libresoc.v:50334.3-50361.6" - process $proc$libresoc.v:50334$2056 - assign { } { } - assign { } { } - assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:50335.5-50335.29" - switch \initial - attribute \src "libresoc.v:50335.9-50335.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - switch \$23 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\xirr_accept_rd[0:0] $2\xirr_accept_rd[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" - switch \icp_wb__we - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\xirr_accept_rd[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\xirr_accept_rd[0:0] $3\xirr_accept_rd[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" - switch \icp_wb__adr [5:0] - attribute \src "libresoc.v:0.0-0.0" - case 6'000001 - assign { } { } - assign $3\xirr_accept_rd[0:0] $4\xirr_accept_rd[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" - switch \$25 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\xirr_accept_rd[0:0] 1'1 - case - assign $4\xirr_accept_rd[0:0] 1'0 - end - case - assign $3\xirr_accept_rd[0:0] 1'0 - end - end - case - assign $1\xirr_accept_rd[0:0] 1'0 - end - sync always - update \xirr_accept_rd $0\xirr_accept_rd[0:0] - end - attribute \src "libresoc.v:50362.3-50390.6" - process $proc$libresoc.v:50362$2057 - assign { } { } - assign { } { } - assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:50363.5-50363.29" - switch \initial - attribute \src "libresoc.v:50363.9-50363.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - switch \$27 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\be_out[31:0] $2\be_out[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" - switch \icp_wb__we - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\be_out[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\be_out[31:0] $3\be_out[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" - switch \icp_wb__adr [5:0] - attribute \src "libresoc.v:0.0-0.0" - case 6'000000 - assign { } { } - assign $3\be_out[31:0] { \cppr \xisr } - attribute \src "libresoc.v:0.0-0.0" - case 6'000001 - assign { } { } - assign $3\be_out[31:0] { \cppr \xisr } - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign $3\be_out[31:0] [23:0] 24'000000000000000000000000 - assign $3\be_out[31:0] [31:24] \mfrr - case - assign $3\be_out[31:0] 0 - end - end - case - assign $1\be_out[31:0] 0 - end - sync always - update \be_out $0\be_out[31:0] - end - attribute \src "libresoc.v:50391.3-50400.6" - process $proc$libresoc.v:50391$2058 - assign { } { } - assign { } { } - assign $0\pending_priority[7:0] $1\pending_priority[7:0] - attribute \src "libresoc.v:50392.5-50392.29" - switch \initial - attribute \src "libresoc.v:50392.9-50392.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - switch \$29 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\pending_priority[7:0] \ics_i_pri - case - assign $1\pending_priority[7:0] 8'11111111 - end - sync always - update \pending_priority $0\pending_priority[7:0] - end - attribute \src "libresoc.v:50401.3-50412.6" - process $proc$libresoc.v:50401$2059 - assign { } { } - assign $0\min_pri[7:0] $1\min_pri[7:0] - attribute \src "libresoc.v:50402.5-50402.29" - switch \initial - attribute \src "libresoc.v:50402.9-50402.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - switch \$31 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\min_pri[7:0] \mfrr - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\min_pri[7:0] \pending_priority - end - sync always - update \min_pri $0\min_pri[7:0] - end - attribute \src "libresoc.v:50413.3-50421.6" - process $proc$libresoc.v:50413$2060 - assign { } { } - assign { } { } - assign $0\core_irq_o$next[0:0]$2061 $1\core_irq_o$next[0:0]$2062 - attribute \src "libresoc.v:50414.5-50414.29" - switch \initial - attribute \src "libresoc.v:50414.9-50414.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\core_irq_o$next[0:0]$2062 1'0 - case - assign $1\core_irq_o$next[0:0]$2062 \irq - end - sync always - update \core_irq_o$next $0\core_irq_o$next[0:0]$2061 - end - attribute \src "libresoc.v:50422.3-50431.6" - process $proc$libresoc.v:50422$2063 - assign { } { } - assign { } { } - assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:50423.5-50423.29" - switch \initial - attribute \src "libresoc.v:50423.9-50423.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:97" - switch \icp_wb__ack - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\icp_wb__dat_r[31:0] \wb_rd_data - case - assign $1\icp_wb__dat_r[31:0] 0 - end - sync always - update \icp_wb__dat_r $0\icp_wb__dat_r[31:0] - end - attribute \src "libresoc.v:50432.3-50494.6" - process $proc$libresoc.v:50432$2064 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\mfrr$11[7:0]$2067 $1\mfrr$11[7:0]$2072 - assign $0\wb_ack$14[0:0]$2068 $1\wb_ack$14[0:0]$2073 - assign { } { } - assign { } { } - assign { } { } - assign $0\xisr$9[23:0]$2070 $2\xisr$9[23:0]$2079 - assign $0\cppr$10[7:0]$2065 $4\cppr$10[7:0]$2080 - assign $0\wb_rd_data$13[31:0]$2069 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } - assign $0\irq$12[0:0]$2066 $1\irq$12[0:0]$2081 - attribute \src "libresoc.v:50433.5-50433.29" - switch \initial - attribute \src "libresoc.v:50433.9-50433.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - switch \$15 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign $1\wb_ack$14[0:0]$2073 1'1 - assign $1\cppr$10[7:0]$2071 $2\cppr$10[7:0]$2074 - assign $1\mfrr$11[7:0]$2072 $2\mfrr$11[7:0]$2075 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" - switch \icp_wb__we - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $2\cppr$10[7:0]$2074 $3\cppr$10[7:0]$2076 - assign $2\mfrr$11[7:0]$2075 $3\mfrr$11[7:0]$2077 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" - switch \icp_wb__adr [5:0] - attribute \src "libresoc.v:0.0-0.0" - case 6'000000 - assign { } { } - assign $3\mfrr$11[7:0]$2077 \mfrr - assign $3\cppr$10[7:0]$2076 \be_in [31:24] - attribute \src "libresoc.v:0.0-0.0" - case 6'000001 - assign { } { } - assign $3\mfrr$11[7:0]$2077 \mfrr - assign $3\cppr$10[7:0]$2076 \be_in [31:24] - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign $3\cppr$10[7:0]$2076 \cppr - assign { } { } - assign $3\mfrr$11[7:0]$2077 \be_in [31:24] - case - assign $3\cppr$10[7:0]$2076 \cppr - assign $3\mfrr$11[7:0]$2077 \mfrr - end - case - assign $2\cppr$10[7:0]$2074 \cppr - assign $2\mfrr$11[7:0]$2075 \mfrr - end - case - assign $1\cppr$10[7:0]$2071 \cppr - assign $1\mfrr$11[7:0]$2072 \mfrr - assign $1\wb_ack$14[0:0]$2073 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - switch \$17 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\xisr$9[23:0]$2078 { 20'00000000000000000001 \ics_i_src } - case - assign $1\xisr$9[23:0]$2078 24'000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - switch \$19 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xisr$9[23:0]$2079 24'000000000000000000000010 - case - assign $2\xisr$9[23:0]$2079 $1\xisr$9[23:0]$2078 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" - switch \xirr_accept_rd - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cppr$10[7:0]$2080 \min_pri - case - assign $4\cppr$10[7:0]$2080 $1\cppr$10[7:0]$2071 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" - switch { \irq \$21 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\irq$12[0:0]$2081 1'1 - case - assign $1\irq$12[0:0]$2081 1'0 - end - sync always - update \cppr$10 $0\cppr$10[7:0]$2065 - update \irq$12 $0\irq$12[0:0]$2066 - update \mfrr$11 $0\mfrr$11[7:0]$2067 - update \wb_ack$14 $0\wb_ack$14[0:0]$2068 - update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$2069 - update \xisr$9 $0\xisr$9[23:0]$2070 - end - connect \$15 $and$libresoc.v:50294$2026_Y - connect \$17 $ne$libresoc.v:50295$2027_Y - connect \$19 $lt$libresoc.v:50296$2028_Y - connect \$21 $lt$libresoc.v:50297$2029_Y - connect \$23 $and$libresoc.v:50298$2030_Y - connect \$25 $eq$libresoc.v:50299$2031_Y - connect \$27 $and$libresoc.v:50300$2032_Y - connect \$29 $ne$libresoc.v:50301$2033_Y - connect \$31 $lt$libresoc.v:50302$2034_Y - connect \$7 $and$libresoc.v:50303$2035_Y - connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 } - connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] } - connect \icp_wb__ack \$7 -end -attribute \src "libresoc.v:50502.1-51551.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.xics_ics" -attribute \generator "nMigen" -module \xics_ics - attribute \src "libresoc.v:51432.3-51481.6" - wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:51143.3-51152.6" - wire width 4 $0\cur_idx0[3:0] - attribute \src "libresoc.v:51352.3-51361.6" - wire width 4 $0\cur_idx10[3:0] - attribute \src "libresoc.v:51372.3-51381.6" - wire width 4 $0\cur_idx11[3:0] - attribute \src "libresoc.v:51392.3-51401.6" - wire width 4 $0\cur_idx12[3:0] - attribute \src "libresoc.v:51412.3-51421.6" - wire width 4 $0\cur_idx13[3:0] - attribute \src "libresoc.v:51482.3-51491.6" - wire width 4 $0\cur_idx14[3:0] - attribute \src "libresoc.v:51502.3-51511.6" - wire width 4 $0\cur_idx15[3:0] - attribute \src "libresoc.v:51163.3-51172.6" - wire width 4 $0\cur_idx1[3:0] - attribute \src "libresoc.v:51183.3-51192.6" - wire width 4 $0\cur_idx2[3:0] - attribute \src "libresoc.v:51203.3-51212.6" - wire width 4 $0\cur_idx3[3:0] - attribute \src "libresoc.v:51232.3-51241.6" - wire width 4 $0\cur_idx4[3:0] - attribute \src "libresoc.v:51252.3-51261.6" - wire width 4 $0\cur_idx5[3:0] - attribute \src "libresoc.v:51272.3-51281.6" - wire width 4 $0\cur_idx6[3:0] - attribute \src "libresoc.v:51292.3-51301.6" - wire width 4 $0\cur_idx7[3:0] - attribute \src "libresoc.v:51312.3-51321.6" - wire width 4 $0\cur_idx8[3:0] - attribute \src "libresoc.v:51332.3-51341.6" - wire width 4 $0\cur_idx9[3:0] - attribute \src "libresoc.v:51133.3-51142.6" - wire width 8 $0\cur_pri0[7:0] - attribute \src "libresoc.v:51342.3-51351.6" - wire width 8 $0\cur_pri10[7:0] - attribute \src "libresoc.v:51362.3-51371.6" - wire width 8 $0\cur_pri11[7:0] - attribute \src "libresoc.v:51382.3-51391.6" - wire width 8 $0\cur_pri12[7:0] - attribute \src "libresoc.v:51402.3-51411.6" - wire width 8 $0\cur_pri13[7:0] - attribute \src "libresoc.v:51422.3-51431.6" - wire width 8 $0\cur_pri14[7:0] - attribute \src "libresoc.v:51492.3-51501.6" - wire width 8 $0\cur_pri15[7:0] - attribute \src "libresoc.v:51153.3-51162.6" - wire width 8 $0\cur_pri1[7:0] - attribute \src "libresoc.v:51173.3-51182.6" - wire width 8 $0\cur_pri2[7:0] - attribute \src "libresoc.v:51193.3-51202.6" - wire width 8 $0\cur_pri3[7:0] - attribute \src "libresoc.v:51213.3-51222.6" - wire width 8 $0\cur_pri4[7:0] - attribute \src "libresoc.v:51242.3-51251.6" - wire width 8 $0\cur_pri5[7:0] - attribute \src "libresoc.v:51262.3-51271.6" - wire width 8 $0\cur_pri6[7:0] - attribute \src "libresoc.v:51282.3-51291.6" - wire width 8 $0\cur_pri7[7:0] - attribute \src "libresoc.v:51302.3-51311.6" - wire width 8 $0\cur_pri8[7:0] - attribute \src "libresoc.v:51322.3-51331.6" - wire width 8 $0\cur_pri9[7:0] - attribute \src "libresoc.v:51512.3-51521.6" - wire $0\ibit[0:0] - attribute \src "libresoc.v:51017.3-51018.25" - wire width 8 $0\icp_o_pri[7:0] - attribute \src "libresoc.v:51015.3-51016.28" - wire width 4 $0\icp_o_src[3:0] - attribute \src "libresoc.v:51531.3-51539.6" - wire $0\ics_wb__ack$next[0:0]$2336 - attribute \src "libresoc.v:51009.3-51010.39" - wire $0\ics_wb__ack[0:0] - attribute \src "libresoc.v:51522.3-51530.6" - wire width 32 $0\ics_wb__dat_r$next[31:0]$2333 - attribute \src "libresoc.v:51011.3-51012.43" - wire width 32 $0\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:50503.7-50503.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:51223.3-51231.6" - wire width 16 $0\int_level_l$next[15:0]$2305 - attribute \src "libresoc.v:51013.3-51014.39" - wire width 16 $0\int_level_l[15:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $0\xive0_pri$next[7:0]$2215 - attribute \src "libresoc.v:51019.3-51020.35" - wire width 8 $0\xive0_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $0\xive10_pri$next[7:0]$2216 - attribute \src "libresoc.v:51039.3-51040.37" - wire width 8 $0\xive10_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $0\xive11_pri$next[7:0]$2217 - attribute \src "libresoc.v:51041.3-51042.37" - wire width 8 $0\xive11_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $0\xive12_pri$next[7:0]$2218 - attribute \src "libresoc.v:51043.3-51044.37" - wire width 8 $0\xive12_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $0\xive13_pri$next[7:0]$2219 - attribute \src "libresoc.v:51045.3-51046.37" - wire width 8 $0\xive13_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $0\xive14_pri$next[7:0]$2220 - attribute \src "libresoc.v:51005.3-51006.37" - wire width 8 $0\xive14_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $0\xive15_pri$next[7:0]$2221 - attribute \src "libresoc.v:51007.3-51008.37" - wire width 8 $0\xive15_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $0\xive1_pri$next[7:0]$2222 - attribute \src "libresoc.v:51021.3-51022.35" - wire width 8 $0\xive1_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $0\xive2_pri$next[7:0]$2223 - attribute \src "libresoc.v:51023.3-51024.35" - wire width 8 $0\xive2_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $0\xive3_pri$next[7:0]$2224 - attribute \src "libresoc.v:51025.3-51026.35" - wire width 8 $0\xive3_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $0\xive4_pri$next[7:0]$2225 - attribute \src "libresoc.v:51027.3-51028.35" - wire width 8 $0\xive4_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $0\xive5_pri$next[7:0]$2226 - attribute \src "libresoc.v:51029.3-51030.35" - wire width 8 $0\xive5_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $0\xive6_pri$next[7:0]$2227 - attribute \src "libresoc.v:51031.3-51032.35" - wire width 8 $0\xive6_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $0\xive7_pri$next[7:0]$2228 - attribute \src "libresoc.v:51033.3-51034.35" - wire width 8 $0\xive7_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $0\xive8_pri$next[7:0]$2229 - attribute \src "libresoc.v:51035.3-51036.35" - wire width 8 $0\xive8_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $0\xive9_pri$next[7:0]$2230 - attribute \src "libresoc.v:51037.3-51038.35" - wire width 8 $0\xive9_pri[7:0] - attribute \src "libresoc.v:51432.3-51481.6" - wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:51143.3-51152.6" - wire width 4 $1\cur_idx0[3:0] - attribute \src "libresoc.v:51352.3-51361.6" - wire width 4 $1\cur_idx10[3:0] - attribute \src "libresoc.v:51372.3-51381.6" - wire width 4 $1\cur_idx11[3:0] - attribute \src "libresoc.v:51392.3-51401.6" - wire width 4 $1\cur_idx12[3:0] - attribute \src "libresoc.v:51412.3-51421.6" - wire width 4 $1\cur_idx13[3:0] - attribute \src "libresoc.v:51482.3-51491.6" - wire width 4 $1\cur_idx14[3:0] - attribute \src "libresoc.v:51502.3-51511.6" - wire width 4 $1\cur_idx15[3:0] - attribute \src "libresoc.v:51163.3-51172.6" - wire width 4 $1\cur_idx1[3:0] - attribute \src "libresoc.v:51183.3-51192.6" - wire width 4 $1\cur_idx2[3:0] - attribute \src "libresoc.v:51203.3-51212.6" - wire width 4 $1\cur_idx3[3:0] - attribute \src "libresoc.v:51232.3-51241.6" - wire width 4 $1\cur_idx4[3:0] - attribute \src "libresoc.v:51252.3-51261.6" - wire width 4 $1\cur_idx5[3:0] - attribute \src "libresoc.v:51272.3-51281.6" - wire width 4 $1\cur_idx6[3:0] - attribute \src "libresoc.v:51292.3-51301.6" - wire width 4 $1\cur_idx7[3:0] - attribute \src "libresoc.v:51312.3-51321.6" - wire width 4 $1\cur_idx8[3:0] - attribute \src "libresoc.v:51332.3-51341.6" - wire width 4 $1\cur_idx9[3:0] - attribute \src "libresoc.v:51133.3-51142.6" - wire width 8 $1\cur_pri0[7:0] - attribute \src "libresoc.v:51342.3-51351.6" - wire width 8 $1\cur_pri10[7:0] - attribute \src "libresoc.v:51362.3-51371.6" - wire width 8 $1\cur_pri11[7:0] - attribute \src "libresoc.v:51382.3-51391.6" - wire width 8 $1\cur_pri12[7:0] - attribute \src "libresoc.v:51402.3-51411.6" - wire width 8 $1\cur_pri13[7:0] - attribute \src "libresoc.v:51422.3-51431.6" - wire width 8 $1\cur_pri14[7:0] - attribute \src "libresoc.v:51492.3-51501.6" - wire width 8 $1\cur_pri15[7:0] - attribute \src "libresoc.v:51153.3-51162.6" - wire width 8 $1\cur_pri1[7:0] - attribute \src "libresoc.v:51173.3-51182.6" - wire width 8 $1\cur_pri2[7:0] - attribute \src "libresoc.v:51193.3-51202.6" - wire width 8 $1\cur_pri3[7:0] - attribute \src "libresoc.v:51213.3-51222.6" - wire width 8 $1\cur_pri4[7:0] - attribute \src "libresoc.v:51242.3-51251.6" - wire width 8 $1\cur_pri5[7:0] - attribute \src "libresoc.v:51262.3-51271.6" - wire width 8 $1\cur_pri6[7:0] - attribute \src "libresoc.v:51282.3-51291.6" - wire width 8 $1\cur_pri7[7:0] - attribute \src "libresoc.v:51302.3-51311.6" - wire width 8 $1\cur_pri8[7:0] - attribute \src "libresoc.v:51322.3-51331.6" - wire width 8 $1\cur_pri9[7:0] - attribute \src "libresoc.v:51512.3-51521.6" - wire $1\ibit[0:0] - attribute \src "libresoc.v:50782.13-50782.30" - wire width 8 $1\icp_o_pri[7:0] - attribute \src "libresoc.v:50787.13-50787.29" - wire width 4 $1\icp_o_src[3:0] - attribute \src "libresoc.v:51531.3-51539.6" - wire $1\ics_wb__ack$next[0:0]$2337 - attribute \src "libresoc.v:50796.7-50796.25" - wire $1\ics_wb__ack[0:0] - attribute \src "libresoc.v:51522.3-51530.6" - wire width 32 $1\ics_wb__dat_r$next[31:0]$2334 - attribute \src "libresoc.v:50805.14-50805.35" - wire width 32 $1\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:51223.3-51231.6" - wire width 16 $1\int_level_l$next[15:0]$2306 - attribute \src "libresoc.v:50817.14-50817.36" - wire width 16 $1\int_level_l[15:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $1\xive0_pri$next[7:0]$2231 - attribute \src "libresoc.v:50839.13-50839.30" - wire width 8 $1\xive0_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $1\xive10_pri$next[7:0]$2232 - attribute \src "libresoc.v:50843.13-50843.31" - wire width 8 $1\xive10_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $1\xive11_pri$next[7:0]$2233 - attribute \src "libresoc.v:50847.13-50847.31" - wire width 8 $1\xive11_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $1\xive12_pri$next[7:0]$2234 - attribute \src "libresoc.v:50851.13-50851.31" - wire width 8 $1\xive12_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $1\xive13_pri$next[7:0]$2235 - attribute \src "libresoc.v:50855.13-50855.31" - wire width 8 $1\xive13_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $1\xive14_pri$next[7:0]$2236 - attribute \src "libresoc.v:50859.13-50859.31" - wire width 8 $1\xive14_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $1\xive15_pri$next[7:0]$2237 - attribute \src "libresoc.v:50863.13-50863.31" - wire width 8 $1\xive15_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $1\xive1_pri$next[7:0]$2238 - attribute \src "libresoc.v:50867.13-50867.30" - wire width 8 $1\xive1_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $1\xive2_pri$next[7:0]$2239 - attribute \src "libresoc.v:50871.13-50871.30" - wire width 8 $1\xive2_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $1\xive3_pri$next[7:0]$2240 - attribute \src "libresoc.v:50875.13-50875.30" - wire width 8 $1\xive3_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $1\xive4_pri$next[7:0]$2241 - attribute \src "libresoc.v:50879.13-50879.30" - wire width 8 $1\xive4_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $1\xive5_pri$next[7:0]$2242 - attribute \src "libresoc.v:50883.13-50883.30" - wire width 8 $1\xive5_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $1\xive6_pri$next[7:0]$2243 - attribute \src "libresoc.v:50887.13-50887.30" - wire width 8 $1\xive6_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $1\xive7_pri$next[7:0]$2244 - attribute \src "libresoc.v:50891.13-50891.30" - wire width 8 $1\xive7_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $1\xive8_pri$next[7:0]$2245 - attribute \src "libresoc.v:50895.13-50895.30" - wire width 8 $1\xive8_pri[7:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $1\xive9_pri$next[7:0]$2246 - attribute \src "libresoc.v:50899.13-50899.30" - wire width 8 $1\xive9_pri[7:0] - attribute \src "libresoc.v:51432.3-51481.6" - wire width 32 $2\be_out[31:0] - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $2\xive0_pri$next[7:0]$2247 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $2\xive10_pri$next[7:0]$2248 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $2\xive11_pri$next[7:0]$2249 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $2\xive12_pri$next[7:0]$2250 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $2\xive13_pri$next[7:0]$2251 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $2\xive14_pri$next[7:0]$2252 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $2\xive15_pri$next[7:0]$2253 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $2\xive1_pri$next[7:0]$2254 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $2\xive2_pri$next[7:0]$2255 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $2\xive3_pri$next[7:0]$2256 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $2\xive4_pri$next[7:0]$2257 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $2\xive5_pri$next[7:0]$2258 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $2\xive6_pri$next[7:0]$2259 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $2\xive7_pri$next[7:0]$2260 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $2\xive8_pri$next[7:0]$2261 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $2\xive9_pri$next[7:0]$2262 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $3\xive0_pri$next[7:0]$2263 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $3\xive10_pri$next[7:0]$2264 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $3\xive11_pri$next[7:0]$2265 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $3\xive12_pri$next[7:0]$2266 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $3\xive13_pri$next[7:0]$2267 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $3\xive14_pri$next[7:0]$2268 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $3\xive15_pri$next[7:0]$2269 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $3\xive1_pri$next[7:0]$2270 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $3\xive2_pri$next[7:0]$2271 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $3\xive3_pri$next[7:0]$2272 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $3\xive4_pri$next[7:0]$2273 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $3\xive5_pri$next[7:0]$2274 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $3\xive6_pri$next[7:0]$2275 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $3\xive7_pri$next[7:0]$2276 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $3\xive8_pri$next[7:0]$2277 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $3\xive9_pri$next[7:0]$2278 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $4\xive0_pri$next[7:0]$2279 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $4\xive10_pri$next[7:0]$2280 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $4\xive11_pri$next[7:0]$2281 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $4\xive12_pri$next[7:0]$2282 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $4\xive13_pri$next[7:0]$2283 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $4\xive14_pri$next[7:0]$2284 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $4\xive15_pri$next[7:0]$2285 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $4\xive1_pri$next[7:0]$2286 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $4\xive2_pri$next[7:0]$2287 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $4\xive3_pri$next[7:0]$2288 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $4\xive4_pri$next[7:0]$2289 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $4\xive5_pri$next[7:0]$2290 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $4\xive6_pri$next[7:0]$2291 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $4\xive7_pri$next[7:0]$2292 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $4\xive8_pri$next[7:0]$2293 - attribute \src "libresoc.v:51047.3-51132.6" - wire width 8 $4\xive9_pri$next[7:0]$2294 - attribute \src "libresoc.v:50904.19-50904.113" - wire $and$libresoc.v:50904$2092_Y - attribute \src "libresoc.v:50906.19-50906.114" - wire $and$libresoc.v:50906$2094_Y - attribute \src "libresoc.v:50908.19-50908.114" - wire $and$libresoc.v:50908$2096_Y - attribute \src "libresoc.v:50910.19-50910.114" - wire $and$libresoc.v:50910$2098_Y - attribute \src "libresoc.v:50912.19-50912.114" - wire $and$libresoc.v:50912$2100_Y - attribute \src "libresoc.v:50914.19-50914.114" - wire $and$libresoc.v:50914$2102_Y - attribute \src "libresoc.v:50916.19-50916.114" - wire $and$libresoc.v:50916$2104_Y - attribute \src "libresoc.v:50919.19-50919.114" - wire $and$libresoc.v:50919$2107_Y - attribute \src "libresoc.v:50921.19-50921.114" - wire $and$libresoc.v:50921$2109_Y - attribute \src "libresoc.v:50923.19-50923.114" - wire $and$libresoc.v:50923$2111_Y - attribute \src "libresoc.v:50926.19-50926.114" - wire $and$libresoc.v:50926$2114_Y - attribute \src "libresoc.v:50928.19-50928.114" - wire $and$libresoc.v:50928$2116_Y - attribute \src "libresoc.v:50930.19-50930.114" - wire $and$libresoc.v:50930$2118_Y - attribute \src "libresoc.v:50932.19-50932.114" - wire $and$libresoc.v:50932$2120_Y - attribute \src "libresoc.v:50934.19-50934.115" - wire $and$libresoc.v:50934$2122_Y - attribute \src "libresoc.v:50936.19-50936.115" - wire $and$libresoc.v:50936$2124_Y - attribute \src "libresoc.v:50938.19-50938.115" - wire $and$libresoc.v:50938$2126_Y - attribute \src "libresoc.v:50941.19-50941.115" - wire $and$libresoc.v:50941$2129_Y - attribute \src "libresoc.v:50943.19-50943.115" - wire $and$libresoc.v:50943$2131_Y - attribute \src "libresoc.v:50945.19-50945.115" - wire $and$libresoc.v:50945$2133_Y - attribute \src "libresoc.v:50948.19-50948.115" - wire $and$libresoc.v:50948$2136_Y - attribute \src "libresoc.v:50950.19-50950.115" - wire $and$libresoc.v:50950$2138_Y - attribute \src "libresoc.v:50952.19-50952.115" - wire $and$libresoc.v:50952$2140_Y - attribute \src "libresoc.v:50954.19-50954.115" - wire $and$libresoc.v:50954$2142_Y - attribute \src "libresoc.v:50956.19-50956.115" - wire $and$libresoc.v:50956$2144_Y - attribute \src "libresoc.v:50959.19-50959.115" - wire $and$libresoc.v:50959$2147_Y - attribute \src "libresoc.v:50983.17-50983.115" - wire $and$libresoc.v:50983$2171_Y - attribute \src "libresoc.v:50991.18-50991.112" - wire $and$libresoc.v:50991$2179_Y - attribute \src "libresoc.v:50993.18-50993.112" - wire $and$libresoc.v:50993$2181_Y - attribute \src "libresoc.v:50995.18-50995.112" - wire $and$libresoc.v:50995$2183_Y - attribute \src "libresoc.v:50997.18-50997.112" - wire $and$libresoc.v:50997$2185_Y - attribute \src "libresoc.v:51000.18-51000.112" - wire $and$libresoc.v:51000$2188_Y - attribute \src "libresoc.v:51002.18-51002.112" - wire $and$libresoc.v:51002$2190_Y - attribute \src "libresoc.v:51004.18-51004.112" - wire $and$libresoc.v:51004$2192_Y - attribute \src "libresoc.v:50918.18-50918.109" - wire $eq$libresoc.v:50918$2106_Y - attribute \src "libresoc.v:50940.18-50940.109" - wire $eq$libresoc.v:50940$2128_Y - attribute \src "libresoc.v:50957.17-50957.114" - wire $eq$libresoc.v:50957$2145_Y - attribute \src "libresoc.v:50960.19-50960.110" - wire $eq$libresoc.v:50960$2148_Y - attribute \src "libresoc.v:50962.18-50962.109" - wire $eq$libresoc.v:50962$2150_Y - attribute \src "libresoc.v:50964.18-50964.109" - wire $eq$libresoc.v:50964$2152_Y - attribute \src "libresoc.v:50966.18-50966.109" - wire $eq$libresoc.v:50966$2154_Y - attribute \src "libresoc.v:50968.18-50968.109" - wire $eq$libresoc.v:50968$2156_Y - attribute \src "libresoc.v:50970.18-50970.109" - wire $eq$libresoc.v:50970$2158_Y - attribute \src "libresoc.v:50972.17-50972.114" - wire $eq$libresoc.v:50972$2160_Y - attribute \src "libresoc.v:50973.18-50973.109" - wire $eq$libresoc.v:50973$2161_Y - attribute \src "libresoc.v:50975.18-50975.109" - wire $eq$libresoc.v:50975$2163_Y - attribute \src "libresoc.v:50977.18-50977.110" - wire $eq$libresoc.v:50977$2165_Y - attribute \src "libresoc.v:50979.18-50979.110" - wire $eq$libresoc.v:50979$2167_Y - attribute \src "libresoc.v:50981.18-50981.110" - wire $eq$libresoc.v:50981$2169_Y - attribute \src "libresoc.v:50984.18-50984.110" - wire $eq$libresoc.v:50984$2172_Y - attribute \src "libresoc.v:50986.18-50986.110" - wire $eq$libresoc.v:50986$2174_Y - attribute \src "libresoc.v:50988.18-50988.110" - wire $eq$libresoc.v:50988$2176_Y - attribute \src "libresoc.v:50999.17-50999.108" - wire $eq$libresoc.v:50999$2187_Y - attribute \src "libresoc.v:50903.18-50903.111" - wire $lt$libresoc.v:50903$2091_Y - attribute \src "libresoc.v:50905.19-50905.112" - wire $lt$libresoc.v:50905$2093_Y - attribute \src "libresoc.v:50907.19-50907.112" - wire $lt$libresoc.v:50907$2095_Y - attribute \src "libresoc.v:50909.19-50909.112" - wire $lt$libresoc.v:50909$2097_Y - attribute \src "libresoc.v:50911.19-50911.112" - wire $lt$libresoc.v:50911$2099_Y - attribute \src "libresoc.v:50913.19-50913.112" - wire $lt$libresoc.v:50913$2101_Y - attribute \src "libresoc.v:50915.19-50915.112" - wire $lt$libresoc.v:50915$2103_Y - attribute \src "libresoc.v:50917.19-50917.112" - wire $lt$libresoc.v:50917$2105_Y - attribute \src "libresoc.v:50920.19-50920.112" - wire $lt$libresoc.v:50920$2108_Y - attribute \src "libresoc.v:50922.19-50922.112" - wire $lt$libresoc.v:50922$2110_Y - attribute \src "libresoc.v:50925.19-50925.112" - wire $lt$libresoc.v:50925$2113_Y - attribute \src "libresoc.v:50927.19-50927.112" - wire $lt$libresoc.v:50927$2115_Y - attribute \src "libresoc.v:50929.19-50929.112" - wire $lt$libresoc.v:50929$2117_Y - attribute \src "libresoc.v:50931.19-50931.112" - wire $lt$libresoc.v:50931$2119_Y - attribute \src "libresoc.v:50933.19-50933.113" - wire $lt$libresoc.v:50933$2121_Y - attribute \src "libresoc.v:50935.19-50935.113" - wire $lt$libresoc.v:50935$2123_Y - attribute \src "libresoc.v:50937.19-50937.114" - wire $lt$libresoc.v:50937$2125_Y - attribute \src "libresoc.v:50939.19-50939.114" - wire $lt$libresoc.v:50939$2127_Y - attribute \src "libresoc.v:50942.19-50942.114" - wire $lt$libresoc.v:50942$2130_Y - attribute \src "libresoc.v:50944.19-50944.114" - wire $lt$libresoc.v:50944$2132_Y - attribute \src "libresoc.v:50947.19-50947.114" - wire $lt$libresoc.v:50947$2135_Y - attribute \src "libresoc.v:50949.19-50949.114" - wire $lt$libresoc.v:50949$2137_Y - attribute \src "libresoc.v:50951.19-50951.114" - wire $lt$libresoc.v:50951$2139_Y - attribute \src "libresoc.v:50953.19-50953.114" - wire $lt$libresoc.v:50953$2141_Y - attribute \src "libresoc.v:50955.19-50955.114" - wire $lt$libresoc.v:50955$2143_Y - attribute \src "libresoc.v:50958.19-50958.114" - wire $lt$libresoc.v:50958$2146_Y - attribute \src "libresoc.v:50992.18-50992.110" - wire $lt$libresoc.v:50992$2180_Y - attribute \src "libresoc.v:50994.18-50994.110" - wire $lt$libresoc.v:50994$2182_Y - attribute \src "libresoc.v:50996.18-50996.111" - wire $lt$libresoc.v:50996$2184_Y - attribute \src "libresoc.v:50998.18-50998.111" - wire $lt$libresoc.v:50998$2186_Y - attribute \src "libresoc.v:51001.18-51001.111" - wire $lt$libresoc.v:51001$2189_Y - attribute \src "libresoc.v:51003.18-51003.111" - wire $lt$libresoc.v:51003$2191_Y - attribute \src "libresoc.v:50990.18-50990.40" - wire width 16 $shr$libresoc.v:50990$2178_Y - attribute \src "libresoc.v:50902.17-50902.114" - wire width 8 $ternary$libresoc.v:50902$2090_Y - attribute \src "libresoc.v:50924.18-50924.116" - wire width 8 $ternary$libresoc.v:50924$2112_Y - attribute \src "libresoc.v:50946.18-50946.116" - wire width 8 $ternary$libresoc.v:50946$2134_Y - attribute \src "libresoc.v:50961.19-50961.118" - wire width 8 $ternary$libresoc.v:50961$2149_Y - attribute \src "libresoc.v:50963.18-50963.116" - wire width 8 $ternary$libresoc.v:50963$2151_Y - attribute \src "libresoc.v:50965.18-50965.116" - wire width 8 $ternary$libresoc.v:50965$2153_Y - attribute \src "libresoc.v:50967.18-50967.116" - wire width 8 $ternary$libresoc.v:50967$2155_Y - attribute \src "libresoc.v:50969.18-50969.116" - wire width 8 $ternary$libresoc.v:50969$2157_Y - attribute \src "libresoc.v:50971.18-50971.116" - wire width 8 $ternary$libresoc.v:50971$2159_Y - attribute \src "libresoc.v:50974.18-50974.116" - wire width 8 $ternary$libresoc.v:50974$2162_Y - attribute \src "libresoc.v:50976.18-50976.116" - wire width 8 $ternary$libresoc.v:50976$2164_Y - attribute \src "libresoc.v:50978.18-50978.117" - wire width 8 $ternary$libresoc.v:50978$2166_Y - attribute \src "libresoc.v:50980.18-50980.117" - wire width 8 $ternary$libresoc.v:50980$2168_Y - attribute \src "libresoc.v:50982.18-50982.117" - wire width 8 $ternary$libresoc.v:50982$2170_Y - attribute \src "libresoc.v:50985.18-50985.117" - wire width 8 $ternary$libresoc.v:50985$2173_Y - attribute \src "libresoc.v:50987.18-50987.117" - wire width 8 $ternary$libresoc.v:50987$2175_Y - attribute \src "libresoc.v:50989.18-50989.117" - wire width 8 $ternary$libresoc.v:50989$2177_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire width 8 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire width 8 \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$159 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$161 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$163 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$165 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$167 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$169 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$179 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$187 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$189 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire width 8 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$191 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$193 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$195 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$197 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$199 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$201 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire width 8 \$203 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire \$204 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire width 8 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire width 8 \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire width 8 \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire width 8 \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire width 8 \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire width 8 \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire width 8 \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire width 8 \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire \$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire width 8 \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire width 8 \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire \$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire width 8 \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire \$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire width 8 \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire \$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire width 8 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:315" - wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" - wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - wire \$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:337" - wire width 32 \be_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" - wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" - wire width 4 \cur_idx0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" - wire width 4 \cur_idx1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" - wire width 4 \cur_idx10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" - wire width 4 \cur_idx11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" - wire width 4 \cur_idx12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" - wire width 4 \cur_idx13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" - wire width 4 \cur_idx14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" - wire width 4 \cur_idx15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" - wire width 4 \cur_idx2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" - wire width 4 \cur_idx3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" - wire width 4 \cur_idx4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" - wire width 4 \cur_idx5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" - wire width 4 \cur_idx6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" - wire width 4 \cur_idx7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" - wire width 4 \cur_idx8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" - wire width 4 \cur_idx9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" - wire width 8 \cur_pri0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" - wire width 8 \cur_pri1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" - wire width 8 \cur_pri10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" - wire width 8 \cur_pri11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" - wire width 8 \cur_pri12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" - wire width 8 \cur_pri13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" - wire width 8 \cur_pri14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" - wire width 8 \cur_pri15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" - wire width 8 \cur_pri2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" - wire width 8 \cur_pri3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" - wire width 8 \cur_pri4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" - wire width 8 \cur_pri5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" - wire width 8 \cur_pri6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" - wire width 8 \cur_pri7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" - wire width 8 \cur_pri8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" - wire width 8 \cur_pri9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:314" - wire \ibit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" - wire width 8 output 1 \icp_o_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" - wire width 8 \icp_o_pri$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" - wire width 4 output 12 \icp_o_src - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" - wire width 4 \icp_o_src$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" - wire width 8 \icp_r_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" - wire width 4 \icp_r_src - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 9 \ics_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire \ics_wb__ack$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 4 \ics_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 6 \ics_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 8 \ics_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 \ics_wb__dat_r$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 10 \ics_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 7 \ics_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 11 \ics_wb__we - attribute \src "libresoc.v:50503.7-50503.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 5 \int_level_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:263" - wire width 16 \int_level_l - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:263" - wire width 16 \int_level_l$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" - wire input 2 \intclk_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" - wire input 3 \intclk_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:358" - wire width 4 \max_idx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:359" - wire width 8 \max_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:261" - wire width 4 \reg_idx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:287" - wire \reg_is_config - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:288" - wire \reg_is_debug - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" - wire \reg_is_xive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" - wire \wb_valid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive0_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive0_pri$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive10_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive10_pri$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive11_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive11_pri$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive12_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive12_pri$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive13_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive13_pri$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive14_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive14_pri$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive15_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive15_pri$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive1_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive1_pri$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive2_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive2_pri$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive3_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive3_pri$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive4_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive4_pri$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive5_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive5_pri$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive6_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive6_pri$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive7_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive7_pri$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive8_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive8_pri$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive9_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" - wire width 8 \xive9_pri$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50904$2092 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [3] - connect \B \$99 - connect \Y $and$libresoc.v:50904$2092_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50906$2094 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [3] - connect \B \$103 - connect \Y $and$libresoc.v:50906$2094_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50908$2096 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [4] - connect \B \$107 - connect \Y $and$libresoc.v:50908$2096_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50910$2098 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [4] - connect \B \$111 - connect \Y $and$libresoc.v:50910$2098_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50912$2100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [5] - connect \B \$115 - connect \Y $and$libresoc.v:50912$2100_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50914$2102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [5] - connect \B \$119 - connect \Y $and$libresoc.v:50914$2102_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50916$2104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [6] - connect \B \$123 - connect \Y $and$libresoc.v:50916$2104_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50919$2107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [6] - connect \B \$127 - connect \Y $and$libresoc.v:50919$2107_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50921$2109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [7] - connect \B \$131 - connect \Y $and$libresoc.v:50921$2109_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50923$2111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [7] - connect \B \$135 - connect \Y $and$libresoc.v:50923$2111_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50926$2114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [8] - connect \B \$139 - connect \Y $and$libresoc.v:50926$2114_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50928$2116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [8] - connect \B \$143 - connect \Y $and$libresoc.v:50928$2116_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50930$2118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [9] - connect \B \$147 - connect \Y $and$libresoc.v:50930$2118_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50932$2120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [9] - connect \B \$151 - connect \Y $and$libresoc.v:50932$2120_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50934$2122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [10] - connect \B \$155 - connect \Y $and$libresoc.v:50934$2122_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50936$2124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [10] - connect \B \$159 - connect \Y $and$libresoc.v:50936$2124_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50938$2126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [11] - connect \B \$163 - connect \Y $and$libresoc.v:50938$2126_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50941$2129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [11] - connect \B \$167 - connect \Y $and$libresoc.v:50941$2129_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50943$2131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [12] - connect \B \$171 - connect \Y $and$libresoc.v:50943$2131_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50945$2133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [12] - connect \B \$175 - connect \Y $and$libresoc.v:50945$2133_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50948$2136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [13] - connect \B \$179 - connect \Y $and$libresoc.v:50948$2136_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50950$2138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [13] - connect \B \$183 - connect \Y $and$libresoc.v:50950$2138_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50952$2140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [14] - connect \B \$187 - connect \Y $and$libresoc.v:50952$2140_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50954$2142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [14] - connect \B \$191 - connect \Y $and$libresoc.v:50954$2142_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50956$2144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [15] - connect \B \$195 - connect \Y $and$libresoc.v:50956$2144_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50959$2147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [15] - connect \B \$199 - connect \Y $and$libresoc.v:50959$2147_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" - cell $and $and$libresoc.v:50983$2171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ics_wb__cyc - connect \B \ics_wb__stb - connect \Y $and$libresoc.v:50983$2171_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" - cell $and $and$libresoc.v:50991$2179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wb_valid - connect \B \ics_wb__we - connect \Y $and$libresoc.v:50991$2179_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50993$2181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [0] - connect \B \$75 - connect \Y $and$libresoc.v:50993$2181_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50995$2183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [0] - connect \B \$79 - connect \Y $and$libresoc.v:50995$2183_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:50997$2185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [1] - connect \B \$83 - connect \Y $and$libresoc.v:50997$2185_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:51000$2188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [1] - connect \B \$87 - connect \Y $and$libresoc.v:51000$2188_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:51002$2190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [2] - connect \B \$91 - connect \Y $and$libresoc.v:51002$2190_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:51004$2192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \int_level_l [2] - connect \B \$95 - connect \Y $and$libresoc.v:51004$2192_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:50918$2106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive1_pri - connect \B 8'11111111 - connect \Y $eq$libresoc.v:50918$2106_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:50940$2128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive2_pri - connect \B 8'11111111 - connect \Y $eq$libresoc.v:50940$2128_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" - cell $eq $eq$libresoc.v:50957$2145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ics_wb__adr [9:0] - connect \B 1'0 - connect \Y $eq$libresoc.v:50957$2145_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:50960$2148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \cur_pri15 - connect \B 8'11111111 - connect \Y $eq$libresoc.v:50960$2148_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:50962$2150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive3_pri - connect \B 8'11111111 - connect \Y $eq$libresoc.v:50962$2150_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:50964$2152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive4_pri - connect \B 8'11111111 - connect \Y $eq$libresoc.v:50964$2152_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:50966$2154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive5_pri - connect \B 8'11111111 - connect \Y $eq$libresoc.v:50966$2154_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:50968$2156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive6_pri - connect \B 8'11111111 - connect \Y $eq$libresoc.v:50968$2156_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:50970$2158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive7_pri - connect \B 8'11111111 - connect \Y $eq$libresoc.v:50970$2158_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" - cell $eq $eq$libresoc.v:50972$2160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \ics_wb__adr [9:0] - connect \B 3'100 - connect \Y $eq$libresoc.v:50972$2160_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:50973$2161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive8_pri - connect \B 8'11111111 - connect \Y $eq$libresoc.v:50973$2161_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:50975$2163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive9_pri - connect \B 8'11111111 - connect \Y $eq$libresoc.v:50975$2163_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:50977$2165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive10_pri - connect \B 8'11111111 - connect \Y $eq$libresoc.v:50977$2165_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:50979$2167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive11_pri - connect \B 8'11111111 - connect \Y $eq$libresoc.v:50979$2167_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:50981$2169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive12_pri - connect \B 8'11111111 - connect \Y $eq$libresoc.v:50981$2169_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:50984$2172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive13_pri - connect \B 8'11111111 - connect \Y $eq$libresoc.v:50984$2172_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:50986$2174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive14_pri - connect \B 8'11111111 - connect \Y $eq$libresoc.v:50986$2174_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:50988$2176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive15_pri - connect \B 8'11111111 - connect \Y $eq$libresoc.v:50988$2176_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:50999$2187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive0_pri - connect \B 8'11111111 - connect \Y $eq$libresoc.v:50999$2187_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50903$2091 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive3_pri - connect \B \cur_pri2 - connect \Y $lt$libresoc.v:50903$2091_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50905$2093 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive3_pri - connect \B \cur_pri2 - connect \Y $lt$libresoc.v:50905$2093_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50907$2095 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive4_pri - connect \B \cur_pri3 - connect \Y $lt$libresoc.v:50907$2095_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50909$2097 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive4_pri - connect \B \cur_pri3 - connect \Y $lt$libresoc.v:50909$2097_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50911$2099 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive5_pri - connect \B \cur_pri4 - connect \Y $lt$libresoc.v:50911$2099_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50913$2101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive5_pri - connect \B \cur_pri4 - connect \Y $lt$libresoc.v:50913$2101_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50915$2103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive6_pri - connect \B \cur_pri5 - connect \Y $lt$libresoc.v:50915$2103_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50917$2105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive6_pri - connect \B \cur_pri5 - connect \Y $lt$libresoc.v:50917$2105_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50920$2108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive7_pri - connect \B \cur_pri6 - connect \Y $lt$libresoc.v:50920$2108_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50922$2110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive7_pri - connect \B \cur_pri6 - connect \Y $lt$libresoc.v:50922$2110_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50925$2113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive8_pri - connect \B \cur_pri7 - connect \Y $lt$libresoc.v:50925$2113_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50927$2115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive8_pri - connect \B \cur_pri7 - connect \Y $lt$libresoc.v:50927$2115_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50929$2117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive9_pri - connect \B \cur_pri8 - connect \Y $lt$libresoc.v:50929$2117_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50931$2119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive9_pri - connect \B \cur_pri8 - connect \Y $lt$libresoc.v:50931$2119_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50933$2121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive10_pri - connect \B \cur_pri9 - connect \Y $lt$libresoc.v:50933$2121_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50935$2123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive10_pri - connect \B \cur_pri9 - connect \Y $lt$libresoc.v:50935$2123_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50937$2125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive11_pri - connect \B \cur_pri10 - connect \Y $lt$libresoc.v:50937$2125_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50939$2127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive11_pri - connect \B \cur_pri10 - connect \Y $lt$libresoc.v:50939$2127_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50942$2130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive12_pri - connect \B \cur_pri11 - connect \Y $lt$libresoc.v:50942$2130_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50944$2132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive12_pri - connect \B \cur_pri11 - connect \Y $lt$libresoc.v:50944$2132_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50947$2135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive13_pri - connect \B \cur_pri12 - connect \Y $lt$libresoc.v:50947$2135_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50949$2137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive13_pri - connect \B \cur_pri12 - connect \Y $lt$libresoc.v:50949$2137_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50951$2139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive14_pri - connect \B \cur_pri13 - connect \Y $lt$libresoc.v:50951$2139_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50953$2141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive14_pri - connect \B \cur_pri13 - connect \Y $lt$libresoc.v:50953$2141_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50955$2143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive15_pri - connect \B \cur_pri14 - connect \Y $lt$libresoc.v:50955$2143_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50958$2146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive15_pri - connect \B \cur_pri14 - connect \Y $lt$libresoc.v:50958$2146_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50992$2180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive0_pri - connect \B \max_pri - connect \Y $lt$libresoc.v:50992$2180_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50994$2182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive0_pri - connect \B \max_pri - connect \Y $lt$libresoc.v:50994$2182_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50996$2184 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive1_pri - connect \B \cur_pri0 - connect \Y $lt$libresoc.v:50996$2184_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:50998$2186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive1_pri - connect \B \cur_pri0 - connect \Y $lt$libresoc.v:50998$2186_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:51001$2189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive2_pri - connect \B \cur_pri1 - connect \Y $lt$libresoc.v:51001$2189_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:51003$2191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \xive2_pri - connect \B \cur_pri1 - connect \Y $lt$libresoc.v:51003$2191_Y - end - attribute \src "libresoc.v:50990.18-50990.40" - cell $shr $shr$libresoc.v:50990$2178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A \int_level_l - connect \B \reg_idx - connect \Y $shr$libresoc.v:50990$2178_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:50902$2090 - parameter \WIDTH 8 - connect \A \xive0_pri - connect \B 8'11111111 - connect \S \$8 - connect \Y $ternary$libresoc.v:50902$2090_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:50924$2112 - parameter \WIDTH 8 - connect \A \xive1_pri - connect \B 8'11111111 - connect \S \$12 - connect \Y $ternary$libresoc.v:50924$2112_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:50946$2134 - parameter \WIDTH 8 - connect \A \xive2_pri - connect \B 8'11111111 - connect \S \$16 - connect \Y $ternary$libresoc.v:50946$2134_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:50961$2149 - parameter \WIDTH 8 - connect \A \cur_pri15 - connect \B 8'11111111 - connect \S \$204 - connect \Y $ternary$libresoc.v:50961$2149_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:50963$2151 - parameter \WIDTH 8 - connect \A \xive3_pri - connect \B 8'11111111 - connect \S \$20 - connect \Y $ternary$libresoc.v:50963$2151_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:50965$2153 - parameter \WIDTH 8 - connect \A \xive4_pri - connect \B 8'11111111 - connect \S \$24 - connect \Y $ternary$libresoc.v:50965$2153_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:50967$2155 - parameter \WIDTH 8 - connect \A \xive5_pri - connect \B 8'11111111 - connect \S \$28 - connect \Y $ternary$libresoc.v:50967$2155_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:50969$2157 - parameter \WIDTH 8 - connect \A \xive6_pri - connect \B 8'11111111 - connect \S \$32 - connect \Y $ternary$libresoc.v:50969$2157_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:50971$2159 - parameter \WIDTH 8 - connect \A \xive7_pri - connect \B 8'11111111 - connect \S \$36 - connect \Y $ternary$libresoc.v:50971$2159_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:50974$2162 - parameter \WIDTH 8 - connect \A \xive8_pri - connect \B 8'11111111 - connect \S \$40 - connect \Y $ternary$libresoc.v:50974$2162_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:50976$2164 - parameter \WIDTH 8 - connect \A \xive9_pri - connect \B 8'11111111 - connect \S \$44 - connect \Y $ternary$libresoc.v:50976$2164_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:50978$2166 - parameter \WIDTH 8 - connect \A \xive10_pri - connect \B 8'11111111 - connect \S \$48 - connect \Y $ternary$libresoc.v:50978$2166_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:50980$2168 - parameter \WIDTH 8 - connect \A \xive11_pri - connect \B 8'11111111 - connect \S \$52 - connect \Y $ternary$libresoc.v:50980$2168_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:50982$2170 - parameter \WIDTH 8 - connect \A \xive12_pri - connect \B 8'11111111 - connect \S \$56 - connect \Y $ternary$libresoc.v:50982$2170_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:50985$2173 - parameter \WIDTH 8 - connect \A \xive13_pri - connect \B 8'11111111 - connect \S \$60 - connect \Y $ternary$libresoc.v:50985$2173_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:50987$2175 - parameter \WIDTH 8 - connect \A \xive14_pri - connect \B 8'11111111 - connect \S \$64 - connect \Y $ternary$libresoc.v:50987$2175_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:50989$2177 - parameter \WIDTH 8 - connect \A \xive15_pri - connect \B 8'11111111 - connect \S \$68 - connect \Y $ternary$libresoc.v:50989$2177_Y - end - attribute \src "libresoc.v:50503.7-50503.20" - process $proc$libresoc.v:50503$2338 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:50782.13-50782.30" - process $proc$libresoc.v:50782$2339 - assign { } { } - assign $1\icp_o_pri[7:0] 8'00000000 - sync always - sync init - update \icp_o_pri $1\icp_o_pri[7:0] - end - attribute \src "libresoc.v:50787.13-50787.29" - process $proc$libresoc.v:50787$2340 - assign { } { } - assign $1\icp_o_src[3:0] 4'0000 - sync always - sync init - update \icp_o_src $1\icp_o_src[3:0] - end - attribute \src "libresoc.v:50796.7-50796.25" - process $proc$libresoc.v:50796$2341 - assign { } { } - assign $1\ics_wb__ack[0:0] 1'0 - sync always - sync init - update \ics_wb__ack $1\ics_wb__ack[0:0] - end - attribute \src "libresoc.v:50805.14-50805.35" - process $proc$libresoc.v:50805$2342 - assign { } { } - assign $1\ics_wb__dat_r[31:0] 0 - sync always - sync init - update \ics_wb__dat_r $1\ics_wb__dat_r[31:0] - end - attribute \src "libresoc.v:50817.14-50817.36" - process $proc$libresoc.v:50817$2343 - assign { } { } - assign $1\int_level_l[15:0] 16'0000000000000000 - sync always - sync init - update \int_level_l $1\int_level_l[15:0] - end - attribute \src "libresoc.v:50839.13-50839.30" - process $proc$libresoc.v:50839$2344 - assign { } { } - assign $1\xive0_pri[7:0] 8'11111111 - sync always - sync init - update \xive0_pri $1\xive0_pri[7:0] - end - attribute \src "libresoc.v:50843.13-50843.31" - process $proc$libresoc.v:50843$2345 - assign { } { } - assign $1\xive10_pri[7:0] 8'11111111 - sync always - sync init - update \xive10_pri $1\xive10_pri[7:0] - end - attribute \src "libresoc.v:50847.13-50847.31" - process $proc$libresoc.v:50847$2346 - assign { } { } - assign $1\xive11_pri[7:0] 8'11111111 - sync always - sync init - update \xive11_pri $1\xive11_pri[7:0] - end - attribute \src "libresoc.v:50851.13-50851.31" - process $proc$libresoc.v:50851$2347 - assign { } { } - assign $1\xive12_pri[7:0] 8'11111111 - sync always - sync init - update \xive12_pri $1\xive12_pri[7:0] - end - attribute \src "libresoc.v:50855.13-50855.31" - process $proc$libresoc.v:50855$2348 - assign { } { } - assign $1\xive13_pri[7:0] 8'11111111 - sync always - sync init - update \xive13_pri $1\xive13_pri[7:0] - end - attribute \src "libresoc.v:50859.13-50859.31" - process $proc$libresoc.v:50859$2349 - assign { } { } - assign $1\xive14_pri[7:0] 8'11111111 - sync always - sync init - update \xive14_pri $1\xive14_pri[7:0] - end - attribute \src "libresoc.v:50863.13-50863.31" - process $proc$libresoc.v:50863$2350 - assign { } { } - assign $1\xive15_pri[7:0] 8'11111111 - sync always - sync init - update \xive15_pri $1\xive15_pri[7:0] - end - attribute \src "libresoc.v:50867.13-50867.30" - process $proc$libresoc.v:50867$2351 - assign { } { } - assign $1\xive1_pri[7:0] 8'11111111 - sync always - sync init - update \xive1_pri $1\xive1_pri[7:0] - end - attribute \src "libresoc.v:50871.13-50871.30" - process $proc$libresoc.v:50871$2352 - assign { } { } - assign $1\xive2_pri[7:0] 8'11111111 - sync always - sync init - update \xive2_pri $1\xive2_pri[7:0] - end - attribute \src "libresoc.v:50875.13-50875.30" - process $proc$libresoc.v:50875$2353 - assign { } { } - assign $1\xive3_pri[7:0] 8'11111111 - sync always - sync init - update \xive3_pri $1\xive3_pri[7:0] - end - attribute \src "libresoc.v:50879.13-50879.30" - process $proc$libresoc.v:50879$2354 - assign { } { } - assign $1\xive4_pri[7:0] 8'11111111 - sync always - sync init - update \xive4_pri $1\xive4_pri[7:0] - end - attribute \src "libresoc.v:50883.13-50883.30" - process $proc$libresoc.v:50883$2355 - assign { } { } - assign $1\xive5_pri[7:0] 8'11111111 - sync always - sync init - update \xive5_pri $1\xive5_pri[7:0] - end - attribute \src "libresoc.v:50887.13-50887.30" - process $proc$libresoc.v:50887$2356 - assign { } { } - assign $1\xive6_pri[7:0] 8'11111111 - sync always - sync init - update \xive6_pri $1\xive6_pri[7:0] - end - attribute \src "libresoc.v:50891.13-50891.30" - process $proc$libresoc.v:50891$2357 - assign { } { } - assign $1\xive7_pri[7:0] 8'11111111 - sync always - sync init - update \xive7_pri $1\xive7_pri[7:0] - end - attribute \src "libresoc.v:50895.13-50895.30" - process $proc$libresoc.v:50895$2358 - assign { } { } - assign $1\xive8_pri[7:0] 8'11111111 - sync always - sync init - update \xive8_pri $1\xive8_pri[7:0] - end - attribute \src "libresoc.v:50899.13-50899.30" - process $proc$libresoc.v:50899$2359 - assign { } { } - assign $1\xive9_pri[7:0] 8'11111111 - sync always - sync init - update \xive9_pri $1\xive9_pri[7:0] - end - attribute \src "libresoc.v:51005.3-51006.37" - process $proc$libresoc.v:51005$2193 - assign { } { } - assign $0\xive14_pri[7:0] \xive14_pri$next - sync posedge \intclk_clk - update \xive14_pri $0\xive14_pri[7:0] - end - attribute \src "libresoc.v:51007.3-51008.37" - process $proc$libresoc.v:51007$2194 - assign { } { } - assign $0\xive15_pri[7:0] \xive15_pri$next - sync posedge \intclk_clk - update \xive15_pri $0\xive15_pri[7:0] - end - attribute \src "libresoc.v:51009.3-51010.39" - process $proc$libresoc.v:51009$2195 - assign { } { } - assign $0\ics_wb__ack[0:0] \ics_wb__ack$next - sync posedge \intclk_clk - update \ics_wb__ack $0\ics_wb__ack[0:0] - end - attribute \src "libresoc.v:51011.3-51012.43" - process $proc$libresoc.v:51011$2196 - assign { } { } - assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next - sync posedge \intclk_clk - update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] - end - attribute \src "libresoc.v:51013.3-51014.39" - process $proc$libresoc.v:51013$2197 - assign { } { } - assign $0\int_level_l[15:0] \int_level_l$next - sync posedge \intclk_clk - update \int_level_l $0\int_level_l[15:0] - end - attribute \src "libresoc.v:51015.3-51016.28" - process $proc$libresoc.v:51015$2198 - assign { } { } - assign $0\icp_o_src[3:0] \cur_idx15 - sync posedge \intclk_clk - update \icp_o_src $0\icp_o_src[3:0] - end - attribute \src "libresoc.v:51017.3-51018.25" - process $proc$libresoc.v:51017$2199 - assign { } { } - assign $0\icp_o_pri[7:0] \$203 - sync posedge \intclk_clk - update \icp_o_pri $0\icp_o_pri[7:0] - end - attribute \src "libresoc.v:51019.3-51020.35" - process $proc$libresoc.v:51019$2200 - assign { } { } - assign $0\xive0_pri[7:0] \xive0_pri$next - sync posedge \intclk_clk - update \xive0_pri $0\xive0_pri[7:0] - end - attribute \src "libresoc.v:51021.3-51022.35" - process $proc$libresoc.v:51021$2201 - assign { } { } - assign $0\xive1_pri[7:0] \xive1_pri$next - sync posedge \intclk_clk - update \xive1_pri $0\xive1_pri[7:0] - end - attribute \src "libresoc.v:51023.3-51024.35" - process $proc$libresoc.v:51023$2202 - assign { } { } - assign $0\xive2_pri[7:0] \xive2_pri$next - sync posedge \intclk_clk - update \xive2_pri $0\xive2_pri[7:0] - end - attribute \src "libresoc.v:51025.3-51026.35" - process $proc$libresoc.v:51025$2203 - assign { } { } - assign $0\xive3_pri[7:0] \xive3_pri$next - sync posedge \intclk_clk - update \xive3_pri $0\xive3_pri[7:0] - end - attribute \src "libresoc.v:51027.3-51028.35" - process $proc$libresoc.v:51027$2204 - assign { } { } - assign $0\xive4_pri[7:0] \xive4_pri$next - sync posedge \intclk_clk - update \xive4_pri $0\xive4_pri[7:0] - end - attribute \src "libresoc.v:51029.3-51030.35" - process $proc$libresoc.v:51029$2205 - assign { } { } - assign $0\xive5_pri[7:0] \xive5_pri$next - sync posedge \intclk_clk - update \xive5_pri $0\xive5_pri[7:0] - end - attribute \src "libresoc.v:51031.3-51032.35" - process $proc$libresoc.v:51031$2206 - assign { } { } - assign $0\xive6_pri[7:0] \xive6_pri$next - sync posedge \intclk_clk - update \xive6_pri $0\xive6_pri[7:0] - end - attribute \src "libresoc.v:51033.3-51034.35" - process $proc$libresoc.v:51033$2207 - assign { } { } - assign $0\xive7_pri[7:0] \xive7_pri$next - sync posedge \intclk_clk - update \xive7_pri $0\xive7_pri[7:0] - end - attribute \src "libresoc.v:51035.3-51036.35" - process $proc$libresoc.v:51035$2208 - assign { } { } - assign $0\xive8_pri[7:0] \xive8_pri$next - sync posedge \intclk_clk - update \xive8_pri $0\xive8_pri[7:0] - end - attribute \src "libresoc.v:51037.3-51038.35" - process $proc$libresoc.v:51037$2209 - assign { } { } - assign $0\xive9_pri[7:0] \xive9_pri$next - sync posedge \intclk_clk - update \xive9_pri $0\xive9_pri[7:0] - end - attribute \src "libresoc.v:51039.3-51040.37" - process $proc$libresoc.v:51039$2210 - assign { } { } - assign $0\xive10_pri[7:0] \xive10_pri$next - sync posedge \intclk_clk - update \xive10_pri $0\xive10_pri[7:0] - end - attribute \src "libresoc.v:51041.3-51042.37" - process $proc$libresoc.v:51041$2211 - assign { } { } - assign $0\xive11_pri[7:0] \xive11_pri$next - sync posedge \intclk_clk - update \xive11_pri $0\xive11_pri[7:0] - end - attribute \src "libresoc.v:51043.3-51044.37" - process $proc$libresoc.v:51043$2212 - assign { } { } - assign $0\xive12_pri[7:0] \xive12_pri$next - sync posedge \intclk_clk - update \xive12_pri $0\xive12_pri[7:0] - end - attribute \src "libresoc.v:51045.3-51046.37" - process $proc$libresoc.v:51045$2213 - assign { } { } - assign $0\xive13_pri[7:0] \xive13_pri$next - sync posedge \intclk_clk - update \xive13_pri $0\xive13_pri[7:0] - end - attribute \src "libresoc.v:51047.3-51132.6" - process $proc$libresoc.v:51047$2214 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xive0_pri$next[7:0]$2215 $4\xive0_pri$next[7:0]$2279 - assign $0\xive10_pri$next[7:0]$2216 $4\xive10_pri$next[7:0]$2280 - assign $0\xive11_pri$next[7:0]$2217 $4\xive11_pri$next[7:0]$2281 - assign $0\xive12_pri$next[7:0]$2218 $4\xive12_pri$next[7:0]$2282 - assign $0\xive13_pri$next[7:0]$2219 $4\xive13_pri$next[7:0]$2283 - assign $0\xive14_pri$next[7:0]$2220 $4\xive14_pri$next[7:0]$2284 - assign $0\xive15_pri$next[7:0]$2221 $4\xive15_pri$next[7:0]$2285 - assign $0\xive1_pri$next[7:0]$2222 $4\xive1_pri$next[7:0]$2286 - assign $0\xive2_pri$next[7:0]$2223 $4\xive2_pri$next[7:0]$2287 - assign $0\xive3_pri$next[7:0]$2224 $4\xive3_pri$next[7:0]$2288 - assign $0\xive4_pri$next[7:0]$2225 $4\xive4_pri$next[7:0]$2289 - assign $0\xive5_pri$next[7:0]$2226 $4\xive5_pri$next[7:0]$2290 - assign $0\xive6_pri$next[7:0]$2227 $4\xive6_pri$next[7:0]$2291 - assign $0\xive7_pri$next[7:0]$2228 $4\xive7_pri$next[7:0]$2292 - assign $0\xive8_pri$next[7:0]$2229 $4\xive8_pri$next[7:0]$2293 - assign $0\xive9_pri$next[7:0]$2230 $4\xive9_pri$next[7:0]$2294 - attribute \src "libresoc.v:51048.5-51048.29" - switch \initial - attribute \src "libresoc.v:51048.9-51048.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" - switch \$73 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\xive0_pri$next[7:0]$2231 $2\xive0_pri$next[7:0]$2247 - assign $1\xive10_pri$next[7:0]$2232 $2\xive10_pri$next[7:0]$2248 - assign $1\xive11_pri$next[7:0]$2233 $2\xive11_pri$next[7:0]$2249 - assign $1\xive12_pri$next[7:0]$2234 $2\xive12_pri$next[7:0]$2250 - assign $1\xive13_pri$next[7:0]$2235 $2\xive13_pri$next[7:0]$2251 - assign $1\xive14_pri$next[7:0]$2236 $2\xive14_pri$next[7:0]$2252 - assign $1\xive15_pri$next[7:0]$2237 $2\xive15_pri$next[7:0]$2253 - assign $1\xive1_pri$next[7:0]$2238 $2\xive1_pri$next[7:0]$2254 - assign $1\xive2_pri$next[7:0]$2239 $2\xive2_pri$next[7:0]$2255 - assign $1\xive3_pri$next[7:0]$2240 $2\xive3_pri$next[7:0]$2256 - assign $1\xive4_pri$next[7:0]$2241 $2\xive4_pri$next[7:0]$2257 - assign $1\xive5_pri$next[7:0]$2242 $2\xive5_pri$next[7:0]$2258 - assign $1\xive6_pri$next[7:0]$2243 $2\xive6_pri$next[7:0]$2259 - assign $1\xive7_pri$next[7:0]$2244 $2\xive7_pri$next[7:0]$2260 - assign $1\xive8_pri$next[7:0]$2245 $2\xive8_pri$next[7:0]$2261 - assign $1\xive9_pri$next[7:0]$2246 $2\xive9_pri$next[7:0]$2262 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" - switch \reg_is_xive - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\xive0_pri$next[7:0]$2247 $3\xive0_pri$next[7:0]$2263 - assign $2\xive10_pri$next[7:0]$2248 $3\xive10_pri$next[7:0]$2264 - assign $2\xive11_pri$next[7:0]$2249 $3\xive11_pri$next[7:0]$2265 - assign $2\xive12_pri$next[7:0]$2250 $3\xive12_pri$next[7:0]$2266 - assign $2\xive13_pri$next[7:0]$2251 $3\xive13_pri$next[7:0]$2267 - assign $2\xive14_pri$next[7:0]$2252 $3\xive14_pri$next[7:0]$2268 - assign $2\xive15_pri$next[7:0]$2253 $3\xive15_pri$next[7:0]$2269 - assign $2\xive1_pri$next[7:0]$2254 $3\xive1_pri$next[7:0]$2270 - assign $2\xive2_pri$next[7:0]$2255 $3\xive2_pri$next[7:0]$2271 - assign $2\xive3_pri$next[7:0]$2256 $3\xive3_pri$next[7:0]$2272 - assign $2\xive4_pri$next[7:0]$2257 $3\xive4_pri$next[7:0]$2273 - assign $2\xive5_pri$next[7:0]$2258 $3\xive5_pri$next[7:0]$2274 - assign $2\xive6_pri$next[7:0]$2259 $3\xive6_pri$next[7:0]$2275 - assign $2\xive7_pri$next[7:0]$2260 $3\xive7_pri$next[7:0]$2276 - assign $2\xive8_pri$next[7:0]$2261 $3\xive8_pri$next[7:0]$2277 - assign $2\xive9_pri$next[7:0]$2262 $3\xive9_pri$next[7:0]$2278 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" - switch \reg_idx - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $3\xive10_pri$next[7:0]$2264 \xive10_pri - assign $3\xive11_pri$next[7:0]$2265 \xive11_pri - assign $3\xive12_pri$next[7:0]$2266 \xive12_pri - assign $3\xive13_pri$next[7:0]$2267 \xive13_pri - assign $3\xive14_pri$next[7:0]$2268 \xive14_pri - assign $3\xive15_pri$next[7:0]$2269 \xive15_pri - assign $3\xive1_pri$next[7:0]$2270 \xive1_pri - assign $3\xive2_pri$next[7:0]$2271 \xive2_pri - assign $3\xive3_pri$next[7:0]$2272 \xive3_pri - assign $3\xive4_pri$next[7:0]$2273 \xive4_pri - assign $3\xive5_pri$next[7:0]$2274 \xive5_pri - assign $3\xive6_pri$next[7:0]$2275 \xive6_pri - assign $3\xive7_pri$next[7:0]$2276 \xive7_pri - assign $3\xive8_pri$next[7:0]$2277 \xive8_pri - assign $3\xive9_pri$next[7:0]$2278 \xive9_pri - assign $3\xive0_pri$next[7:0]$2263 \be_in [7:0] - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign $3\xive0_pri$next[7:0]$2263 \xive0_pri - assign $3\xive10_pri$next[7:0]$2264 \xive10_pri - assign $3\xive11_pri$next[7:0]$2265 \xive11_pri - assign $3\xive12_pri$next[7:0]$2266 \xive12_pri - assign $3\xive13_pri$next[7:0]$2267 \xive13_pri - assign $3\xive14_pri$next[7:0]$2268 \xive14_pri - assign $3\xive15_pri$next[7:0]$2269 \xive15_pri - assign { } { } - assign $3\xive2_pri$next[7:0]$2271 \xive2_pri - assign $3\xive3_pri$next[7:0]$2272 \xive3_pri - assign $3\xive4_pri$next[7:0]$2273 \xive4_pri - assign $3\xive5_pri$next[7:0]$2274 \xive5_pri - assign $3\xive6_pri$next[7:0]$2275 \xive6_pri - assign $3\xive7_pri$next[7:0]$2276 \xive7_pri - assign $3\xive8_pri$next[7:0]$2277 \xive8_pri - assign $3\xive9_pri$next[7:0]$2278 \xive9_pri - assign $3\xive1_pri$next[7:0]$2270 \be_in [7:0] - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign $3\xive0_pri$next[7:0]$2263 \xive0_pri - assign $3\xive10_pri$next[7:0]$2264 \xive10_pri - assign $3\xive11_pri$next[7:0]$2265 \xive11_pri - assign $3\xive12_pri$next[7:0]$2266 \xive12_pri - assign $3\xive13_pri$next[7:0]$2267 \xive13_pri - assign $3\xive14_pri$next[7:0]$2268 \xive14_pri - assign $3\xive15_pri$next[7:0]$2269 \xive15_pri - assign $3\xive1_pri$next[7:0]$2270 \xive1_pri - assign { } { } - assign $3\xive3_pri$next[7:0]$2272 \xive3_pri - assign $3\xive4_pri$next[7:0]$2273 \xive4_pri - assign $3\xive5_pri$next[7:0]$2274 \xive5_pri - assign $3\xive6_pri$next[7:0]$2275 \xive6_pri - assign $3\xive7_pri$next[7:0]$2276 \xive7_pri - assign $3\xive8_pri$next[7:0]$2277 \xive8_pri - assign $3\xive9_pri$next[7:0]$2278 \xive9_pri - assign $3\xive2_pri$next[7:0]$2271 \be_in [7:0] - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign $3\xive0_pri$next[7:0]$2263 \xive0_pri - assign $3\xive10_pri$next[7:0]$2264 \xive10_pri - assign $3\xive11_pri$next[7:0]$2265 \xive11_pri - assign $3\xive12_pri$next[7:0]$2266 \xive12_pri - assign $3\xive13_pri$next[7:0]$2267 \xive13_pri - assign $3\xive14_pri$next[7:0]$2268 \xive14_pri - assign $3\xive15_pri$next[7:0]$2269 \xive15_pri - assign $3\xive1_pri$next[7:0]$2270 \xive1_pri - assign $3\xive2_pri$next[7:0]$2271 \xive2_pri - assign { } { } - assign $3\xive4_pri$next[7:0]$2273 \xive4_pri - assign $3\xive5_pri$next[7:0]$2274 \xive5_pri - assign $3\xive6_pri$next[7:0]$2275 \xive6_pri - assign $3\xive7_pri$next[7:0]$2276 \xive7_pri - assign $3\xive8_pri$next[7:0]$2277 \xive8_pri - assign $3\xive9_pri$next[7:0]$2278 \xive9_pri - assign $3\xive3_pri$next[7:0]$2272 \be_in [7:0] - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign $3\xive0_pri$next[7:0]$2263 \xive0_pri - assign $3\xive10_pri$next[7:0]$2264 \xive10_pri - assign $3\xive11_pri$next[7:0]$2265 \xive11_pri - assign $3\xive12_pri$next[7:0]$2266 \xive12_pri - assign $3\xive13_pri$next[7:0]$2267 \xive13_pri - assign $3\xive14_pri$next[7:0]$2268 \xive14_pri - assign $3\xive15_pri$next[7:0]$2269 \xive15_pri - assign $3\xive1_pri$next[7:0]$2270 \xive1_pri - assign $3\xive2_pri$next[7:0]$2271 \xive2_pri - assign $3\xive3_pri$next[7:0]$2272 \xive3_pri - assign { } { } - assign $3\xive5_pri$next[7:0]$2274 \xive5_pri - assign $3\xive6_pri$next[7:0]$2275 \xive6_pri - assign $3\xive7_pri$next[7:0]$2276 \xive7_pri - assign $3\xive8_pri$next[7:0]$2277 \xive8_pri - assign $3\xive9_pri$next[7:0]$2278 \xive9_pri - assign $3\xive4_pri$next[7:0]$2273 \be_in [7:0] - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign $3\xive0_pri$next[7:0]$2263 \xive0_pri - assign $3\xive10_pri$next[7:0]$2264 \xive10_pri - assign $3\xive11_pri$next[7:0]$2265 \xive11_pri - assign $3\xive12_pri$next[7:0]$2266 \xive12_pri - assign $3\xive13_pri$next[7:0]$2267 \xive13_pri - assign $3\xive14_pri$next[7:0]$2268 \xive14_pri - assign $3\xive15_pri$next[7:0]$2269 \xive15_pri - assign $3\xive1_pri$next[7:0]$2270 \xive1_pri - assign $3\xive2_pri$next[7:0]$2271 \xive2_pri - assign $3\xive3_pri$next[7:0]$2272 \xive3_pri - assign $3\xive4_pri$next[7:0]$2273 \xive4_pri - assign { } { } - assign $3\xive6_pri$next[7:0]$2275 \xive6_pri - assign $3\xive7_pri$next[7:0]$2276 \xive7_pri - assign $3\xive8_pri$next[7:0]$2277 \xive8_pri - assign $3\xive9_pri$next[7:0]$2278 \xive9_pri - assign $3\xive5_pri$next[7:0]$2274 \be_in [7:0] - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign $3\xive0_pri$next[7:0]$2263 \xive0_pri - assign $3\xive10_pri$next[7:0]$2264 \xive10_pri - assign $3\xive11_pri$next[7:0]$2265 \xive11_pri - assign $3\xive12_pri$next[7:0]$2266 \xive12_pri - assign $3\xive13_pri$next[7:0]$2267 \xive13_pri - assign $3\xive14_pri$next[7:0]$2268 \xive14_pri - assign $3\xive15_pri$next[7:0]$2269 \xive15_pri - assign $3\xive1_pri$next[7:0]$2270 \xive1_pri - assign $3\xive2_pri$next[7:0]$2271 \xive2_pri - assign $3\xive3_pri$next[7:0]$2272 \xive3_pri - assign $3\xive4_pri$next[7:0]$2273 \xive4_pri - assign $3\xive5_pri$next[7:0]$2274 \xive5_pri - assign { } { } - assign $3\xive7_pri$next[7:0]$2276 \xive7_pri - assign $3\xive8_pri$next[7:0]$2277 \xive8_pri - assign $3\xive9_pri$next[7:0]$2278 \xive9_pri - assign $3\xive6_pri$next[7:0]$2275 \be_in [7:0] - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign $3\xive0_pri$next[7:0]$2263 \xive0_pri - assign $3\xive10_pri$next[7:0]$2264 \xive10_pri - assign $3\xive11_pri$next[7:0]$2265 \xive11_pri - assign $3\xive12_pri$next[7:0]$2266 \xive12_pri - assign $3\xive13_pri$next[7:0]$2267 \xive13_pri - assign $3\xive14_pri$next[7:0]$2268 \xive14_pri - assign $3\xive15_pri$next[7:0]$2269 \xive15_pri - assign $3\xive1_pri$next[7:0]$2270 \xive1_pri - assign $3\xive2_pri$next[7:0]$2271 \xive2_pri - assign $3\xive3_pri$next[7:0]$2272 \xive3_pri - assign $3\xive4_pri$next[7:0]$2273 \xive4_pri - assign $3\xive5_pri$next[7:0]$2274 \xive5_pri - assign $3\xive6_pri$next[7:0]$2275 \xive6_pri - assign { } { } - assign $3\xive8_pri$next[7:0]$2277 \xive8_pri - assign $3\xive9_pri$next[7:0]$2278 \xive9_pri - assign $3\xive7_pri$next[7:0]$2276 \be_in [7:0] - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign $3\xive0_pri$next[7:0]$2263 \xive0_pri - assign $3\xive10_pri$next[7:0]$2264 \xive10_pri - assign $3\xive11_pri$next[7:0]$2265 \xive11_pri - assign $3\xive12_pri$next[7:0]$2266 \xive12_pri - assign $3\xive13_pri$next[7:0]$2267 \xive13_pri - assign $3\xive14_pri$next[7:0]$2268 \xive14_pri - assign $3\xive15_pri$next[7:0]$2269 \xive15_pri - assign $3\xive1_pri$next[7:0]$2270 \xive1_pri - assign $3\xive2_pri$next[7:0]$2271 \xive2_pri - assign $3\xive3_pri$next[7:0]$2272 \xive3_pri - assign $3\xive4_pri$next[7:0]$2273 \xive4_pri - assign $3\xive5_pri$next[7:0]$2274 \xive5_pri - assign $3\xive6_pri$next[7:0]$2275 \xive6_pri - assign $3\xive7_pri$next[7:0]$2276 \xive7_pri - assign { } { } - assign $3\xive9_pri$next[7:0]$2278 \xive9_pri - assign $3\xive8_pri$next[7:0]$2277 \be_in [7:0] - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign $3\xive0_pri$next[7:0]$2263 \xive0_pri - assign $3\xive10_pri$next[7:0]$2264 \xive10_pri - assign $3\xive11_pri$next[7:0]$2265 \xive11_pri - assign $3\xive12_pri$next[7:0]$2266 \xive12_pri - assign $3\xive13_pri$next[7:0]$2267 \xive13_pri - assign $3\xive14_pri$next[7:0]$2268 \xive14_pri - assign $3\xive15_pri$next[7:0]$2269 \xive15_pri - assign $3\xive1_pri$next[7:0]$2270 \xive1_pri - assign $3\xive2_pri$next[7:0]$2271 \xive2_pri - assign $3\xive3_pri$next[7:0]$2272 \xive3_pri - assign $3\xive4_pri$next[7:0]$2273 \xive4_pri - assign $3\xive5_pri$next[7:0]$2274 \xive5_pri - assign $3\xive6_pri$next[7:0]$2275 \xive6_pri - assign $3\xive7_pri$next[7:0]$2276 \xive7_pri - assign $3\xive8_pri$next[7:0]$2277 \xive8_pri - assign { } { } - assign $3\xive9_pri$next[7:0]$2278 \be_in [7:0] - attribute \src "libresoc.v:0.0-0.0" - case 4'1010 - assign $3\xive0_pri$next[7:0]$2263 \xive0_pri - assign { } { } - assign $3\xive11_pri$next[7:0]$2265 \xive11_pri - assign $3\xive12_pri$next[7:0]$2266 \xive12_pri - assign $3\xive13_pri$next[7:0]$2267 \xive13_pri - assign $3\xive14_pri$next[7:0]$2268 \xive14_pri - assign $3\xive15_pri$next[7:0]$2269 \xive15_pri - assign $3\xive1_pri$next[7:0]$2270 \xive1_pri - assign $3\xive2_pri$next[7:0]$2271 \xive2_pri - assign $3\xive3_pri$next[7:0]$2272 \xive3_pri - assign $3\xive4_pri$next[7:0]$2273 \xive4_pri - assign $3\xive5_pri$next[7:0]$2274 \xive5_pri - assign $3\xive6_pri$next[7:0]$2275 \xive6_pri - assign $3\xive7_pri$next[7:0]$2276 \xive7_pri - assign $3\xive8_pri$next[7:0]$2277 \xive8_pri - assign $3\xive9_pri$next[7:0]$2278 \xive9_pri - assign $3\xive10_pri$next[7:0]$2264 \be_in [7:0] - attribute \src "libresoc.v:0.0-0.0" - case 4'1011 - assign $3\xive0_pri$next[7:0]$2263 \xive0_pri - assign $3\xive10_pri$next[7:0]$2264 \xive10_pri - assign { } { } - assign $3\xive12_pri$next[7:0]$2266 \xive12_pri - assign $3\xive13_pri$next[7:0]$2267 \xive13_pri - assign $3\xive14_pri$next[7:0]$2268 \xive14_pri - assign $3\xive15_pri$next[7:0]$2269 \xive15_pri - assign $3\xive1_pri$next[7:0]$2270 \xive1_pri - assign $3\xive2_pri$next[7:0]$2271 \xive2_pri - assign $3\xive3_pri$next[7:0]$2272 \xive3_pri - assign $3\xive4_pri$next[7:0]$2273 \xive4_pri - assign $3\xive5_pri$next[7:0]$2274 \xive5_pri - assign $3\xive6_pri$next[7:0]$2275 \xive6_pri - assign $3\xive7_pri$next[7:0]$2276 \xive7_pri - assign $3\xive8_pri$next[7:0]$2277 \xive8_pri - assign $3\xive9_pri$next[7:0]$2278 \xive9_pri - assign $3\xive11_pri$next[7:0]$2265 \be_in [7:0] - attribute \src "libresoc.v:0.0-0.0" - case 4'1100 - assign $3\xive0_pri$next[7:0]$2263 \xive0_pri - assign $3\xive10_pri$next[7:0]$2264 \xive10_pri - assign $3\xive11_pri$next[7:0]$2265 \xive11_pri - assign { } { } - assign $3\xive13_pri$next[7:0]$2267 \xive13_pri - assign $3\xive14_pri$next[7:0]$2268 \xive14_pri - assign $3\xive15_pri$next[7:0]$2269 \xive15_pri - assign $3\xive1_pri$next[7:0]$2270 \xive1_pri - assign $3\xive2_pri$next[7:0]$2271 \xive2_pri - assign $3\xive3_pri$next[7:0]$2272 \xive3_pri - assign $3\xive4_pri$next[7:0]$2273 \xive4_pri - assign $3\xive5_pri$next[7:0]$2274 \xive5_pri - assign $3\xive6_pri$next[7:0]$2275 \xive6_pri - assign $3\xive7_pri$next[7:0]$2276 \xive7_pri - assign $3\xive8_pri$next[7:0]$2277 \xive8_pri - assign $3\xive9_pri$next[7:0]$2278 \xive9_pri - assign $3\xive12_pri$next[7:0]$2266 \be_in [7:0] - attribute \src "libresoc.v:0.0-0.0" - case 4'1101 - assign $3\xive0_pri$next[7:0]$2263 \xive0_pri - assign $3\xive10_pri$next[7:0]$2264 \xive10_pri - assign $3\xive11_pri$next[7:0]$2265 \xive11_pri - assign $3\xive12_pri$next[7:0]$2266 \xive12_pri - assign { } { } - assign $3\xive14_pri$next[7:0]$2268 \xive14_pri - assign $3\xive15_pri$next[7:0]$2269 \xive15_pri - assign $3\xive1_pri$next[7:0]$2270 \xive1_pri - assign $3\xive2_pri$next[7:0]$2271 \xive2_pri - assign $3\xive3_pri$next[7:0]$2272 \xive3_pri - assign $3\xive4_pri$next[7:0]$2273 \xive4_pri - assign $3\xive5_pri$next[7:0]$2274 \xive5_pri - assign $3\xive6_pri$next[7:0]$2275 \xive6_pri - assign $3\xive7_pri$next[7:0]$2276 \xive7_pri - assign $3\xive8_pri$next[7:0]$2277 \xive8_pri - assign $3\xive9_pri$next[7:0]$2278 \xive9_pri - assign $3\xive13_pri$next[7:0]$2267 \be_in [7:0] - attribute \src "libresoc.v:0.0-0.0" - case 4'1110 - assign $3\xive0_pri$next[7:0]$2263 \xive0_pri - assign $3\xive10_pri$next[7:0]$2264 \xive10_pri - assign $3\xive11_pri$next[7:0]$2265 \xive11_pri - assign $3\xive12_pri$next[7:0]$2266 \xive12_pri - assign $3\xive13_pri$next[7:0]$2267 \xive13_pri - assign { } { } - assign $3\xive15_pri$next[7:0]$2269 \xive15_pri - assign $3\xive1_pri$next[7:0]$2270 \xive1_pri - assign $3\xive2_pri$next[7:0]$2271 \xive2_pri - assign $3\xive3_pri$next[7:0]$2272 \xive3_pri - assign $3\xive4_pri$next[7:0]$2273 \xive4_pri - assign $3\xive5_pri$next[7:0]$2274 \xive5_pri - assign $3\xive6_pri$next[7:0]$2275 \xive6_pri - assign $3\xive7_pri$next[7:0]$2276 \xive7_pri - assign $3\xive8_pri$next[7:0]$2277 \xive8_pri - assign $3\xive9_pri$next[7:0]$2278 \xive9_pri - assign $3\xive14_pri$next[7:0]$2268 \be_in [7:0] - attribute \src "libresoc.v:0.0-0.0" - case 4'---- - assign $3\xive0_pri$next[7:0]$2263 \xive0_pri - assign $3\xive10_pri$next[7:0]$2264 \xive10_pri - assign $3\xive11_pri$next[7:0]$2265 \xive11_pri - assign $3\xive12_pri$next[7:0]$2266 \xive12_pri - assign $3\xive13_pri$next[7:0]$2267 \xive13_pri - assign $3\xive14_pri$next[7:0]$2268 \xive14_pri - assign { } { } - assign $3\xive1_pri$next[7:0]$2270 \xive1_pri - assign $3\xive2_pri$next[7:0]$2271 \xive2_pri - assign $3\xive3_pri$next[7:0]$2272 \xive3_pri - assign $3\xive4_pri$next[7:0]$2273 \xive4_pri - assign $3\xive5_pri$next[7:0]$2274 \xive5_pri - assign $3\xive6_pri$next[7:0]$2275 \xive6_pri - assign $3\xive7_pri$next[7:0]$2276 \xive7_pri - assign $3\xive8_pri$next[7:0]$2277 \xive8_pri - assign $3\xive9_pri$next[7:0]$2278 \xive9_pri - assign $3\xive15_pri$next[7:0]$2269 \be_in [7:0] - case - assign $3\xive0_pri$next[7:0]$2263 \xive0_pri - assign $3\xive10_pri$next[7:0]$2264 \xive10_pri - assign $3\xive11_pri$next[7:0]$2265 \xive11_pri - assign $3\xive12_pri$next[7:0]$2266 \xive12_pri - assign $3\xive13_pri$next[7:0]$2267 \xive13_pri - assign $3\xive14_pri$next[7:0]$2268 \xive14_pri - assign $3\xive15_pri$next[7:0]$2269 \xive15_pri - assign $3\xive1_pri$next[7:0]$2270 \xive1_pri - assign $3\xive2_pri$next[7:0]$2271 \xive2_pri - assign $3\xive3_pri$next[7:0]$2272 \xive3_pri - assign $3\xive4_pri$next[7:0]$2273 \xive4_pri - assign $3\xive5_pri$next[7:0]$2274 \xive5_pri - assign $3\xive6_pri$next[7:0]$2275 \xive6_pri - assign $3\xive7_pri$next[7:0]$2276 \xive7_pri - assign $3\xive8_pri$next[7:0]$2277 \xive8_pri - assign $3\xive9_pri$next[7:0]$2278 \xive9_pri - end - case - assign $2\xive0_pri$next[7:0]$2247 \xive0_pri - assign $2\xive10_pri$next[7:0]$2248 \xive10_pri - assign $2\xive11_pri$next[7:0]$2249 \xive11_pri - assign $2\xive12_pri$next[7:0]$2250 \xive12_pri - assign $2\xive13_pri$next[7:0]$2251 \xive13_pri - assign $2\xive14_pri$next[7:0]$2252 \xive14_pri - assign $2\xive15_pri$next[7:0]$2253 \xive15_pri - assign $2\xive1_pri$next[7:0]$2254 \xive1_pri - assign $2\xive2_pri$next[7:0]$2255 \xive2_pri - assign $2\xive3_pri$next[7:0]$2256 \xive3_pri - assign $2\xive4_pri$next[7:0]$2257 \xive4_pri - assign $2\xive5_pri$next[7:0]$2258 \xive5_pri - assign $2\xive6_pri$next[7:0]$2259 \xive6_pri - assign $2\xive7_pri$next[7:0]$2260 \xive7_pri - assign $2\xive8_pri$next[7:0]$2261 \xive8_pri - assign $2\xive9_pri$next[7:0]$2262 \xive9_pri - end - case - assign $1\xive0_pri$next[7:0]$2231 \xive0_pri - assign $1\xive10_pri$next[7:0]$2232 \xive10_pri - assign $1\xive11_pri$next[7:0]$2233 \xive11_pri - assign $1\xive12_pri$next[7:0]$2234 \xive12_pri - assign $1\xive13_pri$next[7:0]$2235 \xive13_pri - assign $1\xive14_pri$next[7:0]$2236 \xive14_pri - assign $1\xive15_pri$next[7:0]$2237 \xive15_pri - assign $1\xive1_pri$next[7:0]$2238 \xive1_pri - assign $1\xive2_pri$next[7:0]$2239 \xive2_pri - assign $1\xive3_pri$next[7:0]$2240 \xive3_pri - assign $1\xive4_pri$next[7:0]$2241 \xive4_pri - assign $1\xive5_pri$next[7:0]$2242 \xive5_pri - assign $1\xive6_pri$next[7:0]$2243 \xive6_pri - assign $1\xive7_pri$next[7:0]$2244 \xive7_pri - assign $1\xive8_pri$next[7:0]$2245 \xive8_pri - assign $1\xive9_pri$next[7:0]$2246 \xive9_pri - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $4\xive0_pri$next[7:0]$2279 8'11111111 - assign $4\xive1_pri$next[7:0]$2286 8'11111111 - assign $4\xive2_pri$next[7:0]$2287 8'11111111 - assign $4\xive3_pri$next[7:0]$2288 8'11111111 - assign $4\xive4_pri$next[7:0]$2289 8'11111111 - assign $4\xive5_pri$next[7:0]$2290 8'11111111 - assign $4\xive6_pri$next[7:0]$2291 8'11111111 - assign $4\xive7_pri$next[7:0]$2292 8'11111111 - assign $4\xive8_pri$next[7:0]$2293 8'11111111 - assign $4\xive9_pri$next[7:0]$2294 8'11111111 - assign $4\xive10_pri$next[7:0]$2280 8'11111111 - assign $4\xive11_pri$next[7:0]$2281 8'11111111 - assign $4\xive12_pri$next[7:0]$2282 8'11111111 - assign $4\xive13_pri$next[7:0]$2283 8'11111111 - assign $4\xive14_pri$next[7:0]$2284 8'11111111 - assign $4\xive15_pri$next[7:0]$2285 8'11111111 - case - assign $4\xive0_pri$next[7:0]$2279 $1\xive0_pri$next[7:0]$2231 - assign $4\xive10_pri$next[7:0]$2280 $1\xive10_pri$next[7:0]$2232 - assign $4\xive11_pri$next[7:0]$2281 $1\xive11_pri$next[7:0]$2233 - assign $4\xive12_pri$next[7:0]$2282 $1\xive12_pri$next[7:0]$2234 - assign $4\xive13_pri$next[7:0]$2283 $1\xive13_pri$next[7:0]$2235 - assign $4\xive14_pri$next[7:0]$2284 $1\xive14_pri$next[7:0]$2236 - assign $4\xive15_pri$next[7:0]$2285 $1\xive15_pri$next[7:0]$2237 - assign $4\xive1_pri$next[7:0]$2286 $1\xive1_pri$next[7:0]$2238 - assign $4\xive2_pri$next[7:0]$2287 $1\xive2_pri$next[7:0]$2239 - assign $4\xive3_pri$next[7:0]$2288 $1\xive3_pri$next[7:0]$2240 - assign $4\xive4_pri$next[7:0]$2289 $1\xive4_pri$next[7:0]$2241 - assign $4\xive5_pri$next[7:0]$2290 $1\xive5_pri$next[7:0]$2242 - assign $4\xive6_pri$next[7:0]$2291 $1\xive6_pri$next[7:0]$2243 - assign $4\xive7_pri$next[7:0]$2292 $1\xive7_pri$next[7:0]$2244 - assign $4\xive8_pri$next[7:0]$2293 $1\xive8_pri$next[7:0]$2245 - assign $4\xive9_pri$next[7:0]$2294 $1\xive9_pri$next[7:0]$2246 - end - sync always - update \xive0_pri$next $0\xive0_pri$next[7:0]$2215 - update \xive10_pri$next $0\xive10_pri$next[7:0]$2216 - update \xive11_pri$next $0\xive11_pri$next[7:0]$2217 - update \xive12_pri$next $0\xive12_pri$next[7:0]$2218 - update \xive13_pri$next $0\xive13_pri$next[7:0]$2219 - update \xive14_pri$next $0\xive14_pri$next[7:0]$2220 - update \xive15_pri$next $0\xive15_pri$next[7:0]$2221 - update \xive1_pri$next $0\xive1_pri$next[7:0]$2222 - update \xive2_pri$next $0\xive2_pri$next[7:0]$2223 - update \xive3_pri$next $0\xive3_pri$next[7:0]$2224 - update \xive4_pri$next $0\xive4_pri$next[7:0]$2225 - update \xive5_pri$next $0\xive5_pri$next[7:0]$2226 - update \xive6_pri$next $0\xive6_pri$next[7:0]$2227 - update \xive7_pri$next $0\xive7_pri$next[7:0]$2228 - update \xive8_pri$next $0\xive8_pri$next[7:0]$2229 - update \xive9_pri$next $0\xive9_pri$next[7:0]$2230 - end - attribute \src "libresoc.v:51133.3-51142.6" - process $proc$libresoc.v:51133$2295 - assign { } { } - assign { } { } - assign $0\cur_pri0[7:0] $1\cur_pri0[7:0] - attribute \src "libresoc.v:51134.5-51134.29" - switch \initial - attribute \src "libresoc.v:51134.9-51134.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$77 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_pri0[7:0] \xive0_pri - case - assign $1\cur_pri0[7:0] \max_pri - end - sync always - update \cur_pri0 $0\cur_pri0[7:0] - end - attribute \src "libresoc.v:51143.3-51152.6" - process $proc$libresoc.v:51143$2296 - assign { } { } - assign { } { } - assign $0\cur_idx0[3:0] $1\cur_idx0[3:0] - attribute \src "libresoc.v:51144.5-51144.29" - switch \initial - attribute \src "libresoc.v:51144.9-51144.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$81 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_idx0[3:0] 4'0000 - case - assign $1\cur_idx0[3:0] \max_idx - end - sync always - update \cur_idx0 $0\cur_idx0[3:0] - end - attribute \src "libresoc.v:51153.3-51162.6" - process $proc$libresoc.v:51153$2297 - assign { } { } - assign { } { } - assign $0\cur_pri1[7:0] $1\cur_pri1[7:0] - attribute \src "libresoc.v:51154.5-51154.29" - switch \initial - attribute \src "libresoc.v:51154.9-51154.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$85 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_pri1[7:0] \xive1_pri - case - assign $1\cur_pri1[7:0] \cur_pri0 - end - sync always - update \cur_pri1 $0\cur_pri1[7:0] - end - attribute \src "libresoc.v:51163.3-51172.6" - process $proc$libresoc.v:51163$2298 - assign { } { } - assign { } { } - assign $0\cur_idx1[3:0] $1\cur_idx1[3:0] - attribute \src "libresoc.v:51164.5-51164.29" - switch \initial - attribute \src "libresoc.v:51164.9-51164.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$89 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_idx1[3:0] 4'0001 - case - assign $1\cur_idx1[3:0] \cur_idx0 - end - sync always - update \cur_idx1 $0\cur_idx1[3:0] - end - attribute \src "libresoc.v:51173.3-51182.6" - process $proc$libresoc.v:51173$2299 - assign { } { } - assign { } { } - assign $0\cur_pri2[7:0] $1\cur_pri2[7:0] - attribute \src "libresoc.v:51174.5-51174.29" - switch \initial - attribute \src "libresoc.v:51174.9-51174.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$93 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_pri2[7:0] \xive2_pri - case - assign $1\cur_pri2[7:0] \cur_pri1 - end - sync always - update \cur_pri2 $0\cur_pri2[7:0] - end - attribute \src "libresoc.v:51183.3-51192.6" - process $proc$libresoc.v:51183$2300 - assign { } { } - assign { } { } - assign $0\cur_idx2[3:0] $1\cur_idx2[3:0] - attribute \src "libresoc.v:51184.5-51184.29" - switch \initial - attribute \src "libresoc.v:51184.9-51184.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$97 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_idx2[3:0] 4'0010 - case - assign $1\cur_idx2[3:0] \cur_idx1 - end - sync always - update \cur_idx2 $0\cur_idx2[3:0] - end - attribute \src "libresoc.v:51193.3-51202.6" - process $proc$libresoc.v:51193$2301 - assign { } { } - assign { } { } - assign $0\cur_pri3[7:0] $1\cur_pri3[7:0] - attribute \src "libresoc.v:51194.5-51194.29" - switch \initial - attribute \src "libresoc.v:51194.9-51194.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$101 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_pri3[7:0] \xive3_pri - case - assign $1\cur_pri3[7:0] \cur_pri2 - end - sync always - update \cur_pri3 $0\cur_pri3[7:0] - end - attribute \src "libresoc.v:51203.3-51212.6" - process $proc$libresoc.v:51203$2302 - assign { } { } - assign { } { } - assign $0\cur_idx3[3:0] $1\cur_idx3[3:0] - attribute \src "libresoc.v:51204.5-51204.29" - switch \initial - attribute \src "libresoc.v:51204.9-51204.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$105 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_idx3[3:0] 4'0011 - case - assign $1\cur_idx3[3:0] \cur_idx2 - end - sync always - update \cur_idx3 $0\cur_idx3[3:0] - end - attribute \src "libresoc.v:51213.3-51222.6" - process $proc$libresoc.v:51213$2303 - assign { } { } - assign { } { } - assign $0\cur_pri4[7:0] $1\cur_pri4[7:0] - attribute \src "libresoc.v:51214.5-51214.29" - switch \initial - attribute \src "libresoc.v:51214.9-51214.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$109 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_pri4[7:0] \xive4_pri - case - assign $1\cur_pri4[7:0] \cur_pri3 - end - sync always - update \cur_pri4 $0\cur_pri4[7:0] - end - attribute \src "libresoc.v:51223.3-51231.6" - process $proc$libresoc.v:51223$2304 - assign { } { } - assign { } { } - assign $0\int_level_l$next[15:0]$2305 $1\int_level_l$next[15:0]$2306 - attribute \src "libresoc.v:51224.5-51224.29" - switch \initial - attribute \src "libresoc.v:51224.9-51224.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\int_level_l$next[15:0]$2306 16'0000000000000000 - case - assign $1\int_level_l$next[15:0]$2306 \int_level_i - end - sync always - update \int_level_l$next $0\int_level_l$next[15:0]$2305 - end - attribute \src "libresoc.v:51232.3-51241.6" - process $proc$libresoc.v:51232$2307 - assign { } { } - assign { } { } - assign $0\cur_idx4[3:0] $1\cur_idx4[3:0] - attribute \src "libresoc.v:51233.5-51233.29" - switch \initial - attribute \src "libresoc.v:51233.9-51233.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$113 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_idx4[3:0] 4'0100 - case - assign $1\cur_idx4[3:0] \cur_idx3 - end - sync always - update \cur_idx4 $0\cur_idx4[3:0] - end - attribute \src "libresoc.v:51242.3-51251.6" - process $proc$libresoc.v:51242$2308 - assign { } { } - assign { } { } - assign $0\cur_pri5[7:0] $1\cur_pri5[7:0] - attribute \src "libresoc.v:51243.5-51243.29" - switch \initial - attribute \src "libresoc.v:51243.9-51243.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$117 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_pri5[7:0] \xive5_pri - case - assign $1\cur_pri5[7:0] \cur_pri4 - end - sync always - update \cur_pri5 $0\cur_pri5[7:0] - end - attribute \src "libresoc.v:51252.3-51261.6" - process $proc$libresoc.v:51252$2309 - assign { } { } - assign { } { } - assign $0\cur_idx5[3:0] $1\cur_idx5[3:0] - attribute \src "libresoc.v:51253.5-51253.29" - switch \initial - attribute \src "libresoc.v:51253.9-51253.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$121 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_idx5[3:0] 4'0101 - case - assign $1\cur_idx5[3:0] \cur_idx4 - end - sync always - update \cur_idx5 $0\cur_idx5[3:0] - end - attribute \src "libresoc.v:51262.3-51271.6" - process $proc$libresoc.v:51262$2310 - assign { } { } - assign { } { } - assign $0\cur_pri6[7:0] $1\cur_pri6[7:0] - attribute \src "libresoc.v:51263.5-51263.29" - switch \initial - attribute \src "libresoc.v:51263.9-51263.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$125 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_pri6[7:0] \xive6_pri - case - assign $1\cur_pri6[7:0] \cur_pri5 - end - sync always - update \cur_pri6 $0\cur_pri6[7:0] - end - attribute \src "libresoc.v:51272.3-51281.6" - process $proc$libresoc.v:51272$2311 - assign { } { } - assign { } { } - assign $0\cur_idx6[3:0] $1\cur_idx6[3:0] - attribute \src "libresoc.v:51273.5-51273.29" - switch \initial - attribute \src "libresoc.v:51273.9-51273.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$129 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_idx6[3:0] 4'0110 - case - assign $1\cur_idx6[3:0] \cur_idx5 - end - sync always - update \cur_idx6 $0\cur_idx6[3:0] - end - attribute \src "libresoc.v:51282.3-51291.6" - process $proc$libresoc.v:51282$2312 - assign { } { } - assign { } { } - assign $0\cur_pri7[7:0] $1\cur_pri7[7:0] - attribute \src "libresoc.v:51283.5-51283.29" - switch \initial - attribute \src "libresoc.v:51283.9-51283.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$133 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_pri7[7:0] \xive7_pri - case - assign $1\cur_pri7[7:0] \cur_pri6 - end - sync always - update \cur_pri7 $0\cur_pri7[7:0] - end - attribute \src "libresoc.v:51292.3-51301.6" - process $proc$libresoc.v:51292$2313 - assign { } { } - assign { } { } - assign $0\cur_idx7[3:0] $1\cur_idx7[3:0] - attribute \src "libresoc.v:51293.5-51293.29" - switch \initial - attribute \src "libresoc.v:51293.9-51293.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$137 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_idx7[3:0] 4'0111 - case - assign $1\cur_idx7[3:0] \cur_idx6 - end - sync always - update \cur_idx7 $0\cur_idx7[3:0] - end - attribute \src "libresoc.v:51302.3-51311.6" - process $proc$libresoc.v:51302$2314 - assign { } { } - assign { } { } - assign $0\cur_pri8[7:0] $1\cur_pri8[7:0] - attribute \src "libresoc.v:51303.5-51303.29" - switch \initial - attribute \src "libresoc.v:51303.9-51303.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$141 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_pri8[7:0] \xive8_pri - case - assign $1\cur_pri8[7:0] \cur_pri7 - end - sync always - update \cur_pri8 $0\cur_pri8[7:0] - end - attribute \src "libresoc.v:51312.3-51321.6" - process $proc$libresoc.v:51312$2315 - assign { } { } - assign { } { } - assign $0\cur_idx8[3:0] $1\cur_idx8[3:0] - attribute \src "libresoc.v:51313.5-51313.29" - switch \initial - attribute \src "libresoc.v:51313.9-51313.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$145 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_idx8[3:0] 4'1000 - case - assign $1\cur_idx8[3:0] \cur_idx7 - end - sync always - update \cur_idx8 $0\cur_idx8[3:0] - end - attribute \src "libresoc.v:51322.3-51331.6" - process $proc$libresoc.v:51322$2316 - assign { } { } - assign { } { } - assign $0\cur_pri9[7:0] $1\cur_pri9[7:0] - attribute \src "libresoc.v:51323.5-51323.29" - switch \initial - attribute \src "libresoc.v:51323.9-51323.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$149 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_pri9[7:0] \xive9_pri - case - assign $1\cur_pri9[7:0] \cur_pri8 - end - sync always - update \cur_pri9 $0\cur_pri9[7:0] - end - attribute \src "libresoc.v:51332.3-51341.6" - process $proc$libresoc.v:51332$2317 - assign { } { } - assign { } { } - assign $0\cur_idx9[3:0] $1\cur_idx9[3:0] - attribute \src "libresoc.v:51333.5-51333.29" - switch \initial - attribute \src "libresoc.v:51333.9-51333.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$153 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_idx9[3:0] 4'1001 - case - assign $1\cur_idx9[3:0] \cur_idx8 - end - sync always - update \cur_idx9 $0\cur_idx9[3:0] - end - attribute \src "libresoc.v:51342.3-51351.6" - process $proc$libresoc.v:51342$2318 - assign { } { } - assign { } { } - assign $0\cur_pri10[7:0] $1\cur_pri10[7:0] - attribute \src "libresoc.v:51343.5-51343.29" - switch \initial - attribute \src "libresoc.v:51343.9-51343.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$157 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_pri10[7:0] \xive10_pri - case - assign $1\cur_pri10[7:0] \cur_pri9 - end - sync always - update \cur_pri10 $0\cur_pri10[7:0] - end - attribute \src "libresoc.v:51352.3-51361.6" - process $proc$libresoc.v:51352$2319 - assign { } { } - assign { } { } - assign $0\cur_idx10[3:0] $1\cur_idx10[3:0] - attribute \src "libresoc.v:51353.5-51353.29" - switch \initial - attribute \src "libresoc.v:51353.9-51353.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$161 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_idx10[3:0] 4'1010 - case - assign $1\cur_idx10[3:0] \cur_idx9 - end - sync always - update \cur_idx10 $0\cur_idx10[3:0] - end - attribute \src "libresoc.v:51362.3-51371.6" - process $proc$libresoc.v:51362$2320 - assign { } { } - assign { } { } - assign $0\cur_pri11[7:0] $1\cur_pri11[7:0] - attribute \src "libresoc.v:51363.5-51363.29" - switch \initial - attribute \src "libresoc.v:51363.9-51363.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$165 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_pri11[7:0] \xive11_pri - case - assign $1\cur_pri11[7:0] \cur_pri10 - end - sync always - update \cur_pri11 $0\cur_pri11[7:0] - end - attribute \src "libresoc.v:51372.3-51381.6" - process $proc$libresoc.v:51372$2321 - assign { } { } - assign { } { } - assign $0\cur_idx11[3:0] $1\cur_idx11[3:0] - attribute \src "libresoc.v:51373.5-51373.29" - switch \initial - attribute \src "libresoc.v:51373.9-51373.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$169 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_idx11[3:0] 4'1011 - case - assign $1\cur_idx11[3:0] \cur_idx10 - end - sync always - update \cur_idx11 $0\cur_idx11[3:0] - end - attribute \src "libresoc.v:51382.3-51391.6" - process $proc$libresoc.v:51382$2322 - assign { } { } - assign { } { } - assign $0\cur_pri12[7:0] $1\cur_pri12[7:0] - attribute \src "libresoc.v:51383.5-51383.29" - switch \initial - attribute \src "libresoc.v:51383.9-51383.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$173 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_pri12[7:0] \xive12_pri - case - assign $1\cur_pri12[7:0] \cur_pri11 - end - sync always - update \cur_pri12 $0\cur_pri12[7:0] - end - attribute \src "libresoc.v:51392.3-51401.6" - process $proc$libresoc.v:51392$2323 - assign { } { } - assign { } { } - assign $0\cur_idx12[3:0] $1\cur_idx12[3:0] - attribute \src "libresoc.v:51393.5-51393.29" - switch \initial - attribute \src "libresoc.v:51393.9-51393.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$177 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_idx12[3:0] 4'1100 - case - assign $1\cur_idx12[3:0] \cur_idx11 - end - sync always - update \cur_idx12 $0\cur_idx12[3:0] - end - attribute \src "libresoc.v:51402.3-51411.6" - process $proc$libresoc.v:51402$2324 - assign { } { } - assign { } { } - assign $0\cur_pri13[7:0] $1\cur_pri13[7:0] - attribute \src "libresoc.v:51403.5-51403.29" - switch \initial - attribute \src "libresoc.v:51403.9-51403.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$181 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_pri13[7:0] \xive13_pri - case - assign $1\cur_pri13[7:0] \cur_pri12 - end - sync always - update \cur_pri13 $0\cur_pri13[7:0] - end - attribute \src "libresoc.v:51412.3-51421.6" - process $proc$libresoc.v:51412$2325 - assign { } { } - assign { } { } - assign $0\cur_idx13[3:0] $1\cur_idx13[3:0] - attribute \src "libresoc.v:51413.5-51413.29" - switch \initial - attribute \src "libresoc.v:51413.9-51413.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$185 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_idx13[3:0] 4'1101 - case - assign $1\cur_idx13[3:0] \cur_idx12 - end - sync always - update \cur_idx13 $0\cur_idx13[3:0] - end - attribute \src "libresoc.v:51422.3-51431.6" - process $proc$libresoc.v:51422$2326 - assign { } { } - assign { } { } - assign $0\cur_pri14[7:0] $1\cur_pri14[7:0] - attribute \src "libresoc.v:51423.5-51423.29" - switch \initial - attribute \src "libresoc.v:51423.9-51423.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$189 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_pri14[7:0] \xive14_pri - case - assign $1\cur_pri14[7:0] \cur_pri13 - end - sync always - update \cur_pri14 $0\cur_pri14[7:0] - end - attribute \src "libresoc.v:51432.3-51481.6" - process $proc$libresoc.v:51432$2327 - assign { } { } - assign { } { } - assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:51433.5-51433.29" - switch \initial - attribute \src "libresoc.v:51433.9-51433.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" - switch { \reg_is_debug \reg_is_config \reg_is_xive } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $1\be_out[31:0] $2\be_out[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - switch \reg_idx - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$7 } - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$11 } - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$15 } - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$19 } - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$23 } - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$27 } - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$31 } - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$35 } - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$39 } - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$43 } - attribute \src "libresoc.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$47 } - attribute \src "libresoc.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$51 } - attribute \src "libresoc.v:0.0-0.0" - case 4'1100 - assign { } { } - assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$55 } - attribute \src "libresoc.v:0.0-0.0" - case 4'1101 - assign { } { } - assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$59 } - attribute \src "libresoc.v:0.0-0.0" - case 4'1110 - assign { } { } - assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$63 } - attribute \src "libresoc.v:0.0-0.0" - case 4'---- - assign { } { } - assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$67 } - case - assign $2\be_out[31:0] 0 - end - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $1\be_out[31:0] 134217744 - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $1\be_out[31:0] { \icp_r_src 20'00000000000000000000 \icp_r_pri } - case - assign $1\be_out[31:0] 0 - end - sync always - update \be_out $0\be_out[31:0] - end - attribute \src "libresoc.v:51482.3-51491.6" - process $proc$libresoc.v:51482$2328 - assign { } { } - assign { } { } - assign $0\cur_idx14[3:0] $1\cur_idx14[3:0] - attribute \src "libresoc.v:51483.5-51483.29" - switch \initial - attribute \src "libresoc.v:51483.9-51483.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$193 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_idx14[3:0] 4'1110 - case - assign $1\cur_idx14[3:0] \cur_idx13 - end - sync always - update \cur_idx14 $0\cur_idx14[3:0] - end - attribute \src "libresoc.v:51492.3-51501.6" - process $proc$libresoc.v:51492$2329 - assign { } { } - assign { } { } - assign $0\cur_pri15[7:0] $1\cur_pri15[7:0] - attribute \src "libresoc.v:51493.5-51493.29" - switch \initial - attribute \src "libresoc.v:51493.9-51493.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$197 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_pri15[7:0] \xive15_pri - case - assign $1\cur_pri15[7:0] \cur_pri14 - end - sync always - update \cur_pri15 $0\cur_pri15[7:0] - end - attribute \src "libresoc.v:51502.3-51511.6" - process $proc$libresoc.v:51502$2330 - assign { } { } - assign { } { } - assign $0\cur_idx15[3:0] $1\cur_idx15[3:0] - attribute \src "libresoc.v:51503.5-51503.29" - switch \initial - attribute \src "libresoc.v:51503.9-51503.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - switch \$201 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cur_idx15[3:0] 4'1111 - case - assign $1\cur_idx15[3:0] \cur_idx14 - end - sync always - update \cur_idx15 $0\cur_idx15[3:0] - end - attribute \src "libresoc.v:51512.3-51521.6" - process $proc$libresoc.v:51512$2331 - assign { } { } - assign { } { } - assign $0\ibit[0:0] $1\ibit[0:0] - attribute \src "libresoc.v:51513.5-51513.29" - switch \initial - attribute \src "libresoc.v:51513.9-51513.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" - switch { \reg_is_debug \reg_is_config \reg_is_xive } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $1\ibit[0:0] \$71 - case - assign $1\ibit[0:0] 1'0 - end - sync always - update \ibit $0\ibit[0:0] - end - attribute \src "libresoc.v:51522.3-51530.6" - process $proc$libresoc.v:51522$2332 - assign { } { } - assign { } { } - assign $0\ics_wb__dat_r$next[31:0]$2333 $1\ics_wb__dat_r$next[31:0]$2334 - attribute \src "libresoc.v:51523.5-51523.29" - switch \initial - attribute \src "libresoc.v:51523.9-51523.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ics_wb__dat_r$next[31:0]$2334 0 - case - assign $1\ics_wb__dat_r$next[31:0]$2334 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } - end - sync always - update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$2333 - end - attribute \src "libresoc.v:51531.3-51539.6" - process $proc$libresoc.v:51531$2335 - assign { } { } - assign { } { } - assign $0\ics_wb__ack$next[0:0]$2336 $1\ics_wb__ack$next[0:0]$2337 - attribute \src "libresoc.v:51532.5-51532.29" - switch \initial - attribute \src "libresoc.v:51532.9-51532.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \intclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ics_wb__ack$next[0:0]$2337 1'0 - case - assign $1\ics_wb__ack$next[0:0]$2337 \wb_valid - end - sync always - update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$2336 - end - connect \$7 $ternary$libresoc.v:50902$2090_Y - connect \$99 $lt$libresoc.v:50903$2091_Y - connect \$101 $and$libresoc.v:50904$2092_Y - connect \$103 $lt$libresoc.v:50905$2093_Y - connect \$105 $and$libresoc.v:50906$2094_Y - connect \$107 $lt$libresoc.v:50907$2095_Y - connect \$109 $and$libresoc.v:50908$2096_Y - connect \$111 $lt$libresoc.v:50909$2097_Y - connect \$113 $and$libresoc.v:50910$2098_Y - connect \$115 $lt$libresoc.v:50911$2099_Y - connect \$117 $and$libresoc.v:50912$2100_Y - connect \$119 $lt$libresoc.v:50913$2101_Y - connect \$121 $and$libresoc.v:50914$2102_Y - connect \$123 $lt$libresoc.v:50915$2103_Y - connect \$125 $and$libresoc.v:50916$2104_Y - connect \$127 $lt$libresoc.v:50917$2105_Y - connect \$12 $eq$libresoc.v:50918$2106_Y - connect \$129 $and$libresoc.v:50919$2107_Y - connect \$131 $lt$libresoc.v:50920$2108_Y - connect \$133 $and$libresoc.v:50921$2109_Y - connect \$135 $lt$libresoc.v:50922$2110_Y - connect \$137 $and$libresoc.v:50923$2111_Y - connect \$11 $ternary$libresoc.v:50924$2112_Y - connect \$139 $lt$libresoc.v:50925$2113_Y - connect \$141 $and$libresoc.v:50926$2114_Y - connect \$143 $lt$libresoc.v:50927$2115_Y - connect \$145 $and$libresoc.v:50928$2116_Y - connect \$147 $lt$libresoc.v:50929$2117_Y - connect \$149 $and$libresoc.v:50930$2118_Y - connect \$151 $lt$libresoc.v:50931$2119_Y - connect \$153 $and$libresoc.v:50932$2120_Y - connect \$155 $lt$libresoc.v:50933$2121_Y - connect \$157 $and$libresoc.v:50934$2122_Y - connect \$159 $lt$libresoc.v:50935$2123_Y - connect \$161 $and$libresoc.v:50936$2124_Y - connect \$163 $lt$libresoc.v:50937$2125_Y - connect \$165 $and$libresoc.v:50938$2126_Y - connect \$167 $lt$libresoc.v:50939$2127_Y - connect \$16 $eq$libresoc.v:50940$2128_Y - connect \$169 $and$libresoc.v:50941$2129_Y - connect \$171 $lt$libresoc.v:50942$2130_Y - connect \$173 $and$libresoc.v:50943$2131_Y - connect \$175 $lt$libresoc.v:50944$2132_Y - connect \$177 $and$libresoc.v:50945$2133_Y - connect \$15 $ternary$libresoc.v:50946$2134_Y - connect \$179 $lt$libresoc.v:50947$2135_Y - connect \$181 $and$libresoc.v:50948$2136_Y - connect \$183 $lt$libresoc.v:50949$2137_Y - connect \$185 $and$libresoc.v:50950$2138_Y - connect \$187 $lt$libresoc.v:50951$2139_Y - connect \$189 $and$libresoc.v:50952$2140_Y - connect \$191 $lt$libresoc.v:50953$2141_Y - connect \$193 $and$libresoc.v:50954$2142_Y - connect \$195 $lt$libresoc.v:50955$2143_Y - connect \$197 $and$libresoc.v:50956$2144_Y - connect \$1 $eq$libresoc.v:50957$2145_Y - connect \$199 $lt$libresoc.v:50958$2146_Y - connect \$201 $and$libresoc.v:50959$2147_Y - connect \$204 $eq$libresoc.v:50960$2148_Y - connect \$203 $ternary$libresoc.v:50961$2149_Y - connect \$20 $eq$libresoc.v:50962$2150_Y - connect \$19 $ternary$libresoc.v:50963$2151_Y - connect \$24 $eq$libresoc.v:50964$2152_Y - connect \$23 $ternary$libresoc.v:50965$2153_Y - connect \$28 $eq$libresoc.v:50966$2154_Y - connect \$27 $ternary$libresoc.v:50967$2155_Y - connect \$32 $eq$libresoc.v:50968$2156_Y - connect \$31 $ternary$libresoc.v:50969$2157_Y - connect \$36 $eq$libresoc.v:50970$2158_Y - connect \$35 $ternary$libresoc.v:50971$2159_Y - connect \$3 $eq$libresoc.v:50972$2160_Y - connect \$40 $eq$libresoc.v:50973$2161_Y - connect \$39 $ternary$libresoc.v:50974$2162_Y - connect \$44 $eq$libresoc.v:50975$2163_Y - connect \$43 $ternary$libresoc.v:50976$2164_Y - connect \$48 $eq$libresoc.v:50977$2165_Y - connect \$47 $ternary$libresoc.v:50978$2166_Y - connect \$52 $eq$libresoc.v:50979$2167_Y - connect \$51 $ternary$libresoc.v:50980$2168_Y - connect \$56 $eq$libresoc.v:50981$2169_Y - connect \$55 $ternary$libresoc.v:50982$2170_Y - connect \$5 $and$libresoc.v:50983$2171_Y - connect \$60 $eq$libresoc.v:50984$2172_Y - connect \$59 $ternary$libresoc.v:50985$2173_Y - connect \$64 $eq$libresoc.v:50986$2174_Y - connect \$63 $ternary$libresoc.v:50987$2175_Y - connect \$68 $eq$libresoc.v:50988$2176_Y - connect \$67 $ternary$libresoc.v:50989$2177_Y - connect \$71 $shr$libresoc.v:50990$2178_Y [0] - connect \$73 $and$libresoc.v:50991$2179_Y - connect \$75 $lt$libresoc.v:50992$2180_Y - connect \$77 $and$libresoc.v:50993$2181_Y - connect \$79 $lt$libresoc.v:50994$2182_Y - connect \$81 $and$libresoc.v:50995$2183_Y - connect \$83 $lt$libresoc.v:50996$2184_Y - connect \$85 $and$libresoc.v:50997$2185_Y - connect \$87 $lt$libresoc.v:50998$2186_Y - connect \$8 $eq$libresoc.v:50999$2187_Y - connect \$89 $and$libresoc.v:51000$2188_Y - connect \$91 $lt$libresoc.v:51001$2189_Y - connect \$93 $and$libresoc.v:51002$2190_Y - connect \$95 $lt$libresoc.v:51003$2191_Y - connect \$97 $and$libresoc.v:51004$2192_Y - connect \icp_r_pri \$203 - connect \icp_r_src \cur_idx15 - connect \max_idx 4'0000 - connect \max_pri 8'11111111 - connect { \icp_o_pri$next \icp_o_src$next } { \icp_r_pri \icp_r_src } - connect \be_in { \ics_wb__dat_w [7:0] \ics_wb__dat_w [15:8] \ics_wb__dat_w [23:16] \ics_wb__dat_w [31:24] } - connect \wb_valid \$5 - connect \reg_idx \ics_wb__adr [3:0] - connect \reg_is_debug \$3 - connect \reg_is_config \$1 - connect \reg_is_xive \ics_wb__adr [9] -end diff --git a/experiments9/non_generated/partial_core_ls180.il b/experiments9/non_generated/partial_core_ls180.il new file mode 100644 index 0000000..0b6e584 --- /dev/null +++ b/experiments9/non_generated/partial_core_ls180.il @@ -0,0 +1,146332 @@ +# Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os) +autoidx 3715 +attribute \src "libresoc.v:5.1-277.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag._fsm" +attribute \generator "nMigen" +module \_fsm + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $0\fsm_state$next[3:0]$25 + attribute \src "libresoc.v:91.3-92.35" + wire width 4 $0\fsm_state[3:0] + attribute \src "libresoc.v:6.7-6.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:97.3-124.6" + wire $0\isdr$next[0:0]$21 + attribute \src "libresoc.v:93.3-94.25" + wire $0\isdr[0:0] + attribute \src "libresoc.v:240.3-267.6" + wire $0\isir$next[0:0]$38 + attribute \src "libresoc.v:95.3-96.25" + wire $0\isir[0:0] + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $10\fsm_state$next[3:0]$35 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $11\fsm_state$next[3:0]$36 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $1\fsm_state$next[3:0]$26 + attribute \src "libresoc.v:46.13-46.29" + wire width 4 $1\fsm_state[3:0] + attribute \src "libresoc.v:97.3-124.6" + wire $1\isdr$next[0:0]$22 + attribute \src "libresoc.v:51.7-51.18" + wire $1\isdr[0:0] + attribute \src "libresoc.v:240.3-267.6" + wire $1\isir$next[0:0]$39 + attribute \src "libresoc.v:56.7-56.18" + wire $1\isir[0:0] + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $2\fsm_state$next[3:0]$27 + attribute \src "libresoc.v:97.3-124.6" + wire $2\isdr$next[0:0]$23 + attribute \src "libresoc.v:240.3-267.6" + wire $2\isir$next[0:0]$40 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $3\fsm_state$next[3:0]$28 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $4\fsm_state$next[3:0]$29 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $5\fsm_state$next[3:0]$30 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $6\fsm_state$next[3:0]$31 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $7\fsm_state$next[3:0]$32 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $8\fsm_state$next[3:0]$33 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $9\fsm_state$next[3:0]$34 + attribute \src "libresoc.v:75.17-75.110" + wire $eq$libresoc.v:75$1_Y + attribute \src "libresoc.v:76.18-76.111" + wire $eq$libresoc.v:76$2_Y + attribute \src "libresoc.v:77.18-77.111" + wire $eq$libresoc.v:77$3_Y + attribute \src "libresoc.v:78.18-78.111" + wire $eq$libresoc.v:78$4_Y + attribute \src "libresoc.v:79.18-79.111" + wire $eq$libresoc.v:79$5_Y + attribute \src "libresoc.v:80.17-80.108" + wire $eq$libresoc.v:80$6_Y + attribute \src "libresoc.v:81.18-81.111" + wire $eq$libresoc.v:81$7_Y + attribute \src "libresoc.v:82.18-82.111" + wire $eq$libresoc.v:82$8_Y + attribute \src "libresoc.v:83.18-83.111" + wire $eq$libresoc.v:83$9_Y + attribute \src "libresoc.v:84.18-84.111" + wire $eq$libresoc.v:84$10_Y + attribute \src "libresoc.v:85.18-85.111" + wire $eq$libresoc.v:85$11_Y + attribute \src "libresoc.v:86.18-86.111" + wire $eq$libresoc.v:86$12_Y + attribute \src "libresoc.v:87.18-87.112" + wire $eq$libresoc.v:87$13_Y + attribute \src "libresoc.v:88.17-88.108" + wire $eq$libresoc.v:88$14_Y + attribute \src "libresoc.v:89.17-89.108" + wire $eq$libresoc.v:89$15_Y + attribute \src "libresoc.v:90.17-90.108" + wire $eq$libresoc.v:90$16_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:117" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 9 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 10 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire output 11 \capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" + wire width 4 \fsm_state + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" + wire width 4 \fsm_state$next + attribute \src "libresoc.v:6.7-6.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire output 1 \isdr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire \isdr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire output 4 \isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire \isir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:50" + wire \local_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" + wire output 8 \negjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" + wire output 6 \negjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire output 7 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire output 5 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:37" + wire \rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire output 2 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:27" + wire output 3 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + cell $eq $eq$libresoc.v:75$1 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:75$1_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + cell $eq $eq$libresoc.v:76$2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:76$2_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" + cell $eq $eq$libresoc.v:77$3 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:77$3_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" + cell $eq $eq$libresoc.v:78$4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:78$4_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + cell $eq $eq$libresoc.v:79$5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:79$5_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" + cell $eq $eq$libresoc.v:80$6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 1'0 + connect \Y $eq$libresoc.v:80$6_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + cell $eq $eq$libresoc.v:81$7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:81$7_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" + cell $eq $eq$libresoc.v:82$8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:82$8_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" + cell $eq $eq$libresoc.v:83$9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:83$9_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" + cell $eq $eq$libresoc.v:84$10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:84$10_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" + cell $eq $eq$libresoc.v:85$11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:85$11_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" + cell $eq $eq$libresoc.v:86$12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:86$12_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" + cell $eq $eq$libresoc.v:87$13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:87$13_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" + cell $eq $eq$libresoc.v:88$14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 2'11 + connect \Y $eq$libresoc.v:88$14_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" + cell $eq $eq$libresoc.v:89$15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 3'101 + connect \Y $eq$libresoc.v:89$15_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:117" + cell $eq $eq$libresoc.v:90$16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 4'1000 + connect \Y $eq$libresoc.v:90$16_Y + end + attribute \src "libresoc.v:125.3-239.6" + process $proc$libresoc.v:125$24 + assign { } { } + assign { } { } + assign $0\fsm_state$next[3:0]$25 $1\fsm_state$next[3:0]$26 + attribute \src "libresoc.v:126.5-126.29" + switch \initial + attribute \src "libresoc.v:126.9-126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $2\fsm_state$next[3:0]$27 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[3:0]$27 4'0001 + case + assign $2\fsm_state$next[3:0]$27 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $3\fsm_state$next[3:0]$28 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[3:0]$28 4'0010 + case + assign $3\fsm_state$next[3:0]$28 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $4\fsm_state$next[3:0]$29 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[3:0]$29 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\fsm_state$next[3:0]$29 4'0100 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $5\fsm_state$next[3:0]$30 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[3:0]$30 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $5\fsm_state$next[3:0]$30 4'0000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $6\fsm_state$next[3:0]$31 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\fsm_state$next[3:0]$31 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $6\fsm_state$next[3:0]$31 4'0110 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $7\fsm_state$next[3:0]$32 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\fsm_state$next[3:0]$32 4'0110 + case + assign $7\fsm_state$next[3:0]$32 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $8\fsm_state$next[3:0]$33 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\fsm_state$next[3:0]$33 4'0111 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $8\fsm_state$next[3:0]$33 4'1000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $9\fsm_state$next[3:0]$34 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\fsm_state$next[3:0]$34 4'1001 + case + assign $9\fsm_state$next[3:0]$34 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $10\fsm_state$next[3:0]$35 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\fsm_state$next[3:0]$35 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $10\fsm_state$next[3:0]$35 4'1000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $11\fsm_state$next[3:0]$36 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\fsm_state$next[3:0]$36 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $11\fsm_state$next[3:0]$36 4'0010 + end + case + assign $1\fsm_state$next[3:0]$26 \fsm_state + end + sync always + update \fsm_state$next $0\fsm_state$next[3:0]$25 + end + attribute \src "libresoc.v:240.3-267.6" + process $proc$libresoc.v:240$37 + assign { } { } + assign { } { } + assign $0\isir$next[0:0]$38 $1\isir$next[0:0]$39 + attribute \src "libresoc.v:241.5-241.29" + switch \initial + attribute \src "libresoc.v:241.9-241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\isir$next[0:0]$39 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\isir$next[0:0]$39 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\isir$next[0:0]$39 $2\isir$next[0:0]$40 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\isir$next[0:0]$40 1'1 + case + assign $2\isir$next[0:0]$40 \isir + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\isir$next[0:0]$39 1'0 + case + assign $1\isir$next[0:0]$39 \isir + end + sync always + update \isir$next $0\isir$next[0:0]$38 + end + attribute \src "libresoc.v:46.13-46.29" + process $proc$libresoc.v:46$42 + assign { } { } + assign $1\fsm_state[3:0] 4'0000 + sync always + sync init + update \fsm_state $1\fsm_state[3:0] + end + attribute \src "libresoc.v:51.7-51.18" + process $proc$libresoc.v:51$43 + assign { } { } + assign $1\isdr[0:0] 1'0 + sync always + sync init + update \isdr $1\isdr[0:0] + end + attribute \src "libresoc.v:56.7-56.18" + process $proc$libresoc.v:56$44 + assign { } { } + assign $1\isir[0:0] 1'0 + sync always + sync init + update \isir $1\isir[0:0] + end + attribute \src "libresoc.v:6.7-6.20" + process $proc$libresoc.v:6$41 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:91.3-92.35" + process $proc$libresoc.v:91$17 + assign { } { } + assign $0\fsm_state[3:0] \fsm_state$next + sync posedge \local_clk + update \fsm_state $0\fsm_state[3:0] + end + attribute \src "libresoc.v:93.3-94.25" + process $proc$libresoc.v:93$18 + assign { } { } + assign $0\isdr[0:0] \isdr$next + sync posedge \local_clk + update \isdr $0\isdr[0:0] + end + attribute \src "libresoc.v:95.3-96.25" + process $proc$libresoc.v:95$19 + assign { } { } + assign $0\isir[0:0] \isir$next + sync posedge \local_clk + update \isir $0\isir[0:0] + end + attribute \src "libresoc.v:97.3-124.6" + process $proc$libresoc.v:97$20 + assign { } { } + assign { } { } + assign $0\isdr$next[0:0]$21 $1\isdr$next[0:0]$22 + attribute \src "libresoc.v:98.5-98.29" + switch \initial + attribute \src "libresoc.v:98.9-98.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\isdr$next[0:0]$22 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\isdr$next[0:0]$22 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\isdr$next[0:0]$22 $2\isdr$next[0:0]$23 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\isdr$next[0:0]$23 1'1 + case + assign $2\isdr$next[0:0]$23 \isdr + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\isdr$next[0:0]$22 1'0 + case + assign $1\isdr$next[0:0]$22 \isdr + end + sync always + update \isdr$next $0\isdr$next[0:0]$21 + end + connect \$9 $eq$libresoc.v:75$1_Y + connect \$11 $eq$libresoc.v:76$2_Y + connect \$13 $eq$libresoc.v:77$3_Y + connect \$15 $eq$libresoc.v:78$4_Y + connect \$17 $eq$libresoc.v:79$5_Y + connect \$1 $eq$libresoc.v:80$6_Y + connect \$19 $eq$libresoc.v:81$7_Y + connect \$21 $eq$libresoc.v:82$8_Y + connect \$23 $eq$libresoc.v:83$9_Y + connect \$25 $eq$libresoc.v:84$10_Y + connect \$27 $eq$libresoc.v:85$11_Y + connect \$29 $eq$libresoc.v:86$12_Y + connect \$31 $eq$libresoc.v:87$13_Y + connect \$3 $eq$libresoc.v:88$14_Y + connect \$5 $eq$libresoc.v:89$15_Y + connect \$7 $eq$libresoc.v:90$16_Y + connect \update \$7 + connect \shift \$5 + connect \capture \$3 + connect \rst \$1 + connect \local_clk \TAP_bus__tck + connect \negjtag_rst \rst + connect \negjtag_clk \TAP_bus__tck + connect \posjtag_rst \rst + connect \posjtag_clk \TAP_bus__tck +end +attribute \src "libresoc.v:281.1-392.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag._idblock" +attribute \generator "nMigen" +module \_idblock + attribute \src "libresoc.v:365.3-385.6" + wire width 32 $0\TAP_id_sr$next[31:0]$63 + attribute \src "libresoc.v:363.3-364.35" + wire width 32 $0\TAP_id_sr[31:0] + attribute \src "libresoc.v:282.7-282.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:365.3-385.6" + wire width 32 $1\TAP_id_sr$next[31:0]$64 + attribute \src "libresoc.v:318.14-318.31" + wire width 32 $1\TAP_id_sr[31:0] + attribute \src "libresoc.v:365.3-385.6" + wire width 32 $2\TAP_id_sr$next[31:0]$65 + attribute \src "libresoc.v:347.17-347.105" + wire $and$libresoc.v:347$45_Y + attribute \src "libresoc.v:351.18-351.103" + wire $and$libresoc.v:351$49_Y + attribute \src "libresoc.v:353.18-353.105" + wire $and$libresoc.v:353$51_Y + attribute \src "libresoc.v:357.18-357.103" + wire $and$libresoc.v:357$55_Y + attribute \src "libresoc.v:358.18-358.106" + wire $and$libresoc.v:358$56_Y + attribute \src "libresoc.v:362.17-362.101" + wire $and$libresoc.v:362$60_Y + attribute \src "libresoc.v:348.18-348.102" + wire $eq$libresoc.v:348$46_Y + attribute \src "libresoc.v:349.18-349.102" + wire $eq$libresoc.v:349$47_Y + attribute \src "libresoc.v:352.17-352.101" + wire $eq$libresoc.v:352$50_Y + attribute \src "libresoc.v:354.18-354.102" + wire $eq$libresoc.v:354$52_Y + attribute \src "libresoc.v:355.18-355.102" + wire $eq$libresoc.v:355$53_Y + attribute \src "libresoc.v:359.18-359.102" + wire $eq$libresoc.v:359$57_Y + attribute \src "libresoc.v:360.17-360.101" + wire $eq$libresoc.v:360$58_Y + attribute \src "libresoc.v:350.18-350.104" + wire $or$libresoc.v:350$48_Y + attribute \src "libresoc.v:356.18-356.104" + wire $or$libresoc.v:356$54_Y + attribute \src "libresoc.v:361.17-361.101" + wire $or$libresoc.v:361$59_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:369" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 5 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:226" + wire width 32 \TAP_id_sr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:226" + wire width 32 \TAP_id_sr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:215" + wire output 6 \TAP_id_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:233" + wire \_bypass + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:230" + wire \_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:231" + wire \_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:229" + wire \_tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:232" + wire \_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire input 1 \capture + attribute \src "libresoc.v:282.7-282.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire width 4 input 9 \ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire input 2 \isdr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire input 8 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire input 7 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire input 3 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:27" + wire input 4 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + cell $and $and$libresoc.v:347$45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$7 + connect \B \capture + connect \Y $and$libresoc.v:347$45_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $and $and$libresoc.v:351$49 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isdr + connect \B \$15 + connect \Y $and$libresoc.v:351$49_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + cell $and $and$libresoc.v:353$51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$17 + connect \B \shift + connect \Y $and$libresoc.v:353$51_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $and $and$libresoc.v:357$55 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isdr + connect \B \$25 + connect \Y $and$libresoc.v:357$55_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + cell $and $and$libresoc.v:358$56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \B \update + connect \Y $and$libresoc.v:358$56_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $and $and$libresoc.v:362$60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isdr + connect \B \$5 + connect \Y $and$libresoc.v:362$60_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:348$46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ir + connect \B 1'1 + connect \Y $eq$libresoc.v:348$46_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:349$47 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \ir + connect \B 4'1111 + connect \Y $eq$libresoc.v:349$47_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:352$50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ir + connect \B 1'1 + connect \Y $eq$libresoc.v:352$50_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:354$52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ir + connect \B 1'1 + connect \Y $eq$libresoc.v:354$52_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:355$53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \ir + connect \B 4'1111 + connect \Y $eq$libresoc.v:355$53_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:369" + cell $eq $eq$libresoc.v:359$57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \ir + connect \B 4'1111 + connect \Y $eq$libresoc.v:359$57_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:360$58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \ir + connect \B 4'1111 + connect \Y $eq$libresoc.v:360$58_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $or $or$libresoc.v:350$48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$11 + connect \B \$13 + connect \Y $or$libresoc.v:350$48_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $or $or$libresoc.v:356$54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$21 + connect \B \$23 + connect \Y $or$libresoc.v:356$54_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $or $or$libresoc.v:361$59 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $or$libresoc.v:361$59_Y + end + attribute \src "libresoc.v:282.7-282.20" + process $proc$libresoc.v:282$66 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:318.14-318.31" + process $proc$libresoc.v:318$67 + assign { } { } + assign $1\TAP_id_sr[31:0] 0 + sync always + sync init + update \TAP_id_sr $1\TAP_id_sr[31:0] + end + attribute \src "libresoc.v:363.3-364.35" + process $proc$libresoc.v:363$61 + assign { } { } + assign $0\TAP_id_sr[31:0] \TAP_id_sr$next + sync posedge \posjtag_clk + update \TAP_id_sr $0\TAP_id_sr[31:0] + end + attribute \src "libresoc.v:365.3-385.6" + process $proc$libresoc.v:365$62 + assign { } { } + assign { } { } + assign $0\TAP_id_sr$next[31:0]$63 $1\TAP_id_sr$next[31:0]$64 + attribute \src "libresoc.v:366.5-366.29" + switch \initial + attribute \src "libresoc.v:366.9-366.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:244" + switch { \_shift \_capture } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\TAP_id_sr$next[31:0]$64 6399 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\TAP_id_sr$next[31:0]$64 $2\TAP_id_sr$next[31:0]$65 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:247" + switch \_bypass + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\TAP_id_sr$next[31:0]$65 [31:1] \TAP_id_sr [31:1] + assign $2\TAP_id_sr$next[31:0]$65 [0] \_tdi + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\TAP_id_sr$next[31:0]$65 { \_tdi \TAP_id_sr [31:1] } + end + case + assign $1\TAP_id_sr$next[31:0]$64 \TAP_id_sr + end + sync always + update \TAP_id_sr$next $0\TAP_id_sr$next[31:0]$63 + end + connect \$9 $and$libresoc.v:347$45_Y + connect \$11 $eq$libresoc.v:348$46_Y + connect \$13 $eq$libresoc.v:349$47_Y + connect \$15 $or$libresoc.v:350$48_Y + connect \$17 $and$libresoc.v:351$49_Y + connect \$1 $eq$libresoc.v:352$50_Y + connect \$19 $and$libresoc.v:353$51_Y + connect \$21 $eq$libresoc.v:354$52_Y + connect \$23 $eq$libresoc.v:355$53_Y + connect \$25 $or$libresoc.v:356$54_Y + connect \$27 $and$libresoc.v:357$55_Y + connect \$29 $and$libresoc.v:358$56_Y + connect \$31 $eq$libresoc.v:359$57_Y + connect \$3 $eq$libresoc.v:360$58_Y + connect \$5 $or$libresoc.v:361$59_Y + connect \$7 $and$libresoc.v:362$60_Y + connect \TAP_id_tdo \TAP_id_sr [0] + connect \_bypass \$31 + connect \_update \$29 + connect \_shift \$19 + connect \_capture \$9 + connect \_tdi \TAP_bus__tdi +end +attribute \src "libresoc.v:396.1-480.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag._irblock" +attribute \generator "nMigen" +module \_irblock + attribute \src "libresoc.v:397.7-397.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:458.3-478.6" + wire width 4 $0\ir$next[3:0]$80 + attribute \src "libresoc.v:441.3-442.21" + wire width 4 $0\ir[3:0] + attribute \src "libresoc.v:445.3-457.6" + wire width 4 $0\shift_ir$next[3:0]$77 + attribute \src "libresoc.v:443.3-444.33" + wire width 4 $0\shift_ir[3:0] + attribute \src "libresoc.v:458.3-478.6" + wire width 4 $1\ir$next[3:0]$81 + attribute \src "libresoc.v:416.13-416.22" + wire width 4 $1\ir[3:0] + attribute \src "libresoc.v:445.3-457.6" + wire width 4 $1\shift_ir$next[3:0]$78 + attribute \src "libresoc.v:428.13-428.28" + wire width 4 $1\shift_ir[3:0] + attribute \src "libresoc.v:458.3-478.6" + wire width 4 $2\ir$next[3:0]$82 + attribute \src "libresoc.v:435.17-435.103" + wire $and$libresoc.v:435$68_Y + attribute \src "libresoc.v:436.18-436.105" + wire $and$libresoc.v:436$69_Y + attribute \src "libresoc.v:437.17-437.105" + wire $and$libresoc.v:437$70_Y + attribute \src "libresoc.v:438.17-438.103" + wire $and$libresoc.v:438$71_Y + attribute \src "libresoc.v:439.17-439.104" + wire $and$libresoc.v:439$72_Y + attribute \src "libresoc.v:440.17-440.105" + wire $and$libresoc.v:440$73_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:355" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:357" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:356" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:357" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:355" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:356" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 4 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire input 1 \capture + attribute \src "libresoc.v:397.7-397.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire width 4 output 9 \ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire width 4 \ir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire input 5 \isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire input 8 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire input 7 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire input 2 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:139" + wire width 4 \shift_ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:139" + wire width 4 \shift_ir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:129" + wire output 6 \tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:27" + wire input 3 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:356" + cell $and $and$libresoc.v:435$68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \shift + connect \Y $and$libresoc.v:435$68_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:357" + cell $and $and$libresoc.v:436$69 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \update + connect \Y $and$libresoc.v:436$69_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:355" + cell $and $and$libresoc.v:437$70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \capture + connect \Y $and$libresoc.v:437$70_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:356" + cell $and $and$libresoc.v:438$71 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \shift + connect \Y $and$libresoc.v:438$71_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:357" + cell $and $and$libresoc.v:439$72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \update + connect \Y $and$libresoc.v:439$72_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:355" + cell $and $and$libresoc.v:440$73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \capture + connect \Y $and$libresoc.v:440$73_Y + end + attribute \src "libresoc.v:397.7-397.20" + process $proc$libresoc.v:397$83 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:416.13-416.22" + process $proc$libresoc.v:416$84 + assign { } { } + assign $1\ir[3:0] 4'0001 + sync always + sync init + update \ir $1\ir[3:0] + end + attribute \src "libresoc.v:428.13-428.28" + process $proc$libresoc.v:428$85 + assign { } { } + assign $1\shift_ir[3:0] 4'0000 + sync always + sync init + update \shift_ir $1\shift_ir[3:0] + end + attribute \src "libresoc.v:441.3-442.21" + process $proc$libresoc.v:441$74 + assign { } { } + assign $0\ir[3:0] \ir$next + sync posedge \posjtag_clk + update \ir $0\ir[3:0] + end + attribute \src "libresoc.v:443.3-444.33" + process $proc$libresoc.v:443$75 + assign { } { } + assign $0\shift_ir[3:0] \shift_ir$next + sync posedge \posjtag_clk + update \shift_ir $0\shift_ir[3:0] + end + attribute \src "libresoc.v:445.3-457.6" + process $proc$libresoc.v:445$76 + assign { } { } + assign { } { } + assign $0\shift_ir$next[3:0]$77 $1\shift_ir$next[3:0]$78 + attribute \src "libresoc.v:446.5-446.29" + switch \initial + attribute \src "libresoc.v:446.9-446.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:142" + switch { \$5 \$3 \$1 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\shift_ir$next[3:0]$78 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\shift_ir$next[3:0]$78 { \TAP_bus__tdi \shift_ir [3:1] } + case + assign $1\shift_ir$next[3:0]$78 \shift_ir + end + sync always + update \shift_ir$next $0\shift_ir$next[3:0]$77 + end + attribute \src "libresoc.v:458.3-478.6" + process $proc$libresoc.v:458$79 + assign { } { } + assign { } { } + assign { } { } + assign $0\ir$next[3:0]$80 $2\ir$next[3:0]$82 + attribute \src "libresoc.v:459.5-459.29" + switch \initial + attribute \src "libresoc.v:459.9-459.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:142" + switch { \$11 \$9 \$7 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $1\ir$next[3:0]$81 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $1\ir$next[3:0]$81 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\ir$next[3:0]$81 \shift_ir + case + assign $1\ir$next[3:0]$81 \ir + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ir$next[3:0]$82 4'0001 + case + assign $2\ir$next[3:0]$82 $1\ir$next[3:0]$81 + end + sync always + update \ir$next $0\ir$next[3:0]$80 + end + connect \$9 $and$libresoc.v:435$68_Y + connect \$11 $and$libresoc.v:436$69_Y + connect \$1 $and$libresoc.v:437$70_Y + connect \$3 $and$libresoc.v:438$71_Y + connect \$5 $and$libresoc.v:439$72_Y + connect \$7 $and$libresoc.v:440$73_Y + connect \tdo \ir [0] +end +attribute \src "libresoc.v:484.1-671.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.clksel" +attribute \generator "nMigen" +module \clksel + attribute \src "libresoc.v:621.3-640.6" + wire $0\clk1$next[0:0]$115 + attribute \src "libresoc.v:555.3-556.25" + wire $0\clk1[0:0] + attribute \src "libresoc.v:574.3-588.6" + wire $0\clk2$next[0:0]$103 + attribute \src "libresoc.v:561.3-562.25" + wire $0\clk2[0:0] + attribute \src "libresoc.v:606.3-620.6" + wire $0\clk3$next[0:0]$111 + attribute \src "libresoc.v:557.3-558.25" + wire $0\clk3[0:0] + attribute \src "libresoc.v:565.3-573.6" + wire $0\clk4$next[0:0]$100 + attribute \src "libresoc.v:563.3-564.25" + wire $0\clk4[0:0] + attribute \src "libresoc.v:641.3-663.6" + wire $0\core_clk_o[0:0] + attribute \src "libresoc.v:589.3-605.6" + wire width 2 $0\counter3$next[1:0]$107 + attribute \src "libresoc.v:559.3-560.33" + wire width 2 $0\counter3[1:0] + attribute \src "libresoc.v:485.7-485.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:621.3-640.6" + wire $1\clk1$next[0:0]$116 + attribute \src "libresoc.v:507.7-507.18" + wire $1\clk1[0:0] + attribute \src "libresoc.v:574.3-588.6" + wire $1\clk2$next[0:0]$104 + attribute \src "libresoc.v:511.7-511.18" + wire $1\clk2[0:0] + attribute \src "libresoc.v:606.3-620.6" + wire $1\clk3$next[0:0]$112 + attribute \src "libresoc.v:515.7-515.18" + wire $1\clk3[0:0] + attribute \src "libresoc.v:565.3-573.6" + wire $1\clk4$next[0:0]$101 + attribute \src "libresoc.v:519.7-519.18" + wire $1\clk4[0:0] + attribute \src "libresoc.v:641.3-663.6" + wire $1\core_clk_o[0:0] + attribute \src "libresoc.v:589.3-605.6" + wire width 2 $1\counter3$next[1:0]$108 + attribute \src "libresoc.v:536.13-536.28" + wire width 2 $1\counter3[1:0] + attribute \src "libresoc.v:621.3-640.6" + wire $2\clk1$next[0:0]$117 + attribute \src "libresoc.v:574.3-588.6" + wire $2\clk2$next[0:0]$105 + attribute \src "libresoc.v:606.3-620.6" + wire $2\clk3$next[0:0]$113 + attribute \src "libresoc.v:589.3-605.6" + wire width 2 $2\counter3$next[1:0]$109 + attribute \src "libresoc.v:621.3-640.6" + wire $3\clk1$next[0:0]$118 + attribute \src "libresoc.v:554.17-554.101" + wire width 3 $add$libresoc.v:554$93_Y + attribute \src "libresoc.v:547.18-547.103" + wire $eq$libresoc.v:547$86_Y + attribute \src "libresoc.v:549.18-549.103" + wire $eq$libresoc.v:549$88_Y + attribute \src "libresoc.v:553.17-553.102" + wire $eq$libresoc.v:553$92_Y + attribute \src "libresoc.v:548.18-548.93" + wire $not$libresoc.v:548$87_Y + attribute \src "libresoc.v:550.18-550.93" + wire $not$libresoc.v:550$89_Y + attribute \src "libresoc.v:551.17-551.92" + wire $not$libresoc.v:551$90_Y + attribute \src "libresoc.v:552.17-552.92" + wire $not$libresoc.v:552$91_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:55" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" + wire \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:60" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:62" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:57" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:64" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:64" + wire width 3 \$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" + wire \clk0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" + wire \clk1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" + wire \clk1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" + wire \clk2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" + wire \clk2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" + wire \clk3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" + wire \clk3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" + wire \clk4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" + wire \clk4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" + wire \clk5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" + wire \clk6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:46" + wire \clk7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:34" + wire input 2 \clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:36" + wire width 3 input 4 \clk_sel_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:37" + wire output 6 \core_clk_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:47" + wire width 2 \counter3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:47" + wire width 2 \counter3$next + attribute \src "libresoc.v:485.7-485.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:35" + wire output 5 \pll_48_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + wire input 1 \pllclk_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + wire \pllclk_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:38" + wire input 3 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:64" + cell $add $add$libresoc.v:554$93 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \counter3 + connect \B 1'1 + connect \Y $add$libresoc.v:554$93_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" + cell $eq $eq$libresoc.v:547$86 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \counter3 + connect \B 2'10 + connect \Y $eq$libresoc.v:547$86_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" + cell $eq $eq$libresoc.v:549$88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \counter3 + connect \B 2'10 + connect \Y $eq$libresoc.v:549$88_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" + cell $eq $eq$libresoc.v:553$92 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \counter3 + connect \B 2'10 + connect \Y $eq$libresoc.v:553$92_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:60" + cell $not $not$libresoc.v:548$87 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clk3 + connect \Y $not$libresoc.v:548$87_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:62" + cell $not $not$libresoc.v:550$89 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clk1 + connect \Y $not$libresoc.v:550$89_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:55" + cell $not $not$libresoc.v:551$90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clk4 + connect \Y $not$libresoc.v:551$90_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:57" + cell $not $not$libresoc.v:552$91 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clk2 + connect \Y $not$libresoc.v:552$91_Y + end + attribute \src "libresoc.v:485.7-485.20" + process $proc$libresoc.v:485$120 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:507.7-507.18" + process $proc$libresoc.v:507$121 + assign { } { } + assign $1\clk1[0:0] 1'0 + sync always + sync init + update \clk1 $1\clk1[0:0] + end + attribute \src "libresoc.v:511.7-511.18" + process $proc$libresoc.v:511$122 + assign { } { } + assign $1\clk2[0:0] 1'0 + sync always + sync init + update \clk2 $1\clk2[0:0] + end + attribute \src "libresoc.v:515.7-515.18" + process $proc$libresoc.v:515$123 + assign { } { } + assign $1\clk3[0:0] 1'0 + sync always + sync init + update \clk3 $1\clk3[0:0] + end + attribute \src "libresoc.v:519.7-519.18" + process $proc$libresoc.v:519$124 + assign { } { } + assign $1\clk4[0:0] 1'0 + sync always + sync init + update \clk4 $1\clk4[0:0] + end + attribute \src "libresoc.v:536.13-536.28" + process $proc$libresoc.v:536$125 + assign { } { } + assign $1\counter3[1:0] 2'00 + sync always + sync init + update \counter3 $1\counter3[1:0] + end + attribute \src "libresoc.v:555.3-556.25" + process $proc$libresoc.v:555$94 + assign { } { } + assign $0\clk1[0:0] \clk1$next + sync posedge \pllclk_clk + update \clk1 $0\clk1[0:0] + end + attribute \src "libresoc.v:557.3-558.25" + process $proc$libresoc.v:557$95 + assign { } { } + assign $0\clk3[0:0] \clk3$next + sync posedge \pllclk_clk + update \clk3 $0\clk3[0:0] + end + attribute \src "libresoc.v:559.3-560.33" + process $proc$libresoc.v:559$96 + assign { } { } + assign $0\counter3[1:0] \counter3$next + sync posedge \pllclk_clk + update \counter3 $0\counter3[1:0] + end + attribute \src "libresoc.v:561.3-562.25" + process $proc$libresoc.v:561$97 + assign { } { } + assign $0\clk2[0:0] \clk2$next + sync posedge \pllclk_clk + update \clk2 $0\clk2[0:0] + end + attribute \src "libresoc.v:563.3-564.25" + process $proc$libresoc.v:563$98 + assign { } { } + assign $0\clk4[0:0] \clk4$next + sync posedge \pllclk_clk + update \clk4 $0\clk4[0:0] + end + attribute \src "libresoc.v:565.3-573.6" + process $proc$libresoc.v:565$99 + assign { } { } + assign { } { } + assign $0\clk4$next[0:0]$100 $1\clk4$next[0:0]$101 + attribute \src "libresoc.v:566.5-566.29" + switch \initial + attribute \src "libresoc.v:566.9-566.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \pllclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\clk4$next[0:0]$101 1'0 + case + assign $1\clk4$next[0:0]$101 \$1 + end + sync always + update \clk4$next $0\clk4$next[0:0]$100 + end + attribute \src "libresoc.v:574.3-588.6" + process $proc$libresoc.v:574$102 + assign { } { } + assign { } { } + assign { } { } + assign $0\clk2$next[0:0]$103 $2\clk2$next[0:0]$105 + attribute \src "libresoc.v:575.5-575.29" + switch \initial + attribute \src "libresoc.v:575.9-575.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:56" + switch \clk4 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\clk2$next[0:0]$104 \$3 + case + assign $1\clk2$next[0:0]$104 \clk2 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \pllclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\clk2$next[0:0]$105 1'0 + case + assign $2\clk2$next[0:0]$105 $1\clk2$next[0:0]$104 + end + sync always + update \clk2$next $0\clk2$next[0:0]$103 + end + attribute \src "libresoc.v:589.3-605.6" + process $proc$libresoc.v:589$106 + assign { } { } + assign { } { } + assign $0\counter3$next[1:0]$107 $2\counter3$next[1:0]$109 + attribute \src "libresoc.v:590.5-590.29" + switch \initial + attribute \src "libresoc.v:590.9-590.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\counter3$next[1:0]$108 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\counter3$next[1:0]$108 \$7 [1:0] + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \pllclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\counter3$next[1:0]$109 2'00 + case + assign $2\counter3$next[1:0]$109 $1\counter3$next[1:0]$108 + end + sync always + update \counter3$next $0\counter3$next[1:0]$107 + end + attribute \src "libresoc.v:606.3-620.6" + process $proc$libresoc.v:606$110 + assign { } { } + assign { } { } + assign { } { } + assign $0\clk3$next[0:0]$111 $2\clk3$next[0:0]$113 + attribute \src "libresoc.v:607.5-607.29" + switch \initial + attribute \src "libresoc.v:607.9-607.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" + switch \$10 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\clk3$next[0:0]$112 \$12 + case + assign $1\clk3$next[0:0]$112 \clk3 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \pllclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\clk3$next[0:0]$113 1'0 + case + assign $2\clk3$next[0:0]$113 $1\clk3$next[0:0]$112 + end + sync always + update \clk3$next $0\clk3$next[0:0]$111 + end + attribute \src "libresoc.v:621.3-640.6" + process $proc$libresoc.v:621$114 + assign { } { } + assign { } { } + assign { } { } + assign $0\clk1$next[0:0]$115 $3\clk1$next[0:0]$118 + attribute \src "libresoc.v:622.5-622.29" + switch \initial + attribute \src "libresoc.v:622.9-622.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" + switch \$14 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\clk1$next[0:0]$116 $2\clk1$next[0:0]$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:61" + switch \clk3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\clk1$next[0:0]$117 \$16 + case + assign $2\clk1$next[0:0]$117 \clk1 + end + case + assign $1\clk1$next[0:0]$116 \clk1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \pllclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\clk1$next[0:0]$118 1'0 + case + assign $3\clk1$next[0:0]$118 $1\clk1$next[0:0]$116 + end + sync always + update \clk1$next $0\clk1$next[0:0]$115 + end + attribute \src "libresoc.v:641.3-663.6" + process $proc$libresoc.v:641$119 + assign { } { } + assign { } { } + assign $0\core_clk_o[0:0] $1\core_clk_o[0:0] + attribute \src "libresoc.v:642.5-642.29" + switch \initial + attribute \src "libresoc.v:642.9-642.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:67" + switch \clk_sel_i + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\core_clk_o[0:0] \clk0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\core_clk_o[0:0] \clk1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\core_clk_o[0:0] \clk2 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\core_clk_o[0:0] \clk3 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\core_clk_o[0:0] \clk4 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\core_clk_o[0:0] \clk5 + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\core_clk_o[0:0] \clk6 + attribute \src "libresoc.v:0.0-0.0" + case 3'--- + assign { } { } + assign $1\core_clk_o[0:0] \clk7 + case + assign $1\core_clk_o[0:0] 1'0 + end + sync always + update \core_clk_o $0\core_clk_o[0:0] + end + connect \$10 $eq$libresoc.v:547$86_Y + connect \$12 $not$libresoc.v:548$87_Y + connect \$14 $eq$libresoc.v:549$88_Y + connect \$16 $not$libresoc.v:550$89_Y + connect \$1 $not$libresoc.v:551$90_Y + connect \$3 $not$libresoc.v:552$91_Y + connect \$5 $eq$libresoc.v:553$92_Y + connect \$8 $add$libresoc.v:554$93_Y + connect \$7 \$8 + connect \clk5 1'0 + connect \pll_48_o \clk1 + connect \clk7 1'1 + connect \clk6 1'0 + connect \clk0 \clk_24_i + connect \pllclk_rst \rst +end +attribute \src "libresoc.v:675.1-1389.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dbg" +attribute \generator "nMigen" +module \dbg + attribute \src "libresoc.v:1205.3-1214.6" + wire $0\d_cr_req[0:0] + attribute \src "libresoc.v:1012.3-1021.6" + wire $0\d_gpr_req[0:0] + attribute \src "libresoc.v:1215.3-1224.6" + wire $0\d_xer_req[0:0] + attribute \src "libresoc.v:994.3-1011.6" + wire $0\dmi_ack_o[0:0] + attribute \src "libresoc.v:1225.3-1255.6" + wire width 64 $0\dmi_dout[63:0] + attribute \src "libresoc.v:1196.3-1204.6" + wire $0\dmi_read_log_data$next[0:0]$239 + attribute \src "libresoc.v:972.3-973.51" + wire $0\dmi_read_log_data[0:0] + attribute \src "libresoc.v:1187.3-1195.6" + wire $0\dmi_read_log_data_1$next[0:0]$236 + attribute \src "libresoc.v:974.3-975.55" + wire $0\dmi_read_log_data_1[0:0] + attribute \src "libresoc.v:1022.3-1030.6" + wire $0\dmi_req_i_1$next[0:0]$202 + attribute \src "libresoc.v:984.3-985.39" + wire $0\dmi_req_i_1[0:0] + attribute \src "libresoc.v:1346.3-1379.6" + wire $0\do_dmi_log_rd$next[0:0]$266 + attribute \src "libresoc.v:986.3-987.43" + wire $0\do_dmi_log_rd[0:0] + attribute \src "libresoc.v:1316.3-1345.6" + wire $0\do_icreset$next[0:0]$259 + attribute \src "libresoc.v:988.3-989.37" + wire $0\do_icreset[0:0] + attribute \src "libresoc.v:1286.3-1315.6" + wire $0\do_reset$next[0:0]$252 + attribute \src "libresoc.v:990.3-991.33" + wire $0\do_reset[0:0] + attribute \src "libresoc.v:1256.3-1285.6" + wire $0\do_step$next[0:0]$245 + attribute \src "libresoc.v:992.3-993.31" + wire $0\do_step[0:0] + attribute \src "libresoc.v:1125.3-1152.6" + wire width 7 $0\gspr_index$next[6:0]$224 + attribute \src "libresoc.v:978.3-979.37" + wire width 7 $0\gspr_index[6:0] + attribute \src "libresoc.v:676.7-676.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:1153.3-1186.6" + wire width 32 $0\log_dmi_addr$next[31:0]$230 + attribute \src "libresoc.v:976.3-977.41" + wire width 32 $0\log_dmi_addr[31:0] + attribute \src "libresoc.v:1081.3-1124.6" + wire $0\stopping$next[0:0]$215 + attribute \src "libresoc.v:980.3-981.33" + wire $0\stopping[0:0] + attribute \src "libresoc.v:1031.3-1080.6" + wire $0\terminated$next[0:0]$205 + attribute \src "libresoc.v:982.3-983.37" + wire $0\terminated[0:0] + attribute \src "libresoc.v:1205.3-1214.6" + wire $1\d_cr_req[0:0] + attribute \src "libresoc.v:1012.3-1021.6" + wire $1\d_gpr_req[0:0] + attribute \src "libresoc.v:1215.3-1224.6" + wire $1\d_xer_req[0:0] + attribute \src "libresoc.v:994.3-1011.6" + wire $1\dmi_ack_o[0:0] + attribute \src "libresoc.v:1225.3-1255.6" + wire width 64 $1\dmi_dout[63:0] + attribute \src "libresoc.v:1196.3-1204.6" + wire $1\dmi_read_log_data$next[0:0]$240 + attribute \src "libresoc.v:847.7-847.31" + wire $1\dmi_read_log_data[0:0] + attribute \src "libresoc.v:1187.3-1195.6" + wire $1\dmi_read_log_data_1$next[0:0]$237 + attribute \src "libresoc.v:851.7-851.33" + wire $1\dmi_read_log_data_1[0:0] + attribute \src "libresoc.v:1022.3-1030.6" + wire $1\dmi_req_i_1$next[0:0]$203 + attribute \src "libresoc.v:857.7-857.25" + wire $1\dmi_req_i_1[0:0] + attribute \src "libresoc.v:1346.3-1379.6" + wire $1\do_dmi_log_rd$next[0:0]$267 + attribute \src "libresoc.v:863.7-863.27" + wire $1\do_dmi_log_rd[0:0] + attribute \src "libresoc.v:1316.3-1345.6" + wire $1\do_icreset$next[0:0]$260 + attribute \src "libresoc.v:867.7-867.24" + wire $1\do_icreset[0:0] + attribute \src "libresoc.v:1286.3-1315.6" + wire $1\do_reset$next[0:0]$253 + attribute \src "libresoc.v:871.7-871.22" + wire $1\do_reset[0:0] + attribute \src "libresoc.v:1256.3-1285.6" + wire $1\do_step$next[0:0]$246 + attribute \src "libresoc.v:875.7-875.21" + wire $1\do_step[0:0] + attribute \src "libresoc.v:1125.3-1152.6" + wire width 7 $1\gspr_index$next[6:0]$225 + attribute \src "libresoc.v:879.13-879.31" + wire width 7 $1\gspr_index[6:0] + attribute \src "libresoc.v:1153.3-1186.6" + wire width 32 $1\log_dmi_addr$next[31:0]$231 + attribute \src "libresoc.v:889.14-889.34" + wire width 32 $1\log_dmi_addr[31:0] + attribute \src "libresoc.v:1081.3-1124.6" + wire $1\stopping$next[0:0]$216 + attribute \src "libresoc.v:899.7-899.22" + wire $1\stopping[0:0] + attribute \src "libresoc.v:1031.3-1080.6" + wire $1\terminated$next[0:0]$206 + attribute \src "libresoc.v:905.7-905.24" + wire $1\terminated[0:0] + attribute \src "libresoc.v:1346.3-1379.6" + wire $2\do_dmi_log_rd$next[0:0]$268 + attribute \src "libresoc.v:1316.3-1345.6" + wire $2\do_icreset$next[0:0]$261 + attribute \src "libresoc.v:1286.3-1315.6" + wire $2\do_reset$next[0:0]$254 + attribute \src "libresoc.v:1256.3-1285.6" + wire $2\do_step$next[0:0]$247 + attribute \src "libresoc.v:1125.3-1152.6" + wire width 7 $2\gspr_index$next[6:0]$226 + attribute \src "libresoc.v:1153.3-1186.6" + wire width 32 $2\log_dmi_addr$next[31:0]$232 + attribute \src "libresoc.v:1081.3-1124.6" + wire $2\stopping$next[0:0]$217 + attribute \src "libresoc.v:1031.3-1080.6" + wire $2\terminated$next[0:0]$207 + attribute \src "libresoc.v:1346.3-1379.6" + wire $3\do_dmi_log_rd$next[0:0]$269 + attribute \src "libresoc.v:1316.3-1345.6" + wire $3\do_icreset$next[0:0]$262 + attribute \src "libresoc.v:1286.3-1315.6" + wire $3\do_reset$next[0:0]$255 + attribute \src "libresoc.v:1256.3-1285.6" + wire $3\do_step$next[0:0]$248 + attribute \src "libresoc.v:1125.3-1152.6" + wire width 7 $3\gspr_index$next[6:0]$227 + attribute \src "libresoc.v:1153.3-1186.6" + wire width 32 $3\log_dmi_addr$next[31:0]$233 + attribute \src "libresoc.v:1081.3-1124.6" + wire $3\stopping$next[0:0]$218 + attribute \src "libresoc.v:1031.3-1080.6" + wire $3\terminated$next[0:0]$208 + attribute \src "libresoc.v:1346.3-1379.6" + wire $4\do_dmi_log_rd$next[0:0]$270 + attribute \src "libresoc.v:1316.3-1345.6" + wire $4\do_icreset$next[0:0]$263 + attribute \src "libresoc.v:1286.3-1315.6" + wire $4\do_reset$next[0:0]$256 + attribute \src "libresoc.v:1256.3-1285.6" + wire $4\do_step$next[0:0]$249 + attribute \src "libresoc.v:1125.3-1152.6" + wire width 7 $4\gspr_index$next[6:0]$228 + attribute \src "libresoc.v:1153.3-1186.6" + wire width 32 $4\log_dmi_addr$next[31:0]$234 + attribute \src "libresoc.v:1081.3-1124.6" + wire $4\stopping$next[0:0]$219 + attribute \src "libresoc.v:1031.3-1080.6" + wire $4\terminated$next[0:0]$209 + attribute \src "libresoc.v:1316.3-1345.6" + wire $5\do_icreset$next[0:0]$264 + attribute \src "libresoc.v:1286.3-1315.6" + wire $5\do_reset$next[0:0]$257 + attribute \src "libresoc.v:1256.3-1285.6" + wire $5\do_step$next[0:0]$250 + attribute \src "libresoc.v:1081.3-1124.6" + wire $5\stopping$next[0:0]$220 + attribute \src "libresoc.v:1031.3-1080.6" + wire $5\terminated$next[0:0]$210 + attribute \src "libresoc.v:1081.3-1124.6" + wire $6\stopping$next[0:0]$221 + attribute \src "libresoc.v:1031.3-1080.6" + wire $6\terminated$next[0:0]$211 + attribute \src "libresoc.v:1081.3-1124.6" + wire $7\stopping$next[0:0]$222 + attribute \src "libresoc.v:1031.3-1080.6" + wire $7\terminated$next[0:0]$212 + attribute \src "libresoc.v:1031.3-1080.6" + wire $8\terminated$next[0:0]$213 + attribute \src "libresoc.v:919.19-919.110" + wire width 3 $add$libresoc.v:919$135_Y + attribute \src "libresoc.v:910.17-910.109" + wire $and$libresoc.v:910$126_Y + attribute \src "libresoc.v:913.19-913.103" + wire $and$libresoc.v:913$129_Y + attribute \src "libresoc.v:915.19-915.113" + wire $and$libresoc.v:915$131_Y + attribute \src "libresoc.v:922.19-922.103" + wire $and$libresoc.v:922$138_Y + attribute \src "libresoc.v:924.19-924.102" + wire $and$libresoc.v:924$140_Y + attribute \src "libresoc.v:929.18-929.101" + wire $and$libresoc.v:929$145_Y + attribute \src "libresoc.v:931.18-931.111" + wire $and$libresoc.v:931$147_Y + attribute \src "libresoc.v:936.18-936.101" + wire $and$libresoc.v:936$152_Y + attribute \src "libresoc.v:938.18-938.111" + wire $and$libresoc.v:938$154_Y + attribute \src "libresoc.v:944.18-944.101" + wire $and$libresoc.v:944$160_Y + attribute \src "libresoc.v:946.18-946.111" + wire $and$libresoc.v:946$162_Y + attribute \src "libresoc.v:950.17-950.99" + wire $and$libresoc.v:950$166_Y + attribute \src "libresoc.v:952.18-952.101" + wire $and$libresoc.v:952$168_Y + attribute \src "libresoc.v:954.18-954.111" + wire $and$libresoc.v:954$170_Y + attribute \src "libresoc.v:959.18-959.101" + wire $and$libresoc.v:959$175_Y + attribute \src "libresoc.v:962.18-962.111" + wire $and$libresoc.v:962$178_Y + attribute \src "libresoc.v:967.18-967.101" + wire $and$libresoc.v:967$183_Y + attribute \src "libresoc.v:969.18-969.111" + wire $and$libresoc.v:969$185_Y + attribute \src "libresoc.v:911.18-911.103" + wire $eq$libresoc.v:911$127_Y + attribute \src "libresoc.v:916.19-916.104" + wire $eq$libresoc.v:916$132_Y + attribute \src "libresoc.v:917.19-917.104" + wire $eq$libresoc.v:917$133_Y + attribute \src "libresoc.v:918.19-918.104" + wire $eq$libresoc.v:918$134_Y + attribute \src "libresoc.v:920.19-920.104" + wire $eq$libresoc.v:920$136_Y + attribute \src "libresoc.v:921.18-921.103" + wire $eq$libresoc.v:921$137_Y + attribute \src "libresoc.v:925.18-925.103" + wire $eq$libresoc.v:925$141_Y + attribute \src "libresoc.v:926.18-926.103" + wire $eq$libresoc.v:926$142_Y + attribute \src "libresoc.v:932.18-932.103" + wire $eq$libresoc.v:932$148_Y + attribute \src "libresoc.v:933.18-933.103" + wire $eq$libresoc.v:933$149_Y + attribute \src "libresoc.v:934.18-934.103" + wire $eq$libresoc.v:934$150_Y + attribute \src "libresoc.v:940.18-940.103" + wire $eq$libresoc.v:940$156_Y + attribute \src "libresoc.v:941.18-941.103" + wire $eq$libresoc.v:941$157_Y + attribute \src "libresoc.v:942.18-942.103" + wire $eq$libresoc.v:942$158_Y + attribute \src "libresoc.v:947.18-947.103" + wire $eq$libresoc.v:947$163_Y + attribute \src "libresoc.v:948.18-948.103" + wire $eq$libresoc.v:948$164_Y + attribute \src "libresoc.v:949.18-949.103" + wire $eq$libresoc.v:949$165_Y + attribute \src "libresoc.v:955.18-955.103" + wire $eq$libresoc.v:955$171_Y + attribute \src "libresoc.v:956.18-956.103" + wire $eq$libresoc.v:956$172_Y + attribute \src "libresoc.v:957.18-957.103" + wire $eq$libresoc.v:957$173_Y + attribute \src "libresoc.v:963.18-963.103" + wire $eq$libresoc.v:963$179_Y + attribute \src "libresoc.v:964.18-964.103" + wire $eq$libresoc.v:964$180_Y + attribute \src "libresoc.v:965.18-965.103" + wire $eq$libresoc.v:965$181_Y + attribute \src "libresoc.v:970.18-970.103" + wire $eq$libresoc.v:970$186_Y + attribute \src "libresoc.v:971.18-971.103" + wire $eq$libresoc.v:971$187_Y + attribute \src "libresoc.v:912.19-912.99" + wire $not$libresoc.v:912$128_Y + attribute \src "libresoc.v:914.19-914.105" + wire $not$libresoc.v:914$130_Y + attribute \src "libresoc.v:923.19-923.95" + wire $not$libresoc.v:923$139_Y + attribute \src "libresoc.v:927.18-927.98" + wire $not$libresoc.v:927$143_Y + attribute \src "libresoc.v:930.18-930.104" + wire $not$libresoc.v:930$146_Y + attribute \src "libresoc.v:935.18-935.98" + wire $not$libresoc.v:935$151_Y + attribute \src "libresoc.v:937.18-937.104" + wire $not$libresoc.v:937$153_Y + attribute \src "libresoc.v:939.17-939.97" + wire $not$libresoc.v:939$155_Y + attribute \src "libresoc.v:943.18-943.98" + wire $not$libresoc.v:943$159_Y + attribute \src "libresoc.v:945.18-945.104" + wire $not$libresoc.v:945$161_Y + attribute \src "libresoc.v:951.18-951.98" + wire $not$libresoc.v:951$167_Y + attribute \src "libresoc.v:953.18-953.104" + wire $not$libresoc.v:953$169_Y + attribute \src "libresoc.v:958.18-958.98" + wire $not$libresoc.v:958$174_Y + attribute \src "libresoc.v:960.18-960.104" + wire $not$libresoc.v:960$176_Y + attribute \src "libresoc.v:961.17-961.103" + wire $not$libresoc.v:961$177_Y + attribute \src "libresoc.v:966.18-966.98" + wire $not$libresoc.v:966$182_Y + attribute \src "libresoc.v:968.18-968.104" + wire $not$libresoc.v:968$184_Y + attribute \src "libresoc.v:928.17-928.126" + wire width 64 $pos$libresoc.v:928$144_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + wire width 3 \$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + wire width 3 \$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" + wire \$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" + wire \$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" + wire \$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" + wire \$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 input 10 \core_dbg_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 input 9 \core_dbg_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" + wire output 7 \core_rst_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:97" + wire output 11 \core_stop_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" + wire input 12 \core_stopped_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire input 19 \d_cr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 input 18 \d_cr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire output 17 \d_cr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire input 16 \d_gpr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" + wire width 7 output 14 \d_gpr_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 input 15 \d_gpr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire output 13 \d_gpr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire input 22 \d_xer_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 input 21 \d_xer_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire output 20 \d_xer_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire output 4 \dmi_ack_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 input 24 \dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 input 3 \dmi_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 output 5 \dmi_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" + wire \dmi_read_log_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" + wire \dmi_read_log_data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" + wire \dmi_read_log_data_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" + wire \dmi_read_log_data_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire input 1 \dmi_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" + wire \dmi_req_i_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" + wire \dmi_req_i_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire input 2 \dmi_we_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" + wire \do_dmi_log_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" + wire \do_dmi_log_rd$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" + wire \do_icreset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" + wire \do_icreset$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" + wire \do_reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" + wire \do_reset$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" + wire \do_step + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" + wire \do_step$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143" + wire width 7 \gspr_index + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143" + wire width 7 \gspr_index$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" + wire \icache_rst_o + attribute \src "libresoc.v:676.7-676.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" + wire input 6 \intclk_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" + wire input 23 \intclk_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145" + wire width 32 \log_dmi_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145" + wire width 32 \log_dmi_addr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" + wire width 64 \log_dmi_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:119" + wire width 32 \log_write_addr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:134" + wire width 64 \stat_reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" + wire \stopping + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" + wire \stopping$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102" + wire input 8 \terminate_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" + wire \terminated + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" + wire \terminated$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:122" + wire \terminated_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $add $add$libresoc.v:919$135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \log_dmi_addr [1:0] + connect \B 1'1 + connect \Y $add$libresoc.v:919$135_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:910$126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$7 + connect \Y $and$libresoc.v:910$126_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:913$129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$101 + connect \Y $and$libresoc.v:913$129_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:915$131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$105 + connect \Y $and$libresoc.v:915$131_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" + cell $and $and$libresoc.v:922$138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$118 + connect \Y $and$libresoc.v:922$138_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" + cell $and $and$libresoc.v:924$140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \stopping + connect \B \$122 + connect \Y $and$libresoc.v:924$140_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:929$145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$17 + connect \Y $and$libresoc.v:929$145_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:931$147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$21 + connect \Y $and$libresoc.v:931$147_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:936$152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$31 + connect \Y $and$libresoc.v:936$152_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:938$154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$35 + connect \Y $and$libresoc.v:938$154_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:944$160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$45 + connect \Y $and$libresoc.v:944$160_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:946$162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$49 + connect \Y $and$libresoc.v:946$162_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:950$166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$3 + connect \Y $and$libresoc.v:950$166_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:952$168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$59 + connect \Y $and$libresoc.v:952$168_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:954$170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$63 + connect \Y $and$libresoc.v:954$170_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:959$175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$73 + connect \Y $and$libresoc.v:959$175_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:962$178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$77 + connect \Y $and$libresoc.v:962$178_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:967$183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$87 + connect \Y $and$libresoc.v:967$183_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:969$185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$91 + connect \Y $and$libresoc.v:969$185_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:911$127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:911$127_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:916$132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:916$132_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:917$133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:917$133_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:918$134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:918$134_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" + cell $eq $eq$libresoc.v:920$136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'111 + connect \Y $eq$libresoc.v:920$136_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:921$137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:921$137_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:925$141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:925$141_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:926$142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:926$142_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:932$148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:932$148_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:933$149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:933$149_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:934$150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:934$150_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:940$156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:940$156_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:941$157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:941$157_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:942$158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:942$158_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:947$163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:947$163_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:948$164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:948$164_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:949$165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:949$165_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:955$171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:955$171_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:956$172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:956$172_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:957$173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:957$173_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:963$179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:963$179_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:964$180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:964$180_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:965$181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:965$181_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:970$186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:970$186_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:971$187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:971$187_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:912$128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:912$128_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:914$130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:914$130_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" + cell $not $not$libresoc.v:923$139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \do_step + connect \Y $not$libresoc.v:923$139_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:927$143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:927$143_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:930$146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:930$146_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:935$151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:935$151_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:937$153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:937$153_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:939$155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:939$155_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:943$159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:943$159_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:945$161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:945$161_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:951$167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:951$167_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:953$169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:953$169_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:958$174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:958$174_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:960$176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:960$176_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:961$177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:961$177_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:966$182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:966$182_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:968$184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:968$184_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170" + cell $pos $pos$libresoc.v:928$144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } + connect \Y $pos$libresoc.v:928$144_Y + end + attribute \src "libresoc.v:1012.3-1021.6" + process $proc$libresoc.v:1012$200 + assign { } { } + assign { } { } + assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] + attribute \src "libresoc.v:1013.5-1013.29" + switch \initial + attribute \src "libresoc.v:1013.9-1013.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\d_gpr_req[0:0] \dmi_req_i + case + assign $1\d_gpr_req[0:0] 1'0 + end + sync always + update \d_gpr_req $0\d_gpr_req[0:0] + end + attribute \src "libresoc.v:1022.3-1030.6" + process $proc$libresoc.v:1022$201 + assign { } { } + assign { } { } + assign $0\dmi_req_i_1$next[0:0]$202 $1\dmi_req_i_1$next[0:0]$203 + attribute \src "libresoc.v:1023.5-1023.29" + switch \initial + attribute \src "libresoc.v:1023.9-1023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_req_i_1$next[0:0]$203 1'0 + case + assign $1\dmi_req_i_1$next[0:0]$203 \dmi_req_i + end + sync always + update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$202 + end + attribute \src "libresoc.v:1031.3-1080.6" + process $proc$libresoc.v:1031$204 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\terminated$next[0:0]$205 $8\terminated$next[0:0]$213 + attribute \src "libresoc.v:1032.5-1032.29" + switch \initial + attribute \src "libresoc.v:1032.9-1032.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$65 \$61 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\terminated$next[0:0]$206 $2\terminated$next[0:0]$207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\terminated$next[0:0]$207 $3\terminated$next[0:0]$208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$71 \$69 \$67 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign { } { } + assign { } { } + assign $3\terminated$next[0:0]$208 $6\terminated$next[0:0]$211 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" + switch \dmi_din [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\terminated$next[0:0]$209 1'0 + case + assign $4\terminated$next[0:0]$209 \terminated + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" + switch \dmi_din [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\terminated$next[0:0]$210 1'0 + case + assign $5\terminated$next[0:0]$210 $4\terminated$next[0:0]$209 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" + switch \dmi_din [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\terminated$next[0:0]$211 1'0 + case + assign $6\terminated$next[0:0]$211 $5\terminated$next[0:0]$210 + end + case + assign $3\terminated$next[0:0]$208 \terminated + end + case + assign $2\terminated$next[0:0]$207 \terminated + end + case + assign $1\terminated$next[0:0]$206 \terminated + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" + switch \terminate_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\terminated$next[0:0]$212 1'1 + case + assign $7\terminated$next[0:0]$212 $1\terminated$next[0:0]$206 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\terminated$next[0:0]$213 1'0 + case + assign $8\terminated$next[0:0]$213 $7\terminated$next[0:0]$212 + end + sync always + update \terminated$next $0\terminated$next[0:0]$205 + end + attribute \src "libresoc.v:1081.3-1124.6" + process $proc$libresoc.v:1081$214 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\stopping$next[0:0]$215 $7\stopping$next[0:0]$222 + attribute \src "libresoc.v:1082.5-1082.29" + switch \initial + attribute \src "libresoc.v:1082.9-1082.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$79 \$75 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\stopping$next[0:0]$216 $2\stopping$next[0:0]$217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\stopping$next[0:0]$217 $3\stopping$next[0:0]$218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$85 \$83 \$81 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign { } { } + assign $3\stopping$next[0:0]$218 $5\stopping$next[0:0]$220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" + switch \dmi_din [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\stopping$next[0:0]$219 1'1 + case + assign $4\stopping$next[0:0]$219 \stopping + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" + switch \dmi_din [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\stopping$next[0:0]$220 1'0 + case + assign $5\stopping$next[0:0]$220 $4\stopping$next[0:0]$219 + end + case + assign $3\stopping$next[0:0]$218 \stopping + end + case + assign $2\stopping$next[0:0]$217 \stopping + end + case + assign $1\stopping$next[0:0]$216 \stopping + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" + switch \terminate_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\stopping$next[0:0]$221 1'1 + case + assign $6\stopping$next[0:0]$221 $1\stopping$next[0:0]$216 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\stopping$next[0:0]$222 1'0 + case + assign $7\stopping$next[0:0]$222 $6\stopping$next[0:0]$221 + end + sync always + update \stopping$next $0\stopping$next[0:0]$215 + end + attribute \src "libresoc.v:1125.3-1152.6" + process $proc$libresoc.v:1125$223 + assign { } { } + assign { } { } + assign { } { } + assign $0\gspr_index$next[6:0]$224 $4\gspr_index$next[6:0]$228 + attribute \src "libresoc.v:1126.5-1126.29" + switch \initial + attribute \src "libresoc.v:1126.9-1126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$93 \$89 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\gspr_index$next[6:0]$225 $2\gspr_index$next[6:0]$226 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\gspr_index$next[6:0]$226 $3\gspr_index$next[6:0]$227 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$99 \$97 \$95 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\gspr_index$next[6:0]$227 \gspr_index + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $3\gspr_index$next[6:0]$227 \dmi_din [6:0] + case + assign $3\gspr_index$next[6:0]$227 \gspr_index + end + case + assign $2\gspr_index$next[6:0]$226 \gspr_index + end + case + assign $1\gspr_index$next[6:0]$225 \gspr_index + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\gspr_index$next[6:0]$228 7'0000000 + case + assign $4\gspr_index$next[6:0]$228 $1\gspr_index$next[6:0]$225 + end + sync always + update \gspr_index$next $0\gspr_index$next[6:0]$224 + end + attribute \src "libresoc.v:1153.3-1186.6" + process $proc$libresoc.v:1153$229 + assign { } { } + assign { } { } + assign { } { } + assign $0\log_dmi_addr$next[31:0]$230 $4\log_dmi_addr$next[31:0]$234 + attribute \src "libresoc.v:1154.5-1154.29" + switch \initial + attribute \src "libresoc.v:1154.9-1154.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$107 \$103 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\log_dmi_addr$next[31:0]$231 $2\log_dmi_addr$next[31:0]$232 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\log_dmi_addr$next[31:0]$232 $3\log_dmi_addr$next[31:0]$233 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$113 \$111 \$109 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\log_dmi_addr$next[31:0]$233 \log_dmi_addr + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $3\log_dmi_addr$next[31:0]$233 \log_dmi_addr + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $3\log_dmi_addr$next[31:0]$233 \dmi_din [31:0] + case + assign $3\log_dmi_addr$next[31:0]$233 \log_dmi_addr + end + case + assign $2\log_dmi_addr$next[31:0]$232 \log_dmi_addr + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign $1\log_dmi_addr$next[31:0]$231 [31:2] \log_dmi_addr [31:2] + assign $1\log_dmi_addr$next[31:0]$231 [1:0] \$115 [1:0] + case + assign $1\log_dmi_addr$next[31:0]$231 \log_dmi_addr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\log_dmi_addr$next[31:0]$234 0 + case + assign $4\log_dmi_addr$next[31:0]$234 $1\log_dmi_addr$next[31:0]$231 + end + sync always + update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$230 + end + attribute \src "libresoc.v:1187.3-1195.6" + process $proc$libresoc.v:1187$235 + assign { } { } + assign { } { } + assign $0\dmi_read_log_data_1$next[0:0]$236 $1\dmi_read_log_data_1$next[0:0]$237 + attribute \src "libresoc.v:1188.5-1188.29" + switch \initial + attribute \src "libresoc.v:1188.9-1188.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_read_log_data_1$next[0:0]$237 1'0 + case + assign $1\dmi_read_log_data_1$next[0:0]$237 \dmi_read_log_data + end + sync always + update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$236 + end + attribute \src "libresoc.v:1196.3-1204.6" + process $proc$libresoc.v:1196$238 + assign { } { } + assign { } { } + assign $0\dmi_read_log_data$next[0:0]$239 $1\dmi_read_log_data$next[0:0]$240 + attribute \src "libresoc.v:1197.5-1197.29" + switch \initial + attribute \src "libresoc.v:1197.9-1197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_read_log_data$next[0:0]$240 1'0 + case + assign $1\dmi_read_log_data$next[0:0]$240 \$120 + end + sync always + update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$239 + end + attribute \src "libresoc.v:1205.3-1214.6" + process $proc$libresoc.v:1205$241 + assign { } { } + assign { } { } + assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] + attribute \src "libresoc.v:1206.5-1206.29" + switch \initial + attribute \src "libresoc.v:1206.9-1206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\d_cr_req[0:0] \dmi_req_i + case + assign $1\d_cr_req[0:0] 1'0 + end + sync always + update \d_cr_req $0\d_cr_req[0:0] + end + attribute \src "libresoc.v:1215.3-1224.6" + process $proc$libresoc.v:1215$242 + assign { } { } + assign { } { } + assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] + attribute \src "libresoc.v:1216.5-1216.29" + switch \initial + attribute \src "libresoc.v:1216.9-1216.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\d_xer_req[0:0] \dmi_req_i + case + assign $1\d_xer_req[0:0] 1'0 + end + sync always + update \d_xer_req $0\d_xer_req[0:0] + end + attribute \src "libresoc.v:1225.3-1255.6" + process $proc$libresoc.v:1225$243 + assign { } { } + assign { } { } + assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] + attribute \src "libresoc.v:1226.5-1226.29" + switch \initial + attribute \src "libresoc.v:1226.9-1226.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:173" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dmi_dout[63:0] \stat_reg + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dmi_dout[63:0] \core_dbg_pc + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dmi_dout[63:0] \core_dbg_msr + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dmi_dout[63:0] \d_gpr_data + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dmi_dout[63:0] { \log_write_addr_o \log_dmi_addr } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dmi_dout[63:0] \log_dmi_data + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dmi_dout[63:0] \d_cr_data + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dmi_dout[63:0] \d_xer_data + case + assign $1\dmi_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dmi_dout $0\dmi_dout[63:0] + end + attribute \src "libresoc.v:1256.3-1285.6" + process $proc$libresoc.v:1256$244 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_step$next[0:0]$245 $5\do_step$next[0:0]$250 + attribute \src "libresoc.v:1257.5-1257.29" + switch \initial + attribute \src "libresoc.v:1257.9-1257.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$9 \$5 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_step$next[0:0]$246 $2\do_step$next[0:0]$247 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_step$next[0:0]$247 $3\do_step$next[0:0]$248 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$15 \$13 \$11 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_step$next[0:0]$248 $4\do_step$next[0:0]$249 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" + switch \dmi_din [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_step$next[0:0]$249 1'1 + case + assign $4\do_step$next[0:0]$249 1'0 + end + case + assign $3\do_step$next[0:0]$248 1'0 + end + case + assign $2\do_step$next[0:0]$247 1'0 + end + case + assign $1\do_step$next[0:0]$246 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\do_step$next[0:0]$250 1'0 + case + assign $5\do_step$next[0:0]$250 $1\do_step$next[0:0]$246 + end + sync always + update \do_step$next $0\do_step$next[0:0]$245 + end + attribute \src "libresoc.v:1286.3-1315.6" + process $proc$libresoc.v:1286$251 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_reset$next[0:0]$252 $5\do_reset$next[0:0]$257 + attribute \src "libresoc.v:1287.5-1287.29" + switch \initial + attribute \src "libresoc.v:1287.9-1287.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$23 \$19 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_reset$next[0:0]$253 $2\do_reset$next[0:0]$254 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_reset$next[0:0]$254 $3\do_reset$next[0:0]$255 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$29 \$27 \$25 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_reset$next[0:0]$255 $4\do_reset$next[0:0]$256 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" + switch \dmi_din [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_reset$next[0:0]$256 1'1 + case + assign $4\do_reset$next[0:0]$256 1'0 + end + case + assign $3\do_reset$next[0:0]$255 1'0 + end + case + assign $2\do_reset$next[0:0]$254 1'0 + end + case + assign $1\do_reset$next[0:0]$253 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\do_reset$next[0:0]$257 1'0 + case + assign $5\do_reset$next[0:0]$257 $1\do_reset$next[0:0]$253 + end + sync always + update \do_reset$next $0\do_reset$next[0:0]$252 + end + attribute \src "libresoc.v:1316.3-1345.6" + process $proc$libresoc.v:1316$258 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_icreset$next[0:0]$259 $5\do_icreset$next[0:0]$264 + attribute \src "libresoc.v:1317.5-1317.29" + switch \initial + attribute \src "libresoc.v:1317.9-1317.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$37 \$33 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_icreset$next[0:0]$260 $2\do_icreset$next[0:0]$261 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_icreset$next[0:0]$261 $3\do_icreset$next[0:0]$262 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$43 \$41 \$39 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_icreset$next[0:0]$262 $4\do_icreset$next[0:0]$263 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" + switch \dmi_din [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_icreset$next[0:0]$263 1'1 + case + assign $4\do_icreset$next[0:0]$263 1'0 + end + case + assign $3\do_icreset$next[0:0]$262 1'0 + end + case + assign $2\do_icreset$next[0:0]$261 1'0 + end + case + assign $1\do_icreset$next[0:0]$260 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\do_icreset$next[0:0]$264 1'0 + case + assign $5\do_icreset$next[0:0]$264 $1\do_icreset$next[0:0]$260 + end + sync always + update \do_icreset$next $0\do_icreset$next[0:0]$259 + end + attribute \src "libresoc.v:1346.3-1379.6" + process $proc$libresoc.v:1346$265 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_dmi_log_rd$next[0:0]$266 $4\do_dmi_log_rd$next[0:0]$270 + attribute \src "libresoc.v:1347.5-1347.29" + switch \initial + attribute \src "libresoc.v:1347.9-1347.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$51 \$47 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_dmi_log_rd$next[0:0]$267 $2\do_dmi_log_rd$next[0:0]$268 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_dmi_log_rd$next[0:0]$268 $3\do_dmi_log_rd$next[0:0]$269 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$57 \$55 \$53 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\do_dmi_log_rd$next[0:0]$269 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $3\do_dmi_log_rd$next[0:0]$269 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $3\do_dmi_log_rd$next[0:0]$269 1'1 + case + assign $3\do_dmi_log_rd$next[0:0]$269 1'0 + end + case + assign $2\do_dmi_log_rd$next[0:0]$268 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\do_dmi_log_rd$next[0:0]$267 1'1 + case + assign $1\do_dmi_log_rd$next[0:0]$267 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_dmi_log_rd$next[0:0]$270 1'0 + case + assign $4\do_dmi_log_rd$next[0:0]$270 $1\do_dmi_log_rd$next[0:0]$267 + end + sync always + update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$266 + end + attribute \src "libresoc.v:676.7-676.20" + process $proc$libresoc.v:676$271 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:847.7-847.31" + process $proc$libresoc.v:847$272 + assign { } { } + assign $1\dmi_read_log_data[0:0] 1'0 + sync always + sync init + update \dmi_read_log_data $1\dmi_read_log_data[0:0] + end + attribute \src "libresoc.v:851.7-851.33" + process $proc$libresoc.v:851$273 + assign { } { } + assign $1\dmi_read_log_data_1[0:0] 1'0 + sync always + sync init + update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] + end + attribute \src "libresoc.v:857.7-857.25" + process $proc$libresoc.v:857$274 + assign { } { } + assign $1\dmi_req_i_1[0:0] 1'0 + sync always + sync init + update \dmi_req_i_1 $1\dmi_req_i_1[0:0] + end + attribute \src "libresoc.v:863.7-863.27" + process $proc$libresoc.v:863$275 + assign { } { } + assign $1\do_dmi_log_rd[0:0] 1'0 + sync always + sync init + update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] + end + attribute \src "libresoc.v:867.7-867.24" + process $proc$libresoc.v:867$276 + assign { } { } + assign $1\do_icreset[0:0] 1'0 + sync always + sync init + update \do_icreset $1\do_icreset[0:0] + end + attribute \src "libresoc.v:871.7-871.22" + process $proc$libresoc.v:871$277 + assign { } { } + assign $1\do_reset[0:0] 1'0 + sync always + sync init + update \do_reset $1\do_reset[0:0] + end + attribute \src "libresoc.v:875.7-875.21" + process $proc$libresoc.v:875$278 + assign { } { } + assign $1\do_step[0:0] 1'0 + sync always + sync init + update \do_step $1\do_step[0:0] + end + attribute \src "libresoc.v:879.13-879.31" + process $proc$libresoc.v:879$279 + assign { } { } + assign $1\gspr_index[6:0] 7'0000000 + sync always + sync init + update \gspr_index $1\gspr_index[6:0] + end + attribute \src "libresoc.v:889.14-889.34" + process $proc$libresoc.v:889$280 + assign { } { } + assign $1\log_dmi_addr[31:0] 0 + sync always + sync init + update \log_dmi_addr $1\log_dmi_addr[31:0] + end + attribute \src "libresoc.v:899.7-899.22" + process $proc$libresoc.v:899$281 + assign { } { } + assign $1\stopping[0:0] 1'0 + sync always + sync init + update \stopping $1\stopping[0:0] + end + attribute \src "libresoc.v:905.7-905.24" + process $proc$libresoc.v:905$282 + assign { } { } + assign $1\terminated[0:0] 1'0 + sync always + sync init + update \terminated $1\terminated[0:0] + end + attribute \src "libresoc.v:972.3-973.51" + process $proc$libresoc.v:972$188 + assign { } { } + assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next + sync posedge \intclk_clk + update \dmi_read_log_data $0\dmi_read_log_data[0:0] + end + attribute \src "libresoc.v:974.3-975.55" + process $proc$libresoc.v:974$189 + assign { } { } + assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next + sync posedge \intclk_clk + update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] + end + attribute \src "libresoc.v:976.3-977.41" + process $proc$libresoc.v:976$190 + assign { } { } + assign $0\log_dmi_addr[31:0] \log_dmi_addr$next + sync posedge \intclk_clk + update \log_dmi_addr $0\log_dmi_addr[31:0] + end + attribute \src "libresoc.v:978.3-979.37" + process $proc$libresoc.v:978$191 + assign { } { } + assign $0\gspr_index[6:0] \gspr_index$next + sync posedge \intclk_clk + update \gspr_index $0\gspr_index[6:0] + end + attribute \src "libresoc.v:980.3-981.33" + process $proc$libresoc.v:980$192 + assign { } { } + assign $0\stopping[0:0] \stopping$next + sync posedge \intclk_clk + update \stopping $0\stopping[0:0] + end + attribute \src "libresoc.v:982.3-983.37" + process $proc$libresoc.v:982$193 + assign { } { } + assign $0\terminated[0:0] \terminated$next + sync posedge \intclk_clk + update \terminated $0\terminated[0:0] + end + attribute \src "libresoc.v:984.3-985.39" + process $proc$libresoc.v:984$194 + assign { } { } + assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next + sync posedge \intclk_clk + update \dmi_req_i_1 $0\dmi_req_i_1[0:0] + end + attribute \src "libresoc.v:986.3-987.43" + process $proc$libresoc.v:986$195 + assign { } { } + assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next + sync posedge \intclk_clk + update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] + end + attribute \src "libresoc.v:988.3-989.37" + process $proc$libresoc.v:988$196 + assign { } { } + assign $0\do_icreset[0:0] \do_icreset$next + sync posedge \intclk_clk + update \do_icreset $0\do_icreset[0:0] + end + attribute \src "libresoc.v:990.3-991.33" + process $proc$libresoc.v:990$197 + assign { } { } + assign $0\do_reset[0:0] \do_reset$next + sync posedge \intclk_clk + update \do_reset $0\do_reset[0:0] + end + attribute \src "libresoc.v:992.3-993.31" + process $proc$libresoc.v:992$198 + assign { } { } + assign $0\do_step[0:0] \do_step$next + sync posedge \intclk_clk + update \do_step $0\do_step[0:0] + end + attribute \src "libresoc.v:994.3-1011.6" + process $proc$libresoc.v:994$199 + assign { } { } + assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] + attribute \src "libresoc.v:995.5-995.29" + switch \initial + attribute \src "libresoc.v:995.9-995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_gpr_ack + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_cr_ack + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_xer_ack + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi_ack_o[0:0] \dmi_req_i + end + sync always + update \dmi_ack_o $0\dmi_ack_o[0:0] + end + connect \$9 $and$libresoc.v:910$126_Y + connect \$99 $eq$libresoc.v:911$127_Y + connect \$101 $not$libresoc.v:912$128_Y + connect \$103 $and$libresoc.v:913$129_Y + connect \$105 $not$libresoc.v:914$130_Y + connect \$107 $and$libresoc.v:915$131_Y + connect \$109 $eq$libresoc.v:916$132_Y + connect \$111 $eq$libresoc.v:917$133_Y + connect \$113 $eq$libresoc.v:918$134_Y + connect \$116 $add$libresoc.v:919$135_Y + connect \$118 $eq$libresoc.v:920$136_Y + connect \$11 $eq$libresoc.v:921$137_Y + connect \$120 $and$libresoc.v:922$138_Y + connect \$122 $not$libresoc.v:923$139_Y + connect \$124 $and$libresoc.v:924$140_Y + connect \$13 $eq$libresoc.v:925$141_Y + connect \$15 $eq$libresoc.v:926$142_Y + connect \$17 $not$libresoc.v:927$143_Y + connect \$1 $pos$libresoc.v:928$144_Y + connect \$19 $and$libresoc.v:929$145_Y + connect \$21 $not$libresoc.v:930$146_Y + connect \$23 $and$libresoc.v:931$147_Y + connect \$25 $eq$libresoc.v:932$148_Y + connect \$27 $eq$libresoc.v:933$149_Y + connect \$29 $eq$libresoc.v:934$150_Y + connect \$31 $not$libresoc.v:935$151_Y + connect \$33 $and$libresoc.v:936$152_Y + connect \$35 $not$libresoc.v:937$153_Y + connect \$37 $and$libresoc.v:938$154_Y + connect \$3 $not$libresoc.v:939$155_Y + connect \$39 $eq$libresoc.v:940$156_Y + connect \$41 $eq$libresoc.v:941$157_Y + connect \$43 $eq$libresoc.v:942$158_Y + connect \$45 $not$libresoc.v:943$159_Y + connect \$47 $and$libresoc.v:944$160_Y + connect \$49 $not$libresoc.v:945$161_Y + connect \$51 $and$libresoc.v:946$162_Y + connect \$53 $eq$libresoc.v:947$163_Y + connect \$55 $eq$libresoc.v:948$164_Y + connect \$57 $eq$libresoc.v:949$165_Y + connect \$5 $and$libresoc.v:950$166_Y + connect \$59 $not$libresoc.v:951$167_Y + connect \$61 $and$libresoc.v:952$168_Y + connect \$63 $not$libresoc.v:953$169_Y + connect \$65 $and$libresoc.v:954$170_Y + connect \$67 $eq$libresoc.v:955$171_Y + connect \$69 $eq$libresoc.v:956$172_Y + connect \$71 $eq$libresoc.v:957$173_Y + connect \$73 $not$libresoc.v:958$174_Y + connect \$75 $and$libresoc.v:959$175_Y + connect \$77 $not$libresoc.v:960$176_Y + connect \$7 $not$libresoc.v:961$177_Y + connect \$79 $and$libresoc.v:962$178_Y + connect \$81 $eq$libresoc.v:963$179_Y + connect \$83 $eq$libresoc.v:964$180_Y + connect \$85 $eq$libresoc.v:965$181_Y + connect \$87 $not$libresoc.v:966$182_Y + connect \$89 $and$libresoc.v:967$183_Y + connect \$91 $not$libresoc.v:968$184_Y + connect \$93 $and$libresoc.v:969$185_Y + connect \$95 $eq$libresoc.v:970$186_Y + connect \$97 $eq$libresoc.v:971$187_Y + connect \$115 \$116 + connect \log_write_addr_o 0 + connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \terminated_o \terminated + connect \icache_rst_o \do_icreset + connect \core_rst_o \do_reset + connect \core_stop_o \$124 + connect \d_gpr_addr \gspr_index + connect \stat_reg \$1 +end +attribute \src "libresoc.v:1393.1-7326.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec" +attribute \generator "nMigen" +module \dec + attribute \src "libresoc.v:3587.3-3725.6" + wire width 8 $0\asmcode[7:0] + attribute \src "libresoc.v:5572.3-5713.6" + wire $0\br[0:0] + attribute \src "libresoc.v:4294.3-4435.6" + wire width 3 $0\cr_in[2:0] + attribute \src "libresoc.v:4436.3-4577.6" + wire width 3 $0\cr_out[2:0] + attribute \src "libresoc.v:5004.3-5145.6" + wire width 2 $0\cry_in[1:0] + attribute \src "libresoc.v:5430.3-5571.6" + wire $0\cry_out[0:0] + attribute \src "libresoc.v:6850.3-6991.6" + wire width 5 $0\form[4:0] + attribute \src "libresoc.v:6566.3-6707.6" + wire width 12 $0\function_unit[11:0] + attribute \src "libresoc.v:3726.3-3867.6" + wire width 3 $0\in1_sel[2:0] + attribute \src "libresoc.v:3868.3-4009.6" + wire width 4 $0\in2_sel[3:0] + attribute \src "libresoc.v:4010.3-4151.6" + wire width 2 $0\in3_sel[1:0] + attribute \src "libresoc.v:1394.7-1394.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:6708.3-6849.6" + wire width 7 $0\internal_op[6:0] + attribute \src "libresoc.v:5146.3-5287.6" + wire $0\inv_a[0:0] + attribute \src "libresoc.v:5288.3-5429.6" + wire $0\inv_out[0:0] + attribute \src "libresoc.v:5998.3-6139.6" + wire $0\is_32b[0:0] + attribute \src "libresoc.v:4578.3-4719.6" + wire width 4 $0\ldst_len[3:0] + attribute \src "libresoc.v:6282.3-6423.6" + wire $0\lk[0:0] + attribute \src "libresoc.v:4152.3-4293.6" + wire width 2 $0\out_sel[1:0] + attribute \src "libresoc.v:4862.3-5003.6" + wire width 2 $0\rc_sel[1:0] + attribute \src "libresoc.v:5856.3-5997.6" + wire $0\rsrv[0:0] + attribute \src "libresoc.v:6424.3-6565.6" + wire $0\sgl_pipe[0:0] + attribute \src "libresoc.v:6140.3-6281.6" + wire $0\sgn[0:0] + attribute \src "libresoc.v:5714.3-5855.6" + wire $0\sgn_ext[0:0] + attribute \src "libresoc.v:4720.3-4861.6" + wire width 2 $0\upd[1:0] + attribute \src "libresoc.v:3587.3-3725.6" + wire width 8 $1\asmcode[7:0] + attribute \src "libresoc.v:5572.3-5713.6" + wire $1\br[0:0] + attribute \src "libresoc.v:4294.3-4435.6" + wire width 3 $1\cr_in[2:0] + attribute \src "libresoc.v:4436.3-4577.6" + wire width 3 $1\cr_out[2:0] + attribute \src "libresoc.v:5004.3-5145.6" + wire width 2 $1\cry_in[1:0] + attribute \src "libresoc.v:5430.3-5571.6" + wire $1\cry_out[0:0] + attribute \src "libresoc.v:6850.3-6991.6" + wire width 5 $1\form[4:0] + attribute \src "libresoc.v:6566.3-6707.6" + wire width 12 $1\function_unit[11:0] + attribute \src "libresoc.v:3726.3-3867.6" + wire width 3 $1\in1_sel[2:0] + attribute \src "libresoc.v:3868.3-4009.6" + wire width 4 $1\in2_sel[3:0] + attribute \src "libresoc.v:4010.3-4151.6" + wire width 2 $1\in3_sel[1:0] + attribute \src "libresoc.v:6708.3-6849.6" + wire width 7 $1\internal_op[6:0] + attribute \src "libresoc.v:5146.3-5287.6" + wire $1\inv_a[0:0] + attribute \src "libresoc.v:5288.3-5429.6" + wire $1\inv_out[0:0] + attribute \src "libresoc.v:5998.3-6139.6" + wire $1\is_32b[0:0] + attribute \src "libresoc.v:4578.3-4719.6" + wire width 4 $1\ldst_len[3:0] + attribute \src "libresoc.v:6282.3-6423.6" + wire $1\lk[0:0] + attribute \src "libresoc.v:4152.3-4293.6" + wire width 2 $1\out_sel[1:0] + attribute \src "libresoc.v:4862.3-5003.6" + wire width 2 $1\rc_sel[1:0] + attribute \src "libresoc.v:5856.3-5997.6" + wire $1\rsrv[0:0] + attribute \src "libresoc.v:6424.3-6565.6" + wire $1\sgl_pipe[0:0] + attribute \src "libresoc.v:6140.3-6281.6" + wire $1\sgn[0:0] + attribute \src "libresoc.v:5714.3-5855.6" + wire $1\sgn_ext[0:0] + attribute \src "libresoc.v:4720.3-4861.6" + wire width 2 $1\upd[1:0] + attribute \src "libresoc.v:3587.3-3725.6" + wire width 8 $2\asmcode[7:0] + attribute \src "libresoc.v:5572.3-5713.6" + wire $2\br[0:0] + attribute \src "libresoc.v:4294.3-4435.6" + wire width 3 $2\cr_in[2:0] + attribute \src "libresoc.v:4436.3-4577.6" + wire width 3 $2\cr_out[2:0] + attribute \src "libresoc.v:5004.3-5145.6" + wire width 2 $2\cry_in[1:0] + attribute \src "libresoc.v:5430.3-5571.6" + wire $2\cry_out[0:0] + attribute \src "libresoc.v:6850.3-6991.6" + wire width 5 $2\form[4:0] + attribute \src "libresoc.v:6566.3-6707.6" + wire width 12 $2\function_unit[11:0] + attribute \src "libresoc.v:3726.3-3867.6" + wire width 3 $2\in1_sel[2:0] + attribute \src "libresoc.v:3868.3-4009.6" + wire width 4 $2\in2_sel[3:0] + attribute \src "libresoc.v:4010.3-4151.6" + wire width 2 $2\in3_sel[1:0] + attribute \src "libresoc.v:6708.3-6849.6" + wire width 7 $2\internal_op[6:0] + attribute \src "libresoc.v:5146.3-5287.6" + wire $2\inv_a[0:0] + attribute \src "libresoc.v:5288.3-5429.6" + wire $2\inv_out[0:0] + attribute \src "libresoc.v:5998.3-6139.6" + wire $2\is_32b[0:0] + attribute \src "libresoc.v:4578.3-4719.6" + wire width 4 $2\ldst_len[3:0] + attribute \src "libresoc.v:6282.3-6423.6" + wire $2\lk[0:0] + attribute \src "libresoc.v:4152.3-4293.6" + wire width 2 $2\out_sel[1:0] + attribute \src "libresoc.v:4862.3-5003.6" + wire width 2 $2\rc_sel[1:0] + attribute \src "libresoc.v:5856.3-5997.6" + wire $2\rsrv[0:0] + attribute \src "libresoc.v:6424.3-6565.6" + wire $2\sgl_pipe[0:0] + attribute \src "libresoc.v:6140.3-6281.6" + wire $2\sgn[0:0] + attribute \src "libresoc.v:5714.3-5855.6" + wire $2\sgn_ext[0:0] + attribute \src "libresoc.v:4720.3-4861.6" + wire width 2 $2\upd[1:0] + attribute \src "libresoc.v:3451.17-3451.211" + wire width 32 $ternary$libresoc.v:3451$283_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + wire width 32 \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 25 \BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 24 \BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 30 \BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 3 \BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 2 \BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 29 \BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 28 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 26 \BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 output 27 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 11 \LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 23 \OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 20 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 21 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 18 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 19 \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 22 \Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 output 31 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 output 34 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 output 35 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 32 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 33 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 16 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 36 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec19_dec19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec19_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec19_dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec19_dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec19_dec19_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec19_dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec19_dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec19_dec19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec19_dec19_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec19_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec19_dec19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec19_dec19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec19_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec19_dec19_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec19_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec30_dec30_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec30_dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec30_dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec30_dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec30_dec30_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec30_dec30_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec30_dec30_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec30_dec30_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec30_dec30_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec30_dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec30_dec30_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec30_dec30_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec30_dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec30_dec30_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec30_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec31_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec31_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec31_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec31_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec31_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec31_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec31_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec58_dec58_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec58_dec58_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec58_dec58_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec58_dec58_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec58_dec58_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec58_dec58_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec58_dec58_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec58_dec58_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec58_dec58_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec58_dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec58_dec58_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec58_dec58_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec58_dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec58_dec58_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec58_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec62_dec62_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec62_dec62_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec62_dec62_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec62_dec62_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec62_dec62_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec62_dec62_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec62_dec62_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec62_dec62_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec62_dec62_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec62_dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec62_dec62_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec62_dec62_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec62_dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec62_dec62_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec62_opcode_in + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 7 \function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 12 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 13 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \in3_sel + attribute \src "libresoc.v:1394.7-1394.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 6 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 9 \is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 32 \opcode_switch$1 + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 15 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 1 \raw_opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 3 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \sh + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 17 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$libresoc.v:3451$283 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:3451$283_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:3452.9-3478.4" + cell \dec19 \dec19 + connect \dec19_asmcode \dec19_dec19_asmcode + connect \dec19_br \dec19_dec19_br + connect \dec19_cr_in \dec19_dec19_cr_in + connect \dec19_cr_out \dec19_dec19_cr_out + connect \dec19_cry_in \dec19_dec19_cry_in + connect \dec19_cry_out \dec19_dec19_cry_out + connect \dec19_form \dec19_dec19_form + connect \dec19_function_unit \dec19_dec19_function_unit + connect \dec19_in1_sel \dec19_dec19_in1_sel + connect \dec19_in2_sel \dec19_dec19_in2_sel + connect \dec19_in3_sel \dec19_dec19_in3_sel + connect \dec19_internal_op \dec19_dec19_internal_op + connect \dec19_inv_a \dec19_dec19_inv_a + connect \dec19_inv_out \dec19_dec19_inv_out + connect \dec19_is_32b \dec19_dec19_is_32b + connect \dec19_ldst_len \dec19_dec19_ldst_len + connect \dec19_lk \dec19_dec19_lk + connect \dec19_out_sel \dec19_dec19_out_sel + connect \dec19_rc_sel \dec19_dec19_rc_sel + connect \dec19_rsrv \dec19_dec19_rsrv + connect \dec19_sgl_pipe \dec19_dec19_sgl_pipe + connect \dec19_sgn \dec19_dec19_sgn + connect \dec19_sgn_ext \dec19_dec19_sgn_ext + connect \dec19_upd \dec19_dec19_upd + connect \opcode_in \dec19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:3479.9-3505.4" + cell \dec30 \dec30 + connect \dec30_asmcode \dec30_dec30_asmcode + connect \dec30_br \dec30_dec30_br + connect \dec30_cr_in \dec30_dec30_cr_in + connect \dec30_cr_out \dec30_dec30_cr_out + connect \dec30_cry_in \dec30_dec30_cry_in + connect \dec30_cry_out \dec30_dec30_cry_out + connect \dec30_form \dec30_dec30_form + connect \dec30_function_unit \dec30_dec30_function_unit + connect \dec30_in1_sel \dec30_dec30_in1_sel + connect \dec30_in2_sel \dec30_dec30_in2_sel + connect \dec30_in3_sel \dec30_dec30_in3_sel + connect \dec30_internal_op \dec30_dec30_internal_op + connect \dec30_inv_a \dec30_dec30_inv_a + connect \dec30_inv_out \dec30_dec30_inv_out + connect \dec30_is_32b \dec30_dec30_is_32b + connect \dec30_ldst_len \dec30_dec30_ldst_len + connect \dec30_lk \dec30_dec30_lk + connect \dec30_out_sel \dec30_dec30_out_sel + connect \dec30_rc_sel \dec30_dec30_rc_sel + connect \dec30_rsrv \dec30_dec30_rsrv + connect \dec30_sgl_pipe \dec30_dec30_sgl_pipe + connect \dec30_sgn \dec30_dec30_sgn + connect \dec30_sgn_ext \dec30_dec30_sgn_ext + connect \dec30_upd \dec30_dec30_upd + connect \opcode_in \dec30_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:3506.9-3532.4" + cell \dec31 \dec31 + connect \dec31_asmcode \dec31_dec31_asmcode + connect \dec31_br \dec31_dec31_br + connect \dec31_cr_in \dec31_dec31_cr_in + connect \dec31_cr_out \dec31_dec31_cr_out + connect \dec31_cry_in \dec31_dec31_cry_in + connect \dec31_cry_out \dec31_dec31_cry_out + connect \dec31_form \dec31_dec31_form + connect \dec31_function_unit \dec31_dec31_function_unit + connect \dec31_in1_sel \dec31_dec31_in1_sel + connect \dec31_in2_sel \dec31_dec31_in2_sel + connect \dec31_in3_sel \dec31_dec31_in3_sel + connect \dec31_internal_op \dec31_dec31_internal_op + connect \dec31_inv_a \dec31_dec31_inv_a + connect \dec31_inv_out \dec31_dec31_inv_out + connect \dec31_is_32b \dec31_dec31_is_32b + connect \dec31_ldst_len \dec31_dec31_ldst_len + connect \dec31_lk \dec31_dec31_lk + connect \dec31_out_sel \dec31_dec31_out_sel + connect \dec31_rc_sel \dec31_dec31_rc_sel + connect \dec31_rsrv \dec31_dec31_rsrv + connect \dec31_sgl_pipe \dec31_dec31_sgl_pipe + connect \dec31_sgn \dec31_dec31_sgn + connect \dec31_sgn_ext \dec31_dec31_sgn_ext + connect \dec31_upd \dec31_dec31_upd + connect \opcode_in \dec31_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:3533.9-3559.4" + cell \dec58 \dec58 + connect \dec58_asmcode \dec58_dec58_asmcode + connect \dec58_br \dec58_dec58_br + connect \dec58_cr_in \dec58_dec58_cr_in + connect \dec58_cr_out \dec58_dec58_cr_out + connect \dec58_cry_in \dec58_dec58_cry_in + connect \dec58_cry_out \dec58_dec58_cry_out + connect \dec58_form \dec58_dec58_form + connect \dec58_function_unit \dec58_dec58_function_unit + connect \dec58_in1_sel \dec58_dec58_in1_sel + connect \dec58_in2_sel \dec58_dec58_in2_sel + connect \dec58_in3_sel \dec58_dec58_in3_sel + connect \dec58_internal_op \dec58_dec58_internal_op + connect \dec58_inv_a \dec58_dec58_inv_a + connect \dec58_inv_out \dec58_dec58_inv_out + connect \dec58_is_32b \dec58_dec58_is_32b + connect \dec58_ldst_len \dec58_dec58_ldst_len + connect \dec58_lk \dec58_dec58_lk + connect \dec58_out_sel \dec58_dec58_out_sel + connect \dec58_rc_sel \dec58_dec58_rc_sel + connect \dec58_rsrv \dec58_dec58_rsrv + connect \dec58_sgl_pipe \dec58_dec58_sgl_pipe + connect \dec58_sgn \dec58_dec58_sgn + connect \dec58_sgn_ext \dec58_dec58_sgn_ext + connect \dec58_upd \dec58_dec58_upd + connect \opcode_in \dec58_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:3560.9-3586.4" + cell \dec62 \dec62 + connect \dec62_asmcode \dec62_dec62_asmcode + connect \dec62_br \dec62_dec62_br + connect \dec62_cr_in \dec62_dec62_cr_in + connect \dec62_cr_out \dec62_dec62_cr_out + connect \dec62_cry_in \dec62_dec62_cry_in + connect \dec62_cry_out \dec62_dec62_cry_out + connect \dec62_form \dec62_dec62_form + connect \dec62_function_unit \dec62_dec62_function_unit + connect \dec62_in1_sel \dec62_dec62_in1_sel + connect \dec62_in2_sel \dec62_dec62_in2_sel + connect \dec62_in3_sel \dec62_dec62_in3_sel + connect \dec62_internal_op \dec62_dec62_internal_op + connect \dec62_inv_a \dec62_dec62_inv_a + connect \dec62_inv_out \dec62_dec62_inv_out + connect \dec62_is_32b \dec62_dec62_is_32b + connect \dec62_ldst_len \dec62_dec62_ldst_len + connect \dec62_lk \dec62_dec62_lk + connect \dec62_out_sel \dec62_dec62_out_sel + connect \dec62_rc_sel \dec62_dec62_rc_sel + connect \dec62_rsrv \dec62_dec62_rsrv + connect \dec62_sgl_pipe \dec62_dec62_sgl_pipe + connect \dec62_sgn \dec62_dec62_sgn + connect \dec62_sgn_ext \dec62_dec62_sgn_ext + connect \dec62_upd \dec62_dec62_upd + connect \opcode_in \dec62_opcode_in + end + attribute \src "libresoc.v:1394.7-1394.20" + process $proc$libresoc.v:1394$308 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:3587.3-3725.6" + process $proc$libresoc.v:3587$284 + assign { } { } + assign { } { } + assign { } { } + assign $0\asmcode[7:0] $2\asmcode[7:0] + attribute \src "libresoc.v:3588.5-3588.29" + switch \initial + attribute \src "libresoc.v:3588.9-3588.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\asmcode[7:0] \dec19_dec19_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\asmcode[7:0] \dec30_dec30_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\asmcode[7:0] \dec31_dec31_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\asmcode[7:0] \dec58_dec58_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\asmcode[7:0] \dec62_dec62_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\asmcode[7:0] 8'00000111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\asmcode[7:0] 8'00001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\asmcode[7:0] 8'00000110 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\asmcode[7:0] 8'00001001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\asmcode[7:0] 8'00010001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\asmcode[7:0] 8'00010010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\asmcode[7:0] 8'00010100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\asmcode[7:0] 8'00010101 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\asmcode[7:0] 8'00011101 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\asmcode[7:0] 8'00011111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\asmcode[7:0] 8'01001110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\asmcode[7:0] 8'01001111 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\asmcode[7:0] 8'01011000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\asmcode[7:0] 8'01011010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\asmcode[7:0] 8'01011110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\asmcode[7:0] 8'01011111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\asmcode[7:0] 8'01100111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\asmcode[7:0] 8'01101001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\asmcode[7:0] 8'10000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\asmcode[7:0] 8'10001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\asmcode[7:0] 8'10001011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\asmcode[7:0] 8'10011000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\asmcode[7:0] 8'10011001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\asmcode[7:0] 8'10011010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\asmcode[7:0] 8'10100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\asmcode[7:0] 8'10101001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\asmcode[7:0] 8'10110010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\asmcode[7:0] 8'10110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\asmcode[7:0] 8'10111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\asmcode[7:0] 8'10111011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\asmcode[7:0] 8'11000011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\asmcode[7:0] 8'11001011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\asmcode[7:0] 8'11001111 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\asmcode[7:0] 8'11010001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\asmcode[7:0] 8'11010010 + case + assign $1\asmcode[7:0] 8'00000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\asmcode[7:0] 8'00010011 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\asmcode[7:0] 8'10000110 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\asmcode[7:0] 8'10011100 + case + assign $2\asmcode[7:0] $1\asmcode[7:0] + end + sync always + update \asmcode $0\asmcode[7:0] + end + attribute \src "libresoc.v:3726.3-3867.6" + process $proc$libresoc.v:3726$285 + assign { } { } + assign { } { } + assign { } { } + assign $0\in1_sel[2:0] $2\in1_sel[2:0] + attribute \src "libresoc.v:3727.5-3727.29" + switch \initial + attribute \src "libresoc.v:3727.9-3727.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in1_sel[2:0] \dec19_dec19_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in1_sel[2:0] \dec30_dec30_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in1_sel[2:0] \dec31_dec31_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in1_sel[2:0] \dec58_dec58_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in1_sel[2:0] \dec62_dec62_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + case + assign $1\in1_sel[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in1_sel[2:0] 3'000 + case + assign $2\in1_sel[2:0] $1\in1_sel[2:0] + end + sync always + update \in1_sel $0\in1_sel[2:0] + end + attribute \src "libresoc.v:3868.3-4009.6" + process $proc$libresoc.v:3868$286 + assign { } { } + assign { } { } + assign { } { } + assign $0\in2_sel[3:0] $2\in2_sel[3:0] + attribute \src "libresoc.v:3869.5-3869.29" + switch \initial + attribute \src "libresoc.v:3869.9-3869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in2_sel[3:0] \dec19_dec19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in2_sel[3:0] \dec30_dec30_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in2_sel[3:0] \dec31_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in2_sel[3:0] \dec58_dec58_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in2_sel[3:0] \dec62_dec62_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in2_sel[3:0] 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in2_sel[3:0] 4'0110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in2_sel[3:0] 4'0111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + case + assign $1\in2_sel[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + case + assign $2\in2_sel[3:0] $1\in2_sel[3:0] + end + sync always + update \in2_sel $0\in2_sel[3:0] + end + attribute \src "libresoc.v:4010.3-4151.6" + process $proc$libresoc.v:4010$287 + assign { } { } + assign { } { } + assign { } { } + assign $0\in3_sel[1:0] $2\in3_sel[1:0] + attribute \src "libresoc.v:4011.5-4011.29" + switch \initial + attribute \src "libresoc.v:4011.9-4011.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in3_sel[1:0] \dec19_dec19_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in3_sel[1:0] \dec30_dec30_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in3_sel[1:0] \dec31_dec31_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in3_sel[1:0] \dec58_dec58_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in3_sel[1:0] \dec62_dec62_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + case + assign $1\in3_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in3_sel[1:0] 2'00 + case + assign $2\in3_sel[1:0] $1\in3_sel[1:0] + end + sync always + update \in3_sel $0\in3_sel[1:0] + end + attribute \src "libresoc.v:4152.3-4293.6" + process $proc$libresoc.v:4152$288 + assign { } { } + assign { } { } + assign { } { } + assign $0\out_sel[1:0] $2\out_sel[1:0] + attribute \src "libresoc.v:4153.5-4153.29" + switch \initial + attribute \src "libresoc.v:4153.9-4153.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\out_sel[1:0] \dec19_dec19_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\out_sel[1:0] \dec30_dec30_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\out_sel[1:0] \dec31_dec31_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\out_sel[1:0] \dec58_dec58_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\out_sel[1:0] \dec62_dec62_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\out_sel[1:0] 2'10 + case + assign $1\out_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\out_sel[1:0] 2'01 + case + assign $2\out_sel[1:0] $1\out_sel[1:0] + end + sync always + update \out_sel $0\out_sel[1:0] + end + attribute \src "libresoc.v:4294.3-4435.6" + process $proc$libresoc.v:4294$289 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_in[2:0] $2\cr_in[2:0] + attribute \src "libresoc.v:4295.5-4295.29" + switch \initial + attribute \src "libresoc.v:4295.9-4295.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cr_in[2:0] \dec19_dec19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cr_in[2:0] \dec30_dec30_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cr_in[2:0] \dec31_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cr_in[2:0] \dec58_dec58_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cr_in[2:0] \dec62_dec62_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + case + assign $1\cr_in[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cr_in[2:0] 3'000 + case + assign $2\cr_in[2:0] $1\cr_in[2:0] + end + sync always + update \cr_in $0\cr_in[2:0] + end + attribute \src "libresoc.v:4436.3-4577.6" + process $proc$libresoc.v:4436$290 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_out[2:0] $2\cr_out[2:0] + attribute \src "libresoc.v:4437.5-4437.29" + switch \initial + attribute \src "libresoc.v:4437.9-4437.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cr_out[2:0] \dec19_dec19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cr_out[2:0] \dec30_dec30_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cr_out[2:0] \dec31_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cr_out[2:0] \dec58_dec58_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cr_out[2:0] \dec62_dec62_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + case + assign $1\cr_out[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cr_out[2:0] 3'000 + case + assign $2\cr_out[2:0] $1\cr_out[2:0] + end + sync always + update \cr_out $0\cr_out[2:0] + end + attribute \src "libresoc.v:4578.3-4719.6" + process $proc$libresoc.v:4578$291 + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_len[3:0] $2\ldst_len[3:0] + attribute \src "libresoc.v:4579.5-4579.29" + switch \initial + attribute \src "libresoc.v:4579.9-4579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ldst_len[3:0] \dec19_dec19_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\ldst_len[3:0] \dec30_dec30_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ldst_len[3:0] \dec31_dec31_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\ldst_len[3:0] \dec58_dec58_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\ldst_len[3:0] \dec62_dec62_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + case + assign $1\ldst_len[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + case + assign $2\ldst_len[3:0] $1\ldst_len[3:0] + end + sync always + update \ldst_len $0\ldst_len[3:0] + end + attribute \src "libresoc.v:4720.3-4861.6" + process $proc$libresoc.v:4720$292 + assign { } { } + assign { } { } + assign { } { } + assign $0\upd[1:0] $2\upd[1:0] + attribute \src "libresoc.v:4721.5-4721.29" + switch \initial + attribute \src "libresoc.v:4721.9-4721.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\upd[1:0] \dec19_dec19_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\upd[1:0] \dec30_dec30_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\upd[1:0] \dec31_dec31_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\upd[1:0] \dec58_dec58_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\upd[1:0] \dec62_dec62_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\upd[1:0] 2'00 + case + assign $1\upd[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\upd[1:0] 2'00 + case + assign $2\upd[1:0] $1\upd[1:0] + end + sync always + update \upd $0\upd[1:0] + end + attribute \src "libresoc.v:4862.3-5003.6" + process $proc$libresoc.v:4862$293 + assign { } { } + assign { } { } + assign { } { } + assign $0\rc_sel[1:0] $2\rc_sel[1:0] + attribute \src "libresoc.v:4863.5-4863.29" + switch \initial + attribute \src "libresoc.v:4863.9-4863.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\rc_sel[1:0] \dec19_dec19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\rc_sel[1:0] \dec30_dec30_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\rc_sel[1:0] \dec31_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\rc_sel[1:0] \dec58_dec58_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\rc_sel[1:0] \dec62_dec62_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + case + assign $1\rc_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\rc_sel[1:0] 2'00 + case + assign $2\rc_sel[1:0] $1\rc_sel[1:0] + end + sync always + update \rc_sel $0\rc_sel[1:0] + end + attribute \src "libresoc.v:5004.3-5145.6" + process $proc$libresoc.v:5004$294 + assign { } { } + assign { } { } + assign { } { } + assign $0\cry_in[1:0] $2\cry_in[1:0] + attribute \src "libresoc.v:5005.5-5005.29" + switch \initial + attribute \src "libresoc.v:5005.9-5005.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cry_in[1:0] \dec19_dec19_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cry_in[1:0] \dec30_dec30_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cry_in[1:0] \dec31_dec31_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cry_in[1:0] \dec58_dec58_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cry_in[1:0] \dec62_dec62_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + case + assign $1\cry_in[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cry_in[1:0] 2'00 + case + assign $2\cry_in[1:0] $1\cry_in[1:0] + end + sync always + update \cry_in $0\cry_in[1:0] + end + attribute \src "libresoc.v:5146.3-5287.6" + process $proc$libresoc.v:5146$295 + assign { } { } + assign { } { } + assign { } { } + assign $0\inv_a[0:0] $2\inv_a[0:0] + attribute \src "libresoc.v:5147.5-5147.29" + switch \initial + attribute \src "libresoc.v:5147.9-5147.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\inv_a[0:0] \dec19_dec19_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\inv_a[0:0] \dec30_dec30_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\inv_a[0:0] \dec31_dec31_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\inv_a[0:0] \dec58_dec58_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\inv_a[0:0] \dec62_dec62_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + case + assign $1\inv_a[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\inv_a[0:0] 1'0 + case + assign $2\inv_a[0:0] $1\inv_a[0:0] + end + sync always + update \inv_a $0\inv_a[0:0] + end + attribute \src "libresoc.v:5288.3-5429.6" + process $proc$libresoc.v:5288$296 + assign { } { } + assign { } { } + assign { } { } + assign $0\inv_out[0:0] $2\inv_out[0:0] + attribute \src "libresoc.v:5289.5-5289.29" + switch \initial + attribute \src "libresoc.v:5289.9-5289.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\inv_out[0:0] \dec19_dec19_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\inv_out[0:0] \dec30_dec30_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\inv_out[0:0] \dec31_dec31_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\inv_out[0:0] \dec58_dec58_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\inv_out[0:0] \dec62_dec62_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + case + assign $1\inv_out[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\inv_out[0:0] 1'0 + case + assign $2\inv_out[0:0] $1\inv_out[0:0] + end + sync always + update \inv_out $0\inv_out[0:0] + end + attribute \src "libresoc.v:5430.3-5571.6" + process $proc$libresoc.v:5430$297 + assign { } { } + assign { } { } + assign { } { } + assign $0\cry_out[0:0] $2\cry_out[0:0] + attribute \src "libresoc.v:5431.5-5431.29" + switch \initial + attribute \src "libresoc.v:5431.9-5431.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cry_out[0:0] \dec19_dec19_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cry_out[0:0] \dec30_dec30_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cry_out[0:0] \dec31_dec31_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cry_out[0:0] \dec58_dec58_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cry_out[0:0] \dec62_dec62_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + case + assign $1\cry_out[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cry_out[0:0] 1'0 + case + assign $2\cry_out[0:0] $1\cry_out[0:0] + end + sync always + update \cry_out $0\cry_out[0:0] + end + attribute \src "libresoc.v:5572.3-5713.6" + process $proc$libresoc.v:5572$298 + assign { } { } + assign { } { } + assign { } { } + assign $0\br[0:0] $2\br[0:0] + attribute \src "libresoc.v:5573.5-5573.29" + switch \initial + attribute \src "libresoc.v:5573.9-5573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\br[0:0] \dec19_dec19_br + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\br[0:0] \dec30_dec30_br + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\br[0:0] \dec31_dec31_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\br[0:0] \dec58_dec58_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\br[0:0] \dec62_dec62_br + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\br[0:0] 1'0 + case + assign $1\br[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\br[0:0] 1'0 + case + assign $2\br[0:0] $1\br[0:0] + end + sync always + update \br $0\br[0:0] + end + attribute \src "libresoc.v:5714.3-5855.6" + process $proc$libresoc.v:5714$299 + assign { } { } + assign { } { } + assign { } { } + assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] + attribute \src "libresoc.v:5715.5-5715.29" + switch \initial + attribute \src "libresoc.v:5715.9-5715.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgn_ext[0:0] \dec19_dec19_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgn_ext[0:0] \dec30_dec30_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgn_ext[0:0] \dec31_dec31_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgn_ext[0:0] \dec58_dec58_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgn_ext[0:0] \dec62_dec62_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + case + assign $1\sgn_ext[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + case + assign $2\sgn_ext[0:0] $1\sgn_ext[0:0] + end + sync always + update \sgn_ext $0\sgn_ext[0:0] + end + attribute \src "libresoc.v:5856.3-5997.6" + process $proc$libresoc.v:5856$300 + assign { } { } + assign { } { } + assign { } { } + assign $0\rsrv[0:0] $2\rsrv[0:0] + attribute \src "libresoc.v:5857.5-5857.29" + switch \initial + attribute \src "libresoc.v:5857.9-5857.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\rsrv[0:0] \dec19_dec19_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\rsrv[0:0] \dec30_dec30_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\rsrv[0:0] \dec31_dec31_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\rsrv[0:0] \dec58_dec58_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\rsrv[0:0] \dec62_dec62_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + case + assign $1\rsrv[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\rsrv[0:0] 1'0 + case + assign $2\rsrv[0:0] $1\rsrv[0:0] + end + sync always + update \rsrv $0\rsrv[0:0] + end + attribute \src "libresoc.v:5998.3-6139.6" + process $proc$libresoc.v:5998$301 + assign { } { } + assign { } { } + assign { } { } + assign $0\is_32b[0:0] $2\is_32b[0:0] + attribute \src "libresoc.v:5999.5-5999.29" + switch \initial + attribute \src "libresoc.v:5999.9-5999.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\is_32b[0:0] \dec19_dec19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\is_32b[0:0] \dec30_dec30_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\is_32b[0:0] \dec31_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\is_32b[0:0] \dec58_dec58_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\is_32b[0:0] \dec62_dec62_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + case + assign $1\is_32b[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\is_32b[0:0] 1'0 + case + assign $2\is_32b[0:0] $1\is_32b[0:0] + end + sync always + update \is_32b $0\is_32b[0:0] + end + attribute \src "libresoc.v:6140.3-6281.6" + process $proc$libresoc.v:6140$302 + assign { } { } + assign { } { } + assign { } { } + assign $0\sgn[0:0] $2\sgn[0:0] + attribute \src "libresoc.v:6141.5-6141.29" + switch \initial + attribute \src "libresoc.v:6141.9-6141.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgn[0:0] \dec19_dec19_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgn[0:0] \dec30_dec30_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgn[0:0] \dec31_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgn[0:0] \dec58_dec58_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgn[0:0] \dec62_dec62_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgn[0:0] 1'0 + case + assign $1\sgn[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgn[0:0] 1'0 + case + assign $2\sgn[0:0] $1\sgn[0:0] + end + sync always + update \sgn $0\sgn[0:0] + end + attribute \src "libresoc.v:6282.3-6423.6" + process $proc$libresoc.v:6282$303 + assign { } { } + assign { } { } + assign { } { } + assign $0\lk[0:0] $2\lk[0:0] + attribute \src "libresoc.v:6283.5-6283.29" + switch \initial + attribute \src "libresoc.v:6283.9-6283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\lk[0:0] \dec19_dec19_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\lk[0:0] \dec30_dec30_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\lk[0:0] \dec31_dec31_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\lk[0:0] \dec58_dec58_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\lk[0:0] \dec62_dec62_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\lk[0:0] 1'0 + case + assign $1\lk[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\lk[0:0] 1'0 + case + assign $2\lk[0:0] $1\lk[0:0] + end + sync always + update \lk $0\lk[0:0] + end + attribute \src "libresoc.v:6424.3-6565.6" + process $proc$libresoc.v:6424$304 + assign { } { } + assign { } { } + assign { } { } + assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] + attribute \src "libresoc.v:6425.5-6425.29" + switch \initial + attribute \src "libresoc.v:6425.9-6425.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgl_pipe[0:0] \dec19_dec19_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgl_pipe[0:0] \dec30_dec30_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgl_pipe[0:0] \dec31_dec31_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgl_pipe[0:0] \dec58_dec58_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgl_pipe[0:0] \dec62_dec62_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + case + assign $1\sgl_pipe[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgl_pipe[0:0] 1'1 + case + assign $2\sgl_pipe[0:0] $1\sgl_pipe[0:0] + end + sync always + update \sgl_pipe $0\sgl_pipe[0:0] + end + attribute \src "libresoc.v:6566.3-6707.6" + process $proc$libresoc.v:6566$305 + assign { } { } + assign { } { } + assign { } { } + assign $0\function_unit[11:0] $2\function_unit[11:0] + attribute \src "libresoc.v:6567.5-6567.29" + switch \initial + attribute \src "libresoc.v:6567.9-6567.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\function_unit[11:0] \dec19_dec19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\function_unit[11:0] \dec30_dec30_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\function_unit[11:0] \dec31_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\function_unit[11:0] \dec58_dec58_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\function_unit[11:0] \dec62_dec62_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + case + assign $1\function_unit[11:0] 12'000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\function_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\function_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\function_unit[11:0] 12'000000000000 + case + assign $2\function_unit[11:0] $1\function_unit[11:0] + end + sync always + update \function_unit $0\function_unit[11:0] + end + attribute \src "libresoc.v:6708.3-6849.6" + process $proc$libresoc.v:6708$306 + assign { } { } + assign { } { } + assign { } { } + assign $0\internal_op[6:0] $2\internal_op[6:0] + attribute \src "libresoc.v:6709.5-6709.29" + switch \initial + attribute \src "libresoc.v:6709.9-6709.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\internal_op[6:0] \dec19_dec19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\internal_op[6:0] \dec30_dec30_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\internal_op[6:0] \dec31_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\internal_op[6:0] \dec58_dec58_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\internal_op[6:0] \dec62_dec62_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\internal_op[6:0] 7'1001001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\internal_op[6:0] 7'0000110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\internal_op[6:0] 7'0000111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\internal_op[6:0] 7'1000011 + case + assign $1\internal_op[6:0] 7'0000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\internal_op[6:0] 7'0000101 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\internal_op[6:0] 7'1000100 + case + assign $2\internal_op[6:0] $1\internal_op[6:0] + end + sync always + update \internal_op $0\internal_op[6:0] + end + attribute \src "libresoc.v:6850.3-6991.6" + process $proc$libresoc.v:6850$307 + assign { } { } + assign { } { } + assign { } { } + assign $0\form[4:0] $2\form[4:0] + attribute \src "libresoc.v:6851.5-6851.29" + switch \initial + attribute \src "libresoc.v:6851.9-6851.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\form[4:0] \dec19_dec19_form + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\form[4:0] \dec30_dec30_form + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\form[4:0] \dec31_dec31_form + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\form[4:0] \dec58_dec58_form + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\form[4:0] \dec62_dec62_form + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\form[4:0] 5'00011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\form[4:0] 5'00001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\form[4:0] 5'00100 + case + assign $1\form[4:0] 5'00000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\form[4:0] 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\form[4:0] 5'00000 + case + assign $2\form[4:0] $1\form[4:0] + end + sync always + update \form $0\form[4:0] + end + connect \$2 $ternary$libresoc.v:3451$283_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \SPR \opcode_in [20:11] + connect \MB \opcode_in [10:6] + connect \ME \opcode_in [5:1] + connect \SH \opcode_in [15:11] + connect \BC \opcode_in [10:6] + connect \TO \opcode_in [25:21] + connect \DS \opcode_in [15:2] + connect \D \opcode_in [15:0] + connect \BH \opcode_in [12:11] + connect \BI \opcode_in [20:16] + connect \BO \opcode_in [25:21] + connect \FXM \opcode_in [19:12] + connect \BT \opcode_in [25:21] + connect \BA \opcode_in [20:16] + connect \BB \opcode_in [15:11] + connect \CR \opcode_in [10:1] + connect \BF \opcode_in [25:23] + connect \BD \opcode_in [15:2] + connect \OE \opcode_in [10] + connect \Rc \opcode_in [0] + connect \AA \opcode_in [1] + connect \LK \opcode_in [0] + connect \LI \opcode_in [25:2] + connect \ME32 \opcode_in [5:1] + connect \MB32 \opcode_in [10:6] + connect \sh { \opcode_in [1] \opcode_in [15:11] } + connect \SH32 \opcode_in [15:11] + connect \L \opcode_in [21] + connect \UI \opcode_in [15:0] + connect \SI \opcode_in [15:0] + connect \RB \opcode_in [15:11] + connect \RA \opcode_in [20:16] + connect \RT \opcode_in [25:21] + connect \RS \opcode_in [25:21] + connect \opcode_in \$2 + connect \opcode_switch$1 \opcode_in + connect \dec62_opcode_in \opcode_in + connect \dec58_opcode_in \opcode_in + connect \dec31_opcode_in \opcode_in + connect \dec30_opcode_in \opcode_in + connect \dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:7330.1-8837.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19" +attribute \generator "nMigen" +module \dec19 + attribute \src "libresoc.v:7848.3-7899.6" + wire width 8 $0\dec19_asmcode[7:0] + attribute \src "libresoc.v:8056.3-8107.6" + wire $0\dec19_br[0:0] + attribute \src "libresoc.v:8732.3-8783.6" + wire width 3 $0\dec19_cr_in[2:0] + attribute \src "libresoc.v:8784.3-8835.6" + wire width 3 $0\dec19_cr_out[2:0] + attribute \src "libresoc.v:7796.3-7847.6" + wire width 2 $0\dec19_cry_in[1:0] + attribute \src "libresoc.v:8004.3-8055.6" + wire $0\dec19_cry_out[0:0] + attribute \src "libresoc.v:8472.3-8523.6" + wire width 5 $0\dec19_form[4:0] + attribute \src "libresoc.v:7588.3-7639.6" + wire width 12 $0\dec19_function_unit[11:0] + attribute \src "libresoc.v:8524.3-8575.6" + wire width 3 $0\dec19_in1_sel[2:0] + attribute \src "libresoc.v:8576.3-8627.6" + wire width 4 $0\dec19_in2_sel[3:0] + attribute \src "libresoc.v:8628.3-8679.6" + wire width 2 $0\dec19_in3_sel[1:0] + attribute \src "libresoc.v:8160.3-8211.6" + wire width 7 $0\dec19_internal_op[6:0] + attribute \src "libresoc.v:7900.3-7951.6" + wire $0\dec19_inv_a[0:0] + attribute \src "libresoc.v:7952.3-8003.6" + wire $0\dec19_inv_out[0:0] + attribute \src "libresoc.v:8264.3-8315.6" + wire $0\dec19_is_32b[0:0] + attribute \src "libresoc.v:7640.3-7691.6" + wire width 4 $0\dec19_ldst_len[3:0] + attribute \src "libresoc.v:8368.3-8419.6" + wire $0\dec19_lk[0:0] + attribute \src "libresoc.v:8680.3-8731.6" + wire width 2 $0\dec19_out_sel[1:0] + attribute \src "libresoc.v:7744.3-7795.6" + wire width 2 $0\dec19_rc_sel[1:0] + attribute \src "libresoc.v:8212.3-8263.6" + wire $0\dec19_rsrv[0:0] + attribute \src "libresoc.v:8420.3-8471.6" + wire $0\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:8316.3-8367.6" + wire $0\dec19_sgn[0:0] + attribute \src "libresoc.v:8108.3-8159.6" + wire $0\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:7692.3-7743.6" + wire width 2 $0\dec19_upd[1:0] + attribute \src "libresoc.v:7331.7-7331.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:7848.3-7899.6" + wire width 8 $1\dec19_asmcode[7:0] + attribute \src "libresoc.v:8056.3-8107.6" + wire $1\dec19_br[0:0] + attribute \src "libresoc.v:8732.3-8783.6" + wire width 3 $1\dec19_cr_in[2:0] + attribute \src "libresoc.v:8784.3-8835.6" + wire width 3 $1\dec19_cr_out[2:0] + attribute \src "libresoc.v:7796.3-7847.6" + wire width 2 $1\dec19_cry_in[1:0] + attribute \src "libresoc.v:8004.3-8055.6" + wire $1\dec19_cry_out[0:0] + attribute \src "libresoc.v:8472.3-8523.6" + wire width 5 $1\dec19_form[4:0] + attribute \src "libresoc.v:7588.3-7639.6" + wire width 12 $1\dec19_function_unit[11:0] + attribute \src "libresoc.v:8524.3-8575.6" + wire width 3 $1\dec19_in1_sel[2:0] + attribute \src "libresoc.v:8576.3-8627.6" + wire width 4 $1\dec19_in2_sel[3:0] + attribute \src "libresoc.v:8628.3-8679.6" + wire width 2 $1\dec19_in3_sel[1:0] + attribute \src "libresoc.v:8160.3-8211.6" + wire width 7 $1\dec19_internal_op[6:0] + attribute \src "libresoc.v:7900.3-7951.6" + wire $1\dec19_inv_a[0:0] + attribute \src "libresoc.v:7952.3-8003.6" + wire $1\dec19_inv_out[0:0] + attribute \src "libresoc.v:8264.3-8315.6" + wire $1\dec19_is_32b[0:0] + attribute \src "libresoc.v:7640.3-7691.6" + wire width 4 $1\dec19_ldst_len[3:0] + attribute \src "libresoc.v:8368.3-8419.6" + wire $1\dec19_lk[0:0] + attribute \src "libresoc.v:8680.3-8731.6" + wire width 2 $1\dec19_out_sel[1:0] + attribute \src "libresoc.v:7744.3-7795.6" + wire width 2 $1\dec19_rc_sel[1:0] + attribute \src "libresoc.v:8212.3-8263.6" + wire $1\dec19_rsrv[0:0] + attribute \src "libresoc.v:8420.3-8471.6" + wire $1\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:8316.3-8367.6" + wire $1\dec19_sgn[0:0] + attribute \src "libresoc.v:8108.3-8159.6" + wire $1\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:7692.3-7743.6" + wire width 2 $1\dec19_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec19_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec19_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec19_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec19_upd + attribute \src "libresoc.v:7331.7-7331.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \src "libresoc.v:7331.7-7331.20" + process $proc$libresoc.v:7331$333 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:7588.3-7639.6" + process $proc$libresoc.v:7588$309 + assign { } { } + assign { } { } + assign $0\dec19_function_unit[11:0] $1\dec19_function_unit[11:0] + attribute \src "libresoc.v:7589.5-7589.29" + switch \initial + attribute \src "libresoc.v:7589.9-7589.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000010000000 + case + assign $1\dec19_function_unit[11:0] 12'000000000000 + end + sync always + update \dec19_function_unit $0\dec19_function_unit[11:0] + end + attribute \src "libresoc.v:7640.3-7691.6" + process $proc$libresoc.v:7640$310 + assign { } { } + assign { } { } + assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] + attribute \src "libresoc.v:7641.5-7641.29" + switch \initial + attribute \src "libresoc.v:7641.9-7641.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + case + assign $1\dec19_ldst_len[3:0] 4'0000 + end + sync always + update \dec19_ldst_len $0\dec19_ldst_len[3:0] + end + attribute \src "libresoc.v:7692.3-7743.6" + process $proc$libresoc.v:7692$311 + assign { } { } + assign { } { } + assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] + attribute \src "libresoc.v:7693.5-7693.29" + switch \initial + attribute \src "libresoc.v:7693.9-7693.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + case + assign $1\dec19_upd[1:0] 2'00 + end + sync always + update \dec19_upd $0\dec19_upd[1:0] + end + attribute \src "libresoc.v:7744.3-7795.6" + process $proc$libresoc.v:7744$312 + assign { } { } + assign { } { } + assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] + attribute \src "libresoc.v:7745.5-7745.29" + switch \initial + attribute \src "libresoc.v:7745.9-7745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + case + assign $1\dec19_rc_sel[1:0] 2'00 + end + sync always + update \dec19_rc_sel $0\dec19_rc_sel[1:0] + end + attribute \src "libresoc.v:7796.3-7847.6" + process $proc$libresoc.v:7796$313 + assign { } { } + assign { } { } + assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] + attribute \src "libresoc.v:7797.5-7797.29" + switch \initial + attribute \src "libresoc.v:7797.9-7797.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + case + assign $1\dec19_cry_in[1:0] 2'00 + end + sync always + update \dec19_cry_in $0\dec19_cry_in[1:0] + end + attribute \src "libresoc.v:7848.3-7899.6" + process $proc$libresoc.v:7848$314 + assign { } { } + assign { } { } + assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] + attribute \src "libresoc.v:7849.5-7849.29" + switch \initial + attribute \src "libresoc.v:7849.9-7849.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'10010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01001000 + case + assign $1\dec19_asmcode[7:0] 8'00000000 + end + sync always + update \dec19_asmcode $0\dec19_asmcode[7:0] + end + attribute \src "libresoc.v:7900.3-7951.6" + process $proc$libresoc.v:7900$315 + assign { } { } + assign { } { } + assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] + attribute \src "libresoc.v:7901.5-7901.29" + switch \initial + attribute \src "libresoc.v:7901.9-7901.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + case + assign $1\dec19_inv_a[0:0] 1'0 + end + sync always + update \dec19_inv_a $0\dec19_inv_a[0:0] + end + attribute \src "libresoc.v:7952.3-8003.6" + process $proc$libresoc.v:7952$316 + assign { } { } + assign { } { } + assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] + attribute \src "libresoc.v:7953.5-7953.29" + switch \initial + attribute \src "libresoc.v:7953.9-7953.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + case + assign $1\dec19_inv_out[0:0] 1'0 + end + sync always + update \dec19_inv_out $0\dec19_inv_out[0:0] + end + attribute \src "libresoc.v:8004.3-8055.6" + process $proc$libresoc.v:8004$317 + assign { } { } + assign { } { } + assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] + attribute \src "libresoc.v:8005.5-8005.29" + switch \initial + attribute \src "libresoc.v:8005.9-8005.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + case + assign $1\dec19_cry_out[0:0] 1'0 + end + sync always + update \dec19_cry_out $0\dec19_cry_out[0:0] + end + attribute \src "libresoc.v:8056.3-8107.6" + process $proc$libresoc.v:8056$318 + assign { } { } + assign { } { } + assign $0\dec19_br[0:0] $1\dec19_br[0:0] + attribute \src "libresoc.v:8057.5-8057.29" + switch \initial + attribute \src "libresoc.v:8057.9-8057.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + case + assign $1\dec19_br[0:0] 1'0 + end + sync always + update \dec19_br $0\dec19_br[0:0] + end + attribute \src "libresoc.v:8108.3-8159.6" + process $proc$libresoc.v:8108$319 + assign { } { } + assign { } { } + assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:8109.5-8109.29" + switch \initial + attribute \src "libresoc.v:8109.9-8109.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + case + assign $1\dec19_sgn_ext[0:0] 1'0 + end + sync always + update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] + end + attribute \src "libresoc.v:8160.3-8211.6" + process $proc$libresoc.v:8160$320 + assign { } { } + assign { } { } + assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] + attribute \src "libresoc.v:8161.5-8161.29" + switch \initial + attribute \src "libresoc.v:8161.9-8161.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000110 + case + assign $1\dec19_internal_op[6:0] 7'0000000 + end + sync always + update \dec19_internal_op $0\dec19_internal_op[6:0] + end + attribute \src "libresoc.v:8212.3-8263.6" + process $proc$libresoc.v:8212$321 + assign { } { } + assign { } { } + assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] + attribute \src "libresoc.v:8213.5-8213.29" + switch \initial + attribute \src "libresoc.v:8213.9-8213.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + case + assign $1\dec19_rsrv[0:0] 1'0 + end + sync always + update \dec19_rsrv $0\dec19_rsrv[0:0] + end + attribute \src "libresoc.v:8264.3-8315.6" + process $proc$libresoc.v:8264$322 + assign { } { } + assign { } { } + assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] + attribute \src "libresoc.v:8265.5-8265.29" + switch \initial + attribute \src "libresoc.v:8265.9-8265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + case + assign $1\dec19_is_32b[0:0] 1'0 + end + sync always + update \dec19_is_32b $0\dec19_is_32b[0:0] + end + attribute \src "libresoc.v:8316.3-8367.6" + process $proc$libresoc.v:8316$323 + assign { } { } + assign { } { } + assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] + attribute \src "libresoc.v:8317.5-8317.29" + switch \initial + attribute \src "libresoc.v:8317.9-8317.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + case + assign $1\dec19_sgn[0:0] 1'0 + end + sync always + update \dec19_sgn $0\dec19_sgn[0:0] + end + attribute \src "libresoc.v:8368.3-8419.6" + process $proc$libresoc.v:8368$324 + assign { } { } + assign { } { } + assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] + attribute \src "libresoc.v:8369.5-8369.29" + switch \initial + attribute \src "libresoc.v:8369.9-8369.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + case + assign $1\dec19_lk[0:0] 1'0 + end + sync always + update \dec19_lk $0\dec19_lk[0:0] + end + attribute \src "libresoc.v:8420.3-8471.6" + process $proc$libresoc.v:8420$325 + assign { } { } + assign { } { } + assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:8421.5-8421.29" + switch \initial + attribute \src "libresoc.v:8421.9-8421.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + case + assign $1\dec19_sgl_pipe[0:0] 1'0 + end + sync always + update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] + end + attribute \src "libresoc.v:8472.3-8523.6" + process $proc$libresoc.v:8472$326 + assign { } { } + assign { } { } + assign $0\dec19_form[4:0] $1\dec19_form[4:0] + attribute \src "libresoc.v:8473.5-8473.29" + switch \initial + attribute \src "libresoc.v:8473.9-8473.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + case + assign $1\dec19_form[4:0] 5'00000 + end + sync always + update \dec19_form $0\dec19_form[4:0] + end + attribute \src "libresoc.v:8524.3-8575.6" + process $proc$libresoc.v:8524$327 + assign { } { } + assign { } { } + assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] + attribute \src "libresoc.v:8525.5-8525.29" + switch \initial + attribute \src "libresoc.v:8525.9-8525.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + case + assign $1\dec19_in1_sel[2:0] 3'000 + end + sync always + update \dec19_in1_sel $0\dec19_in1_sel[2:0] + end + attribute \src "libresoc.v:8576.3-8627.6" + process $proc$libresoc.v:8576$328 + assign { } { } + assign { } { } + assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] + attribute \src "libresoc.v:8577.5-8577.29" + switch \initial + attribute \src "libresoc.v:8577.9-8577.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + case + assign $1\dec19_in2_sel[3:0] 4'0000 + end + sync always + update \dec19_in2_sel $0\dec19_in2_sel[3:0] + end + attribute \src "libresoc.v:8628.3-8679.6" + process $proc$libresoc.v:8628$329 + assign { } { } + assign { } { } + assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] + attribute \src "libresoc.v:8629.5-8629.29" + switch \initial + attribute \src "libresoc.v:8629.9-8629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + case + assign $1\dec19_in3_sel[1:0] 2'00 + end + sync always + update \dec19_in3_sel $0\dec19_in3_sel[1:0] + end + attribute \src "libresoc.v:8680.3-8731.6" + process $proc$libresoc.v:8680$330 + assign { } { } + assign { } { } + assign $0\dec19_out_sel[1:0] $1\dec19_out_sel[1:0] + attribute \src "libresoc.v:8681.5-8681.29" + switch \initial + attribute \src "libresoc.v:8681.9-8681.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + case + assign $1\dec19_out_sel[1:0] 2'00 + end + sync always + update \dec19_out_sel $0\dec19_out_sel[1:0] + end + attribute \src "libresoc.v:8732.3-8783.6" + process $proc$libresoc.v:8732$331 + assign { } { } + assign { } { } + assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] + attribute \src "libresoc.v:8733.5-8733.29" + switch \initial + attribute \src "libresoc.v:8733.9-8733.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + case + assign $1\dec19_cr_in[2:0] 3'000 + end + sync always + update \dec19_cr_in $0\dec19_cr_in[2:0] + end + attribute \src "libresoc.v:8784.3-8835.6" + process $proc$libresoc.v:8784$332 + assign { } { } + assign { } { } + assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] + attribute \src "libresoc.v:8785.5-8785.29" + switch \initial + attribute \src "libresoc.v:8785.9-8785.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + case + assign $1\dec19_cr_out[2:0] 3'000 + end + sync always + update \dec19_cr_out $0\dec19_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:8841.1-10730.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2" +attribute \generator "nMigen" +module \dec2 + attribute \src "libresoc.v:10596.3-10677.6" + wire width 8 $0\asmcode[7:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 64 $0\cia[63:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $0\cr_in1[2:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\cr_in1_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $0\cr_in2$1[2:0]$352 + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $0\cr_in2[2:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\cr_in2_ok$2[0:0]$353 + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\cr_in2_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $0\cr_out[2:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\cr_out_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 8 $0\cr_rd[7:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\cr_rd_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 8 $0\cr_wr[7:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\cr_wr_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 5 $0\ea[4:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\ea_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $0\fast1[2:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $0\fast2[2:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $0\fasto1[2:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\fasto1_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $0\fasto2[2:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\fasto2_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 12 $0\fn_unit[11:0] + attribute \src "libresoc.v:8842.7-8842.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 2 $0\input_carry[1:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 32 $0\insn[31:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 7 $0\insn_type[6:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\is_32bit[0:0] + attribute \src "libresoc.v:10576.3-10595.6" + wire $0\is_priv_insn[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\lk[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 64 $0\msr[63:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 5 $0\reg1[4:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\reg1_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 5 $0\reg2[4:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\reg2_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 5 $0\reg3[4:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\reg3_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 5 $0\rego[4:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\rego_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 10 $0\spr1[9:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\spr1_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 10 $0\spro[9:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\spro_ok[0:0] + attribute \src "libresoc.v:10530.3-10539.6" + wire $0\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:10566.3-10575.6" + wire width 13 $0\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:10540.3-10555.6" + wire width 3 $0\tmp_xer_in[2:0] + attribute \src "libresoc.v:10556.3-10565.6" + wire $0\tmp_xer_out[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 13 $0\trapaddr[12:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 7 $0\traptype[6:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $0\xer_in[2:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $0\xer_out[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 8 $1\asmcode[7:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 64 $1\cia[63:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $1\cr_in1[2:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\cr_in1_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $1\cr_in2$1[2:0]$354 + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $1\cr_in2[2:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\cr_in2_ok$2[0:0]$355 + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\cr_in2_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $1\cr_out[2:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\cr_out_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 8 $1\cr_rd[7:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\cr_rd_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 8 $1\cr_wr[7:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\cr_wr_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 5 $1\ea[4:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\ea_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $1\fast1[2:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $1\fast2[2:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\fast2_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $1\fasto1[2:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\fasto1_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $1\fasto2[2:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\fasto2_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 12 $1\fn_unit[11:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 2 $1\input_carry[1:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 32 $1\insn[31:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 7 $1\insn_type[6:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\is_32bit[0:0] + attribute \src "libresoc.v:10576.3-10595.6" + wire $1\is_priv_insn[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\lk[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 64 $1\msr[63:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\rc_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 5 $1\reg1[4:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\reg1_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 5 $1\reg2[4:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\reg2_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 5 $1\reg3[4:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\reg3_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 5 $1\rego[4:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\rego_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 10 $1\spr1[9:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\spr1_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 10 $1\spro[9:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\spro_ok[0:0] + attribute \src "libresoc.v:10530.3-10539.6" + wire $1\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:10566.3-10575.6" + wire width 13 $1\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:10540.3-10555.6" + wire width 3 $1\tmp_xer_in[2:0] + attribute \src "libresoc.v:10556.3-10565.6" + wire $1\tmp_xer_out[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 13 $1\trapaddr[12:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 7 $1\traptype[6:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $1\xer_in[2:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $1\xer_out[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $2\fast1[2:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $2\fast1_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $2\fast2[2:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $2\fast2_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $2\fasto1[2:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $2\fasto1_ok[0:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire width 3 $2\fasto2[2:0] + attribute \src "libresoc.v:10596.3-10677.6" + wire $2\fasto2_ok[0:0] + attribute \src "libresoc.v:10576.3-10595.6" + wire $2\is_priv_insn[0:0] + attribute \src "libresoc.v:10540.3-10555.6" + wire width 3 $2\tmp_xer_in[2:0] + attribute \src "libresoc.v:10381.18-10381.120" + wire $and$libresoc.v:10381$338_Y + attribute \src "libresoc.v:10382.18-10382.123" + wire $and$libresoc.v:10382$339_Y + attribute \src "libresoc.v:10383.18-10383.124" + wire $and$libresoc.v:10383$340_Y + attribute \src "libresoc.v:10377.18-10377.122" + wire $eq$libresoc.v:10377$334_Y + attribute \src "libresoc.v:10378.18-10378.122" + wire $eq$libresoc.v:10378$335_Y + attribute \src "libresoc.v:10379.18-10379.122" + wire $eq$libresoc.v:10379$336_Y + attribute \src "libresoc.v:10380.18-10380.122" + wire $eq$libresoc.v:10380$337_Y + attribute \src "libresoc.v:10384.18-10384.122" + wire $eq$libresoc.v:10384$341_Y + attribute \src "libresoc.v:10385.18-10385.116" + wire $eq$libresoc.v:10385$342_Y + attribute \src "libresoc.v:10386.18-10386.116" + wire $eq$libresoc.v:10386$343_Y + attribute \src "libresoc.v:10388.18-10388.116" + wire $eq$libresoc.v:10388$345_Y + attribute \src "libresoc.v:10387.18-10387.110" + wire $or$libresoc.v:10387$344_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:859" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:861" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:863" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:867" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:889" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:890" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:891" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:892" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:923" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:933" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + wire width 8 output 5 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 output 39 \cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 30 \cr_in1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 31 \cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 32 \cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 34 \cr_in2$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 33 \cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 35 \cr_in2_ok$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 36 \cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 37 \cr_out_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 output 51 \cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 52 \cr_rd_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 output 53 \cr_wr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 54 \cr_wr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 input 56 \cur_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + wire input 57 \cur_eint + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 input 3 \cur_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 input 2 \cur_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 \dec_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \dec_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \dec_XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_a_fast_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_a_fast_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_a_reg_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_a_reg_a_ok + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:85" + wire width 3 \dec_a_sel_in + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \dec_a_spr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_a_spr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_b_fast_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_b_fast_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_b_reg_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_b_reg_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire width 4 \dec_b_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_c_reg_c + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_c_reg_c_ok + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" + wire width 2 \dec_c_sel_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_in_cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_in_cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_in_cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_in_cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_in_cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_in_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \dec_cr_in_cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_in_cr_fxm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 \dec_cr_in_sel_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_out_cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \dec_cr_out_cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_out_cr_fxm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 \dec_cr_out_sel_in + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_cry_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:885" + wire \dec_irq_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_o2_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_o2_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363" + wire \dec_o2_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_o2_reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_o2_reg_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_o_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_o_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_o_reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_o_reg_o_ok + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" + wire width 2 \dec_o_sel_in + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \dec_o_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_o_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_rc_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 \dec_rc_sel_in + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 8 \ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 9 \ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:884" + wire \ext_irq_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 22 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 23 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 24 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 25 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 26 \fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 27 \fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 28 \fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 29 \fasto2_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 12 output 42 \fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:887" + wire \illeg_ok + attribute \src "libresoc.v:8842.7-8842.15" + wire \initial + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 2 output 48 \input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 output 40 \insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" + wire width 32 \insn_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" + wire width 32 \insn_in$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" + wire width 32 \insn_in$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + wire width 32 \insn_in$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" + wire width 32 \insn_in$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" + wire width 32 \insn_in$9 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 output 41 \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire output 55 \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:41" + wire \is_priv_insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire output 43 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 output 38 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 46 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 47 \oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" + wire \priv_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 4 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 44 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 45 \rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 10 \reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 11 \reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 12 \reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 13 \reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 14 \reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 15 \reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 6 \rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 7 \rego_ok + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:362" + wire width 2 \sel_in + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 18 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 19 \spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 16 \spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 17 \spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + wire width 8 \tmp_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_cr_in1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_cr_in2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_cr_in2_ok$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_cr_out_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_fasto2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_rego_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \tmp_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \tmp_spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \tmp_tmp_cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \tmp_tmp_cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_cr_rd_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \tmp_tmp_cr_wr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_cr_wr_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 12 \tmp_tmp_fn_unit + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 2 \tmp_tmp_input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 \tmp_tmp_insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 \tmp_tmp_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire \tmp_tmp_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire \tmp_tmp_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 \tmp_tmp_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 13 \tmp_tmp_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 7 \tmp_tmp_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 \tmp_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + wire \tmp_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 13 output 50 \trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 7 output 49 \traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 output 20 \xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + wire output 21 \xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:889" + cell $and $and$libresoc.v:10381$338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_eint + connect \B \cur_msr [15] + connect \Y $and$libresoc.v:10381$338_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:890" + cell $and $and$libresoc.v:10382$339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_dec [63] + connect \B \cur_msr [15] + connect \Y $and$libresoc.v:10382$339_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:891" + cell $and $and$libresoc.v:10383$340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_priv_insn + connect \B \cur_msr [14] + connect \Y $and$libresoc.v:10383$340_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:859" + cell $eq $eq$libresoc.v:10377$334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:10377$334_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:861" + cell $eq $eq$libresoc.v:10378$335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0001010 + connect \Y $eq$libresoc.v:10378$335_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:863" + cell $eq $eq$libresoc.v:10379$336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:10379$336_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:867" + cell $eq $eq$libresoc.v:10380$337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0111111 + connect \Y $eq$libresoc.v:10380$337_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:892" + cell $eq $eq$libresoc.v:10384$341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0000000 + connect \Y $eq$libresoc.v:10384$341_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:923" + cell $eq $eq$libresoc.v:10385$342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'0111111 + connect \Y $eq$libresoc.v:10385$342_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924" + cell $eq $eq$libresoc.v:10386$343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1001001 + connect \Y $eq$libresoc.v:10386$343_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:933" + cell $eq $eq$libresoc.v:10388$345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1000110 + connect \Y $eq$libresoc.v:10388$345_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924" + cell $or $or$libresoc.v:10387$344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$29 + connect \B \$31 + connect \Y $or$libresoc.v:10387$344_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10389.7-10426.4" + cell \dec \dec + connect \BA \dec_BA + connect \BB \dec_BB + connect \BC \dec_BC + connect \BI \dec_BI + connect \BO \dec_BO + connect \BT \dec_BT + connect \FXM \dec_FXM + connect \LK \dec_LK + connect \OE \dec_OE + connect \RA \dec_RA + connect \RB \dec_RB + connect \RS \dec_RS + connect \RT \dec_RT + connect \Rc \dec_Rc + connect \SPR \dec_SPR + connect \XL_BT \dec_XL_BT + connect \XL_XO \dec_XL_XO + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \asmcode \dec_asmcode + connect \bigendian \bigendian + connect \cr_in \dec_cr_in + connect \cr_out \dec_cr_out + connect \cry_in \dec_cry_in + connect \function_unit \dec_function_unit + connect \in1_sel \dec_in1_sel + connect \in2_sel \dec_in2_sel + connect \in3_sel \dec_in3_sel + connect \internal_op \dec_internal_op + connect \is_32b \dec_is_32b + connect \lk \dec_lk + connect \opcode_in \dec_opcode_in + connect \out_sel \dec_out_sel + connect \raw_opcode_in \raw_opcode_in + connect \rc_sel \dec_rc_sel + connect \upd \dec_upd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10427.9-10441.4" + cell \dec_a \dec_a + connect \BO \dec_BO + connect \RA \dec_RA + connect \RS \dec_RS + connect \SPR \dec_SPR + connect \XL_XO \dec_XL_XO + connect \fast_a \dec_a_fast_a + connect \fast_a_ok \dec_a_fast_a_ok + connect \internal_op \dec_internal_op + connect \reg_a \dec_a_reg_a + connect \reg_a_ok \dec_a_reg_a_ok + connect \sel_in \dec_a_sel_in + connect \spr_a \dec_a_spr_a + connect \spr_a_ok \dec_a_spr_a_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10442.9-10452.4" + cell \dec_b \dec_b + connect \RB \dec_RB + connect \RS \dec_RS + connect \XL_XO \dec_XL_XO + connect \fast_b \dec_b_fast_b + connect \fast_b_ok \dec_b_fast_b_ok + connect \internal_op \dec_internal_op + connect \reg_b \dec_b_reg_b + connect \reg_b_ok \dec_b_reg_b_ok + connect \sel_in \dec_b_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10453.9-10459.4" + cell \dec_c \dec_c + connect \RB \dec_RB + connect \RS \dec_RS + connect \reg_c \dec_c_reg_c + connect \reg_c_ok \dec_c_reg_c_ok + connect \sel_in \dec_c_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10460.13-10479.4" + cell \dec_cr_in \dec_cr_in$3 + connect \BA \dec_BA + connect \BB \dec_BB + connect \BC \dec_BC + connect \BI \dec_BI + connect \BT \dec_BT + connect \FXM \dec_FXM + connect \X_BFA \dec_X_BFA + connect \cr_bitfield \dec_cr_in_cr_bitfield + connect \cr_bitfield_b \dec_cr_in_cr_bitfield_b + connect \cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b_ok + connect \cr_bitfield_o \dec_cr_in_cr_bitfield_o + connect \cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o_ok + connect \cr_bitfield_ok \dec_cr_in_cr_bitfield_ok + connect \cr_fxm \dec_cr_in_cr_fxm + connect \cr_fxm_ok \dec_cr_in_cr_fxm_ok + connect \insn_in \dec_cr_in_insn_in + connect \internal_op \dec_internal_op + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10480.14-10492.4" + cell \dec_cr_out \dec_cr_out$4 + connect \FXM \dec_FXM + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield \dec_cr_out_cr_bitfield + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \cr_fxm \dec_cr_out_cr_fxm + connect \cr_fxm_ok \dec_cr_out_cr_fxm_ok + connect \insn_in \dec_cr_out_insn_in + connect \internal_op \dec_internal_op + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10493.9-10506.4" + cell \dec_o \dec_o + connect \BO \dec_BO + connect \RA \dec_RA + connect \RT \dec_RT + connect \SPR \dec_SPR + connect \fast_o \dec_o_fast_o + connect \fast_o_ok \dec_o_fast_o_ok + connect \internal_op \dec_internal_op + connect \reg_o \dec_o_reg_o + connect \reg_o_ok \dec_o_reg_o_ok + connect \sel_in \dec_o_sel_in + connect \spr_o \dec_o_spr_o + connect \spr_o_ok \dec_o_spr_o_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10507.10-10516.4" + cell \dec_o2 \dec_o2 + connect \RA \dec_RA + connect \fast_o \dec_o2_fast_o + connect \fast_o_ok \dec_o2_fast_o_ok + connect \internal_op \dec_internal_op + connect \lk \dec_o2_lk + connect \reg_o \dec_o2_reg_o + connect \reg_o_ok \dec_o2_reg_o_ok + connect \upd \dec_upd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10517.10-10523.4" + cell \dec_oe \dec_oe + connect \OE \dec_OE + connect \internal_op \dec_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10524.10-10529.4" + cell \dec_rc \dec_rc + connect \Rc \dec_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:10530.3-10539.6" + process $proc$libresoc.v:10530$346 + assign { } { } + assign { } { } + assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:10531.5-10531.29" + switch \initial + attribute \src "libresoc.v:10531.9-10531.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:758" + switch \dec_lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_tmp_lk[0:0] \dec_LK + case + assign $1\tmp_tmp_lk[0:0] 1'0 + end + sync always + update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] + end + attribute \src "libresoc.v:10540.3-10555.6" + process $proc$libresoc.v:10540$347 + assign { } { } + assign { } { } + assign { } { } + assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] + attribute \src "libresoc.v:10541.5-10541.29" + switch \initial + attribute \src "libresoc.v:10541.9-10541.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:859" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_xer_in[2:0] 3'111 + case + assign $1\tmp_xer_in[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:861" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\tmp_xer_in[2:0] 3'001 + case + assign $2\tmp_xer_in[2:0] $1\tmp_xer_in[2:0] + end + sync always + update \tmp_xer_in $0\tmp_xer_in[2:0] + end + attribute \src "libresoc.v:10556.3-10565.6" + process $proc$libresoc.v:10556$348 + assign { } { } + assign { } { } + assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] + attribute \src "libresoc.v:10557.5-10557.29" + switch \initial + attribute \src "libresoc.v:10557.9-10557.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:863" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_xer_out[0:0] 1'1 + case + assign $1\tmp_xer_out[0:0] 1'0 + end + sync always + update \tmp_xer_out $0\tmp_xer_out[0:0] + end + attribute \src "libresoc.v:10566.3-10575.6" + process $proc$libresoc.v:10566$349 + assign { } { } + assign { } { } + assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:10567.5-10567.29" + switch \initial + attribute \src "libresoc.v:10567.9-10567.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:867" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_tmp_trapaddr[12:0] 13'0000001110000 + case + assign $1\tmp_tmp_trapaddr[12:0] 13'0000000000000 + end + sync always + update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] + end + attribute \src "libresoc.v:10576.3-10595.6" + process $proc$libresoc.v:10576$350 + assign { } { } + assign { } { } + assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] + attribute \src "libresoc.v:10577.5-10577.29" + switch \initial + attribute \src "libresoc.v:10577.9-10577.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:42" + switch \dec_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110 + assign { } { } + assign $1\is_priv_insn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 , 7'0110001 + assign { } { } + assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:49" + switch \tmp_tmp_insn [20] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\is_priv_insn[0:0] 1'1 + case + assign $2\is_priv_insn[0:0] 1'0 + end + case + assign $1\is_priv_insn[0:0] 1'0 + end + sync always + update \is_priv_insn $0\is_priv_insn[0:0] + end + attribute \src "libresoc.v:10596.3-10677.6" + process $proc$libresoc.v:10596$351 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_out[2:0] $1\cr_out[2:0] + assign $0\lk[0:0] $1\lk[0:0] + assign $0\cia[63:0] $1\cia[63:0] + assign $0\cr_in1[2:0] $1\cr_in1[2:0] + assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0] + assign $0\cr_in2[2:0] $1\cr_in2[2:0] + assign $0\cr_in2$1[2:0]$352 $1\cr_in2$1[2:0]$354 + assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0] + assign $0\cr_in2_ok$2[0:0]$353 $1\cr_in2_ok$2[0:0]$355 + assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0] + assign $0\cr_rd[7:0] $1\cr_rd[7:0] + assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0] + assign $0\cr_wr[7:0] $1\cr_wr[7:0] + assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0] + assign $0\ea[4:0] $1\ea[4:0] + assign $0\ea_ok[0:0] $1\ea_ok[0:0] + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fn_unit[11:0] $1\fn_unit[11:0] + assign $0\input_carry[1:0] $1\input_carry[1:0] + assign $0\insn[31:0] $1\insn[31:0] + assign $0\insn_type[6:0] $1\insn_type[6:0] + assign $0\is_32bit[0:0] $1\is_32bit[0:0] + assign $0\msr[63:0] $1\msr[63:0] + assign $0\oe[0:0] $1\oe[0:0] + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + assign $0\rc[0:0] $1\rc[0:0] + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + assign $0\reg1[4:0] $1\reg1[4:0] + assign $0\reg1_ok[0:0] $1\reg1_ok[0:0] + assign $0\reg2[4:0] $1\reg2[4:0] + assign $0\reg2_ok[0:0] $1\reg2_ok[0:0] + assign $0\reg3[4:0] $1\reg3[4:0] + assign $0\reg3_ok[0:0] $1\reg3_ok[0:0] + assign $0\rego[4:0] $1\rego[4:0] + assign $0\rego_ok[0:0] $1\rego_ok[0:0] + assign $0\spr1[9:0] $1\spr1[9:0] + assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] + assign $0\spro[9:0] $1\spro[9:0] + assign $0\spro_ok[0:0] $1\spro_ok[0:0] + assign $0\trapaddr[12:0] $1\trapaddr[12:0] + assign $0\traptype[6:0] $1\traptype[6:0] + assign $0\xer_in[2:0] $1\xer_in[2:0] + assign $0\xer_out[0:0] $1\xer_out[0:0] + assign $0\fasto1[2:0] $2\fasto1[2:0] + assign $0\fasto1_ok[0:0] $2\fasto1_ok[0:0] + assign $0\fasto2[2:0] $2\fasto2[2:0] + assign $0\fasto2_ok[0:0] $2\fasto2_ok[0:0] + assign $0\fast1[2:0] $2\fast1[2:0] + assign $0\fast1_ok[0:0] $2\fast1_ok[0:0] + assign $0\fast2[2:0] $2\fast2[2:0] + assign $0\fast2_ok[0:0] $2\fast2_ok[0:0] + assign $0\asmcode[7:0] \dec_asmcode + attribute \src "libresoc.v:10597.5-10597.29" + switch \initial + attribute \src "libresoc.v:10597.9-10597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:895" + switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok } + attribute \src "libresoc.v:0.0-0.0" + case 4'---1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$355 $1\cr_in2$1[2:0]$354 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000010010000 + assign $1\traptype[6:0] 7'0100000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 4'--1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$355 $1\cr_in2$1[2:0]$354 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000001010000 + assign $1\traptype[6:0] 7'0010000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 4'-1-- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$355 $1\cr_in2$1[2:0]$354 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000001110000 + assign $1\traptype[6:0] 7'0000010 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 4'1--- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$355 $1\cr_in2$1[2:0]$354 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000001110000 + assign $1\traptype[6:0] 7'1000000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\traptype[6:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[11:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$355 $1\cr_in2$1[2:0]$354 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$12 \tmp_cr_in2$11 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\fasto1[2:0] 3'011 + assign $2\fasto1_ok[0:0] 1'1 + assign $2\fasto2[2:0] 3'100 + assign $2\fasto2_ok[0:0] 1'1 + case + assign $2\fasto1[2:0] $1\fasto1[2:0] + assign $2\fasto1_ok[0:0] $1\fasto1_ok[0:0] + assign $2\fasto2[2:0] $1\fasto2[2:0] + assign $2\fasto2_ok[0:0] $1\fasto2_ok[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:933" + switch \$35 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\fast1[2:0] 3'011 + assign $2\fast1_ok[0:0] 1'1 + assign $2\fast2[2:0] 3'100 + assign $2\fast2_ok[0:0] 1'1 + case + assign $2\fast1[2:0] $1\fast1[2:0] + assign $2\fast1_ok[0:0] $1\fast1_ok[0:0] + assign $2\fast2[2:0] $1\fast2[2:0] + assign $2\fast2_ok[0:0] $1\fast2_ok[0:0] + end + sync always + update \asmcode $0\asmcode[7:0] + update \cr_out $0\cr_out[2:0] + update \lk $0\lk[0:0] + update \cia $0\cia[63:0] + update \cr_in1 $0\cr_in1[2:0] + update \cr_in1_ok $0\cr_in1_ok[0:0] + update \cr_in2 $0\cr_in2[2:0] + update \cr_in2$1 $0\cr_in2$1[2:0]$352 + update \cr_in2_ok $0\cr_in2_ok[0:0] + update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$353 + update \cr_out_ok $0\cr_out_ok[0:0] + update \cr_rd $0\cr_rd[7:0] + update \cr_rd_ok $0\cr_rd_ok[0:0] + update \cr_wr $0\cr_wr[7:0] + update \cr_wr_ok $0\cr_wr_ok[0:0] + update \ea $0\ea[4:0] + update \ea_ok $0\ea_ok[0:0] + update \fast1 $0\fast1[2:0] + update \fast1_ok $0\fast1_ok[0:0] + update \fast2 $0\fast2[2:0] + update \fast2_ok $0\fast2_ok[0:0] + update \fasto1 $0\fasto1[2:0] + update \fasto1_ok $0\fasto1_ok[0:0] + update \fasto2 $0\fasto2[2:0] + update \fasto2_ok $0\fasto2_ok[0:0] + update \fn_unit $0\fn_unit[11:0] + update \input_carry $0\input_carry[1:0] + update \insn $0\insn[31:0] + update \insn_type $0\insn_type[6:0] + update \is_32bit $0\is_32bit[0:0] + update \msr $0\msr[63:0] + update \oe $0\oe[0:0] + update \oe_ok $0\oe_ok[0:0] + update \rc $0\rc[0:0] + update \rc_ok $0\rc_ok[0:0] + update \reg1 $0\reg1[4:0] + update \reg1_ok $0\reg1_ok[0:0] + update \reg2 $0\reg2[4:0] + update \reg2_ok $0\reg2_ok[0:0] + update \reg3 $0\reg3[4:0] + update \reg3_ok $0\reg3_ok[0:0] + update \rego $0\rego[4:0] + update \rego_ok $0\rego_ok[0:0] + update \spr1 $0\spr1[9:0] + update \spr1_ok $0\spr1_ok[0:0] + update \spro $0\spro[9:0] + update \spro_ok $0\spro_ok[0:0] + update \trapaddr $0\trapaddr[12:0] + update \traptype $0\traptype[6:0] + update \xer_in $0\xer_in[2:0] + update \xer_out $0\xer_out[0:0] + end + attribute \src "libresoc.v:8842.7-8842.20" + process $proc$libresoc.v:8842$356 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + connect \$13 $eq$libresoc.v:10377$334_Y + connect \$15 $eq$libresoc.v:10378$335_Y + connect \$17 $eq$libresoc.v:10379$336_Y + connect \$19 $eq$libresoc.v:10380$337_Y + connect \$21 $and$libresoc.v:10381$338_Y + connect \$23 $and$libresoc.v:10382$339_Y + connect \$25 $and$libresoc.v:10383$340_Y + connect \$27 $eq$libresoc.v:10384$341_Y + connect \$29 $eq$libresoc.v:10385$342_Y + connect \$31 $eq$libresoc.v:10386$343_Y + connect \$33 $or$libresoc.v:10387$344_Y + connect \$35 $eq$libresoc.v:10388$345_Y + connect \tmp_asmcode 8'00000000 + connect \tmp_tmp_traptype 7'0000000 + connect \illeg_ok \$27 + connect \priv_ok \$25 + connect \dec_irq_ok \$23 + connect \ext_irq_ok \$21 + connect { \tmp_cr_out_ok \tmp_cr_out } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield } + connect { \tmp_cr_in2_ok$12 \tmp_cr_in2$11 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o } + connect { \tmp_cr_in2_ok \tmp_cr_in2 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b } + connect { \tmp_cr_in1_ok \tmp_cr_in1 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield } + connect { \tmp_fasto2_ok \tmp_fasto2 } { \dec_o2_fast_o_ok \dec_o2_fast_o } + connect { \tmp_fasto1_ok \tmp_fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o } + connect { \tmp_fast2_ok \tmp_fast2 } { \dec_b_fast_b_ok \dec_b_fast_b } + connect { \tmp_fast1_ok \tmp_fast1 } { \dec_a_fast_a_ok \dec_a_fast_a } + connect { \tmp_spro_ok \tmp_spro } { \dec_o_spr_o_ok \dec_o_spr_o } + connect { \tmp_spr1_ok \tmp_spr1 } { \dec_a_spr_a_ok \dec_a_spr_a } + connect { \tmp_ea_ok \tmp_ea } { \dec_o2_reg_o_ok \dec_o2_reg_o } + connect { \tmp_rego_ok \tmp_rego } { \dec_o_reg_o_ok \dec_o_reg_o } + connect { \tmp_reg3_ok \tmp_reg3 } { \dec_c_reg_c_ok \dec_c_reg_c } + connect { \tmp_reg2_ok \tmp_reg2 } { \dec_b_reg_b_ok \dec_b_reg_b } + connect { \tmp_reg1_ok \tmp_reg1 } { \dec_a_reg_a_ok \dec_a_reg_a } + connect \dec_o2_lk \tmp_tmp_lk + connect \sel_in \dec_out_sel + connect \dec_o_sel_in \dec_out_sel + connect \dec_c_sel_in \dec_in3_sel + connect \dec_b_sel_in \dec_in2_sel + connect \dec_a_sel_in \dec_in1_sel + connect \insn_in$10 \dec_opcode_in + connect \insn_in$9 \dec_opcode_in + connect \insn_in$8 \dec_opcode_in + connect \insn_in$7 \dec_opcode_in + connect \insn_in$6 \dec_opcode_in + connect \tmp_tmp_is_32bit \dec_is_32b + connect \tmp_tmp_input_carry \dec_cry_in + connect { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm } + connect { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm } + connect { \tmp_tmp_oe_ok \tmp_tmp_oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \tmp_tmp_rc_ok \tmp_tmp_rc } { \dec_rc_rc_ok \dec_rc_rc } + connect \tmp_tmp_fn_unit \dec_function_unit + connect \tmp_tmp_insn_type \dec_internal_op + connect \tmp_tmp_cia \cur_pc + connect \tmp_tmp_msr \cur_msr + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_cr_out + connect \dec_cr_in_sel_in \dec_cr_in + connect \dec_oe_sel_in \dec_rc_sel + connect \dec_rc_sel_in \dec_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$5 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \tmp_tmp_insn \dec_opcode_in +end +attribute \src "libresoc.v:10734.1-11881.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30" +attribute \generator "nMigen" +module \dec30 + attribute \src "libresoc.v:11177.3-11213.6" + wire width 8 $0\dec30_asmcode[7:0] + attribute \src "libresoc.v:11325.3-11361.6" + wire $0\dec30_br[0:0] + attribute \src "libresoc.v:11806.3-11842.6" + wire width 3 $0\dec30_cr_in[2:0] + attribute \src "libresoc.v:11843.3-11879.6" + wire width 3 $0\dec30_cr_out[2:0] + attribute \src "libresoc.v:11140.3-11176.6" + wire width 2 $0\dec30_cry_in[1:0] + attribute \src "libresoc.v:11288.3-11324.6" + wire $0\dec30_cry_out[0:0] + attribute \src "libresoc.v:11621.3-11657.6" + wire width 5 $0\dec30_form[4:0] + attribute \src "libresoc.v:10992.3-11028.6" + wire width 12 $0\dec30_function_unit[11:0] + attribute \src "libresoc.v:11658.3-11694.6" + wire width 3 $0\dec30_in1_sel[2:0] + attribute \src "libresoc.v:11695.3-11731.6" + wire width 4 $0\dec30_in2_sel[3:0] + attribute \src "libresoc.v:11732.3-11768.6" + wire width 2 $0\dec30_in3_sel[1:0] + attribute \src "libresoc.v:11399.3-11435.6" + wire width 7 $0\dec30_internal_op[6:0] + attribute \src "libresoc.v:11214.3-11250.6" + wire $0\dec30_inv_a[0:0] + attribute \src "libresoc.v:11251.3-11287.6" + wire $0\dec30_inv_out[0:0] + attribute \src "libresoc.v:11473.3-11509.6" + wire $0\dec30_is_32b[0:0] + attribute \src "libresoc.v:11029.3-11065.6" + wire width 4 $0\dec30_ldst_len[3:0] + attribute \src "libresoc.v:11547.3-11583.6" + wire $0\dec30_lk[0:0] + attribute \src "libresoc.v:11769.3-11805.6" + wire width 2 $0\dec30_out_sel[1:0] + attribute \src "libresoc.v:11103.3-11139.6" + wire width 2 $0\dec30_rc_sel[1:0] + attribute \src "libresoc.v:11436.3-11472.6" + wire $0\dec30_rsrv[0:0] + attribute \src "libresoc.v:11584.3-11620.6" + wire $0\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:11510.3-11546.6" + wire $0\dec30_sgn[0:0] + attribute \src "libresoc.v:11362.3-11398.6" + wire $0\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:11066.3-11102.6" + wire width 2 $0\dec30_upd[1:0] + attribute \src "libresoc.v:10735.7-10735.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:11177.3-11213.6" + wire width 8 $1\dec30_asmcode[7:0] + attribute \src "libresoc.v:11325.3-11361.6" + wire $1\dec30_br[0:0] + attribute \src "libresoc.v:11806.3-11842.6" + wire width 3 $1\dec30_cr_in[2:0] + attribute \src "libresoc.v:11843.3-11879.6" + wire width 3 $1\dec30_cr_out[2:0] + attribute \src "libresoc.v:11140.3-11176.6" + wire width 2 $1\dec30_cry_in[1:0] + attribute \src "libresoc.v:11288.3-11324.6" + wire $1\dec30_cry_out[0:0] + attribute \src "libresoc.v:11621.3-11657.6" + wire width 5 $1\dec30_form[4:0] + attribute \src "libresoc.v:10992.3-11028.6" + wire width 12 $1\dec30_function_unit[11:0] + attribute \src "libresoc.v:11658.3-11694.6" + wire width 3 $1\dec30_in1_sel[2:0] + attribute \src "libresoc.v:11695.3-11731.6" + wire width 4 $1\dec30_in2_sel[3:0] + attribute \src "libresoc.v:11732.3-11768.6" + wire width 2 $1\dec30_in3_sel[1:0] + attribute \src "libresoc.v:11399.3-11435.6" + wire width 7 $1\dec30_internal_op[6:0] + attribute \src "libresoc.v:11214.3-11250.6" + wire $1\dec30_inv_a[0:0] + attribute \src "libresoc.v:11251.3-11287.6" + wire $1\dec30_inv_out[0:0] + attribute \src "libresoc.v:11473.3-11509.6" + wire $1\dec30_is_32b[0:0] + attribute \src "libresoc.v:11029.3-11065.6" + wire width 4 $1\dec30_ldst_len[3:0] + attribute \src "libresoc.v:11547.3-11583.6" + wire $1\dec30_lk[0:0] + attribute \src "libresoc.v:11769.3-11805.6" + wire width 2 $1\dec30_out_sel[1:0] + attribute \src "libresoc.v:11103.3-11139.6" + wire width 2 $1\dec30_rc_sel[1:0] + attribute \src "libresoc.v:11436.3-11472.6" + wire $1\dec30_rsrv[0:0] + attribute \src "libresoc.v:11584.3-11620.6" + wire $1\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:11510.3-11546.6" + wire $1\dec30_sgn[0:0] + attribute \src "libresoc.v:11362.3-11398.6" + wire $1\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:11066.3-11102.6" + wire width 2 $1\dec30_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec30_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec30_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec30_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec30_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec30_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec30_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec30_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec30_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec30_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec30_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec30_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec30_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec30_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec30_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec30_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec30_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec30_upd + attribute \src "libresoc.v:10735.7-10735.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 4 \opcode_switch + attribute \src "libresoc.v:10735.7-10735.20" + process $proc$libresoc.v:10735$381 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:10992.3-11028.6" + process $proc$libresoc.v:10992$357 + assign { } { } + assign { } { } + assign $0\dec30_function_unit[11:0] $1\dec30_function_unit[11:0] + attribute \src "libresoc.v:10993.5-10993.29" + switch \initial + attribute \src "libresoc.v:10993.9-10993.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + case + assign $1\dec30_function_unit[11:0] 12'000000000000 + end + sync always + update \dec30_function_unit $0\dec30_function_unit[11:0] + end + attribute \src "libresoc.v:11029.3-11065.6" + process $proc$libresoc.v:11029$358 + assign { } { } + assign { } { } + assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] + attribute \src "libresoc.v:11030.5-11030.29" + switch \initial + attribute \src "libresoc.v:11030.9-11030.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + case + assign $1\dec30_ldst_len[3:0] 4'0000 + end + sync always + update \dec30_ldst_len $0\dec30_ldst_len[3:0] + end + attribute \src "libresoc.v:11066.3-11102.6" + process $proc$libresoc.v:11066$359 + assign { } { } + assign { } { } + assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] + attribute \src "libresoc.v:11067.5-11067.29" + switch \initial + attribute \src "libresoc.v:11067.9-11067.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + case + assign $1\dec30_upd[1:0] 2'00 + end + sync always + update \dec30_upd $0\dec30_upd[1:0] + end + attribute \src "libresoc.v:11103.3-11139.6" + process $proc$libresoc.v:11103$360 + assign { } { } + assign { } { } + assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] + attribute \src "libresoc.v:11104.5-11104.29" + switch \initial + attribute \src "libresoc.v:11104.9-11104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + case + assign $1\dec30_rc_sel[1:0] 2'00 + end + sync always + update \dec30_rc_sel $0\dec30_rc_sel[1:0] + end + attribute \src "libresoc.v:11140.3-11176.6" + process $proc$libresoc.v:11140$361 + assign { } { } + assign { } { } + assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] + attribute \src "libresoc.v:11141.5-11141.29" + switch \initial + attribute \src "libresoc.v:11141.9-11141.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + case + assign $1\dec30_cry_in[1:0] 2'00 + end + sync always + update \dec30_cry_in $0\dec30_cry_in[1:0] + end + attribute \src "libresoc.v:11177.3-11213.6" + process $proc$libresoc.v:11177$362 + assign { } { } + assign { } { } + assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] + attribute \src "libresoc.v:11178.5-11178.29" + switch \initial + attribute \src "libresoc.v:11178.9-11178.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010110 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010110 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010111 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010111 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010011 + case + assign $1\dec30_asmcode[7:0] 8'00000000 + end + sync always + update \dec30_asmcode $0\dec30_asmcode[7:0] + end + attribute \src "libresoc.v:11214.3-11250.6" + process $proc$libresoc.v:11214$363 + assign { } { } + assign { } { } + assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] + attribute \src "libresoc.v:11215.5-11215.29" + switch \initial + attribute \src "libresoc.v:11215.9-11215.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + case + assign $1\dec30_inv_a[0:0] 1'0 + end + sync always + update \dec30_inv_a $0\dec30_inv_a[0:0] + end + attribute \src "libresoc.v:11251.3-11287.6" + process $proc$libresoc.v:11251$364 + assign { } { } + assign { } { } + assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] + attribute \src "libresoc.v:11252.5-11252.29" + switch \initial + attribute \src "libresoc.v:11252.9-11252.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + case + assign $1\dec30_inv_out[0:0] 1'0 + end + sync always + update \dec30_inv_out $0\dec30_inv_out[0:0] + end + attribute \src "libresoc.v:11288.3-11324.6" + process $proc$libresoc.v:11288$365 + assign { } { } + assign { } { } + assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] + attribute \src "libresoc.v:11289.5-11289.29" + switch \initial + attribute \src "libresoc.v:11289.9-11289.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + case + assign $1\dec30_cry_out[0:0] 1'0 + end + sync always + update \dec30_cry_out $0\dec30_cry_out[0:0] + end + attribute \src "libresoc.v:11325.3-11361.6" + process $proc$libresoc.v:11325$366 + assign { } { } + assign { } { } + assign $0\dec30_br[0:0] $1\dec30_br[0:0] + attribute \src "libresoc.v:11326.5-11326.29" + switch \initial + attribute \src "libresoc.v:11326.9-11326.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + case + assign $1\dec30_br[0:0] 1'0 + end + sync always + update \dec30_br $0\dec30_br[0:0] + end + attribute \src "libresoc.v:11362.3-11398.6" + process $proc$libresoc.v:11362$367 + assign { } { } + assign { } { } + assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:11363.5-11363.29" + switch \initial + attribute \src "libresoc.v:11363.9-11363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + case + assign $1\dec30_sgn_ext[0:0] 1'0 + end + sync always + update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] + end + attribute \src "libresoc.v:11399.3-11435.6" + process $proc$libresoc.v:11399$368 + assign { } { } + assign { } { } + assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] + attribute \src "libresoc.v:11400.5-11400.29" + switch \initial + attribute \src "libresoc.v:11400.9-11400.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + case + assign $1\dec30_internal_op[6:0] 7'0000000 + end + sync always + update \dec30_internal_op $0\dec30_internal_op[6:0] + end + attribute \src "libresoc.v:11436.3-11472.6" + process $proc$libresoc.v:11436$369 + assign { } { } + assign { } { } + assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] + attribute \src "libresoc.v:11437.5-11437.29" + switch \initial + attribute \src "libresoc.v:11437.9-11437.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + case + assign $1\dec30_rsrv[0:0] 1'0 + end + sync always + update \dec30_rsrv $0\dec30_rsrv[0:0] + end + attribute \src "libresoc.v:11473.3-11509.6" + process $proc$libresoc.v:11473$370 + assign { } { } + assign { } { } + assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] + attribute \src "libresoc.v:11474.5-11474.29" + switch \initial + attribute \src "libresoc.v:11474.9-11474.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + case + assign $1\dec30_is_32b[0:0] 1'0 + end + sync always + update \dec30_is_32b $0\dec30_is_32b[0:0] + end + attribute \src "libresoc.v:11510.3-11546.6" + process $proc$libresoc.v:11510$371 + assign { } { } + assign { } { } + assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] + attribute \src "libresoc.v:11511.5-11511.29" + switch \initial + attribute \src "libresoc.v:11511.9-11511.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + case + assign $1\dec30_sgn[0:0] 1'0 + end + sync always + update \dec30_sgn $0\dec30_sgn[0:0] + end + attribute \src "libresoc.v:11547.3-11583.6" + process $proc$libresoc.v:11547$372 + assign { } { } + assign { } { } + assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] + attribute \src "libresoc.v:11548.5-11548.29" + switch \initial + attribute \src "libresoc.v:11548.9-11548.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + case + assign $1\dec30_lk[0:0] 1'0 + end + sync always + update \dec30_lk $0\dec30_lk[0:0] + end + attribute \src "libresoc.v:11584.3-11620.6" + process $proc$libresoc.v:11584$373 + assign { } { } + assign { } { } + assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:11585.5-11585.29" + switch \initial + attribute \src "libresoc.v:11585.9-11585.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + case + assign $1\dec30_sgl_pipe[0:0] 1'0 + end + sync always + update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] + end + attribute \src "libresoc.v:11621.3-11657.6" + process $proc$libresoc.v:11621$374 + assign { } { } + assign { } { } + assign $0\dec30_form[4:0] $1\dec30_form[4:0] + attribute \src "libresoc.v:11622.5-11622.29" + switch \initial + attribute \src "libresoc.v:11622.9-11622.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_form[4:0] 5'10101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_form[4:0] 5'10101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + case + assign $1\dec30_form[4:0] 5'00000 + end + sync always + update \dec30_form $0\dec30_form[4:0] + end + attribute \src "libresoc.v:11658.3-11694.6" + process $proc$libresoc.v:11658$375 + assign { } { } + assign { } { } + assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] + attribute \src "libresoc.v:11659.5-11659.29" + switch \initial + attribute \src "libresoc.v:11659.9-11659.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + case + assign $1\dec30_in1_sel[2:0] 3'000 + end + sync always + update \dec30_in1_sel $0\dec30_in1_sel[2:0] + end + attribute \src "libresoc.v:11695.3-11731.6" + process $proc$libresoc.v:11695$376 + assign { } { } + assign { } { } + assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] + attribute \src "libresoc.v:11696.5-11696.29" + switch \initial + attribute \src "libresoc.v:11696.9-11696.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'0001 + case + assign $1\dec30_in2_sel[3:0] 4'0000 + end + sync always + update \dec30_in2_sel $0\dec30_in2_sel[3:0] + end + attribute \src "libresoc.v:11732.3-11768.6" + process $proc$libresoc.v:11732$377 + assign { } { } + assign { } { } + assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] + attribute \src "libresoc.v:11733.5-11733.29" + switch \initial + attribute \src "libresoc.v:11733.9-11733.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + case + assign $1\dec30_in3_sel[1:0] 2'00 + end + sync always + update \dec30_in3_sel $0\dec30_in3_sel[1:0] + end + attribute \src "libresoc.v:11769.3-11805.6" + process $proc$libresoc.v:11769$378 + assign { } { } + assign { } { } + assign $0\dec30_out_sel[1:0] $1\dec30_out_sel[1:0] + attribute \src "libresoc.v:11770.5-11770.29" + switch \initial + attribute \src "libresoc.v:11770.9-11770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + case + assign $1\dec30_out_sel[1:0] 2'00 + end + sync always + update \dec30_out_sel $0\dec30_out_sel[1:0] + end + attribute \src "libresoc.v:11806.3-11842.6" + process $proc$libresoc.v:11806$379 + assign { } { } + assign { } { } + assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] + attribute \src "libresoc.v:11807.5-11807.29" + switch \initial + attribute \src "libresoc.v:11807.9-11807.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + case + assign $1\dec30_cr_in[2:0] 3'000 + end + sync always + update \dec30_cr_in $0\dec30_cr_in[2:0] + end + attribute \src "libresoc.v:11843.3-11879.6" + process $proc$libresoc.v:11843$380 + assign { } { } + assign { } { } + assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] + attribute \src "libresoc.v:11844.5-11844.29" + switch \initial + attribute \src "libresoc.v:11844.9-11844.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + case + assign $1\dec30_cr_out[2:0] 3'000 + end + sync always + update \dec30_cr_out $0\dec30_cr_out[2:0] + end + connect \opcode_switch \opcode_in [4:1] +end +attribute \src "libresoc.v:11885.1-18255.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31" +attribute \generator "nMigen" +module \dec31 + attribute \src "libresoc.v:16954.3-17014.6" + wire width 8 $0\dec31_asmcode[7:0] + attribute \src "libresoc.v:17808.3-17868.6" + wire $0\dec31_br[0:0] + attribute \src "libresoc.v:17259.3-17319.6" + wire width 3 $0\dec31_cr_in[2:0] + attribute \src "libresoc.v:17320.3-17380.6" + wire width 3 $0\dec31_cr_out[2:0] + attribute \src "libresoc.v:17564.3-17624.6" + wire width 2 $0\dec31_cry_in[1:0] + attribute \src "libresoc.v:17747.3-17807.6" + wire $0\dec31_cry_out[0:0] + attribute \src "libresoc.v:16893.3-16953.6" + wire width 5 $0\dec31_form[4:0] + attribute \src "libresoc.v:16771.3-16831.6" + wire width 12 $0\dec31_function_unit[11:0] + attribute \src "libresoc.v:17015.3-17075.6" + wire width 3 $0\dec31_in1_sel[2:0] + attribute \src "libresoc.v:17076.3-17136.6" + wire width 4 $0\dec31_in2_sel[3:0] + attribute \src "libresoc.v:17137.3-17197.6" + wire width 2 $0\dec31_in3_sel[1:0] + attribute \src "libresoc.v:16832.3-16892.6" + wire width 7 $0\dec31_internal_op[6:0] + attribute \src "libresoc.v:17625.3-17685.6" + wire $0\dec31_inv_a[0:0] + attribute \src "libresoc.v:17686.3-17746.6" + wire $0\dec31_inv_out[0:0] + attribute \src "libresoc.v:17991.3-18051.6" + wire $0\dec31_is_32b[0:0] + attribute \src "libresoc.v:17381.3-17441.6" + wire width 4 $0\dec31_ldst_len[3:0] + attribute \src "libresoc.v:18113.3-18173.6" + wire $0\dec31_lk[0:0] + attribute \src "libresoc.v:17198.3-17258.6" + wire width 2 $0\dec31_out_sel[1:0] + attribute \src "libresoc.v:17503.3-17563.6" + wire width 2 $0\dec31_rc_sel[1:0] + attribute \src "libresoc.v:17930.3-17990.6" + wire $0\dec31_rsrv[0:0] + attribute \src "libresoc.v:18174.3-18234.6" + wire $0\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:18052.3-18112.6" + wire $0\dec31_sgn[0:0] + attribute \src "libresoc.v:17869.3-17929.6" + wire $0\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:17442.3-17502.6" + wire width 2 $0\dec31_upd[1:0] + attribute \src "libresoc.v:11886.7-11886.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:16954.3-17014.6" + wire width 8 $1\dec31_asmcode[7:0] + attribute \src "libresoc.v:17808.3-17868.6" + wire $1\dec31_br[0:0] + attribute \src "libresoc.v:17259.3-17319.6" + wire width 3 $1\dec31_cr_in[2:0] + attribute \src "libresoc.v:17320.3-17380.6" + wire width 3 $1\dec31_cr_out[2:0] + attribute \src "libresoc.v:17564.3-17624.6" + wire width 2 $1\dec31_cry_in[1:0] + attribute \src "libresoc.v:17747.3-17807.6" + wire $1\dec31_cry_out[0:0] + attribute \src "libresoc.v:16893.3-16953.6" + wire width 5 $1\dec31_form[4:0] + attribute \src "libresoc.v:16771.3-16831.6" + wire width 12 $1\dec31_function_unit[11:0] + attribute \src "libresoc.v:17015.3-17075.6" + wire width 3 $1\dec31_in1_sel[2:0] + attribute \src "libresoc.v:17076.3-17136.6" + wire width 4 $1\dec31_in2_sel[3:0] + attribute \src "libresoc.v:17137.3-17197.6" + wire width 2 $1\dec31_in3_sel[1:0] + attribute \src "libresoc.v:16832.3-16892.6" + wire width 7 $1\dec31_internal_op[6:0] + attribute \src "libresoc.v:17625.3-17685.6" + wire $1\dec31_inv_a[0:0] + attribute \src "libresoc.v:17686.3-17746.6" + wire $1\dec31_inv_out[0:0] + attribute \src "libresoc.v:17991.3-18051.6" + wire $1\dec31_is_32b[0:0] + attribute \src "libresoc.v:17381.3-17441.6" + wire width 4 $1\dec31_ldst_len[3:0] + attribute \src "libresoc.v:18113.3-18173.6" + wire $1\dec31_lk[0:0] + attribute \src "libresoc.v:17198.3-17258.6" + wire width 2 $1\dec31_out_sel[1:0] + attribute \src "libresoc.v:17503.3-17563.6" + wire width 2 $1\dec31_rc_sel[1:0] + attribute \src "libresoc.v:17930.3-17990.6" + wire $1\dec31_rsrv[0:0] + attribute \src "libresoc.v:18174.3-18234.6" + wire $1\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:18052.3-18112.6" + wire $1\dec31_sgn[0:0] + attribute \src "libresoc.v:17869.3-17929.6" + wire $1\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:17442.3-17502.6" + wire width 2 $1\dec31_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub0_dec31_dec_sub0_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub0_dec31_dec_sub0_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub0_dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub0_dec31_dec_sub0_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub0_dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub0_dec31_dec_sub0_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub0_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub10_dec31_dec_sub10_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub10_dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub10_dec31_dec_sub10_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub10_dec31_dec_sub10_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub10_dec31_dec_sub10_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub10_dec31_dec_sub10_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub10_dec31_dec_sub10_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub10_dec31_dec_sub10_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub10_dec31_dec_sub10_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub10_dec31_dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub10_dec31_dec_sub10_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub10_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub11_dec31_dec_sub11_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub11_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub11_dec31_dec_sub11_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub11_dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub11_dec31_dec_sub11_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub11_dec31_dec_sub11_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub11_dec31_dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub11_dec31_dec_sub11_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub11_dec31_dec_sub11_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub11_dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub11_dec31_dec_sub11_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub11_dec31_dec_sub11_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub11_dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub11_dec31_dec_sub11_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub11_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub15_dec31_dec_sub15_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub15_dec31_dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub15_dec31_dec_sub15_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub15_dec31_dec_sub15_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub15_dec31_dec_sub15_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub15_dec31_dec_sub15_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub15_dec31_dec_sub15_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub15_dec31_dec_sub15_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub15_dec31_dec_sub15_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub15_dec31_dec_sub15_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub15_dec31_dec_sub15_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub15_dec31_dec_sub15_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub15_dec31_dec_sub15_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub15_dec31_dec_sub15_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub15_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub16_dec31_dec_sub16_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub16_dec31_dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub16_dec31_dec_sub16_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub16_dec31_dec_sub16_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub16_dec31_dec_sub16_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub16_dec31_dec_sub16_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub16_dec31_dec_sub16_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub16_dec31_dec_sub16_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub16_dec31_dec_sub16_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub16_dec31_dec_sub16_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub16_dec31_dec_sub16_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub16_dec31_dec_sub16_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub16_dec31_dec_sub16_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub16_dec31_dec_sub16_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub16_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub18_dec31_dec_sub18_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub18_dec31_dec_sub18_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub18_dec31_dec_sub18_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub18_dec31_dec_sub18_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub18_dec31_dec_sub18_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub18_dec31_dec_sub18_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub18_dec31_dec_sub18_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub18_dec31_dec_sub18_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub18_dec31_dec_sub18_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub18_dec31_dec_sub18_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub18_dec31_dec_sub18_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub18_dec31_dec_sub18_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub18_dec31_dec_sub18_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub18_dec31_dec_sub18_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub18_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub19_dec31_dec_sub19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub19_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub19_dec31_dec_sub19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub19_dec31_dec_sub19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub19_dec31_dec_sub19_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub19_dec31_dec_sub19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub19_dec31_dec_sub19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub19_dec31_dec_sub19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub19_dec31_dec_sub19_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub19_dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub19_dec31_dec_sub19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub19_dec31_dec_sub19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub19_dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub19_dec31_dec_sub19_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub19_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub20_dec31_dec_sub20_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub20_dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub20_dec31_dec_sub20_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub20_dec31_dec_sub20_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub20_dec31_dec_sub20_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub20_dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub20_dec31_dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub20_dec31_dec_sub20_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub20_dec31_dec_sub20_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub20_dec31_dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub20_dec31_dec_sub20_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub20_dec31_dec_sub20_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub20_dec31_dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub20_dec31_dec_sub20_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub20_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub21_dec31_dec_sub21_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub21_dec31_dec_sub21_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub21_dec31_dec_sub21_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub21_dec31_dec_sub21_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub21_dec31_dec_sub21_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub21_dec31_dec_sub21_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub21_dec31_dec_sub21_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub21_dec31_dec_sub21_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub21_dec31_dec_sub21_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub21_dec31_dec_sub21_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub21_dec31_dec_sub21_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub21_dec31_dec_sub21_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub21_dec31_dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub21_dec31_dec_sub21_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub21_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub22_dec31_dec_sub22_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub22_dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub22_dec31_dec_sub22_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub22_dec31_dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub22_dec31_dec_sub22_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub22_dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub22_dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub22_dec31_dec_sub22_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub22_dec31_dec_sub22_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub22_dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub22_dec31_dec_sub22_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub22_dec31_dec_sub22_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub22_dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub22_dec31_dec_sub22_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub22_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub23_dec31_dec_sub23_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub23_dec31_dec_sub23_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub23_dec31_dec_sub23_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub23_dec31_dec_sub23_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub23_dec31_dec_sub23_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub23_dec31_dec_sub23_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub23_dec31_dec_sub23_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub23_dec31_dec_sub23_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub23_dec31_dec_sub23_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub23_dec31_dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub23_dec31_dec_sub23_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub23_dec31_dec_sub23_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub23_dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub23_dec31_dec_sub23_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub23_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub24_dec31_dec_sub24_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub24_dec31_dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub24_dec31_dec_sub24_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub24_dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub24_dec31_dec_sub24_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub24_dec31_dec_sub24_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub24_dec31_dec_sub24_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub24_dec31_dec_sub24_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub24_dec31_dec_sub24_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub24_dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub24_dec31_dec_sub24_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub24_dec31_dec_sub24_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub24_dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub24_dec31_dec_sub24_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub24_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub26_dec31_dec_sub26_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub26_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub26_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub26_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub26_dec31_dec_sub26_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub26_dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub26_dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub26_dec31_dec_sub26_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub26_dec31_dec_sub26_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub26_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub26_dec31_dec_sub26_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub26_dec31_dec_sub26_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub26_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub26_dec31_dec_sub26_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub26_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub27_dec31_dec_sub27_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub27_dec31_dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub27_dec31_dec_sub27_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub27_dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub27_dec31_dec_sub27_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub27_dec31_dec_sub27_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub27_dec31_dec_sub27_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub27_dec31_dec_sub27_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub27_dec31_dec_sub27_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub27_dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub27_dec31_dec_sub27_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub27_dec31_dec_sub27_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub27_dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub27_dec31_dec_sub27_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub27_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub28_dec31_dec_sub28_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub28_dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub28_dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub28_dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub28_dec31_dec_sub28_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub28_dec31_dec_sub28_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub28_dec31_dec_sub28_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub28_dec31_dec_sub28_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub28_dec31_dec_sub28_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub28_dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub28_dec31_dec_sub28_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub28_dec31_dec_sub28_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub28_dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub28_dec31_dec_sub28_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub28_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub4_dec31_dec_sub4_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub4_dec31_dec_sub4_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub4_dec31_dec_sub4_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub4_dec31_dec_sub4_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub4_dec31_dec_sub4_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub4_dec31_dec_sub4_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub4_dec31_dec_sub4_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub4_dec31_dec_sub4_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub4_dec31_dec_sub4_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub4_dec31_dec_sub4_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub4_dec31_dec_sub4_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub4_dec31_dec_sub4_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub4_dec31_dec_sub4_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub4_dec31_dec_sub4_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub4_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub8_dec31_dec_sub8_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub8_dec31_dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub8_dec31_dec_sub8_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub8_dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub8_dec31_dec_sub8_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub8_dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub8_dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub8_dec31_dec_sub8_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub8_dec31_dec_sub8_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub8_dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub8_dec31_dec_sub8_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub8_dec31_dec_sub8_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub8_dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub8_dec31_dec_sub8_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub8_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub9_dec31_dec_sub9_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub9_dec31_dec_sub9_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub9_dec31_dec_sub9_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub9_dec31_dec_sub9_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub9_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub9_dec31_dec_sub9_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub9_opcode_in + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_upd + attribute \src "libresoc.v:11886.7-11886.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:16285.18-16311.4" + cell \dec31_dec_sub0 \dec31_dec_sub0 + connect \dec31_dec_sub0_asmcode \dec31_dec_sub0_dec31_dec_sub0_asmcode + connect \dec31_dec_sub0_br \dec31_dec_sub0_dec31_dec_sub0_br + connect \dec31_dec_sub0_cr_in \dec31_dec_sub0_dec31_dec_sub0_cr_in + connect \dec31_dec_sub0_cr_out \dec31_dec_sub0_dec31_dec_sub0_cr_out + connect \dec31_dec_sub0_cry_in \dec31_dec_sub0_dec31_dec_sub0_cry_in + connect \dec31_dec_sub0_cry_out \dec31_dec_sub0_dec31_dec_sub0_cry_out + connect \dec31_dec_sub0_form \dec31_dec_sub0_dec31_dec_sub0_form + connect \dec31_dec_sub0_function_unit \dec31_dec_sub0_dec31_dec_sub0_function_unit + connect \dec31_dec_sub0_in1_sel \dec31_dec_sub0_dec31_dec_sub0_in1_sel + connect \dec31_dec_sub0_in2_sel \dec31_dec_sub0_dec31_dec_sub0_in2_sel + connect \dec31_dec_sub0_in3_sel \dec31_dec_sub0_dec31_dec_sub0_in3_sel + connect \dec31_dec_sub0_internal_op \dec31_dec_sub0_dec31_dec_sub0_internal_op + connect \dec31_dec_sub0_inv_a \dec31_dec_sub0_dec31_dec_sub0_inv_a + connect \dec31_dec_sub0_inv_out \dec31_dec_sub0_dec31_dec_sub0_inv_out + connect \dec31_dec_sub0_is_32b \dec31_dec_sub0_dec31_dec_sub0_is_32b + connect \dec31_dec_sub0_ldst_len \dec31_dec_sub0_dec31_dec_sub0_ldst_len + connect \dec31_dec_sub0_lk \dec31_dec_sub0_dec31_dec_sub0_lk + connect \dec31_dec_sub0_out_sel \dec31_dec_sub0_dec31_dec_sub0_out_sel + connect \dec31_dec_sub0_rc_sel \dec31_dec_sub0_dec31_dec_sub0_rc_sel + connect \dec31_dec_sub0_rsrv \dec31_dec_sub0_dec31_dec_sub0_rsrv + connect \dec31_dec_sub0_sgl_pipe \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + connect \dec31_dec_sub0_sgn \dec31_dec_sub0_dec31_dec_sub0_sgn + connect \dec31_dec_sub0_sgn_ext \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + connect \dec31_dec_sub0_upd \dec31_dec_sub0_dec31_dec_sub0_upd + connect \opcode_in \dec31_dec_sub0_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16312.19-16338.4" + cell \dec31_dec_sub10 \dec31_dec_sub10 + connect \dec31_dec_sub10_asmcode \dec31_dec_sub10_dec31_dec_sub10_asmcode + connect \dec31_dec_sub10_br \dec31_dec_sub10_dec31_dec_sub10_br + connect \dec31_dec_sub10_cr_in \dec31_dec_sub10_dec31_dec_sub10_cr_in + connect \dec31_dec_sub10_cr_out \dec31_dec_sub10_dec31_dec_sub10_cr_out + connect \dec31_dec_sub10_cry_in \dec31_dec_sub10_dec31_dec_sub10_cry_in + connect \dec31_dec_sub10_cry_out \dec31_dec_sub10_dec31_dec_sub10_cry_out + connect \dec31_dec_sub10_form \dec31_dec_sub10_dec31_dec_sub10_form + connect \dec31_dec_sub10_function_unit \dec31_dec_sub10_dec31_dec_sub10_function_unit + connect \dec31_dec_sub10_in1_sel \dec31_dec_sub10_dec31_dec_sub10_in1_sel + connect \dec31_dec_sub10_in2_sel \dec31_dec_sub10_dec31_dec_sub10_in2_sel + connect \dec31_dec_sub10_in3_sel \dec31_dec_sub10_dec31_dec_sub10_in3_sel + connect \dec31_dec_sub10_internal_op \dec31_dec_sub10_dec31_dec_sub10_internal_op + connect \dec31_dec_sub10_inv_a \dec31_dec_sub10_dec31_dec_sub10_inv_a + connect \dec31_dec_sub10_inv_out \dec31_dec_sub10_dec31_dec_sub10_inv_out + connect \dec31_dec_sub10_is_32b \dec31_dec_sub10_dec31_dec_sub10_is_32b + connect \dec31_dec_sub10_ldst_len \dec31_dec_sub10_dec31_dec_sub10_ldst_len + connect \dec31_dec_sub10_lk \dec31_dec_sub10_dec31_dec_sub10_lk + connect \dec31_dec_sub10_out_sel \dec31_dec_sub10_dec31_dec_sub10_out_sel + connect \dec31_dec_sub10_rc_sel \dec31_dec_sub10_dec31_dec_sub10_rc_sel + connect \dec31_dec_sub10_rsrv \dec31_dec_sub10_dec31_dec_sub10_rsrv + connect \dec31_dec_sub10_sgl_pipe \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + connect \dec31_dec_sub10_sgn \dec31_dec_sub10_dec31_dec_sub10_sgn + connect \dec31_dec_sub10_sgn_ext \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + connect \dec31_dec_sub10_upd \dec31_dec_sub10_dec31_dec_sub10_upd + connect \opcode_in \dec31_dec_sub10_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16339.19-16365.4" + cell \dec31_dec_sub11 \dec31_dec_sub11 + connect \dec31_dec_sub11_asmcode \dec31_dec_sub11_dec31_dec_sub11_asmcode + connect \dec31_dec_sub11_br \dec31_dec_sub11_dec31_dec_sub11_br + connect \dec31_dec_sub11_cr_in \dec31_dec_sub11_dec31_dec_sub11_cr_in + connect \dec31_dec_sub11_cr_out \dec31_dec_sub11_dec31_dec_sub11_cr_out + connect \dec31_dec_sub11_cry_in \dec31_dec_sub11_dec31_dec_sub11_cry_in + connect \dec31_dec_sub11_cry_out \dec31_dec_sub11_dec31_dec_sub11_cry_out + connect \dec31_dec_sub11_form \dec31_dec_sub11_dec31_dec_sub11_form + connect \dec31_dec_sub11_function_unit \dec31_dec_sub11_dec31_dec_sub11_function_unit + connect \dec31_dec_sub11_in1_sel \dec31_dec_sub11_dec31_dec_sub11_in1_sel + connect \dec31_dec_sub11_in2_sel \dec31_dec_sub11_dec31_dec_sub11_in2_sel + connect \dec31_dec_sub11_in3_sel \dec31_dec_sub11_dec31_dec_sub11_in3_sel + connect \dec31_dec_sub11_internal_op \dec31_dec_sub11_dec31_dec_sub11_internal_op + connect \dec31_dec_sub11_inv_a \dec31_dec_sub11_dec31_dec_sub11_inv_a + connect \dec31_dec_sub11_inv_out \dec31_dec_sub11_dec31_dec_sub11_inv_out + connect \dec31_dec_sub11_is_32b \dec31_dec_sub11_dec31_dec_sub11_is_32b + connect \dec31_dec_sub11_ldst_len \dec31_dec_sub11_dec31_dec_sub11_ldst_len + connect \dec31_dec_sub11_lk \dec31_dec_sub11_dec31_dec_sub11_lk + connect \dec31_dec_sub11_out_sel \dec31_dec_sub11_dec31_dec_sub11_out_sel + connect \dec31_dec_sub11_rc_sel \dec31_dec_sub11_dec31_dec_sub11_rc_sel + connect \dec31_dec_sub11_rsrv \dec31_dec_sub11_dec31_dec_sub11_rsrv + connect \dec31_dec_sub11_sgl_pipe \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + connect \dec31_dec_sub11_sgn \dec31_dec_sub11_dec31_dec_sub11_sgn + connect \dec31_dec_sub11_sgn_ext \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + connect \dec31_dec_sub11_upd \dec31_dec_sub11_dec31_dec_sub11_upd + connect \opcode_in \dec31_dec_sub11_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16366.19-16392.4" + cell \dec31_dec_sub15 \dec31_dec_sub15 + connect \dec31_dec_sub15_asmcode \dec31_dec_sub15_dec31_dec_sub15_asmcode + connect \dec31_dec_sub15_br \dec31_dec_sub15_dec31_dec_sub15_br + connect \dec31_dec_sub15_cr_in \dec31_dec_sub15_dec31_dec_sub15_cr_in + connect \dec31_dec_sub15_cr_out \dec31_dec_sub15_dec31_dec_sub15_cr_out + connect \dec31_dec_sub15_cry_in \dec31_dec_sub15_dec31_dec_sub15_cry_in + connect \dec31_dec_sub15_cry_out \dec31_dec_sub15_dec31_dec_sub15_cry_out + connect \dec31_dec_sub15_form \dec31_dec_sub15_dec31_dec_sub15_form + connect \dec31_dec_sub15_function_unit \dec31_dec_sub15_dec31_dec_sub15_function_unit + connect \dec31_dec_sub15_in1_sel \dec31_dec_sub15_dec31_dec_sub15_in1_sel + connect \dec31_dec_sub15_in2_sel \dec31_dec_sub15_dec31_dec_sub15_in2_sel + connect \dec31_dec_sub15_in3_sel \dec31_dec_sub15_dec31_dec_sub15_in3_sel + connect \dec31_dec_sub15_internal_op \dec31_dec_sub15_dec31_dec_sub15_internal_op + connect \dec31_dec_sub15_inv_a \dec31_dec_sub15_dec31_dec_sub15_inv_a + connect \dec31_dec_sub15_inv_out \dec31_dec_sub15_dec31_dec_sub15_inv_out + connect \dec31_dec_sub15_is_32b \dec31_dec_sub15_dec31_dec_sub15_is_32b + connect \dec31_dec_sub15_ldst_len \dec31_dec_sub15_dec31_dec_sub15_ldst_len + connect \dec31_dec_sub15_lk \dec31_dec_sub15_dec31_dec_sub15_lk + connect \dec31_dec_sub15_out_sel \dec31_dec_sub15_dec31_dec_sub15_out_sel + connect \dec31_dec_sub15_rc_sel \dec31_dec_sub15_dec31_dec_sub15_rc_sel + connect \dec31_dec_sub15_rsrv \dec31_dec_sub15_dec31_dec_sub15_rsrv + connect \dec31_dec_sub15_sgl_pipe \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + connect \dec31_dec_sub15_sgn \dec31_dec_sub15_dec31_dec_sub15_sgn + connect \dec31_dec_sub15_sgn_ext \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + connect \dec31_dec_sub15_upd \dec31_dec_sub15_dec31_dec_sub15_upd + connect \opcode_in \dec31_dec_sub15_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16393.19-16419.4" + cell \dec31_dec_sub16 \dec31_dec_sub16 + connect \dec31_dec_sub16_asmcode \dec31_dec_sub16_dec31_dec_sub16_asmcode + connect \dec31_dec_sub16_br \dec31_dec_sub16_dec31_dec_sub16_br + connect \dec31_dec_sub16_cr_in \dec31_dec_sub16_dec31_dec_sub16_cr_in + connect \dec31_dec_sub16_cr_out \dec31_dec_sub16_dec31_dec_sub16_cr_out + connect \dec31_dec_sub16_cry_in \dec31_dec_sub16_dec31_dec_sub16_cry_in + connect \dec31_dec_sub16_cry_out \dec31_dec_sub16_dec31_dec_sub16_cry_out + connect \dec31_dec_sub16_form \dec31_dec_sub16_dec31_dec_sub16_form + connect \dec31_dec_sub16_function_unit \dec31_dec_sub16_dec31_dec_sub16_function_unit + connect \dec31_dec_sub16_in1_sel \dec31_dec_sub16_dec31_dec_sub16_in1_sel + connect \dec31_dec_sub16_in2_sel \dec31_dec_sub16_dec31_dec_sub16_in2_sel + connect \dec31_dec_sub16_in3_sel \dec31_dec_sub16_dec31_dec_sub16_in3_sel + connect \dec31_dec_sub16_internal_op \dec31_dec_sub16_dec31_dec_sub16_internal_op + connect \dec31_dec_sub16_inv_a \dec31_dec_sub16_dec31_dec_sub16_inv_a + connect \dec31_dec_sub16_inv_out \dec31_dec_sub16_dec31_dec_sub16_inv_out + connect \dec31_dec_sub16_is_32b \dec31_dec_sub16_dec31_dec_sub16_is_32b + connect \dec31_dec_sub16_ldst_len \dec31_dec_sub16_dec31_dec_sub16_ldst_len + connect \dec31_dec_sub16_lk \dec31_dec_sub16_dec31_dec_sub16_lk + connect \dec31_dec_sub16_out_sel \dec31_dec_sub16_dec31_dec_sub16_out_sel + connect \dec31_dec_sub16_rc_sel \dec31_dec_sub16_dec31_dec_sub16_rc_sel + connect \dec31_dec_sub16_rsrv \dec31_dec_sub16_dec31_dec_sub16_rsrv + connect \dec31_dec_sub16_sgl_pipe \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + connect \dec31_dec_sub16_sgn \dec31_dec_sub16_dec31_dec_sub16_sgn + connect \dec31_dec_sub16_sgn_ext \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + connect \dec31_dec_sub16_upd \dec31_dec_sub16_dec31_dec_sub16_upd + connect \opcode_in \dec31_dec_sub16_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16420.19-16446.4" + cell \dec31_dec_sub18 \dec31_dec_sub18 + connect \dec31_dec_sub18_asmcode \dec31_dec_sub18_dec31_dec_sub18_asmcode + connect \dec31_dec_sub18_br \dec31_dec_sub18_dec31_dec_sub18_br + connect \dec31_dec_sub18_cr_in \dec31_dec_sub18_dec31_dec_sub18_cr_in + connect \dec31_dec_sub18_cr_out \dec31_dec_sub18_dec31_dec_sub18_cr_out + connect \dec31_dec_sub18_cry_in \dec31_dec_sub18_dec31_dec_sub18_cry_in + connect \dec31_dec_sub18_cry_out \dec31_dec_sub18_dec31_dec_sub18_cry_out + connect \dec31_dec_sub18_form \dec31_dec_sub18_dec31_dec_sub18_form + connect \dec31_dec_sub18_function_unit \dec31_dec_sub18_dec31_dec_sub18_function_unit + connect \dec31_dec_sub18_in1_sel \dec31_dec_sub18_dec31_dec_sub18_in1_sel + connect \dec31_dec_sub18_in2_sel \dec31_dec_sub18_dec31_dec_sub18_in2_sel + connect \dec31_dec_sub18_in3_sel \dec31_dec_sub18_dec31_dec_sub18_in3_sel + connect \dec31_dec_sub18_internal_op \dec31_dec_sub18_dec31_dec_sub18_internal_op + connect \dec31_dec_sub18_inv_a \dec31_dec_sub18_dec31_dec_sub18_inv_a + connect \dec31_dec_sub18_inv_out \dec31_dec_sub18_dec31_dec_sub18_inv_out + connect \dec31_dec_sub18_is_32b \dec31_dec_sub18_dec31_dec_sub18_is_32b + connect \dec31_dec_sub18_ldst_len \dec31_dec_sub18_dec31_dec_sub18_ldst_len + connect \dec31_dec_sub18_lk \dec31_dec_sub18_dec31_dec_sub18_lk + connect \dec31_dec_sub18_out_sel \dec31_dec_sub18_dec31_dec_sub18_out_sel + connect \dec31_dec_sub18_rc_sel \dec31_dec_sub18_dec31_dec_sub18_rc_sel + connect \dec31_dec_sub18_rsrv \dec31_dec_sub18_dec31_dec_sub18_rsrv + connect \dec31_dec_sub18_sgl_pipe \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + connect \dec31_dec_sub18_sgn \dec31_dec_sub18_dec31_dec_sub18_sgn + connect \dec31_dec_sub18_sgn_ext \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + connect \dec31_dec_sub18_upd \dec31_dec_sub18_dec31_dec_sub18_upd + connect \opcode_in \dec31_dec_sub18_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16447.19-16473.4" + cell \dec31_dec_sub19 \dec31_dec_sub19 + connect \dec31_dec_sub19_asmcode \dec31_dec_sub19_dec31_dec_sub19_asmcode + connect \dec31_dec_sub19_br \dec31_dec_sub19_dec31_dec_sub19_br + connect \dec31_dec_sub19_cr_in \dec31_dec_sub19_dec31_dec_sub19_cr_in + connect \dec31_dec_sub19_cr_out \dec31_dec_sub19_dec31_dec_sub19_cr_out + connect \dec31_dec_sub19_cry_in \dec31_dec_sub19_dec31_dec_sub19_cry_in + connect \dec31_dec_sub19_cry_out \dec31_dec_sub19_dec31_dec_sub19_cry_out + connect \dec31_dec_sub19_form \dec31_dec_sub19_dec31_dec_sub19_form + connect \dec31_dec_sub19_function_unit \dec31_dec_sub19_dec31_dec_sub19_function_unit + connect \dec31_dec_sub19_in1_sel \dec31_dec_sub19_dec31_dec_sub19_in1_sel + connect \dec31_dec_sub19_in2_sel \dec31_dec_sub19_dec31_dec_sub19_in2_sel + connect \dec31_dec_sub19_in3_sel \dec31_dec_sub19_dec31_dec_sub19_in3_sel + connect \dec31_dec_sub19_internal_op \dec31_dec_sub19_dec31_dec_sub19_internal_op + connect \dec31_dec_sub19_inv_a \dec31_dec_sub19_dec31_dec_sub19_inv_a + connect \dec31_dec_sub19_inv_out \dec31_dec_sub19_dec31_dec_sub19_inv_out + connect \dec31_dec_sub19_is_32b \dec31_dec_sub19_dec31_dec_sub19_is_32b + connect \dec31_dec_sub19_ldst_len \dec31_dec_sub19_dec31_dec_sub19_ldst_len + connect \dec31_dec_sub19_lk \dec31_dec_sub19_dec31_dec_sub19_lk + connect \dec31_dec_sub19_out_sel \dec31_dec_sub19_dec31_dec_sub19_out_sel + connect \dec31_dec_sub19_rc_sel \dec31_dec_sub19_dec31_dec_sub19_rc_sel + connect \dec31_dec_sub19_rsrv \dec31_dec_sub19_dec31_dec_sub19_rsrv + connect \dec31_dec_sub19_sgl_pipe \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe + connect \dec31_dec_sub19_sgn \dec31_dec_sub19_dec31_dec_sub19_sgn + connect \dec31_dec_sub19_sgn_ext \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + connect \dec31_dec_sub19_upd \dec31_dec_sub19_dec31_dec_sub19_upd + connect \opcode_in \dec31_dec_sub19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16474.19-16500.4" + cell \dec31_dec_sub20 \dec31_dec_sub20 + connect \dec31_dec_sub20_asmcode \dec31_dec_sub20_dec31_dec_sub20_asmcode + connect \dec31_dec_sub20_br \dec31_dec_sub20_dec31_dec_sub20_br + connect \dec31_dec_sub20_cr_in \dec31_dec_sub20_dec31_dec_sub20_cr_in + connect \dec31_dec_sub20_cr_out \dec31_dec_sub20_dec31_dec_sub20_cr_out + connect \dec31_dec_sub20_cry_in \dec31_dec_sub20_dec31_dec_sub20_cry_in + connect \dec31_dec_sub20_cry_out \dec31_dec_sub20_dec31_dec_sub20_cry_out + connect \dec31_dec_sub20_form \dec31_dec_sub20_dec31_dec_sub20_form + connect \dec31_dec_sub20_function_unit \dec31_dec_sub20_dec31_dec_sub20_function_unit + connect \dec31_dec_sub20_in1_sel \dec31_dec_sub20_dec31_dec_sub20_in1_sel + connect \dec31_dec_sub20_in2_sel \dec31_dec_sub20_dec31_dec_sub20_in2_sel + connect \dec31_dec_sub20_in3_sel \dec31_dec_sub20_dec31_dec_sub20_in3_sel + connect \dec31_dec_sub20_internal_op \dec31_dec_sub20_dec31_dec_sub20_internal_op + connect \dec31_dec_sub20_inv_a \dec31_dec_sub20_dec31_dec_sub20_inv_a + connect \dec31_dec_sub20_inv_out \dec31_dec_sub20_dec31_dec_sub20_inv_out + connect \dec31_dec_sub20_is_32b \dec31_dec_sub20_dec31_dec_sub20_is_32b + connect \dec31_dec_sub20_ldst_len \dec31_dec_sub20_dec31_dec_sub20_ldst_len + connect \dec31_dec_sub20_lk \dec31_dec_sub20_dec31_dec_sub20_lk + connect \dec31_dec_sub20_out_sel \dec31_dec_sub20_dec31_dec_sub20_out_sel + connect \dec31_dec_sub20_rc_sel \dec31_dec_sub20_dec31_dec_sub20_rc_sel + connect \dec31_dec_sub20_rsrv \dec31_dec_sub20_dec31_dec_sub20_rsrv + connect \dec31_dec_sub20_sgl_pipe \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + connect \dec31_dec_sub20_sgn \dec31_dec_sub20_dec31_dec_sub20_sgn + connect \dec31_dec_sub20_sgn_ext \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + connect \dec31_dec_sub20_upd \dec31_dec_sub20_dec31_dec_sub20_upd + connect \opcode_in \dec31_dec_sub20_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16501.19-16527.4" + cell \dec31_dec_sub21 \dec31_dec_sub21 + connect \dec31_dec_sub21_asmcode \dec31_dec_sub21_dec31_dec_sub21_asmcode + connect \dec31_dec_sub21_br \dec31_dec_sub21_dec31_dec_sub21_br + connect \dec31_dec_sub21_cr_in \dec31_dec_sub21_dec31_dec_sub21_cr_in + connect \dec31_dec_sub21_cr_out \dec31_dec_sub21_dec31_dec_sub21_cr_out + connect \dec31_dec_sub21_cry_in \dec31_dec_sub21_dec31_dec_sub21_cry_in + connect \dec31_dec_sub21_cry_out \dec31_dec_sub21_dec31_dec_sub21_cry_out + connect \dec31_dec_sub21_form \dec31_dec_sub21_dec31_dec_sub21_form + connect \dec31_dec_sub21_function_unit \dec31_dec_sub21_dec31_dec_sub21_function_unit + connect \dec31_dec_sub21_in1_sel \dec31_dec_sub21_dec31_dec_sub21_in1_sel + connect \dec31_dec_sub21_in2_sel \dec31_dec_sub21_dec31_dec_sub21_in2_sel + connect \dec31_dec_sub21_in3_sel \dec31_dec_sub21_dec31_dec_sub21_in3_sel + connect \dec31_dec_sub21_internal_op \dec31_dec_sub21_dec31_dec_sub21_internal_op + connect \dec31_dec_sub21_inv_a \dec31_dec_sub21_dec31_dec_sub21_inv_a + connect \dec31_dec_sub21_inv_out \dec31_dec_sub21_dec31_dec_sub21_inv_out + connect \dec31_dec_sub21_is_32b \dec31_dec_sub21_dec31_dec_sub21_is_32b + connect \dec31_dec_sub21_ldst_len \dec31_dec_sub21_dec31_dec_sub21_ldst_len + connect \dec31_dec_sub21_lk \dec31_dec_sub21_dec31_dec_sub21_lk + connect \dec31_dec_sub21_out_sel \dec31_dec_sub21_dec31_dec_sub21_out_sel + connect \dec31_dec_sub21_rc_sel \dec31_dec_sub21_dec31_dec_sub21_rc_sel + connect \dec31_dec_sub21_rsrv \dec31_dec_sub21_dec31_dec_sub21_rsrv + connect \dec31_dec_sub21_sgl_pipe \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + connect \dec31_dec_sub21_sgn \dec31_dec_sub21_dec31_dec_sub21_sgn + connect \dec31_dec_sub21_sgn_ext \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + connect \dec31_dec_sub21_upd \dec31_dec_sub21_dec31_dec_sub21_upd + connect \opcode_in \dec31_dec_sub21_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16528.19-16554.4" + cell \dec31_dec_sub22 \dec31_dec_sub22 + connect \dec31_dec_sub22_asmcode \dec31_dec_sub22_dec31_dec_sub22_asmcode + connect \dec31_dec_sub22_br \dec31_dec_sub22_dec31_dec_sub22_br + connect \dec31_dec_sub22_cr_in \dec31_dec_sub22_dec31_dec_sub22_cr_in + connect \dec31_dec_sub22_cr_out \dec31_dec_sub22_dec31_dec_sub22_cr_out + connect \dec31_dec_sub22_cry_in \dec31_dec_sub22_dec31_dec_sub22_cry_in + connect \dec31_dec_sub22_cry_out \dec31_dec_sub22_dec31_dec_sub22_cry_out + connect \dec31_dec_sub22_form \dec31_dec_sub22_dec31_dec_sub22_form + connect \dec31_dec_sub22_function_unit \dec31_dec_sub22_dec31_dec_sub22_function_unit + connect \dec31_dec_sub22_in1_sel \dec31_dec_sub22_dec31_dec_sub22_in1_sel + connect \dec31_dec_sub22_in2_sel \dec31_dec_sub22_dec31_dec_sub22_in2_sel + connect \dec31_dec_sub22_in3_sel \dec31_dec_sub22_dec31_dec_sub22_in3_sel + connect \dec31_dec_sub22_internal_op \dec31_dec_sub22_dec31_dec_sub22_internal_op + connect \dec31_dec_sub22_inv_a \dec31_dec_sub22_dec31_dec_sub22_inv_a + connect \dec31_dec_sub22_inv_out \dec31_dec_sub22_dec31_dec_sub22_inv_out + connect \dec31_dec_sub22_is_32b \dec31_dec_sub22_dec31_dec_sub22_is_32b + connect \dec31_dec_sub22_ldst_len \dec31_dec_sub22_dec31_dec_sub22_ldst_len + connect \dec31_dec_sub22_lk \dec31_dec_sub22_dec31_dec_sub22_lk + connect \dec31_dec_sub22_out_sel \dec31_dec_sub22_dec31_dec_sub22_out_sel + connect \dec31_dec_sub22_rc_sel \dec31_dec_sub22_dec31_dec_sub22_rc_sel + connect \dec31_dec_sub22_rsrv \dec31_dec_sub22_dec31_dec_sub22_rsrv + connect \dec31_dec_sub22_sgl_pipe \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + connect \dec31_dec_sub22_sgn \dec31_dec_sub22_dec31_dec_sub22_sgn + connect \dec31_dec_sub22_sgn_ext \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + connect \dec31_dec_sub22_upd \dec31_dec_sub22_dec31_dec_sub22_upd + connect \opcode_in \dec31_dec_sub22_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16555.19-16581.4" + cell \dec31_dec_sub23 \dec31_dec_sub23 + connect \dec31_dec_sub23_asmcode \dec31_dec_sub23_dec31_dec_sub23_asmcode + connect \dec31_dec_sub23_br \dec31_dec_sub23_dec31_dec_sub23_br + connect \dec31_dec_sub23_cr_in \dec31_dec_sub23_dec31_dec_sub23_cr_in + connect \dec31_dec_sub23_cr_out \dec31_dec_sub23_dec31_dec_sub23_cr_out + connect \dec31_dec_sub23_cry_in \dec31_dec_sub23_dec31_dec_sub23_cry_in + connect \dec31_dec_sub23_cry_out \dec31_dec_sub23_dec31_dec_sub23_cry_out + connect \dec31_dec_sub23_form \dec31_dec_sub23_dec31_dec_sub23_form + connect \dec31_dec_sub23_function_unit \dec31_dec_sub23_dec31_dec_sub23_function_unit + connect \dec31_dec_sub23_in1_sel \dec31_dec_sub23_dec31_dec_sub23_in1_sel + connect \dec31_dec_sub23_in2_sel \dec31_dec_sub23_dec31_dec_sub23_in2_sel + connect \dec31_dec_sub23_in3_sel \dec31_dec_sub23_dec31_dec_sub23_in3_sel + connect \dec31_dec_sub23_internal_op \dec31_dec_sub23_dec31_dec_sub23_internal_op + connect \dec31_dec_sub23_inv_a \dec31_dec_sub23_dec31_dec_sub23_inv_a + connect \dec31_dec_sub23_inv_out \dec31_dec_sub23_dec31_dec_sub23_inv_out + connect \dec31_dec_sub23_is_32b \dec31_dec_sub23_dec31_dec_sub23_is_32b + connect \dec31_dec_sub23_ldst_len \dec31_dec_sub23_dec31_dec_sub23_ldst_len + connect \dec31_dec_sub23_lk \dec31_dec_sub23_dec31_dec_sub23_lk + connect \dec31_dec_sub23_out_sel \dec31_dec_sub23_dec31_dec_sub23_out_sel + connect \dec31_dec_sub23_rc_sel \dec31_dec_sub23_dec31_dec_sub23_rc_sel + connect \dec31_dec_sub23_rsrv \dec31_dec_sub23_dec31_dec_sub23_rsrv + connect \dec31_dec_sub23_sgl_pipe \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + connect \dec31_dec_sub23_sgn \dec31_dec_sub23_dec31_dec_sub23_sgn + connect \dec31_dec_sub23_sgn_ext \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + connect \dec31_dec_sub23_upd \dec31_dec_sub23_dec31_dec_sub23_upd + connect \opcode_in \dec31_dec_sub23_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16582.19-16608.4" + cell \dec31_dec_sub24 \dec31_dec_sub24 + connect \dec31_dec_sub24_asmcode \dec31_dec_sub24_dec31_dec_sub24_asmcode + connect \dec31_dec_sub24_br \dec31_dec_sub24_dec31_dec_sub24_br + connect \dec31_dec_sub24_cr_in \dec31_dec_sub24_dec31_dec_sub24_cr_in + connect \dec31_dec_sub24_cr_out \dec31_dec_sub24_dec31_dec_sub24_cr_out + connect \dec31_dec_sub24_cry_in \dec31_dec_sub24_dec31_dec_sub24_cry_in + connect \dec31_dec_sub24_cry_out \dec31_dec_sub24_dec31_dec_sub24_cry_out + connect \dec31_dec_sub24_form \dec31_dec_sub24_dec31_dec_sub24_form + connect \dec31_dec_sub24_function_unit \dec31_dec_sub24_dec31_dec_sub24_function_unit + connect \dec31_dec_sub24_in1_sel \dec31_dec_sub24_dec31_dec_sub24_in1_sel + connect \dec31_dec_sub24_in2_sel \dec31_dec_sub24_dec31_dec_sub24_in2_sel + connect \dec31_dec_sub24_in3_sel \dec31_dec_sub24_dec31_dec_sub24_in3_sel + connect \dec31_dec_sub24_internal_op \dec31_dec_sub24_dec31_dec_sub24_internal_op + connect \dec31_dec_sub24_inv_a \dec31_dec_sub24_dec31_dec_sub24_inv_a + connect \dec31_dec_sub24_inv_out \dec31_dec_sub24_dec31_dec_sub24_inv_out + connect \dec31_dec_sub24_is_32b \dec31_dec_sub24_dec31_dec_sub24_is_32b + connect \dec31_dec_sub24_ldst_len \dec31_dec_sub24_dec31_dec_sub24_ldst_len + connect \dec31_dec_sub24_lk \dec31_dec_sub24_dec31_dec_sub24_lk + connect \dec31_dec_sub24_out_sel \dec31_dec_sub24_dec31_dec_sub24_out_sel + connect \dec31_dec_sub24_rc_sel \dec31_dec_sub24_dec31_dec_sub24_rc_sel + connect \dec31_dec_sub24_rsrv \dec31_dec_sub24_dec31_dec_sub24_rsrv + connect \dec31_dec_sub24_sgl_pipe \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + connect \dec31_dec_sub24_sgn \dec31_dec_sub24_dec31_dec_sub24_sgn + connect \dec31_dec_sub24_sgn_ext \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + connect \dec31_dec_sub24_upd \dec31_dec_sub24_dec31_dec_sub24_upd + connect \opcode_in \dec31_dec_sub24_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16609.19-16635.4" + cell \dec31_dec_sub26 \dec31_dec_sub26 + connect \dec31_dec_sub26_asmcode \dec31_dec_sub26_dec31_dec_sub26_asmcode + connect \dec31_dec_sub26_br \dec31_dec_sub26_dec31_dec_sub26_br + connect \dec31_dec_sub26_cr_in \dec31_dec_sub26_dec31_dec_sub26_cr_in + connect \dec31_dec_sub26_cr_out \dec31_dec_sub26_dec31_dec_sub26_cr_out + connect \dec31_dec_sub26_cry_in \dec31_dec_sub26_dec31_dec_sub26_cry_in + connect \dec31_dec_sub26_cry_out \dec31_dec_sub26_dec31_dec_sub26_cry_out + connect \dec31_dec_sub26_form \dec31_dec_sub26_dec31_dec_sub26_form + connect \dec31_dec_sub26_function_unit \dec31_dec_sub26_dec31_dec_sub26_function_unit + connect \dec31_dec_sub26_in1_sel \dec31_dec_sub26_dec31_dec_sub26_in1_sel + connect \dec31_dec_sub26_in2_sel \dec31_dec_sub26_dec31_dec_sub26_in2_sel + connect \dec31_dec_sub26_in3_sel \dec31_dec_sub26_dec31_dec_sub26_in3_sel + connect \dec31_dec_sub26_internal_op \dec31_dec_sub26_dec31_dec_sub26_internal_op + connect \dec31_dec_sub26_inv_a \dec31_dec_sub26_dec31_dec_sub26_inv_a + connect \dec31_dec_sub26_inv_out \dec31_dec_sub26_dec31_dec_sub26_inv_out + connect \dec31_dec_sub26_is_32b \dec31_dec_sub26_dec31_dec_sub26_is_32b + connect \dec31_dec_sub26_ldst_len \dec31_dec_sub26_dec31_dec_sub26_ldst_len + connect \dec31_dec_sub26_lk \dec31_dec_sub26_dec31_dec_sub26_lk + connect \dec31_dec_sub26_out_sel \dec31_dec_sub26_dec31_dec_sub26_out_sel + connect \dec31_dec_sub26_rc_sel \dec31_dec_sub26_dec31_dec_sub26_rc_sel + connect \dec31_dec_sub26_rsrv \dec31_dec_sub26_dec31_dec_sub26_rsrv + connect \dec31_dec_sub26_sgl_pipe \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe + connect \dec31_dec_sub26_sgn \dec31_dec_sub26_dec31_dec_sub26_sgn + connect \dec31_dec_sub26_sgn_ext \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + connect \dec31_dec_sub26_upd \dec31_dec_sub26_dec31_dec_sub26_upd + connect \opcode_in \dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16636.19-16662.4" + cell \dec31_dec_sub27 \dec31_dec_sub27 + connect \dec31_dec_sub27_asmcode \dec31_dec_sub27_dec31_dec_sub27_asmcode + connect \dec31_dec_sub27_br \dec31_dec_sub27_dec31_dec_sub27_br + connect \dec31_dec_sub27_cr_in \dec31_dec_sub27_dec31_dec_sub27_cr_in + connect \dec31_dec_sub27_cr_out \dec31_dec_sub27_dec31_dec_sub27_cr_out + connect \dec31_dec_sub27_cry_in \dec31_dec_sub27_dec31_dec_sub27_cry_in + connect \dec31_dec_sub27_cry_out \dec31_dec_sub27_dec31_dec_sub27_cry_out + connect \dec31_dec_sub27_form \dec31_dec_sub27_dec31_dec_sub27_form + connect \dec31_dec_sub27_function_unit \dec31_dec_sub27_dec31_dec_sub27_function_unit + connect \dec31_dec_sub27_in1_sel \dec31_dec_sub27_dec31_dec_sub27_in1_sel + connect \dec31_dec_sub27_in2_sel \dec31_dec_sub27_dec31_dec_sub27_in2_sel + connect \dec31_dec_sub27_in3_sel \dec31_dec_sub27_dec31_dec_sub27_in3_sel + connect \dec31_dec_sub27_internal_op \dec31_dec_sub27_dec31_dec_sub27_internal_op + connect \dec31_dec_sub27_inv_a \dec31_dec_sub27_dec31_dec_sub27_inv_a + connect \dec31_dec_sub27_inv_out \dec31_dec_sub27_dec31_dec_sub27_inv_out + connect \dec31_dec_sub27_is_32b \dec31_dec_sub27_dec31_dec_sub27_is_32b + connect \dec31_dec_sub27_ldst_len \dec31_dec_sub27_dec31_dec_sub27_ldst_len + connect \dec31_dec_sub27_lk \dec31_dec_sub27_dec31_dec_sub27_lk + connect \dec31_dec_sub27_out_sel \dec31_dec_sub27_dec31_dec_sub27_out_sel + connect \dec31_dec_sub27_rc_sel \dec31_dec_sub27_dec31_dec_sub27_rc_sel + connect \dec31_dec_sub27_rsrv \dec31_dec_sub27_dec31_dec_sub27_rsrv + connect \dec31_dec_sub27_sgl_pipe \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + connect \dec31_dec_sub27_sgn \dec31_dec_sub27_dec31_dec_sub27_sgn + connect \dec31_dec_sub27_sgn_ext \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + connect \dec31_dec_sub27_upd \dec31_dec_sub27_dec31_dec_sub27_upd + connect \opcode_in \dec31_dec_sub27_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16663.19-16689.4" + cell \dec31_dec_sub28 \dec31_dec_sub28 + connect \dec31_dec_sub28_asmcode \dec31_dec_sub28_dec31_dec_sub28_asmcode + connect \dec31_dec_sub28_br \dec31_dec_sub28_dec31_dec_sub28_br + connect \dec31_dec_sub28_cr_in \dec31_dec_sub28_dec31_dec_sub28_cr_in + connect \dec31_dec_sub28_cr_out \dec31_dec_sub28_dec31_dec_sub28_cr_out + connect \dec31_dec_sub28_cry_in \dec31_dec_sub28_dec31_dec_sub28_cry_in + connect \dec31_dec_sub28_cry_out \dec31_dec_sub28_dec31_dec_sub28_cry_out + connect \dec31_dec_sub28_form \dec31_dec_sub28_dec31_dec_sub28_form + connect \dec31_dec_sub28_function_unit \dec31_dec_sub28_dec31_dec_sub28_function_unit + connect \dec31_dec_sub28_in1_sel \dec31_dec_sub28_dec31_dec_sub28_in1_sel + connect \dec31_dec_sub28_in2_sel \dec31_dec_sub28_dec31_dec_sub28_in2_sel + connect \dec31_dec_sub28_in3_sel \dec31_dec_sub28_dec31_dec_sub28_in3_sel + connect \dec31_dec_sub28_internal_op \dec31_dec_sub28_dec31_dec_sub28_internal_op + connect \dec31_dec_sub28_inv_a \dec31_dec_sub28_dec31_dec_sub28_inv_a + connect \dec31_dec_sub28_inv_out \dec31_dec_sub28_dec31_dec_sub28_inv_out + connect \dec31_dec_sub28_is_32b \dec31_dec_sub28_dec31_dec_sub28_is_32b + connect \dec31_dec_sub28_ldst_len \dec31_dec_sub28_dec31_dec_sub28_ldst_len + connect \dec31_dec_sub28_lk \dec31_dec_sub28_dec31_dec_sub28_lk + connect \dec31_dec_sub28_out_sel \dec31_dec_sub28_dec31_dec_sub28_out_sel + connect \dec31_dec_sub28_rc_sel \dec31_dec_sub28_dec31_dec_sub28_rc_sel + connect \dec31_dec_sub28_rsrv \dec31_dec_sub28_dec31_dec_sub28_rsrv + connect \dec31_dec_sub28_sgl_pipe \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe + connect \dec31_dec_sub28_sgn \dec31_dec_sub28_dec31_dec_sub28_sgn + connect \dec31_dec_sub28_sgn_ext \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + connect \dec31_dec_sub28_upd \dec31_dec_sub28_dec31_dec_sub28_upd + connect \opcode_in \dec31_dec_sub28_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16690.18-16716.4" + cell \dec31_dec_sub4 \dec31_dec_sub4 + connect \dec31_dec_sub4_asmcode \dec31_dec_sub4_dec31_dec_sub4_asmcode + connect \dec31_dec_sub4_br \dec31_dec_sub4_dec31_dec_sub4_br + connect \dec31_dec_sub4_cr_in \dec31_dec_sub4_dec31_dec_sub4_cr_in + connect \dec31_dec_sub4_cr_out \dec31_dec_sub4_dec31_dec_sub4_cr_out + connect \dec31_dec_sub4_cry_in \dec31_dec_sub4_dec31_dec_sub4_cry_in + connect \dec31_dec_sub4_cry_out \dec31_dec_sub4_dec31_dec_sub4_cry_out + connect \dec31_dec_sub4_form \dec31_dec_sub4_dec31_dec_sub4_form + connect \dec31_dec_sub4_function_unit \dec31_dec_sub4_dec31_dec_sub4_function_unit + connect \dec31_dec_sub4_in1_sel \dec31_dec_sub4_dec31_dec_sub4_in1_sel + connect \dec31_dec_sub4_in2_sel \dec31_dec_sub4_dec31_dec_sub4_in2_sel + connect \dec31_dec_sub4_in3_sel \dec31_dec_sub4_dec31_dec_sub4_in3_sel + connect \dec31_dec_sub4_internal_op \dec31_dec_sub4_dec31_dec_sub4_internal_op + connect \dec31_dec_sub4_inv_a \dec31_dec_sub4_dec31_dec_sub4_inv_a + connect \dec31_dec_sub4_inv_out \dec31_dec_sub4_dec31_dec_sub4_inv_out + connect \dec31_dec_sub4_is_32b \dec31_dec_sub4_dec31_dec_sub4_is_32b + connect \dec31_dec_sub4_ldst_len \dec31_dec_sub4_dec31_dec_sub4_ldst_len + connect \dec31_dec_sub4_lk \dec31_dec_sub4_dec31_dec_sub4_lk + connect \dec31_dec_sub4_out_sel \dec31_dec_sub4_dec31_dec_sub4_out_sel + connect \dec31_dec_sub4_rc_sel \dec31_dec_sub4_dec31_dec_sub4_rc_sel + connect \dec31_dec_sub4_rsrv \dec31_dec_sub4_dec31_dec_sub4_rsrv + connect \dec31_dec_sub4_sgl_pipe \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe + connect \dec31_dec_sub4_sgn \dec31_dec_sub4_dec31_dec_sub4_sgn + connect \dec31_dec_sub4_sgn_ext \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + connect \dec31_dec_sub4_upd \dec31_dec_sub4_dec31_dec_sub4_upd + connect \opcode_in \dec31_dec_sub4_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16717.18-16743.4" + cell \dec31_dec_sub8 \dec31_dec_sub8 + connect \dec31_dec_sub8_asmcode \dec31_dec_sub8_dec31_dec_sub8_asmcode + connect \dec31_dec_sub8_br \dec31_dec_sub8_dec31_dec_sub8_br + connect \dec31_dec_sub8_cr_in \dec31_dec_sub8_dec31_dec_sub8_cr_in + connect \dec31_dec_sub8_cr_out \dec31_dec_sub8_dec31_dec_sub8_cr_out + connect \dec31_dec_sub8_cry_in \dec31_dec_sub8_dec31_dec_sub8_cry_in + connect \dec31_dec_sub8_cry_out \dec31_dec_sub8_dec31_dec_sub8_cry_out + connect \dec31_dec_sub8_form \dec31_dec_sub8_dec31_dec_sub8_form + connect \dec31_dec_sub8_function_unit \dec31_dec_sub8_dec31_dec_sub8_function_unit + connect \dec31_dec_sub8_in1_sel \dec31_dec_sub8_dec31_dec_sub8_in1_sel + connect \dec31_dec_sub8_in2_sel \dec31_dec_sub8_dec31_dec_sub8_in2_sel + connect \dec31_dec_sub8_in3_sel \dec31_dec_sub8_dec31_dec_sub8_in3_sel + connect \dec31_dec_sub8_internal_op \dec31_dec_sub8_dec31_dec_sub8_internal_op + connect \dec31_dec_sub8_inv_a \dec31_dec_sub8_dec31_dec_sub8_inv_a + connect \dec31_dec_sub8_inv_out \dec31_dec_sub8_dec31_dec_sub8_inv_out + connect \dec31_dec_sub8_is_32b \dec31_dec_sub8_dec31_dec_sub8_is_32b + connect \dec31_dec_sub8_ldst_len \dec31_dec_sub8_dec31_dec_sub8_ldst_len + connect \dec31_dec_sub8_lk \dec31_dec_sub8_dec31_dec_sub8_lk + connect \dec31_dec_sub8_out_sel \dec31_dec_sub8_dec31_dec_sub8_out_sel + connect \dec31_dec_sub8_rc_sel \dec31_dec_sub8_dec31_dec_sub8_rc_sel + connect \dec31_dec_sub8_rsrv \dec31_dec_sub8_dec31_dec_sub8_rsrv + connect \dec31_dec_sub8_sgl_pipe \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + connect \dec31_dec_sub8_sgn \dec31_dec_sub8_dec31_dec_sub8_sgn + connect \dec31_dec_sub8_sgn_ext \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + connect \dec31_dec_sub8_upd \dec31_dec_sub8_dec31_dec_sub8_upd + connect \opcode_in \dec31_dec_sub8_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16744.18-16770.4" + cell \dec31_dec_sub9 \dec31_dec_sub9 + connect \dec31_dec_sub9_asmcode \dec31_dec_sub9_dec31_dec_sub9_asmcode + connect \dec31_dec_sub9_br \dec31_dec_sub9_dec31_dec_sub9_br + connect \dec31_dec_sub9_cr_in \dec31_dec_sub9_dec31_dec_sub9_cr_in + connect \dec31_dec_sub9_cr_out \dec31_dec_sub9_dec31_dec_sub9_cr_out + connect \dec31_dec_sub9_cry_in \dec31_dec_sub9_dec31_dec_sub9_cry_in + connect \dec31_dec_sub9_cry_out \dec31_dec_sub9_dec31_dec_sub9_cry_out + connect \dec31_dec_sub9_form \dec31_dec_sub9_dec31_dec_sub9_form + connect \dec31_dec_sub9_function_unit \dec31_dec_sub9_dec31_dec_sub9_function_unit + connect \dec31_dec_sub9_in1_sel \dec31_dec_sub9_dec31_dec_sub9_in1_sel + connect \dec31_dec_sub9_in2_sel \dec31_dec_sub9_dec31_dec_sub9_in2_sel + connect \dec31_dec_sub9_in3_sel \dec31_dec_sub9_dec31_dec_sub9_in3_sel + connect \dec31_dec_sub9_internal_op \dec31_dec_sub9_dec31_dec_sub9_internal_op + connect \dec31_dec_sub9_inv_a \dec31_dec_sub9_dec31_dec_sub9_inv_a + connect \dec31_dec_sub9_inv_out \dec31_dec_sub9_dec31_dec_sub9_inv_out + connect \dec31_dec_sub9_is_32b \dec31_dec_sub9_dec31_dec_sub9_is_32b + connect \dec31_dec_sub9_ldst_len \dec31_dec_sub9_dec31_dec_sub9_ldst_len + connect \dec31_dec_sub9_lk \dec31_dec_sub9_dec31_dec_sub9_lk + connect \dec31_dec_sub9_out_sel \dec31_dec_sub9_dec31_dec_sub9_out_sel + connect \dec31_dec_sub9_rc_sel \dec31_dec_sub9_dec31_dec_sub9_rc_sel + connect \dec31_dec_sub9_rsrv \dec31_dec_sub9_dec31_dec_sub9_rsrv + connect \dec31_dec_sub9_sgl_pipe \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + connect \dec31_dec_sub9_sgn \dec31_dec_sub9_dec31_dec_sub9_sgn + connect \dec31_dec_sub9_sgn_ext \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd + connect \opcode_in \dec31_dec_sub9_opcode_in + end + attribute \src "libresoc.v:11886.7-11886.20" + process $proc$libresoc.v:11886$406 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:16771.3-16831.6" + process $proc$libresoc.v:16771$382 + assign { } { } + assign { } { } + assign $0\dec31_function_unit[11:0] $1\dec31_function_unit[11:0] + attribute \src "libresoc.v:16772.5-16772.29" + switch \initial + attribute \src "libresoc.v:16772.9-16772.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub10_dec31_dec_sub10_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub28_dec31_dec_sub28_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub0_dec31_dec_sub0_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub26_dec31_dec_sub26_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub19_dec31_dec_sub19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub22_dec31_dec_sub22_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub9_dec31_dec_sub9_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub11_dec31_dec_sub11_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub27_dec31_dec_sub27_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub15_dec31_dec_sub15_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub20_dec31_dec_sub20_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub21_dec31_dec_sub21_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub23_dec31_dec_sub23_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub16_dec31_dec_sub16_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub18_dec31_dec_sub18_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub8_dec31_dec_sub8_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub24_dec31_dec_sub24_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub4_dec31_dec_sub4_function_unit + case + assign $1\dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_function_unit $0\dec31_function_unit[11:0] + end + attribute \src "libresoc.v:16832.3-16892.6" + process $proc$libresoc.v:16832$383 + assign { } { } + assign { } { } + assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] + attribute \src "libresoc.v:16833.5-16833.29" + switch \initial + attribute \src "libresoc.v:16833.9-16833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub10_dec31_dec_sub10_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub28_dec31_dec_sub28_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub0_dec31_dec_sub0_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub26_dec31_dec_sub26_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub19_dec31_dec_sub19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub22_dec31_dec_sub22_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub9_dec31_dec_sub9_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub11_dec31_dec_sub11_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub27_dec31_dec_sub27_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub15_dec31_dec_sub15_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub20_dec31_dec_sub20_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub21_dec31_dec_sub21_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub23_dec31_dec_sub23_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub16_dec31_dec_sub16_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub18_dec31_dec_sub18_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub8_dec31_dec_sub8_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub24_dec31_dec_sub24_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub4_dec31_dec_sub4_internal_op + case + assign $1\dec31_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_internal_op $0\dec31_internal_op[6:0] + end + attribute \src "libresoc.v:16893.3-16953.6" + process $proc$libresoc.v:16893$384 + assign { } { } + assign { } { } + assign $0\dec31_form[4:0] $1\dec31_form[4:0] + attribute \src "libresoc.v:16894.5-16894.29" + switch \initial + attribute \src "libresoc.v:16894.9-16894.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub10_dec31_dec_sub10_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub28_dec31_dec_sub28_form + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub0_dec31_dec_sub0_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub26_dec31_dec_sub26_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub19_dec31_dec_sub19_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub22_dec31_dec_sub22_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub9_dec31_dec_sub9_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub11_dec31_dec_sub11_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub27_dec31_dec_sub27_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub15_dec31_dec_sub15_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub20_dec31_dec_sub20_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub21_dec31_dec_sub21_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub23_dec31_dec_sub23_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub16_dec31_dec_sub16_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub18_dec31_dec_sub18_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub8_dec31_dec_sub8_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub24_dec31_dec_sub24_form + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub4_dec31_dec_sub4_form + case + assign $1\dec31_form[4:0] 5'00000 + end + sync always + update \dec31_form $0\dec31_form[4:0] + end + attribute \src "libresoc.v:16954.3-17014.6" + process $proc$libresoc.v:16954$385 + assign { } { } + assign { } { } + assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] + attribute \src "libresoc.v:16955.5-16955.29" + switch \initial + attribute \src "libresoc.v:16955.9-16955.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub10_dec31_dec_sub10_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub28_dec31_dec_sub28_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub0_dec31_dec_sub0_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub26_dec31_dec_sub26_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub19_dec31_dec_sub19_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub22_dec31_dec_sub22_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub9_dec31_dec_sub9_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub11_dec31_dec_sub11_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub27_dec31_dec_sub27_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub15_dec31_dec_sub15_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub20_dec31_dec_sub20_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub21_dec31_dec_sub21_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub23_dec31_dec_sub23_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub16_dec31_dec_sub16_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub18_dec31_dec_sub18_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub8_dec31_dec_sub8_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub24_dec31_dec_sub24_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub4_dec31_dec_sub4_asmcode + case + assign $1\dec31_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_asmcode $0\dec31_asmcode[7:0] + end + attribute \src "libresoc.v:17015.3-17075.6" + process $proc$libresoc.v:17015$386 + assign { } { } + assign { } { } + assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] + attribute \src "libresoc.v:17016.5-17016.29" + switch \initial + attribute \src "libresoc.v:17016.9-17016.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub10_dec31_dec_sub10_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub28_dec31_dec_sub28_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub0_dec31_dec_sub0_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub26_dec31_dec_sub26_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub19_dec31_dec_sub19_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub22_dec31_dec_sub22_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub9_dec31_dec_sub9_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub11_dec31_dec_sub11_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub27_dec31_dec_sub27_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub15_dec31_dec_sub15_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub20_dec31_dec_sub20_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub21_dec31_dec_sub21_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub23_dec31_dec_sub23_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub16_dec31_dec_sub16_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub18_dec31_dec_sub18_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub8_dec31_dec_sub8_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub24_dec31_dec_sub24_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub4_dec31_dec_sub4_in1_sel + case + assign $1\dec31_in1_sel[2:0] 3'000 + end + sync always + update \dec31_in1_sel $0\dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:17076.3-17136.6" + process $proc$libresoc.v:17076$387 + assign { } { } + assign { } { } + assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] + attribute \src "libresoc.v:17077.5-17077.29" + switch \initial + attribute \src "libresoc.v:17077.9-17077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub10_dec31_dec_sub10_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub28_dec31_dec_sub28_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub0_dec31_dec_sub0_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub26_dec31_dec_sub26_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub19_dec31_dec_sub19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub22_dec31_dec_sub22_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub9_dec31_dec_sub9_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub11_dec31_dec_sub11_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub27_dec31_dec_sub27_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub15_dec31_dec_sub15_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub20_dec31_dec_sub20_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub21_dec31_dec_sub21_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub23_dec31_dec_sub23_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub16_dec31_dec_sub16_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub18_dec31_dec_sub18_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub8_dec31_dec_sub8_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub24_dec31_dec_sub24_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub4_dec31_dec_sub4_in2_sel + case + assign $1\dec31_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_in2_sel $0\dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:17137.3-17197.6" + process $proc$libresoc.v:17137$388 + assign { } { } + assign { } { } + assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] + attribute \src "libresoc.v:17138.5-17138.29" + switch \initial + attribute \src "libresoc.v:17138.9-17138.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_in3_sel + case + assign $1\dec31_in3_sel[1:0] 2'00 + end + sync always + update \dec31_in3_sel $0\dec31_in3_sel[1:0] + end + attribute \src "libresoc.v:17198.3-17258.6" + process $proc$libresoc.v:17198$389 + assign { } { } + assign { } { } + assign $0\dec31_out_sel[1:0] $1\dec31_out_sel[1:0] + attribute \src "libresoc.v:17199.5-17199.29" + switch \initial + attribute \src "libresoc.v:17199.9-17199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_out_sel + case + assign $1\dec31_out_sel[1:0] 2'00 + end + sync always + update \dec31_out_sel $0\dec31_out_sel[1:0] + end + attribute \src "libresoc.v:17259.3-17319.6" + process $proc$libresoc.v:17259$390 + assign { } { } + assign { } { } + assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] + attribute \src "libresoc.v:17260.5-17260.29" + switch \initial + attribute \src "libresoc.v:17260.9-17260.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_in + case + assign $1\dec31_cr_in[2:0] 3'000 + end + sync always + update \dec31_cr_in $0\dec31_cr_in[2:0] + end + attribute \src "libresoc.v:17320.3-17380.6" + process $proc$libresoc.v:17320$391 + assign { } { } + assign { } { } + assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] + attribute \src "libresoc.v:17321.5-17321.29" + switch \initial + attribute \src "libresoc.v:17321.9-17321.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_out + case + assign $1\dec31_cr_out[2:0] 3'000 + end + sync always + update \dec31_cr_out $0\dec31_cr_out[2:0] + end + attribute \src "libresoc.v:17381.3-17441.6" + process $proc$libresoc.v:17381$392 + assign { } { } + assign { } { } + assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] + attribute \src "libresoc.v:17382.5-17382.29" + switch \initial + attribute \src "libresoc.v:17382.9-17382.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub10_dec31_dec_sub10_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub28_dec31_dec_sub28_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub0_dec31_dec_sub0_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub26_dec31_dec_sub26_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub19_dec31_dec_sub19_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub22_dec31_dec_sub22_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub9_dec31_dec_sub9_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub11_dec31_dec_sub11_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub27_dec31_dec_sub27_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub15_dec31_dec_sub15_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub20_dec31_dec_sub20_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub21_dec31_dec_sub21_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub23_dec31_dec_sub23_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub16_dec31_dec_sub16_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub18_dec31_dec_sub18_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub8_dec31_dec_sub8_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub24_dec31_dec_sub24_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub4_dec31_dec_sub4_ldst_len + case + assign $1\dec31_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_ldst_len $0\dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:17442.3-17502.6" + process $proc$libresoc.v:17442$393 + assign { } { } + assign { } { } + assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] + attribute \src "libresoc.v:17443.5-17443.29" + switch \initial + attribute \src "libresoc.v:17443.9-17443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub10_dec31_dec_sub10_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub28_dec31_dec_sub28_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub0_dec31_dec_sub0_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub26_dec31_dec_sub26_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub19_dec31_dec_sub19_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub22_dec31_dec_sub22_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub9_dec31_dec_sub9_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub11_dec31_dec_sub11_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub27_dec31_dec_sub27_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub15_dec31_dec_sub15_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub20_dec31_dec_sub20_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub21_dec31_dec_sub21_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub23_dec31_dec_sub23_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub16_dec31_dec_sub16_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub18_dec31_dec_sub18_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub8_dec31_dec_sub8_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub24_dec31_dec_sub24_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub4_dec31_dec_sub4_upd + case + assign $1\dec31_upd[1:0] 2'00 + end + sync always + update \dec31_upd $0\dec31_upd[1:0] + end + attribute \src "libresoc.v:17503.3-17563.6" + process $proc$libresoc.v:17503$394 + assign { } { } + assign { } { } + assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] + attribute \src "libresoc.v:17504.5-17504.29" + switch \initial + attribute \src "libresoc.v:17504.9-17504.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_rc_sel + case + assign $1\dec31_rc_sel[1:0] 2'00 + end + sync always + update \dec31_rc_sel $0\dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:17564.3-17624.6" + process $proc$libresoc.v:17564$395 + assign { } { } + assign { } { } + assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] + attribute \src "libresoc.v:17565.5-17565.29" + switch \initial + attribute \src "libresoc.v:17565.9-17565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub10_dec31_dec_sub10_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub28_dec31_dec_sub28_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub0_dec31_dec_sub0_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub26_dec31_dec_sub26_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub19_dec31_dec_sub19_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub22_dec31_dec_sub22_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub9_dec31_dec_sub9_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub11_dec31_dec_sub11_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub27_dec31_dec_sub27_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub15_dec31_dec_sub15_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub20_dec31_dec_sub20_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub21_dec31_dec_sub21_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub23_dec31_dec_sub23_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub16_dec31_dec_sub16_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub18_dec31_dec_sub18_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub8_dec31_dec_sub8_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub24_dec31_dec_sub24_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub4_dec31_dec_sub4_cry_in + case + assign $1\dec31_cry_in[1:0] 2'00 + end + sync always + update \dec31_cry_in $0\dec31_cry_in[1:0] + end + attribute \src "libresoc.v:17625.3-17685.6" + process $proc$libresoc.v:17625$396 + assign { } { } + assign { } { } + assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] + attribute \src "libresoc.v:17626.5-17626.29" + switch \initial + attribute \src "libresoc.v:17626.9-17626.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_a + case + assign $1\dec31_inv_a[0:0] 1'0 + end + sync always + update \dec31_inv_a $0\dec31_inv_a[0:0] + end + attribute \src "libresoc.v:17686.3-17746.6" + process $proc$libresoc.v:17686$397 + assign { } { } + assign { } { } + assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] + attribute \src "libresoc.v:17687.5-17687.29" + switch \initial + attribute \src "libresoc.v:17687.9-17687.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_out + case + assign $1\dec31_inv_out[0:0] 1'0 + end + sync always + update \dec31_inv_out $0\dec31_inv_out[0:0] + end + attribute \src "libresoc.v:17747.3-17807.6" + process $proc$libresoc.v:17747$398 + assign { } { } + assign { } { } + assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] + attribute \src "libresoc.v:17748.5-17748.29" + switch \initial + attribute \src "libresoc.v:17748.9-17748.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_cry_out + case + assign $1\dec31_cry_out[0:0] 1'0 + end + sync always + update \dec31_cry_out $0\dec31_cry_out[0:0] + end + attribute \src "libresoc.v:17808.3-17868.6" + process $proc$libresoc.v:17808$399 + assign { } { } + assign { } { } + assign $0\dec31_br[0:0] $1\dec31_br[0:0] + attribute \src "libresoc.v:17809.5-17809.29" + switch \initial + attribute \src "libresoc.v:17809.9-17809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub10_dec31_dec_sub10_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub28_dec31_dec_sub28_br + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub0_dec31_dec_sub0_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub26_dec31_dec_sub26_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub19_dec31_dec_sub19_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub22_dec31_dec_sub22_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub9_dec31_dec_sub9_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub11_dec31_dec_sub11_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub27_dec31_dec_sub27_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub15_dec31_dec_sub15_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub20_dec31_dec_sub20_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub21_dec31_dec_sub21_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub23_dec31_dec_sub23_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub16_dec31_dec_sub16_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub18_dec31_dec_sub18_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub8_dec31_dec_sub8_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub24_dec31_dec_sub24_br + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub4_dec31_dec_sub4_br + case + assign $1\dec31_br[0:0] 1'0 + end + sync always + update \dec31_br $0\dec31_br[0:0] + end + attribute \src "libresoc.v:17869.3-17929.6" + process $proc$libresoc.v:17869$400 + assign { } { } + assign { } { } + assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:17870.5-17870.29" + switch \initial + attribute \src "libresoc.v:17870.9-17870.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + case + assign $1\dec31_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] + end + attribute \src "libresoc.v:17930.3-17990.6" + process $proc$libresoc.v:17930$401 + assign { } { } + assign { } { } + assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] + attribute \src "libresoc.v:17931.5-17931.29" + switch \initial + attribute \src "libresoc.v:17931.9-17931.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub10_dec31_dec_sub10_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub28_dec31_dec_sub28_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub0_dec31_dec_sub0_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub26_dec31_dec_sub26_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub19_dec31_dec_sub19_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub22_dec31_dec_sub22_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub9_dec31_dec_sub9_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub11_dec31_dec_sub11_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub27_dec31_dec_sub27_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub15_dec31_dec_sub15_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub20_dec31_dec_sub20_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub21_dec31_dec_sub21_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub23_dec31_dec_sub23_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub16_dec31_dec_sub16_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub18_dec31_dec_sub18_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub8_dec31_dec_sub8_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub24_dec31_dec_sub24_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub4_dec31_dec_sub4_rsrv + case + assign $1\dec31_rsrv[0:0] 1'0 + end + sync always + update \dec31_rsrv $0\dec31_rsrv[0:0] + end + attribute \src "libresoc.v:17991.3-18051.6" + process $proc$libresoc.v:17991$402 + assign { } { } + assign { } { } + assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] + attribute \src "libresoc.v:17992.5-17992.29" + switch \initial + attribute \src "libresoc.v:17992.9-17992.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub10_dec31_dec_sub10_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub28_dec31_dec_sub28_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub0_dec31_dec_sub0_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub26_dec31_dec_sub26_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub19_dec31_dec_sub19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub22_dec31_dec_sub22_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub9_dec31_dec_sub9_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub11_dec31_dec_sub11_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub27_dec31_dec_sub27_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub15_dec31_dec_sub15_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub20_dec31_dec_sub20_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub21_dec31_dec_sub21_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub23_dec31_dec_sub23_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub16_dec31_dec_sub16_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub18_dec31_dec_sub18_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub8_dec31_dec_sub8_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub24_dec31_dec_sub24_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub4_dec31_dec_sub4_is_32b + case + assign $1\dec31_is_32b[0:0] 1'0 + end + sync always + update \dec31_is_32b $0\dec31_is_32b[0:0] + end + attribute \src "libresoc.v:18052.3-18112.6" + process $proc$libresoc.v:18052$403 + assign { } { } + assign { } { } + assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] + attribute \src "libresoc.v:18053.5-18053.29" + switch \initial + attribute \src "libresoc.v:18053.9-18053.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn + case + assign $1\dec31_sgn[0:0] 1'0 + end + sync always + update \dec31_sgn $0\dec31_sgn[0:0] + end + attribute \src "libresoc.v:18113.3-18173.6" + process $proc$libresoc.v:18113$404 + assign { } { } + assign { } { } + assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] + attribute \src "libresoc.v:18114.5-18114.29" + switch \initial + attribute \src "libresoc.v:18114.9-18114.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub10_dec31_dec_sub10_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub28_dec31_dec_sub28_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub0_dec31_dec_sub0_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub26_dec31_dec_sub26_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub19_dec31_dec_sub19_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub22_dec31_dec_sub22_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub9_dec31_dec_sub9_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub11_dec31_dec_sub11_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub27_dec31_dec_sub27_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub15_dec31_dec_sub15_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub20_dec31_dec_sub20_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub21_dec31_dec_sub21_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub23_dec31_dec_sub23_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub16_dec31_dec_sub16_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub18_dec31_dec_sub18_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub8_dec31_dec_sub8_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub24_dec31_dec_sub24_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub4_dec31_dec_sub4_lk + case + assign $1\dec31_lk[0:0] 1'0 + end + sync always + update \dec31_lk $0\dec31_lk[0:0] + end + attribute \src "libresoc.v:18174.3-18234.6" + process $proc$libresoc.v:18174$405 + assign { } { } + assign { } { } + assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:18175.5-18175.29" + switch \initial + attribute \src "libresoc.v:18175.9-18175.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe + case + assign $1\dec31_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_sgl_pipe $0\dec31_sgl_pipe[0:0] + end + connect \dec31_dec_sub4_opcode_in \opcode_in + connect \dec31_dec_sub24_opcode_in \opcode_in + connect \dec31_dec_sub8_opcode_in \opcode_in + connect \dec31_dec_sub18_opcode_in \opcode_in + connect \dec31_dec_sub16_opcode_in \opcode_in + connect \dec31_dec_sub23_opcode_in \opcode_in + connect \dec31_dec_sub21_opcode_in \opcode_in + connect \dec31_dec_sub20_opcode_in \opcode_in + connect \dec31_dec_sub15_opcode_in \opcode_in + connect \dec31_dec_sub27_opcode_in \opcode_in + connect \dec31_dec_sub11_opcode_in \opcode_in + connect \dec31_dec_sub9_opcode_in \opcode_in + connect \dec31_dec_sub22_opcode_in \opcode_in + connect \dec31_dec_sub19_opcode_in \opcode_in + connect \dec31_dec_sub26_opcode_in \opcode_in + connect \dec31_dec_sub0_opcode_in \opcode_in + connect \dec31_dec_sub28_opcode_in \opcode_in + connect \dec31_dec_sub10_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:18259.1-18974.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0" +attribute \generator "nMigen" +module \dec31_dec_sub0 + attribute \src "libresoc.v:18612.3-18630.6" + wire width 8 $0\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:18688.3-18706.6" + wire $0\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:18935.3-18953.6" + wire width 3 $0\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:18954.3-18972.6" + wire width 3 $0\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:18593.3-18611.6" + wire width 2 $0\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:18669.3-18687.6" + wire $0\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:18840.3-18858.6" + wire width 5 $0\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:18517.3-18535.6" + wire width 12 $0\dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:18859.3-18877.6" + wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:18878.3-18896.6" + wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:18897.3-18915.6" + wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:18726.3-18744.6" + wire width 7 $0\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:18631.3-18649.6" + wire $0\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:18650.3-18668.6" + wire $0\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:18764.3-18782.6" + wire $0\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:18536.3-18554.6" + wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:18802.3-18820.6" + wire $0\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:18916.3-18934.6" + wire width 2 $0\dec31_dec_sub0_out_sel[1:0] + attribute \src "libresoc.v:18574.3-18592.6" + wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:18745.3-18763.6" + wire $0\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:18821.3-18839.6" + wire $0\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:18783.3-18801.6" + wire $0\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:18707.3-18725.6" + wire $0\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:18555.3-18573.6" + wire width 2 $0\dec31_dec_sub0_upd[1:0] + attribute \src "libresoc.v:18260.7-18260.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:18612.3-18630.6" + wire width 8 $1\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:18688.3-18706.6" + wire $1\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:18935.3-18953.6" + wire width 3 $1\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:18954.3-18972.6" + wire width 3 $1\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:18593.3-18611.6" + wire width 2 $1\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:18669.3-18687.6" + wire $1\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:18840.3-18858.6" + wire width 5 $1\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:18517.3-18535.6" + wire width 12 $1\dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:18859.3-18877.6" + wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:18878.3-18896.6" + wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:18897.3-18915.6" + wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:18726.3-18744.6" + wire width 7 $1\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:18631.3-18649.6" + wire $1\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:18650.3-18668.6" + wire $1\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:18764.3-18782.6" + wire $1\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:18536.3-18554.6" + wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:18802.3-18820.6" + wire $1\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:18916.3-18934.6" + wire width 2 $1\dec31_dec_sub0_out_sel[1:0] + attribute \src "libresoc.v:18574.3-18592.6" + wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:18745.3-18763.6" + wire $1\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:18821.3-18839.6" + wire $1\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:18783.3-18801.6" + wire $1\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:18707.3-18725.6" + wire $1\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:18555.3-18573.6" + wire width 2 $1\dec31_dec_sub0_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub0_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub0_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub0_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub0_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub0_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub0_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub0_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub0_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub0_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub0_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub0_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub0_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub0_upd + attribute \src "libresoc.v:18260.7-18260.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:18260.7-18260.20" + process $proc$libresoc.v:18260$431 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:18517.3-18535.6" + process $proc$libresoc.v:18517$407 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_function_unit[11:0] $1\dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:18518.5-18518.29" + switch \initial + attribute \src "libresoc.v:18518.9-18518.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000001000000 + case + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[11:0] + end + attribute \src "libresoc.v:18536.3-18554.6" + process $proc$libresoc.v:18536$408 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:18537.5-18537.29" + switch \initial + attribute \src "libresoc.v:18537.9-18537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] + end + attribute \src "libresoc.v:18555.3-18573.6" + process $proc$libresoc.v:18555$409 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] + attribute \src "libresoc.v:18556.5-18556.29" + switch \initial + attribute \src "libresoc.v:18556.9-18556.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] + end + attribute \src "libresoc.v:18574.3-18592.6" + process $proc$libresoc.v:18574$410 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:18575.5-18575.29" + switch \initial + attribute \src "libresoc.v:18575.9-18575.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] + end + attribute \src "libresoc.v:18593.3-18611.6" + process $proc$libresoc.v:18593$411 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:18594.5-18594.29" + switch \initial + attribute \src "libresoc.v:18594.9-18594.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] + end + attribute \src "libresoc.v:18612.3-18630.6" + process $proc$libresoc.v:18612$412 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:18613.5-18613.29" + switch \initial + attribute \src "libresoc.v:18613.9-18613.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'10011011 + case + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] + end + attribute \src "libresoc.v:18631.3-18649.6" + process $proc$libresoc.v:18631$413 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:18632.5-18632.29" + switch \initial + attribute \src "libresoc.v:18632.9-18632.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] + end + attribute \src "libresoc.v:18650.3-18668.6" + process $proc$libresoc.v:18650$414 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:18651.5-18651.29" + switch \initial + attribute \src "libresoc.v:18651.9-18651.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] + end + attribute \src "libresoc.v:18669.3-18687.6" + process $proc$libresoc.v:18669$415 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:18670.5-18670.29" + switch \initial + attribute \src "libresoc.v:18670.9-18670.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] + end + attribute \src "libresoc.v:18688.3-18706.6" + process $proc$libresoc.v:18688$416 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:18689.5-18689.29" + switch \initial + attribute \src "libresoc.v:18689.9-18689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + case + assign $1\dec31_dec_sub0_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] + end + attribute \src "libresoc.v:18707.3-18725.6" + process $proc$libresoc.v:18707$417 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:18708.5-18708.29" + switch \initial + attribute \src "libresoc.v:18708.9-18708.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] + end + attribute \src "libresoc.v:18726.3-18744.6" + process $proc$libresoc.v:18726$418 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:18727.5-18727.29" + switch \initial + attribute \src "libresoc.v:18727.9-18727.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0111011 + case + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] + end + attribute \src "libresoc.v:18745.3-18763.6" + process $proc$libresoc.v:18745$419 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:18746.5-18746.29" + switch \initial + attribute \src "libresoc.v:18746.9-18746.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] + end + attribute \src "libresoc.v:18764.3-18782.6" + process $proc$libresoc.v:18764$420 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:18765.5-18765.29" + switch \initial + attribute \src "libresoc.v:18765.9-18765.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] + end + attribute \src "libresoc.v:18783.3-18801.6" + process $proc$libresoc.v:18783$421 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:18784.5-18784.29" + switch \initial + attribute \src "libresoc.v:18784.9-18784.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] + end + attribute \src "libresoc.v:18802.3-18820.6" + process $proc$libresoc.v:18802$422 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:18803.5-18803.29" + switch \initial + attribute \src "libresoc.v:18803.9-18803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] + end + attribute \src "libresoc.v:18821.3-18839.6" + process $proc$libresoc.v:18821$423 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:18822.5-18822.29" + switch \initial + attribute \src "libresoc.v:18822.9-18822.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] + end + attribute \src "libresoc.v:18840.3-18858.6" + process $proc$libresoc.v:18840$424 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:18841.5-18841.29" + switch \initial + attribute \src "libresoc.v:18841.9-18841.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'11000 + case + assign $1\dec31_dec_sub0_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] + end + attribute \src "libresoc.v:18859.3-18877.6" + process $proc$libresoc.v:18859$425 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:18860.5-18860.29" + switch \initial + attribute \src "libresoc.v:18860.9-18860.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] + end + attribute \src "libresoc.v:18878.3-18896.6" + process $proc$libresoc.v:18878$426 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:18879.5-18879.29" + switch \initial + attribute \src "libresoc.v:18879.9-18879.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] + end + attribute \src "libresoc.v:18897.3-18915.6" + process $proc$libresoc.v:18897$427 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:18898.5-18898.29" + switch \initial + attribute \src "libresoc.v:18898.9-18898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] + end + attribute \src "libresoc.v:18916.3-18934.6" + process $proc$libresoc.v:18916$428 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_out_sel[1:0] $1\dec31_dec_sub0_out_sel[1:0] + attribute \src "libresoc.v:18917.5-18917.29" + switch \initial + attribute \src "libresoc.v:18917.9-18917.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_out_sel $0\dec31_dec_sub0_out_sel[1:0] + end + attribute \src "libresoc.v:18935.3-18953.6" + process $proc$libresoc.v:18935$429 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:18936.5-18936.29" + switch \initial + attribute \src "libresoc.v:18936.9-18936.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'011 + case + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] + end + attribute \src "libresoc.v:18954.3-18972.6" + process $proc$libresoc.v:18954$430 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:18955.5-18955.29" + switch \initial + attribute \src "libresoc.v:18955.9-18955.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:18978.1-20125.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10" +attribute \generator "nMigen" +module \dec31_dec_sub10 + attribute \src "libresoc.v:19421.3-19457.6" + wire width 8 $0\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:19569.3-19605.6" + wire $0\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:20050.3-20086.6" + wire width 3 $0\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:20087.3-20123.6" + wire width 3 $0\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:19384.3-19420.6" + wire width 2 $0\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:19532.3-19568.6" + wire $0\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:19865.3-19901.6" + wire width 5 $0\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:19236.3-19272.6" + wire width 12 $0\dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:19902.3-19938.6" + wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:19939.3-19975.6" + wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:19976.3-20012.6" + wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:19643.3-19679.6" + wire width 7 $0\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:19458.3-19494.6" + wire $0\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:19495.3-19531.6" + wire $0\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:19717.3-19753.6" + wire $0\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:19273.3-19309.6" + wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:19791.3-19827.6" + wire $0\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:20013.3-20049.6" + wire width 2 $0\dec31_dec_sub10_out_sel[1:0] + attribute \src "libresoc.v:19347.3-19383.6" + wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:19680.3-19716.6" + wire $0\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:19828.3-19864.6" + wire $0\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:19754.3-19790.6" + wire $0\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:19606.3-19642.6" + wire $0\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:19310.3-19346.6" + wire width 2 $0\dec31_dec_sub10_upd[1:0] + attribute \src "libresoc.v:18979.7-18979.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:19421.3-19457.6" + wire width 8 $1\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:19569.3-19605.6" + wire $1\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:20050.3-20086.6" + wire width 3 $1\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:20087.3-20123.6" + wire width 3 $1\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:19384.3-19420.6" + wire width 2 $1\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:19532.3-19568.6" + wire $1\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:19865.3-19901.6" + wire width 5 $1\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:19236.3-19272.6" + wire width 12 $1\dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:19902.3-19938.6" + wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:19939.3-19975.6" + wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:19976.3-20012.6" + wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:19643.3-19679.6" + wire width 7 $1\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:19458.3-19494.6" + wire $1\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:19495.3-19531.6" + wire $1\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:19717.3-19753.6" + wire $1\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:19273.3-19309.6" + wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:19791.3-19827.6" + wire $1\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:20013.3-20049.6" + wire width 2 $1\dec31_dec_sub10_out_sel[1:0] + attribute \src "libresoc.v:19347.3-19383.6" + wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:19680.3-19716.6" + wire $1\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:19828.3-19864.6" + wire $1\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:19754.3-19790.6" + wire $1\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:19606.3-19642.6" + wire $1\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:19310.3-19346.6" + wire width 2 $1\dec31_dec_sub10_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub10_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub10_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub10_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub10_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub10_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub10_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub10_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub10_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub10_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub10_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub10_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub10_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub10_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub10_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub10_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub10_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub10_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub10_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub10_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub10_upd + attribute \src "libresoc.v:18979.7-18979.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:18979.7-18979.20" + process $proc$libresoc.v:18979$456 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:19236.3-19272.6" + process $proc$libresoc.v:19236$432 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_function_unit[11:0] $1\dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:19237.5-19237.29" + switch \initial + attribute \src "libresoc.v:19237.9-19237.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + case + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[11:0] + end + attribute \src "libresoc.v:19273.3-19309.6" + process $proc$libresoc.v:19273$433 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:19274.5-19274.29" + switch \initial + attribute \src "libresoc.v:19274.9-19274.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] + end + attribute \src "libresoc.v:19310.3-19346.6" + process $proc$libresoc.v:19310$434 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] + attribute \src "libresoc.v:19311.5-19311.29" + switch \initial + attribute \src "libresoc.v:19311.9-19311.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] + end + attribute \src "libresoc.v:19347.3-19383.6" + process $proc$libresoc.v:19347$435 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:19348.5-19348.29" + switch \initial + attribute \src "libresoc.v:19348.9-19348.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] + end + attribute \src "libresoc.v:19384.3-19420.6" + process $proc$libresoc.v:19384$436 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:19385.5-19385.29" + switch \initial + attribute \src "libresoc.v:19385.9-19385.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + case + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] + end + attribute \src "libresoc.v:19421.3-19457.6" + process $proc$libresoc.v:19421$437 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:19422.5-19422.29" + switch \initial + attribute \src "libresoc.v:19422.9-19422.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001110 + case + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] + end + attribute \src "libresoc.v:19458.3-19494.6" + process $proc$libresoc.v:19458$438 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:19459.5-19459.29" + switch \initial + attribute \src "libresoc.v:19459.9-19459.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] + end + attribute \src "libresoc.v:19495.3-19531.6" + process $proc$libresoc.v:19495$439 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:19496.5-19496.29" + switch \initial + attribute \src "libresoc.v:19496.9-19496.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] + end + attribute \src "libresoc.v:19532.3-19568.6" + process $proc$libresoc.v:19532$440 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:19533.5-19533.29" + switch \initial + attribute \src "libresoc.v:19533.9-19533.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] + end + attribute \src "libresoc.v:19569.3-19605.6" + process $proc$libresoc.v:19569$441 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:19570.5-19570.29" + switch \initial + attribute \src "libresoc.v:19570.9-19570.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + case + assign $1\dec31_dec_sub10_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] + end + attribute \src "libresoc.v:19606.3-19642.6" + process $proc$libresoc.v:19606$442 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:19607.5-19607.29" + switch \initial + attribute \src "libresoc.v:19607.9-19607.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] + end + attribute \src "libresoc.v:19643.3-19679.6" + process $proc$libresoc.v:19643$443 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:19644.5-19644.29" + switch \initial + attribute \src "libresoc.v:19644.9-19644.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + case + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] + end + attribute \src "libresoc.v:19680.3-19716.6" + process $proc$libresoc.v:19680$444 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:19681.5-19681.29" + switch \initial + attribute \src "libresoc.v:19681.9-19681.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] + end + attribute \src "libresoc.v:19717.3-19753.6" + process $proc$libresoc.v:19717$445 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:19718.5-19718.29" + switch \initial + attribute \src "libresoc.v:19718.9-19718.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] + end + attribute \src "libresoc.v:19754.3-19790.6" + process $proc$libresoc.v:19754$446 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:19755.5-19755.29" + switch \initial + attribute \src "libresoc.v:19755.9-19755.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] + end + attribute \src "libresoc.v:19791.3-19827.6" + process $proc$libresoc.v:19791$447 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:19792.5-19792.29" + switch \initial + attribute \src "libresoc.v:19792.9-19792.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] + end + attribute \src "libresoc.v:19828.3-19864.6" + process $proc$libresoc.v:19828$448 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:19829.5-19829.29" + switch \initial + attribute \src "libresoc.v:19829.9-19829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] + end + attribute \src "libresoc.v:19865.3-19901.6" + process $proc$libresoc.v:19865$449 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:19866.5-19866.29" + switch \initial + attribute \src "libresoc.v:19866.9-19866.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub10_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] + end + attribute \src "libresoc.v:19902.3-19938.6" + process $proc$libresoc.v:19902$450 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:19903.5-19903.29" + switch \initial + attribute \src "libresoc.v:19903.9-19903.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] + end + attribute \src "libresoc.v:19939.3-19975.6" + process $proc$libresoc.v:19939$451 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:19940.5-19940.29" + switch \initial + attribute \src "libresoc.v:19940.9-19940.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] + end + attribute \src "libresoc.v:19976.3-20012.6" + process $proc$libresoc.v:19976$452 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:19977.5-19977.29" + switch \initial + attribute \src "libresoc.v:19977.9-19977.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] + end + attribute \src "libresoc.v:20013.3-20049.6" + process $proc$libresoc.v:20013$453 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_out_sel[1:0] $1\dec31_dec_sub10_out_sel[1:0] + attribute \src "libresoc.v:20014.5-20014.29" + switch \initial + attribute \src "libresoc.v:20014.9-20014.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub10_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_out_sel $0\dec31_dec_sub10_out_sel[1:0] + end + attribute \src "libresoc.v:20050.3-20086.6" + process $proc$libresoc.v:20050$454 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:20051.5-20051.29" + switch \initial + attribute \src "libresoc.v:20051.9-20051.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] + end + attribute \src "libresoc.v:20087.3-20123.6" + process $proc$libresoc.v:20087$455 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:20088.5-20088.29" + switch \initial + attribute \src "libresoc.v:20088.9-20088.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub10_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:20129.1-21708.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11" +attribute \generator "nMigen" +module \dec31_dec_sub11 + attribute \src "libresoc.v:20662.3-20716.6" + wire width 8 $0\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:20882.3-20936.6" + wire $0\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:21597.3-21651.6" + wire width 3 $0\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:21652.3-21706.6" + wire width 3 $0\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:20607.3-20661.6" + wire width 2 $0\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:20827.3-20881.6" + wire $0\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:21322.3-21376.6" + wire width 5 $0\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:20387.3-20441.6" + wire width 12 $0\dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:21377.3-21431.6" + wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:21432.3-21486.6" + wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:21487.3-21541.6" + wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:20992.3-21046.6" + wire width 7 $0\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:20717.3-20771.6" + wire $0\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:20772.3-20826.6" + wire $0\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:21102.3-21156.6" + wire $0\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:20442.3-20496.6" + wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:21212.3-21266.6" + wire $0\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:21542.3-21596.6" + wire width 2 $0\dec31_dec_sub11_out_sel[1:0] + attribute \src "libresoc.v:20552.3-20606.6" + wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:21047.3-21101.6" + wire $0\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:21267.3-21321.6" + wire $0\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:21157.3-21211.6" + wire $0\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:20937.3-20991.6" + wire $0\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:20497.3-20551.6" + wire width 2 $0\dec31_dec_sub11_upd[1:0] + attribute \src "libresoc.v:20130.7-20130.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20662.3-20716.6" + wire width 8 $1\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:20882.3-20936.6" + wire $1\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:21597.3-21651.6" + wire width 3 $1\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:21652.3-21706.6" + wire width 3 $1\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:20607.3-20661.6" + wire width 2 $1\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:20827.3-20881.6" + wire $1\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:21322.3-21376.6" + wire width 5 $1\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:20387.3-20441.6" + wire width 12 $1\dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:21377.3-21431.6" + wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:21432.3-21486.6" + wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:21487.3-21541.6" + wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:20992.3-21046.6" + wire width 7 $1\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:20717.3-20771.6" + wire $1\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:20772.3-20826.6" + wire $1\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:21102.3-21156.6" + wire $1\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:20442.3-20496.6" + wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:21212.3-21266.6" + wire $1\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:21542.3-21596.6" + wire width 2 $1\dec31_dec_sub11_out_sel[1:0] + attribute \src "libresoc.v:20552.3-20606.6" + wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:21047.3-21101.6" + wire $1\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:21267.3-21321.6" + wire $1\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:21157.3-21211.6" + wire $1\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:20937.3-20991.6" + wire $1\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:20497.3-20551.6" + wire width 2 $1\dec31_dec_sub11_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub11_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub11_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub11_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub11_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub11_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub11_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub11_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub11_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub11_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub11_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub11_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub11_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub11_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub11_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub11_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub11_upd + attribute \src "libresoc.v:20130.7-20130.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:20130.7-20130.20" + process $proc$libresoc.v:20130$481 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20387.3-20441.6" + process $proc$libresoc.v:20387$457 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_function_unit[11:0] $1\dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:20388.5-20388.29" + switch \initial + attribute \src "libresoc.v:20388.9-20388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + case + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[11:0] + end + attribute \src "libresoc.v:20442.3-20496.6" + process $proc$libresoc.v:20442$458 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:20443.5-20443.29" + switch \initial + attribute \src "libresoc.v:20443.9-20443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] + end + attribute \src "libresoc.v:20497.3-20551.6" + process $proc$libresoc.v:20497$459 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] + attribute \src "libresoc.v:20498.5-20498.29" + switch \initial + attribute \src "libresoc.v:20498.9-20498.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] + end + attribute \src "libresoc.v:20552.3-20606.6" + process $proc$libresoc.v:20552$460 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:20553.5-20553.29" + switch \initial + attribute \src "libresoc.v:20553.9-20553.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] + end + attribute \src "libresoc.v:20607.3-20661.6" + process $proc$libresoc.v:20607$461 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:20608.5-20608.29" + switch \initial + attribute \src "libresoc.v:20608.9-20608.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] + end + attribute \src "libresoc.v:20662.3-20716.6" + process $proc$libresoc.v:20662$462 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:20663.5-20663.29" + switch \initial + attribute \src "libresoc.v:20663.9-20663.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000010 + case + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] + end + attribute \src "libresoc.v:20717.3-20771.6" + process $proc$libresoc.v:20717$463 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:20718.5-20718.29" + switch \initial + attribute \src "libresoc.v:20718.9-20718.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] + end + attribute \src "libresoc.v:20772.3-20826.6" + process $proc$libresoc.v:20772$464 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:20773.5-20773.29" + switch \initial + attribute \src "libresoc.v:20773.9-20773.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] + end + attribute \src "libresoc.v:20827.3-20881.6" + process $proc$libresoc.v:20827$465 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:20828.5-20828.29" + switch \initial + attribute \src "libresoc.v:20828.9-20828.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] + end + attribute \src "libresoc.v:20882.3-20936.6" + process $proc$libresoc.v:20882$466 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:20883.5-20883.29" + switch \initial + attribute \src "libresoc.v:20883.9-20883.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + case + assign $1\dec31_dec_sub11_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] + end + attribute \src "libresoc.v:20937.3-20991.6" + process $proc$libresoc.v:20937$467 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:20938.5-20938.29" + switch \initial + attribute \src "libresoc.v:20938.9-20938.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] + end + attribute \src "libresoc.v:20992.3-21046.6" + process $proc$libresoc.v:20992$468 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:20993.5-20993.29" + switch \initial + attribute \src "libresoc.v:20993.9-20993.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + case + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] + end + attribute \src "libresoc.v:21047.3-21101.6" + process $proc$libresoc.v:21047$469 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:21048.5-21048.29" + switch \initial + attribute \src "libresoc.v:21048.9-21048.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] + end + attribute \src "libresoc.v:21102.3-21156.6" + process $proc$libresoc.v:21102$470 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:21103.5-21103.29" + switch \initial + attribute \src "libresoc.v:21103.9-21103.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub11_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] + end + attribute \src "libresoc.v:21157.3-21211.6" + process $proc$libresoc.v:21157$471 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:21158.5-21158.29" + switch \initial + attribute \src "libresoc.v:21158.9-21158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] + end + attribute \src "libresoc.v:21212.3-21266.6" + process $proc$libresoc.v:21212$472 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:21213.5-21213.29" + switch \initial + attribute \src "libresoc.v:21213.9-21213.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] + end + attribute \src "libresoc.v:21267.3-21321.6" + process $proc$libresoc.v:21267$473 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:21268.5-21268.29" + switch \initial + attribute \src "libresoc.v:21268.9-21268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] + end + attribute \src "libresoc.v:21322.3-21376.6" + process $proc$libresoc.v:21322$474 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:21323.5-21323.29" + switch \initial + attribute \src "libresoc.v:21323.9-21323.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub11_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] + end + attribute \src "libresoc.v:21377.3-21431.6" + process $proc$libresoc.v:21377$475 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:21378.5-21378.29" + switch \initial + attribute \src "libresoc.v:21378.9-21378.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] + end + attribute \src "libresoc.v:21432.3-21486.6" + process $proc$libresoc.v:21432$476 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:21433.5-21433.29" + switch \initial + attribute \src "libresoc.v:21433.9-21433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] + end + attribute \src "libresoc.v:21487.3-21541.6" + process $proc$libresoc.v:21487$477 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:21488.5-21488.29" + switch \initial + attribute \src "libresoc.v:21488.9-21488.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] + end + attribute \src "libresoc.v:21542.3-21596.6" + process $proc$libresoc.v:21542$478 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_out_sel[1:0] $1\dec31_dec_sub11_out_sel[1:0] + attribute \src "libresoc.v:21543.5-21543.29" + switch \initial + attribute \src "libresoc.v:21543.9-21543.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub11_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_out_sel $0\dec31_dec_sub11_out_sel[1:0] + end + attribute \src "libresoc.v:21597.3-21651.6" + process $proc$libresoc.v:21597$479 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:21598.5-21598.29" + switch \initial + attribute \src "libresoc.v:21598.9-21598.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] + end + attribute \src "libresoc.v:21652.3-21706.6" + process $proc$libresoc.v:21652$480 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:21653.5-21653.29" + switch \initial + attribute \src "libresoc.v:21653.9-21653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:21712.1-24443.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15" +attribute \generator "nMigen" +module \dec31_dec_sub15 + attribute \src "libresoc.v:22485.3-22587.6" + wire width 8 $0\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:22897.3-22999.6" + wire $0\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:24236.3-24338.6" + wire width 3 $0\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:24339.3-24441.6" + wire width 3 $0\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:22382.3-22484.6" + wire width 2 $0\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:22794.3-22896.6" + wire $0\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:23721.3-23823.6" + wire width 5 $0\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:21970.3-22072.6" + wire width 12 $0\dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:23824.3-23926.6" + wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:23927.3-24029.6" + wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:24030.3-24132.6" + wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:23103.3-23205.6" + wire width 7 $0\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:22588.3-22690.6" + wire $0\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:22691.3-22793.6" + wire $0\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:23309.3-23411.6" + wire $0\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:22073.3-22175.6" + wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:23515.3-23617.6" + wire $0\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:24133.3-24235.6" + wire width 2 $0\dec31_dec_sub15_out_sel[1:0] + attribute \src "libresoc.v:22279.3-22381.6" + wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:23206.3-23308.6" + wire $0\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:23618.3-23720.6" + wire $0\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:23412.3-23514.6" + wire $0\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:23000.3-23102.6" + wire $0\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:22176.3-22278.6" + wire width 2 $0\dec31_dec_sub15_upd[1:0] + attribute \src "libresoc.v:21713.7-21713.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:22485.3-22587.6" + wire width 8 $1\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:22897.3-22999.6" + wire $1\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:24236.3-24338.6" + wire width 3 $1\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:24339.3-24441.6" + wire width 3 $1\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:22382.3-22484.6" + wire width 2 $1\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:22794.3-22896.6" + wire $1\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:23721.3-23823.6" + wire width 5 $1\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:21970.3-22072.6" + wire width 12 $1\dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:23824.3-23926.6" + wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:23927.3-24029.6" + wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:24030.3-24132.6" + wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:23103.3-23205.6" + wire width 7 $1\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:22588.3-22690.6" + wire $1\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:22691.3-22793.6" + wire $1\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:23309.3-23411.6" + wire $1\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:22073.3-22175.6" + wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:23515.3-23617.6" + wire $1\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:24133.3-24235.6" + wire width 2 $1\dec31_dec_sub15_out_sel[1:0] + attribute \src "libresoc.v:22279.3-22381.6" + wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:23206.3-23308.6" + wire $1\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:23618.3-23720.6" + wire $1\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:23412.3-23514.6" + wire $1\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:23000.3-23102.6" + wire $1\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:22176.3-22278.6" + wire width 2 $1\dec31_dec_sub15_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub15_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub15_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub15_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub15_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub15_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub15_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub15_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub15_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub15_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub15_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub15_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub15_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub15_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub15_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub15_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub15_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub15_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub15_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub15_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub15_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub15_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub15_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub15_upd + attribute \src "libresoc.v:21713.7-21713.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:21713.7-21713.20" + process $proc$libresoc.v:21713$506 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:21970.3-22072.6" + process $proc$libresoc.v:21970$482 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_function_unit[11:0] $1\dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:21971.5-21971.29" + switch \initial + attribute \src "libresoc.v:21971.9-21971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + case + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[11:0] + end + attribute \src "libresoc.v:22073.3-22175.6" + process $proc$libresoc.v:22073$483 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:22074.5-22074.29" + switch \initial + attribute \src "libresoc.v:22074.9-22074.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] + end + attribute \src "libresoc.v:22176.3-22278.6" + process $proc$libresoc.v:22176$484 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] + attribute \src "libresoc.v:22177.5-22177.29" + switch \initial + attribute \src "libresoc.v:22177.9-22177.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] + end + attribute \src "libresoc.v:22279.3-22381.6" + process $proc$libresoc.v:22279$485 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:22280.5-22280.29" + switch \initial + attribute \src "libresoc.v:22280.9-22280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] + end + attribute \src "libresoc.v:22382.3-22484.6" + process $proc$libresoc.v:22382$486 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:22383.5-22383.29" + switch \initial + attribute \src "libresoc.v:22383.9-22383.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] + end + attribute \src "libresoc.v:22485.3-22587.6" + process $proc$libresoc.v:22485$487 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:22486.5-22486.29" + switch \initial + attribute \src "libresoc.v:22486.9-22486.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + case + assign $1\dec31_dec_sub15_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] + end + attribute \src "libresoc.v:22588.3-22690.6" + process $proc$libresoc.v:22588$488 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:22589.5-22589.29" + switch \initial + attribute \src "libresoc.v:22589.9-22589.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] + end + attribute \src "libresoc.v:22691.3-22793.6" + process $proc$libresoc.v:22691$489 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:22692.5-22692.29" + switch \initial + attribute \src "libresoc.v:22692.9-22692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] + end + attribute \src "libresoc.v:22794.3-22896.6" + process $proc$libresoc.v:22794$490 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:22795.5-22795.29" + switch \initial + attribute \src "libresoc.v:22795.9-22795.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] + end + attribute \src "libresoc.v:22897.3-22999.6" + process $proc$libresoc.v:22897$491 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:22898.5-22898.29" + switch \initial + attribute \src "libresoc.v:22898.9-22898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + case + assign $1\dec31_dec_sub15_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] + end + attribute \src "libresoc.v:23000.3-23102.6" + process $proc$libresoc.v:23000$492 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:23001.5-23001.29" + switch \initial + attribute \src "libresoc.v:23001.9-23001.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] + end + attribute \src "libresoc.v:23103.3-23205.6" + process $proc$libresoc.v:23103$493 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:23104.5-23104.29" + switch \initial + attribute \src "libresoc.v:23104.9-23104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + case + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] + end + attribute \src "libresoc.v:23206.3-23308.6" + process $proc$libresoc.v:23206$494 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:23207.5-23207.29" + switch \initial + attribute \src "libresoc.v:23207.9-23207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] + end + attribute \src "libresoc.v:23309.3-23411.6" + process $proc$libresoc.v:23309$495 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:23310.5-23310.29" + switch \initial + attribute \src "libresoc.v:23310.9-23310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] + end + attribute \src "libresoc.v:23412.3-23514.6" + process $proc$libresoc.v:23412$496 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:23413.5-23413.29" + switch \initial + attribute \src "libresoc.v:23413.9-23413.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] + end + attribute \src "libresoc.v:23515.3-23617.6" + process $proc$libresoc.v:23515$497 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:23516.5-23516.29" + switch \initial + attribute \src "libresoc.v:23516.9-23516.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] + end + attribute \src "libresoc.v:23618.3-23720.6" + process $proc$libresoc.v:23618$498 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:23619.5-23619.29" + switch \initial + attribute \src "libresoc.v:23619.9-23619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] + end + attribute \src "libresoc.v:23721.3-23823.6" + process $proc$libresoc.v:23721$499 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:23722.5-23722.29" + switch \initial + attribute \src "libresoc.v:23722.9-23722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + case + assign $1\dec31_dec_sub15_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] + end + attribute \src "libresoc.v:23824.3-23926.6" + process $proc$libresoc.v:23824$500 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:23825.5-23825.29" + switch \initial + attribute \src "libresoc.v:23825.9-23825.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] + end + attribute \src "libresoc.v:23927.3-24029.6" + process $proc$libresoc.v:23927$501 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:23928.5-23928.29" + switch \initial + attribute \src "libresoc.v:23928.9-23928.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] + end + attribute \src "libresoc.v:24030.3-24132.6" + process $proc$libresoc.v:24030$502 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:24031.5-24031.29" + switch \initial + attribute \src "libresoc.v:24031.9-24031.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] + end + attribute \src "libresoc.v:24133.3-24235.6" + process $proc$libresoc.v:24133$503 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_out_sel[1:0] $1\dec31_dec_sub15_out_sel[1:0] + attribute \src "libresoc.v:24134.5-24134.29" + switch \initial + attribute \src "libresoc.v:24134.9-24134.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub15_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_out_sel $0\dec31_dec_sub15_out_sel[1:0] + end + attribute \src "libresoc.v:24236.3-24338.6" + process $proc$libresoc.v:24236$504 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:24237.5-24237.29" + switch \initial + attribute \src "libresoc.v:24237.9-24237.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + case + assign $1\dec31_dec_sub15_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] + end + attribute \src "libresoc.v:24339.3-24441.6" + process $proc$libresoc.v:24339$505 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:24340.5-24340.29" + switch \initial + attribute \src "libresoc.v:24340.9-24340.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:24447.1-24946.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16" +attribute \generator "nMigen" +module \dec31_dec_sub16 + attribute \src "libresoc.v:24755.3-24764.6" + wire width 8 $0\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:24795.3-24804.6" + wire $0\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:24925.3-24934.6" + wire width 3 $0\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:24935.3-24944.6" + wire width 3 $0\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:24745.3-24754.6" + wire width 2 $0\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:24785.3-24794.6" + wire $0\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:24875.3-24884.6" + wire width 5 $0\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:24705.3-24714.6" + wire width 12 $0\dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:24885.3-24894.6" + wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:24895.3-24904.6" + wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:24905.3-24914.6" + wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:24815.3-24824.6" + wire width 7 $0\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:24765.3-24774.6" + wire $0\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:24775.3-24784.6" + wire $0\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:24835.3-24844.6" + wire $0\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:24715.3-24724.6" + wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:24855.3-24864.6" + wire $0\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:24915.3-24924.6" + wire width 2 $0\dec31_dec_sub16_out_sel[1:0] + attribute \src "libresoc.v:24735.3-24744.6" + wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:24825.3-24834.6" + wire $0\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:24865.3-24874.6" + wire $0\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:24845.3-24854.6" + wire $0\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:24805.3-24814.6" + wire $0\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:24725.3-24734.6" + wire width 2 $0\dec31_dec_sub16_upd[1:0] + attribute \src "libresoc.v:24448.7-24448.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:24755.3-24764.6" + wire width 8 $1\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:24795.3-24804.6" + wire $1\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:24925.3-24934.6" + wire width 3 $1\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:24935.3-24944.6" + wire width 3 $1\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:24745.3-24754.6" + wire width 2 $1\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:24785.3-24794.6" + wire $1\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:24875.3-24884.6" + wire width 5 $1\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:24705.3-24714.6" + wire width 12 $1\dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:24885.3-24894.6" + wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:24895.3-24904.6" + wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:24905.3-24914.6" + wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:24815.3-24824.6" + wire width 7 $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:24765.3-24774.6" + wire $1\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:24775.3-24784.6" + wire $1\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:24835.3-24844.6" + wire $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:24715.3-24724.6" + wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:24855.3-24864.6" + wire $1\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:24915.3-24924.6" + wire width 2 $1\dec31_dec_sub16_out_sel[1:0] + attribute \src "libresoc.v:24735.3-24744.6" + wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:24825.3-24834.6" + wire $1\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:24865.3-24874.6" + wire $1\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:24845.3-24854.6" + wire $1\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:24805.3-24814.6" + wire $1\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:24725.3-24734.6" + wire width 2 $1\dec31_dec_sub16_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub16_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub16_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub16_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub16_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub16_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub16_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub16_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub16_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub16_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub16_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub16_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub16_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub16_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub16_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub16_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub16_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub16_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub16_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub16_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub16_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub16_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub16_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub16_upd + attribute \src "libresoc.v:24448.7-24448.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:24448.7-24448.20" + process $proc$libresoc.v:24448$531 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:24705.3-24714.6" + process $proc$libresoc.v:24705$507 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_function_unit[11:0] $1\dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:24706.5-24706.29" + switch \initial + attribute \src "libresoc.v:24706.9-24706.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_function_unit[11:0] 12'000001000000 + case + assign $1\dec31_dec_sub16_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[11:0] + end + attribute \src "libresoc.v:24715.3-24724.6" + process $proc$libresoc.v:24715$508 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:24716.5-24716.29" + switch \initial + attribute \src "libresoc.v:24716.9-24716.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] + end + attribute \src "libresoc.v:24725.3-24734.6" + process $proc$libresoc.v:24725$509 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] + attribute \src "libresoc.v:24726.5-24726.29" + switch \initial + attribute \src "libresoc.v:24726.9-24726.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub16_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] + end + attribute \src "libresoc.v:24735.3-24744.6" + process $proc$libresoc.v:24735$510 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:24736.5-24736.29" + switch \initial + attribute \src "libresoc.v:24736.9-24736.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] + end + attribute \src "libresoc.v:24745.3-24754.6" + process $proc$libresoc.v:24745$511 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:24746.5-24746.29" + switch \initial + attribute \src "libresoc.v:24746.9-24746.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] + end + attribute \src "libresoc.v:24755.3-24764.6" + process $proc$libresoc.v:24755$512 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:24756.5-24756.29" + switch \initial + attribute \src "libresoc.v:24756.9-24756.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_asmcode[7:0] 8'01110110 + case + assign $1\dec31_dec_sub16_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] + end + attribute \src "libresoc.v:24765.3-24774.6" + process $proc$libresoc.v:24765$513 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:24766.5-24766.29" + switch \initial + attribute \src "libresoc.v:24766.9-24766.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] + end + attribute \src "libresoc.v:24775.3-24784.6" + process $proc$libresoc.v:24775$514 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:24776.5-24776.29" + switch \initial + attribute \src "libresoc.v:24776.9-24776.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] + end + attribute \src "libresoc.v:24785.3-24794.6" + process $proc$libresoc.v:24785$515 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:24786.5-24786.29" + switch \initial + attribute \src "libresoc.v:24786.9-24786.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] + end + attribute \src "libresoc.v:24795.3-24804.6" + process $proc$libresoc.v:24795$516 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:24796.5-24796.29" + switch \initial + attribute \src "libresoc.v:24796.9-24796.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_br[0:0] 1'0 + case + assign $1\dec31_dec_sub16_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] + end + attribute \src "libresoc.v:24805.3-24814.6" + process $proc$libresoc.v:24805$517 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:24806.5-24806.29" + switch \initial + attribute \src "libresoc.v:24806.9-24806.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] + end + attribute \src "libresoc.v:24815.3-24824.6" + process $proc$libresoc.v:24815$518 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:24816.5-24816.29" + switch \initial + attribute \src "libresoc.v:24816.9-24816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0110000 + case + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] + end + attribute \src "libresoc.v:24825.3-24834.6" + process $proc$libresoc.v:24825$519 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:24826.5-24826.29" + switch \initial + attribute \src "libresoc.v:24826.9-24826.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] + end + attribute \src "libresoc.v:24835.3-24844.6" + process $proc$libresoc.v:24835$520 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:24836.5-24836.29" + switch \initial + attribute \src "libresoc.v:24836.9-24836.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] + end + attribute \src "libresoc.v:24845.3-24854.6" + process $proc$libresoc.v:24845$521 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:24846.5-24846.29" + switch \initial + attribute \src "libresoc.v:24846.9-24846.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] + end + attribute \src "libresoc.v:24855.3-24864.6" + process $proc$libresoc.v:24855$522 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:24856.5-24856.29" + switch \initial + attribute \src "libresoc.v:24856.9-24856.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub16_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] + end + attribute \src "libresoc.v:24865.3-24874.6" + process $proc$libresoc.v:24865$523 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:24866.5-24866.29" + switch \initial + attribute \src "libresoc.v:24866.9-24866.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] + end + attribute \src "libresoc.v:24875.3-24884.6" + process $proc$libresoc.v:24875$524 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:24876.5-24876.29" + switch \initial + attribute \src "libresoc.v:24876.9-24876.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_form[4:0] 5'01010 + case + assign $1\dec31_dec_sub16_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] + end + attribute \src "libresoc.v:24885.3-24894.6" + process $proc$libresoc.v:24885$525 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:24886.5-24886.29" + switch \initial + attribute \src "libresoc.v:24886.9-24886.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub16_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] + end + attribute \src "libresoc.v:24895.3-24904.6" + process $proc$libresoc.v:24895$526 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:24896.5-24896.29" + switch \initial + attribute \src "libresoc.v:24896.9-24896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] + end + attribute \src "libresoc.v:24905.3-24914.6" + process $proc$libresoc.v:24905$527 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:24906.5-24906.29" + switch \initial + attribute \src "libresoc.v:24906.9-24906.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] + end + attribute \src "libresoc.v:24915.3-24924.6" + process $proc$libresoc.v:24915$528 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_out_sel[1:0] $1\dec31_dec_sub16_out_sel[1:0] + attribute \src "libresoc.v:24916.5-24916.29" + switch \initial + attribute \src "libresoc.v:24916.9-24916.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_out_sel $0\dec31_dec_sub16_out_sel[1:0] + end + attribute \src "libresoc.v:24925.3-24934.6" + process $proc$libresoc.v:24925$529 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:24926.5-24926.29" + switch \initial + attribute \src "libresoc.v:24926.9-24926.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cr_in[2:0] 3'110 + case + assign $1\dec31_dec_sub16_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] + end + attribute \src "libresoc.v:24935.3-24944.6" + process $proc$libresoc.v:24935$530 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:24936.5-24936.29" + switch \initial + attribute \src "libresoc.v:24936.9-24936.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cr_out[2:0] 3'100 + case + assign $1\dec31_dec_sub16_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:24950.1-25737.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" +attribute \generator "nMigen" +module \dec31_dec_sub18 + attribute \src "libresoc.v:25318.3-25339.6" + wire width 8 $0\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:25406.3-25427.6" + wire $0\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:25692.3-25713.6" + wire width 3 $0\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:25714.3-25735.6" + wire width 3 $0\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:25296.3-25317.6" + wire width 2 $0\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:25384.3-25405.6" + wire $0\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:25582.3-25603.6" + wire width 5 $0\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:25208.3-25229.6" + wire width 12 $0\dec31_dec_sub18_function_unit[11:0] + attribute \src "libresoc.v:25604.3-25625.6" + wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:25626.3-25647.6" + wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:25648.3-25669.6" + wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:25450.3-25471.6" + wire width 7 $0\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:25340.3-25361.6" + wire $0\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:25362.3-25383.6" + wire $0\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:25494.3-25515.6" + wire $0\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:25230.3-25251.6" + wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:25538.3-25559.6" + wire $0\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:25670.3-25691.6" + wire width 2 $0\dec31_dec_sub18_out_sel[1:0] + attribute \src "libresoc.v:25274.3-25295.6" + wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:25472.3-25493.6" + wire $0\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:25560.3-25581.6" + wire $0\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:25516.3-25537.6" + wire $0\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:25428.3-25449.6" + wire $0\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:25252.3-25273.6" + wire width 2 $0\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:24951.7-24951.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:25318.3-25339.6" + wire width 8 $1\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:25406.3-25427.6" + wire $1\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:25692.3-25713.6" + wire width 3 $1\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:25714.3-25735.6" + wire width 3 $1\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:25296.3-25317.6" + wire width 2 $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:25384.3-25405.6" + wire $1\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:25582.3-25603.6" + wire width 5 $1\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:25208.3-25229.6" + wire width 12 $1\dec31_dec_sub18_function_unit[11:0] + attribute \src "libresoc.v:25604.3-25625.6" + wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:25626.3-25647.6" + wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:25648.3-25669.6" + wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:25450.3-25471.6" + wire width 7 $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:25340.3-25361.6" + wire $1\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:25362.3-25383.6" + wire $1\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:25494.3-25515.6" + wire $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:25230.3-25251.6" + wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:25538.3-25559.6" + wire $1\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:25670.3-25691.6" + wire width 2 $1\dec31_dec_sub18_out_sel[1:0] + attribute \src "libresoc.v:25274.3-25295.6" + wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:25472.3-25493.6" + wire $1\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:25560.3-25581.6" + wire $1\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:25516.3-25537.6" + wire $1\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:25428.3-25449.6" + wire $1\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:25252.3-25273.6" + wire width 2 $1\dec31_dec_sub18_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub18_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub18_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub18_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub18_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub18_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub18_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub18_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub18_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub18_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub18_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub18_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub18_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub18_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub18_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub18_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub18_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub18_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub18_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub18_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub18_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub18_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub18_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub18_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub18_upd + attribute \src "libresoc.v:24951.7-24951.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:24951.7-24951.20" + process $proc$libresoc.v:24951$556 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:25208.3-25229.6" + process $proc$libresoc.v:25208$532 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_function_unit[11:0] $1\dec31_dec_sub18_function_unit[11:0] + attribute \src "libresoc.v:25209.5-25209.29" + switch \initial + attribute \src "libresoc.v:25209.9-25209.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 + case + assign $1\dec31_dec_sub18_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[11:0] + end + attribute \src "libresoc.v:25230.3-25251.6" + process $proc$libresoc.v:25230$533 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:25231.5-25231.29" + switch \initial + attribute \src "libresoc.v:25231.9-25231.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] + end + attribute \src "libresoc.v:25252.3-25273.6" + process $proc$libresoc.v:25252$534 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:25253.5-25253.29" + switch \initial + attribute \src "libresoc.v:25253.9-25253.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] + end + attribute \src "libresoc.v:25274.3-25295.6" + process $proc$libresoc.v:25274$535 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:25275.5-25275.29" + switch \initial + attribute \src "libresoc.v:25275.9-25275.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] + end + attribute \src "libresoc.v:25296.3-25317.6" + process $proc$libresoc.v:25296$536 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:25297.5-25297.29" + switch \initial + attribute \src "libresoc.v:25297.9-25297.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] + end + attribute \src "libresoc.v:25318.3-25339.6" + process $proc$libresoc.v:25318$537 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:25319.5-25319.29" + switch \initial + attribute \src "libresoc.v:25319.9-25319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'01111000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'01110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'10011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001101 + case + assign $1\dec31_dec_sub18_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] + end + attribute \src "libresoc.v:25340.3-25361.6" + process $proc$libresoc.v:25340$538 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:25341.5-25341.29" + switch \initial + attribute \src "libresoc.v:25341.9-25341.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] + end + attribute \src "libresoc.v:25362.3-25383.6" + process $proc$libresoc.v:25362$539 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:25363.5-25363.29" + switch \initial + attribute \src "libresoc.v:25363.9-25363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] + end + attribute \src "libresoc.v:25384.3-25405.6" + process $proc$libresoc.v:25384$540 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:25385.5-25385.29" + switch \initial + attribute \src "libresoc.v:25385.9-25385.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] + end + attribute \src "libresoc.v:25406.3-25427.6" + process $proc$libresoc.v:25406$541 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:25407.5-25407.29" + switch \initial + attribute \src "libresoc.v:25407.9-25407.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + case + assign $1\dec31_dec_sub18_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] + end + attribute \src "libresoc.v:25428.3-25449.6" + process $proc$libresoc.v:25428$542 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:25429.5-25429.29" + switch \initial + attribute \src "libresoc.v:25429.9-25429.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] + end + attribute \src "libresoc.v:25450.3-25471.6" + process $proc$libresoc.v:25450$543 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:25451.5-25451.29" + switch \initial + attribute \src "libresoc.v:25451.9-25451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + case + assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] + end + attribute \src "libresoc.v:25472.3-25493.6" + process $proc$libresoc.v:25472$544 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:25473.5-25473.29" + switch \initial + attribute \src "libresoc.v:25473.9-25473.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] + end + attribute \src "libresoc.v:25494.3-25515.6" + process $proc$libresoc.v:25494$545 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:25495.5-25495.29" + switch \initial + attribute \src "libresoc.v:25495.9-25495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] + end + attribute \src "libresoc.v:25516.3-25537.6" + process $proc$libresoc.v:25516$546 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:25517.5-25517.29" + switch \initial + attribute \src "libresoc.v:25517.9-25517.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] + end + attribute \src "libresoc.v:25538.3-25559.6" + process $proc$libresoc.v:25538$547 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:25539.5-25539.29" + switch \initial + attribute \src "libresoc.v:25539.9-25539.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] + end + attribute \src "libresoc.v:25560.3-25581.6" + process $proc$libresoc.v:25560$548 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:25561.5-25561.29" + switch \initial + attribute \src "libresoc.v:25561.9-25561.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] + end + attribute \src "libresoc.v:25582.3-25603.6" + process $proc$libresoc.v:25582$549 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:25583.5-25583.29" + switch \initial + attribute \src "libresoc.v:25583.9-25583.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub18_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] + end + attribute \src "libresoc.v:25604.3-25625.6" + process $proc$libresoc.v:25604$550 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:25605.5-25605.29" + switch \initial + attribute \src "libresoc.v:25605.9-25605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] + end + attribute \src "libresoc.v:25626.3-25647.6" + process $proc$libresoc.v:25626$551 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:25627.5-25627.29" + switch \initial + attribute \src "libresoc.v:25627.9-25627.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] + end + attribute \src "libresoc.v:25648.3-25669.6" + process $proc$libresoc.v:25648$552 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:25649.5-25649.29" + switch \initial + attribute \src "libresoc.v:25649.9-25649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] + end + attribute \src "libresoc.v:25670.3-25691.6" + process $proc$libresoc.v:25670$553 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_out_sel[1:0] $1\dec31_dec_sub18_out_sel[1:0] + attribute \src "libresoc.v:25671.5-25671.29" + switch \initial + attribute \src "libresoc.v:25671.9-25671.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[1:0] + end + attribute \src "libresoc.v:25692.3-25713.6" + process $proc$libresoc.v:25692$554 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:25693.5-25693.29" + switch \initial + attribute \src "libresoc.v:25693.9-25693.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] + end + attribute \src "libresoc.v:25714.3-25735.6" + process $proc$libresoc.v:25714$555 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:25715.5-25715.29" + switch \initial + attribute \src "libresoc.v:25715.9-25715.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:25741.1-26456.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" +attribute \generator "nMigen" +module \dec31_dec_sub19 + attribute \src "libresoc.v:26094.3-26112.6" + wire width 8 $0\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:26170.3-26188.6" + wire $0\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:26417.3-26435.6" + wire width 3 $0\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:26436.3-26454.6" + wire width 3 $0\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:26075.3-26093.6" + wire width 2 $0\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:26151.3-26169.6" + wire $0\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:26322.3-26340.6" + wire width 5 $0\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:25999.3-26017.6" + wire width 12 $0\dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:26341.3-26359.6" + wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:26360.3-26378.6" + wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:26379.3-26397.6" + wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:26208.3-26226.6" + wire width 7 $0\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:26113.3-26131.6" + wire $0\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:26132.3-26150.6" + wire $0\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:26246.3-26264.6" + wire $0\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:26018.3-26036.6" + wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:26284.3-26302.6" + wire $0\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:26398.3-26416.6" + wire width 2 $0\dec31_dec_sub19_out_sel[1:0] + attribute \src "libresoc.v:26056.3-26074.6" + wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:26227.3-26245.6" + wire $0\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:26303.3-26321.6" + wire $0\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:26265.3-26283.6" + wire $0\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:26189.3-26207.6" + wire $0\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:26037.3-26055.6" + wire width 2 $0\dec31_dec_sub19_upd[1:0] + attribute \src "libresoc.v:25742.7-25742.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26094.3-26112.6" + wire width 8 $1\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:26170.3-26188.6" + wire $1\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:26417.3-26435.6" + wire width 3 $1\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:26436.3-26454.6" + wire width 3 $1\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:26075.3-26093.6" + wire width 2 $1\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:26151.3-26169.6" + wire $1\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:26322.3-26340.6" + wire width 5 $1\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:25999.3-26017.6" + wire width 12 $1\dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:26341.3-26359.6" + wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:26360.3-26378.6" + wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:26379.3-26397.6" + wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:26208.3-26226.6" + wire width 7 $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:26113.3-26131.6" + wire $1\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:26132.3-26150.6" + wire $1\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:26246.3-26264.6" + wire $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:26018.3-26036.6" + wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:26284.3-26302.6" + wire $1\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:26398.3-26416.6" + wire width 2 $1\dec31_dec_sub19_out_sel[1:0] + attribute \src "libresoc.v:26056.3-26074.6" + wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:26227.3-26245.6" + wire $1\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:26303.3-26321.6" + wire $1\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:26265.3-26283.6" + wire $1\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:26189.3-26207.6" + wire $1\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:26037.3-26055.6" + wire width 2 $1\dec31_dec_sub19_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub19_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub19_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub19_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub19_upd + attribute \src "libresoc.v:25742.7-25742.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:25742.7-25742.20" + process $proc$libresoc.v:25742$581 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:25999.3-26017.6" + process $proc$libresoc.v:25999$557 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_function_unit[11:0] $1\dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:26000.5-26000.29" + switch \initial + attribute \src "libresoc.v:26000.9-26000.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 + case + assign $1\dec31_dec_sub19_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[11:0] + end + attribute \src "libresoc.v:26018.3-26036.6" + process $proc$libresoc.v:26018$558 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:26019.5-26019.29" + switch \initial + attribute \src "libresoc.v:26019.9-26019.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] + end + attribute \src "libresoc.v:26037.3-26055.6" + process $proc$libresoc.v:26037$559 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] + attribute \src "libresoc.v:26038.5-26038.29" + switch \initial + attribute \src "libresoc.v:26038.9-26038.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] + end + attribute \src "libresoc.v:26056.3-26074.6" + process $proc$libresoc.v:26056$560 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:26057.5-26057.29" + switch \initial + attribute \src "libresoc.v:26057.9-26057.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] + end + attribute \src "libresoc.v:26075.3-26093.6" + process $proc$libresoc.v:26075$561 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:26076.5-26076.29" + switch \initial + attribute \src "libresoc.v:26076.9-26076.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] + end + attribute \src "libresoc.v:26094.3-26112.6" + process $proc$libresoc.v:26094$562 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:26095.5-26095.29" + switch \initial + attribute \src "libresoc.v:26095.9-26095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01111001 + case + assign $1\dec31_dec_sub19_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] + end + attribute \src "libresoc.v:26113.3-26131.6" + process $proc$libresoc.v:26113$563 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:26114.5-26114.29" + switch \initial + attribute \src "libresoc.v:26114.9-26114.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] + end + attribute \src "libresoc.v:26132.3-26150.6" + process $proc$libresoc.v:26132$564 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:26133.5-26133.29" + switch \initial + attribute \src "libresoc.v:26133.9-26133.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] + end + attribute \src "libresoc.v:26151.3-26169.6" + process $proc$libresoc.v:26151$565 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:26152.5-26152.29" + switch \initial + attribute \src "libresoc.v:26152.9-26152.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] + end + attribute \src "libresoc.v:26170.3-26188.6" + process $proc$libresoc.v:26170$566 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:26171.5-26171.29" + switch \initial + attribute \src "libresoc.v:26171.9-26171.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + case + assign $1\dec31_dec_sub19_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] + end + attribute \src "libresoc.v:26189.3-26207.6" + process $proc$libresoc.v:26189$567 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:26190.5-26190.29" + switch \initial + attribute \src "libresoc.v:26190.9-26190.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] + end + attribute \src "libresoc.v:26208.3-26226.6" + process $proc$libresoc.v:26208$568 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:26209.5-26209.29" + switch \initial + attribute \src "libresoc.v:26209.9-26209.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001 + case + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] + end + attribute \src "libresoc.v:26227.3-26245.6" + process $proc$libresoc.v:26227$569 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:26228.5-26228.29" + switch \initial + attribute \src "libresoc.v:26228.9-26228.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] + end + attribute \src "libresoc.v:26246.3-26264.6" + process $proc$libresoc.v:26246$570 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:26247.5-26247.29" + switch \initial + attribute \src "libresoc.v:26247.9-26247.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] + end + attribute \src "libresoc.v:26265.3-26283.6" + process $proc$libresoc.v:26265$571 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:26266.5-26266.29" + switch \initial + attribute \src "libresoc.v:26266.9-26266.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] + end + attribute \src "libresoc.v:26284.3-26302.6" + process $proc$libresoc.v:26284$572 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:26285.5-26285.29" + switch \initial + attribute \src "libresoc.v:26285.9-26285.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] + end + attribute \src "libresoc.v:26303.3-26321.6" + process $proc$libresoc.v:26303$573 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:26304.5-26304.29" + switch \initial + attribute \src "libresoc.v:26304.9-26304.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] + end + attribute \src "libresoc.v:26322.3-26340.6" + process $proc$libresoc.v:26322$574 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:26323.5-26323.29" + switch \initial + attribute \src "libresoc.v:26323.9-26323.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + case + assign $1\dec31_dec_sub19_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] + end + attribute \src "libresoc.v:26341.3-26359.6" + process $proc$libresoc.v:26341$575 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:26342.5-26342.29" + switch \initial + attribute \src "libresoc.v:26342.9-26342.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] + end + attribute \src "libresoc.v:26360.3-26378.6" + process $proc$libresoc.v:26360$576 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:26361.5-26361.29" + switch \initial + attribute \src "libresoc.v:26361.9-26361.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] + end + attribute \src "libresoc.v:26379.3-26397.6" + process $proc$libresoc.v:26379$577 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:26380.5-26380.29" + switch \initial + attribute \src "libresoc.v:26380.9-26380.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] + end + attribute \src "libresoc.v:26398.3-26416.6" + process $proc$libresoc.v:26398$578 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_out_sel[1:0] $1\dec31_dec_sub19_out_sel[1:0] + attribute \src "libresoc.v:26399.5-26399.29" + switch \initial + attribute \src "libresoc.v:26399.9-26399.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'11 + case + assign $1\dec31_dec_sub19_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[1:0] + end + attribute \src "libresoc.v:26417.3-26435.6" + process $proc$libresoc.v:26417$579 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:26418.5-26418.29" + switch \initial + attribute \src "libresoc.v:26418.9-26418.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] + end + attribute \src "libresoc.v:26436.3-26454.6" + process $proc$libresoc.v:26436$580 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:26437.5-26437.29" + switch \initial + attribute \src "libresoc.v:26437.9-26437.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:26460.1-27319.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" +attribute \generator "nMigen" +module \dec31_dec_sub20 + attribute \src "libresoc.v:26843.3-26867.6" + wire width 8 $0\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:26943.3-26967.6" + wire $0\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:27268.3-27292.6" + wire width 3 $0\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:27293.3-27317.6" + wire width 3 $0\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:26818.3-26842.6" + wire width 2 $0\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:26918.3-26942.6" + wire $0\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:27143.3-27167.6" + wire width 5 $0\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:26718.3-26742.6" + wire width 12 $0\dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:27168.3-27192.6" + wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:27193.3-27217.6" + wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:27218.3-27242.6" + wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:26993.3-27017.6" + wire width 7 $0\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:26868.3-26892.6" + wire $0\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:26893.3-26917.6" + wire $0\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:27043.3-27067.6" + wire $0\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:26743.3-26767.6" + wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:27093.3-27117.6" + wire $0\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:27243.3-27267.6" + wire width 2 $0\dec31_dec_sub20_out_sel[1:0] + attribute \src "libresoc.v:26793.3-26817.6" + wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:27018.3-27042.6" + wire $0\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:27118.3-27142.6" + wire $0\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:27068.3-27092.6" + wire $0\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:26968.3-26992.6" + wire $0\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:26768.3-26792.6" + wire width 2 $0\dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:26461.7-26461.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26843.3-26867.6" + wire width 8 $1\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:26943.3-26967.6" + wire $1\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:27268.3-27292.6" + wire width 3 $1\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:27293.3-27317.6" + wire width 3 $1\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:26818.3-26842.6" + wire width 2 $1\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:26918.3-26942.6" + wire $1\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:27143.3-27167.6" + wire width 5 $1\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:26718.3-26742.6" + wire width 12 $1\dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:27168.3-27192.6" + wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:27193.3-27217.6" + wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:27218.3-27242.6" + wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:26993.3-27017.6" + wire width 7 $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:26868.3-26892.6" + wire $1\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:26893.3-26917.6" + wire $1\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:27043.3-27067.6" + wire $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:26743.3-26767.6" + wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:27093.3-27117.6" + wire $1\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:27243.3-27267.6" + wire width 2 $1\dec31_dec_sub20_out_sel[1:0] + attribute \src "libresoc.v:26793.3-26817.6" + wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:27018.3-27042.6" + wire $1\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:27118.3-27142.6" + wire $1\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:27068.3-27092.6" + wire $1\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:26968.3-26992.6" + wire $1\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:26768.3-26792.6" + wire width 2 $1\dec31_dec_sub20_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub20_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub20_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub20_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub20_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub20_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub20_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub20_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub20_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub20_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub20_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub20_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub20_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub20_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub20_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub20_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub20_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub20_upd + attribute \src "libresoc.v:26461.7-26461.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:26461.7-26461.20" + process $proc$libresoc.v:26461$606 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26718.3-26742.6" + process $proc$libresoc.v:26718$582 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_function_unit[11:0] $1\dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:26719.5-26719.29" + switch \initial + attribute \src "libresoc.v:26719.9-26719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + case + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[11:0] + end + attribute \src "libresoc.v:26743.3-26767.6" + process $proc$libresoc.v:26743$583 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:26744.5-26744.29" + switch \initial + attribute \src "libresoc.v:26744.9-26744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + case + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] + end + attribute \src "libresoc.v:26768.3-26792.6" + process $proc$libresoc.v:26768$584 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:26769.5-26769.29" + switch \initial + attribute \src "libresoc.v:26769.9-26769.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] + end + attribute \src "libresoc.v:26793.3-26817.6" + process $proc$libresoc.v:26793$585 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:26794.5-26794.29" + switch \initial + attribute \src "libresoc.v:26794.9-26794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] + end + attribute \src "libresoc.v:26818.3-26842.6" + process $proc$libresoc.v:26818$586 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:26819.5-26819.29" + switch \initial + attribute \src "libresoc.v:26819.9-26819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] + end + attribute \src "libresoc.v:26843.3-26867.6" + process $proc$libresoc.v:26843$587 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:26844.5-26844.29" + switch \initial + attribute \src "libresoc.v:26844.9-26844.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01011001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'10101101 + case + assign $1\dec31_dec_sub20_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] + end + attribute \src "libresoc.v:26868.3-26892.6" + process $proc$libresoc.v:26868$588 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:26869.5-26869.29" + switch \initial + attribute \src "libresoc.v:26869.9-26869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] + end + attribute \src "libresoc.v:26893.3-26917.6" + process $proc$libresoc.v:26893$589 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:26894.5-26894.29" + switch \initial + attribute \src "libresoc.v:26894.9-26894.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] + end + attribute \src "libresoc.v:26918.3-26942.6" + process $proc$libresoc.v:26918$590 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:26919.5-26919.29" + switch \initial + attribute \src "libresoc.v:26919.9-26919.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] + end + attribute \src "libresoc.v:26943.3-26967.6" + process $proc$libresoc.v:26943$591 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:26944.5-26944.29" + switch \initial + attribute \src "libresoc.v:26944.9-26944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'1 + case + assign $1\dec31_dec_sub20_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] + end + attribute \src "libresoc.v:26968.3-26992.6" + process $proc$libresoc.v:26968$592 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:26969.5-26969.29" + switch \initial + attribute \src "libresoc.v:26969.9-26969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] + end + attribute \src "libresoc.v:26993.3-27017.6" + process $proc$libresoc.v:26993$593 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:26994.5-26994.29" + switch \initial + attribute \src "libresoc.v:26994.9-26994.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] + end + attribute \src "libresoc.v:27018.3-27042.6" + process $proc$libresoc.v:27018$594 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:27019.5-27019.29" + switch \initial + attribute \src "libresoc.v:27019.9-27019.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] + end + attribute \src "libresoc.v:27043.3-27067.6" + process $proc$libresoc.v:27043$595 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:27044.5-27044.29" + switch \initial + attribute \src "libresoc.v:27044.9-27044.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] + end + attribute \src "libresoc.v:27068.3-27092.6" + process $proc$libresoc.v:27068$596 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:27069.5-27069.29" + switch \initial + attribute \src "libresoc.v:27069.9-27069.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] + end + attribute \src "libresoc.v:27093.3-27117.6" + process $proc$libresoc.v:27093$597 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:27094.5-27094.29" + switch \initial + attribute \src "libresoc.v:27094.9-27094.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] + end + attribute \src "libresoc.v:27118.3-27142.6" + process $proc$libresoc.v:27118$598 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:27119.5-27119.29" + switch \initial + attribute \src "libresoc.v:27119.9-27119.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] + end + attribute \src "libresoc.v:27143.3-27167.6" + process $proc$libresoc.v:27143$599 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:27144.5-27144.29" + switch \initial + attribute \src "libresoc.v:27144.9-27144.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub20_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] + end + attribute \src "libresoc.v:27168.3-27192.6" + process $proc$libresoc.v:27168$600 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:27169.5-27169.29" + switch \initial + attribute \src "libresoc.v:27169.9-27169.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] + end + attribute \src "libresoc.v:27193.3-27217.6" + process $proc$libresoc.v:27193$601 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:27194.5-27194.29" + switch \initial + attribute \src "libresoc.v:27194.9-27194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] + end + attribute \src "libresoc.v:27218.3-27242.6" + process $proc$libresoc.v:27218$602 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:27219.5-27219.29" + switch \initial + attribute \src "libresoc.v:27219.9-27219.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] + end + attribute \src "libresoc.v:27243.3-27267.6" + process $proc$libresoc.v:27243$603 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_out_sel[1:0] $1\dec31_dec_sub20_out_sel[1:0] + attribute \src "libresoc.v:27244.5-27244.29" + switch \initial + attribute \src "libresoc.v:27244.9-27244.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[1:0] + end + attribute \src "libresoc.v:27268.3-27292.6" + process $proc$libresoc.v:27268$604 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:27269.5-27269.29" + switch \initial + attribute \src "libresoc.v:27269.9-27269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] + end + attribute \src "libresoc.v:27293.3-27317.6" + process $proc$libresoc.v:27293$605 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:27294.5-27294.29" + switch \initial + attribute \src "libresoc.v:27294.9-27294.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:27323.1-28740.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21" +attribute \generator "nMigen" +module \dec31_dec_sub21 + attribute \src "libresoc.v:28365.3-28395.6" + wire width 8 $0\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:27973.3-28021.6" + wire $0\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:28641.3-28689.6" + wire width 3 $0\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:28690.3-28738.6" + wire width 3 $0\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:27777.3-27825.6" + wire width 2 $0\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:27924.3-27972.6" + wire $0\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:28396.3-28444.6" + wire width 5 $0\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:27581.3-27629.6" + wire width 12 $0\dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:28445.3-28493.6" + wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:28494.3-28542.6" + wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:28543.3-28591.6" + wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:28120.3-28168.6" + wire width 7 $0\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:27826.3-27874.6" + wire $0\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:27875.3-27923.6" + wire $0\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:28169.3-28217.6" + wire $0\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:27630.3-27678.6" + wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:28267.3-28315.6" + wire $0\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:28592.3-28640.6" + wire width 2 $0\dec31_dec_sub21_out_sel[1:0] + attribute \src "libresoc.v:27728.3-27776.6" + wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:28071.3-28119.6" + wire $0\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:28316.3-28364.6" + wire $0\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:28218.3-28266.6" + wire $0\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:28022.3-28070.6" + wire $0\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:27679.3-27727.6" + wire width 2 $0\dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:27324.7-27324.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:28365.3-28395.6" + wire width 8 $1\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:27973.3-28021.6" + wire $1\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:28641.3-28689.6" + wire width 3 $1\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:28690.3-28738.6" + wire width 3 $1\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:27777.3-27825.6" + wire width 2 $1\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:27924.3-27972.6" + wire $1\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:28396.3-28444.6" + wire width 5 $1\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:27581.3-27629.6" + wire width 12 $1\dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:28445.3-28493.6" + wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:28494.3-28542.6" + wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:28543.3-28591.6" + wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:28120.3-28168.6" + wire width 7 $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:27826.3-27874.6" + wire $1\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:27875.3-27923.6" + wire $1\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:28169.3-28217.6" + wire $1\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:27630.3-27678.6" + wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:28267.3-28315.6" + wire $1\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:28592.3-28640.6" + wire width 2 $1\dec31_dec_sub21_out_sel[1:0] + attribute \src "libresoc.v:27728.3-27776.6" + wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:28071.3-28119.6" + wire $1\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:28316.3-28364.6" + wire $1\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:28218.3-28266.6" + wire $1\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:28022.3-28070.6" + wire $1\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:27679.3-27727.6" + wire width 2 $1\dec31_dec_sub21_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub21_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub21_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub21_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub21_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub21_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub21_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub21_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub21_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub21_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub21_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub21_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub21_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub21_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub21_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub21_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub21_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub21_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub21_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub21_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub21_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub21_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub21_upd + attribute \src "libresoc.v:27324.7-27324.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:27324.7-27324.20" + process $proc$libresoc.v:27324$631 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:27581.3-27629.6" + process $proc$libresoc.v:27581$607 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_function_unit[11:0] $1\dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:27582.5-27582.29" + switch \initial + attribute \src "libresoc.v:27582.9-27582.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + case + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[11:0] + end + attribute \src "libresoc.v:27630.3-27678.6" + process $proc$libresoc.v:27630$608 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:27631.5-27631.29" + switch \initial + attribute \src "libresoc.v:27631.9-27631.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + case + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] + end + attribute \src "libresoc.v:27679.3-27727.6" + process $proc$libresoc.v:27679$609 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:27680.5-27680.29" + switch \initial + attribute \src "libresoc.v:27680.9-27680.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + case + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] + end + attribute \src "libresoc.v:27728.3-27776.6" + process $proc$libresoc.v:27728$610 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:27729.5-27729.29" + switch \initial + attribute \src "libresoc.v:27729.9-27729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] + end + attribute \src "libresoc.v:27777.3-27825.6" + process $proc$libresoc.v:27777$611 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:27778.5-27778.29" + switch \initial + attribute \src "libresoc.v:27778.9-27778.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] + end + attribute \src "libresoc.v:27826.3-27874.6" + process $proc$libresoc.v:27826$612 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:27827.5-27827.29" + switch \initial + attribute \src "libresoc.v:27827.9-27827.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] + end + attribute \src "libresoc.v:27875.3-27923.6" + process $proc$libresoc.v:27875$613 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:27876.5-27876.29" + switch \initial + attribute \src "libresoc.v:27876.9-27876.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] + end + attribute \src "libresoc.v:27924.3-27972.6" + process $proc$libresoc.v:27924$614 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:27925.5-27925.29" + switch \initial + attribute \src "libresoc.v:27925.9-27925.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] + end + attribute \src "libresoc.v:27973.3-28021.6" + process $proc$libresoc.v:27973$615 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:27974.5-27974.29" + switch \initial + attribute \src "libresoc.v:27974.9-27974.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + case + assign $1\dec31_dec_sub21_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] + end + attribute \src "libresoc.v:28022.3-28070.6" + process $proc$libresoc.v:28022$616 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:28023.5-28023.29" + switch \initial + attribute \src "libresoc.v:28023.9-28023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] + end + attribute \src "libresoc.v:28071.3-28119.6" + process $proc$libresoc.v:28071$617 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:28072.5-28072.29" + switch \initial + attribute \src "libresoc.v:28072.9-28072.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] + end + attribute \src "libresoc.v:28120.3-28168.6" + process $proc$libresoc.v:28120$618 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:28121.5-28121.29" + switch \initial + attribute \src "libresoc.v:28121.9-28121.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] + end + attribute \src "libresoc.v:28169.3-28217.6" + process $proc$libresoc.v:28169$619 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:28170.5-28170.29" + switch \initial + attribute \src "libresoc.v:28170.9-28170.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] + end + attribute \src "libresoc.v:28218.3-28266.6" + process $proc$libresoc.v:28218$620 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:28219.5-28219.29" + switch \initial + attribute \src "libresoc.v:28219.9-28219.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] + end + attribute \src "libresoc.v:28267.3-28315.6" + process $proc$libresoc.v:28267$621 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:28268.5-28268.29" + switch \initial + attribute \src "libresoc.v:28268.9-28268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] + end + attribute \src "libresoc.v:28316.3-28364.6" + process $proc$libresoc.v:28316$622 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:28317.5-28317.29" + switch \initial + attribute \src "libresoc.v:28317.9-28317.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] + end + attribute \src "libresoc.v:28365.3-28395.6" + process $proc$libresoc.v:28365$623 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:28366.5-28366.29" + switch \initial + attribute \src "libresoc.v:28366.9-28366.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01101000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10100111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110001 + case + assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] + end + attribute \src "libresoc.v:28396.3-28444.6" + process $proc$libresoc.v:28396$624 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:28397.5-28397.29" + switch \initial + attribute \src "libresoc.v:28397.9-28397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub21_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] + end + attribute \src "libresoc.v:28445.3-28493.6" + process $proc$libresoc.v:28445$625 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:28446.5-28446.29" + switch \initial + attribute \src "libresoc.v:28446.9-28446.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] + end + attribute \src "libresoc.v:28494.3-28542.6" + process $proc$libresoc.v:28494$626 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:28495.5-28495.29" + switch \initial + attribute \src "libresoc.v:28495.9-28495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] + end + attribute \src "libresoc.v:28543.3-28591.6" + process $proc$libresoc.v:28543$627 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:28544.5-28544.29" + switch \initial + attribute \src "libresoc.v:28544.9-28544.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] + end + attribute \src "libresoc.v:28592.3-28640.6" + process $proc$libresoc.v:28592$628 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_out_sel[1:0] $1\dec31_dec_sub21_out_sel[1:0] + attribute \src "libresoc.v:28593.5-28593.29" + switch \initial + attribute \src "libresoc.v:28593.9-28593.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_out_sel $0\dec31_dec_sub21_out_sel[1:0] + end + attribute \src "libresoc.v:28641.3-28689.6" + process $proc$libresoc.v:28641$629 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:28642.5-28642.29" + switch \initial + attribute \src "libresoc.v:28642.9-28642.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] + end + attribute \src "libresoc.v:28690.3-28738.6" + process $proc$libresoc.v:28690$630 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:28691.5-28691.29" + switch \initial + attribute \src "libresoc.v:28691.9-28691.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:28744.1-30323.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" +attribute \generator "nMigen" +module \dec31_dec_sub22 + attribute \src "libresoc.v:29277.3-29331.6" + wire width 8 $0\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:29497.3-29551.6" + wire $0\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:30212.3-30266.6" + wire width 3 $0\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:30267.3-30321.6" + wire width 3 $0\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:29222.3-29276.6" + wire width 2 $0\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:29442.3-29496.6" + wire $0\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:29937.3-29991.6" + wire width 5 $0\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:29002.3-29056.6" + wire width 12 $0\dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:29992.3-30046.6" + wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:30047.3-30101.6" + wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:30102.3-30156.6" + wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:29607.3-29661.6" + wire width 7 $0\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:29332.3-29386.6" + wire $0\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:29387.3-29441.6" + wire $0\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:29717.3-29771.6" + wire $0\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:29057.3-29111.6" + wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:29827.3-29881.6" + wire $0\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:30157.3-30211.6" + wire width 2 $0\dec31_dec_sub22_out_sel[1:0] + attribute \src "libresoc.v:29167.3-29221.6" + wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:29662.3-29716.6" + wire $0\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:29882.3-29936.6" + wire $0\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:29772.3-29826.6" + wire $0\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:29552.3-29606.6" + wire $0\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:29112.3-29166.6" + wire width 2 $0\dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:28745.7-28745.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:29277.3-29331.6" + wire width 8 $1\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:29497.3-29551.6" + wire $1\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:30212.3-30266.6" + wire width 3 $1\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:30267.3-30321.6" + wire width 3 $1\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:29222.3-29276.6" + wire width 2 $1\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:29442.3-29496.6" + wire $1\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:29937.3-29991.6" + wire width 5 $1\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:29002.3-29056.6" + wire width 12 $1\dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:29992.3-30046.6" + wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:30047.3-30101.6" + wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:30102.3-30156.6" + wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:29607.3-29661.6" + wire width 7 $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:29332.3-29386.6" + wire $1\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:29387.3-29441.6" + wire $1\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:29717.3-29771.6" + wire $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:29057.3-29111.6" + wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:29827.3-29881.6" + wire $1\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:30157.3-30211.6" + wire width 2 $1\dec31_dec_sub22_out_sel[1:0] + attribute \src "libresoc.v:29167.3-29221.6" + wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:29662.3-29716.6" + wire $1\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:29882.3-29936.6" + wire $1\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:29772.3-29826.6" + wire $1\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:29552.3-29606.6" + wire $1\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:29112.3-29166.6" + wire width 2 $1\dec31_dec_sub22_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub22_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub22_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub22_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub22_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub22_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub22_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub22_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub22_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub22_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub22_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub22_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub22_upd + attribute \src "libresoc.v:28745.7-28745.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:28745.7-28745.20" + process $proc$libresoc.v:28745$656 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:29002.3-29056.6" + process $proc$libresoc.v:29002$632 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_function_unit[11:0] $1\dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:29003.5-29003.29" + switch \initial + attribute \src "libresoc.v:29003.9-29003.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + case + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[11:0] + end + attribute \src "libresoc.v:29057.3-29111.6" + process $proc$libresoc.v:29057$633 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:29058.5-29058.29" + switch \initial + attribute \src "libresoc.v:29058.9-29058.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] + end + attribute \src "libresoc.v:29112.3-29166.6" + process $proc$libresoc.v:29112$634 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:29113.5-29113.29" + switch \initial + attribute \src "libresoc.v:29113.9-29113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] + end + attribute \src "libresoc.v:29167.3-29221.6" + process $proc$libresoc.v:29167$635 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:29168.5-29168.29" + switch \initial + attribute \src "libresoc.v:29168.9-29168.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] + end + attribute \src "libresoc.v:29222.3-29276.6" + process $proc$libresoc.v:29222$636 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:29223.5-29223.29" + switch \initial + attribute \src "libresoc.v:29223.9-29223.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] + end + attribute \src "libresoc.v:29277.3-29331.6" + process $proc$libresoc.v:29277$637 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:29278.5-29278.29" + switch \initial + attribute \src "libresoc.v:29278.9-29278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'11001001 + case + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] + end + attribute \src "libresoc.v:29332.3-29386.6" + process $proc$libresoc.v:29332$638 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:29333.5-29333.29" + switch \initial + attribute \src "libresoc.v:29333.9-29333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] + end + attribute \src "libresoc.v:29387.3-29441.6" + process $proc$libresoc.v:29387$639 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:29388.5-29388.29" + switch \initial + attribute \src "libresoc.v:29388.9-29388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] + end + attribute \src "libresoc.v:29442.3-29496.6" + process $proc$libresoc.v:29442$640 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:29443.5-29443.29" + switch \initial + attribute \src "libresoc.v:29443.9-29443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] + end + attribute \src "libresoc.v:29497.3-29551.6" + process $proc$libresoc.v:29497$641 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:29498.5-29498.29" + switch \initial + attribute \src "libresoc.v:29498.9-29498.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + case + assign $1\dec31_dec_sub22_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] + end + attribute \src "libresoc.v:29552.3-29606.6" + process $proc$libresoc.v:29552$642 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:29553.5-29553.29" + switch \initial + attribute \src "libresoc.v:29553.9-29553.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] + end + attribute \src "libresoc.v:29607.3-29661.6" + process $proc$libresoc.v:29607$643 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:29608.5-29608.29" + switch \initial + attribute \src "libresoc.v:29608.9-29608.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + case + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] + end + attribute \src "libresoc.v:29662.3-29716.6" + process $proc$libresoc.v:29662$644 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:29663.5-29663.29" + switch \initial + attribute \src "libresoc.v:29663.9-29663.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] + end + attribute \src "libresoc.v:29717.3-29771.6" + process $proc$libresoc.v:29717$645 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:29718.5-29718.29" + switch \initial + attribute \src "libresoc.v:29718.9-29718.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] + end + attribute \src "libresoc.v:29772.3-29826.6" + process $proc$libresoc.v:29772$646 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:29773.5-29773.29" + switch \initial + attribute \src "libresoc.v:29773.9-29773.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] + end + attribute \src "libresoc.v:29827.3-29881.6" + process $proc$libresoc.v:29827$647 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:29828.5-29828.29" + switch \initial + attribute \src "libresoc.v:29828.9-29828.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] + end + attribute \src "libresoc.v:29882.3-29936.6" + process $proc$libresoc.v:29882$648 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:29883.5-29883.29" + switch \initial + attribute \src "libresoc.v:29883.9-29883.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] + end + attribute \src "libresoc.v:29937.3-29991.6" + process $proc$libresoc.v:29937$649 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:29938.5-29938.29" + switch \initial + attribute \src "libresoc.v:29938.9-29938.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub22_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] + end + attribute \src "libresoc.v:29992.3-30046.6" + process $proc$libresoc.v:29992$650 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:29993.5-29993.29" + switch \initial + attribute \src "libresoc.v:29993.9-29993.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] + end + attribute \src "libresoc.v:30047.3-30101.6" + process $proc$libresoc.v:30047$651 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:30048.5-30048.29" + switch \initial + attribute \src "libresoc.v:30048.9-30048.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] + end + attribute \src "libresoc.v:30102.3-30156.6" + process $proc$libresoc.v:30102$652 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:30103.5-30103.29" + switch \initial + attribute \src "libresoc.v:30103.9-30103.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] + end + attribute \src "libresoc.v:30157.3-30211.6" + process $proc$libresoc.v:30157$653 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_out_sel[1:0] $1\dec31_dec_sub22_out_sel[1:0] + attribute \src "libresoc.v:30158.5-30158.29" + switch \initial + attribute \src "libresoc.v:30158.9-30158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_out_sel $0\dec31_dec_sub22_out_sel[1:0] + end + attribute \src "libresoc.v:30212.3-30266.6" + process $proc$libresoc.v:30212$654 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:30213.5-30213.29" + switch \initial + attribute \src "libresoc.v:30213.9-30213.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] + end + attribute \src "libresoc.v:30267.3-30321.6" + process $proc$libresoc.v:30267$655 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:30268.5-30268.29" + switch \initial + attribute \src "libresoc.v:30268.9-30268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:30327.1-31762.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" +attribute \generator "nMigen" +module \dec31_dec_sub23 + attribute \src "libresoc.v:30830.3-30878.6" + wire width 8 $0\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:31026.3-31074.6" + wire $0\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:31663.3-31711.6" + wire width 3 $0\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:31712.3-31760.6" + wire width 3 $0\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:30781.3-30829.6" + wire width 2 $0\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:30977.3-31025.6" + wire $0\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:31418.3-31466.6" + wire width 5 $0\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:30585.3-30633.6" + wire width 12 $0\dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:31467.3-31515.6" + wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:31516.3-31564.6" + wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:31565.3-31613.6" + wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:31124.3-31172.6" + wire width 7 $0\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:30879.3-30927.6" + wire $0\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:30928.3-30976.6" + wire $0\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:31222.3-31270.6" + wire $0\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:30634.3-30682.6" + wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:31320.3-31368.6" + wire $0\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:31614.3-31662.6" + wire width 2 $0\dec31_dec_sub23_out_sel[1:0] + attribute \src "libresoc.v:30732.3-30780.6" + wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:31173.3-31221.6" + wire $0\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:31369.3-31417.6" + wire $0\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:31271.3-31319.6" + wire $0\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:31075.3-31123.6" + wire $0\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:30683.3-30731.6" + wire width 2 $0\dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:30328.7-30328.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:30830.3-30878.6" + wire width 8 $1\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:31026.3-31074.6" + wire $1\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:31663.3-31711.6" + wire width 3 $1\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:31712.3-31760.6" + wire width 3 $1\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:30781.3-30829.6" + wire width 2 $1\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:30977.3-31025.6" + wire $1\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:31418.3-31466.6" + wire width 5 $1\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:30585.3-30633.6" + wire width 12 $1\dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:31467.3-31515.6" + wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:31516.3-31564.6" + wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:31565.3-31613.6" + wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:31124.3-31172.6" + wire width 7 $1\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:30879.3-30927.6" + wire $1\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:30928.3-30976.6" + wire $1\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:31222.3-31270.6" + wire $1\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:30634.3-30682.6" + wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:31320.3-31368.6" + wire $1\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:31614.3-31662.6" + wire width 2 $1\dec31_dec_sub23_out_sel[1:0] + attribute \src "libresoc.v:30732.3-30780.6" + wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:31173.3-31221.6" + wire $1\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:31369.3-31417.6" + wire $1\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:31271.3-31319.6" + wire $1\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:31075.3-31123.6" + wire $1\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:30683.3-30731.6" + wire width 2 $1\dec31_dec_sub23_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub23_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub23_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub23_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub23_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub23_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub23_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub23_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub23_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub23_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub23_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub23_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub23_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub23_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub23_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub23_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub23_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub23_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub23_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub23_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub23_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub23_upd + attribute \src "libresoc.v:30328.7-30328.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:30328.7-30328.20" + process $proc$libresoc.v:30328$681 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:30585.3-30633.6" + process $proc$libresoc.v:30585$657 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_function_unit[11:0] $1\dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:30586.5-30586.29" + switch \initial + attribute \src "libresoc.v:30586.9-30586.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + case + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[11:0] + end + attribute \src "libresoc.v:30634.3-30682.6" + process $proc$libresoc.v:30634$658 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:30635.5-30635.29" + switch \initial + attribute \src "libresoc.v:30635.9-30635.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + case + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] + end + attribute \src "libresoc.v:30683.3-30731.6" + process $proc$libresoc.v:30683$659 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:30684.5-30684.29" + switch \initial + attribute \src "libresoc.v:30684.9-30684.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] + end + attribute \src "libresoc.v:30732.3-30780.6" + process $proc$libresoc.v:30732$660 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:30733.5-30733.29" + switch \initial + attribute \src "libresoc.v:30733.9-30733.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] + end + attribute \src "libresoc.v:30781.3-30829.6" + process $proc$libresoc.v:30781$661 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:30782.5-30782.29" + switch \initial + attribute \src "libresoc.v:30782.9-30782.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] + end + attribute \src "libresoc.v:30830.3-30878.6" + process $proc$libresoc.v:30830$662 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:30831.5-30831.29" + switch \initial + attribute \src "libresoc.v:30831.9-30831.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111101 + case + assign $1\dec31_dec_sub23_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] + end + attribute \src "libresoc.v:30879.3-30927.6" + process $proc$libresoc.v:30879$663 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:30880.5-30880.29" + switch \initial + attribute \src "libresoc.v:30880.9-30880.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] + end + attribute \src "libresoc.v:30928.3-30976.6" + process $proc$libresoc.v:30928$664 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:30929.5-30929.29" + switch \initial + attribute \src "libresoc.v:30929.9-30929.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] + end + attribute \src "libresoc.v:30977.3-31025.6" + process $proc$libresoc.v:30977$665 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:30978.5-30978.29" + switch \initial + attribute \src "libresoc.v:30978.9-30978.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] + end + attribute \src "libresoc.v:31026.3-31074.6" + process $proc$libresoc.v:31026$666 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:31027.5-31027.29" + switch \initial + attribute \src "libresoc.v:31027.9-31027.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + case + assign $1\dec31_dec_sub23_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] + end + attribute \src "libresoc.v:31075.3-31123.6" + process $proc$libresoc.v:31075$667 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:31076.5-31076.29" + switch \initial + attribute \src "libresoc.v:31076.9-31076.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] + end + attribute \src "libresoc.v:31124.3-31172.6" + process $proc$libresoc.v:31124$668 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:31125.5-31125.29" + switch \initial + attribute \src "libresoc.v:31125.9-31125.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] + end + attribute \src "libresoc.v:31173.3-31221.6" + process $proc$libresoc.v:31173$669 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:31174.5-31174.29" + switch \initial + attribute \src "libresoc.v:31174.9-31174.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] + end + attribute \src "libresoc.v:31222.3-31270.6" + process $proc$libresoc.v:31222$670 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:31223.5-31223.29" + switch \initial + attribute \src "libresoc.v:31223.9-31223.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] + end + attribute \src "libresoc.v:31271.3-31319.6" + process $proc$libresoc.v:31271$671 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:31272.5-31272.29" + switch \initial + attribute \src "libresoc.v:31272.9-31272.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] + end + attribute \src "libresoc.v:31320.3-31368.6" + process $proc$libresoc.v:31320$672 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:31321.5-31321.29" + switch \initial + attribute \src "libresoc.v:31321.9-31321.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] + end + attribute \src "libresoc.v:31369.3-31417.6" + process $proc$libresoc.v:31369$673 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:31370.5-31370.29" + switch \initial + attribute \src "libresoc.v:31370.9-31370.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] + end + attribute \src "libresoc.v:31418.3-31466.6" + process $proc$libresoc.v:31418$674 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:31419.5-31419.29" + switch \initial + attribute \src "libresoc.v:31419.9-31419.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub23_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] + end + attribute \src "libresoc.v:31467.3-31515.6" + process $proc$libresoc.v:31467$675 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:31468.5-31468.29" + switch \initial + attribute \src "libresoc.v:31468.9-31468.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] + end + attribute \src "libresoc.v:31516.3-31564.6" + process $proc$libresoc.v:31516$676 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:31517.5-31517.29" + switch \initial + attribute \src "libresoc.v:31517.9-31517.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] + end + attribute \src "libresoc.v:31565.3-31613.6" + process $proc$libresoc.v:31565$677 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:31566.5-31566.29" + switch \initial + attribute \src "libresoc.v:31566.9-31566.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] + end + attribute \src "libresoc.v:31614.3-31662.6" + process $proc$libresoc.v:31614$678 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_out_sel[1:0] $1\dec31_dec_sub23_out_sel[1:0] + attribute \src "libresoc.v:31615.5-31615.29" + switch \initial + attribute \src "libresoc.v:31615.9-31615.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_out_sel $0\dec31_dec_sub23_out_sel[1:0] + end + attribute \src "libresoc.v:31663.3-31711.6" + process $proc$libresoc.v:31663$679 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:31664.5-31664.29" + switch \initial + attribute \src "libresoc.v:31664.9-31664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] + end + attribute \src "libresoc.v:31712.3-31760.6" + process $proc$libresoc.v:31712$680 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:31713.5-31713.29" + switch \initial + attribute \src "libresoc.v:31713.9-31713.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:31766.1-32481.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" +attribute \generator "nMigen" +module \dec31_dec_sub24 + attribute \src "libresoc.v:32119.3-32137.6" + wire width 8 $0\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:32195.3-32213.6" + wire $0\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:32442.3-32460.6" + wire width 3 $0\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:32461.3-32479.6" + wire width 3 $0\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:32100.3-32118.6" + wire width 2 $0\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:32176.3-32194.6" + wire $0\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:32347.3-32365.6" + wire width 5 $0\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:32024.3-32042.6" + wire width 12 $0\dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:32366.3-32384.6" + wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:32385.3-32403.6" + wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:32404.3-32422.6" + wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:32233.3-32251.6" + wire width 7 $0\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:32138.3-32156.6" + wire $0\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:32157.3-32175.6" + wire $0\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:32271.3-32289.6" + wire $0\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:32043.3-32061.6" + wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:32309.3-32327.6" + wire $0\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:32423.3-32441.6" + wire width 2 $0\dec31_dec_sub24_out_sel[1:0] + attribute \src "libresoc.v:32081.3-32099.6" + wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:32252.3-32270.6" + wire $0\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:32328.3-32346.6" + wire $0\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:32290.3-32308.6" + wire $0\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:32214.3-32232.6" + wire $0\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:32062.3-32080.6" + wire width 2 $0\dec31_dec_sub24_upd[1:0] + attribute \src "libresoc.v:31767.7-31767.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:32119.3-32137.6" + wire width 8 $1\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:32195.3-32213.6" + wire $1\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:32442.3-32460.6" + wire width 3 $1\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:32461.3-32479.6" + wire width 3 $1\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:32100.3-32118.6" + wire width 2 $1\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:32176.3-32194.6" + wire $1\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:32347.3-32365.6" + wire width 5 $1\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:32024.3-32042.6" + wire width 12 $1\dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:32366.3-32384.6" + wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:32385.3-32403.6" + wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:32404.3-32422.6" + wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:32233.3-32251.6" + wire width 7 $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:32138.3-32156.6" + wire $1\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:32157.3-32175.6" + wire $1\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:32271.3-32289.6" + wire $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:32043.3-32061.6" + wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:32309.3-32327.6" + wire $1\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:32423.3-32441.6" + wire width 2 $1\dec31_dec_sub24_out_sel[1:0] + attribute \src "libresoc.v:32081.3-32099.6" + wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:32252.3-32270.6" + wire $1\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:32328.3-32346.6" + wire $1\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:32290.3-32308.6" + wire $1\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:32214.3-32232.6" + wire $1\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:32062.3-32080.6" + wire width 2 $1\dec31_dec_sub24_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub24_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub24_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub24_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub24_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub24_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub24_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub24_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub24_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub24_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub24_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub24_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub24_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub24_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub24_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub24_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub24_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub24_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub24_upd + attribute \src "libresoc.v:31767.7-31767.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:31767.7-31767.20" + process $proc$libresoc.v:31767$706 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:32024.3-32042.6" + process $proc$libresoc.v:32024$682 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_function_unit[11:0] $1\dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:32025.5-32025.29" + switch \initial + attribute \src "libresoc.v:32025.9-32025.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + case + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[11:0] + end + attribute \src "libresoc.v:32043.3-32061.6" + process $proc$libresoc.v:32043$683 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:32044.5-32044.29" + switch \initial + attribute \src "libresoc.v:32044.9-32044.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] + end + attribute \src "libresoc.v:32062.3-32080.6" + process $proc$libresoc.v:32062$684 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] + attribute \src "libresoc.v:32063.5-32063.29" + switch \initial + attribute \src "libresoc.v:32063.9-32063.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] + end + attribute \src "libresoc.v:32081.3-32099.6" + process $proc$libresoc.v:32081$685 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:32082.5-32082.29" + switch \initial + attribute \src "libresoc.v:32082.9-32082.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] + end + attribute \src "libresoc.v:32100.3-32118.6" + process $proc$libresoc.v:32100$686 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:32101.5-32101.29" + switch \initial + attribute \src "libresoc.v:32101.9-32101.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] + end + attribute \src "libresoc.v:32119.3-32137.6" + process $proc$libresoc.v:32119$687 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:32120.5-32120.29" + switch \initial + attribute \src "libresoc.v:32120.9-32120.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100101 + case + assign $1\dec31_dec_sub24_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] + end + attribute \src "libresoc.v:32138.3-32156.6" + process $proc$libresoc.v:32138$688 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:32139.5-32139.29" + switch \initial + attribute \src "libresoc.v:32139.9-32139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] + end + attribute \src "libresoc.v:32157.3-32175.6" + process $proc$libresoc.v:32157$689 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:32158.5-32158.29" + switch \initial + attribute \src "libresoc.v:32158.9-32158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] + end + attribute \src "libresoc.v:32176.3-32194.6" + process $proc$libresoc.v:32176$690 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:32177.5-32177.29" + switch \initial + attribute \src "libresoc.v:32177.9-32177.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] + end + attribute \src "libresoc.v:32195.3-32213.6" + process $proc$libresoc.v:32195$691 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:32196.5-32196.29" + switch \initial + attribute \src "libresoc.v:32196.9-32196.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + case + assign $1\dec31_dec_sub24_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] + end + attribute \src "libresoc.v:32214.3-32232.6" + process $proc$libresoc.v:32214$692 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:32215.5-32215.29" + switch \initial + attribute \src "libresoc.v:32215.9-32215.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] + end + attribute \src "libresoc.v:32233.3-32251.6" + process $proc$libresoc.v:32233$693 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:32234.5-32234.29" + switch \initial + attribute \src "libresoc.v:32234.9-32234.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] + end + attribute \src "libresoc.v:32252.3-32270.6" + process $proc$libresoc.v:32252$694 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:32253.5-32253.29" + switch \initial + attribute \src "libresoc.v:32253.9-32253.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] + end + attribute \src "libresoc.v:32271.3-32289.6" + process $proc$libresoc.v:32271$695 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:32272.5-32272.29" + switch \initial + attribute \src "libresoc.v:32272.9-32272.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub24_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] + end + attribute \src "libresoc.v:32290.3-32308.6" + process $proc$libresoc.v:32290$696 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:32291.5-32291.29" + switch \initial + attribute \src "libresoc.v:32291.9-32291.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] + end + attribute \src "libresoc.v:32309.3-32327.6" + process $proc$libresoc.v:32309$697 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:32310.5-32310.29" + switch \initial + attribute \src "libresoc.v:32310.9-32310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] + end + attribute \src "libresoc.v:32328.3-32346.6" + process $proc$libresoc.v:32328$698 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:32329.5-32329.29" + switch \initial + attribute \src "libresoc.v:32329.9-32329.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] + end + attribute \src "libresoc.v:32347.3-32365.6" + process $proc$libresoc.v:32347$699 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:32348.5-32348.29" + switch \initial + attribute \src "libresoc.v:32348.9-32348.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub24_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] + end + attribute \src "libresoc.v:32366.3-32384.6" + process $proc$libresoc.v:32366$700 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:32367.5-32367.29" + switch \initial + attribute \src "libresoc.v:32367.9-32367.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] + end + attribute \src "libresoc.v:32385.3-32403.6" + process $proc$libresoc.v:32385$701 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:32386.5-32386.29" + switch \initial + attribute \src "libresoc.v:32386.9-32386.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] + end + attribute \src "libresoc.v:32404.3-32422.6" + process $proc$libresoc.v:32404$702 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:32405.5-32405.29" + switch \initial + attribute \src "libresoc.v:32405.9-32405.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] + end + attribute \src "libresoc.v:32423.3-32441.6" + process $proc$libresoc.v:32423$703 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_out_sel[1:0] $1\dec31_dec_sub24_out_sel[1:0] + attribute \src "libresoc.v:32424.5-32424.29" + switch \initial + attribute \src "libresoc.v:32424.9-32424.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub24_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_out_sel $0\dec31_dec_sub24_out_sel[1:0] + end + attribute \src "libresoc.v:32442.3-32460.6" + process $proc$libresoc.v:32442$704 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:32443.5-32443.29" + switch \initial + attribute \src "libresoc.v:32443.9-32443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] + end + attribute \src "libresoc.v:32461.3-32479.6" + process $proc$libresoc.v:32461$705 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:32462.5-32462.29" + switch \initial + attribute \src "libresoc.v:32462.9-32462.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub24_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:32485.1-33992.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" +attribute \generator "nMigen" +module \dec31_dec_sub26 + attribute \src "libresoc.v:33003.3-33054.6" + wire width 8 $0\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:33211.3-33262.6" + wire $0\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:33887.3-33938.6" + wire width 3 $0\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:33939.3-33990.6" + wire width 3 $0\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:32951.3-33002.6" + wire width 2 $0\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:33159.3-33210.6" + wire $0\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:33627.3-33678.6" + wire width 5 $0\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:32743.3-32794.6" + wire width 12 $0\dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:33679.3-33730.6" + wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:33731.3-33782.6" + wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:33783.3-33834.6" + wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:33315.3-33366.6" + wire width 7 $0\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:33055.3-33106.6" + wire $0\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:33107.3-33158.6" + wire $0\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:33419.3-33470.6" + wire $0\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:32795.3-32846.6" + wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:33523.3-33574.6" + wire $0\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:33835.3-33886.6" + wire width 2 $0\dec31_dec_sub26_out_sel[1:0] + attribute \src "libresoc.v:32899.3-32950.6" + wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:33367.3-33418.6" + wire $0\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:33575.3-33626.6" + wire $0\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:33471.3-33522.6" + wire $0\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:33263.3-33314.6" + wire $0\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:32847.3-32898.6" + wire width 2 $0\dec31_dec_sub26_upd[1:0] + attribute \src "libresoc.v:32486.7-32486.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:33003.3-33054.6" + wire width 8 $1\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:33211.3-33262.6" + wire $1\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:33887.3-33938.6" + wire width 3 $1\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:33939.3-33990.6" + wire width 3 $1\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:32951.3-33002.6" + wire width 2 $1\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:33159.3-33210.6" + wire $1\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:33627.3-33678.6" + wire width 5 $1\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:32743.3-32794.6" + wire width 12 $1\dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:33679.3-33730.6" + wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:33731.3-33782.6" + wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:33783.3-33834.6" + wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:33315.3-33366.6" + wire width 7 $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:33055.3-33106.6" + wire $1\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:33107.3-33158.6" + wire $1\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:33419.3-33470.6" + wire $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:32795.3-32846.6" + wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:33523.3-33574.6" + wire $1\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:33835.3-33886.6" + wire width 2 $1\dec31_dec_sub26_out_sel[1:0] + attribute \src "libresoc.v:32899.3-32950.6" + wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:33367.3-33418.6" + wire $1\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:33575.3-33626.6" + wire $1\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:33471.3-33522.6" + wire $1\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:33263.3-33314.6" + wire $1\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:32847.3-32898.6" + wire width 2 $1\dec31_dec_sub26_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub26_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub26_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub26_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub26_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub26_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub26_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub26_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub26_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub26_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub26_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub26_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub26_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub26_upd + attribute \src "libresoc.v:32486.7-32486.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:32486.7-32486.20" + process $proc$libresoc.v:32486$731 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:32743.3-32794.6" + process $proc$libresoc.v:32743$707 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_function_unit[11:0] $1\dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:32744.5-32744.29" + switch \initial + attribute \src "libresoc.v:32744.9-32744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 + case + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[11:0] + end + attribute \src "libresoc.v:32795.3-32846.6" + process $proc$libresoc.v:32795$708 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:32796.5-32796.29" + switch \initial + attribute \src "libresoc.v:32796.9-32796.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] + end + attribute \src "libresoc.v:32847.3-32898.6" + process $proc$libresoc.v:32847$709 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] + attribute \src "libresoc.v:32848.5-32848.29" + switch \initial + attribute \src "libresoc.v:32848.9-32848.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] + end + attribute \src "libresoc.v:32899.3-32950.6" + process $proc$libresoc.v:32899$710 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:32900.5-32900.29" + switch \initial + attribute \src "libresoc.v:32900.9-32900.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] + end + attribute \src "libresoc.v:32951.3-33002.6" + process $proc$libresoc.v:32951$711 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:32952.5-32952.29" + switch \initial + attribute \src "libresoc.v:32952.9-32952.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] + end + attribute \src "libresoc.v:33003.3-33054.6" + process $proc$libresoc.v:33003$712 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:33004.5-33004.29" + switch \initial + attribute \src "libresoc.v:33004.9-33004.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100001 + case + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] + end + attribute \src "libresoc.v:33055.3-33106.6" + process $proc$libresoc.v:33055$713 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:33056.5-33056.29" + switch \initial + attribute \src "libresoc.v:33056.9-33056.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] + end + attribute \src "libresoc.v:33107.3-33158.6" + process $proc$libresoc.v:33107$714 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:33108.5-33108.29" + switch \initial + attribute \src "libresoc.v:33108.9-33108.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] + end + attribute \src "libresoc.v:33159.3-33210.6" + process $proc$libresoc.v:33159$715 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:33160.5-33160.29" + switch \initial + attribute \src "libresoc.v:33160.9-33160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] + end + attribute \src "libresoc.v:33211.3-33262.6" + process $proc$libresoc.v:33211$716 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:33212.5-33212.29" + switch \initial + attribute \src "libresoc.v:33212.9-33212.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + case + assign $1\dec31_dec_sub26_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] + end + attribute \src "libresoc.v:33263.3-33314.6" + process $proc$libresoc.v:33263$717 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:33264.5-33264.29" + switch \initial + attribute \src "libresoc.v:33264.9-33264.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] + end + attribute \src "libresoc.v:33315.3-33366.6" + process $proc$libresoc.v:33315$718 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:33316.5-33316.29" + switch \initial + attribute \src "libresoc.v:33316.9-33316.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] + end + attribute \src "libresoc.v:33367.3-33418.6" + process $proc$libresoc.v:33367$719 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:33368.5-33368.29" + switch \initial + attribute \src "libresoc.v:33368.9-33368.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] + end + attribute \src "libresoc.v:33419.3-33470.6" + process $proc$libresoc.v:33419$720 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:33420.5-33420.29" + switch \initial + attribute \src "libresoc.v:33420.9-33420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] + end + attribute \src "libresoc.v:33471.3-33522.6" + process $proc$libresoc.v:33471$721 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:33472.5-33472.29" + switch \initial + attribute \src "libresoc.v:33472.9-33472.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] + end + attribute \src "libresoc.v:33523.3-33574.6" + process $proc$libresoc.v:33523$722 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:33524.5-33524.29" + switch \initial + attribute \src "libresoc.v:33524.9-33524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] + end + attribute \src "libresoc.v:33575.3-33626.6" + process $proc$libresoc.v:33575$723 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:33576.5-33576.29" + switch \initial + attribute \src "libresoc.v:33576.9-33576.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] + end + attribute \src "libresoc.v:33627.3-33678.6" + process $proc$libresoc.v:33627$724 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:33628.5-33628.29" + switch \initial + attribute \src "libresoc.v:33628.9-33628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'10000 + case + assign $1\dec31_dec_sub26_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] + end + attribute \src "libresoc.v:33679.3-33730.6" + process $proc$libresoc.v:33679$725 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:33680.5-33680.29" + switch \initial + attribute \src "libresoc.v:33680.9-33680.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] + end + attribute \src "libresoc.v:33731.3-33782.6" + process $proc$libresoc.v:33731$726 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:33732.5-33732.29" + switch \initial + attribute \src "libresoc.v:33732.9-33732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 + case + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "libresoc.v:33783.3-33834.6" + process $proc$libresoc.v:33783$727 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:33784.5-33784.29" + switch \initial + attribute \src "libresoc.v:33784.9-33784.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] + end + attribute \src "libresoc.v:33835.3-33886.6" + process $proc$libresoc.v:33835$728 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_out_sel[1:0] $1\dec31_dec_sub26_out_sel[1:0] + attribute \src "libresoc.v:33836.5-33836.29" + switch \initial + attribute \src "libresoc.v:33836.9-33836.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub26_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_out_sel $0\dec31_dec_sub26_out_sel[1:0] + end + attribute \src "libresoc.v:33887.3-33938.6" + process $proc$libresoc.v:33887$729 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:33888.5-33888.29" + switch \initial + attribute \src "libresoc.v:33888.9-33888.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] + end + attribute \src "libresoc.v:33939.3-33990.6" + process $proc$libresoc.v:33939$730 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:33940.5-33940.29" + switch \initial + attribute \src "libresoc.v:33940.9-33940.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:33996.1-34711.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" +attribute \generator "nMigen" +module \dec31_dec_sub27 + attribute \src "libresoc.v:34349.3-34367.6" + wire width 8 $0\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:34425.3-34443.6" + wire $0\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:34672.3-34690.6" + wire width 3 $0\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:34691.3-34709.6" + wire width 3 $0\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:34330.3-34348.6" + wire width 2 $0\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:34406.3-34424.6" + wire $0\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:34577.3-34595.6" + wire width 5 $0\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:34254.3-34272.6" + wire width 12 $0\dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:34596.3-34614.6" + wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:34615.3-34633.6" + wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:34634.3-34652.6" + wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:34463.3-34481.6" + wire width 7 $0\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:34368.3-34386.6" + wire $0\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:34387.3-34405.6" + wire $0\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:34501.3-34519.6" + wire $0\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:34273.3-34291.6" + wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:34539.3-34557.6" + wire $0\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:34653.3-34671.6" + wire width 2 $0\dec31_dec_sub27_out_sel[1:0] + attribute \src "libresoc.v:34311.3-34329.6" + wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:34482.3-34500.6" + wire $0\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:34558.3-34576.6" + wire $0\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:34520.3-34538.6" + wire $0\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:34444.3-34462.6" + wire $0\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:34292.3-34310.6" + wire width 2 $0\dec31_dec_sub27_upd[1:0] + attribute \src "libresoc.v:33997.7-33997.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:34349.3-34367.6" + wire width 8 $1\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:34425.3-34443.6" + wire $1\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:34672.3-34690.6" + wire width 3 $1\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:34691.3-34709.6" + wire width 3 $1\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:34330.3-34348.6" + wire width 2 $1\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:34406.3-34424.6" + wire $1\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:34577.3-34595.6" + wire width 5 $1\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:34254.3-34272.6" + wire width 12 $1\dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:34596.3-34614.6" + wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:34615.3-34633.6" + wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:34634.3-34652.6" + wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:34463.3-34481.6" + wire width 7 $1\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:34368.3-34386.6" + wire $1\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:34387.3-34405.6" + wire $1\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:34501.3-34519.6" + wire $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:34273.3-34291.6" + wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:34539.3-34557.6" + wire $1\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:34653.3-34671.6" + wire width 2 $1\dec31_dec_sub27_out_sel[1:0] + attribute \src "libresoc.v:34311.3-34329.6" + wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:34482.3-34500.6" + wire $1\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:34558.3-34576.6" + wire $1\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:34520.3-34538.6" + wire $1\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:34444.3-34462.6" + wire $1\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:34292.3-34310.6" + wire width 2 $1\dec31_dec_sub27_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub27_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub27_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub27_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub27_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub27_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub27_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub27_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub27_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub27_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub27_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub27_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub27_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub27_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub27_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub27_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub27_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub27_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub27_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub27_upd + attribute \src "libresoc.v:33997.7-33997.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:33997.7-33997.20" + process $proc$libresoc.v:33997$756 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:34254.3-34272.6" + process $proc$libresoc.v:34254$732 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_function_unit[11:0] $1\dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:34255.5-34255.29" + switch \initial + attribute \src "libresoc.v:34255.9-34255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + case + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[11:0] + end + attribute \src "libresoc.v:34273.3-34291.6" + process $proc$libresoc.v:34273$733 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:34274.5-34274.29" + switch \initial + attribute \src "libresoc.v:34274.9-34274.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] + end + attribute \src "libresoc.v:34292.3-34310.6" + process $proc$libresoc.v:34292$734 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] + attribute \src "libresoc.v:34293.5-34293.29" + switch \initial + attribute \src "libresoc.v:34293.9-34293.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] + end + attribute \src "libresoc.v:34311.3-34329.6" + process $proc$libresoc.v:34311$735 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:34312.5-34312.29" + switch \initial + attribute \src "libresoc.v:34312.9-34312.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] + end + attribute \src "libresoc.v:34330.3-34348.6" + process $proc$libresoc.v:34330$736 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:34331.5-34331.29" + switch \initial + attribute \src "libresoc.v:34331.9-34331.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] + end + attribute \src "libresoc.v:34349.3-34367.6" + process $proc$libresoc.v:34349$737 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:34350.5-34350.29" + switch \initial + attribute \src "libresoc.v:34350.9-34350.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'01000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100100 + case + assign $1\dec31_dec_sub27_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] + end + attribute \src "libresoc.v:34368.3-34386.6" + process $proc$libresoc.v:34368$738 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:34369.5-34369.29" + switch \initial + attribute \src "libresoc.v:34369.9-34369.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] + end + attribute \src "libresoc.v:34387.3-34405.6" + process $proc$libresoc.v:34387$739 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:34388.5-34388.29" + switch \initial + attribute \src "libresoc.v:34388.9-34388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] + end + attribute \src "libresoc.v:34406.3-34424.6" + process $proc$libresoc.v:34406$740 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:34407.5-34407.29" + switch \initial + attribute \src "libresoc.v:34407.9-34407.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] + end + attribute \src "libresoc.v:34425.3-34443.6" + process $proc$libresoc.v:34425$741 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:34426.5-34426.29" + switch \initial + attribute \src "libresoc.v:34426.9-34426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + case + assign $1\dec31_dec_sub27_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] + end + attribute \src "libresoc.v:34444.3-34462.6" + process $proc$libresoc.v:34444$742 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:34445.5-34445.29" + switch \initial + attribute \src "libresoc.v:34445.9-34445.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] + end + attribute \src "libresoc.v:34463.3-34481.6" + process $proc$libresoc.v:34463$743 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:34464.5-34464.29" + switch \initial + attribute \src "libresoc.v:34464.9-34464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] + end + attribute \src "libresoc.v:34482.3-34500.6" + process $proc$libresoc.v:34482$744 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:34483.5-34483.29" + switch \initial + attribute \src "libresoc.v:34483.9-34483.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] + end + attribute \src "libresoc.v:34501.3-34519.6" + process $proc$libresoc.v:34501$745 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:34502.5-34502.29" + switch \initial + attribute \src "libresoc.v:34502.9-34502.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] + end + attribute \src "libresoc.v:34520.3-34538.6" + process $proc$libresoc.v:34520$746 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:34521.5-34521.29" + switch \initial + attribute \src "libresoc.v:34521.9-34521.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] + end + attribute \src "libresoc.v:34539.3-34557.6" + process $proc$libresoc.v:34539$747 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:34540.5-34540.29" + switch \initial + attribute \src "libresoc.v:34540.9-34540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] + end + attribute \src "libresoc.v:34558.3-34576.6" + process $proc$libresoc.v:34558$748 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:34559.5-34559.29" + switch \initial + attribute \src "libresoc.v:34559.9-34559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] + end + attribute \src "libresoc.v:34577.3-34595.6" + process $proc$libresoc.v:34577$749 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:34578.5-34578.29" + switch \initial + attribute \src "libresoc.v:34578.9-34578.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub27_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] + end + attribute \src "libresoc.v:34596.3-34614.6" + process $proc$libresoc.v:34596$750 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:34597.5-34597.29" + switch \initial + attribute \src "libresoc.v:34597.9-34597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] + end + attribute \src "libresoc.v:34615.3-34633.6" + process $proc$libresoc.v:34615$751 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:34616.5-34616.29" + switch \initial + attribute \src "libresoc.v:34616.9-34616.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] + end + attribute \src "libresoc.v:34634.3-34652.6" + process $proc$libresoc.v:34634$752 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:34635.5-34635.29" + switch \initial + attribute \src "libresoc.v:34635.9-34635.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] + end + attribute \src "libresoc.v:34653.3-34671.6" + process $proc$libresoc.v:34653$753 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_out_sel[1:0] $1\dec31_dec_sub27_out_sel[1:0] + attribute \src "libresoc.v:34654.5-34654.29" + switch \initial + attribute \src "libresoc.v:34654.9-34654.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub27_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_out_sel $0\dec31_dec_sub27_out_sel[1:0] + end + attribute \src "libresoc.v:34672.3-34690.6" + process $proc$libresoc.v:34672$754 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:34673.5-34673.29" + switch \initial + attribute \src "libresoc.v:34673.9-34673.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] + end + attribute \src "libresoc.v:34691.3-34709.6" + process $proc$libresoc.v:34691$755 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:34692.5-34692.29" + switch \initial + attribute \src "libresoc.v:34692.9-34692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub27_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:34715.1-35862.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" +attribute \generator "nMigen" +module \dec31_dec_sub28 + attribute \src "libresoc.v:35158.3-35194.6" + wire width 8 $0\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:35306.3-35342.6" + wire $0\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:35787.3-35823.6" + wire width 3 $0\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:35824.3-35860.6" + wire width 3 $0\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:35121.3-35157.6" + wire width 2 $0\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:35269.3-35305.6" + wire $0\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:35602.3-35638.6" + wire width 5 $0\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:34973.3-35009.6" + wire width 12 $0\dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:35639.3-35675.6" + wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:35676.3-35712.6" + wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:35713.3-35749.6" + wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:35380.3-35416.6" + wire width 7 $0\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:35195.3-35231.6" + wire $0\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:35232.3-35268.6" + wire $0\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:35454.3-35490.6" + wire $0\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:35010.3-35046.6" + wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:35528.3-35564.6" + wire $0\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:35750.3-35786.6" + wire width 2 $0\dec31_dec_sub28_out_sel[1:0] + attribute \src "libresoc.v:35084.3-35120.6" + wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:35417.3-35453.6" + wire $0\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:35565.3-35601.6" + wire $0\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:35491.3-35527.6" + wire $0\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:35343.3-35379.6" + wire $0\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:35047.3-35083.6" + wire width 2 $0\dec31_dec_sub28_upd[1:0] + attribute \src "libresoc.v:34716.7-34716.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:35158.3-35194.6" + wire width 8 $1\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:35306.3-35342.6" + wire $1\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:35787.3-35823.6" + wire width 3 $1\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:35824.3-35860.6" + wire width 3 $1\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:35121.3-35157.6" + wire width 2 $1\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:35269.3-35305.6" + wire $1\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:35602.3-35638.6" + wire width 5 $1\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:34973.3-35009.6" + wire width 12 $1\dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:35639.3-35675.6" + wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:35676.3-35712.6" + wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:35713.3-35749.6" + wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:35380.3-35416.6" + wire width 7 $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:35195.3-35231.6" + wire $1\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:35232.3-35268.6" + wire $1\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:35454.3-35490.6" + wire $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:35010.3-35046.6" + wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:35528.3-35564.6" + wire $1\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:35750.3-35786.6" + wire width 2 $1\dec31_dec_sub28_out_sel[1:0] + attribute \src "libresoc.v:35084.3-35120.6" + wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:35417.3-35453.6" + wire $1\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:35565.3-35601.6" + wire $1\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:35491.3-35527.6" + wire $1\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:35343.3-35379.6" + wire $1\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:35047.3-35083.6" + wire width 2 $1\dec31_dec_sub28_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub28_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub28_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub28_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub28_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub28_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub28_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub28_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub28_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub28_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub28_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub28_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub28_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub28_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub28_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub28_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub28_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub28_upd + attribute \src "libresoc.v:34716.7-34716.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:34716.7-34716.20" + process $proc$libresoc.v:34716$781 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:34973.3-35009.6" + process $proc$libresoc.v:34973$757 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_function_unit[11:0] $1\dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:34974.5-34974.29" + switch \initial + attribute \src "libresoc.v:34974.9-34974.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + case + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[11:0] + end + attribute \src "libresoc.v:35010.3-35046.6" + process $proc$libresoc.v:35010$758 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:35011.5-35011.29" + switch \initial + attribute \src "libresoc.v:35011.9-35011.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] + end + attribute \src "libresoc.v:35047.3-35083.6" + process $proc$libresoc.v:35047$759 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] + attribute \src "libresoc.v:35048.5-35048.29" + switch \initial + attribute \src "libresoc.v:35048.9-35048.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] + end + attribute \src "libresoc.v:35084.3-35120.6" + process $proc$libresoc.v:35084$760 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:35085.5-35085.29" + switch \initial + attribute \src "libresoc.v:35085.9-35085.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] + end + attribute \src "libresoc.v:35121.3-35157.6" + process $proc$libresoc.v:35121$761 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:35122.5-35122.29" + switch \initial + attribute \src "libresoc.v:35122.9-35122.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] + end + attribute \src "libresoc.v:35158.3-35194.6" + process $proc$libresoc.v:35158$762 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:35159.5-35159.29" + switch \initial + attribute \src "libresoc.v:35159.9-35159.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00001111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'01000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'11010000 + case + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] + end + attribute \src "libresoc.v:35195.3-35231.6" + process $proc$libresoc.v:35195$763 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:35196.5-35196.29" + switch \initial + attribute \src "libresoc.v:35196.9-35196.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] + end + attribute \src "libresoc.v:35232.3-35268.6" + process $proc$libresoc.v:35232$764 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:35233.5-35233.29" + switch \initial + attribute \src "libresoc.v:35233.9-35233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] + end + attribute \src "libresoc.v:35269.3-35305.6" + process $proc$libresoc.v:35269$765 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:35270.5-35270.29" + switch \initial + attribute \src "libresoc.v:35270.9-35270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] + end + attribute \src "libresoc.v:35306.3-35342.6" + process $proc$libresoc.v:35306$766 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:35307.5-35307.29" + switch \initial + attribute \src "libresoc.v:35307.9-35307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + case + assign $1\dec31_dec_sub28_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] + end + attribute \src "libresoc.v:35343.3-35379.6" + process $proc$libresoc.v:35343$767 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:35344.5-35344.29" + switch \initial + attribute \src "libresoc.v:35344.9-35344.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] + end + attribute \src "libresoc.v:35380.3-35416.6" + process $proc$libresoc.v:35380$768 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:35381.5-35381.29" + switch \initial + attribute \src "libresoc.v:35381.9-35381.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 + case + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] + end + attribute \src "libresoc.v:35417.3-35453.6" + process $proc$libresoc.v:35417$769 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:35418.5-35418.29" + switch \initial + attribute \src "libresoc.v:35418.9-35418.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] + end + attribute \src "libresoc.v:35454.3-35490.6" + process $proc$libresoc.v:35454$770 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:35455.5-35455.29" + switch \initial + attribute \src "libresoc.v:35455.9-35455.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] + end + attribute \src "libresoc.v:35491.3-35527.6" + process $proc$libresoc.v:35491$771 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:35492.5-35492.29" + switch \initial + attribute \src "libresoc.v:35492.9-35492.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] + end + attribute \src "libresoc.v:35528.3-35564.6" + process $proc$libresoc.v:35528$772 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:35529.5-35529.29" + switch \initial + attribute \src "libresoc.v:35529.9-35529.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] + end + attribute \src "libresoc.v:35565.3-35601.6" + process $proc$libresoc.v:35565$773 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:35566.5-35566.29" + switch \initial + attribute \src "libresoc.v:35566.9-35566.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] + end + attribute \src "libresoc.v:35602.3-35638.6" + process $proc$libresoc.v:35602$774 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:35603.5-35603.29" + switch \initial + attribute \src "libresoc.v:35603.9-35603.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub28_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] + end + attribute \src "libresoc.v:35639.3-35675.6" + process $proc$libresoc.v:35639$775 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:35640.5-35640.29" + switch \initial + attribute \src "libresoc.v:35640.9-35640.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] + end + attribute \src "libresoc.v:35676.3-35712.6" + process $proc$libresoc.v:35676$776 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:35677.5-35677.29" + switch \initial + attribute \src "libresoc.v:35677.9-35677.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] + end + attribute \src "libresoc.v:35713.3-35749.6" + process $proc$libresoc.v:35713$777 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:35714.5-35714.29" + switch \initial + attribute \src "libresoc.v:35714.9-35714.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] + end + attribute \src "libresoc.v:35750.3-35786.6" + process $proc$libresoc.v:35750$778 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_out_sel[1:0] $1\dec31_dec_sub28_out_sel[1:0] + attribute \src "libresoc.v:35751.5-35751.29" + switch \initial + attribute \src "libresoc.v:35751.9-35751.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub28_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_out_sel $0\dec31_dec_sub28_out_sel[1:0] + end + attribute \src "libresoc.v:35787.3-35823.6" + process $proc$libresoc.v:35787$779 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:35788.5-35788.29" + switch \initial + attribute \src "libresoc.v:35788.9-35788.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] + end + attribute \src "libresoc.v:35824.3-35860.6" + process $proc$libresoc.v:35824$780 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:35825.5-35825.29" + switch \initial + attribute \src "libresoc.v:35825.9-35825.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:35866.1-36437.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" +attribute \generator "nMigen" +module \dec31_dec_sub4 + attribute \src "libresoc.v:36189.3-36201.6" + wire width 8 $0\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:36241.3-36253.6" + wire $0\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:36410.3-36422.6" + wire width 3 $0\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:36423.3-36435.6" + wire width 3 $0\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:36176.3-36188.6" + wire width 2 $0\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:36228.3-36240.6" + wire $0\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:36345.3-36357.6" + wire width 5 $0\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:36124.3-36136.6" + wire width 12 $0\dec31_dec_sub4_function_unit[11:0] + attribute \src "libresoc.v:36358.3-36370.6" + wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:36371.3-36383.6" + wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:36384.3-36396.6" + wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:36267.3-36279.6" + wire width 7 $0\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:36202.3-36214.6" + wire $0\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:36215.3-36227.6" + wire $0\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:36293.3-36305.6" + wire $0\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:36137.3-36149.6" + wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:36319.3-36331.6" + wire $0\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:36397.3-36409.6" + wire width 2 $0\dec31_dec_sub4_out_sel[1:0] + attribute \src "libresoc.v:36163.3-36175.6" + wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:36280.3-36292.6" + wire $0\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:36332.3-36344.6" + wire $0\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:36306.3-36318.6" + wire $0\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:36254.3-36266.6" + wire $0\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:36150.3-36162.6" + wire width 2 $0\dec31_dec_sub4_upd[1:0] + attribute \src "libresoc.v:35867.7-35867.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:36189.3-36201.6" + wire width 8 $1\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:36241.3-36253.6" + wire $1\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:36410.3-36422.6" + wire width 3 $1\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:36423.3-36435.6" + wire width 3 $1\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:36176.3-36188.6" + wire width 2 $1\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:36228.3-36240.6" + wire $1\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:36345.3-36357.6" + wire width 5 $1\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:36124.3-36136.6" + wire width 12 $1\dec31_dec_sub4_function_unit[11:0] + attribute \src "libresoc.v:36358.3-36370.6" + wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:36371.3-36383.6" + wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:36384.3-36396.6" + wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:36267.3-36279.6" + wire width 7 $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:36202.3-36214.6" + wire $1\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:36215.3-36227.6" + wire $1\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:36293.3-36305.6" + wire $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:36137.3-36149.6" + wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:36319.3-36331.6" + wire $1\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:36397.3-36409.6" + wire width 2 $1\dec31_dec_sub4_out_sel[1:0] + attribute \src "libresoc.v:36163.3-36175.6" + wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:36280.3-36292.6" + wire $1\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:36332.3-36344.6" + wire $1\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:36306.3-36318.6" + wire $1\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:36254.3-36266.6" + wire $1\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:36150.3-36162.6" + wire width 2 $1\dec31_dec_sub4_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub4_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub4_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub4_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub4_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub4_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub4_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub4_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub4_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub4_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub4_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub4_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub4_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub4_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub4_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub4_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub4_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub4_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub4_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub4_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub4_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub4_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub4_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub4_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub4_upd + attribute \src "libresoc.v:35867.7-35867.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:35867.7-35867.20" + process $proc$libresoc.v:35867$806 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:36124.3-36136.6" + process $proc$libresoc.v:36124$782 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_function_unit[11:0] $1\dec31_dec_sub4_function_unit[11:0] + attribute \src "libresoc.v:36125.5-36125.29" + switch \initial + attribute \src "libresoc.v:36125.9-36125.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 + case + assign $1\dec31_dec_sub4_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[11:0] + end + attribute \src "libresoc.v:36137.3-36149.6" + process $proc$libresoc.v:36137$783 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:36138.5-36138.29" + switch \initial + attribute \src "libresoc.v:36138.9-36138.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] + end + attribute \src "libresoc.v:36150.3-36162.6" + process $proc$libresoc.v:36150$784 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] + attribute \src "libresoc.v:36151.5-36151.29" + switch \initial + attribute \src "libresoc.v:36151.9-36151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] + end + attribute \src "libresoc.v:36163.3-36175.6" + process $proc$libresoc.v:36163$785 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:36164.5-36164.29" + switch \initial + attribute \src "libresoc.v:36164.9-36164.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] + end + attribute \src "libresoc.v:36176.3-36188.6" + process $proc$libresoc.v:36176$786 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:36177.5-36177.29" + switch \initial + attribute \src "libresoc.v:36177.9-36177.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] + end + attribute \src "libresoc.v:36189.3-36201.6" + process $proc$libresoc.v:36189$787 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:36190.5-36190.29" + switch \initial + attribute \src "libresoc.v:36190.9-36190.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001110 + case + assign $1\dec31_dec_sub4_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] + end + attribute \src "libresoc.v:36202.3-36214.6" + process $proc$libresoc.v:36202$788 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:36203.5-36203.29" + switch \initial + attribute \src "libresoc.v:36203.9-36203.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] + end + attribute \src "libresoc.v:36215.3-36227.6" + process $proc$libresoc.v:36215$789 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:36216.5-36216.29" + switch \initial + attribute \src "libresoc.v:36216.9-36216.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] + end + attribute \src "libresoc.v:36228.3-36240.6" + process $proc$libresoc.v:36228$790 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:36229.5-36229.29" + switch \initial + attribute \src "libresoc.v:36229.9-36229.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] + end + attribute \src "libresoc.v:36241.3-36253.6" + process $proc$libresoc.v:36241$791 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:36242.5-36242.29" + switch \initial + attribute \src "libresoc.v:36242.9-36242.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_br[0:0] 1'0 + case + assign $1\dec31_dec_sub4_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] + end + attribute \src "libresoc.v:36254.3-36266.6" + process $proc$libresoc.v:36254$792 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:36255.5-36255.29" + switch \initial + attribute \src "libresoc.v:36255.9-36255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] + end + attribute \src "libresoc.v:36267.3-36279.6" + process $proc$libresoc.v:36267$793 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:36268.5-36268.29" + switch \initial + attribute \src "libresoc.v:36268.9-36268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + case + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] + end + attribute \src "libresoc.v:36280.3-36292.6" + process $proc$libresoc.v:36280$794 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:36281.5-36281.29" + switch \initial + attribute \src "libresoc.v:36281.9-36281.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] + end + attribute \src "libresoc.v:36293.3-36305.6" + process $proc$libresoc.v:36293$795 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:36294.5-36294.29" + switch \initial + attribute \src "libresoc.v:36294.9-36294.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] + end + attribute \src "libresoc.v:36306.3-36318.6" + process $proc$libresoc.v:36306$796 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:36307.5-36307.29" + switch \initial + attribute \src "libresoc.v:36307.9-36307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] + end + attribute \src "libresoc.v:36319.3-36331.6" + process $proc$libresoc.v:36319$797 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:36320.5-36320.29" + switch \initial + attribute \src "libresoc.v:36320.9-36320.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] + end + attribute \src "libresoc.v:36332.3-36344.6" + process $proc$libresoc.v:36332$798 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:36333.5-36333.29" + switch \initial + attribute \src "libresoc.v:36333.9-36333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] + end + attribute \src "libresoc.v:36345.3-36357.6" + process $proc$libresoc.v:36345$799 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:36346.5-36346.29" + switch \initial + attribute \src "libresoc.v:36346.9-36346.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub4_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] + end + attribute \src "libresoc.v:36358.3-36370.6" + process $proc$libresoc.v:36358$800 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:36359.5-36359.29" + switch \initial + attribute \src "libresoc.v:36359.9-36359.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] + end + attribute \src "libresoc.v:36371.3-36383.6" + process $proc$libresoc.v:36371$801 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:36372.5-36372.29" + switch \initial + attribute \src "libresoc.v:36372.9-36372.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] + end + attribute \src "libresoc.v:36384.3-36396.6" + process $proc$libresoc.v:36384$802 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:36385.5-36385.29" + switch \initial + attribute \src "libresoc.v:36385.9-36385.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] + end + attribute \src "libresoc.v:36397.3-36409.6" + process $proc$libresoc.v:36397$803 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_out_sel[1:0] $1\dec31_dec_sub4_out_sel[1:0] + attribute \src "libresoc.v:36398.5-36398.29" + switch \initial + attribute \src "libresoc.v:36398.9-36398.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_out_sel $0\dec31_dec_sub4_out_sel[1:0] + end + attribute \src "libresoc.v:36410.3-36422.6" + process $proc$libresoc.v:36410$804 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:36411.5-36411.29" + switch \initial + attribute \src "libresoc.v:36411.9-36411.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] + end + attribute \src "libresoc.v:36423.3-36435.6" + process $proc$libresoc.v:36423$805 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:36424.5-36424.29" + switch \initial + attribute \src "libresoc.v:36424.9-36424.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:36441.1-37732.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" +attribute \generator "nMigen" +module \dec31_dec_sub8 + attribute \src "libresoc.v:36914.3-36956.6" + wire width 8 $0\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:37086.3-37128.6" + wire $0\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:37645.3-37687.6" + wire width 3 $0\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:37688.3-37730.6" + wire width 3 $0\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:36871.3-36913.6" + wire width 2 $0\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:37043.3-37085.6" + wire $0\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:37430.3-37472.6" + wire width 5 $0\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:36699.3-36741.6" + wire width 12 $0\dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:37473.3-37515.6" + wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:37516.3-37558.6" + wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:37559.3-37601.6" + wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:37172.3-37214.6" + wire width 7 $0\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:36957.3-36999.6" + wire $0\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:37000.3-37042.6" + wire $0\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:37258.3-37300.6" + wire $0\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:36742.3-36784.6" + wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:37344.3-37386.6" + wire $0\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:37602.3-37644.6" + wire width 2 $0\dec31_dec_sub8_out_sel[1:0] + attribute \src "libresoc.v:36828.3-36870.6" + wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:37215.3-37257.6" + wire $0\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:37387.3-37429.6" + wire $0\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:37301.3-37343.6" + wire $0\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:37129.3-37171.6" + wire $0\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:36785.3-36827.6" + wire width 2 $0\dec31_dec_sub8_upd[1:0] + attribute \src "libresoc.v:36442.7-36442.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:36914.3-36956.6" + wire width 8 $1\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:37086.3-37128.6" + wire $1\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:37645.3-37687.6" + wire width 3 $1\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:37688.3-37730.6" + wire width 3 $1\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:36871.3-36913.6" + wire width 2 $1\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:37043.3-37085.6" + wire $1\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:37430.3-37472.6" + wire width 5 $1\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:36699.3-36741.6" + wire width 12 $1\dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:37473.3-37515.6" + wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:37516.3-37558.6" + wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:37559.3-37601.6" + wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:37172.3-37214.6" + wire width 7 $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:36957.3-36999.6" + wire $1\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:37000.3-37042.6" + wire $1\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:37258.3-37300.6" + wire $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:36742.3-36784.6" + wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:37344.3-37386.6" + wire $1\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:37602.3-37644.6" + wire width 2 $1\dec31_dec_sub8_out_sel[1:0] + attribute \src "libresoc.v:36828.3-36870.6" + wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:37215.3-37257.6" + wire $1\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:37387.3-37429.6" + wire $1\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:37301.3-37343.6" + wire $1\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:37129.3-37171.6" + wire $1\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:36785.3-36827.6" + wire width 2 $1\dec31_dec_sub8_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub8_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub8_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub8_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub8_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub8_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub8_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub8_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub8_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub8_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub8_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub8_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub8_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub8_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub8_upd + attribute \src "libresoc.v:36442.7-36442.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:36442.7-36442.20" + process $proc$libresoc.v:36442$831 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:36699.3-36741.6" + process $proc$libresoc.v:36699$807 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_function_unit[11:0] $1\dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:36700.5-36700.29" + switch \initial + attribute \src "libresoc.v:36700.9-36700.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + case + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[11:0] + end + attribute \src "libresoc.v:36742.3-36784.6" + process $proc$libresoc.v:36742$808 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:36743.5-36743.29" + switch \initial + attribute \src "libresoc.v:36743.9-36743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] + end + attribute \src "libresoc.v:36785.3-36827.6" + process $proc$libresoc.v:36785$809 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] + attribute \src "libresoc.v:36786.5-36786.29" + switch \initial + attribute \src "libresoc.v:36786.9-36786.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] + end + attribute \src "libresoc.v:36828.3-36870.6" + process $proc$libresoc.v:36828$810 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:36829.5-36829.29" + switch \initial + attribute \src "libresoc.v:36829.9-36829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] + end + attribute \src "libresoc.v:36871.3-36913.6" + process $proc$libresoc.v:36871$811 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:36872.5-36872.29" + switch \initial + attribute \src "libresoc.v:36872.9-36872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + case + assign $1\dec31_dec_sub8_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] + end + attribute \src "libresoc.v:36914.3-36956.6" + process $proc$libresoc.v:36914$812 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:36915.5-36915.29" + switch \initial + attribute \src "libresoc.v:36915.9-36915.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11001000 + case + assign $1\dec31_dec_sub8_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] + end + attribute \src "libresoc.v:36957.3-36999.6" + process $proc$libresoc.v:36957$813 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:36958.5-36958.29" + switch \initial + attribute \src "libresoc.v:36958.9-36958.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + case + assign $1\dec31_dec_sub8_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] + end + attribute \src "libresoc.v:37000.3-37042.6" + process $proc$libresoc.v:37000$814 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:37001.5-37001.29" + switch \initial + attribute \src "libresoc.v:37001.9-37001.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] + end + attribute \src "libresoc.v:37043.3-37085.6" + process $proc$libresoc.v:37043$815 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:37044.5-37044.29" + switch \initial + attribute \src "libresoc.v:37044.9-37044.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] + end + attribute \src "libresoc.v:37086.3-37128.6" + process $proc$libresoc.v:37086$816 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:37087.5-37087.29" + switch \initial + attribute \src "libresoc.v:37087.9-37087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + case + assign $1\dec31_dec_sub8_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] + end + attribute \src "libresoc.v:37129.3-37171.6" + process $proc$libresoc.v:37129$817 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:37130.5-37130.29" + switch \initial + attribute \src "libresoc.v:37130.9-37130.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] + end + attribute \src "libresoc.v:37172.3-37214.6" + process $proc$libresoc.v:37172$818 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:37173.5-37173.29" + switch \initial + attribute \src "libresoc.v:37173.9-37173.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + case + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] + end + attribute \src "libresoc.v:37215.3-37257.6" + process $proc$libresoc.v:37215$819 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:37216.5-37216.29" + switch \initial + attribute \src "libresoc.v:37216.9-37216.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] + end + attribute \src "libresoc.v:37258.3-37300.6" + process $proc$libresoc.v:37258$820 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:37259.5-37259.29" + switch \initial + attribute \src "libresoc.v:37259.9-37259.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] + end + attribute \src "libresoc.v:37301.3-37343.6" + process $proc$libresoc.v:37301$821 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:37302.5-37302.29" + switch \initial + attribute \src "libresoc.v:37302.9-37302.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] + end + attribute \src "libresoc.v:37344.3-37386.6" + process $proc$libresoc.v:37344$822 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:37345.5-37345.29" + switch \initial + attribute \src "libresoc.v:37345.9-37345.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] + end + attribute \src "libresoc.v:37387.3-37429.6" + process $proc$libresoc.v:37387$823 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:37388.5-37388.29" + switch \initial + attribute \src "libresoc.v:37388.9-37388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] + end + attribute \src "libresoc.v:37430.3-37472.6" + process $proc$libresoc.v:37430$824 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:37431.5-37431.29" + switch \initial + attribute \src "libresoc.v:37431.9-37431.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub8_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] + end + attribute \src "libresoc.v:37473.3-37515.6" + process $proc$libresoc.v:37473$825 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:37474.5-37474.29" + switch \initial + attribute \src "libresoc.v:37474.9-37474.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] + end + attribute \src "libresoc.v:37516.3-37558.6" + process $proc$libresoc.v:37516$826 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:37517.5-37517.29" + switch \initial + attribute \src "libresoc.v:37517.9-37517.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] + end + attribute \src "libresoc.v:37559.3-37601.6" + process $proc$libresoc.v:37559$827 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:37560.5-37560.29" + switch \initial + attribute \src "libresoc.v:37560.9-37560.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] + end + attribute \src "libresoc.v:37602.3-37644.6" + process $proc$libresoc.v:37602$828 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_out_sel[1:0] $1\dec31_dec_sub8_out_sel[1:0] + attribute \src "libresoc.v:37603.5-37603.29" + switch \initial + attribute \src "libresoc.v:37603.9-37603.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub8_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_out_sel $0\dec31_dec_sub8_out_sel[1:0] + end + attribute \src "libresoc.v:37645.3-37687.6" + process $proc$libresoc.v:37645$829 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:37646.5-37646.29" + switch \initial + attribute \src "libresoc.v:37646.9-37646.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] + end + attribute \src "libresoc.v:37688.3-37730.6" + process $proc$libresoc.v:37688$830 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:37689.5-37689.29" + switch \initial + attribute \src "libresoc.v:37689.9-37689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:37736.1-39315.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" +attribute \generator "nMigen" +module \dec31_dec_sub9 + attribute \src "libresoc.v:38269.3-38323.6" + wire width 8 $0\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:38489.3-38543.6" + wire $0\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:39204.3-39258.6" + wire width 3 $0\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:39259.3-39313.6" + wire width 3 $0\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:38214.3-38268.6" + wire width 2 $0\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:38434.3-38488.6" + wire $0\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:38929.3-38983.6" + wire width 5 $0\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:37994.3-38048.6" + wire width 12 $0\dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:38984.3-39038.6" + wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:39039.3-39093.6" + wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:39094.3-39148.6" + wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:38599.3-38653.6" + wire width 7 $0\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:38324.3-38378.6" + wire $0\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:38379.3-38433.6" + wire $0\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:38709.3-38763.6" + wire $0\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:38049.3-38103.6" + wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:38819.3-38873.6" + wire $0\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:39149.3-39203.6" + wire width 2 $0\dec31_dec_sub9_out_sel[1:0] + attribute \src "libresoc.v:38159.3-38213.6" + wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:38654.3-38708.6" + wire $0\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:38874.3-38928.6" + wire $0\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:38764.3-38818.6" + wire $0\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:38544.3-38598.6" + wire $0\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:38104.3-38158.6" + wire width 2 $0\dec31_dec_sub9_upd[1:0] + attribute \src "libresoc.v:37737.7-37737.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:38269.3-38323.6" + wire width 8 $1\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:38489.3-38543.6" + wire $1\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:39204.3-39258.6" + wire width 3 $1\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:39259.3-39313.6" + wire width 3 $1\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:38214.3-38268.6" + wire width 2 $1\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:38434.3-38488.6" + wire $1\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:38929.3-38983.6" + wire width 5 $1\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:37994.3-38048.6" + wire width 12 $1\dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:38984.3-39038.6" + wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:39039.3-39093.6" + wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:39094.3-39148.6" + wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:38599.3-38653.6" + wire width 7 $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:38324.3-38378.6" + wire $1\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:38379.3-38433.6" + wire $1\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:38709.3-38763.6" + wire $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:38049.3-38103.6" + wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:38819.3-38873.6" + wire $1\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:39149.3-39203.6" + wire width 2 $1\dec31_dec_sub9_out_sel[1:0] + attribute \src "libresoc.v:38159.3-38213.6" + wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:38654.3-38708.6" + wire $1\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:38874.3-38928.6" + wire $1\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:38764.3-38818.6" + wire $1\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:38544.3-38598.6" + wire $1\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:38104.3-38158.6" + wire width 2 $1\dec31_dec_sub9_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub9_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub9_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub9_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub9_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub9_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub9_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub9_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub9_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub9_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub9_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub9_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub9_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub9_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub9_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub9_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub9_upd + attribute \src "libresoc.v:37737.7-37737.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:37737.7-37737.20" + process $proc$libresoc.v:37737$856 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:37994.3-38048.6" + process $proc$libresoc.v:37994$832 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_function_unit[11:0] $1\dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:37995.5-37995.29" + switch \initial + attribute \src "libresoc.v:37995.9-37995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + case + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[11:0] + end + attribute \src "libresoc.v:38049.3-38103.6" + process $proc$libresoc.v:38049$833 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:38050.5-38050.29" + switch \initial + attribute \src "libresoc.v:38050.9-38050.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] + end + attribute \src "libresoc.v:38104.3-38158.6" + process $proc$libresoc.v:38104$834 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] + attribute \src "libresoc.v:38105.5-38105.29" + switch \initial + attribute \src "libresoc.v:38105.9-38105.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] + end + attribute \src "libresoc.v:38159.3-38213.6" + process $proc$libresoc.v:38159$835 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:38160.5-38160.29" + switch \initial + attribute \src "libresoc.v:38160.9-38160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] + end + attribute \src "libresoc.v:38214.3-38268.6" + process $proc$libresoc.v:38214$836 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:38215.5-38215.29" + switch \initial + attribute \src "libresoc.v:38215.9-38215.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] + end + attribute \src "libresoc.v:38269.3-38323.6" + process $proc$libresoc.v:38269$837 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:38270.5-38270.29" + switch \initial + attribute \src "libresoc.v:38270.9-38270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111111 + case + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] + end + attribute \src "libresoc.v:38324.3-38378.6" + process $proc$libresoc.v:38324$838 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:38325.5-38325.29" + switch \initial + attribute \src "libresoc.v:38325.9-38325.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] + end + attribute \src "libresoc.v:38379.3-38433.6" + process $proc$libresoc.v:38379$839 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:38380.5-38380.29" + switch \initial + attribute \src "libresoc.v:38380.9-38380.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] + end + attribute \src "libresoc.v:38434.3-38488.6" + process $proc$libresoc.v:38434$840 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:38435.5-38435.29" + switch \initial + attribute \src "libresoc.v:38435.9-38435.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] + end + attribute \src "libresoc.v:38489.3-38543.6" + process $proc$libresoc.v:38489$841 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:38490.5-38490.29" + switch \initial + attribute \src "libresoc.v:38490.9-38490.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + case + assign $1\dec31_dec_sub9_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] + end + attribute \src "libresoc.v:38544.3-38598.6" + process $proc$libresoc.v:38544$842 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:38545.5-38545.29" + switch \initial + attribute \src "libresoc.v:38545.9-38545.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] + end + attribute \src "libresoc.v:38599.3-38653.6" + process $proc$libresoc.v:38599$843 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:38600.5-38600.29" + switch \initial + attribute \src "libresoc.v:38600.9-38600.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + case + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] + end + attribute \src "libresoc.v:38654.3-38708.6" + process $proc$libresoc.v:38654$844 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:38655.5-38655.29" + switch \initial + attribute \src "libresoc.v:38655.9-38655.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] + end + attribute \src "libresoc.v:38709.3-38763.6" + process $proc$libresoc.v:38709$845 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:38710.5-38710.29" + switch \initial + attribute \src "libresoc.v:38710.9-38710.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] + end + attribute \src "libresoc.v:38764.3-38818.6" + process $proc$libresoc.v:38764$846 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:38765.5-38765.29" + switch \initial + attribute \src "libresoc.v:38765.9-38765.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] + end + attribute \src "libresoc.v:38819.3-38873.6" + process $proc$libresoc.v:38819$847 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:38820.5-38820.29" + switch \initial + attribute \src "libresoc.v:38820.9-38820.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] + end + attribute \src "libresoc.v:38874.3-38928.6" + process $proc$libresoc.v:38874$848 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:38875.5-38875.29" + switch \initial + attribute \src "libresoc.v:38875.9-38875.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] + end + attribute \src "libresoc.v:38929.3-38983.6" + process $proc$libresoc.v:38929$849 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:38930.5-38930.29" + switch \initial + attribute \src "libresoc.v:38930.9-38930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub9_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] + end + attribute \src "libresoc.v:38984.3-39038.6" + process $proc$libresoc.v:38984$850 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:38985.5-38985.29" + switch \initial + attribute \src "libresoc.v:38985.9-38985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] + end + attribute \src "libresoc.v:39039.3-39093.6" + process $proc$libresoc.v:39039$851 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:39040.5-39040.29" + switch \initial + attribute \src "libresoc.v:39040.9-39040.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] + end + attribute \src "libresoc.v:39094.3-39148.6" + process $proc$libresoc.v:39094$852 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:39095.5-39095.29" + switch \initial + attribute \src "libresoc.v:39095.9-39095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] + end + attribute \src "libresoc.v:39149.3-39203.6" + process $proc$libresoc.v:39149$853 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_out_sel[1:0] $1\dec31_dec_sub9_out_sel[1:0] + attribute \src "libresoc.v:39150.5-39150.29" + switch \initial + attribute \src "libresoc.v:39150.9-39150.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub9_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_out_sel $0\dec31_dec_sub9_out_sel[1:0] + end + attribute \src "libresoc.v:39204.3-39258.6" + process $proc$libresoc.v:39204$854 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:39205.5-39205.29" + switch \initial + attribute \src "libresoc.v:39205.9-39205.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] + end + attribute \src "libresoc.v:39259.3-39313.6" + process $proc$libresoc.v:39259$855 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:39260.5-39260.29" + switch \initial + attribute \src "libresoc.v:39260.9-39260.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:39319.1-39962.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58" +attribute \generator "nMigen" +module \dec58 + attribute \src "libresoc.v:39657.3-39672.6" + wire width 8 $0\dec58_asmcode[7:0] + attribute \src "libresoc.v:39721.3-39736.6" + wire $0\dec58_br[0:0] + attribute \src "libresoc.v:39929.3-39944.6" + wire width 3 $0\dec58_cr_in[2:0] + attribute \src "libresoc.v:39945.3-39960.6" + wire width 3 $0\dec58_cr_out[2:0] + attribute \src "libresoc.v:39641.3-39656.6" + wire width 2 $0\dec58_cry_in[1:0] + attribute \src "libresoc.v:39705.3-39720.6" + wire $0\dec58_cry_out[0:0] + attribute \src "libresoc.v:39849.3-39864.6" + wire width 5 $0\dec58_form[4:0] + attribute \src "libresoc.v:39577.3-39592.6" + wire width 12 $0\dec58_function_unit[11:0] + attribute \src "libresoc.v:39865.3-39880.6" + wire width 3 $0\dec58_in1_sel[2:0] + attribute \src "libresoc.v:39881.3-39896.6" + wire width 4 $0\dec58_in2_sel[3:0] + attribute \src "libresoc.v:39897.3-39912.6" + wire width 2 $0\dec58_in3_sel[1:0] + attribute \src "libresoc.v:39753.3-39768.6" + wire width 7 $0\dec58_internal_op[6:0] + attribute \src "libresoc.v:39673.3-39688.6" + wire $0\dec58_inv_a[0:0] + attribute \src "libresoc.v:39689.3-39704.6" + wire $0\dec58_inv_out[0:0] + attribute \src "libresoc.v:39785.3-39800.6" + wire $0\dec58_is_32b[0:0] + attribute \src "libresoc.v:39593.3-39608.6" + wire width 4 $0\dec58_ldst_len[3:0] + attribute \src "libresoc.v:39817.3-39832.6" + wire $0\dec58_lk[0:0] + attribute \src "libresoc.v:39913.3-39928.6" + wire width 2 $0\dec58_out_sel[1:0] + attribute \src "libresoc.v:39625.3-39640.6" + wire width 2 $0\dec58_rc_sel[1:0] + attribute \src "libresoc.v:39769.3-39784.6" + wire $0\dec58_rsrv[0:0] + attribute \src "libresoc.v:39833.3-39848.6" + wire $0\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:39801.3-39816.6" + wire $0\dec58_sgn[0:0] + attribute \src "libresoc.v:39737.3-39752.6" + wire $0\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:39609.3-39624.6" + wire width 2 $0\dec58_upd[1:0] + attribute \src "libresoc.v:39320.7-39320.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:39657.3-39672.6" + wire width 8 $1\dec58_asmcode[7:0] + attribute \src "libresoc.v:39721.3-39736.6" + wire $1\dec58_br[0:0] + attribute \src "libresoc.v:39929.3-39944.6" + wire width 3 $1\dec58_cr_in[2:0] + attribute \src "libresoc.v:39945.3-39960.6" + wire width 3 $1\dec58_cr_out[2:0] + attribute \src "libresoc.v:39641.3-39656.6" + wire width 2 $1\dec58_cry_in[1:0] + attribute \src "libresoc.v:39705.3-39720.6" + wire $1\dec58_cry_out[0:0] + attribute \src "libresoc.v:39849.3-39864.6" + wire width 5 $1\dec58_form[4:0] + attribute \src "libresoc.v:39577.3-39592.6" + wire width 12 $1\dec58_function_unit[11:0] + attribute \src "libresoc.v:39865.3-39880.6" + wire width 3 $1\dec58_in1_sel[2:0] + attribute \src "libresoc.v:39881.3-39896.6" + wire width 4 $1\dec58_in2_sel[3:0] + attribute \src "libresoc.v:39897.3-39912.6" + wire width 2 $1\dec58_in3_sel[1:0] + attribute \src "libresoc.v:39753.3-39768.6" + wire width 7 $1\dec58_internal_op[6:0] + attribute \src "libresoc.v:39673.3-39688.6" + wire $1\dec58_inv_a[0:0] + attribute \src "libresoc.v:39689.3-39704.6" + wire $1\dec58_inv_out[0:0] + attribute \src "libresoc.v:39785.3-39800.6" + wire $1\dec58_is_32b[0:0] + attribute \src "libresoc.v:39593.3-39608.6" + wire width 4 $1\dec58_ldst_len[3:0] + attribute \src "libresoc.v:39817.3-39832.6" + wire $1\dec58_lk[0:0] + attribute \src "libresoc.v:39913.3-39928.6" + wire width 2 $1\dec58_out_sel[1:0] + attribute \src "libresoc.v:39625.3-39640.6" + wire width 2 $1\dec58_rc_sel[1:0] + attribute \src "libresoc.v:39769.3-39784.6" + wire $1\dec58_rsrv[0:0] + attribute \src "libresoc.v:39833.3-39848.6" + wire $1\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:39801.3-39816.6" + wire $1\dec58_sgn[0:0] + attribute \src "libresoc.v:39737.3-39752.6" + wire $1\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:39609.3-39624.6" + wire width 2 $1\dec58_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec58_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec58_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec58_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec58_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec58_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec58_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec58_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec58_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec58_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec58_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec58_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec58_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec58_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec58_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec58_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec58_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec58_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec58_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec58_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec58_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec58_upd + attribute \src "libresoc.v:39320.7-39320.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 2 \opcode_switch + attribute \src "libresoc.v:39320.7-39320.20" + process $proc$libresoc.v:39320$881 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:39577.3-39592.6" + process $proc$libresoc.v:39577$857 + assign { } { } + assign { } { } + assign $0\dec58_function_unit[11:0] $1\dec58_function_unit[11:0] + attribute \src "libresoc.v:39578.5-39578.29" + switch \initial + attribute \src "libresoc.v:39578.9-39578.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_function_unit[11:0] 12'000000000100 + case + assign $1\dec58_function_unit[11:0] 12'000000000000 + end + sync always + update \dec58_function_unit $0\dec58_function_unit[11:0] + end + attribute \src "libresoc.v:39593.3-39608.6" + process $proc$libresoc.v:39593$858 + assign { } { } + assign { } { } + assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] + attribute \src "libresoc.v:39594.5-39594.29" + switch \initial + attribute \src "libresoc.v:39594.9-39594.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'0100 + case + assign $1\dec58_ldst_len[3:0] 4'0000 + end + sync always + update \dec58_ldst_len $0\dec58_ldst_len[3:0] + end + attribute \src "libresoc.v:39609.3-39624.6" + process $proc$libresoc.v:39609$859 + assign { } { } + assign { } { } + assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] + attribute \src "libresoc.v:39610.5-39610.29" + switch \initial + attribute \src "libresoc.v:39610.9-39610.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_upd[1:0] 2'00 + case + assign $1\dec58_upd[1:0] 2'00 + end + sync always + update \dec58_upd $0\dec58_upd[1:0] + end + attribute \src "libresoc.v:39625.3-39640.6" + process $proc$libresoc.v:39625$860 + assign { } { } + assign { } { } + assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] + attribute \src "libresoc.v:39626.5-39626.29" + switch \initial + attribute \src "libresoc.v:39626.9-39626.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + case + assign $1\dec58_rc_sel[1:0] 2'00 + end + sync always + update \dec58_rc_sel $0\dec58_rc_sel[1:0] + end + attribute \src "libresoc.v:39641.3-39656.6" + process $proc$libresoc.v:39641$861 + assign { } { } + assign { } { } + assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] + attribute \src "libresoc.v:39642.5-39642.29" + switch \initial + attribute \src "libresoc.v:39642.9-39642.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + case + assign $1\dec58_cry_in[1:0] 2'00 + end + sync always + update \dec58_cry_in $0\dec58_cry_in[1:0] + end + attribute \src "libresoc.v:39657.3-39672.6" + process $proc$libresoc.v:39657$862 + assign { } { } + assign { } { } + assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] + attribute \src "libresoc.v:39658.5-39658.29" + switch \initial + attribute \src "libresoc.v:39658.9-39658.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01010010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01010101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01100010 + case + assign $1\dec58_asmcode[7:0] 8'00000000 + end + sync always + update \dec58_asmcode $0\dec58_asmcode[7:0] + end + attribute \src "libresoc.v:39673.3-39688.6" + process $proc$libresoc.v:39673$863 + assign { } { } + assign { } { } + assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] + attribute \src "libresoc.v:39674.5-39674.29" + switch \initial + attribute \src "libresoc.v:39674.9-39674.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + case + assign $1\dec58_inv_a[0:0] 1'0 + end + sync always + update \dec58_inv_a $0\dec58_inv_a[0:0] + end + attribute \src "libresoc.v:39689.3-39704.6" + process $proc$libresoc.v:39689$864 + assign { } { } + assign { } { } + assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] + attribute \src "libresoc.v:39690.5-39690.29" + switch \initial + attribute \src "libresoc.v:39690.9-39690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + case + assign $1\dec58_inv_out[0:0] 1'0 + end + sync always + update \dec58_inv_out $0\dec58_inv_out[0:0] + end + attribute \src "libresoc.v:39705.3-39720.6" + process $proc$libresoc.v:39705$865 + assign { } { } + assign { } { } + assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] + attribute \src "libresoc.v:39706.5-39706.29" + switch \initial + attribute \src "libresoc.v:39706.9-39706.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + case + assign $1\dec58_cry_out[0:0] 1'0 + end + sync always + update \dec58_cry_out $0\dec58_cry_out[0:0] + end + attribute \src "libresoc.v:39721.3-39736.6" + process $proc$libresoc.v:39721$866 + assign { } { } + assign { } { } + assign $0\dec58_br[0:0] $1\dec58_br[0:0] + attribute \src "libresoc.v:39722.5-39722.29" + switch \initial + attribute \src "libresoc.v:39722.9-39722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + case + assign $1\dec58_br[0:0] 1'0 + end + sync always + update \dec58_br $0\dec58_br[0:0] + end + attribute \src "libresoc.v:39737.3-39752.6" + process $proc$libresoc.v:39737$867 + assign { } { } + assign { } { } + assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:39738.5-39738.29" + switch \initial + attribute \src "libresoc.v:39738.9-39738.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'1 + case + assign $1\dec58_sgn_ext[0:0] 1'0 + end + sync always + update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] + end + attribute \src "libresoc.v:39753.3-39768.6" + process $proc$libresoc.v:39753$868 + assign { } { } + assign { } { } + assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] + attribute \src "libresoc.v:39754.5-39754.29" + switch \initial + attribute \src "libresoc.v:39754.9-39754.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + case + assign $1\dec58_internal_op[6:0] 7'0000000 + end + sync always + update \dec58_internal_op $0\dec58_internal_op[6:0] + end + attribute \src "libresoc.v:39769.3-39784.6" + process $proc$libresoc.v:39769$869 + assign { } { } + assign { } { } + assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] + attribute \src "libresoc.v:39770.5-39770.29" + switch \initial + attribute \src "libresoc.v:39770.9-39770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + case + assign $1\dec58_rsrv[0:0] 1'0 + end + sync always + update \dec58_rsrv $0\dec58_rsrv[0:0] + end + attribute \src "libresoc.v:39785.3-39800.6" + process $proc$libresoc.v:39785$870 + assign { } { } + assign { } { } + assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] + attribute \src "libresoc.v:39786.5-39786.29" + switch \initial + attribute \src "libresoc.v:39786.9-39786.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + case + assign $1\dec58_is_32b[0:0] 1'0 + end + sync always + update \dec58_is_32b $0\dec58_is_32b[0:0] + end + attribute \src "libresoc.v:39801.3-39816.6" + process $proc$libresoc.v:39801$871 + assign { } { } + assign { } { } + assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] + attribute \src "libresoc.v:39802.5-39802.29" + switch \initial + attribute \src "libresoc.v:39802.9-39802.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + case + assign $1\dec58_sgn[0:0] 1'0 + end + sync always + update \dec58_sgn $0\dec58_sgn[0:0] + end + attribute \src "libresoc.v:39817.3-39832.6" + process $proc$libresoc.v:39817$872 + assign { } { } + assign { } { } + assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] + attribute \src "libresoc.v:39818.5-39818.29" + switch \initial + attribute \src "libresoc.v:39818.9-39818.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + case + assign $1\dec58_lk[0:0] 1'0 + end + sync always + update \dec58_lk $0\dec58_lk[0:0] + end + attribute \src "libresoc.v:39833.3-39848.6" + process $proc$libresoc.v:39833$873 + assign { } { } + assign { } { } + assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:39834.5-39834.29" + switch \initial + attribute \src "libresoc.v:39834.9-39834.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + case + assign $1\dec58_sgl_pipe[0:0] 1'0 + end + sync always + update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] + end + attribute \src "libresoc.v:39849.3-39864.6" + process $proc$libresoc.v:39849$874 + assign { } { } + assign { } { } + assign $0\dec58_form[4:0] $1\dec58_form[4:0] + attribute \src "libresoc.v:39850.5-39850.29" + switch \initial + attribute \src "libresoc.v:39850.9-39850.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + case + assign $1\dec58_form[4:0] 5'00000 + end + sync always + update \dec58_form $0\dec58_form[4:0] + end + attribute \src "libresoc.v:39865.3-39880.6" + process $proc$libresoc.v:39865$875 + assign { } { } + assign { } { } + assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] + attribute \src "libresoc.v:39866.5-39866.29" + switch \initial + attribute \src "libresoc.v:39866.9-39866.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + case + assign $1\dec58_in1_sel[2:0] 3'000 + end + sync always + update \dec58_in1_sel $0\dec58_in1_sel[2:0] + end + attribute \src "libresoc.v:39881.3-39896.6" + process $proc$libresoc.v:39881$876 + assign { } { } + assign { } { } + assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] + attribute \src "libresoc.v:39882.5-39882.29" + switch \initial + attribute \src "libresoc.v:39882.9-39882.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + case + assign $1\dec58_in2_sel[3:0] 4'0000 + end + sync always + update \dec58_in2_sel $0\dec58_in2_sel[3:0] + end + attribute \src "libresoc.v:39897.3-39912.6" + process $proc$libresoc.v:39897$877 + assign { } { } + assign { } { } + assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] + attribute \src "libresoc.v:39898.5-39898.29" + switch \initial + attribute \src "libresoc.v:39898.9-39898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + case + assign $1\dec58_in3_sel[1:0] 2'00 + end + sync always + update \dec58_in3_sel $0\dec58_in3_sel[1:0] + end + attribute \src "libresoc.v:39913.3-39928.6" + process $proc$libresoc.v:39913$878 + assign { } { } + assign { } { } + assign $0\dec58_out_sel[1:0] $1\dec58_out_sel[1:0] + attribute \src "libresoc.v:39914.5-39914.29" + switch \initial + attribute \src "libresoc.v:39914.9-39914.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_out_sel[1:0] 2'01 + case + assign $1\dec58_out_sel[1:0] 2'00 + end + sync always + update \dec58_out_sel $0\dec58_out_sel[1:0] + end + attribute \src "libresoc.v:39929.3-39944.6" + process $proc$libresoc.v:39929$879 + assign { } { } + assign { } { } + assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] + attribute \src "libresoc.v:39930.5-39930.29" + switch \initial + attribute \src "libresoc.v:39930.9-39930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + case + assign $1\dec58_cr_in[2:0] 3'000 + end + sync always + update \dec58_cr_in $0\dec58_cr_in[2:0] + end + attribute \src "libresoc.v:39945.3-39960.6" + process $proc$libresoc.v:39945$880 + assign { } { } + assign { } { } + assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] + attribute \src "libresoc.v:39946.5-39946.29" + switch \initial + attribute \src "libresoc.v:39946.9-39946.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + case + assign $1\dec58_cr_out[2:0] 3'000 + end + sync always + update \dec58_cr_out $0\dec58_cr_out[2:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:39966.1-40537.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62" +attribute \generator "nMigen" +module \dec62 + attribute \src "libresoc.v:40289.3-40301.6" + wire width 8 $0\dec62_asmcode[7:0] + attribute \src "libresoc.v:40341.3-40353.6" + wire $0\dec62_br[0:0] + attribute \src "libresoc.v:40510.3-40522.6" + wire width 3 $0\dec62_cr_in[2:0] + attribute \src "libresoc.v:40523.3-40535.6" + wire width 3 $0\dec62_cr_out[2:0] + attribute \src "libresoc.v:40276.3-40288.6" + wire width 2 $0\dec62_cry_in[1:0] + attribute \src "libresoc.v:40328.3-40340.6" + wire $0\dec62_cry_out[0:0] + attribute \src "libresoc.v:40445.3-40457.6" + wire width 5 $0\dec62_form[4:0] + attribute \src "libresoc.v:40224.3-40236.6" + wire width 12 $0\dec62_function_unit[11:0] + attribute \src "libresoc.v:40458.3-40470.6" + wire width 3 $0\dec62_in1_sel[2:0] + attribute \src "libresoc.v:40471.3-40483.6" + wire width 4 $0\dec62_in2_sel[3:0] + attribute \src "libresoc.v:40484.3-40496.6" + wire width 2 $0\dec62_in3_sel[1:0] + attribute \src "libresoc.v:40367.3-40379.6" + wire width 7 $0\dec62_internal_op[6:0] + attribute \src "libresoc.v:40302.3-40314.6" + wire $0\dec62_inv_a[0:0] + attribute \src "libresoc.v:40315.3-40327.6" + wire $0\dec62_inv_out[0:0] + attribute \src "libresoc.v:40393.3-40405.6" + wire $0\dec62_is_32b[0:0] + attribute \src "libresoc.v:40237.3-40249.6" + wire width 4 $0\dec62_ldst_len[3:0] + attribute \src "libresoc.v:40419.3-40431.6" + wire $0\dec62_lk[0:0] + attribute \src "libresoc.v:40497.3-40509.6" + wire width 2 $0\dec62_out_sel[1:0] + attribute \src "libresoc.v:40263.3-40275.6" + wire width 2 $0\dec62_rc_sel[1:0] + attribute \src "libresoc.v:40380.3-40392.6" + wire $0\dec62_rsrv[0:0] + attribute \src "libresoc.v:40432.3-40444.6" + wire $0\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:40406.3-40418.6" + wire $0\dec62_sgn[0:0] + attribute \src "libresoc.v:40354.3-40366.6" + wire $0\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:40250.3-40262.6" + wire width 2 $0\dec62_upd[1:0] + attribute \src "libresoc.v:39967.7-39967.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:40289.3-40301.6" + wire width 8 $1\dec62_asmcode[7:0] + attribute \src "libresoc.v:40341.3-40353.6" + wire $1\dec62_br[0:0] + attribute \src "libresoc.v:40510.3-40522.6" + wire width 3 $1\dec62_cr_in[2:0] + attribute \src "libresoc.v:40523.3-40535.6" + wire width 3 $1\dec62_cr_out[2:0] + attribute \src "libresoc.v:40276.3-40288.6" + wire width 2 $1\dec62_cry_in[1:0] + attribute \src "libresoc.v:40328.3-40340.6" + wire $1\dec62_cry_out[0:0] + attribute \src "libresoc.v:40445.3-40457.6" + wire width 5 $1\dec62_form[4:0] + attribute \src "libresoc.v:40224.3-40236.6" + wire width 12 $1\dec62_function_unit[11:0] + attribute \src "libresoc.v:40458.3-40470.6" + wire width 3 $1\dec62_in1_sel[2:0] + attribute \src "libresoc.v:40471.3-40483.6" + wire width 4 $1\dec62_in2_sel[3:0] + attribute \src "libresoc.v:40484.3-40496.6" + wire width 2 $1\dec62_in3_sel[1:0] + attribute \src "libresoc.v:40367.3-40379.6" + wire width 7 $1\dec62_internal_op[6:0] + attribute \src "libresoc.v:40302.3-40314.6" + wire $1\dec62_inv_a[0:0] + attribute \src "libresoc.v:40315.3-40327.6" + wire $1\dec62_inv_out[0:0] + attribute \src "libresoc.v:40393.3-40405.6" + wire $1\dec62_is_32b[0:0] + attribute \src "libresoc.v:40237.3-40249.6" + wire width 4 $1\dec62_ldst_len[3:0] + attribute \src "libresoc.v:40419.3-40431.6" + wire $1\dec62_lk[0:0] + attribute \src "libresoc.v:40497.3-40509.6" + wire width 2 $1\dec62_out_sel[1:0] + attribute \src "libresoc.v:40263.3-40275.6" + wire width 2 $1\dec62_rc_sel[1:0] + attribute \src "libresoc.v:40380.3-40392.6" + wire $1\dec62_rsrv[0:0] + attribute \src "libresoc.v:40432.3-40444.6" + wire $1\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:40406.3-40418.6" + wire $1\dec62_sgn[0:0] + attribute \src "libresoc.v:40354.3-40366.6" + wire $1\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:40250.3-40262.6" + wire width 2 $1\dec62_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec62_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec62_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec62_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec62_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec62_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec62_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec62_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec62_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec62_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec62_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec62_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec62_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec62_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec62_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec62_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec62_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec62_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec62_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec62_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec62_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec62_upd + attribute \src "libresoc.v:39967.7-39967.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 2 \opcode_switch + attribute \src "libresoc.v:39967.7-39967.20" + process $proc$libresoc.v:39967$906 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:40224.3-40236.6" + process $proc$libresoc.v:40224$882 + assign { } { } + assign { } { } + assign $0\dec62_function_unit[11:0] $1\dec62_function_unit[11:0] + attribute \src "libresoc.v:40225.5-40225.29" + switch \initial + attribute \src "libresoc.v:40225.9-40225.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_function_unit[11:0] 12'000000000100 + case + assign $1\dec62_function_unit[11:0] 12'000000000000 + end + sync always + update \dec62_function_unit $0\dec62_function_unit[11:0] + end + attribute \src "libresoc.v:40237.3-40249.6" + process $proc$libresoc.v:40237$883 + assign { } { } + assign { } { } + assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] + attribute \src "libresoc.v:40238.5-40238.29" + switch \initial + attribute \src "libresoc.v:40238.9-40238.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_ldst_len[3:0] 4'1000 + case + assign $1\dec62_ldst_len[3:0] 4'0000 + end + sync always + update \dec62_ldst_len $0\dec62_ldst_len[3:0] + end + attribute \src "libresoc.v:40250.3-40262.6" + process $proc$libresoc.v:40250$884 + assign { } { } + assign { } { } + assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] + attribute \src "libresoc.v:40251.5-40251.29" + switch \initial + attribute \src "libresoc.v:40251.9-40251.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_upd[1:0] 2'01 + case + assign $1\dec62_upd[1:0] 2'00 + end + sync always + update \dec62_upd $0\dec62_upd[1:0] + end + attribute \src "libresoc.v:40263.3-40275.6" + process $proc$libresoc.v:40263$885 + assign { } { } + assign { } { } + assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] + attribute \src "libresoc.v:40264.5-40264.29" + switch \initial + attribute \src "libresoc.v:40264.9-40264.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_rc_sel[1:0] 2'00 + case + assign $1\dec62_rc_sel[1:0] 2'00 + end + sync always + update \dec62_rc_sel $0\dec62_rc_sel[1:0] + end + attribute \src "libresoc.v:40276.3-40288.6" + process $proc$libresoc.v:40276$886 + assign { } { } + assign { } { } + assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] + attribute \src "libresoc.v:40277.5-40277.29" + switch \initial + attribute \src "libresoc.v:40277.9-40277.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cry_in[1:0] 2'00 + case + assign $1\dec62_cry_in[1:0] 2'00 + end + sync always + update \dec62_cry_in $0\dec62_cry_in[1:0] + end + attribute \src "libresoc.v:40289.3-40301.6" + process $proc$libresoc.v:40289$887 + assign { } { } + assign { } { } + assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] + attribute \src "libresoc.v:40290.5-40290.29" + switch \initial + attribute \src "libresoc.v:40290.9-40290.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_asmcode[7:0] 8'10101100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_asmcode[7:0] 8'10101111 + case + assign $1\dec62_asmcode[7:0] 8'00000000 + end + sync always + update \dec62_asmcode $0\dec62_asmcode[7:0] + end + attribute \src "libresoc.v:40302.3-40314.6" + process $proc$libresoc.v:40302$888 + assign { } { } + assign { } { } + assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] + attribute \src "libresoc.v:40303.5-40303.29" + switch \initial + attribute \src "libresoc.v:40303.9-40303.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_inv_a[0:0] 1'0 + case + assign $1\dec62_inv_a[0:0] 1'0 + end + sync always + update \dec62_inv_a $0\dec62_inv_a[0:0] + end + attribute \src "libresoc.v:40315.3-40327.6" + process $proc$libresoc.v:40315$889 + assign { } { } + assign { } { } + assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] + attribute \src "libresoc.v:40316.5-40316.29" + switch \initial + attribute \src "libresoc.v:40316.9-40316.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_inv_out[0:0] 1'0 + case + assign $1\dec62_inv_out[0:0] 1'0 + end + sync always + update \dec62_inv_out $0\dec62_inv_out[0:0] + end + attribute \src "libresoc.v:40328.3-40340.6" + process $proc$libresoc.v:40328$890 + assign { } { } + assign { } { } + assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] + attribute \src "libresoc.v:40329.5-40329.29" + switch \initial + attribute \src "libresoc.v:40329.9-40329.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cry_out[0:0] 1'0 + case + assign $1\dec62_cry_out[0:0] 1'0 + end + sync always + update \dec62_cry_out $0\dec62_cry_out[0:0] + end + attribute \src "libresoc.v:40341.3-40353.6" + process $proc$libresoc.v:40341$891 + assign { } { } + assign { } { } + assign $0\dec62_br[0:0] $1\dec62_br[0:0] + attribute \src "libresoc.v:40342.5-40342.29" + switch \initial + attribute \src "libresoc.v:40342.9-40342.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_br[0:0] 1'0 + case + assign $1\dec62_br[0:0] 1'0 + end + sync always + update \dec62_br $0\dec62_br[0:0] + end + attribute \src "libresoc.v:40354.3-40366.6" + process $proc$libresoc.v:40354$892 + assign { } { } + assign { } { } + assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:40355.5-40355.29" + switch \initial + attribute \src "libresoc.v:40355.9-40355.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgn_ext[0:0] 1'0 + case + assign $1\dec62_sgn_ext[0:0] 1'0 + end + sync always + update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] + end + attribute \src "libresoc.v:40367.3-40379.6" + process $proc$libresoc.v:40367$893 + assign { } { } + assign { } { } + assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] + attribute \src "libresoc.v:40368.5-40368.29" + switch \initial + attribute \src "libresoc.v:40368.9-40368.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_internal_op[6:0] 7'0100110 + case + assign $1\dec62_internal_op[6:0] 7'0000000 + end + sync always + update \dec62_internal_op $0\dec62_internal_op[6:0] + end + attribute \src "libresoc.v:40380.3-40392.6" + process $proc$libresoc.v:40380$894 + assign { } { } + assign { } { } + assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] + attribute \src "libresoc.v:40381.5-40381.29" + switch \initial + attribute \src "libresoc.v:40381.9-40381.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_rsrv[0:0] 1'0 + case + assign $1\dec62_rsrv[0:0] 1'0 + end + sync always + update \dec62_rsrv $0\dec62_rsrv[0:0] + end + attribute \src "libresoc.v:40393.3-40405.6" + process $proc$libresoc.v:40393$895 + assign { } { } + assign { } { } + assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] + attribute \src "libresoc.v:40394.5-40394.29" + switch \initial + attribute \src "libresoc.v:40394.9-40394.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_is_32b[0:0] 1'0 + case + assign $1\dec62_is_32b[0:0] 1'0 + end + sync always + update \dec62_is_32b $0\dec62_is_32b[0:0] + end + attribute \src "libresoc.v:40406.3-40418.6" + process $proc$libresoc.v:40406$896 + assign { } { } + assign { } { } + assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] + attribute \src "libresoc.v:40407.5-40407.29" + switch \initial + attribute \src "libresoc.v:40407.9-40407.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgn[0:0] 1'0 + case + assign $1\dec62_sgn[0:0] 1'0 + end + sync always + update \dec62_sgn $0\dec62_sgn[0:0] + end + attribute \src "libresoc.v:40419.3-40431.6" + process $proc$libresoc.v:40419$897 + assign { } { } + assign { } { } + assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] + attribute \src "libresoc.v:40420.5-40420.29" + switch \initial + attribute \src "libresoc.v:40420.9-40420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_lk[0:0] 1'0 + case + assign $1\dec62_lk[0:0] 1'0 + end + sync always + update \dec62_lk $0\dec62_lk[0:0] + end + attribute \src "libresoc.v:40432.3-40444.6" + process $proc$libresoc.v:40432$898 + assign { } { } + assign { } { } + assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:40433.5-40433.29" + switch \initial + attribute \src "libresoc.v:40433.9-40433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgl_pipe[0:0] 1'1 + case + assign $1\dec62_sgl_pipe[0:0] 1'0 + end + sync always + update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] + end + attribute \src "libresoc.v:40445.3-40457.6" + process $proc$libresoc.v:40445$899 + assign { } { } + assign { } { } + assign $0\dec62_form[4:0] $1\dec62_form[4:0] + attribute \src "libresoc.v:40446.5-40446.29" + switch \initial + attribute \src "libresoc.v:40446.9-40446.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_form[4:0] 5'00101 + case + assign $1\dec62_form[4:0] 5'00000 + end + sync always + update \dec62_form $0\dec62_form[4:0] + end + attribute \src "libresoc.v:40458.3-40470.6" + process $proc$libresoc.v:40458$900 + assign { } { } + assign { } { } + assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] + attribute \src "libresoc.v:40459.5-40459.29" + switch \initial + attribute \src "libresoc.v:40459.9-40459.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in1_sel[2:0] 3'010 + case + assign $1\dec62_in1_sel[2:0] 3'000 + end + sync always + update \dec62_in1_sel $0\dec62_in1_sel[2:0] + end + attribute \src "libresoc.v:40471.3-40483.6" + process $proc$libresoc.v:40471$901 + assign { } { } + assign { } { } + assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] + attribute \src "libresoc.v:40472.5-40472.29" + switch \initial + attribute \src "libresoc.v:40472.9-40472.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in2_sel[3:0] 4'1000 + case + assign $1\dec62_in2_sel[3:0] 4'0000 + end + sync always + update \dec62_in2_sel $0\dec62_in2_sel[3:0] + end + attribute \src "libresoc.v:40484.3-40496.6" + process $proc$libresoc.v:40484$902 + assign { } { } + assign { } { } + assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] + attribute \src "libresoc.v:40485.5-40485.29" + switch \initial + attribute \src "libresoc.v:40485.9-40485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in3_sel[1:0] 2'01 + case + assign $1\dec62_in3_sel[1:0] 2'00 + end + sync always + update \dec62_in3_sel $0\dec62_in3_sel[1:0] + end + attribute \src "libresoc.v:40497.3-40509.6" + process $proc$libresoc.v:40497$903 + assign { } { } + assign { } { } + assign $0\dec62_out_sel[1:0] $1\dec62_out_sel[1:0] + attribute \src "libresoc.v:40498.5-40498.29" + switch \initial + attribute \src "libresoc.v:40498.9-40498.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_out_sel[1:0] 2'00 + case + assign $1\dec62_out_sel[1:0] 2'00 + end + sync always + update \dec62_out_sel $0\dec62_out_sel[1:0] + end + attribute \src "libresoc.v:40510.3-40522.6" + process $proc$libresoc.v:40510$904 + assign { } { } + assign { } { } + assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] + attribute \src "libresoc.v:40511.5-40511.29" + switch \initial + attribute \src "libresoc.v:40511.9-40511.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cr_in[2:0] 3'000 + case + assign $1\dec62_cr_in[2:0] 3'000 + end + sync always + update \dec62_cr_in $0\dec62_cr_in[2:0] + end + attribute \src "libresoc.v:40523.3-40535.6" + process $proc$libresoc.v:40523$905 + assign { } { } + assign { } { } + assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] + attribute \src "libresoc.v:40524.5-40524.29" + switch \initial + attribute \src "libresoc.v:40524.9-40524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cr_out[2:0] 3'000 + case + assign $1\dec62_cr_out[2:0] 3'000 + end + sync always + update \dec62_cr_out $0\dec62_cr_out[2:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:40541.1-41046.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a" +attribute \generator "nMigen" +module \dec_a + attribute \src "libresoc.v:40975.3-41010.6" + wire width 3 $0\fast_a[2:0] + attribute \src "libresoc.v:40975.3-41010.6" + wire $0\fast_a_ok[0:0] + attribute \src "libresoc.v:40542.7-40542.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:40943.3-40958.6" + wire width 5 $0\reg_a[4:0] + attribute \src "libresoc.v:40959.3-40974.6" + wire $0\reg_a_ok[0:0] + attribute \src "libresoc.v:41011.3-41021.6" + wire width 10 $0\spr[9:0] + attribute \src "libresoc.v:41033.3-41044.6" + wire width 10 $0\spr_a[9:0] + attribute \src "libresoc.v:41033.3-41044.6" + wire $0\spr_a_ok[0:0] + attribute \src "libresoc.v:41022.3-41032.6" + wire width 10 $0\sprmap_spr_i[9:0] + attribute \src "libresoc.v:40975.3-41010.6" + wire width 3 $1\fast_a[2:0] + attribute \src "libresoc.v:40975.3-41010.6" + wire $1\fast_a_ok[0:0] + attribute \src "libresoc.v:40943.3-40958.6" + wire width 5 $1\reg_a[4:0] + attribute \src "libresoc.v:40959.3-40974.6" + wire $1\reg_a_ok[0:0] + attribute \src "libresoc.v:41011.3-41021.6" + wire width 10 $1\spr[9:0] + attribute \src "libresoc.v:41033.3-41044.6" + wire width 10 $1\spr_a[9:0] + attribute \src "libresoc.v:41033.3-41044.6" + wire $1\spr_a_ok[0:0] + attribute \src "libresoc.v:41022.3-41032.6" + wire width 10 $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:40975.3-41010.6" + wire width 3 $2\fast_a[2:0] + attribute \src "libresoc.v:40975.3-41010.6" + wire $2\fast_a_ok[0:0] + attribute \src "libresoc.v:40943.3-40958.6" + wire width 5 $2\reg_a[4:0] + attribute \src "libresoc.v:40959.3-40974.6" + wire $2\reg_a_ok[0:0] + attribute \src "libresoc.v:40975.3-41010.6" + wire width 3 $3\fast_a[2:0] + attribute \src "libresoc.v:40975.3-41010.6" + wire $3\fast_a_ok[0:0] + attribute \src "libresoc.v:40927.18-40927.110" + wire $and$libresoc.v:40927$913_Y + attribute \src "libresoc.v:40932.18-40932.113" + wire $and$libresoc.v:40932$918_Y + attribute \src "libresoc.v:40935.17-40935.107" + wire $and$libresoc.v:40935$921_Y + attribute \src "libresoc.v:40922.18-40922.112" + wire $eq$libresoc.v:40922$908_Y + attribute \src "libresoc.v:40923.18-40923.111" + wire $eq$libresoc.v:40923$909_Y + attribute \src "libresoc.v:40924.18-40924.112" + wire $eq$libresoc.v:40924$910_Y + attribute \src "libresoc.v:40926.17-40926.110" + wire $eq$libresoc.v:40926$912_Y + attribute \src "libresoc.v:40929.18-40929.112" + wire $eq$libresoc.v:40929$915_Y + attribute \src "libresoc.v:40933.17-40933.111" + wire $eq$libresoc.v:40933$919_Y + attribute \src "libresoc.v:40925.18-40925.109" + wire $ne$libresoc.v:40925$911_Y + attribute \src "libresoc.v:40934.17-40934.108" + wire $ne$libresoc.v:40934$920_Y + attribute \src "libresoc.v:40930.18-40930.105" + wire $not$libresoc.v:40930$916_Y + attribute \src "libresoc.v:40931.18-40931.108" + wire $not$libresoc.v:40931$917_Y + attribute \src "libresoc.v:40921.17-40921.107" + wire $or$libresoc.v:40921$907_Y + attribute \src "libresoc.v:40928.18-40928.110" + wire $or$libresoc.v:40928$914_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 10 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 9 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 input 11 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 input 12 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 6 \fast_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 7 \fast_a_ok + attribute \src "libresoc.v:40542.7-40542.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 13 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" + wire width 5 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 2 \reg_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \reg_a_ok + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:85" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + wire width 10 \spr + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 4 \spr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \spr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \sprmap_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \sprmap_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + wire width 10 \sprmap_spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \sprmap_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \sprmap_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $and $and$libresoc.v:40927$913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \$17 + connect \Y $and$libresoc.v:40927$913_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" + cell $and $and$libresoc.v:40932$918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [9] + connect \B \$27 + connect \Y $and$libresoc.v:40932$918_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $and $and$libresoc.v:40935$921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \$5 + connect \Y $and$libresoc.v:40935$921_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + cell $eq $eq$libresoc.v:40922$908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'100 + connect \Y $eq$libresoc.v:40922$908_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + cell $eq $eq$libresoc.v:40923$909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'001 + connect \Y $eq$libresoc.v:40923$909_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + cell $eq $eq$libresoc.v:40924$910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$libresoc.v:40924$910_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + cell $eq $eq$libresoc.v:40926$912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'001 + connect \Y $eq$libresoc.v:40926$912_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + cell $eq $eq$libresoc.v:40929$915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'100 + connect \Y $eq$libresoc.v:40929$915_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + cell $eq $eq$libresoc.v:40933$919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$libresoc.v:40933$919_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $ne $ne$libresoc.v:40925$911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $ne$libresoc.v:40925$911_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $ne $ne$libresoc.v:40934$920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $ne$libresoc.v:40934$920_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" + cell $not $not$libresoc.v:40930$916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \BO [2] + connect \Y $not$libresoc.v:40930$916_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" + cell $not $not$libresoc.v:40931$917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [5] + connect \Y $not$libresoc.v:40931$917_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $or $or$libresoc.v:40921$907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$7 + connect \Y $or$libresoc.v:40921$907_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $or $or$libresoc.v:40928$914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$13 + connect \B \$19 + connect \Y $or$libresoc.v:40928$914_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:40936.10-40942.4" + cell \sprmap \sprmap + connect \fast_o \sprmap_fast_o + connect \fast_o_ok \sprmap_fast_o_ok + connect \spr_i \sprmap_spr_i + connect \spr_o \sprmap_spr_o + connect \spr_o_ok \sprmap_spr_o_ok + end + attribute \src "libresoc.v:40542.7-40542.20" + process $proc$libresoc.v:40542$928 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:40943.3-40958.6" + process $proc$libresoc.v:40943$922 + assign { } { } + assign { } { } + assign { } { } + assign $0\reg_a[4:0] $2\reg_a[4:0] + attribute \src "libresoc.v:40944.5-40944.29" + switch \initial + attribute \src "libresoc.v:40944.9-40944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg_a[4:0] \ra + case + assign $1\reg_a[4:0] 5'00000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg_a[4:0] \RS + case + assign $2\reg_a[4:0] $1\reg_a[4:0] + end + sync always + update \reg_a $0\reg_a[4:0] + end + attribute \src "libresoc.v:40959.3-40974.6" + process $proc$libresoc.v:40959$923 + assign { } { } + assign { } { } + assign { } { } + assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0] + attribute \src "libresoc.v:40960.5-40960.29" + switch \initial + attribute \src "libresoc.v:40960.9-40960.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg_a_ok[0:0] 1'1 + case + assign $1\reg_a_ok[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg_a_ok[0:0] 1'1 + case + assign $2\reg_a_ok[0:0] $1\reg_a_ok[0:0] + end + sync always + update \reg_a_ok $0\reg_a_ok[0:0] + end + attribute \src "libresoc.v:40975.3-41010.6" + process $proc$libresoc.v:40975$924 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast_a[2:0] $1\fast_a[2:0] + assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0] + attribute \src "libresoc.v:40976.5-40976.29" + switch \initial + attribute \src "libresoc.v:40976.9-40976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign { } { } + assign $1\fast_a[2:0] $2\fast_a[2:0] + assign $1\fast_a_ok[0:0] $2\fast_a_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\fast_a[2:0] 3'000 + assign $2\fast_a_ok[0:0] 1'1 + case + assign $2\fast_a[2:0] 3'000 + assign $2\fast_a_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign { } { } + assign $1\fast_a[2:0] $3\fast_a[2:0] + assign $1\fast_a_ok[0:0] $3\fast_a_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $3\fast_a[2:0] 3'000 + assign $3\fast_a_ok[0:0] 1'1 + case + assign $3\fast_a[2:0] 3'000 + assign $3\fast_a_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign { } { } + assign { $1\fast_a_ok[0:0] $1\fast_a[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } + case + assign $1\fast_a[2:0] 3'000 + assign $1\fast_a_ok[0:0] 1'0 + end + sync always + update \fast_a $0\fast_a[2:0] + update \fast_a_ok $0\fast_a_ok[0:0] + end + attribute \src "libresoc.v:41011.3-41021.6" + process $proc$libresoc.v:41011$925 + assign { } { } + assign { } { } + assign $0\spr[9:0] $1\spr[9:0] + attribute \src "libresoc.v:41012.5-41012.29" + switch \initial + attribute \src "libresoc.v:41012.9-41012.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } + case + assign $1\spr[9:0] 10'0000000000 + end + sync always + update \spr $0\spr[9:0] + end + attribute \src "libresoc.v:41022.3-41032.6" + process $proc$libresoc.v:41022$926 + assign { } { } + assign { } { } + assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:41023.5-41023.29" + switch \initial + attribute \src "libresoc.v:41023.9-41023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign $1\sprmap_spr_i[9:0] \spr + case + assign $1\sprmap_spr_i[9:0] 10'0000000000 + end + sync always + update \sprmap_spr_i $0\sprmap_spr_i[9:0] + end + attribute \src "libresoc.v:41033.3-41044.6" + process $proc$libresoc.v:41033$927 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr_a[9:0] $1\spr_a[9:0] + assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0] + attribute \src "libresoc.v:41034.5-41034.29" + switch \initial + attribute \src "libresoc.v:41034.9-41034.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign { } { } + assign { $1\spr_a_ok[0:0] $1\spr_a[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } + case + assign $1\spr_a[9:0] 10'0000000000 + assign $1\spr_a_ok[0:0] 1'0 + end + sync always + update \spr_a $0\spr_a[9:0] + update \spr_a_ok $0\spr_a_ok[0:0] + end + connect \$9 $or$libresoc.v:40921$907_Y + connect \$11 $eq$libresoc.v:40922$908_Y + connect \$13 $eq$libresoc.v:40923$909_Y + connect \$15 $eq$libresoc.v:40924$910_Y + connect \$17 $ne$libresoc.v:40925$911_Y + connect \$1 $eq$libresoc.v:40926$912_Y + connect \$19 $and$libresoc.v:40927$913_Y + connect \$21 $or$libresoc.v:40928$914_Y + connect \$23 $eq$libresoc.v:40929$915_Y + connect \$25 $not$libresoc.v:40930$916_Y + connect \$27 $not$libresoc.v:40931$917_Y + connect \$29 $and$libresoc.v:40932$918_Y + connect \$3 $eq$libresoc.v:40933$919_Y + connect \$5 $ne$libresoc.v:40934$920_Y + connect \$7 $and$libresoc.v:40935$921_Y + connect \ra \RA +end +attribute \src "libresoc.v:41050.1-41241.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_b" +attribute \generator "nMigen" +module \dec_b + attribute \src "libresoc.v:41205.3-41222.6" + wire width 3 $0\fast_b[2:0] + attribute \src "libresoc.v:41223.3-41240.6" + wire $0\fast_b_ok[0:0] + attribute \src "libresoc.v:41051.7-41051.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:41175.3-41189.6" + wire width 5 $0\reg_b[4:0] + attribute \src "libresoc.v:41190.3-41204.6" + wire $0\reg_b_ok[0:0] + attribute \src "libresoc.v:41205.3-41222.6" + wire width 3 $1\fast_b[2:0] + attribute \src "libresoc.v:41223.3-41240.6" + wire $1\fast_b_ok[0:0] + attribute \src "libresoc.v:41175.3-41189.6" + wire width 5 $1\reg_b[4:0] + attribute \src "libresoc.v:41190.3-41204.6" + wire $1\reg_b_ok[0:0] + attribute \src "libresoc.v:41205.3-41222.6" + wire width 3 $2\fast_b[2:0] + attribute \src "libresoc.v:41223.3-41240.6" + wire $2\fast_b_ok[0:0] + attribute \src "libresoc.v:41171.17-41171.117" + wire $eq$libresoc.v:41171$929_Y + attribute \src "libresoc.v:41173.17-41173.117" + wire $eq$libresoc.v:41173$931_Y + attribute \src "libresoc.v:41172.17-41172.107" + wire $not$libresoc.v:41172$930_Y + attribute \src "libresoc.v:41174.17-41174.107" + wire $not$libresoc.v:41174$932_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 6 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 input 8 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 4 \fast_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \fast_b_ok + attribute \src "libresoc.v:41051.7-41051.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 9 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 2 \reg_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \reg_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire width 4 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + cell $eq $eq$libresoc.v:41171$929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0001000 + connect \Y $eq$libresoc.v:41171$929_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + cell $eq $eq$libresoc.v:41173$931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0001000 + connect \Y $eq$libresoc.v:41173$931_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + cell $not $not$libresoc.v:41172$930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [9] + connect \Y $not$libresoc.v:41172$930_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + cell $not $not$libresoc.v:41174$932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [9] + connect \Y $not$libresoc.v:41174$932_Y + end + attribute \src "libresoc.v:41051.7-41051.20" + process $proc$libresoc.v:41051$937 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:41175.3-41189.6" + process $proc$libresoc.v:41175$933 + assign { } { } + assign { } { } + assign $0\reg_b[4:0] $1\reg_b[4:0] + attribute \src "libresoc.v:41176.5-41176.29" + switch \initial + attribute \src "libresoc.v:41176.9-41176.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\reg_b[4:0] \RB + attribute \src "libresoc.v:0.0-0.0" + case 4'1101 + assign { } { } + assign $1\reg_b[4:0] \RS + case + assign $1\reg_b[4:0] 5'00000 + end + sync always + update \reg_b $0\reg_b[4:0] + end + attribute \src "libresoc.v:41190.3-41204.6" + process $proc$libresoc.v:41190$934 + assign { } { } + assign { } { } + assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0] + attribute \src "libresoc.v:41191.5-41191.29" + switch \initial + attribute \src "libresoc.v:41191.9-41191.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\reg_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1101 + assign { } { } + assign $1\reg_b_ok[0:0] 1'1 + case + assign $1\reg_b_ok[0:0] 1'0 + end + sync always + update \reg_b_ok $0\reg_b_ok[0:0] + end + attribute \src "libresoc.v:41205.3-41222.6" + process $proc$libresoc.v:41205$935 + assign { } { } + assign { } { } + assign $0\fast_b[2:0] $1\fast_b[2:0] + attribute \src "libresoc.v:41206.5-41206.29" + switch \initial + attribute \src "libresoc.v:41206.9-41206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fast_b[2:0] $2\fast_b[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + switch { \XL_XO [5] \$3 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\fast_b[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\fast_b[2:0] 3'010 + case + assign $2\fast_b[2:0] 3'000 + end + case + assign $1\fast_b[2:0] 3'000 + end + sync always + update \fast_b $0\fast_b[2:0] + end + attribute \src "libresoc.v:41223.3-41240.6" + process $proc$libresoc.v:41223$936 + assign { } { } + assign { } { } + assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0] + attribute \src "libresoc.v:41224.5-41224.29" + switch \initial + attribute \src "libresoc.v:41224.9-41224.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fast_b_ok[0:0] $2\fast_b_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + switch { \XL_XO [5] \$7 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\fast_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\fast_b_ok[0:0] 1'1 + case + assign $2\fast_b_ok[0:0] 1'0 + end + case + assign $1\fast_b_ok[0:0] 1'0 + end + sync always + update \fast_b_ok $0\fast_b_ok[0:0] + end + connect \$1 $eq$libresoc.v:41171$929_Y + connect \$3 $not$libresoc.v:41172$930_Y + connect \$5 $eq$libresoc.v:41173$931_Y + connect \$7 $not$libresoc.v:41174$932_Y +end +attribute \src "libresoc.v:41245.1-41293.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c" +attribute \generator "nMigen" +module \dec_c + attribute \src "libresoc.v:41246.7-41246.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:41263.3-41277.6" + wire width 5 $0\reg_c[4:0] + attribute \src "libresoc.v:41278.3-41292.6" + wire $0\reg_c_ok[0:0] + attribute \src "libresoc.v:41263.3-41277.6" + wire width 5 $1\reg_c[4:0] + attribute \src "libresoc.v:41278.3-41292.6" + wire $1\reg_c_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 4 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 3 \RS + attribute \src "libresoc.v:41246.7-41246.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 1 \reg_c + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \reg_c_ok + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:41246.7-41246.20" + process $proc$libresoc.v:41246$940 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:41263.3-41277.6" + process $proc$libresoc.v:41263$938 + assign { } { } + assign { } { } + assign $0\reg_c[4:0] $1\reg_c[4:0] + attribute \src "libresoc.v:41264.5-41264.29" + switch \initial + attribute \src "libresoc.v:41264.9-41264.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_c[4:0] \RB + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_c[4:0] \RS + case + assign $1\reg_c[4:0] 5'00000 + end + sync always + update \reg_c $0\reg_c[4:0] + end + attribute \src "libresoc.v:41278.3-41292.6" + process $proc$libresoc.v:41278$939 + assign { } { } + assign { } { } + assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] + attribute \src "libresoc.v:41279.5-41279.29" + switch \initial + attribute \src "libresoc.v:41279.9-41279.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_c_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_c_ok[0:0] 1'1 + case + assign $1\reg_c_ok[0:0] 1'0 + end + sync always + update \reg_c_ok $0\reg_c_ok[0:0] + end +end +attribute \src "libresoc.v:41297.1-41602.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in + attribute \src "libresoc.v:41496.3-41522.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:41523.3-41533.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:41474.3-41484.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:41534.3-41544.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:41545.3-41555.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:41447.3-41473.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:41583.3-41601.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:41485.3-41495.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:41298.7-41298.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:41556.3-41566.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:41567.3-41582.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:41496.3-41522.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:41523.3-41533.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:41474.3-41484.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:41534.3-41544.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:41545.3-41555.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:41447.3-41473.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:41583.3-41601.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:41485.3-41495.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:41556.3-41566.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:41567.3-41582.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:41583.3-41601.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:41567.3-41582.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:41440.17-41440.112" + wire $and$libresoc.v:41440$942_Y + attribute \src "libresoc.v:41442.17-41442.112" + wire $and$libresoc.v:41442$944_Y + attribute \src "libresoc.v:41439.17-41439.117" + wire $eq$libresoc.v:41439$941_Y + attribute \src "libresoc.v:41441.17-41441.117" + wire $eq$libresoc.v:41441$943_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 12 \BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 11 \BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 16 \BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 15 \BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 13 \BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 14 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 17 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 5 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 7 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 8 \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 9 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 10 \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 6 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 output 3 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \cr_fxm_ok + attribute \src "libresoc.v:41298.7-41298.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 input 18 \insn_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 2 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:41440$942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:41440$942_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:41442$944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:41442$944_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:41439$941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:41439$941_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:41441$943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:41441$943_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:41443.9-41446.4" + cell \ppick \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:41298.7-41298.20" + process $proc$libresoc.v:41298$955 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:41447.3-41473.6" + process $proc$libresoc.v:41447$945 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:41448.5-41448.29" + switch \initial + attribute \src "libresoc.v:41448.9-41448.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:41474.3-41484.6" + process $proc$libresoc.v:41474$946 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:41475.5-41475.29" + switch \initial + attribute \src "libresoc.v:41475.9-41475.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:41485.3-41495.6" + process $proc$libresoc.v:41485$947 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:41486.5-41486.29" + switch \initial + attribute \src "libresoc.v:41486.9-41486.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:41496.3-41522.6" + process $proc$libresoc.v:41496$948 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:41497.5-41497.29" + switch \initial + attribute \src "libresoc.v:41497.9-41497.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:41523.3-41533.6" + process $proc$libresoc.v:41523$949 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:41524.5-41524.29" + switch \initial + attribute \src "libresoc.v:41524.9-41524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:41534.3-41544.6" + process $proc$libresoc.v:41534$950 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:41535.5-41535.29" + switch \initial + attribute \src "libresoc.v:41535.9-41535.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:41545.3-41555.6" + process $proc$libresoc.v:41545$951 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:41546.5-41546.29" + switch \initial + attribute \src "libresoc.v:41546.9-41546.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:41556.3-41566.6" + process $proc$libresoc.v:41556$952 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:41557.5-41557.29" + switch \initial + attribute \src "libresoc.v:41557.9-41557.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:41567.3-41582.6" + process $proc$libresoc.v:41567$953 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:41568.5-41568.29" + switch \initial + attribute \src "libresoc.v:41568.9-41568.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:41583.3-41601.6" + process $proc$libresoc.v:41583$954 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:41584.5-41584.29" + switch \initial + attribute \src "libresoc.v:41584.9-41584.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:41439$941_Y + connect \$3 $and$libresoc.v:41440$942_Y + connect \$5 $eq$libresoc.v:41441$943_Y + connect \$7 $and$libresoc.v:41442$944_Y +end +attribute \src "libresoc.v:41606.1-41849.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out + attribute \src "libresoc.v:41763.3-41781.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:41733.3-41751.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:41814.3-41848.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:41752.3-41762.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:41607.7-41607.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:41782.3-41792.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:41793.3-41813.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:41763.3-41781.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:41733.3-41751.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:41814.3-41848.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:41752.3-41762.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:41782.3-41792.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:41793.3-41813.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:41814.3-41848.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:41793.3-41813.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:41814.3-41848.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:41793.3-41813.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:41814.3-41848.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:41726.17-41726.117" + wire $eq$libresoc.v:41726$956_Y + attribute \src "libresoc.v:41727.17-41727.117" + wire $eq$libresoc.v:41727$957_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 8 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 10 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 6 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 7 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 output 4 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \cr_fxm_ok + attribute \src "libresoc.v:41607.7-41607.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 input 11 \insn_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:41726$956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:41726$956_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:41727$957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:41727$957_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:41728.13-41732.4" + cell \ppick$1 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:41607.7-41607.20" + process $proc$libresoc.v:41607$964 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:41733.3-41751.6" + process $proc$libresoc.v:41733$958 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:41734.5-41734.29" + switch \initial + attribute \src "libresoc.v:41734.9-41734.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:41752.3-41762.6" + process $proc$libresoc.v:41752$959 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:41753.5-41753.29" + switch \initial + attribute \src "libresoc.v:41753.9-41753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:41763.3-41781.6" + process $proc$libresoc.v:41763$960 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:41764.5-41764.29" + switch \initial + attribute \src "libresoc.v:41764.9-41764.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:41782.3-41792.6" + process $proc$libresoc.v:41782$961 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:41783.5-41783.29" + switch \initial + attribute \src "libresoc.v:41783.9-41783.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:41793.3-41813.6" + process $proc$libresoc.v:41793$962 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:41794.5-41794.29" + switch \initial + attribute \src "libresoc.v:41794.9-41794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:41814.3-41848.6" + process $proc$libresoc.v:41814$963 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:41815.5-41815.29" + switch \initial + attribute \src "libresoc.v:41815.9-41815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:41726$956_Y + connect \$3 $eq$libresoc.v:41727$957_Y +end +attribute \src "libresoc.v:41853.1-42330.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o" +attribute \generator "nMigen" +module \dec_o + attribute \src "libresoc.v:42291.3-42329.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:42291.3-42329.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:41854.7-41854.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:42217.3-42231.6" + wire width 5 $0\reg_o[4:0] + attribute \src "libresoc.v:42232.3-42246.6" + wire $0\reg_o_ok[0:0] + attribute \src "libresoc.v:42247.3-42257.6" + wire width 10 $0\spr[9:0] + attribute \src "libresoc.v:42274.3-42290.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:42274.3-42290.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:42258.3-42273.6" + wire width 10 $0\sprmap_spr_i[9:0] + attribute \src "libresoc.v:42291.3-42329.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:42291.3-42329.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:42217.3-42231.6" + wire width 5 $1\reg_o[4:0] + attribute \src "libresoc.v:42232.3-42246.6" + wire $1\reg_o_ok[0:0] + attribute \src "libresoc.v:42247.3-42257.6" + wire width 10 $1\spr[9:0] + attribute \src "libresoc.v:42274.3-42290.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:42274.3-42290.6" + wire $1\spr_o_ok[0:0] + attribute \src "libresoc.v:42258.3-42273.6" + wire width 10 $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:42291.3-42329.6" + wire width 3 $2\fast_o[2:0] + attribute \src "libresoc.v:42291.3-42329.6" + wire $2\fast_o_ok[0:0] + attribute \src "libresoc.v:42274.3-42290.6" + wire width 10 $2\spr_o[9:0] + attribute \src "libresoc.v:42274.3-42290.6" + wire $2\spr_o_ok[0:0] + attribute \src "libresoc.v:42258.3-42273.6" + wire width 10 $2\sprmap_spr_i[9:0] + attribute \src "libresoc.v:42291.3-42329.6" + wire width 3 $3\fast_o[2:0] + attribute \src "libresoc.v:42291.3-42329.6" + wire $3\fast_o_ok[0:0] + attribute \src "libresoc.v:42291.3-42329.6" + wire width 3 $4\fast_o[2:0] + attribute \src "libresoc.v:42291.3-42329.6" + wire $4\fast_o_ok[0:0] + attribute \src "libresoc.v:42206.17-42206.117" + wire $eq$libresoc.v:42206$965_Y + attribute \src "libresoc.v:42207.17-42207.117" + wire $eq$libresoc.v:42207$966_Y + attribute \src "libresoc.v:42208.17-42208.117" + wire $eq$libresoc.v:42208$967_Y + attribute \src "libresoc.v:42209.17-42209.104" + wire $not$libresoc.v:42209$968_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 10 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 9 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 input 11 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 6 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 7 \fast_o_ok + attribute \src "libresoc.v:41854.7-41854.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 12 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 2 \reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \reg_o_ok + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" + wire width 2 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + wire width 10 \spr + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 4 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \sprmap_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \sprmap_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + wire width 10 \sprmap_spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \sprmap_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \sprmap_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + cell $eq $eq$libresoc.v:42206$965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:42206$965_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + cell $eq $eq$libresoc.v:42207$966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:42207$966_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + cell $eq $eq$libresoc.v:42208$967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:42208$967_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + cell $not $not$libresoc.v:42209$968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \BO [2] + connect \Y $not$libresoc.v:42209$968_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42210.14-42216.4" + cell \sprmap$2 \sprmap + connect \fast_o \sprmap_fast_o + connect \fast_o_ok \sprmap_fast_o_ok + connect \spr_i \sprmap_spr_i + connect \spr_o \sprmap_spr_o + connect \spr_o_ok \sprmap_spr_o_ok + end + attribute \src "libresoc.v:41854.7-41854.20" + process $proc$libresoc.v:41854$975 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:42217.3-42231.6" + process $proc$libresoc.v:42217$969 + assign { } { } + assign { } { } + assign $0\reg_o[4:0] $1\reg_o[4:0] + attribute \src "libresoc.v:42218.5-42218.29" + switch \initial + attribute \src "libresoc.v:42218.9-42218.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_o[4:0] \RT + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_o[4:0] \RA + case + assign $1\reg_o[4:0] 5'00000 + end + sync always + update \reg_o $0\reg_o[4:0] + end + attribute \src "libresoc.v:42232.3-42246.6" + process $proc$libresoc.v:42232$970 + assign { } { } + assign { } { } + assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] + attribute \src "libresoc.v:42233.5-42233.29" + switch \initial + attribute \src "libresoc.v:42233.9-42233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_o_ok[0:0] 1'1 + case + assign $1\reg_o_ok[0:0] 1'0 + end + sync always + update \reg_o_ok $0\reg_o_ok[0:0] + end + attribute \src "libresoc.v:42247.3-42257.6" + process $proc$libresoc.v:42247$971 + assign { } { } + assign { } { } + assign $0\spr[9:0] $1\spr[9:0] + attribute \src "libresoc.v:42248.5-42248.29" + switch \initial + attribute \src "libresoc.v:42248.9-42248.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } + case + assign $1\spr[9:0] 10'0000000000 + end + sync always + update \spr $0\spr[9:0] + end + attribute \src "libresoc.v:42258.3-42273.6" + process $proc$libresoc.v:42258$972 + assign { } { } + assign { } { } + assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:42259.5-42259.29" + switch \initial + attribute \src "libresoc.v:42259.9-42259.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sprmap_spr_i[9:0] \spr + case + assign $2\sprmap_spr_i[9:0] 10'0000000000 + end + case + assign $1\sprmap_spr_i[9:0] 10'0000000000 + end + sync always + update \sprmap_spr_i $0\sprmap_spr_i[9:0] + end + attribute \src "libresoc.v:42274.3-42290.6" + process $proc$libresoc.v:42274$973 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:42275.5-42275.29" + switch \initial + attribute \src "libresoc.v:42275.9-42275.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign { } { } + assign $1\spr_o[9:0] $2\spr_o[9:0] + assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\spr_o_ok[0:0] $2\spr_o[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } + case + assign $2\spr_o[9:0] 10'0000000000 + assign $2\spr_o_ok[0:0] 1'0 + end + case + assign $1\spr_o[9:0] 10'0000000000 + assign $1\spr_o_ok[0:0] 1'0 + end + sync always + update \spr_o $0\spr_o[9:0] + update \spr_o_ok $0\spr_o_ok[0:0] + end + attribute \src "libresoc.v:42291.3-42329.6" + process $proc$libresoc.v:42291$974 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $3\fast_o[2:0] + assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] + attribute \src "libresoc.v:42292.5-42292.29" + switch \initial + attribute \src "libresoc.v:42292.9-42292.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign { } { } + assign $1\fast_o[2:0] $2\fast_o[2:0] + assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\fast_o_ok[0:0] $2\fast_o[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } + case + assign $2\fast_o[2:0] 3'000 + assign $2\fast_o_ok[0:0] 1'0 + end + case + assign $1\fast_o[2:0] 3'000 + assign $1\fast_o_ok[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:337" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0001000 + assign { } { } + assign { } { } + assign $3\fast_o[2:0] $4\fast_o[2:0] + assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $4\fast_o[2:0] 3'000 + assign $4\fast_o_ok[0:0] 1'1 + case + assign $4\fast_o[2:0] $1\fast_o[2:0] + assign $4\fast_o_ok[0:0] $1\fast_o_ok[0:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign { } { } + assign $3\fast_o[2:0] 3'011 + assign $3\fast_o_ok[0:0] 1'1 + case + assign $3\fast_o[2:0] $1\fast_o[2:0] + assign $3\fast_o_ok[0:0] $1\fast_o_ok[0:0] + end + sync always + update \fast_o $0\fast_o[2:0] + update \fast_o_ok $0\fast_o_ok[0:0] + end + connect \$1 $eq$libresoc.v:42206$965_Y + connect \$3 $eq$libresoc.v:42207$966_Y + connect \$5 $eq$libresoc.v:42208$967_Y + connect \$7 $not$libresoc.v:42209$968_Y +end +attribute \src "libresoc.v:42334.1-42495.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2" +attribute \generator "nMigen" +module \dec_o2 + attribute \src "libresoc.v:42455.3-42474.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:42475.3-42494.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:42335.7-42335.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:42441.3-42454.6" + wire width 5 $0\reg_o[4:0] + attribute \src "libresoc.v:42441.3-42454.6" + wire $0\reg_o_ok[0:0] + attribute \src "libresoc.v:42455.3-42474.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:42475.3-42494.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:42441.3-42454.6" + wire width 5 $1\reg_o[4:0] + attribute \src "libresoc.v:42441.3-42454.6" + wire $1\reg_o_ok[0:0] + attribute \src "libresoc.v:42455.3-42474.6" + wire width 3 $2\fast_o[2:0] + attribute \src "libresoc.v:42475.3-42494.6" + wire $2\fast_o_ok[0:0] + attribute \src "libresoc.v:42439.17-42439.108" + wire $eq$libresoc.v:42439$976_Y + attribute \src "libresoc.v:42440.17-42440.100" + wire width 6 $extend$libresoc.v:42440$977_Y + attribute \src "libresoc.v:42440.17-42440.100" + wire width 6 $pos$libresoc.v:42440$978_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 4 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \fast_o_ok + attribute \src "libresoc.v:42335.7-42335.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 8 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363" + wire input 1 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 2 \reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \reg_o_ok + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 input 6 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" + cell $eq $eq$libresoc.v:42439$976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \upd + connect \B 2'01 + connect \Y $eq$libresoc.v:42439$976_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:42440$977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 6 + connect \A \RA + connect \Y $extend$libresoc.v:42440$977_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:42440$978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A $extend$libresoc.v:42440$977_Y + connect \Y $pos$libresoc.v:42440$978_Y + end + attribute \src "libresoc.v:42335.7-42335.20" + process $proc$libresoc.v:42335$982 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:42441.3-42454.6" + process $proc$libresoc.v:42441$979 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg_o[4:0] $1\reg_o[4:0] + assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] + attribute \src "libresoc.v:42442.5-42442.29" + switch \initial + attribute \src "libresoc.v:42442.9-42442.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\reg_o[4:0] \$3 [4:0] + assign $1\reg_o_ok[0:0] 1'1 + case + assign $1\reg_o[4:0] 5'00000 + assign $1\reg_o_ok[0:0] 1'0 + end + sync always + update \reg_o $0\reg_o[4:0] + update \reg_o_ok $0\reg_o_ok[0:0] + end + attribute \src "libresoc.v:42455.3-42474.6" + process $proc$libresoc.v:42455$980 + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:42456.5-42456.29" + switch \initial + attribute \src "libresoc.v:42456.9-42456.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:381" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0000110 , 7'0001000 + assign { } { } + assign $1\fast_o[2:0] $2\fast_o[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:385" + switch \lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast_o[2:0] 3'001 + case + assign $2\fast_o[2:0] 3'000 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\fast_o[2:0] 3'100 + case + assign $1\fast_o[2:0] 3'000 + end + sync always + update \fast_o $0\fast_o[2:0] + end + attribute \src "libresoc.v:42475.3-42494.6" + process $proc$libresoc.v:42475$981 + assign { } { } + assign { } { } + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:42476.5-42476.29" + switch \initial + attribute \src "libresoc.v:42476.9-42476.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:381" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0000110 , 7'0001000 + assign { } { } + assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:385" + switch \lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast_o_ok[0:0] 1'1 + case + assign $2\fast_o_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + case + assign $1\fast_o_ok[0:0] 1'0 + end + sync always + update \fast_o_ok $0\fast_o_ok[0:0] + end + connect \$1 $eq$libresoc.v:42439$976_Y + connect \$3 $pos$libresoc.v:42440$978_Y +end +attribute \src "libresoc.v:42499.1-42633.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe" +attribute \generator "nMigen" +module \dec_oe + attribute \src "libresoc.v:42500.7-42500.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:42591.3-42611.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:42612.3-42632.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:42591.3-42611.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:42612.3-42632.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:42591.3-42611.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:42612.3-42632.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 4 \OE + attribute \src "libresoc.v:42500.7-42500.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:42500.7-42500.20" + process $proc$libresoc.v:42500$985 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:42591.3-42611.6" + process $proc$libresoc.v:42591$983 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:42592.5-42592.29" + switch \initial + attribute \src "libresoc.v:42592.9-42592.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:42612.3-42632.6" + process $proc$libresoc.v:42612$984 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:42613.5-42613.29" + switch \initial + attribute \src "libresoc.v:42613.9-42613.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:42637.1-42691.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc" +attribute \generator "nMigen" +module \dec_rc + attribute \src "libresoc.v:42638.7-42638.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:42653.3-42671.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:42672.3-42690.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:42653.3-42671.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:42672.3-42690.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 3 \Rc + attribute \src "libresoc.v:42638.7-42638.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:42638.7-42638.20" + process $proc$libresoc.v:42638$988 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:42653.3-42671.6" + process $proc$libresoc.v:42653$986 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:42654.5-42654.29" + switch \initial + attribute \src "libresoc.v:42654.9-42654.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:42672.3-42690.6" + process $proc$libresoc.v:42672$987 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:42673.5-42673.29" + switch \initial + attribute \src "libresoc.v:42673.9-42673.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:42695.1-43017.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.imem" +attribute \generator "nMigen" +module \imem + attribute \src "libresoc.v:42974.3-42988.6" + wire width 45 $0\f_badaddr_o$next[44:0]$1051 + attribute \src "libresoc.v:42835.3-42836.39" + wire width 45 $0\f_badaddr_o[44:0] + attribute \src "libresoc.v:42989.3-43000.6" + wire $0\f_busy_o[0:0] + attribute \src "libresoc.v:42956.3-42973.6" + wire $0\f_fetch_err_o$next[0:0]$1047 + attribute \src "libresoc.v:42837.3-42838.43" + wire $0\f_fetch_err_o[0:0] + attribute \src "libresoc.v:43001.3-43013.6" + wire width 64 $0\f_instr_o[63:0] + attribute \src "libresoc.v:42938.3-42955.6" + wire width 45 $0\ibus__adr$next[44:0]$1043 + attribute \src "libresoc.v:42839.3-42840.35" + wire width 45 $0\ibus__adr[44:0] + attribute \src "libresoc.v:42849.3-42871.6" + wire $0\ibus__cyc$next[0:0]$1023 + attribute \src "libresoc.v:42847.3-42848.35" + wire $0\ibus__cyc[0:0] + attribute \src "libresoc.v:42895.3-42917.6" + wire width 8 $0\ibus__sel$next[7:0]$1033 + attribute \src "libresoc.v:42843.3-42844.35" + wire width 8 $0\ibus__sel[7:0] + attribute \src "libresoc.v:42872.3-42894.6" + wire $0\ibus__stb$next[0:0]$1028 + attribute \src "libresoc.v:42845.3-42846.35" + wire $0\ibus__stb[0:0] + attribute \src "libresoc.v:42918.3-42937.6" + wire width 64 $0\ibus_rdata$next[63:0]$1038 + attribute \src "libresoc.v:42841.3-42842.37" + wire width 64 $0\ibus_rdata[63:0] + attribute \src "libresoc.v:42696.7-42696.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:42974.3-42988.6" + wire width 45 $1\f_badaddr_o$next[44:0]$1052 + attribute \src "libresoc.v:42758.14-42758.44" + wire width 45 $1\f_badaddr_o[44:0] + attribute \src "libresoc.v:42989.3-43000.6" + wire $1\f_busy_o[0:0] + attribute \src "libresoc.v:42956.3-42973.6" + wire $1\f_fetch_err_o$next[0:0]$1048 + attribute \src "libresoc.v:42765.7-42765.27" + wire $1\f_fetch_err_o[0:0] + attribute \src "libresoc.v:43001.3-43013.6" + wire width 64 $1\f_instr_o[63:0] + attribute \src "libresoc.v:42938.3-42955.6" + wire width 45 $1\ibus__adr$next[44:0]$1044 + attribute \src "libresoc.v:42779.14-42779.42" + wire width 45 $1\ibus__adr[44:0] + attribute \src "libresoc.v:42849.3-42871.6" + wire $1\ibus__cyc$next[0:0]$1024 + attribute \src "libresoc.v:42784.7-42784.23" + wire $1\ibus__cyc[0:0] + attribute \src "libresoc.v:42895.3-42917.6" + wire width 8 $1\ibus__sel$next[7:0]$1034 + attribute \src "libresoc.v:42793.13-42793.30" + wire width 8 $1\ibus__sel[7:0] + attribute \src "libresoc.v:42872.3-42894.6" + wire $1\ibus__stb$next[0:0]$1029 + attribute \src "libresoc.v:42798.7-42798.23" + wire $1\ibus__stb[0:0] + attribute \src "libresoc.v:42918.3-42937.6" + wire width 64 $1\ibus_rdata$next[63:0]$1039 + attribute \src "libresoc.v:42802.14-42802.47" + wire width 64 $1\ibus_rdata[63:0] + attribute \src "libresoc.v:42974.3-42988.6" + wire width 45 $2\f_badaddr_o$next[44:0]$1053 + attribute \src "libresoc.v:42956.3-42973.6" + wire $2\f_fetch_err_o$next[0:0]$1049 + attribute \src "libresoc.v:42938.3-42955.6" + wire width 45 $2\ibus__adr$next[44:0]$1045 + attribute \src "libresoc.v:42849.3-42871.6" + wire $2\ibus__cyc$next[0:0]$1025 + attribute \src "libresoc.v:42895.3-42917.6" + wire width 8 $2\ibus__sel$next[7:0]$1035 + attribute \src "libresoc.v:42872.3-42894.6" + wire $2\ibus__stb$next[0:0]$1030 + attribute \src "libresoc.v:42918.3-42937.6" + wire width 64 $2\ibus_rdata$next[63:0]$1040 + attribute \src "libresoc.v:42849.3-42871.6" + wire $3\ibus__cyc$next[0:0]$1026 + attribute \src "libresoc.v:42895.3-42917.6" + wire width 8 $3\ibus__sel$next[7:0]$1036 + attribute \src "libresoc.v:42872.3-42894.6" + wire $3\ibus__stb$next[0:0]$1031 + attribute \src "libresoc.v:42918.3-42937.6" + wire width 64 $3\ibus_rdata$next[63:0]$1041 + attribute \src "libresoc.v:42811.18-42811.110" + wire $and$libresoc.v:42811$991_Y + attribute \src "libresoc.v:42817.18-42817.110" + wire $and$libresoc.v:42817$997_Y + attribute \src "libresoc.v:42822.18-42822.110" + wire $and$libresoc.v:42822$1002_Y + attribute \src "libresoc.v:42825.17-42825.108" + wire $and$libresoc.v:42825$1005_Y + attribute \src "libresoc.v:42828.18-42828.110" + wire $and$libresoc.v:42828$1008_Y + attribute \src "libresoc.v:42829.18-42829.115" + wire $and$libresoc.v:42829$1009_Y + attribute \src "libresoc.v:42831.18-42831.115" + wire $and$libresoc.v:42831$1011_Y + attribute \src "libresoc.v:42810.18-42810.105" + wire $not$libresoc.v:42810$990_Y + attribute \src "libresoc.v:42813.18-42813.105" + wire $not$libresoc.v:42813$993_Y + attribute \src "libresoc.v:42814.17-42814.104" + wire $not$libresoc.v:42814$994_Y + attribute \src "libresoc.v:42816.18-42816.105" + wire $not$libresoc.v:42816$996_Y + attribute \src "libresoc.v:42819.18-42819.105" + wire $not$libresoc.v:42819$999_Y + attribute \src "libresoc.v:42821.18-42821.105" + wire $not$libresoc.v:42821$1001_Y + attribute \src "libresoc.v:42824.18-42824.105" + wire $not$libresoc.v:42824$1004_Y + attribute \src "libresoc.v:42827.18-42827.105" + wire $not$libresoc.v:42827$1007_Y + attribute \src "libresoc.v:42830.18-42830.105" + wire $not$libresoc.v:42830$1010_Y + attribute \src "libresoc.v:42832.18-42832.105" + wire $not$libresoc.v:42832$1012_Y + attribute \src "libresoc.v:42834.17-42834.104" + wire $not$libresoc.v:42834$1014_Y + attribute \src "libresoc.v:42809.17-42809.103" + wire $or$libresoc.v:42809$989_Y + attribute \src "libresoc.v:42812.18-42812.115" + wire $or$libresoc.v:42812$992_Y + attribute \src "libresoc.v:42815.18-42815.106" + wire $or$libresoc.v:42815$995_Y + attribute \src "libresoc.v:42818.18-42818.115" + wire $or$libresoc.v:42818$998_Y + attribute \src "libresoc.v:42820.18-42820.106" + wire $or$libresoc.v:42820$1000_Y + attribute \src "libresoc.v:42823.18-42823.115" + wire $or$libresoc.v:42823$1003_Y + attribute \src "libresoc.v:42826.18-42826.106" + wire $or$libresoc.v:42826$1006_Y + attribute \src "libresoc.v:42833.17-42833.114" + wire $or$libresoc.v:42833$1013_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31" + wire \a_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" + wire width 48 input 1 \a_pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25" + wire \a_stall_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" + wire input 2 \a_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" + wire width 45 \f_badaddr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" + wire width 45 \f_badaddr_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" + wire output 4 \f_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" + wire \f_fetch_err_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" + wire \f_fetch_err_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" + wire width 64 output 5 \f_instr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27" + wire \f_stall_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" + wire input 3 \f_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 8 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 13 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 \ibus__adr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 7 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire \ibus__cyc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 12 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 9 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 11 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 \ibus__sel$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 10 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire \ibus__stb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59" + wire width 64 \ibus_rdata + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59" + wire width 64 \ibus_rdata$next + attribute \src "libresoc.v:42696.7-42696.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" + wire input 14 \intclk_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" + wire input 6 \intclk_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $and $and$libresoc.v:42811$991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$11 + connect \Y $and$libresoc.v:42811$991_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $and $and$libresoc.v:42817$997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$21 + connect \Y $and$libresoc.v:42817$997_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $and $and$libresoc.v:42822$1002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$31 + connect \Y $and$libresoc.v:42822$1002_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $and $and$libresoc.v:42825$1005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$1 + connect \Y $and$libresoc.v:42825$1005_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $and $and$libresoc.v:42828$1008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$41 + connect \Y $and$libresoc.v:42828$1008_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + cell $and $and$libresoc.v:42829$1009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__cyc + connect \B \ibus__err + connect \Y $and$libresoc.v:42829$1009_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + cell $and $and$libresoc.v:42831$1011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__cyc + connect \B \ibus__err + connect \Y $and$libresoc.v:42831$1011_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $not$libresoc.v:42810$990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:42810$990_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $not $not$libresoc.v:42813$993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:42813$993_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $not$libresoc.v:42814$994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:42814$994_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $not$libresoc.v:42816$996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:42816$996_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $not $not$libresoc.v:42819$999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:42819$999_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $not$libresoc.v:42821$1001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:42821$1001_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $not $not$libresoc.v:42824$1004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:42824$1004_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $not$libresoc.v:42827$1007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:42827$1007_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" + cell $not $not$libresoc.v:42830$1010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_stall_i + connect \Y $not$libresoc.v:42830$1010_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" + cell $not $not$libresoc.v:42832$1012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_stall_i + connect \Y $not$libresoc.v:42832$1012_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $not $not$libresoc.v:42834$1014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:42834$1014_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:42809$989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \$7 + connect \Y $or$libresoc.v:42809$989_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:42812$992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:42812$992_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:42815$995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \$17 + connect \Y $or$libresoc.v:42815$995_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:42818$998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:42818$998_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:42820$1000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$25 + connect \B \$27 + connect \Y $or$libresoc.v:42820$1000_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:42823$1003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:42823$1003_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:42826$1006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$35 + connect \B \$37 + connect \Y $or$libresoc.v:42826$1006_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:42833$1013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:42833$1013_Y + end + attribute \src "libresoc.v:42696.7-42696.20" + process $proc$libresoc.v:42696$1056 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:42758.14-42758.44" + process $proc$libresoc.v:42758$1057 + assign { } { } + assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \f_badaddr_o $1\f_badaddr_o[44:0] + end + attribute \src "libresoc.v:42765.7-42765.27" + process $proc$libresoc.v:42765$1058 + assign { } { } + assign $1\f_fetch_err_o[0:0] 1'0 + sync always + sync init + update \f_fetch_err_o $1\f_fetch_err_o[0:0] + end + attribute \src "libresoc.v:42779.14-42779.42" + process $proc$libresoc.v:42779$1059 + assign { } { } + assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \ibus__adr $1\ibus__adr[44:0] + end + attribute \src "libresoc.v:42784.7-42784.23" + process $proc$libresoc.v:42784$1060 + assign { } { } + assign $1\ibus__cyc[0:0] 1'0 + sync always + sync init + update \ibus__cyc $1\ibus__cyc[0:0] + end + attribute \src "libresoc.v:42793.13-42793.30" + process $proc$libresoc.v:42793$1061 + assign { } { } + assign $1\ibus__sel[7:0] 8'00000000 + sync always + sync init + update \ibus__sel $1\ibus__sel[7:0] + end + attribute \src "libresoc.v:42798.7-42798.23" + process $proc$libresoc.v:42798$1062 + assign { } { } + assign $1\ibus__stb[0:0] 1'0 + sync always + sync init + update \ibus__stb $1\ibus__stb[0:0] + end + attribute \src "libresoc.v:42802.14-42802.47" + process $proc$libresoc.v:42802$1063 + assign { } { } + assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ibus_rdata $1\ibus_rdata[63:0] + end + attribute \src "libresoc.v:42835.3-42836.39" + process $proc$libresoc.v:42835$1015 + assign { } { } + assign $0\f_badaddr_o[44:0] \f_badaddr_o$next + sync posedge \intclk_clk + update \f_badaddr_o $0\f_badaddr_o[44:0] + end + attribute \src "libresoc.v:42837.3-42838.43" + process $proc$libresoc.v:42837$1016 + assign { } { } + assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next + sync posedge \intclk_clk + update \f_fetch_err_o $0\f_fetch_err_o[0:0] + end + attribute \src "libresoc.v:42839.3-42840.35" + process $proc$libresoc.v:42839$1017 + assign { } { } + assign $0\ibus__adr[44:0] \ibus__adr$next + sync posedge \intclk_clk + update \ibus__adr $0\ibus__adr[44:0] + end + attribute \src "libresoc.v:42841.3-42842.37" + process $proc$libresoc.v:42841$1018 + assign { } { } + assign $0\ibus_rdata[63:0] \ibus_rdata$next + sync posedge \intclk_clk + update \ibus_rdata $0\ibus_rdata[63:0] + end + attribute \src "libresoc.v:42843.3-42844.35" + process $proc$libresoc.v:42843$1019 + assign { } { } + assign $0\ibus__sel[7:0] \ibus__sel$next + sync posedge \intclk_clk + update \ibus__sel $0\ibus__sel[7:0] + end + attribute \src "libresoc.v:42845.3-42846.35" + process $proc$libresoc.v:42845$1020 + assign { } { } + assign $0\ibus__stb[0:0] \ibus__stb$next + sync posedge \intclk_clk + update \ibus__stb $0\ibus__stb[0:0] + end + attribute \src "libresoc.v:42847.3-42848.35" + process $proc$libresoc.v:42847$1021 + assign { } { } + assign $0\ibus__cyc[0:0] \ibus__cyc$next + sync posedge \intclk_clk + update \ibus__cyc $0\ibus__cyc[0:0] + end + attribute \src "libresoc.v:42849.3-42871.6" + process $proc$libresoc.v:42849$1022 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__cyc$next[0:0]$1023 $3\ibus__cyc$next[0:0]$1026 + attribute \src "libresoc.v:42850.5-42850.29" + switch \initial + attribute \src "libresoc.v:42850.9-42850.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { \$3 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ibus__cyc$next[0:0]$1024 $2\ibus__cyc$next[0:0]$1025 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ibus__cyc$next[0:0]$1025 1'0 + case + assign $2\ibus__cyc$next[0:0]$1025 \ibus__cyc + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ibus__cyc$next[0:0]$1024 1'1 + case + assign $1\ibus__cyc$next[0:0]$1024 \ibus__cyc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__cyc$next[0:0]$1026 1'0 + case + assign $3\ibus__cyc$next[0:0]$1026 $1\ibus__cyc$next[0:0]$1024 + end + sync always + update \ibus__cyc$next $0\ibus__cyc$next[0:0]$1023 + end + attribute \src "libresoc.v:42872.3-42894.6" + process $proc$libresoc.v:42872$1027 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__stb$next[0:0]$1028 $3\ibus__stb$next[0:0]$1031 + attribute \src "libresoc.v:42873.5-42873.29" + switch \initial + attribute \src "libresoc.v:42873.9-42873.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { \$13 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ibus__stb$next[0:0]$1029 $2\ibus__stb$next[0:0]$1030 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ibus__stb$next[0:0]$1030 1'0 + case + assign $2\ibus__stb$next[0:0]$1030 \ibus__stb + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ibus__stb$next[0:0]$1029 1'1 + case + assign $1\ibus__stb$next[0:0]$1029 \ibus__stb + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__stb$next[0:0]$1031 1'0 + case + assign $3\ibus__stb$next[0:0]$1031 $1\ibus__stb$next[0:0]$1029 + end + sync always + update \ibus__stb$next $0\ibus__stb$next[0:0]$1028 + end + attribute \src "libresoc.v:42895.3-42917.6" + process $proc$libresoc.v:42895$1032 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__sel$next[7:0]$1033 $3\ibus__sel$next[7:0]$1036 + attribute \src "libresoc.v:42896.5-42896.29" + switch \initial + attribute \src "libresoc.v:42896.9-42896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { \$23 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ibus__sel$next[7:0]$1034 $2\ibus__sel$next[7:0]$1035 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ibus__sel$next[7:0]$1035 8'00000000 + case + assign $2\ibus__sel$next[7:0]$1035 \ibus__sel + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ibus__sel$next[7:0]$1034 8'11111111 + case + assign $1\ibus__sel$next[7:0]$1034 \ibus__sel + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__sel$next[7:0]$1036 8'00000000 + case + assign $3\ibus__sel$next[7:0]$1036 $1\ibus__sel$next[7:0]$1034 + end + sync always + update \ibus__sel$next $0\ibus__sel$next[7:0]$1033 + end + attribute \src "libresoc.v:42918.3-42937.6" + process $proc$libresoc.v:42918$1037 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus_rdata$next[63:0]$1038 $3\ibus_rdata$next[63:0]$1041 + attribute \src "libresoc.v:42919.5-42919.29" + switch \initial + attribute \src "libresoc.v:42919.9-42919.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { \$33 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ibus_rdata$next[63:0]$1039 $2\ibus_rdata$next[63:0]$1040 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ibus_rdata$next[63:0]$1040 \ibus__dat_r + case + assign $2\ibus_rdata$next[63:0]$1040 \ibus_rdata + end + case + assign $1\ibus_rdata$next[63:0]$1039 \ibus_rdata + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus_rdata$next[63:0]$1041 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\ibus_rdata$next[63:0]$1041 $1\ibus_rdata$next[63:0]$1039 + end + sync always + update \ibus_rdata$next $0\ibus_rdata$next[63:0]$1038 + end + attribute \src "libresoc.v:42938.3-42955.6" + process $proc$libresoc.v:42938$1042 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__adr$next[44:0]$1043 $2\ibus__adr$next[44:0]$1045 + attribute \src "libresoc.v:42939.5-42939.29" + switch \initial + attribute \src "libresoc.v:42939.9-42939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { \$43 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $1\ibus__adr$next[44:0]$1044 \ibus__adr + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ibus__adr$next[44:0]$1044 \a_pc_i [47:3] + case + assign $1\ibus__adr$next[44:0]$1044 \ibus__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ibus__adr$next[44:0]$1045 45'000000000000000000000000000000000000000000000 + case + assign $2\ibus__adr$next[44:0]$1045 $1\ibus__adr$next[44:0]$1044 + end + sync always + update \ibus__adr$next $0\ibus__adr$next[44:0]$1043 + end + attribute \src "libresoc.v:42956.3-42973.6" + process $proc$libresoc.v:42956$1046 + assign { } { } + assign { } { } + assign { } { } + assign $0\f_fetch_err_o$next[0:0]$1047 $2\f_fetch_err_o$next[0:0]$1049 + attribute \src "libresoc.v:42957.5-42957.29" + switch \initial + attribute \src "libresoc.v:42957.9-42957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + switch { \$47 \$45 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\f_fetch_err_o$next[0:0]$1048 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\f_fetch_err_o$next[0:0]$1048 1'0 + case + assign $1\f_fetch_err_o$next[0:0]$1048 \f_fetch_err_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\f_fetch_err_o$next[0:0]$1049 1'0 + case + assign $2\f_fetch_err_o$next[0:0]$1049 $1\f_fetch_err_o$next[0:0]$1048 + end + sync always + update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$1047 + end + attribute \src "libresoc.v:42974.3-42988.6" + process $proc$libresoc.v:42974$1050 + assign { } { } + assign { } { } + assign { } { } + assign $0\f_badaddr_o$next[44:0]$1051 $2\f_badaddr_o$next[44:0]$1053 + attribute \src "libresoc.v:42975.5-42975.29" + switch \initial + attribute \src "libresoc.v:42975.9-42975.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + switch { \$51 \$49 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\f_badaddr_o$next[44:0]$1052 \ibus__adr + case + assign $1\f_badaddr_o$next[44:0]$1052 \f_badaddr_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\f_badaddr_o$next[44:0]$1053 45'000000000000000000000000000000000000000000000 + case + assign $2\f_badaddr_o$next[44:0]$1053 $1\f_badaddr_o$next[44:0]$1052 + end + sync always + update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$1051 + end + attribute \src "libresoc.v:42989.3-43000.6" + process $proc$libresoc.v:42989$1054 + assign { } { } + assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] + attribute \src "libresoc.v:42990.5-42990.29" + switch \initial + attribute \src "libresoc.v:42990.9-42990.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch \f_fetch_err_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_busy_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\f_busy_o[0:0] \ibus__cyc + end + sync always + update \f_busy_o $0\f_busy_o[0:0] + end + attribute \src "libresoc.v:43001.3-43013.6" + process $proc$libresoc.v:43001$1055 + assign { } { } + assign { } { } + assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] + attribute \src "libresoc.v:43002.5-43002.29" + switch \initial + attribute \src "libresoc.v:43002.9-43002.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch \f_fetch_err_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\f_instr_o[63:0] \ibus_rdata + end + sync always + update \f_instr_o $0\f_instr_o[63:0] + end + connect \$9 $or$libresoc.v:42809$989_Y + connect \$11 $not$libresoc.v:42810$990_Y + connect \$13 $and$libresoc.v:42811$991_Y + connect \$15 $or$libresoc.v:42812$992_Y + connect \$17 $not$libresoc.v:42813$993_Y + connect \$1 $not$libresoc.v:42814$994_Y + connect \$19 $or$libresoc.v:42815$995_Y + connect \$21 $not$libresoc.v:42816$996_Y + connect \$23 $and$libresoc.v:42817$997_Y + connect \$25 $or$libresoc.v:42818$998_Y + connect \$27 $not$libresoc.v:42819$999_Y + connect \$29 $or$libresoc.v:42820$1000_Y + connect \$31 $not$libresoc.v:42821$1001_Y + connect \$33 $and$libresoc.v:42822$1002_Y + connect \$35 $or$libresoc.v:42823$1003_Y + connect \$37 $not$libresoc.v:42824$1004_Y + connect \$3 $and$libresoc.v:42825$1005_Y + connect \$39 $or$libresoc.v:42826$1006_Y + connect \$41 $not$libresoc.v:42827$1007_Y + connect \$43 $and$libresoc.v:42828$1008_Y + connect \$45 $and$libresoc.v:42829$1009_Y + connect \$47 $not$libresoc.v:42830$1010_Y + connect \$49 $and$libresoc.v:42831$1011_Y + connect \$51 $not$libresoc.v:42832$1012_Y + connect \$5 $or$libresoc.v:42833$1013_Y + connect \$7 $not$libresoc.v:42834$1014_Y + connect \a_stall_i 1'0 + connect \f_stall_i 1'0 + connect \a_busy_o \ibus__cyc +end +attribute \src "libresoc.v:43021.1-44772.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag" +attribute \generator "nMigen" +module \jtag + attribute \src "libresoc.v:44048.3-44071.6" + wire $0\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:44409.3-44424.6" + wire $0\TAP_tdo[0:0] + attribute \src "libresoc.v:44206.3-44238.6" + wire width 4 $0\dmi0_addr_i$next[3:0]$1275 + attribute \src "libresoc.v:43912.3-43913.39" + wire width 4 $0\dmi0_addr_i[3:0] + attribute \src "libresoc.v:44632.3-44648.6" + wire $0\dmi0_addrsr__oe$next[0:0]$1358 + attribute \src "libresoc.v:43932.3-43933.47" + wire $0\dmi0_addrsr__oe[0:0] + attribute \src "libresoc.v:44649.3-44669.6" + wire width 8 $0\dmi0_addrsr_reg$next[7:0]$1362 + attribute \src "libresoc.v:43930.3-43931.47" + wire width 8 $0\dmi0_addrsr_reg[7:0] + attribute \src "libresoc.v:44614.3-44622.6" + wire $0\dmi0_addrsr_update_core$next[0:0]$1352 + attribute \src "libresoc.v:43936.3-43937.63" + wire $0\dmi0_addrsr_update_core[0:0] + attribute \src "libresoc.v:44623.3-44631.6" + wire $0\dmi0_addrsr_update_core_prev$next[0:0]$1355 + attribute \src "libresoc.v:43934.3-43935.73" + wire $0\dmi0_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:44319.3-44339.6" + wire width 64 $0\dmi0_datasr__i$next[63:0]$1293 + attribute \src "libresoc.v:43906.3-43907.45" + wire width 64 $0\dmi0_datasr__i[63:0] + attribute \src "libresoc.v:44010.3-44026.6" + wire width 2 $0\dmi0_datasr__oe$next[1:0]$1242 + attribute \src "libresoc.v:43924.3-43925.47" + wire width 2 $0\dmi0_datasr__oe[1:0] + attribute \src "libresoc.v:44027.3-44047.6" + wire width 64 $0\dmi0_datasr_reg$next[63:0]$1246 + attribute \src "libresoc.v:43922.3-43923.47" + wire width 64 $0\dmi0_datasr_reg[63:0] + attribute \src "libresoc.v:44670.3-44678.6" + wire $0\dmi0_datasr_update_core$next[0:0]$1367 + attribute \src "libresoc.v:43928.3-43929.63" + wire $0\dmi0_datasr_update_core[0:0] + attribute \src "libresoc.v:44001.3-44009.6" + wire $0\dmi0_datasr_update_core_prev$next[0:0]$1239 + attribute \src "libresoc.v:43926.3-43927.73" + wire $0\dmi0_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:44292.3-44318.6" + wire width 64 $0\dmi0_din$next[63:0]$1288 + attribute \src "libresoc.v:43908.3-43909.33" + wire width 64 $0\dmi0_din[63:0] + attribute \src "libresoc.v:44239.3-44291.6" + wire width 3 $0\fsm_state$275$next[2:0]$1281 + attribute \src "libresoc.v:43910.3-43911.45" + wire width 3 $0\fsm_state$275[2:0]$1210 + attribute \src "libresoc.v:43421.13-43421.35" + wire width 3 $0\fsm_state$275[2:0]$1383 + attribute \src "libresoc.v:44105.3-44157.6" + wire width 3 $0\fsm_state$next[2:0]$1258 + attribute \src "libresoc.v:43918.3-43919.35" + wire width 3 $0\fsm_state[2:0] + attribute \src "libresoc.v:43022.7-43022.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:44425.3-44445.6" + wire width 50 $0\io_bd$next[49:0]$1303 + attribute \src "libresoc.v:43962.3-43963.27" + wire width 50 $0\io_bd[49:0] + attribute \src "libresoc.v:44340.3-44408.6" + wire width 50 $0\io_sr$next[49:0]$1298 + attribute \src "libresoc.v:43964.3-43965.27" + wire width 50 $0\io_sr[49:0] + attribute \src "libresoc.v:44072.3-44104.6" + wire width 29 $0\jtag_wb__adr$next[28:0]$1252 + attribute \src "libresoc.v:43920.3-43921.41" + wire width 29 $0\jtag_wb__adr[28:0] + attribute \src "libresoc.v:44158.3-44184.6" + wire width 64 $0\jtag_wb__dat_w$next[63:0]$1265 + attribute \src "libresoc.v:43916.3-43917.45" + wire width 64 $0\jtag_wb__dat_w[63:0] + attribute \src "libresoc.v:44520.3-44536.6" + wire $0\jtag_wb_addrsr__oe$next[0:0]$1328 + attribute \src "libresoc.v:43948.3-43949.53" + wire $0\jtag_wb_addrsr__oe[0:0] + attribute \src "libresoc.v:44537.3-44557.6" + wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$1332 + attribute \src "libresoc.v:43946.3-43947.53" + wire width 29 $0\jtag_wb_addrsr_reg[28:0] + attribute \src "libresoc.v:44502.3-44510.6" + wire $0\jtag_wb_addrsr_update_core$next[0:0]$1322 + attribute \src "libresoc.v:43952.3-43953.69" + wire $0\jtag_wb_addrsr_update_core[0:0] + attribute \src "libresoc.v:44511.3-44519.6" + wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1325 + attribute \src "libresoc.v:43950.3-43951.79" + wire $0\jtag_wb_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:44185.3-44205.6" + wire width 64 $0\jtag_wb_datasr__i$next[63:0]$1270 + attribute \src "libresoc.v:43914.3-43915.51" + wire width 64 $0\jtag_wb_datasr__i[63:0] + attribute \src "libresoc.v:44576.3-44592.6" + wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$1343 + attribute \src "libresoc.v:43940.3-43941.53" + wire width 2 $0\jtag_wb_datasr__oe[1:0] + attribute \src "libresoc.v:44593.3-44613.6" + wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$1347 + attribute \src "libresoc.v:43938.3-43939.53" + wire width 64 $0\jtag_wb_datasr_reg[63:0] + attribute \src "libresoc.v:44558.3-44566.6" + wire $0\jtag_wb_datasr_update_core$next[0:0]$1337 + attribute \src "libresoc.v:43944.3-43945.69" + wire $0\jtag_wb_datasr_update_core[0:0] + attribute \src "libresoc.v:44567.3-44575.6" + wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$1340 + attribute \src "libresoc.v:43942.3-43943.79" + wire $0\jtag_wb_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:44464.3-44480.6" + wire $0\sr0__oe$next[0:0]$1313 + attribute \src "libresoc.v:43956.3-43957.31" + wire $0\sr0__oe[0:0] + attribute \src "libresoc.v:44481.3-44501.6" + wire width 3 $0\sr0_reg$next[2:0]$1317 + attribute \src "libresoc.v:43954.3-43955.31" + wire width 3 $0\sr0_reg[2:0] + attribute \src "libresoc.v:44446.3-44454.6" + wire $0\sr0_update_core$next[0:0]$1307 + attribute \src "libresoc.v:43960.3-43961.47" + wire $0\sr0_update_core[0:0] + attribute \src "libresoc.v:44455.3-44463.6" + wire $0\sr0_update_core_prev$next[0:0]$1310 + attribute \src "libresoc.v:43958.3-43959.57" + wire $0\sr0_update_core_prev[0:0] + attribute \src "libresoc.v:44048.3-44071.6" + wire $1\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:44409.3-44424.6" + wire $1\TAP_tdo[0:0] + attribute \src "libresoc.v:44206.3-44238.6" + wire width 4 $1\dmi0_addr_i$next[3:0]$1276 + attribute \src "libresoc.v:43346.13-43346.31" + wire width 4 $1\dmi0_addr_i[3:0] + attribute \src "libresoc.v:44632.3-44648.6" + wire $1\dmi0_addrsr__oe$next[0:0]$1359 + attribute \src "libresoc.v:43354.7-43354.29" + wire $1\dmi0_addrsr__oe[0:0] + attribute \src "libresoc.v:44649.3-44669.6" + wire width 8 $1\dmi0_addrsr_reg$next[7:0]$1363 + attribute \src "libresoc.v:43362.13-43362.36" + wire width 8 $1\dmi0_addrsr_reg[7:0] + attribute \src "libresoc.v:44614.3-44622.6" + wire $1\dmi0_addrsr_update_core$next[0:0]$1353 + attribute \src "libresoc.v:43370.7-43370.37" + wire $1\dmi0_addrsr_update_core[0:0] + attribute \src "libresoc.v:44623.3-44631.6" + wire $1\dmi0_addrsr_update_core_prev$next[0:0]$1356 + attribute \src "libresoc.v:43374.7-43374.42" + wire $1\dmi0_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:44319.3-44339.6" + wire width 64 $1\dmi0_datasr__i$next[63:0]$1294 + attribute \src "libresoc.v:43378.14-43378.51" + wire width 64 $1\dmi0_datasr__i[63:0] + attribute \src "libresoc.v:44010.3-44026.6" + wire width 2 $1\dmi0_datasr__oe$next[1:0]$1243 + attribute \src "libresoc.v:43384.13-43384.35" + wire width 2 $1\dmi0_datasr__oe[1:0] + attribute \src "libresoc.v:44027.3-44047.6" + wire width 64 $1\dmi0_datasr_reg$next[63:0]$1247 + attribute \src "libresoc.v:43392.14-43392.52" + wire width 64 $1\dmi0_datasr_reg[63:0] + attribute \src "libresoc.v:44670.3-44678.6" + wire $1\dmi0_datasr_update_core$next[0:0]$1368 + attribute \src "libresoc.v:43400.7-43400.37" + wire $1\dmi0_datasr_update_core[0:0] + attribute \src "libresoc.v:44001.3-44009.6" + wire $1\dmi0_datasr_update_core_prev$next[0:0]$1240 + attribute \src "libresoc.v:43404.7-43404.42" + wire $1\dmi0_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:44292.3-44318.6" + wire width 64 $1\dmi0_din$next[63:0]$1289 + attribute \src "libresoc.v:43409.14-43409.45" + wire width 64 $1\dmi0_din[63:0] + attribute \src "libresoc.v:44239.3-44291.6" + wire width 3 $1\fsm_state$275$next[2:0]$1282 + attribute \src "libresoc.v:44105.3-44157.6" + wire width 3 $1\fsm_state$next[2:0]$1259 + attribute \src "libresoc.v:43419.13-43419.29" + wire width 3 $1\fsm_state[2:0] + attribute \src "libresoc.v:44425.3-44445.6" + wire width 50 $1\io_bd$next[49:0]$1304 + attribute \src "libresoc.v:43623.14-43623.39" + wire width 50 $1\io_bd[49:0] + attribute \src "libresoc.v:44340.3-44408.6" + wire width 50 $1\io_sr$next[49:0]$1299 + attribute \src "libresoc.v:43635.14-43635.39" + wire width 50 $1\io_sr[49:0] + attribute \src "libresoc.v:44072.3-44104.6" + wire width 29 $1\jtag_wb__adr$next[28:0]$1253 + attribute \src "libresoc.v:43644.14-43644.41" + wire width 29 $1\jtag_wb__adr[28:0] + attribute \src "libresoc.v:44158.3-44184.6" + wire width 64 $1\jtag_wb__dat_w$next[63:0]$1266 + attribute \src "libresoc.v:43653.14-43653.51" + wire width 64 $1\jtag_wb__dat_w[63:0] + attribute \src "libresoc.v:44520.3-44536.6" + wire $1\jtag_wb_addrsr__oe$next[0:0]$1329 + attribute \src "libresoc.v:43667.7-43667.32" + wire $1\jtag_wb_addrsr__oe[0:0] + attribute \src "libresoc.v:44537.3-44557.6" + wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$1333 + attribute \src "libresoc.v:43675.14-43675.47" + wire width 29 $1\jtag_wb_addrsr_reg[28:0] + attribute \src "libresoc.v:44502.3-44510.6" + wire $1\jtag_wb_addrsr_update_core$next[0:0]$1323 + attribute \src "libresoc.v:43683.7-43683.40" + wire $1\jtag_wb_addrsr_update_core[0:0] + attribute \src "libresoc.v:44511.3-44519.6" + wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1326 + attribute \src "libresoc.v:43687.7-43687.45" + wire $1\jtag_wb_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:44185.3-44205.6" + wire width 64 $1\jtag_wb_datasr__i$next[63:0]$1271 + attribute \src "libresoc.v:43691.14-43691.54" + wire width 64 $1\jtag_wb_datasr__i[63:0] + attribute \src "libresoc.v:44576.3-44592.6" + wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$1344 + attribute \src "libresoc.v:43697.13-43697.38" + wire width 2 $1\jtag_wb_datasr__oe[1:0] + attribute \src "libresoc.v:44593.3-44613.6" + wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$1348 + attribute \src "libresoc.v:43705.14-43705.55" + wire width 64 $1\jtag_wb_datasr_reg[63:0] + attribute \src "libresoc.v:44558.3-44566.6" + wire $1\jtag_wb_datasr_update_core$next[0:0]$1338 + attribute \src "libresoc.v:43713.7-43713.40" + wire $1\jtag_wb_datasr_update_core[0:0] + attribute \src "libresoc.v:44567.3-44575.6" + wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$1341 + attribute \src "libresoc.v:43717.7-43717.45" + wire $1\jtag_wb_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:44464.3-44480.6" + wire $1\sr0__oe$next[0:0]$1314 + attribute \src "libresoc.v:43733.7-43733.21" + wire $1\sr0__oe[0:0] + attribute \src "libresoc.v:44481.3-44501.6" + wire width 3 $1\sr0_reg$next[2:0]$1318 + attribute \src "libresoc.v:43741.13-43741.27" + wire width 3 $1\sr0_reg[2:0] + attribute \src "libresoc.v:44446.3-44454.6" + wire $1\sr0_update_core$next[0:0]$1308 + attribute \src "libresoc.v:43749.7-43749.29" + wire $1\sr0_update_core[0:0] + attribute \src "libresoc.v:44455.3-44463.6" + wire $1\sr0_update_core_prev$next[0:0]$1311 + attribute \src "libresoc.v:43753.7-43753.34" + wire $1\sr0_update_core_prev[0:0] + attribute \src "libresoc.v:44206.3-44238.6" + wire width 4 $2\dmi0_addr_i$next[3:0]$1277 + attribute \src "libresoc.v:44632.3-44648.6" + wire $2\dmi0_addrsr__oe$next[0:0]$1360 + attribute \src "libresoc.v:44649.3-44669.6" + wire width 8 $2\dmi0_addrsr_reg$next[7:0]$1364 + attribute \src "libresoc.v:44319.3-44339.6" + wire width 64 $2\dmi0_datasr__i$next[63:0]$1295 + attribute \src "libresoc.v:44010.3-44026.6" + wire width 2 $2\dmi0_datasr__oe$next[1:0]$1244 + attribute \src "libresoc.v:44027.3-44047.6" + wire width 64 $2\dmi0_datasr_reg$next[63:0]$1248 + attribute \src "libresoc.v:44292.3-44318.6" + wire width 64 $2\dmi0_din$next[63:0]$1290 + attribute \src "libresoc.v:44239.3-44291.6" + wire width 3 $2\fsm_state$275$next[2:0]$1283 + attribute \src "libresoc.v:44105.3-44157.6" + wire width 3 $2\fsm_state$next[2:0]$1260 + attribute \src "libresoc.v:44425.3-44445.6" + wire width 50 $2\io_bd$next[49:0]$1305 + attribute \src "libresoc.v:44340.3-44408.6" + wire width 50 $2\io_sr$next[49:0]$1300 + attribute \src "libresoc.v:44072.3-44104.6" + wire width 29 $2\jtag_wb__adr$next[28:0]$1254 + attribute \src "libresoc.v:44158.3-44184.6" + wire width 64 $2\jtag_wb__dat_w$next[63:0]$1267 + attribute \src "libresoc.v:44520.3-44536.6" + wire $2\jtag_wb_addrsr__oe$next[0:0]$1330 + attribute \src "libresoc.v:44537.3-44557.6" + wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$1334 + attribute \src "libresoc.v:44185.3-44205.6" + wire width 64 $2\jtag_wb_datasr__i$next[63:0]$1272 + attribute \src "libresoc.v:44576.3-44592.6" + wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$1345 + attribute \src "libresoc.v:44593.3-44613.6" + wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$1349 + attribute \src "libresoc.v:44464.3-44480.6" + wire $2\sr0__oe$next[0:0]$1315 + attribute \src "libresoc.v:44481.3-44501.6" + wire width 3 $2\sr0_reg$next[2:0]$1319 + attribute \src "libresoc.v:44206.3-44238.6" + wire width 4 $3\dmi0_addr_i$next[3:0]$1278 + attribute \src "libresoc.v:44649.3-44669.6" + wire width 8 $3\dmi0_addrsr_reg$next[7:0]$1365 + attribute \src "libresoc.v:44319.3-44339.6" + wire width 64 $3\dmi0_datasr__i$next[63:0]$1296 + attribute \src "libresoc.v:44027.3-44047.6" + wire width 64 $3\dmi0_datasr_reg$next[63:0]$1249 + attribute \src "libresoc.v:44292.3-44318.6" + wire width 64 $3\dmi0_din$next[63:0]$1291 + attribute \src "libresoc.v:44239.3-44291.6" + wire width 3 $3\fsm_state$275$next[2:0]$1284 + attribute \src "libresoc.v:44105.3-44157.6" + wire width 3 $3\fsm_state$next[2:0]$1261 + attribute \src "libresoc.v:44072.3-44104.6" + wire width 29 $3\jtag_wb__adr$next[28:0]$1255 + attribute \src "libresoc.v:44158.3-44184.6" + wire width 64 $3\jtag_wb__dat_w$next[63:0]$1268 + attribute \src "libresoc.v:44537.3-44557.6" + wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$1335 + attribute \src "libresoc.v:44185.3-44205.6" + wire width 64 $3\jtag_wb_datasr__i$next[63:0]$1273 + attribute \src "libresoc.v:44593.3-44613.6" + wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$1350 + attribute \src "libresoc.v:44481.3-44501.6" + wire width 3 $3\sr0_reg$next[2:0]$1320 + attribute \src "libresoc.v:44206.3-44238.6" + wire width 4 $4\dmi0_addr_i$next[3:0]$1279 + attribute \src "libresoc.v:44239.3-44291.6" + wire width 3 $4\fsm_state$275$next[2:0]$1285 + attribute \src "libresoc.v:44105.3-44157.6" + wire width 3 $4\fsm_state$next[2:0]$1262 + attribute \src "libresoc.v:44072.3-44104.6" + wire width 29 $4\jtag_wb__adr$next[28:0]$1256 + attribute \src "libresoc.v:44239.3-44291.6" + wire width 3 $5\fsm_state$275$next[2:0]$1286 + attribute \src "libresoc.v:44105.3-44157.6" + wire width 3 $5\fsm_state$next[2:0]$1263 + attribute \src "libresoc.v:43858.19-43858.110" + wire width 30 $add$libresoc.v:43858$1158_Y + attribute \src "libresoc.v:43859.19-43859.110" + wire width 30 $add$libresoc.v:43859$1159_Y + attribute \src "libresoc.v:43866.19-43866.109" + wire width 5 $add$libresoc.v:43866$1167_Y + attribute \src "libresoc.v:43867.19-43867.109" + wire width 5 $add$libresoc.v:43867$1168_Y + attribute \src "libresoc.v:43791.19-43791.110" + wire $and$libresoc.v:43791$1091_Y + attribute \src "libresoc.v:43798.19-43798.110" + wire $and$libresoc.v:43798$1098_Y + attribute \src "libresoc.v:43801.19-43801.114" + wire $and$libresoc.v:43801$1101_Y + attribute \src "libresoc.v:43803.19-43803.112" + wire $and$libresoc.v:43803$1103_Y + attribute \src "libresoc.v:43805.19-43805.113" + wire $and$libresoc.v:43805$1105_Y + attribute \src "libresoc.v:43807.19-43807.121" + wire $and$libresoc.v:43807$1107_Y + attribute \src "libresoc.v:43811.19-43811.114" + wire $and$libresoc.v:43811$1111_Y + attribute \src "libresoc.v:43813.19-43813.112" + wire $and$libresoc.v:43813$1113_Y + attribute \src "libresoc.v:43815.19-43815.113" + wire $and$libresoc.v:43815$1115_Y + attribute \src "libresoc.v:43817.19-43817.132" + wire $and$libresoc.v:43817$1117_Y + attribute \src "libresoc.v:43820.18-43820.108" + wire $and$libresoc.v:43820$1120_Y + attribute \src "libresoc.v:43823.19-43823.114" + wire $and$libresoc.v:43823$1123_Y + attribute \src "libresoc.v:43825.19-43825.112" + wire $and$libresoc.v:43825$1125_Y + attribute \src "libresoc.v:43827.19-43827.113" + wire $and$libresoc.v:43827$1127_Y + attribute \src "libresoc.v:43829.19-43829.132" + wire $and$libresoc.v:43829$1129_Y + attribute \src "libresoc.v:43831.18-43831.110" + wire $and$libresoc.v:43831$1131_Y + attribute \src "libresoc.v:43833.19-43833.114" + wire $and$libresoc.v:43833$1133_Y + attribute \src "libresoc.v:43835.19-43835.112" + wire $and$libresoc.v:43835$1135_Y + attribute \src "libresoc.v:43837.19-43837.113" + wire $and$libresoc.v:43837$1137_Y + attribute \src "libresoc.v:43839.19-43839.129" + wire $and$libresoc.v:43839$1139_Y + attribute \src "libresoc.v:43844.19-43844.114" + wire $and$libresoc.v:43844$1144_Y + attribute \src "libresoc.v:43846.19-43846.112" + wire $and$libresoc.v:43846$1146_Y + attribute \src "libresoc.v:43848.19-43848.113" + wire $and$libresoc.v:43848$1148_Y + attribute \src "libresoc.v:43850.19-43850.129" + wire $and$libresoc.v:43850$1150_Y + attribute \src "libresoc.v:43870.18-43870.108" + wire $and$libresoc.v:43870$1171_Y + attribute \src "libresoc.v:43871.18-43871.111" + wire $and$libresoc.v:43871$1172_Y + attribute \src "libresoc.v:43895.17-43895.110" + wire $and$libresoc.v:43895$1196_Y + attribute \src "libresoc.v:43764.17-43764.110" + wire $eq$libresoc.v:43764$1064_Y + attribute \src "libresoc.v:43775.18-43775.111" + wire $eq$libresoc.v:43775$1075_Y + attribute \src "libresoc.v:43788.19-43788.112" + wire $eq$libresoc.v:43788$1088_Y + attribute \src "libresoc.v:43789.19-43789.112" + wire $eq$libresoc.v:43789$1089_Y + attribute \src "libresoc.v:43792.19-43792.112" + wire $eq$libresoc.v:43792$1092_Y + attribute \src "libresoc.v:43793.19-43793.112" + wire $eq$libresoc.v:43793$1093_Y + attribute \src "libresoc.v:43795.19-43795.112" + wire $eq$libresoc.v:43795$1095_Y + attribute \src "libresoc.v:43797.18-43797.111" + wire $eq$libresoc.v:43797$1097_Y + attribute \src "libresoc.v:43799.19-43799.112" + wire $eq$libresoc.v:43799$1099_Y + attribute \src "libresoc.v:43809.19-43809.112" + wire $eq$libresoc.v:43809$1109_Y + attribute \src "libresoc.v:43818.19-43818.112" + wire $eq$libresoc.v:43818$1118_Y + attribute \src "libresoc.v:43819.17-43819.110" + wire $eq$libresoc.v:43819$1119_Y + attribute \src "libresoc.v:43821.19-43821.112" + wire $eq$libresoc.v:43821$1121_Y + attribute \src "libresoc.v:43830.19-43830.112" + wire $eq$libresoc.v:43830$1130_Y + attribute \src "libresoc.v:43840.19-43840.112" + wire $eq$libresoc.v:43840$1140_Y + attribute \src "libresoc.v:43841.19-43841.112" + wire $eq$libresoc.v:43841$1141_Y + attribute \src "libresoc.v:43842.18-43842.111" + wire $eq$libresoc.v:43842$1142_Y + attribute \src "libresoc.v:43851.19-43851.108" + wire $eq$libresoc.v:43851$1151_Y + attribute \src "libresoc.v:43853.18-43853.111" + wire $eq$libresoc.v:43853$1153_Y + attribute \src "libresoc.v:43854.19-43854.108" + wire $eq$libresoc.v:43854$1154_Y + attribute \src "libresoc.v:43855.19-43855.108" + wire $eq$libresoc.v:43855$1155_Y + attribute \src "libresoc.v:43857.19-43857.108" + wire $eq$libresoc.v:43857$1157_Y + attribute \src "libresoc.v:43861.19-43861.114" + wire $eq$libresoc.v:43861$1162_Y + attribute \src "libresoc.v:43862.19-43862.114" + wire $eq$libresoc.v:43862$1163_Y + attribute \src "libresoc.v:43865.19-43865.114" + wire $eq$libresoc.v:43865$1166_Y + attribute \src "libresoc.v:43868.18-43868.111" + wire $eq$libresoc.v:43868$1169_Y + attribute \src "libresoc.v:43872.18-43872.111" + wire $eq$libresoc.v:43872$1173_Y + attribute \src "libresoc.v:43873.17-43873.110" + wire $eq$libresoc.v:43873$1174_Y + attribute \src "libresoc.v:43874.18-43874.111" + wire $eq$libresoc.v:43874$1175_Y + attribute \src "libresoc.v:43860.19-43860.98" + wire width 8 $extend$libresoc.v:43860$1160_Y + attribute \src "libresoc.v:43800.19-43800.109" + wire $ne$libresoc.v:43800$1100_Y + attribute \src "libresoc.v:43802.19-43802.109" + wire $ne$libresoc.v:43802$1102_Y + attribute \src "libresoc.v:43804.19-43804.109" + wire $ne$libresoc.v:43804$1104_Y + attribute \src "libresoc.v:43810.19-43810.120" + wire $ne$libresoc.v:43810$1110_Y + attribute \src "libresoc.v:43812.19-43812.120" + wire $ne$libresoc.v:43812$1112_Y + attribute \src "libresoc.v:43814.19-43814.120" + wire $ne$libresoc.v:43814$1114_Y + attribute \src "libresoc.v:43822.19-43822.120" + wire $ne$libresoc.v:43822$1122_Y + attribute \src "libresoc.v:43824.19-43824.120" + wire $ne$libresoc.v:43824$1124_Y + attribute \src "libresoc.v:43826.19-43826.120" + wire $ne$libresoc.v:43826$1126_Y + attribute \src "libresoc.v:43832.19-43832.117" + wire $ne$libresoc.v:43832$1132_Y + attribute \src "libresoc.v:43834.19-43834.117" + wire $ne$libresoc.v:43834$1134_Y + attribute \src "libresoc.v:43836.19-43836.117" + wire $ne$libresoc.v:43836$1136_Y + attribute \src "libresoc.v:43843.19-43843.117" + wire $ne$libresoc.v:43843$1143_Y + attribute \src "libresoc.v:43845.19-43845.117" + wire $ne$libresoc.v:43845$1145_Y + attribute \src "libresoc.v:43847.19-43847.117" + wire $ne$libresoc.v:43847$1147_Y + attribute \src "libresoc.v:43806.19-43806.110" + wire $not$libresoc.v:43806$1106_Y + attribute \src "libresoc.v:43816.19-43816.121" + wire $not$libresoc.v:43816$1116_Y + attribute \src "libresoc.v:43828.19-43828.121" + wire $not$libresoc.v:43828$1128_Y + attribute \src "libresoc.v:43838.19-43838.118" + wire $not$libresoc.v:43838$1138_Y + attribute \src "libresoc.v:43849.19-43849.118" + wire $not$libresoc.v:43849$1149_Y + attribute \src "libresoc.v:43852.19-43852.98" + wire $not$libresoc.v:43852$1152_Y + attribute \src "libresoc.v:43786.18-43786.103" + wire $or$libresoc.v:43786$1086_Y + attribute \src "libresoc.v:43790.19-43790.107" + wire $or$libresoc.v:43790$1090_Y + attribute \src "libresoc.v:43794.19-43794.107" + wire $or$libresoc.v:43794$1094_Y + attribute \src "libresoc.v:43796.19-43796.107" + wire $or$libresoc.v:43796$1096_Y + attribute \src "libresoc.v:43808.18-43808.104" + wire $or$libresoc.v:43808$1108_Y + attribute \src "libresoc.v:43856.19-43856.105" + wire $or$libresoc.v:43856$1156_Y + attribute \src "libresoc.v:43863.18-43863.104" + wire $or$libresoc.v:43863$1164_Y + attribute \src "libresoc.v:43864.19-43864.105" + wire $or$libresoc.v:43864$1165_Y + attribute \src "libresoc.v:43869.18-43869.104" + wire $or$libresoc.v:43869$1170_Y + attribute \src "libresoc.v:43884.17-43884.101" + wire $or$libresoc.v:43884$1185_Y + attribute \src "libresoc.v:43860.19-43860.98" + wire width 8 $pos$libresoc.v:43860$1161_Y + attribute \src "libresoc.v:43765.18-43765.135" + wire $ternary$libresoc.v:43765$1065_Y + attribute \src "libresoc.v:43766.19-43766.135" + wire $ternary$libresoc.v:43766$1066_Y + attribute \src "libresoc.v:43767.19-43767.136" + wire $ternary$libresoc.v:43767$1067_Y + attribute \src "libresoc.v:43768.19-43768.137" + wire $ternary$libresoc.v:43768$1068_Y + attribute \src "libresoc.v:43769.19-43769.136" + wire $ternary$libresoc.v:43769$1069_Y + attribute \src "libresoc.v:43770.19-43770.137" + wire $ternary$libresoc.v:43770$1070_Y + attribute \src "libresoc.v:43771.19-43771.137" + wire $ternary$libresoc.v:43771$1071_Y + attribute \src "libresoc.v:43772.19-43772.136" + wire $ternary$libresoc.v:43772$1072_Y + attribute \src "libresoc.v:43773.19-43773.137" + wire $ternary$libresoc.v:43773$1073_Y + attribute \src "libresoc.v:43774.19-43774.137" + wire $ternary$libresoc.v:43774$1074_Y + attribute \src "libresoc.v:43776.19-43776.136" + wire $ternary$libresoc.v:43776$1076_Y + attribute \src "libresoc.v:43777.19-43777.137" + wire $ternary$libresoc.v:43777$1077_Y + attribute \src "libresoc.v:43778.19-43778.137" + wire $ternary$libresoc.v:43778$1078_Y + attribute \src "libresoc.v:43779.19-43779.136" + wire $ternary$libresoc.v:43779$1079_Y + attribute \src "libresoc.v:43780.19-43780.137" + wire $ternary$libresoc.v:43780$1080_Y + attribute \src "libresoc.v:43781.19-43781.137" + wire $ternary$libresoc.v:43781$1081_Y + attribute \src "libresoc.v:43782.19-43782.136" + wire $ternary$libresoc.v:43782$1082_Y + attribute \src "libresoc.v:43783.19-43783.137" + wire $ternary$libresoc.v:43783$1083_Y + attribute \src "libresoc.v:43784.19-43784.137" + wire $ternary$libresoc.v:43784$1084_Y + attribute \src "libresoc.v:43785.19-43785.136" + wire $ternary$libresoc.v:43785$1085_Y + attribute \src "libresoc.v:43787.19-43787.137" + wire $ternary$libresoc.v:43787$1087_Y + attribute \src "libresoc.v:43875.18-43875.130" + wire $ternary$libresoc.v:43875$1176_Y + attribute \src "libresoc.v:43876.18-43876.131" + wire $ternary$libresoc.v:43876$1177_Y + attribute \src "libresoc.v:43877.18-43877.134" + wire $ternary$libresoc.v:43877$1178_Y + attribute \src "libresoc.v:43878.18-43878.133" + wire $ternary$libresoc.v:43878$1179_Y + attribute \src "libresoc.v:43879.18-43879.134" + wire $ternary$libresoc.v:43879$1180_Y + attribute \src "libresoc.v:43880.18-43880.134" + wire $ternary$libresoc.v:43880$1181_Y + attribute \src "libresoc.v:43881.18-43881.133" + wire $ternary$libresoc.v:43881$1182_Y + attribute \src "libresoc.v:43882.18-43882.134" + wire $ternary$libresoc.v:43882$1183_Y + attribute \src "libresoc.v:43883.18-43883.134" + wire $ternary$libresoc.v:43883$1184_Y + attribute \src "libresoc.v:43885.18-43885.133" + wire $ternary$libresoc.v:43885$1186_Y + attribute \src "libresoc.v:43886.18-43886.135" + wire $ternary$libresoc.v:43886$1187_Y + attribute \src "libresoc.v:43887.18-43887.135" + wire $ternary$libresoc.v:43887$1188_Y + attribute \src "libresoc.v:43888.18-43888.134" + wire $ternary$libresoc.v:43888$1189_Y + attribute \src "libresoc.v:43889.18-43889.135" + wire $ternary$libresoc.v:43889$1190_Y + attribute \src "libresoc.v:43890.18-43890.135" + wire $ternary$libresoc.v:43890$1191_Y + attribute \src "libresoc.v:43891.18-43891.134" + wire $ternary$libresoc.v:43891$1192_Y + attribute \src "libresoc.v:43892.18-43892.135" + wire $ternary$libresoc.v:43892$1193_Y + attribute \src "libresoc.v:43893.18-43893.135" + wire $ternary$libresoc.v:43893$1194_Y + attribute \src "libresoc.v:43894.18-43894.134" + wire $ternary$libresoc.v:43894$1195_Y + attribute \src "libresoc.v:43896.18-43896.135" + wire $ternary$libresoc.v:43896$1197_Y + attribute \src "libresoc.v:43897.18-43897.135" + wire $ternary$libresoc.v:43897$1198_Y + attribute \src "libresoc.v:43898.18-43898.134" + wire $ternary$libresoc.v:43898$1199_Y + attribute \src "libresoc.v:43899.18-43899.135" + wire $ternary$libresoc.v:43899$1200_Y + attribute \src "libresoc.v:43900.18-43900.135" + wire $ternary$libresoc.v:43900$1201_Y + attribute \src "libresoc.v:43901.18-43901.134" + wire $ternary$libresoc.v:43901$1202_Y + attribute \src "libresoc.v:43902.18-43902.135" + wire $ternary$libresoc.v:43902$1203_Y + attribute \src "libresoc.v:43903.18-43903.135" + wire $ternary$libresoc.v:43903$1204_Y + attribute \src "libresoc.v:43904.18-43904.134" + wire $ternary$libresoc.v:43904$1205_Y + attribute \src "libresoc.v:43905.18-43905.135" + wire $ternary$libresoc.v:43905$1206_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$117 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$119 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$121 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$123 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$125 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$127 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$129 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$131 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$133 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$135 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$137 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$139 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$141 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$143 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$145 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$147 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$149 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$151 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$153 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" + wire \$155 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + wire \$157 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + wire \$159 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + wire \$161 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + wire \$163 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + wire \$165 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + wire \$167 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + wire \$169 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + wire \$171 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + wire \$173 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + wire \$175 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + wire \$177 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + wire \$179 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + wire \$181 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + wire \$183 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + wire \$185 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + wire \$187 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + wire \$189 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + wire \$191 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + wire \$193 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + wire \$195 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + wire \$197 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + wire \$199 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + wire \$201 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + wire \$203 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + wire \$205 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + wire \$207 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + wire \$209 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + wire \$211 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + wire \$213 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + wire \$215 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + wire \$217 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + wire \$219 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + wire \$221 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + wire \$223 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + wire \$225 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + wire \$227 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + wire \$229 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + wire \$231 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + wire \$233 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + wire \$235 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + wire \$237 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + wire \$239 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + wire \$241 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + wire \$243 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + wire \$245 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + wire \$247 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + wire \$249 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + wire \$251 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + wire \$253 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:229" + wire \$255 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:229" + wire \$256 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" + wire \$259 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" + wire \$261 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" + wire \$263 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:231" + wire \$265 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:201" + wire width 30 \$267 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:201" + wire width 30 \$268 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:225" + wire width 30 \$270 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:225" + wire width 30 \$271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 8 \$273 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" + wire \$276 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" + wire \$278 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" + wire \$280 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:183" + wire \$282 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:153" + wire width 5 \$284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:153" + wire width 5 \$285 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:177" + wire width 5 \$287 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:177" + wire width 5 \$288 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:386" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:475" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:472" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:382" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 118 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 58 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire output 109 \TAP_bus__tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 119 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" + wire \TAP_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire \_fsm_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire \_fsm_isdr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire \_fsm_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire \_fsm_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:27" + wire \_fsm_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:215" + wire \_idblock_TAP_id_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire width 4 \_irblock_ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:129" + wire \_irblock_tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire input 4 \dmi0_ack_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 output 120 \dmi0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 \dmi0_addr_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:130" + wire width 8 \dmi0_addrsr__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:130" + wire width 8 \dmi0_addrsr__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:130" + wire \dmi0_addrsr__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:130" + wire \dmi0_addrsr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" + wire \dmi0_addrsr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" + wire \dmi0_addrsr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 8 \dmi0_addrsr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 8 \dmi0_addrsr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" + wire \dmi0_addrsr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" + wire \dmi0_addrsr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \dmi0_addrsr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \dmi0_addrsr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \dmi0_addrsr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \dmi0_addrsr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" + wire width 64 \dmi0_datasr__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" + wire width 64 \dmi0_datasr__i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" + wire width 64 \dmi0_datasr__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" + wire width 2 \dmi0_datasr__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" + wire width 2 \dmi0_datasr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" + wire \dmi0_datasr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" + wire width 2 \dmi0_datasr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 64 \dmi0_datasr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 64 \dmi0_datasr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" + wire \dmi0_datasr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" + wire \dmi0_datasr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \dmi0_datasr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \dmi0_datasr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \dmi0_datasr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \dmi0_datasr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 output 3 \dmi0_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 \dmi0_din$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 input 5 \dmi0_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire output 1 \dmi0_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire output 2 \dmi0_we_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" + wire width 3 \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" + wire width 3 \fsm_state$275 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" + wire width 3 \fsm_state$275$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" + wire width 3 \fsm_state$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 61 \gpio_gpio0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 11 \gpio_gpio0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 12 \gpio_gpio0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 10 \gpio_gpio0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 62 \gpio_gpio0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 63 \gpio_gpio0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 91 \gpio_gpio10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 41 \gpio_gpio10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 42 \gpio_gpio10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 40 \gpio_gpio10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 92 \gpio_gpio10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 93 \gpio_gpio10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 94 \gpio_gpio11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 44 \gpio_gpio11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 45 \gpio_gpio11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 43 \gpio_gpio11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 95 \gpio_gpio11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 96 \gpio_gpio11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 97 \gpio_gpio12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 47 \gpio_gpio12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 48 \gpio_gpio12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 46 \gpio_gpio12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 98 \gpio_gpio12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 99 \gpio_gpio12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 100 \gpio_gpio13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 50 \gpio_gpio13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 51 \gpio_gpio13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 49 \gpio_gpio13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 101 \gpio_gpio13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 102 \gpio_gpio13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 103 \gpio_gpio14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 53 \gpio_gpio14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 54 \gpio_gpio14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 52 \gpio_gpio14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 104 \gpio_gpio14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 105 \gpio_gpio14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 106 \gpio_gpio15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 56 \gpio_gpio15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 57 \gpio_gpio15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 55 \gpio_gpio15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 107 \gpio_gpio15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 108 \gpio_gpio15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 64 \gpio_gpio1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 14 \gpio_gpio1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 15 \gpio_gpio1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 13 \gpio_gpio1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 65 \gpio_gpio1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 66 \gpio_gpio1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 67 \gpio_gpio2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 17 \gpio_gpio2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 18 \gpio_gpio2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 16 \gpio_gpio2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 68 \gpio_gpio2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 69 \gpio_gpio2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 70 \gpio_gpio3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 20 \gpio_gpio3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 21 \gpio_gpio3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 19 \gpio_gpio3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 71 \gpio_gpio3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 72 \gpio_gpio3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 73 \gpio_gpio4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 23 \gpio_gpio4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 24 \gpio_gpio4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 22 \gpio_gpio4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 74 \gpio_gpio4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 75 \gpio_gpio4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 76 \gpio_gpio5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 26 \gpio_gpio5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 27 \gpio_gpio5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 25 \gpio_gpio5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 77 \gpio_gpio5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 78 \gpio_gpio5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 79 \gpio_gpio6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 29 \gpio_gpio6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 30 \gpio_gpio6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 28 \gpio_gpio6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 80 \gpio_gpio6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 81 \gpio_gpio6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 82 \gpio_gpio7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 32 \gpio_gpio7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 33 \gpio_gpio7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 31 \gpio_gpio7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 83 \gpio_gpio7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 84 \gpio_gpio7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 85 \gpio_gpio8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 35 \gpio_gpio8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 36 \gpio_gpio8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 34 \gpio_gpio8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 86 \gpio_gpio8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 87 \gpio_gpio8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 88 \gpio_gpio9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 38 \gpio_gpio9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 39 \gpio_gpio9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 37 \gpio_gpio9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 89 \gpio_gpio9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 90 \gpio_gpio9__pad__oe + attribute \src "libresoc.v:43022.7-43022.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" + wire input 6 \intclk_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" + wire input 7 \intclk_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:437" + wire width 50 \io_bd + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:437" + wire width 50 \io_bd$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + wire \io_bd2core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:376" + wire \io_bd2io + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:373" + wire \io_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" + wire \io_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:436" + wire width 50 \io_sr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:436" + wire width 50 \io_sr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" + wire \io_update + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire input 116 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 29 output 110 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 29 \jtag_wb__adr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 112 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 64 input 117 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 64 output 115 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 64 \jtag_wb__dat_w$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 111 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 113 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 114 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:78" + wire width 29 \jtag_wb_addrsr__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:78" + wire width 29 \jtag_wb_addrsr__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:78" + wire \jtag_wb_addrsr__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:78" + wire \jtag_wb_addrsr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" + wire \jtag_wb_addrsr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" + wire \jtag_wb_addrsr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 29 \jtag_wb_addrsr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 29 \jtag_wb_addrsr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" + wire \jtag_wb_addrsr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" + wire \jtag_wb_addrsr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \jtag_wb_addrsr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \jtag_wb_addrsr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \jtag_wb_addrsr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \jtag_wb_addrsr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" + wire width 64 \jtag_wb_datasr__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" + wire width 64 \jtag_wb_datasr__i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" + wire width 64 \jtag_wb_datasr__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" + wire width 2 \jtag_wb_datasr__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" + wire width 2 \jtag_wb_datasr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" + wire \jtag_wb_datasr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" + wire width 2 \jtag_wb_datasr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 64 \jtag_wb_datasr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 64 \jtag_wb_datasr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" + wire \jtag_wb_datasr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" + wire \jtag_wb_datasr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \jtag_wb_datasr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \jtag_wb_datasr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \jtag_wb_datasr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \jtag_wb_datasr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" + wire \negjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" + wire \negjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52" + wire width 3 \sr0__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52" + wire width 3 \sr0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52" + wire \sr0__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52" + wire \sr0__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" + wire \sr0_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" + wire \sr0_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 3 \sr0_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 3 \sr0_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" + wire \sr0_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" + wire \sr0_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \sr0_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \sr0_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \sr0_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \sr0_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 60 \uart_rx__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 9 \uart_rx__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 8 \uart_tx__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 59 \uart_tx__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:201" + cell $add $add$libresoc.v:43858$1158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 29 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 30 + connect \A \jtag_wb__adr + connect \B 1'1 + connect \Y $add$libresoc.v:43858$1158_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:225" + cell $add $add$libresoc.v:43859$1159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 29 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 30 + connect \A \jtag_wb__adr + connect \B 1'1 + connect \Y $add$libresoc.v:43859$1159_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:153" + cell $add $add$libresoc.v:43866$1167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \dmi0_addr_i + connect \B 1'1 + connect \Y $add$libresoc.v:43866$1167_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:177" + cell $add $add$libresoc.v:43867$1168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \dmi0_addr_i + connect \B 1'1 + connect \Y $add$libresoc.v:43867$1168_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $and $and$libresoc.v:43791$1091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$145 + connect \Y $and$libresoc.v:43791$1091_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + cell $and $and$libresoc.v:43798$1098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$157 + connect \Y $and$libresoc.v:43798$1098_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $and $and$libresoc.v:43801$1101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$163 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:43801$1101_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $and $and$libresoc.v:43803$1103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$167 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:43803$1103_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $and $and$libresoc.v:43805$1105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$171 + connect \B \_fsm_update + connect \Y $and$libresoc.v:43805$1105_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $and $and$libresoc.v:43807$1107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_update_core_prev + connect \B \$175 + connect \Y $and$libresoc.v:43807$1107_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $and $and$libresoc.v:43811$1111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$181 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:43811$1111_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $and $and$libresoc.v:43813$1113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$185 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:43813$1113_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $and $and$libresoc.v:43815$1115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$189 + connect \B \_fsm_update + connect \Y $and$libresoc.v:43815$1115_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $and $and$libresoc.v:43817$1117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_update_core_prev + connect \B \$193 + connect \Y $and$libresoc.v:43817$1117_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + cell $and $and$libresoc.v:43820$1120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$17 + connect \Y $and$libresoc.v:43820$1120_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $and $and$libresoc.v:43823$1123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$201 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:43823$1123_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $and $and$libresoc.v:43825$1125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$205 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:43825$1125_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $and $and$libresoc.v:43827$1127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$209 + connect \B \_fsm_update + connect \Y $and$libresoc.v:43827$1127_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $and $and$libresoc.v:43829$1129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_update_core_prev + connect \B \$213 + connect \Y $and$libresoc.v:43829$1129_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" + cell $and $and$libresoc.v:43831$1131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$19 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:43831$1131_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $and $and$libresoc.v:43833$1133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$219 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:43833$1133_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $and $and$libresoc.v:43835$1135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$223 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:43835$1135_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $and $and$libresoc.v:43837$1137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$227 + connect \B \_fsm_update + connect \Y $and$libresoc.v:43837$1137_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $and $and$libresoc.v:43839$1139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_update_core_prev + connect \B \$231 + connect \Y $and$libresoc.v:43839$1139_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $and $and$libresoc.v:43844$1144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$239 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:43844$1144_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $and $and$libresoc.v:43846$1146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$243 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:43846$1146_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $and $and$libresoc.v:43848$1148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$247 + connect \B \_fsm_update + connect \Y $and$libresoc.v:43848$1148_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $and $and$libresoc.v:43850$1150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_update_core_prev + connect \B \$251 + connect \Y $and$libresoc.v:43850$1150_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + cell $and $and$libresoc.v:43870$1171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$31 + connect \Y $and$libresoc.v:43870$1171_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" + cell $and $and$libresoc.v:43871$1172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \_fsm_update + connect \Y $and$libresoc.v:43871$1172_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:382" + cell $and $and$libresoc.v:43895$1196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:43895$1196_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:43764$1064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:43764$1064_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:43775$1075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:43775$1075_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:43788$1088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'1 + connect \Y $eq$libresoc.v:43788$1088_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:43789$1089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1111 + connect \Y $eq$libresoc.v:43789$1089_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:43792$1092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:43792$1092_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:43793$1093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:43793$1093_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" + cell $eq $eq$libresoc.v:43795$1095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:43795$1095_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" + cell $eq $eq$libresoc.v:43797$1097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:43797$1097_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + cell $eq $eq$libresoc.v:43799$1099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 3'100 + connect \Y $eq$libresoc.v:43799$1099_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + cell $eq $eq$libresoc.v:43809$1109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 3'101 + connect \Y $eq$libresoc.v:43809$1109_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + cell $eq $eq$libresoc.v:43818$1118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 3'110 + connect \Y $eq$libresoc.v:43818$1118_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:43819$1119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:43819$1119_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + cell $eq $eq$libresoc.v:43821$1121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 3'111 + connect \Y $eq$libresoc.v:43821$1121_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + cell $eq $eq$libresoc.v:43830$1130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1000 + connect \Y $eq$libresoc.v:43830$1130_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + cell $eq $eq$libresoc.v:43840$1140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1001 + connect \Y $eq$libresoc.v:43840$1140_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + cell $eq $eq$libresoc.v:43841$1141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1010 + connect \Y $eq$libresoc.v:43841$1141_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:43842$1142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:43842$1142_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:229" + cell $eq $eq$libresoc.v:43851$1151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 1'0 + connect \Y $eq$libresoc.v:43851$1151_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:43853$1153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:43853$1153_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" + cell $eq $eq$libresoc.v:43854$1154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 1'1 + connect \Y $eq$libresoc.v:43854$1154_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" + cell $eq $eq$libresoc.v:43855$1155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 2'10 + connect \Y $eq$libresoc.v:43855$1155_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:231" + cell $eq $eq$libresoc.v:43857$1157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 2'10 + connect \Y $eq$libresoc.v:43857$1157_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" + cell $eq $eq$libresoc.v:43861$1162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fsm_state$275 + connect \B 1'1 + connect \Y $eq$libresoc.v:43861$1162_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" + cell $eq $eq$libresoc.v:43862$1163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state$275 + connect \B 2'10 + connect \Y $eq$libresoc.v:43862$1163_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:183" + cell $eq $eq$libresoc.v:43865$1166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state$275 + connect \B 2'10 + connect \Y $eq$libresoc.v:43865$1166_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" + cell $eq $eq$libresoc.v:43868$1169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:43868$1169_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" + cell $eq $eq$libresoc.v:43872$1173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:43872$1173_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:43873$1174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:43873$1174_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:386" + cell $eq $eq$libresoc.v:43874$1175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:43874$1175_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + cell $pos $extend$libresoc.v:43860$1160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \dmi0_addr_i + connect \Y $extend$libresoc.v:43860$1160_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $ne $ne$libresoc.v:43800$1100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43800$1100_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $ne $ne$libresoc.v:43802$1102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43802$1102_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $ne $ne$libresoc.v:43804$1104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43804$1104_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $ne $ne$libresoc.v:43810$1110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43810$1110_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $ne $ne$libresoc.v:43812$1112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43812$1112_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $ne $ne$libresoc.v:43814$1114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43814$1114_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $ne $ne$libresoc.v:43822$1122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43822$1122_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $ne $ne$libresoc.v:43824$1124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43824$1124_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $ne $ne$libresoc.v:43826$1126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43826$1126_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $ne $ne$libresoc.v:43832$1132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43832$1132_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $ne $ne$libresoc.v:43834$1134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43834$1134_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $ne $ne$libresoc.v:43836$1136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43836$1136_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $ne $ne$libresoc.v:43843$1143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43843$1143_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $ne $ne$libresoc.v:43845$1145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43845$1145_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $ne $ne$libresoc.v:43847$1147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43847$1147_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $not $not$libresoc.v:43806$1106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_update_core + connect \Y $not$libresoc.v:43806$1106_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $not $not$libresoc.v:43816$1116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_update_core + connect \Y $not$libresoc.v:43816$1116_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $not $not$libresoc.v:43828$1128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_update_core + connect \Y $not$libresoc.v:43828$1128_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $not $not$libresoc.v:43838$1138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_update_core + connect \Y $not$libresoc.v:43838$1138_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $not $not$libresoc.v:43849$1149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_update_core + connect \Y $not$libresoc.v:43849$1149_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:229" + cell $not $not$libresoc.v:43852$1152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$256 + connect \Y $not$libresoc.v:43852$1152_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $or $or$libresoc.v:43786$1086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \$11 + connect \Y $or$libresoc.v:43786$1086_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $or $or$libresoc.v:43790$1090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$141 + connect \B \$143 + connect \Y $or$libresoc.v:43790$1090_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $or $or$libresoc.v:43794$1094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$149 + connect \B \$151 + connect \Y $or$libresoc.v:43794$1094_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + cell $or $or$libresoc.v:43796$1096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$153 + connect \B \$155 + connect \Y $or$libresoc.v:43796$1096_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + cell $or $or$libresoc.v:43808$1108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$13 + connect \B \$15 + connect \Y $or$libresoc.v:43808$1108_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" + cell $or $or$libresoc.v:43856$1156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$259 + connect \B \$261 + connect \Y $or$libresoc.v:43856$1156_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $or $or$libresoc.v:43863$1164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \B \$25 + connect \Y $or$libresoc.v:43863$1164_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" + cell $or $or$libresoc.v:43864$1165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$276 + connect \B \$278 + connect \Y $or$libresoc.v:43864$1165_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + cell $or $or$libresoc.v:43869$1170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \B \$29 + connect \Y $or$libresoc.v:43869$1170_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $or $or$libresoc.v:43884$1185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $or$libresoc.v:43884$1185_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + cell $pos $pos$libresoc.v:43860$1161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:43860$1160_Y + connect \Y $pos$libresoc.v:43860$1161_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43765$1065 + parameter \WIDTH 1 + connect \A \gpio_gpio9__pad__i + connect \B \io_bd [29] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43765$1065_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43766$1066 + parameter \WIDTH 1 + connect \A \gpio_gpio9__core__o + connect \B \io_bd [30] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43766$1066_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43767$1067 + parameter \WIDTH 1 + connect \A \gpio_gpio9__core__oe + connect \B \io_bd [31] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43767$1067_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43768$1068 + parameter \WIDTH 1 + connect \A \gpio_gpio10__pad__i + connect \B \io_bd [32] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43768$1068_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43769$1069 + parameter \WIDTH 1 + connect \A \gpio_gpio10__core__o + connect \B \io_bd [33] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43769$1069_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43770$1070 + parameter \WIDTH 1 + connect \A \gpio_gpio10__core__oe + connect \B \io_bd [34] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43770$1070_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43771$1071 + parameter \WIDTH 1 + connect \A \gpio_gpio11__pad__i + connect \B \io_bd [35] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43771$1071_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43772$1072 + parameter \WIDTH 1 + connect \A \gpio_gpio11__core__o + connect \B \io_bd [36] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43772$1072_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43773$1073 + parameter \WIDTH 1 + connect \A \gpio_gpio11__core__oe + connect \B \io_bd [37] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43773$1073_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43774$1074 + parameter \WIDTH 1 + connect \A \gpio_gpio12__pad__i + connect \B \io_bd [38] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43774$1074_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43776$1076 + parameter \WIDTH 1 + connect \A \gpio_gpio12__core__o + connect \B \io_bd [39] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43776$1076_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43777$1077 + parameter \WIDTH 1 + connect \A \gpio_gpio12__core__oe + connect \B \io_bd [40] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43777$1077_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43778$1078 + parameter \WIDTH 1 + connect \A \gpio_gpio13__pad__i + connect \B \io_bd [41] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43778$1078_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43779$1079 + parameter \WIDTH 1 + connect \A \gpio_gpio13__core__o + connect \B \io_bd [42] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43779$1079_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43780$1080 + parameter \WIDTH 1 + connect \A \gpio_gpio13__core__oe + connect \B \io_bd [43] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43780$1080_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43781$1081 + parameter \WIDTH 1 + connect \A \gpio_gpio14__pad__i + connect \B \io_bd [44] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43781$1081_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43782$1082 + parameter \WIDTH 1 + connect \A \gpio_gpio14__core__o + connect \B \io_bd [45] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43782$1082_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43783$1083 + parameter \WIDTH 1 + connect \A \gpio_gpio14__core__oe + connect \B \io_bd [46] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43783$1083_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43784$1084 + parameter \WIDTH 1 + connect \A \gpio_gpio15__pad__i + connect \B \io_bd [47] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43784$1084_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43785$1085 + parameter \WIDTH 1 + connect \A \gpio_gpio15__core__o + connect \B \io_bd [48] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43785$1085_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43787$1087 + parameter \WIDTH 1 + connect \A \gpio_gpio15__core__oe + connect \B \io_bd [49] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43787$1087_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:475" + cell $mux $ternary$libresoc.v:43875$1176 + parameter \WIDTH 1 + connect \A \uart_tx__core__o + connect \B \io_bd [0] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43875$1176_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:472" + cell $mux $ternary$libresoc.v:43876$1177 + parameter \WIDTH 1 + connect \A \uart_rx__pad__i + connect \B \io_bd [1] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43876$1177_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43877$1178 + parameter \WIDTH 1 + connect \A \gpio_gpio0__pad__i + connect \B \io_bd [2] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43877$1178_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43878$1179 + parameter \WIDTH 1 + connect \A \gpio_gpio0__core__o + connect \B \io_bd [3] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43878$1179_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43879$1180 + parameter \WIDTH 1 + connect \A \gpio_gpio0__core__oe + connect \B \io_bd [4] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43879$1180_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43880$1181 + parameter \WIDTH 1 + connect \A \gpio_gpio1__pad__i + connect \B \io_bd [5] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43880$1181_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43881$1182 + parameter \WIDTH 1 + connect \A \gpio_gpio1__core__o + connect \B \io_bd [6] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43881$1182_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43882$1183 + parameter \WIDTH 1 + connect \A \gpio_gpio1__core__oe + connect \B \io_bd [7] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43882$1183_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43883$1184 + parameter \WIDTH 1 + connect \A \gpio_gpio2__pad__i + connect \B \io_bd [8] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43883$1184_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43885$1186 + parameter \WIDTH 1 + connect \A \gpio_gpio2__core__o + connect \B \io_bd [9] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43885$1186_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43886$1187 + parameter \WIDTH 1 + connect \A \gpio_gpio2__core__oe + connect \B \io_bd [10] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43886$1187_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43887$1188 + parameter \WIDTH 1 + connect \A \gpio_gpio3__pad__i + connect \B \io_bd [11] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43887$1188_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43888$1189 + parameter \WIDTH 1 + connect \A \gpio_gpio3__core__o + connect \B \io_bd [12] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43888$1189_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43889$1190 + parameter \WIDTH 1 + connect \A \gpio_gpio3__core__oe + connect \B \io_bd [13] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43889$1190_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43890$1191 + parameter \WIDTH 1 + connect \A \gpio_gpio4__pad__i + connect \B \io_bd [14] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43890$1191_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43891$1192 + parameter \WIDTH 1 + connect \A \gpio_gpio4__core__o + connect \B \io_bd [15] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43891$1192_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43892$1193 + parameter \WIDTH 1 + connect \A \gpio_gpio4__core__oe + connect \B \io_bd [16] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43892$1193_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43893$1194 + parameter \WIDTH 1 + connect \A \gpio_gpio5__pad__i + connect \B \io_bd [17] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43893$1194_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43894$1195 + parameter \WIDTH 1 + connect \A \gpio_gpio5__core__o + connect \B \io_bd [18] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43894$1195_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43896$1197 + parameter \WIDTH 1 + connect \A \gpio_gpio5__core__oe + connect \B \io_bd [19] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43896$1197_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43897$1198 + parameter \WIDTH 1 + connect \A \gpio_gpio6__pad__i + connect \B \io_bd [20] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43897$1198_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43898$1199 + parameter \WIDTH 1 + connect \A \gpio_gpio6__core__o + connect \B \io_bd [21] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43898$1199_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43899$1200 + parameter \WIDTH 1 + connect \A \gpio_gpio6__core__oe + connect \B \io_bd [22] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43899$1200_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43900$1201 + parameter \WIDTH 1 + connect \A \gpio_gpio7__pad__i + connect \B \io_bd [23] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43900$1201_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43901$1202 + parameter \WIDTH 1 + connect \A \gpio_gpio7__core__o + connect \B \io_bd [24] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43901$1202_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43902$1203 + parameter \WIDTH 1 + connect \A \gpio_gpio7__core__oe + connect \B \io_bd [25] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43902$1203_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43903$1204 + parameter \WIDTH 1 + connect \A \gpio_gpio8__pad__i + connect \B \io_bd [26] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43903$1204_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43904$1205 + parameter \WIDTH 1 + connect \A \gpio_gpio8__core__o + connect \B \io_bd [27] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43904$1205_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43905$1206 + parameter \WIDTH 1 + connect \A \gpio_gpio8__core__oe + connect \B \io_bd [28] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43905$1206_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43966.8-43978.4" + cell \_fsm \_fsm + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tms \TAP_bus__tms + connect \capture \_fsm_capture + connect \isdr \_fsm_isdr + connect \isir \_fsm_isir + connect \negjtag_clk \negjtag_clk + connect \negjtag_rst \negjtag_rst + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \shift \_fsm_shift + connect \update \_fsm_update + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43979.12-43989.4" + cell \_idblock \_idblock + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_id_tdo \_idblock_TAP_id_tdo + connect \capture \_fsm_capture + connect \ir \_irblock_ir + connect \isdr \_fsm_isdr + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \shift \_fsm_shift + connect \update \_fsm_update + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43990.12-44000.4" + cell \_irblock \_irblock + connect \TAP_bus__tdi \TAP_bus__tdi + connect \capture \_fsm_capture + connect \ir \_irblock_ir + connect \isir \_fsm_isir + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \shift \_fsm_shift + connect \tdo \_irblock_tdo + connect \update \_fsm_update + end + attribute \src "libresoc.v:43022.7-43022.20" + process $proc$libresoc.v:43022$1369 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:43346.13-43346.31" + process $proc$libresoc.v:43346$1370 + assign { } { } + assign $1\dmi0_addr_i[3:0] 4'0000 + sync always + sync init + update \dmi0_addr_i $1\dmi0_addr_i[3:0] + end + attribute \src "libresoc.v:43354.7-43354.29" + process $proc$libresoc.v:43354$1371 + assign { } { } + assign $1\dmi0_addrsr__oe[0:0] 1'0 + sync always + sync init + update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] + end + attribute \src "libresoc.v:43362.13-43362.36" + process $proc$libresoc.v:43362$1372 + assign { } { } + assign $1\dmi0_addrsr_reg[7:0] 8'00000000 + sync always + sync init + update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] + end + attribute \src "libresoc.v:43370.7-43370.37" + process $proc$libresoc.v:43370$1373 + assign { } { } + assign $1\dmi0_addrsr_update_core[0:0] 1'0 + sync always + sync init + update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:43374.7-43374.42" + process $proc$libresoc.v:43374$1374 + assign { } { } + assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 + sync always + sync init + update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:43378.14-43378.51" + process $proc$libresoc.v:43378$1375 + assign { } { } + assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] + end + attribute \src "libresoc.v:43384.13-43384.35" + process $proc$libresoc.v:43384$1376 + assign { } { } + assign $1\dmi0_datasr__oe[1:0] 2'00 + sync always + sync init + update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] + end + attribute \src "libresoc.v:43392.14-43392.52" + process $proc$libresoc.v:43392$1377 + assign { } { } + assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] + end + attribute \src "libresoc.v:43400.7-43400.37" + process $proc$libresoc.v:43400$1378 + assign { } { } + assign $1\dmi0_datasr_update_core[0:0] 1'0 + sync always + sync init + update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] + end + attribute \src "libresoc.v:43404.7-43404.42" + process $proc$libresoc.v:43404$1379 + assign { } { } + assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 + sync always + sync init + update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:43409.14-43409.45" + process $proc$libresoc.v:43409$1380 + assign { } { } + assign $1\dmi0_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dmi0_din $1\dmi0_din[63:0] + end + attribute \src "libresoc.v:43419.13-43419.29" + process $proc$libresoc.v:43419$1381 + assign { } { } + assign $1\fsm_state[2:0] 3'000 + sync always + sync init + update \fsm_state $1\fsm_state[2:0] + end + attribute \src "libresoc.v:43421.13-43421.35" + process $proc$libresoc.v:43421$1382 + assign { } { } + assign $0\fsm_state$275[2:0]$1383 3'000 + sync always + sync init + update \fsm_state$275 $0\fsm_state$275[2:0]$1383 + end + attribute \src "libresoc.v:43623.14-43623.39" + process $proc$libresoc.v:43623$1384 + assign { } { } + assign $1\io_bd[49:0] 50'00000000000000000000000000000000000000000000000000 + sync always + sync init + update \io_bd $1\io_bd[49:0] + end + attribute \src "libresoc.v:43635.14-43635.39" + process $proc$libresoc.v:43635$1385 + assign { } { } + assign $1\io_sr[49:0] 50'00000000000000000000000000000000000000000000000000 + sync always + sync init + update \io_sr $1\io_sr[49:0] + end + attribute \src "libresoc.v:43644.14-43644.41" + process $proc$libresoc.v:43644$1386 + assign { } { } + assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 + sync always + sync init + update \jtag_wb__adr $1\jtag_wb__adr[28:0] + end + attribute \src "libresoc.v:43653.14-43653.51" + process $proc$libresoc.v:43653$1387 + assign { } { } + assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] + end + attribute \src "libresoc.v:43667.7-43667.32" + process $proc$libresoc.v:43667$1388 + assign { } { } + assign $1\jtag_wb_addrsr__oe[0:0] 1'0 + sync always + sync init + update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] + end + attribute \src "libresoc.v:43675.14-43675.47" + process $proc$libresoc.v:43675$1389 + assign { } { } + assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 + sync always + sync init + update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] + end + attribute \src "libresoc.v:43683.7-43683.40" + process $proc$libresoc.v:43683$1390 + assign { } { } + assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 + sync always + sync init + update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:43687.7-43687.45" + process $proc$libresoc.v:43687$1391 + assign { } { } + assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 + sync always + sync init + update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:43691.14-43691.54" + process $proc$libresoc.v:43691$1392 + assign { } { } + assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] + end + attribute \src "libresoc.v:43697.13-43697.38" + process $proc$libresoc.v:43697$1393 + assign { } { } + assign $1\jtag_wb_datasr__oe[1:0] 2'00 + sync always + sync init + update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] + end + attribute \src "libresoc.v:43705.14-43705.55" + process $proc$libresoc.v:43705$1394 + assign { } { } + assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] + end + attribute \src "libresoc.v:43713.7-43713.40" + process $proc$libresoc.v:43713$1395 + assign { } { } + assign $1\jtag_wb_datasr_update_core[0:0] 1'0 + sync always + sync init + update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] + end + attribute \src "libresoc.v:43717.7-43717.45" + process $proc$libresoc.v:43717$1396 + assign { } { } + assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 + sync always + sync init + update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:43733.7-43733.21" + process $proc$libresoc.v:43733$1397 + assign { } { } + assign $1\sr0__oe[0:0] 1'0 + sync always + sync init + update \sr0__oe $1\sr0__oe[0:0] + end + attribute \src "libresoc.v:43741.13-43741.27" + process $proc$libresoc.v:43741$1398 + assign { } { } + assign $1\sr0_reg[2:0] 3'000 + sync always + sync init + update \sr0_reg $1\sr0_reg[2:0] + end + attribute \src "libresoc.v:43749.7-43749.29" + process $proc$libresoc.v:43749$1399 + assign { } { } + assign $1\sr0_update_core[0:0] 1'0 + sync always + sync init + update \sr0_update_core $1\sr0_update_core[0:0] + end + attribute \src "libresoc.v:43753.7-43753.34" + process $proc$libresoc.v:43753$1400 + assign { } { } + assign $1\sr0_update_core_prev[0:0] 1'0 + sync always + sync init + update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] + end + attribute \src "libresoc.v:43906.3-43907.45" + process $proc$libresoc.v:43906$1207 + assign { } { } + assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next + sync posedge \intclk_clk + update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] + end + attribute \src "libresoc.v:43908.3-43909.33" + process $proc$libresoc.v:43908$1208 + assign { } { } + assign $0\dmi0_din[63:0] \dmi0_din$next + sync posedge \intclk_clk + update \dmi0_din $0\dmi0_din[63:0] + end + attribute \src "libresoc.v:43910.3-43911.45" + process $proc$libresoc.v:43910$1209 + assign { } { } + assign $0\fsm_state$275[2:0]$1210 \fsm_state$275$next + sync posedge \intclk_clk + update \fsm_state$275 $0\fsm_state$275[2:0]$1210 + end + attribute \src "libresoc.v:43912.3-43913.39" + process $proc$libresoc.v:43912$1211 + assign { } { } + assign $0\dmi0_addr_i[3:0] \dmi0_addr_i$next + sync posedge \intclk_clk + update \dmi0_addr_i $0\dmi0_addr_i[3:0] + end + attribute \src "libresoc.v:43914.3-43915.51" + process $proc$libresoc.v:43914$1212 + assign { } { } + assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next + sync posedge \intclk_clk + update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] + end + attribute \src "libresoc.v:43916.3-43917.45" + process $proc$libresoc.v:43916$1213 + assign { } { } + assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next + sync posedge \intclk_clk + update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] + end + attribute \src "libresoc.v:43918.3-43919.35" + process $proc$libresoc.v:43918$1214 + assign { } { } + assign $0\fsm_state[2:0] \fsm_state$next + sync posedge \intclk_clk + update \fsm_state $0\fsm_state[2:0] + end + attribute \src "libresoc.v:43920.3-43921.41" + process $proc$libresoc.v:43920$1215 + assign { } { } + assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next + sync posedge \intclk_clk + update \jtag_wb__adr $0\jtag_wb__adr[28:0] + end + attribute \src "libresoc.v:43922.3-43923.47" + process $proc$libresoc.v:43922$1216 + assign { } { } + assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next + sync posedge \posjtag_clk + update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] + end + attribute \src "libresoc.v:43924.3-43925.47" + process $proc$libresoc.v:43924$1217 + assign { } { } + assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next + sync posedge \intclk_clk + update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] + end + attribute \src "libresoc.v:43926.3-43927.73" + process $proc$libresoc.v:43926$1218 + assign { } { } + assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next + sync posedge \intclk_clk + update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:43928.3-43929.63" + process $proc$libresoc.v:43928$1219 + assign { } { } + assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next + sync posedge \intclk_clk + update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] + end + attribute \src "libresoc.v:43930.3-43931.47" + process $proc$libresoc.v:43930$1220 + assign { } { } + assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next + sync posedge \posjtag_clk + update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] + end + attribute \src "libresoc.v:43932.3-43933.47" + process $proc$libresoc.v:43932$1221 + assign { } { } + assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next + sync posedge \intclk_clk + update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] + end + attribute \src "libresoc.v:43934.3-43935.73" + process $proc$libresoc.v:43934$1222 + assign { } { } + assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next + sync posedge \intclk_clk + update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:43936.3-43937.63" + process $proc$libresoc.v:43936$1223 + assign { } { } + assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next + sync posedge \intclk_clk + update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:43938.3-43939.53" + process $proc$libresoc.v:43938$1224 + assign { } { } + assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next + sync posedge \posjtag_clk + update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] + end + attribute \src "libresoc.v:43940.3-43941.53" + process $proc$libresoc.v:43940$1225 + assign { } { } + assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next + sync posedge \intclk_clk + update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] + end + attribute \src "libresoc.v:43942.3-43943.79" + process $proc$libresoc.v:43942$1226 + assign { } { } + assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next + sync posedge \intclk_clk + update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:43944.3-43945.69" + process $proc$libresoc.v:43944$1227 + assign { } { } + assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next + sync posedge \intclk_clk + update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] + end + attribute \src "libresoc.v:43946.3-43947.53" + process $proc$libresoc.v:43946$1228 + assign { } { } + assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next + sync posedge \posjtag_clk + update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] + end + attribute \src "libresoc.v:43948.3-43949.53" + process $proc$libresoc.v:43948$1229 + assign { } { } + assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next + sync posedge \intclk_clk + update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] + end + attribute \src "libresoc.v:43950.3-43951.79" + process $proc$libresoc.v:43950$1230 + assign { } { } + assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next + sync posedge \intclk_clk + update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:43952.3-43953.69" + process $proc$libresoc.v:43952$1231 + assign { } { } + assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next + sync posedge \intclk_clk + update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:43954.3-43955.31" + process $proc$libresoc.v:43954$1232 + assign { } { } + assign $0\sr0_reg[2:0] \sr0_reg$next + sync posedge \posjtag_clk + update \sr0_reg $0\sr0_reg[2:0] + end + attribute \src "libresoc.v:43956.3-43957.31" + process $proc$libresoc.v:43956$1233 + assign { } { } + assign $0\sr0__oe[0:0] \sr0__oe$next + sync posedge \intclk_clk + update \sr0__oe $0\sr0__oe[0:0] + end + attribute \src "libresoc.v:43958.3-43959.57" + process $proc$libresoc.v:43958$1234 + assign { } { } + assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next + sync posedge \intclk_clk + update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] + end + attribute \src "libresoc.v:43960.3-43961.47" + process $proc$libresoc.v:43960$1235 + assign { } { } + assign $0\sr0_update_core[0:0] \sr0_update_core$next + sync posedge \intclk_clk + update \sr0_update_core $0\sr0_update_core[0:0] + end + attribute \src "libresoc.v:43962.3-43963.27" + process $proc$libresoc.v:43962$1236 + assign { } { } + assign $0\io_bd[49:0] \io_bd$next + sync negedge \negjtag_clk + update \io_bd $0\io_bd[49:0] + end + attribute \src "libresoc.v:43964.3-43965.27" + process $proc$libresoc.v:43964$1237 + assign { } { } + assign $0\io_sr[49:0] \io_sr$next + sync posedge \posjtag_clk + update \io_sr $0\io_sr[49:0] + end + attribute \src "libresoc.v:44001.3-44009.6" + process $proc$libresoc.v:44001$1238 + assign { } { } + assign { } { } + assign $0\dmi0_datasr_update_core_prev$next[0:0]$1239 $1\dmi0_datasr_update_core_prev$next[0:0]$1240 + attribute \src "libresoc.v:44002.5-44002.29" + switch \initial + attribute \src "libresoc.v:44002.9-44002.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_update_core_prev$next[0:0]$1240 1'0 + case + assign $1\dmi0_datasr_update_core_prev$next[0:0]$1240 \dmi0_datasr_update_core + end + sync always + update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$1239 + end + attribute \src "libresoc.v:44010.3-44026.6" + process $proc$libresoc.v:44010$1241 + assign { } { } + assign { } { } + assign $0\dmi0_datasr__oe$next[1:0]$1242 $2\dmi0_datasr__oe$next[1:0]$1244 + attribute \src "libresoc.v:44011.5-44011.29" + switch \initial + attribute \src "libresoc.v:44011.9-44011.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + switch \$253 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr__oe$next[1:0]$1243 \dmi0_datasr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi0_datasr__oe$next[1:0]$1243 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr__oe$next[1:0]$1244 2'00 + case + assign $2\dmi0_datasr__oe$next[1:0]$1244 $1\dmi0_datasr__oe$next[1:0]$1243 + end + sync always + update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$1242 + end + attribute \src "libresoc.v:44027.3-44047.6" + process $proc$libresoc.v:44027$1245 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_datasr_reg$next[63:0]$1246 $3\dmi0_datasr_reg$next[63:0]$1249 + attribute \src "libresoc.v:44028.5-44028.29" + switch \initial + attribute \src "libresoc.v:44028.9-44028.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" + switch \dmi0_datasr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_reg$next[63:0]$1247 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } + case + assign $1\dmi0_datasr_reg$next[63:0]$1247 \dmi0_datasr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" + switch \dmi0_datasr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr_reg$next[63:0]$1248 \dmi0_datasr__i + case + assign $2\dmi0_datasr_reg$next[63:0]$1248 $1\dmi0_datasr_reg$next[63:0]$1247 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_datasr_reg$next[63:0]$1249 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0_datasr_reg$next[63:0]$1249 $2\dmi0_datasr_reg$next[63:0]$1248 + end + sync always + update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$1246 + end + attribute \src "libresoc.v:44048.3-44071.6" + process $proc$libresoc.v:44048$1250 + assign { } { } + assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:44049.5-44049.29" + switch \initial + attribute \src "libresoc.v:44049.9-44049.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:571" + switch { \dmi0_datasr_shift \dmi0_addrsr_shift \jtag_wb_datasr_shift \jtag_wb_addrsr_shift \sr0_shift } + attribute \src "libresoc.v:0.0-0.0" + case 5'----1 + assign { } { } + assign $1\TAP_bus__tdo[0:0] \sr0_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 5'---1- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \jtag_wb_addrsr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 5'--1-- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \jtag_wb_datasr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 5'-1--- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \dmi0_addrsr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 5'1---- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \dmi0_datasr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\TAP_bus__tdo[0:0] \TAP_tdo + end + sync always + update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] + end + attribute \src "libresoc.v:44072.3-44104.6" + process $proc$libresoc.v:44072$1251 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb__adr$next[28:0]$1252 $4\jtag_wb__adr$next[28:0]$1256 + attribute \src "libresoc.v:44073.5-44073.29" + switch \initial + attribute \src "libresoc.v:44073.9-44073.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\jtag_wb__adr$next[28:0]$1253 $2\jtag_wb__adr$next[28:0]$1254 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:196" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\jtag_wb__adr$next[28:0]$1254 \jtag_wb_addrsr__o + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\jtag_wb__adr$next[28:0]$1254 \$267 [28:0] + case + assign $2\jtag_wb__adr$next[28:0]$1254 \jtag_wb__adr + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\jtag_wb__adr$next[28:0]$1253 $3\jtag_wb__adr$next[28:0]$1255 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:224" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb__adr$next[28:0]$1255 \$270 [28:0] + case + assign $3\jtag_wb__adr$next[28:0]$1255 \jtag_wb__adr + end + case + assign $1\jtag_wb__adr$next[28:0]$1253 \jtag_wb__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\jtag_wb__adr$next[28:0]$1256 29'00000000000000000000000000000 + case + assign $4\jtag_wb__adr$next[28:0]$1256 $1\jtag_wb__adr$next[28:0]$1253 + end + sync always + update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$1252 + end + attribute \src "libresoc.v:44105.3-44157.6" + process $proc$libresoc.v:44105$1257 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$next[2:0]$1258 $5\fsm_state$next[2:0]$1263 + attribute \src "libresoc.v:44106.5-44106.29" + switch \initial + attribute \src "libresoc.v:44106.9-44106.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\fsm_state$next[2:0]$1259 $2\fsm_state$next[2:0]$1260 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:196" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\fsm_state$next[2:0]$1260 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\fsm_state$next[2:0]$1260 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\fsm_state$next[2:0]$1260 3'010 + case + assign $2\fsm_state$next[2:0]$1260 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fsm_state$next[2:0]$1259 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\fsm_state$next[2:0]$1259 $3\fsm_state$next[2:0]$1261 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:213" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[2:0]$1261 3'000 + case + assign $3\fsm_state$next[2:0]$1261 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\fsm_state$next[2:0]$1259 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\fsm_state$next[2:0]$1259 $4\fsm_state$next[2:0]$1262 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:224" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[2:0]$1262 3'001 + case + assign $4\fsm_state$next[2:0]$1262 \fsm_state + end + case + assign $1\fsm_state$next[2:0]$1259 \fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[2:0]$1263 3'000 + case + assign $5\fsm_state$next[2:0]$1263 $1\fsm_state$next[2:0]$1259 + end + sync always + update \fsm_state$next $0\fsm_state$next[2:0]$1258 + end + attribute \src "libresoc.v:44158.3-44184.6" + process $proc$libresoc.v:44158$1264 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb__dat_w$next[63:0]$1265 $3\jtag_wb__dat_w$next[63:0]$1268 + attribute \src "libresoc.v:44159.5-44159.29" + switch \initial + attribute \src "libresoc.v:44159.9-44159.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\jtag_wb__dat_w$next[63:0]$1266 $2\jtag_wb__dat_w$next[63:0]$1267 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:196" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $2\jtag_wb__dat_w$next[63:0]$1267 \jtag_wb__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $2\jtag_wb__dat_w$next[63:0]$1267 \jtag_wb__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\jtag_wb__dat_w$next[63:0]$1267 \jtag_wb_datasr__o + case + assign $2\jtag_wb__dat_w$next[63:0]$1267 \jtag_wb__dat_w + end + case + assign $1\jtag_wb__dat_w$next[63:0]$1266 \jtag_wb__dat_w + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb__dat_w$next[63:0]$1268 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb__dat_w$next[63:0]$1268 $1\jtag_wb__dat_w$next[63:0]$1266 + end + sync always + update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$1265 + end + attribute \src "libresoc.v:44185.3-44205.6" + process $proc$libresoc.v:44185$1269 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr__i$next[63:0]$1270 $3\jtag_wb_datasr__i$next[63:0]$1273 + attribute \src "libresoc.v:44186.5-44186.29" + switch \initial + attribute \src "libresoc.v:44186.9-44186.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\jtag_wb_datasr__i$next[63:0]$1271 $2\jtag_wb_datasr__i$next[63:0]$1272 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:213" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr__i$next[63:0]$1272 \jtag_wb__dat_r + case + assign $2\jtag_wb_datasr__i$next[63:0]$1272 \jtag_wb_datasr__i + end + case + assign $1\jtag_wb_datasr__i$next[63:0]$1271 \jtag_wb_datasr__i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_datasr__i$next[63:0]$1273 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb_datasr__i$next[63:0]$1273 $1\jtag_wb_datasr__i$next[63:0]$1271 + end + sync always + update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$1270 + end + attribute \src "libresoc.v:44206.3-44238.6" + process $proc$libresoc.v:44206$1274 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_addr_i$next[3:0]$1275 $4\dmi0_addr_i$next[3:0]$1279 + attribute \src "libresoc.v:44207.5-44207.29" + switch \initial + attribute \src "libresoc.v:44207.9-44207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" + switch \fsm_state$275 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\dmi0_addr_i$next[3:0]$1276 $2\dmi0_addr_i$next[3:0]$1277 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:148" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\dmi0_addr_i$next[3:0]$1277 \dmi0_addrsr__o [3:0] + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\dmi0_addr_i$next[3:0]$1277 \$284 [3:0] + case + assign $2\dmi0_addr_i$next[3:0]$1277 \dmi0_addr_i + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\dmi0_addr_i$next[3:0]$1276 $3\dmi0_addr_i$next[3:0]$1278 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:176" + switch \dmi0_ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_addr_i$next[3:0]$1278 \$287 [3:0] + case + assign $3\dmi0_addr_i$next[3:0]$1278 \dmi0_addr_i + end + case + assign $1\dmi0_addr_i$next[3:0]$1276 \dmi0_addr_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\dmi0_addr_i$next[3:0]$1279 4'0000 + case + assign $4\dmi0_addr_i$next[3:0]$1279 $1\dmi0_addr_i$next[3:0]$1276 + end + sync always + update \dmi0_addr_i$next $0\dmi0_addr_i$next[3:0]$1275 + end + attribute \src "libresoc.v:44239.3-44291.6" + process $proc$libresoc.v:44239$1280 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$275$next[2:0]$1281 $5\fsm_state$275$next[2:0]$1286 + attribute \src "libresoc.v:44240.5-44240.29" + switch \initial + attribute \src "libresoc.v:44240.9-44240.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" + switch \fsm_state$275 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\fsm_state$275$next[2:0]$1282 $2\fsm_state$275$next[2:0]$1283 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:148" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\fsm_state$275$next[2:0]$1283 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\fsm_state$275$next[2:0]$1283 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\fsm_state$275$next[2:0]$1283 3'010 + case + assign $2\fsm_state$275$next[2:0]$1283 \fsm_state$275 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fsm_state$275$next[2:0]$1282 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\fsm_state$275$next[2:0]$1282 $3\fsm_state$275$next[2:0]$1284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:165" + switch \dmi0_ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$275$next[2:0]$1284 3'000 + case + assign $3\fsm_state$275$next[2:0]$1284 \fsm_state$275 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\fsm_state$275$next[2:0]$1282 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\fsm_state$275$next[2:0]$1282 $4\fsm_state$275$next[2:0]$1285 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:176" + switch \dmi0_ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$275$next[2:0]$1285 3'001 + case + assign $4\fsm_state$275$next[2:0]$1285 \fsm_state$275 + end + case + assign $1\fsm_state$275$next[2:0]$1282 \fsm_state$275 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$275$next[2:0]$1286 3'000 + case + assign $5\fsm_state$275$next[2:0]$1286 $1\fsm_state$275$next[2:0]$1282 + end + sync always + update \fsm_state$275$next $0\fsm_state$275$next[2:0]$1281 + end + attribute \src "libresoc.v:44292.3-44318.6" + process $proc$libresoc.v:44292$1287 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_din$next[63:0]$1288 $3\dmi0_din$next[63:0]$1291 + attribute \src "libresoc.v:44293.5-44293.29" + switch \initial + attribute \src "libresoc.v:44293.9-44293.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" + switch \fsm_state$275 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\dmi0_din$next[63:0]$1289 $2\dmi0_din$next[63:0]$1290 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:148" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $2\dmi0_din$next[63:0]$1290 \dmi0_din + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $2\dmi0_din$next[63:0]$1290 \dmi0_din + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\dmi0_din$next[63:0]$1290 \dmi0_datasr__o + case + assign $2\dmi0_din$next[63:0]$1290 \dmi0_din + end + case + assign $1\dmi0_din$next[63:0]$1289 \dmi0_din + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_din$next[63:0]$1291 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0_din$next[63:0]$1291 $1\dmi0_din$next[63:0]$1289 + end + sync always + update \dmi0_din$next $0\dmi0_din$next[63:0]$1288 + end + attribute \src "libresoc.v:44319.3-44339.6" + process $proc$libresoc.v:44319$1292 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_datasr__i$next[63:0]$1293 $3\dmi0_datasr__i$next[63:0]$1296 + attribute \src "libresoc.v:44320.5-44320.29" + switch \initial + attribute \src "libresoc.v:44320.9-44320.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" + switch \fsm_state$275 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\dmi0_datasr__i$next[63:0]$1294 $2\dmi0_datasr__i$next[63:0]$1295 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:165" + switch \dmi0_ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr__i$next[63:0]$1295 \dmi0_dout + case + assign $2\dmi0_datasr__i$next[63:0]$1295 \dmi0_datasr__i + end + case + assign $1\dmi0_datasr__i$next[63:0]$1294 \dmi0_datasr__i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_datasr__i$next[63:0]$1296 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0_datasr__i$next[63:0]$1296 $1\dmi0_datasr__i$next[63:0]$1294 + end + sync always + update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$1293 + end + attribute \src "libresoc.v:44340.3-44408.6" + process $proc$libresoc.v:44340$1297 + assign { } { } + assign { } { } + assign { } { } + assign $0\io_sr$next[49:0]$1298 $2\io_sr$next[49:0]$1300 + attribute \src "libresoc.v:44341.5-44341.29" + switch \initial + attribute \src "libresoc.v:44341.9-44341.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:439" + switch { \io_update \io_shift \io_capture } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\io_sr$next[49:0]$1299 [0] \uart_tx__core__o + assign $1\io_sr$next[49:0]$1299 [1] \uart_rx__pad__i + assign $1\io_sr$next[49:0]$1299 [2] \gpio_gpio0__pad__i + assign $1\io_sr$next[49:0]$1299 [3] \gpio_gpio0__core__o + assign $1\io_sr$next[49:0]$1299 [4] \gpio_gpio0__core__oe + assign $1\io_sr$next[49:0]$1299 [5] \gpio_gpio1__pad__i + assign $1\io_sr$next[49:0]$1299 [6] \gpio_gpio1__core__o + assign $1\io_sr$next[49:0]$1299 [7] \gpio_gpio1__core__oe + assign $1\io_sr$next[49:0]$1299 [8] \gpio_gpio2__pad__i + assign $1\io_sr$next[49:0]$1299 [9] \gpio_gpio2__core__o + assign $1\io_sr$next[49:0]$1299 [10] \gpio_gpio2__core__oe + assign $1\io_sr$next[49:0]$1299 [11] \gpio_gpio3__pad__i + assign $1\io_sr$next[49:0]$1299 [12] \gpio_gpio3__core__o + assign $1\io_sr$next[49:0]$1299 [13] \gpio_gpio3__core__oe + assign $1\io_sr$next[49:0]$1299 [14] \gpio_gpio4__pad__i + assign $1\io_sr$next[49:0]$1299 [15] \gpio_gpio4__core__o + assign $1\io_sr$next[49:0]$1299 [16] \gpio_gpio4__core__oe + assign $1\io_sr$next[49:0]$1299 [17] \gpio_gpio5__pad__i + assign $1\io_sr$next[49:0]$1299 [18] \gpio_gpio5__core__o + assign $1\io_sr$next[49:0]$1299 [19] \gpio_gpio5__core__oe + assign $1\io_sr$next[49:0]$1299 [20] \gpio_gpio6__pad__i + assign $1\io_sr$next[49:0]$1299 [21] \gpio_gpio6__core__o + assign $1\io_sr$next[49:0]$1299 [22] \gpio_gpio6__core__oe + assign $1\io_sr$next[49:0]$1299 [23] \gpio_gpio7__pad__i + assign $1\io_sr$next[49:0]$1299 [24] \gpio_gpio7__core__o + assign $1\io_sr$next[49:0]$1299 [25] \gpio_gpio7__core__oe + assign $1\io_sr$next[49:0]$1299 [26] \gpio_gpio8__pad__i + assign $1\io_sr$next[49:0]$1299 [27] \gpio_gpio8__core__o + assign $1\io_sr$next[49:0]$1299 [28] \gpio_gpio8__core__oe + assign $1\io_sr$next[49:0]$1299 [29] \gpio_gpio9__pad__i + assign $1\io_sr$next[49:0]$1299 [30] \gpio_gpio9__core__o + assign $1\io_sr$next[49:0]$1299 [31] \gpio_gpio9__core__oe + assign $1\io_sr$next[49:0]$1299 [32] \gpio_gpio10__pad__i + assign $1\io_sr$next[49:0]$1299 [33] \gpio_gpio10__core__o + assign $1\io_sr$next[49:0]$1299 [34] \gpio_gpio10__core__oe + assign $1\io_sr$next[49:0]$1299 [35] \gpio_gpio11__pad__i + assign $1\io_sr$next[49:0]$1299 [36] \gpio_gpio11__core__o + assign $1\io_sr$next[49:0]$1299 [37] \gpio_gpio11__core__oe + assign $1\io_sr$next[49:0]$1299 [38] \gpio_gpio12__pad__i + assign $1\io_sr$next[49:0]$1299 [39] \gpio_gpio12__core__o + assign $1\io_sr$next[49:0]$1299 [40] \gpio_gpio12__core__oe + assign $1\io_sr$next[49:0]$1299 [41] \gpio_gpio13__pad__i + assign $1\io_sr$next[49:0]$1299 [42] \gpio_gpio13__core__o + assign $1\io_sr$next[49:0]$1299 [43] \gpio_gpio13__core__oe + assign $1\io_sr$next[49:0]$1299 [44] \gpio_gpio14__pad__i + assign $1\io_sr$next[49:0]$1299 [45] \gpio_gpio14__core__o + assign $1\io_sr$next[49:0]$1299 [46] \gpio_gpio14__core__oe + assign $1\io_sr$next[49:0]$1299 [47] \gpio_gpio15__pad__i + assign $1\io_sr$next[49:0]$1299 [48] \gpio_gpio15__core__o + assign $1\io_sr$next[49:0]$1299 [49] \gpio_gpio15__core__oe + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\io_sr$next[49:0]$1299 { \io_sr [48:0] \TAP_bus__tdi } + case + assign $1\io_sr$next[49:0]$1299 \io_sr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\io_sr$next[49:0]$1300 50'00000000000000000000000000000000000000000000000000 + case + assign $2\io_sr$next[49:0]$1300 $1\io_sr$next[49:0]$1299 + end + sync always + update \io_sr$next $0\io_sr$next[49:0]$1298 + end + attribute \src "libresoc.v:44409.3-44424.6" + process $proc$libresoc.v:44409$1301 + assign { } { } + assign { } { } + assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] + attribute \src "libresoc.v:44410.5-44410.29" + switch \initial + attribute \src "libresoc.v:44410.9-44410.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" + switch { \$159 \$147 \_fsm_isir } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\TAP_tdo[0:0] \_irblock_tdo + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\TAP_tdo[0:0] \_idblock_TAP_id_tdo + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\TAP_tdo[0:0] \io_sr [49] + case + assign $1\TAP_tdo[0:0] 1'0 + end + sync always + update \TAP_tdo $0\TAP_tdo[0:0] + end + attribute \src "libresoc.v:44425.3-44445.6" + process $proc$libresoc.v:44425$1302 + assign { } { } + assign { } { } + assign { } { } + assign $0\io_bd$next[49:0]$1303 $2\io_bd$next[49:0]$1305 + attribute \src "libresoc.v:44426.5-44426.29" + switch \initial + attribute \src "libresoc.v:44426.9-44426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:439" + switch { \io_update \io_shift \io_capture } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $1\io_bd$next[49:0]$1304 \io_bd + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $1\io_bd$next[49:0]$1304 \io_bd + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\io_bd$next[49:0]$1304 \io_sr + case + assign $1\io_bd$next[49:0]$1304 \io_bd + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \negjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\io_bd$next[49:0]$1305 50'00000000000000000000000000000000000000000000000000 + case + assign $2\io_bd$next[49:0]$1305 $1\io_bd$next[49:0]$1304 + end + sync always + update \io_bd$next $0\io_bd$next[49:0]$1303 + end + attribute \src "libresoc.v:44446.3-44454.6" + process $proc$libresoc.v:44446$1306 + assign { } { } + assign { } { } + assign $0\sr0_update_core$next[0:0]$1307 $1\sr0_update_core$next[0:0]$1308 + attribute \src "libresoc.v:44447.5-44447.29" + switch \initial + attribute \src "libresoc.v:44447.9-44447.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_update_core$next[0:0]$1308 1'0 + case + assign $1\sr0_update_core$next[0:0]$1308 \sr0_update + end + sync always + update \sr0_update_core$next $0\sr0_update_core$next[0:0]$1307 + end + attribute \src "libresoc.v:44455.3-44463.6" + process $proc$libresoc.v:44455$1309 + assign { } { } + assign { } { } + assign $0\sr0_update_core_prev$next[0:0]$1310 $1\sr0_update_core_prev$next[0:0]$1311 + attribute \src "libresoc.v:44456.5-44456.29" + switch \initial + attribute \src "libresoc.v:44456.9-44456.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_update_core_prev$next[0:0]$1311 1'0 + case + assign $1\sr0_update_core_prev$next[0:0]$1311 \sr0_update_core + end + sync always + update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$1310 + end + attribute \src "libresoc.v:44464.3-44480.6" + process $proc$libresoc.v:44464$1312 + assign { } { } + assign { } { } + assign $0\sr0__oe$next[0:0]$1313 $2\sr0__oe$next[0:0]$1315 + attribute \src "libresoc.v:44465.5-44465.29" + switch \initial + attribute \src "libresoc.v:44465.9-44465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + switch \$177 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0__oe$next[0:0]$1314 \sr0_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\sr0__oe$next[0:0]$1314 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr0__oe$next[0:0]$1315 1'0 + case + assign $2\sr0__oe$next[0:0]$1315 $1\sr0__oe$next[0:0]$1314 + end + sync always + update \sr0__oe$next $0\sr0__oe$next[0:0]$1313 + end + attribute \src "libresoc.v:44481.3-44501.6" + process $proc$libresoc.v:44481$1316 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr0_reg$next[2:0]$1317 $3\sr0_reg$next[2:0]$1320 + attribute \src "libresoc.v:44482.5-44482.29" + switch \initial + attribute \src "libresoc.v:44482.9-44482.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" + switch \sr0_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_reg$next[2:0]$1318 { \TAP_bus__tdi \sr0_reg [2:1] } + case + assign $1\sr0_reg$next[2:0]$1318 \sr0_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" + switch \sr0_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr0_reg$next[2:0]$1319 \sr0__i + case + assign $2\sr0_reg$next[2:0]$1319 $1\sr0_reg$next[2:0]$1318 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sr0_reg$next[2:0]$1320 3'000 + case + assign $3\sr0_reg$next[2:0]$1320 $2\sr0_reg$next[2:0]$1319 + end + sync always + update \sr0_reg$next $0\sr0_reg$next[2:0]$1317 + end + attribute \src "libresoc.v:44502.3-44510.6" + process $proc$libresoc.v:44502$1321 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_update_core$next[0:0]$1322 $1\jtag_wb_addrsr_update_core$next[0:0]$1323 + attribute \src "libresoc.v:44503.5-44503.29" + switch \initial + attribute \src "libresoc.v:44503.9-44503.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_update_core$next[0:0]$1323 1'0 + case + assign $1\jtag_wb_addrsr_update_core$next[0:0]$1323 \jtag_wb_addrsr_update + end + sync always + update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$1322 + end + attribute \src "libresoc.v:44511.3-44519.6" + process $proc$libresoc.v:44511$1324 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1325 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1326 + attribute \src "libresoc.v:44512.5-44512.29" + switch \initial + attribute \src "libresoc.v:44512.9-44512.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1326 1'0 + case + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1326 \jtag_wb_addrsr_update_core + end + sync always + update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1325 + end + attribute \src "libresoc.v:44520.3-44536.6" + process $proc$libresoc.v:44520$1327 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr__oe$next[0:0]$1328 $2\jtag_wb_addrsr__oe$next[0:0]$1330 + attribute \src "libresoc.v:44521.5-44521.29" + switch \initial + attribute \src "libresoc.v:44521.9-44521.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + switch \$195 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr__oe$next[0:0]$1329 \jtag_wb_addrsr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\jtag_wb_addrsr__oe$next[0:0]$1329 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_addrsr__oe$next[0:0]$1330 1'0 + case + assign $2\jtag_wb_addrsr__oe$next[0:0]$1330 $1\jtag_wb_addrsr__oe$next[0:0]$1329 + end + sync always + update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$1328 + end + attribute \src "libresoc.v:44537.3-44557.6" + process $proc$libresoc.v:44537$1331 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_reg$next[28:0]$1332 $3\jtag_wb_addrsr_reg$next[28:0]$1335 + attribute \src "libresoc.v:44538.5-44538.29" + switch \initial + attribute \src "libresoc.v:44538.9-44538.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" + switch \jtag_wb_addrsr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_reg$next[28:0]$1333 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } + case + assign $1\jtag_wb_addrsr_reg$next[28:0]$1333 \jtag_wb_addrsr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" + switch \jtag_wb_addrsr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_addrsr_reg$next[28:0]$1334 \jtag_wb_addrsr__i + case + assign $2\jtag_wb_addrsr_reg$next[28:0]$1334 $1\jtag_wb_addrsr_reg$next[28:0]$1333 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_addrsr_reg$next[28:0]$1335 29'00000000000000000000000000000 + case + assign $3\jtag_wb_addrsr_reg$next[28:0]$1335 $2\jtag_wb_addrsr_reg$next[28:0]$1334 + end + sync always + update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$1332 + end + attribute \src "libresoc.v:44558.3-44566.6" + process $proc$libresoc.v:44558$1336 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_update_core$next[0:0]$1337 $1\jtag_wb_datasr_update_core$next[0:0]$1338 + attribute \src "libresoc.v:44559.5-44559.29" + switch \initial + attribute \src "libresoc.v:44559.9-44559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_update_core$next[0:0]$1338 1'0 + case + assign $1\jtag_wb_datasr_update_core$next[0:0]$1338 \jtag_wb_datasr_update + end + sync always + update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$1337 + end + attribute \src "libresoc.v:44567.3-44575.6" + process $proc$libresoc.v:44567$1339 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$1340 $1\jtag_wb_datasr_update_core_prev$next[0:0]$1341 + attribute \src "libresoc.v:44568.5-44568.29" + switch \initial + attribute \src "libresoc.v:44568.9-44568.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$1341 1'0 + case + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$1341 \jtag_wb_datasr_update_core + end + sync always + update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$1340 + end + attribute \src "libresoc.v:44576.3-44592.6" + process $proc$libresoc.v:44576$1342 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr__oe$next[1:0]$1343 $2\jtag_wb_datasr__oe$next[1:0]$1345 + attribute \src "libresoc.v:44577.5-44577.29" + switch \initial + attribute \src "libresoc.v:44577.9-44577.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + switch \$215 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr__oe$next[1:0]$1344 \jtag_wb_datasr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\jtag_wb_datasr__oe$next[1:0]$1344 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr__oe$next[1:0]$1345 2'00 + case + assign $2\jtag_wb_datasr__oe$next[1:0]$1345 $1\jtag_wb_datasr__oe$next[1:0]$1344 + end + sync always + update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$1343 + end + attribute \src "libresoc.v:44593.3-44613.6" + process $proc$libresoc.v:44593$1346 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_reg$next[63:0]$1347 $3\jtag_wb_datasr_reg$next[63:0]$1350 + attribute \src "libresoc.v:44594.5-44594.29" + switch \initial + attribute \src "libresoc.v:44594.9-44594.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" + switch \jtag_wb_datasr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_reg$next[63:0]$1348 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } + case + assign $1\jtag_wb_datasr_reg$next[63:0]$1348 \jtag_wb_datasr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" + switch \jtag_wb_datasr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr_reg$next[63:0]$1349 \jtag_wb_datasr__i + case + assign $2\jtag_wb_datasr_reg$next[63:0]$1349 $1\jtag_wb_datasr_reg$next[63:0]$1348 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_datasr_reg$next[63:0]$1350 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb_datasr_reg$next[63:0]$1350 $2\jtag_wb_datasr_reg$next[63:0]$1349 + end + sync always + update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$1347 + end + attribute \src "libresoc.v:44614.3-44622.6" + process $proc$libresoc.v:44614$1351 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_update_core$next[0:0]$1352 $1\dmi0_addrsr_update_core$next[0:0]$1353 + attribute \src "libresoc.v:44615.5-44615.29" + switch \initial + attribute \src "libresoc.v:44615.9-44615.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_update_core$next[0:0]$1353 1'0 + case + assign $1\dmi0_addrsr_update_core$next[0:0]$1353 \dmi0_addrsr_update + end + sync always + update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$1352 + end + attribute \src "libresoc.v:44623.3-44631.6" + process $proc$libresoc.v:44623$1354 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_update_core_prev$next[0:0]$1355 $1\dmi0_addrsr_update_core_prev$next[0:0]$1356 + attribute \src "libresoc.v:44624.5-44624.29" + switch \initial + attribute \src "libresoc.v:44624.9-44624.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$1356 1'0 + case + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$1356 \dmi0_addrsr_update_core + end + sync always + update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$1355 + end + attribute \src "libresoc.v:44632.3-44648.6" + process $proc$libresoc.v:44632$1357 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr__oe$next[0:0]$1358 $2\dmi0_addrsr__oe$next[0:0]$1360 + attribute \src "libresoc.v:44633.5-44633.29" + switch \initial + attribute \src "libresoc.v:44633.9-44633.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + switch \$233 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr__oe$next[0:0]$1359 \dmi0_addrsr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi0_addrsr__oe$next[0:0]$1359 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_addrsr__oe$next[0:0]$1360 1'0 + case + assign $2\dmi0_addrsr__oe$next[0:0]$1360 $1\dmi0_addrsr__oe$next[0:0]$1359 + end + sync always + update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$1358 + end + attribute \src "libresoc.v:44649.3-44669.6" + process $proc$libresoc.v:44649$1361 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_reg$next[7:0]$1362 $3\dmi0_addrsr_reg$next[7:0]$1365 + attribute \src "libresoc.v:44650.5-44650.29" + switch \initial + attribute \src "libresoc.v:44650.9-44650.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" + switch \dmi0_addrsr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_reg$next[7:0]$1363 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } + case + assign $1\dmi0_addrsr_reg$next[7:0]$1363 \dmi0_addrsr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" + switch \dmi0_addrsr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_addrsr_reg$next[7:0]$1364 \dmi0_addrsr__i + case + assign $2\dmi0_addrsr_reg$next[7:0]$1364 $1\dmi0_addrsr_reg$next[7:0]$1363 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_addrsr_reg$next[7:0]$1365 8'00000000 + case + assign $3\dmi0_addrsr_reg$next[7:0]$1365 $2\dmi0_addrsr_reg$next[7:0]$1364 + end + sync always + update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$1362 + end + attribute \src "libresoc.v:44670.3-44678.6" + process $proc$libresoc.v:44670$1366 + assign { } { } + assign { } { } + assign $0\dmi0_datasr_update_core$next[0:0]$1367 $1\dmi0_datasr_update_core$next[0:0]$1368 + attribute \src "libresoc.v:44671.5-44671.29" + switch \initial + attribute \src "libresoc.v:44671.9-44671.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_update_core$next[0:0]$1368 1'0 + case + assign $1\dmi0_datasr_update_core$next[0:0]$1368 \dmi0_datasr_update + end + sync always + update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$1367 + end + connect \$9 $eq$libresoc.v:43764$1064_Y + connect \$99 $ternary$libresoc.v:43765$1065_Y + connect \$101 $ternary$libresoc.v:43766$1066_Y + connect \$103 $ternary$libresoc.v:43767$1067_Y + connect \$105 $ternary$libresoc.v:43768$1068_Y + connect \$107 $ternary$libresoc.v:43769$1069_Y + connect \$109 $ternary$libresoc.v:43770$1070_Y + connect \$111 $ternary$libresoc.v:43771$1071_Y + connect \$113 $ternary$libresoc.v:43772$1072_Y + connect \$115 $ternary$libresoc.v:43773$1073_Y + connect \$117 $ternary$libresoc.v:43774$1074_Y + connect \$11 $eq$libresoc.v:43775$1075_Y + connect \$119 $ternary$libresoc.v:43776$1076_Y + connect \$121 $ternary$libresoc.v:43777$1077_Y + connect \$123 $ternary$libresoc.v:43778$1078_Y + connect \$125 $ternary$libresoc.v:43779$1079_Y + connect \$127 $ternary$libresoc.v:43780$1080_Y + connect \$129 $ternary$libresoc.v:43781$1081_Y + connect \$131 $ternary$libresoc.v:43782$1082_Y + connect \$133 $ternary$libresoc.v:43783$1083_Y + connect \$135 $ternary$libresoc.v:43784$1084_Y + connect \$137 $ternary$libresoc.v:43785$1085_Y + connect \$13 $or$libresoc.v:43786$1086_Y + connect \$139 $ternary$libresoc.v:43787$1087_Y + connect \$141 $eq$libresoc.v:43788$1088_Y + connect \$143 $eq$libresoc.v:43789$1089_Y + connect \$145 $or$libresoc.v:43790$1090_Y + connect \$147 $and$libresoc.v:43791$1091_Y + connect \$149 $eq$libresoc.v:43792$1092_Y + connect \$151 $eq$libresoc.v:43793$1093_Y + connect \$153 $or$libresoc.v:43794$1094_Y + connect \$155 $eq$libresoc.v:43795$1095_Y + connect \$157 $or$libresoc.v:43796$1096_Y + connect \$15 $eq$libresoc.v:43797$1097_Y + connect \$159 $and$libresoc.v:43798$1098_Y + connect \$161 $eq$libresoc.v:43799$1099_Y + connect \$163 $ne$libresoc.v:43800$1100_Y + connect \$165 $and$libresoc.v:43801$1101_Y + connect \$167 $ne$libresoc.v:43802$1102_Y + connect \$169 $and$libresoc.v:43803$1103_Y + connect \$171 $ne$libresoc.v:43804$1104_Y + connect \$173 $and$libresoc.v:43805$1105_Y + connect \$175 $not$libresoc.v:43806$1106_Y + connect \$177 $and$libresoc.v:43807$1107_Y + connect \$17 $or$libresoc.v:43808$1108_Y + connect \$179 $eq$libresoc.v:43809$1109_Y + connect \$181 $ne$libresoc.v:43810$1110_Y + connect \$183 $and$libresoc.v:43811$1111_Y + connect \$185 $ne$libresoc.v:43812$1112_Y + connect \$187 $and$libresoc.v:43813$1113_Y + connect \$189 $ne$libresoc.v:43814$1114_Y + connect \$191 $and$libresoc.v:43815$1115_Y + connect \$193 $not$libresoc.v:43816$1116_Y + connect \$195 $and$libresoc.v:43817$1117_Y + connect \$197 $eq$libresoc.v:43818$1118_Y + connect \$1 $eq$libresoc.v:43819$1119_Y + connect \$19 $and$libresoc.v:43820$1120_Y + connect \$199 $eq$libresoc.v:43821$1121_Y + connect \$201 $ne$libresoc.v:43822$1122_Y + connect \$203 $and$libresoc.v:43823$1123_Y + connect \$205 $ne$libresoc.v:43824$1124_Y + connect \$207 $and$libresoc.v:43825$1125_Y + connect \$209 $ne$libresoc.v:43826$1126_Y + connect \$211 $and$libresoc.v:43827$1127_Y + connect \$213 $not$libresoc.v:43828$1128_Y + connect \$215 $and$libresoc.v:43829$1129_Y + connect \$217 $eq$libresoc.v:43830$1130_Y + connect \$21 $and$libresoc.v:43831$1131_Y + connect \$219 $ne$libresoc.v:43832$1132_Y + connect \$221 $and$libresoc.v:43833$1133_Y + connect \$223 $ne$libresoc.v:43834$1134_Y + connect \$225 $and$libresoc.v:43835$1135_Y + connect \$227 $ne$libresoc.v:43836$1136_Y + connect \$229 $and$libresoc.v:43837$1137_Y + connect \$231 $not$libresoc.v:43838$1138_Y + connect \$233 $and$libresoc.v:43839$1139_Y + connect \$235 $eq$libresoc.v:43840$1140_Y + connect \$237 $eq$libresoc.v:43841$1141_Y + connect \$23 $eq$libresoc.v:43842$1142_Y + connect \$239 $ne$libresoc.v:43843$1143_Y + connect \$241 $and$libresoc.v:43844$1144_Y + connect \$243 $ne$libresoc.v:43845$1145_Y + connect \$245 $and$libresoc.v:43846$1146_Y + connect \$247 $ne$libresoc.v:43847$1147_Y + connect \$249 $and$libresoc.v:43848$1148_Y + connect \$251 $not$libresoc.v:43849$1149_Y + connect \$253 $and$libresoc.v:43850$1150_Y + connect \$256 $eq$libresoc.v:43851$1151_Y + connect \$255 $not$libresoc.v:43852$1152_Y + connect \$25 $eq$libresoc.v:43853$1153_Y + connect \$259 $eq$libresoc.v:43854$1154_Y + connect \$261 $eq$libresoc.v:43855$1155_Y + connect \$263 $or$libresoc.v:43856$1156_Y + connect \$265 $eq$libresoc.v:43857$1157_Y + connect \$268 $add$libresoc.v:43858$1158_Y + connect \$271 $add$libresoc.v:43859$1159_Y + connect \$273 $pos$libresoc.v:43860$1161_Y + connect \$276 $eq$libresoc.v:43861$1162_Y + connect \$278 $eq$libresoc.v:43862$1163_Y + connect \$27 $or$libresoc.v:43863$1164_Y + connect \$280 $or$libresoc.v:43864$1165_Y + connect \$282 $eq$libresoc.v:43865$1166_Y + connect \$285 $add$libresoc.v:43866$1167_Y + connect \$288 $add$libresoc.v:43867$1168_Y + connect \$29 $eq$libresoc.v:43868$1169_Y + connect \$31 $or$libresoc.v:43869$1170_Y + connect \$33 $and$libresoc.v:43870$1171_Y + connect \$35 $and$libresoc.v:43871$1172_Y + connect \$37 $eq$libresoc.v:43872$1173_Y + connect \$3 $eq$libresoc.v:43873$1174_Y + connect \$39 $eq$libresoc.v:43874$1175_Y + connect \$41 $ternary$libresoc.v:43875$1176_Y + connect \$43 $ternary$libresoc.v:43876$1177_Y + connect \$45 $ternary$libresoc.v:43877$1178_Y + connect \$47 $ternary$libresoc.v:43878$1179_Y + connect \$49 $ternary$libresoc.v:43879$1180_Y + connect \$51 $ternary$libresoc.v:43880$1181_Y + connect \$53 $ternary$libresoc.v:43881$1182_Y + connect \$55 $ternary$libresoc.v:43882$1183_Y + connect \$57 $ternary$libresoc.v:43883$1184_Y + connect \$5 $or$libresoc.v:43884$1185_Y + connect \$59 $ternary$libresoc.v:43885$1186_Y + connect \$61 $ternary$libresoc.v:43886$1187_Y + connect \$63 $ternary$libresoc.v:43887$1188_Y + connect \$65 $ternary$libresoc.v:43888$1189_Y + connect \$67 $ternary$libresoc.v:43889$1190_Y + connect \$69 $ternary$libresoc.v:43890$1191_Y + connect \$71 $ternary$libresoc.v:43891$1192_Y + connect \$73 $ternary$libresoc.v:43892$1193_Y + connect \$75 $ternary$libresoc.v:43893$1194_Y + connect \$77 $ternary$libresoc.v:43894$1195_Y + connect \$7 $and$libresoc.v:43895$1196_Y + connect \$79 $ternary$libresoc.v:43896$1197_Y + connect \$81 $ternary$libresoc.v:43897$1198_Y + connect \$83 $ternary$libresoc.v:43898$1199_Y + connect \$85 $ternary$libresoc.v:43899$1200_Y + connect \$87 $ternary$libresoc.v:43900$1201_Y + connect \$89 $ternary$libresoc.v:43901$1202_Y + connect \$91 $ternary$libresoc.v:43902$1203_Y + connect \$93 $ternary$libresoc.v:43903$1204_Y + connect \$95 $ternary$libresoc.v:43904$1205_Y + connect \$97 $ternary$libresoc.v:43905$1206_Y + connect \$267 \$268 + connect \$270 \$271 + connect \$284 \$285 + connect \$287 \$288 + connect \sr0__i \sr0__o + connect \dmi0_we_i \$282 + connect \dmi0_req_i \$280 + connect \dmi0_addrsr__i \$273 + connect \jtag_wb__we \$265 + connect \jtag_wb__stb \$263 + connect \jtag_wb__cyc \$255 + connect \jtag_wb__sel 1'1 + connect \jtag_wb_addrsr__i \jtag_wb__adr + connect \dmi0_datasr_update \$249 + connect \dmi0_datasr_shift \$245 + connect \dmi0_datasr_capture \$241 + connect \dmi0_datasr_isir { \$237 \$235 } + connect \dmi0_datasr__o \dmi0_datasr_reg + connect \dmi0_addrsr_update \$229 + connect \dmi0_addrsr_shift \$225 + connect \dmi0_addrsr_capture \$221 + connect \dmi0_addrsr_isir \$217 + connect \dmi0_addrsr__o \dmi0_addrsr_reg + connect \jtag_wb_datasr_update \$211 + connect \jtag_wb_datasr_shift \$207 + connect \jtag_wb_datasr_capture \$203 + connect \jtag_wb_datasr_isir { \$199 \$197 } + connect \jtag_wb_datasr__o \jtag_wb_datasr_reg + connect \jtag_wb_addrsr_update \$191 + connect \jtag_wb_addrsr_shift \$187 + connect \jtag_wb_addrsr_capture \$183 + connect \jtag_wb_addrsr_isir \$179 + connect \jtag_wb_addrsr__o \jtag_wb_addrsr_reg + connect \sr0_update \$173 + connect \sr0_shift \$169 + connect \sr0_capture \$165 + connect \sr0_isir \$161 + connect \sr0__o \sr0_reg + connect \gpio_gpio15__pad__oe \$139 + connect \gpio_gpio15__pad__o \$137 + connect \gpio_gpio15__core__i \$135 + connect \gpio_gpio14__pad__oe \$133 + connect \gpio_gpio14__pad__o \$131 + connect \gpio_gpio14__core__i \$129 + connect \gpio_gpio13__pad__oe \$127 + connect \gpio_gpio13__pad__o \$125 + connect \gpio_gpio13__core__i \$123 + connect \gpio_gpio12__pad__oe \$121 + connect \gpio_gpio12__pad__o \$119 + connect \gpio_gpio12__core__i \$117 + connect \gpio_gpio11__pad__oe \$115 + connect \gpio_gpio11__pad__o \$113 + connect \gpio_gpio11__core__i \$111 + connect \gpio_gpio10__pad__oe \$109 + connect \gpio_gpio10__pad__o \$107 + connect \gpio_gpio10__core__i \$105 + connect \gpio_gpio9__pad__oe \$103 + connect \gpio_gpio9__pad__o \$101 + connect \gpio_gpio9__core__i \$99 + connect \gpio_gpio8__pad__oe \$97 + connect \gpio_gpio8__pad__o \$95 + connect \gpio_gpio8__core__i \$93 + connect \gpio_gpio7__pad__oe \$91 + connect \gpio_gpio7__pad__o \$89 + connect \gpio_gpio7__core__i \$87 + connect \gpio_gpio6__pad__oe \$85 + connect \gpio_gpio6__pad__o \$83 + connect \gpio_gpio6__core__i \$81 + connect \gpio_gpio5__pad__oe \$79 + connect \gpio_gpio5__pad__o \$77 + connect \gpio_gpio5__core__i \$75 + connect \gpio_gpio4__pad__oe \$73 + connect \gpio_gpio4__pad__o \$71 + connect \gpio_gpio4__core__i \$69 + connect \gpio_gpio3__pad__oe \$67 + connect \gpio_gpio3__pad__o \$65 + connect \gpio_gpio3__core__i \$63 + connect \gpio_gpio2__pad__oe \$61 + connect \gpio_gpio2__pad__o \$59 + connect \gpio_gpio2__core__i \$57 + connect \gpio_gpio1__pad__oe \$55 + connect \gpio_gpio1__pad__o \$53 + connect \gpio_gpio1__core__i \$51 + connect \gpio_gpio0__pad__oe \$49 + connect \gpio_gpio0__pad__o \$47 + connect \gpio_gpio0__core__i \$45 + connect \uart_rx__core__i \$43 + connect \uart_tx__pad__o \$41 + connect \io_bd2core \$39 + connect \io_bd2io \$37 + connect \io_update \$35 + connect \io_shift \$21 + connect \io_capture \$7 +end +attribute \src "ls180.v:4.1-10347.10" +attribute \cells_not_processed 1 +module \ls180 + attribute \src "ls180.v:10040.1-10050.4" + wire width 7 $0$memwr$\mem$ls180.v:10042$1_ADDR[6:0]$2693 + attribute \src "ls180.v:10040.1-10050.4" + wire width 32 $0$memwr$\mem$ls180.v:10042$1_DATA[31:0]$2694 + attribute \src "ls180.v:10040.1-10050.4" + wire width 32 $0$memwr$\mem$ls180.v:10042$1_EN[31:0]$2695 + attribute \src "ls180.v:10040.1-10050.4" + wire width 7 $0$memwr$\mem$ls180.v:10044$2_ADDR[6:0]$2696 + attribute \src "ls180.v:10040.1-10050.4" + wire width 32 $0$memwr$\mem$ls180.v:10044$2_DATA[31:0]$2697 + attribute \src "ls180.v:10040.1-10050.4" + wire width 32 $0$memwr$\mem$ls180.v:10044$2_EN[31:0]$2698 + attribute \src "ls180.v:10040.1-10050.4" + wire width 7 $0$memwr$\mem$ls180.v:10046$3_ADDR[6:0]$2699 + attribute \src "ls180.v:10040.1-10050.4" + wire width 32 $0$memwr$\mem$ls180.v:10046$3_DATA[31:0]$2700 + attribute \src "ls180.v:10040.1-10050.4" + wire width 32 $0$memwr$\mem$ls180.v:10046$3_EN[31:0]$2701 + attribute \src "ls180.v:10040.1-10050.4" + wire width 7 $0$memwr$\mem$ls180.v:10048$4_ADDR[6:0]$2702 + attribute \src "ls180.v:10040.1-10050.4" + wire width 32 $0$memwr$\mem$ls180.v:10048$4_DATA[31:0]$2703 + attribute \src "ls180.v:10040.1-10050.4" + wire width 32 $0$memwr$\mem$ls180.v:10048$4_EN[31:0]$2704 + attribute \src "ls180.v:10060.1-10064.4" + wire width 3 $0$memwr$\storage$ls180.v:10062$5_ADDR[2:0]$2707 + attribute \src "ls180.v:10060.1-10064.4" + wire width 25 $0$memwr$\storage$ls180.v:10062$5_DATA[24:0]$2708 + attribute \src "ls180.v:10060.1-10064.4" + wire width 25 $0$memwr$\storage$ls180.v:10062$5_EN[24:0]$2709 + attribute \src "ls180.v:10074.1-10078.4" + wire width 3 $0$memwr$\storage_1$ls180.v:10076$6_ADDR[2:0]$2714 + attribute \src "ls180.v:10074.1-10078.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10076$6_DATA[24:0]$2715 + attribute \src "ls180.v:10074.1-10078.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10076$6_EN[24:0]$2716 + attribute \src "ls180.v:10088.1-10092.4" + wire width 3 $0$memwr$\storage_2$ls180.v:10090$7_ADDR[2:0]$2721 + attribute \src "ls180.v:10088.1-10092.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10090$7_DATA[24:0]$2722 + attribute \src "ls180.v:10088.1-10092.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10090$7_EN[24:0]$2723 + attribute \src "ls180.v:10102.1-10106.4" + wire width 3 $0$memwr$\storage_3$ls180.v:10104$8_ADDR[2:0]$2728 + attribute \src "ls180.v:10102.1-10106.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10104$8_DATA[24:0]$2729 + attribute \src "ls180.v:10102.1-10106.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10104$8_EN[24:0]$2730 + attribute \src "ls180.v:10117.1-10121.4" + wire width 4 $0$memwr$\storage_4$ls180.v:10119$9_ADDR[3:0]$2735 + attribute \src "ls180.v:10117.1-10121.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10119$9_DATA[9:0]$2736 + attribute \src "ls180.v:10117.1-10121.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10119$9_EN[9:0]$2737 + attribute \src "ls180.v:10134.1-10138.4" + wire width 4 $0$memwr$\storage_5$ls180.v:10136$10_ADDR[3:0]$2742 + attribute \src "ls180.v:10134.1-10138.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10136$10_DATA[9:0]$2743 + attribute \src "ls180.v:10134.1-10138.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10136$10_EN[9:0]$2744 + attribute \src "ls180.v:10150.1-10154.4" + wire width 5 $0$memwr$\storage_6$ls180.v:10152$11_ADDR[4:0]$2749 + attribute \src "ls180.v:10150.1-10154.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10152$11_DATA[9:0]$2750 + attribute \src "ls180.v:10150.1-10154.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10152$11_EN[9:0]$2751 + attribute \src "ls180.v:10164.1-10168.4" + wire width 5 $0$memwr$\storage_7$ls180.v:10166$12_ADDR[4:0]$2756 + attribute \src "ls180.v:10164.1-10168.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10166$12_DATA[9:0]$2757 + attribute \src "ls180.v:10164.1-10168.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10166$12_EN[9:0]$2758 + attribute \src "ls180.v:3206.1-3299.4" + wire width 3 $0\builder_bankmachine0_next_state[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\builder_bankmachine0_state[2:0] + attribute \src "ls180.v:3363.1-3456.4" + wire width 3 $0\builder_bankmachine1_next_state[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\builder_bankmachine1_state[2:0] + attribute \src "ls180.v:3520.1-3613.4" + wire width 3 $0\builder_bankmachine2_next_state[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\builder_bankmachine2_state[2:0] + attribute \src "ls180.v:3677.1-3770.4" + wire width 3 $0\builder_bankmachine3_next_state[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\builder_bankmachine3_state[2:0] + attribute \src "ls180.v:6500.1-6516.4" + wire $0\builder_comb_rhs_array_muxed0[0:0] + attribute \src "ls180.v:6721.1-6737.4" + wire $0\builder_comb_rhs_array_muxed10[0:0] + attribute \src "ls180.v:6738.1-6754.4" + wire $0\builder_comb_rhs_array_muxed11[0:0] + attribute \src "ls180.v:6806.1-6813.4" + wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] + attribute \src "ls180.v:6814.1-6821.4" + wire $0\builder_comb_rhs_array_muxed13[0:0] + attribute \src "ls180.v:6822.1-6829.4" + wire $0\builder_comb_rhs_array_muxed14[0:0] + attribute \src "ls180.v:6830.1-6837.4" + wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] + attribute \src "ls180.v:6838.1-6845.4" + wire $0\builder_comb_rhs_array_muxed16[0:0] + attribute \src "ls180.v:6846.1-6853.4" + wire $0\builder_comb_rhs_array_muxed17[0:0] + attribute \src "ls180.v:6854.1-6861.4" + wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] + attribute \src "ls180.v:6862.1-6869.4" + wire $0\builder_comb_rhs_array_muxed19[0:0] + attribute \src "ls180.v:6517.1-6533.4" + wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] + attribute \src "ls180.v:6870.1-6877.4" + wire $0\builder_comb_rhs_array_muxed20[0:0] + attribute \src "ls180.v:6878.1-6885.4" + wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] + attribute \src "ls180.v:6886.1-6893.4" + wire $0\builder_comb_rhs_array_muxed22[0:0] + attribute \src "ls180.v:6894.1-6901.4" + wire $0\builder_comb_rhs_array_muxed23[0:0] + attribute \src "ls180.v:6902.1-6921.4" + wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] + attribute \src "ls180.v:6922.1-6941.4" + wire width 32 $0\builder_comb_rhs_array_muxed25[31:0] + attribute \src "ls180.v:6942.1-6961.4" + wire width 4 $0\builder_comb_rhs_array_muxed26[3:0] + attribute \src "ls180.v:6962.1-6981.4" + wire $0\builder_comb_rhs_array_muxed27[0:0] + attribute \src "ls180.v:6982.1-7001.4" + wire $0\builder_comb_rhs_array_muxed28[0:0] + attribute \src "ls180.v:7002.1-7021.4" + wire $0\builder_comb_rhs_array_muxed29[0:0] + attribute \src "ls180.v:6534.1-6550.4" + wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] + attribute \src "ls180.v:7022.1-7041.4" + wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] + attribute \src "ls180.v:7042.1-7061.4" + wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] + attribute \src "ls180.v:6551.1-6567.4" + wire $0\builder_comb_rhs_array_muxed3[0:0] + attribute \src "ls180.v:6568.1-6584.4" + wire $0\builder_comb_rhs_array_muxed4[0:0] + attribute \src "ls180.v:6585.1-6601.4" + wire $0\builder_comb_rhs_array_muxed5[0:0] + attribute \src "ls180.v:6653.1-6669.4" + wire $0\builder_comb_rhs_array_muxed6[0:0] + attribute \src "ls180.v:6670.1-6686.4" + wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] + attribute \src "ls180.v:6687.1-6703.4" + wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] + attribute \src "ls180.v:6704.1-6720.4" + wire $0\builder_comb_rhs_array_muxed9[0:0] + attribute \src "ls180.v:6602.1-6618.4" + wire $0\builder_comb_t_array_muxed0[0:0] + attribute \src "ls180.v:6619.1-6635.4" + wire $0\builder_comb_t_array_muxed1[0:0] + attribute \src "ls180.v:6636.1-6652.4" + wire $0\builder_comb_t_array_muxed2[0:0] + attribute \src "ls180.v:6755.1-6771.4" + wire $0\builder_comb_t_array_muxed3[0:0] + attribute \src "ls180.v:6772.1-6788.4" + wire $0\builder_comb_t_array_muxed4[0:0] + attribute \src "ls180.v:6789.1-6805.4" + wire $0\builder_comb_t_array_muxed5[0:0] + attribute \src "ls180.v:2770.1-2816.4" + wire $0\builder_converter0_next_state[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_converter0_state[0:0] + attribute \src "ls180.v:2830.1-2876.4" + wire $0\builder_converter1_next_state[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_converter1_state[0:0] + attribute \src "ls180.v:2890.1-2936.4" + wire $0\builder_converter2_next_state[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_converter2_state[0:0] + attribute \src "ls180.v:4023.1-4069.4" + wire $0\builder_converter_next_state[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_converter_state[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 20 $0\builder_count[19:0] + attribute \src "ls180.v:5740.1-5751.4" + wire $0\builder_error[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\builder_grant[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 14 $0\builder_libresocsim_adr[13:0] + attribute \src "ls180.v:5629.1-5665.4" + wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] + attribute \src "ls180.v:5629.1-5665.4" + wire $0\builder_libresocsim_adr_next_value_ce1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\builder_libresocsim_dat_w[7:0] + attribute \src "ls180.v:5629.1-5665.4" + wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] + attribute \src "ls180.v:5629.1-5665.4" + wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_libresocsim_we[0:0] + attribute \src "ls180.v:5629.1-5665.4" + wire $0\builder_libresocsim_we_next_value2[0:0] + attribute \src "ls180.v:5629.1-5665.4" + wire $0\builder_libresocsim_we_next_value_ce2[0:0] + attribute \src "ls180.v:5629.1-5665.4" + wire $0\builder_libresocsim_wishbone_ack[0:0] + attribute \src "ls180.v:5629.1-5665.4" + wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] + attribute \src "ls180.v:1857.5-1857.44" + wire $0\builder_libresocsim_wishbone_err[0:0] + attribute \src "ls180.v:1746.5-1746.27" + wire $0\builder_locked0[0:0] + attribute \src "ls180.v:1747.5-1747.27" + wire $0\builder_locked1[0:0] + attribute \src "ls180.v:1748.5-1748.27" + wire $0\builder_locked2[0:0] + attribute \src "ls180.v:1749.5-1749.27" + wire $0\builder_locked3[0:0] + attribute \src "ls180.v:3895.1-3967.4" + wire width 3 $0\builder_multiplexer_next_state[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\builder_multiplexer_state[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl0_regs0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl0_regs1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl10_regs0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl10_regs1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl11_regs0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl11_regs1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl12_regs0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl12_regs1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl13_regs0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl13_regs1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl14_regs0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl14_regs1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl15_regs0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl15_regs1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl16_regs0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl16_regs1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl1_regs0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl1_regs1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl2_regs0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl2_regs1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl3_regs0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl3_regs1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl4_regs0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl4_regs1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl5_regs0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl5_regs1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl6_regs0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl6_regs1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl7_regs0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl7_regs1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl8_regs0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl8_regs1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl9_regs0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_multiregimpl9_regs1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_new_master_rdata_valid0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_new_master_rdata_valid1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_new_master_rdata_valid2[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_new_master_rdata_valid3[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_new_master_wdata_ready[0:0] + attribute \src "ls180.v:5629.1-5665.4" + wire width 2 $0\builder_next_state[1:0] + attribute \src "ls180.v:3112.1-3142.4" + wire width 2 $0\builder_refresher_next_state[1:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 2 $0\builder_refresher_state[1:0] + attribute \src "ls180.v:5380.1-5419.4" + wire width 2 $0\builder_sdblock2memdma_next_state[1:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 2 $0\builder_sdblock2memdma_state[1:0] + attribute \src "ls180.v:4947.1-5026.4" + wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_sdcore_crcupstreaminserter_state[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire width 3 $0\builder_sdcore_fsm_next_state[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\builder_sdcore_fsm_state[2:0] + attribute \src "ls180.v:5439.1-5476.4" + wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_sdmem2blockdma_fsm_state[0:0] + attribute \src "ls180.v:5477.1-5513.4" + wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] + attribute \src "ls180.v:4622.1-4694.4" + wire width 3 $0\builder_sdphy_fsm_next_state[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\builder_sdphy_fsm_state[2:0] + attribute \src "ls180.v:4467.1-4560.4" + wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] + attribute \src "ls180.v:4357.1-4433.4" + wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] + attribute \src "ls180.v:4594.1-4621.4" + wire $0\builder_sdphy_sdphycrcr_next_state[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_sdphy_sdphycrcr_state[0:0] + attribute \src "ls180.v:4728.1-4829.4" + wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] + attribute \src "ls180.v:4323.1-4356.4" + wire $0\builder_sdphy_sdphyinit_next_state[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\builder_sdphy_sdphyinit_state[0:0] + attribute \src "ls180.v:5740.1-5751.4" + wire $0\builder_shared_ack[0:0] + attribute \src "ls180.v:5740.1-5751.4" + wire width 32 $0\builder_shared_dat_r[31:0] + attribute \src "ls180.v:5690.1-5697.4" + wire width 5 $0\builder_slave_sel[4:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 5 $0\builder_slave_sel_r[4:0] + attribute \src "ls180.v:4213.1-4261.4" + wire width 2 $0\builder_spimaster0_next_state[1:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 2 $0\builder_spimaster0_state[1:0] + attribute \src "ls180.v:5580.1-5628.4" + wire width 2 $0\builder_spimaster1_next_state[1:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 2 $0\builder_spimaster1_state[1:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 2 $0\builder_state[1:0] + attribute \src "ls180.v:7181.1-7209.4" + wire $0\builder_sync_f_array_muxed0[0:0] + attribute \src "ls180.v:7210.1-7238.4" + wire $0\builder_sync_f_array_muxed1[0:0] + attribute \src "ls180.v:7062.1-7078.4" + wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] + attribute \src "ls180.v:7079.1-7095.4" + wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] + attribute \src "ls180.v:7096.1-7112.4" + wire $0\builder_sync_rhs_array_muxed2[0:0] + attribute \src "ls180.v:7113.1-7129.4" + wire $0\builder_sync_rhs_array_muxed3[0:0] + attribute \src "ls180.v:7130.1-7146.4" + wire $0\builder_sync_rhs_array_muxed4[0:0] + attribute \src "ls180.v:7147.1-7163.4" + wire $0\builder_sync_rhs_array_muxed5[0:0] + attribute \src "ls180.v:7164.1-7180.4" + wire $0\builder_sync_rhs_array_muxed6[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\libresocsim_clk_divider1[15:0] + attribute \src "ls180.v:5580.1-5628.4" + wire $0\libresocsim_clk_enable[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\libresocsim_control_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\libresocsim_control_storage[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\libresocsim_count[2:0] + attribute \src "ls180.v:5580.1-5628.4" + wire width 3 $0\libresocsim_count_spimaster1_next_value[2:0] + attribute \src "ls180.v:5580.1-5628.4" + wire $0\libresocsim_count_spimaster1_next_value_ce[0:0] + attribute \src "ls180.v:5580.1-5628.4" + wire $0\libresocsim_cs_enable[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\libresocsim_cs_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\libresocsim_cs_storage[0:0] + attribute \src "ls180.v:5580.1-5628.4" + wire $0\libresocsim_done0[0:0] + attribute \src "ls180.v:5580.1-5628.4" + wire $0\libresocsim_irq[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\libresocsim_loopback_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\libresocsim_loopback_storage[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\libresocsim_miso[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\libresocsim_miso_data[7:0] + attribute \src "ls180.v:5580.1-5628.4" + wire $0\libresocsim_miso_latch[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\libresocsim_mosi_data[7:0] + attribute \src "ls180.v:5580.1-5628.4" + wire $0\libresocsim_mosi_latch[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\libresocsim_mosi_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\libresocsim_mosi_sel[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\libresocsim_mosi_storage[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\libresocsim_re[0:0] + attribute \src "ls180.v:6311.1-6316.4" + wire $0\libresocsim_start1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\libresocsim_storage[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_cmd_consumed[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_converter_counter[0:0] + attribute \src "ls180.v:4023.1-4069.4" + wire $0\main_converter_counter_converter_next_value[0:0] + attribute \src "ls180.v:4023.1-4069.4" + wire $0\main_converter_counter_converter_next_value_ce[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_converter_dat_r[31:0] + attribute \src "ls180.v:4023.1-4069.4" + wire $0\main_converter_skip[0:0] + attribute \src "ls180.v:7339.1-7409.4" + wire width 16 $0\main_dfi_p0_rddata[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_dfi_p0_rddata_valid[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 36 $0\main_dummy[35:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_gpio_oe_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_gpio_oe_storage[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_gpio_out_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_gpio_out_storage[15:0] + attribute \src "ls180.v:7296.1-7314.4" + wire width 16 $0\main_gpio_status[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_i2c_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_i2c_storage[2:0] + attribute \src "ls180.v:7335.1-7337.4" + wire $0\main_int_rst[0:0] + attribute \src "ls180.v:1496.11-1496.41" + wire width 2 $0\main_interface0_bus_bte[1:0] + attribute \src "ls180.v:1495.11-1495.41" + wire width 3 $0\main_interface0_bus_cti[2:0] + attribute \src "ls180.v:5439.1-5476.4" + wire width 32 $0\main_interface1_bus_adr[31:0] + attribute \src "ls180.v:1587.11-1587.41" + wire width 2 $0\main_interface1_bus_bte[1:0] + attribute \src "ls180.v:1586.11-1586.41" + wire width 3 $0\main_interface1_bus_cti[2:0] + attribute \src "ls180.v:5439.1-5476.4" + wire $0\main_interface1_bus_cyc[0:0] + attribute \src "ls180.v:1579.12-1579.45" + wire width 32 $0\main_interface1_bus_dat_w[31:0] + attribute \src "ls180.v:5439.1-5476.4" + wire width 4 $0\main_interface1_bus_sel[3:0] + attribute \src "ls180.v:5439.1-5476.4" + wire $0\main_interface1_bus_stb[0:0] + attribute \src "ls180.v:5439.1-5476.4" + wire $0\main_interface1_bus_we[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_libresocsim_bus_errors[31:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_libresocsim_converter0_counter[0:0] + attribute \src "ls180.v:2770.1-2816.4" + wire $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:2770.1-2816.4" + wire $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 64 $0\main_libresocsim_converter0_dat_r[63:0] + attribute \src "ls180.v:2770.1-2816.4" + wire $0\main_libresocsim_converter0_skip[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_libresocsim_converter1_counter[0:0] + attribute \src "ls180.v:2830.1-2876.4" + wire $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:2830.1-2876.4" + wire $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 64 $0\main_libresocsim_converter1_dat_r[63:0] + attribute \src "ls180.v:2830.1-2876.4" + wire $0\main_libresocsim_converter1_skip[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_libresocsim_converter2_counter[0:0] + attribute \src "ls180.v:2890.1-2936.4" + wire $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] + attribute \src "ls180.v:2890.1-2936.4" + wire $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 64 $0\main_libresocsim_converter2_dat_r[63:0] + attribute \src "ls180.v:2890.1-2936.4" + wire $0\main_libresocsim_converter2_skip[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_libresocsim_en_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_libresocsim_en_storage[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_libresocsim_eventmanager_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_libresocsim_eventmanager_storage[0:0] + attribute \src "ls180.v:2770.1-2816.4" + wire width 30 $0\main_libresocsim_interface0_converted_interface_adr[29:0] + attribute \src "ls180.v:147.11-147.69" + wire width 2 $0\main_libresocsim_interface0_converted_interface_bte[1:0] + attribute \src "ls180.v:146.11-146.69" + wire width 3 $0\main_libresocsim_interface0_converted_interface_cti[2:0] + attribute \src "ls180.v:2770.1-2816.4" + wire $0\main_libresocsim_interface0_converted_interface_cyc[0:0] + attribute \src "ls180.v:2758.1-2768.4" + wire width 32 $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] + attribute \src "ls180.v:2770.1-2816.4" + wire width 4 $0\main_libresocsim_interface0_converted_interface_sel[3:0] + attribute \src "ls180.v:2770.1-2816.4" + wire $0\main_libresocsim_interface0_converted_interface_stb[0:0] + attribute \src "ls180.v:2770.1-2816.4" + wire $0\main_libresocsim_interface0_converted_interface_we[0:0] + attribute \src "ls180.v:2830.1-2876.4" + wire width 30 $0\main_libresocsim_interface1_converted_interface_adr[29:0] + attribute \src "ls180.v:162.11-162.69" + wire width 2 $0\main_libresocsim_interface1_converted_interface_bte[1:0] + attribute \src "ls180.v:161.11-161.69" + wire width 3 $0\main_libresocsim_interface1_converted_interface_cti[2:0] + attribute \src "ls180.v:2830.1-2876.4" + wire $0\main_libresocsim_interface1_converted_interface_cyc[0:0] + attribute \src "ls180.v:2818.1-2828.4" + wire width 32 $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] + attribute \src "ls180.v:2830.1-2876.4" + wire width 4 $0\main_libresocsim_interface1_converted_interface_sel[3:0] + attribute \src "ls180.v:2830.1-2876.4" + wire $0\main_libresocsim_interface1_converted_interface_stb[0:0] + attribute \src "ls180.v:2830.1-2876.4" + wire $0\main_libresocsim_interface1_converted_interface_we[0:0] + attribute \src "ls180.v:2890.1-2936.4" + wire width 30 $0\main_libresocsim_interface2_converted_interface_adr[29:0] + attribute \src "ls180.v:177.11-177.69" + wire width 2 $0\main_libresocsim_interface2_converted_interface_bte[1:0] + attribute \src "ls180.v:176.11-176.69" + wire width 3 $0\main_libresocsim_interface2_converted_interface_cti[2:0] + attribute \src "ls180.v:2890.1-2936.4" + wire $0\main_libresocsim_interface2_converted_interface_cyc[0:0] + attribute \src "ls180.v:2878.1-2888.4" + wire width 32 $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] + attribute \src "ls180.v:2890.1-2936.4" + wire width 4 $0\main_libresocsim_interface2_converted_interface_sel[3:0] + attribute \src "ls180.v:2890.1-2936.4" + wire $0\main_libresocsim_interface2_converted_interface_stb[0:0] + attribute \src "ls180.v:2890.1-2936.4" + wire $0\main_libresocsim_interface2_converted_interface_we[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] + attribute \src "ls180.v:2830.1-2876.4" + wire $0\main_libresocsim_libresoc_dbus_ack[0:0] + attribute \src "ls180.v:76.5-76.46" + wire $0\main_libresocsim_libresoc_dbus_err[0:0] + attribute \src "ls180.v:2770.1-2816.4" + wire $0\main_libresocsim_libresoc_ibus_ack[0:0] + attribute \src "ls180.v:87.5-87.46" + wire $0\main_libresocsim_libresoc_ibus_err[0:0] + attribute \src "ls180.v:2751.1-2756.4" + wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] + attribute \src "ls180.v:2890.1-2936.4" + wire $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] + attribute \src "ls180.v:118.5-118.49" + wire $0\main_libresocsim_libresoc_jtag_wb_err[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_libresocsim_load_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_libresocsim_load_storage[31:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_libresocsim_ram_bus_ack[0:0] + attribute \src "ls180.v:193.5-193.40" + wire $0\main_libresocsim_ram_bus_err[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_libresocsim_reload_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_libresocsim_reload_storage[31:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_libresocsim_reset_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_libresocsim_reset_storage[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_libresocsim_scratch_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_libresocsim_scratch_storage[31:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_libresocsim_update_value_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_libresocsim_update_value_storage[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_libresocsim_value[31:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_libresocsim_value_status[31:0] + attribute \src "ls180.v:2939.1-2945.4" + wire width 4 $0\main_libresocsim_we[3:0] + attribute \src "ls180.v:2951.1-2956.4" + wire $0\main_libresocsim_zero_clear[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_libresocsim_zero_old_trigger[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_libresocsim_zero_pending[0:0] + attribute \src "ls180.v:4023.1-4069.4" + wire width 30 $0\main_litedram_wb_adr[29:0] + attribute \src "ls180.v:4023.1-4069.4" + wire $0\main_litedram_wb_cyc[0:0] + attribute \src "ls180.v:4011.1-4021.4" + wire width 16 $0\main_litedram_wb_dat_w[15:0] + attribute \src "ls180.v:4023.1-4069.4" + wire width 2 $0\main_litedram_wb_sel[1:0] + attribute \src "ls180.v:4023.1-4069.4" + wire $0\main_litedram_wb_stb[0:0] + attribute \src "ls180.v:4023.1-4069.4" + wire $0\main_litedram_wb_we[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_pwm0_counter[31:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_pwm0_enable_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_pwm0_enable_storage[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_pwm0_period_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_pwm0_period_storage[31:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_pwm0_width_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_pwm0_width_storage[31:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_pwm1_counter[31:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_pwm1_enable_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_pwm1_enable_storage[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_pwm1_period_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_pwm1_period_storage[31:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_pwm1_width_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_pwm1_width_storage[31:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_rddata_en[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 2 $0\main_sdblock2mem_converter_demux[1:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdblock2mem_converter_source_first[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdblock2mem_converter_source_last[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_sdblock2mem_converter_source_payload_data[31:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdblock2mem_converter_strobe_all[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 5 $0\main_sdblock2mem_fifo_consume[4:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 6 $0\main_sdblock2mem_fifo_level[5:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 5 $0\main_sdblock2mem_fifo_produce[4:0] + attribute \src "ls180.v:1520.5-1520.41" + wire $0\main_sdblock2mem_fifo_replace[0:0] + attribute \src "ls180.v:5347.1-5354.4" + wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0] + attribute \src "ls180.v:5380.1-5419.4" + wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0] + attribute \src "ls180.v:5380.1-5419.4" + wire width 32 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] + attribute \src "ls180.v:5380.1-5419.4" + wire $0\main_sdblock2mem_sink_sink_valid1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] + attribute \src "ls180.v:5380.1-5419.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + attribute \src "ls180.v:5380.1-5419.4" + wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + attribute \src "ls180.v:5380.1-5419.4" + wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + attribute \src "ls180.v:5380.1-5419.4" + wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdcore_block_count_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_sdcore_block_count_storage[31:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdcore_block_length_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 10 $0\main_sdcore_block_length_storage[9:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdcore_cmd_argument_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_sdcore_cmd_argument_storage[31:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdcore_cmd_command_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_sdcore_cmd_command_storage[31:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_sdcore_cmd_count[2:0] + attribute \src "ls180.v:5129.1-5319.4" + wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdcore_cmd_done[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdcore_cmd_error[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 128 $0\main_sdcore_cmd_response_status[127:0] + attribute \src "ls180.v:5129.1-5319.4" + wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + attribute \src "ls180.v:1329.5-1329.34" + wire $0\main_sdcore_cmd_send_w[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdcore_cmd_timeout[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0] + attribute \src "ls180.v:5035.1-5042.4" + wire $0\main_sdcore_crc16_checker_crc0_clr[0:0] + attribute \src "ls180.v:5091.1-5098.4" + wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + attribute \src "ls180.v:5045.1-5052.4" + wire $0\main_sdcore_crc16_checker_crc1_clr[0:0] + attribute \src "ls180.v:5101.1-5108.4" + wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + attribute \src "ls180.v:5055.1-5062.4" + wire $0\main_sdcore_crc16_checker_crc2_clr[0:0] + attribute \src "ls180.v:5111.1-5118.4" + wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + attribute \src "ls180.v:5065.1-5072.4" + wire $0\main_sdcore_crc16_checker_crc3_clr[0:0] + attribute \src "ls180.v:5121.1-5128.4" + wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdcore_crc16_checker_sink_first[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdcore_crc16_checker_sink_last[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0] + attribute \src "ls180.v:5080.1-5087.4" + wire $0\main_sdcore_crc16_checker_sink_ready[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdcore_crc16_checker_sink_valid[0:0] + attribute \src "ls180.v:1435.5-1435.50" + wire $0\main_sdcore_crc16_checker_source_first[0:0] + attribute \src "ls180.v:5074.1-5079.4" + wire $0\main_sdcore_crc16_checker_source_valid[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\main_sdcore_crc16_checker_val[7:0] + attribute \src "ls180.v:5027.1-5032.4" + wire $0\main_sdcore_crc16_checker_valid[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0] + attribute \src "ls180.v:4947.1-5026.4" + wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + attribute \src "ls180.v:4947.1-5026.4" + wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + attribute \src "ls180.v:4909.1-4916.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + attribute \src "ls180.v:4919.1-4926.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + attribute \src "ls180.v:4929.1-4936.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + attribute \src "ls180.v:4939.1-4946.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0] + attribute \src "ls180.v:4947.1-5026.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + attribute \src "ls180.v:4947.1-5026.4" + wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0] + attribute \src "ls180.v:4947.1-5026.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + attribute \src "ls180.v:4947.1-5026.4" + wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0] + attribute \src "ls180.v:4947.1-5026.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + attribute \src "ls180.v:4947.1-5026.4" + wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0] + attribute \src "ls180.v:4947.1-5026.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + attribute \src "ls180.v:4947.1-5026.4" + wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + attribute \src "ls180.v:4947.1-5026.4" + wire $0\main_sdcore_crc16_inserter_sink_ready[0:0] + attribute \src "ls180.v:1392.5-1392.51" + wire $0\main_sdcore_crc16_inserter_source_first[0:0] + attribute \src "ls180.v:4947.1-5026.4" + wire $0\main_sdcore_crc16_inserter_source_last[0:0] + attribute \src "ls180.v:4947.1-5026.4" + wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdcore_crc16_inserter_source_ready[0:0] + attribute \src "ls180.v:4947.1-5026.4" + wire $0\main_sdcore_crc16_inserter_source_valid[0:0] + attribute \src "ls180.v:4887.1-4894.4" + wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_sdcore_data_count[31:0] + attribute \src "ls180.v:5129.1-5319.4" + wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdcore_data_done[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdcore_data_error[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdcore_data_timeout[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 2 $0\main_sdmem2block_converter_mux[1:0] + attribute \src "ls180.v:5525.1-5541.4" + wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdmem2block_dma_base_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 64 $0\main_sdmem2block_dma_base_storage[63:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_sdmem2block_dma_data[31:0] + attribute \src "ls180.v:5439.1-5476.4" + wire width 32 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + attribute \src "ls180.v:5439.1-5476.4" + wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + attribute \src "ls180.v:5477.1-5513.4" + wire $0\main_sdmem2block_dma_done_status[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdmem2block_dma_enable_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdmem2block_dma_enable_storage[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdmem2block_dma_length_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_sdmem2block_dma_length_storage[31:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdmem2block_dma_loop_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdmem2block_dma_loop_storage[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_sdmem2block_dma_offset[31:0] + attribute \src "ls180.v:5477.1-5513.4" + wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + attribute \src "ls180.v:5477.1-5513.4" + wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + attribute \src "ls180.v:5477.1-5513.4" + wire $0\main_sdmem2block_dma_sink_last[0:0] + attribute \src "ls180.v:5477.1-5513.4" + wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0] + attribute \src "ls180.v:5439.1-5476.4" + wire $0\main_sdmem2block_dma_sink_ready[0:0] + attribute \src "ls180.v:5477.1-5513.4" + wire $0\main_sdmem2block_dma_sink_valid[0:0] + attribute \src "ls180.v:1600.5-1600.45" + wire $0\main_sdmem2block_dma_source_first[0:0] + attribute \src "ls180.v:5439.1-5476.4" + wire $0\main_sdmem2block_dma_source_last[0:0] + attribute \src "ls180.v:5439.1-5476.4" + wire width 32 $0\main_sdmem2block_dma_source_payload_data[31:0] + attribute \src "ls180.v:5439.1-5476.4" + wire $0\main_sdmem2block_dma_source_valid[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 5 $0\main_sdmem2block_fifo_consume[4:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 6 $0\main_sdmem2block_fifo_level[5:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 5 $0\main_sdmem2block_fifo_produce[4:0] + attribute \src "ls180.v:1656.5-1656.41" + wire $0\main_sdmem2block_fifo_replace[0:0] + attribute \src "ls180.v:5555.1-5562.4" + wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_clocker_clk0[0:0] + attribute \src "ls180.v:4293.1-4321.4" + wire $0\main_sdphy_clocker_clk1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_clocker_clk_d[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 9 $0\main_sdphy_clocker_clks[8:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_clocker_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 9 $0\main_sdphy_clocker_storage[8:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] + attribute \src "ls180.v:1121.5-1121.53" + wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] + attribute \src "ls180.v:1122.5-1122.52" + wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + attribute \src "ls180.v:1102.5-1102.46" + wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_cmdr_cmdr_reset[0:0] + attribute \src "ls180.v:4467.1-4560.4" + wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + attribute \src "ls180.v:4467.1-4560.4" + wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_cmdr_cmdr_run[0:0] + attribute \src "ls180.v:4467.1-4560.4" + wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\main_sdphy_cmdr_count[7:0] + attribute \src "ls180.v:4467.1-4560.4" + wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + attribute \src "ls180.v:4467.1-4560.4" + wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + attribute \src "ls180.v:1075.5-1075.49" + wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1076.5-1076.48" + wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1077.5-1077.55" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1079.5-1079.57" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1080.5-1080.58" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1082.11-1082.64" + wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1083.5-1083.59" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:4467.1-4560.4" + wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4467.1-4560.4" + wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4467.1-4560.4" + wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1088.11-1088.57" + wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1089.5-1089.52" + wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdphy_cmdr_sink_last[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0] + attribute \src "ls180.v:4467.1-4560.4" + wire $0\main_sdphy_cmdr_sink_ready[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdphy_cmdr_sink_valid[0:0] + attribute \src "ls180.v:4467.1-4560.4" + wire $0\main_sdphy_cmdr_source_last[0:0] + attribute \src "ls180.v:4467.1-4560.4" + wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0] + attribute \src "ls180.v:4467.1-4560.4" + wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdphy_cmdr_source_ready[0:0] + attribute \src "ls180.v:4467.1-4560.4" + wire $0\main_sdphy_cmdr_source_valid[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_sdphy_cmdr_timeout[31:0] + attribute \src "ls180.v:4467.1-4560.4" + wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + attribute \src "ls180.v:4467.1-4560.4" + wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\main_sdphy_cmdw_count[7:0] + attribute \src "ls180.v:4357.1-4433.4" + wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + attribute \src "ls180.v:4357.1-4433.4" + wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + attribute \src "ls180.v:4357.1-4433.4" + wire $0\main_sdphy_cmdw_done[0:0] + attribute \src "ls180.v:4357.1-4433.4" + wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4357.1-4433.4" + wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4357.1-4433.4" + wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1065.11-1065.57" + wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1066.5-1066.52" + wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdphy_cmdw_sink_last[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0] + attribute \src "ls180.v:4357.1-4433.4" + wire $0\main_sdphy_cmdw_sink_ready[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdphy_cmdw_sink_valid[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 10 $0\main_sdphy_datar_count[9:0] + attribute \src "ls180.v:4728.1-4829.4" + wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + attribute \src "ls180.v:4728.1-4829.4" + wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_datar_datar_buf_source_first[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_datar_datar_buf_source_last[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_datar_datar_buf_source_valid[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_datar_datar_converter_demux[0:0] + attribute \src "ls180.v:1277.5-1277.55" + wire $0\main_sdphy_datar_datar_converter_sink_first[0:0] + attribute \src "ls180.v:1278.5-1278.54" + wire $0\main_sdphy_datar_datar_converter_sink_last[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_datar_datar_converter_source_first[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_datar_datar_converter_source_last[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0] + attribute \src "ls180.v:1258.5-1258.48" + wire $0\main_sdphy_datar_datar_pads_in_ready[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_datar_datar_reset[0:0] + attribute \src "ls180.v:4728.1-4829.4" + wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + attribute \src "ls180.v:4728.1-4829.4" + wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_datar_datar_run[0:0] + attribute \src "ls180.v:4728.1-4829.4" + wire $0\main_sdphy_datar_datar_source_source_ready0[0:0] + attribute \src "ls180.v:1229.5-1229.50" + wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1230.5-1230.49" + wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1231.5-1231.56" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1233.5-1233.58" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1234.5-1234.59" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1236.11-1236.65" + wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1237.5-1237.60" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:4728.1-4829.4" + wire $0\main_sdphy_datar_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1240.5-1240.51" + wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1241.5-1241.52" + wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1242.11-1242.58" + wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1243.5-1243.53" + wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdphy_datar_sink_last[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0] + attribute \src "ls180.v:4728.1-4829.4" + wire $0\main_sdphy_datar_sink_ready[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdphy_datar_sink_valid[0:0] + attribute \src "ls180.v:1250.5-1250.41" + wire $0\main_sdphy_datar_source_first[0:0] + attribute \src "ls180.v:4728.1-4829.4" + wire $0\main_sdphy_datar_source_last[0:0] + attribute \src "ls180.v:4728.1-4829.4" + wire width 8 $0\main_sdphy_datar_source_payload_data[7:0] + attribute \src "ls180.v:4728.1-4829.4" + wire width 3 $0\main_sdphy_datar_source_payload_status[2:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdphy_datar_source_ready[0:0] + attribute \src "ls180.v:4728.1-4829.4" + wire $0\main_sdphy_datar_source_valid[0:0] + attribute \src "ls180.v:4728.1-4829.4" + wire $0\main_sdphy_datar_stop[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_sdphy_datar_timeout[31:0] + attribute \src "ls180.v:4728.1-4829.4" + wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + attribute \src "ls180.v:4728.1-4829.4" + wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\main_sdphy_dataw_count[7:0] + attribute \src "ls180.v:4622.1-4694.4" + wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + attribute \src "ls180.v:4622.1-4694.4" + wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0] + attribute \src "ls180.v:1199.5-1199.54" + wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] + attribute \src "ls180.v:1200.5-1200.53" + wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + attribute \src "ls180.v:1180.5-1180.47" + wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_dataw_crcr_reset[0:0] + attribute \src "ls180.v:4594.1-4621.4" + wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + attribute \src "ls180.v:4594.1-4621.4" + wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdphy_dataw_crcr_run[0:0] + attribute \src "ls180.v:4594.1-4621.4" + wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] + attribute \src "ls180.v:4594.1-4621.4" + wire $0\main_sdphy_dataw_error[0:0] + attribute \src "ls180.v:1167.5-1167.50" + wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1168.5-1168.49" + wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1169.5-1169.56" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1170.5-1170.58" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] + attribute \src "ls180.v:1171.5-1171.58" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1172.5-1172.59" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1173.11-1173.65" + wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] + attribute \src "ls180.v:1174.11-1174.65" + wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1175.5-1175.60" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:1165.5-1165.50" + wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] + attribute \src "ls180.v:4622.1-4694.4" + wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1154.5-1154.51" + wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1155.5-1155.52" + wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:4622.1-4694.4" + wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:4622.1-4694.4" + wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdphy_dataw_sink_first[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdphy_dataw_sink_last[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0] + attribute \src "ls180.v:4622.1-4694.4" + wire $0\main_sdphy_dataw_sink_ready[0:0] + attribute \src "ls180.v:5129.1-5319.4" + wire $0\main_sdphy_dataw_sink_valid[0:0] + attribute \src "ls180.v:4622.1-4694.4" + wire $0\main_sdphy_dataw_start[0:0] + attribute \src "ls180.v:4622.1-4694.4" + wire $0\main_sdphy_dataw_stop[0:0] + attribute \src "ls180.v:4594.1-4621.4" + wire $0\main_sdphy_dataw_valid[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\main_sdphy_init_count[7:0] + attribute \src "ls180.v:4323.1-4356.4" + wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + attribute \src "ls180.v:4323.1-4356.4" + wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + attribute \src "ls180.v:1047.5-1047.40" + wire $0\main_sdphy_init_initialize_w[0:0] + attribute \src "ls180.v:4323.1-4356.4" + wire $0\main_sdphy_init_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4323.1-4356.4" + wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4323.1-4356.4" + wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:4323.1-4356.4" + wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:4323.1-4356.4" + wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:7339.1-7409.4" + wire $0\main_sdphy_sdpads_cmd_i[0:0] + attribute \src "ls180.v:7339.1-7409.4" + wire width 4 $0\main_sdphy_sdpads_data_i[3:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_address_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 13 $0\main_sdram_address_storage[12:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_baddress_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 2 $0\main_sdram_baddress_storage[1:0] + attribute \src "ls180.v:3168.1-3175.4" + wire $0\main_sdram_bankmachine0_auto_precharge[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:425.5-425.64" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:408.5-408.67" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:409.5-409.66" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3190.1-3197.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3157.1-3164.4" + wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "ls180.v:3206.1-3299.4" + wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "ls180.v:3206.1-3299.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3206.1-3299.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3206.1-3299.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3206.1-3299.4" + wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "ls180.v:3206.1-3299.4" + wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "ls180.v:3855.1-3863.4" + wire $0\main_sdram_bankmachine0_cmd_ready[0:0] + attribute \src "ls180.v:3206.1-3299.4" + wire $0\main_sdram_bankmachine0_cmd_valid[0:0] + attribute \src "ls180.v:3206.1-3299.4" + wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "ls180.v:3206.1-3299.4" + wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "ls180.v:3206.1-3299.4" + wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 13 $0\main_sdram_bankmachine0_row[12:0] + attribute \src "ls180.v:3206.1-3299.4" + wire $0\main_sdram_bankmachine0_row_close[0:0] + attribute \src "ls180.v:3206.1-3299.4" + wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3206.1-3299.4" + wire $0\main_sdram_bankmachine0_row_open[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine0_row_opened[0:0] + attribute \src "ls180.v:467.32-467.76" + wire $0\main_sdram_bankmachine0_trascon_ready[0:0] + attribute \src "ls180.v:465.32-465.75" + wire $0\main_sdram_bankmachine0_trccon_ready[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "ls180.v:3325.1-3332.4" + wire $0\main_sdram_bankmachine1_auto_precharge[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:507.5-507.64" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:490.5-490.67" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:491.5-491.66" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3347.1-3354.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3314.1-3321.4" + wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "ls180.v:3363.1-3456.4" + wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "ls180.v:3363.1-3456.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3363.1-3456.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3363.1-3456.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3363.1-3456.4" + wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "ls180.v:3363.1-3456.4" + wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "ls180.v:3864.1-3872.4" + wire $0\main_sdram_bankmachine1_cmd_ready[0:0] + attribute \src "ls180.v:3363.1-3456.4" + wire $0\main_sdram_bankmachine1_cmd_valid[0:0] + attribute \src "ls180.v:3363.1-3456.4" + wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "ls180.v:3363.1-3456.4" + wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "ls180.v:3363.1-3456.4" + wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 13 $0\main_sdram_bankmachine1_row[12:0] + attribute \src "ls180.v:3363.1-3456.4" + wire $0\main_sdram_bankmachine1_row_close[0:0] + attribute \src "ls180.v:3363.1-3456.4" + wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3363.1-3456.4" + wire $0\main_sdram_bankmachine1_row_open[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine1_row_opened[0:0] + attribute \src "ls180.v:549.32-549.76" + wire $0\main_sdram_bankmachine1_trascon_ready[0:0] + attribute \src "ls180.v:547.32-547.75" + wire $0\main_sdram_bankmachine1_trccon_ready[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "ls180.v:3482.1-3489.4" + wire $0\main_sdram_bankmachine2_auto_precharge[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:589.5-589.64" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:572.5-572.67" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:573.5-573.66" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3504.1-3511.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3471.1-3478.4" + wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "ls180.v:3520.1-3613.4" + wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "ls180.v:3520.1-3613.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3520.1-3613.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3520.1-3613.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3520.1-3613.4" + wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "ls180.v:3520.1-3613.4" + wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "ls180.v:3873.1-3881.4" + wire $0\main_sdram_bankmachine2_cmd_ready[0:0] + attribute \src "ls180.v:3520.1-3613.4" + wire $0\main_sdram_bankmachine2_cmd_valid[0:0] + attribute \src "ls180.v:3520.1-3613.4" + wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "ls180.v:3520.1-3613.4" + wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "ls180.v:3520.1-3613.4" + wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 13 $0\main_sdram_bankmachine2_row[12:0] + attribute \src "ls180.v:3520.1-3613.4" + wire $0\main_sdram_bankmachine2_row_close[0:0] + attribute \src "ls180.v:3520.1-3613.4" + wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3520.1-3613.4" + wire $0\main_sdram_bankmachine2_row_open[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine2_row_opened[0:0] + attribute \src "ls180.v:631.32-631.76" + wire $0\main_sdram_bankmachine2_trascon_ready[0:0] + attribute \src "ls180.v:629.32-629.75" + wire $0\main_sdram_bankmachine2_trccon_ready[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "ls180.v:3639.1-3646.4" + wire $0\main_sdram_bankmachine3_auto_precharge[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:671.5-671.64" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:654.5-654.67" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:655.5-655.66" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3661.1-3668.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3628.1-3635.4" + wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "ls180.v:3677.1-3770.4" + wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "ls180.v:3677.1-3770.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3677.1-3770.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3677.1-3770.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3677.1-3770.4" + wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "ls180.v:3677.1-3770.4" + wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "ls180.v:3882.1-3890.4" + wire $0\main_sdram_bankmachine3_cmd_ready[0:0] + attribute \src "ls180.v:3677.1-3770.4" + wire $0\main_sdram_bankmachine3_cmd_valid[0:0] + attribute \src "ls180.v:3677.1-3770.4" + wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "ls180.v:3677.1-3770.4" + wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "ls180.v:3677.1-3770.4" + wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 13 $0\main_sdram_bankmachine3_row[12:0] + attribute \src "ls180.v:3677.1-3770.4" + wire $0\main_sdram_bankmachine3_row_close[0:0] + attribute \src "ls180.v:3677.1-3770.4" + wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3677.1-3770.4" + wire $0\main_sdram_bankmachine3_row_open[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine3_row_opened[0:0] + attribute \src "ls180.v:713.32-713.76" + wire $0\main_sdram_bankmachine3_trascon_ready[0:0] + attribute \src "ls180.v:711.32-711.75" + wire $0\main_sdram_bankmachine3_trccon_ready[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "ls180.v:3804.1-3809.4" + wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "ls180.v:3810.1-3815.4" + wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "ls180.v:3816.1-3821.4" + wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "ls180.v:721.5-721.43" + wire $0\main_sdram_choose_cmd_cmd_ready[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 2 $0\main_sdram_choose_cmd_grant[1:0] + attribute \src "ls180.v:3790.1-3796.4" + wire width 4 $0\main_sdram_choose_cmd_valids[3:0] + attribute \src "ls180.v:719.5-719.48" + wire $0\main_sdram_choose_cmd_want_activates[0:0] + attribute \src "ls180.v:718.5-718.43" + wire $0\main_sdram_choose_cmd_want_cmds[0:0] + attribute \src "ls180.v:716.5-716.44" + wire $0\main_sdram_choose_cmd_want_reads[0:0] + attribute \src "ls180.v:717.5-717.45" + wire $0\main_sdram_choose_cmd_want_writes[0:0] + attribute \src "ls180.v:3837.1-3842.4" + wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "ls180.v:3843.1-3848.4" + wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "ls180.v:3849.1-3854.4" + wire $0\main_sdram_choose_req_cmd_payload_we[0:0] + attribute \src "ls180.v:3895.1-3967.4" + wire $0\main_sdram_choose_req_cmd_ready[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 2 $0\main_sdram_choose_req_grant[1:0] + attribute \src "ls180.v:3823.1-3829.4" + wire width 4 $0\main_sdram_choose_req_valids[3:0] + attribute \src "ls180.v:3895.1-3967.4" + wire $0\main_sdram_choose_req_want_activates[0:0] + attribute \src "ls180.v:3895.1-3967.4" + wire $0\main_sdram_choose_req_want_reads[0:0] + attribute \src "ls180.v:3895.1-3967.4" + wire $0\main_sdram_choose_req_want_writes[0:0] + attribute \src "ls180.v:3112.1-3142.4" + wire $0\main_sdram_cmd_last[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 13 $0\main_sdram_cmd_payload_a[12:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 2 $0\main_sdram_cmd_payload_ba[1:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_cmd_payload_cas[0:0] + attribute \src "ls180.v:369.5-369.42" + wire $0\main_sdram_cmd_payload_is_read[0:0] + attribute \src "ls180.v:370.5-370.43" + wire $0\main_sdram_cmd_payload_is_write[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_cmd_payload_ras[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_cmd_payload_we[0:0] + attribute \src "ls180.v:3895.1-3967.4" + wire $0\main_sdram_cmd_ready[0:0] + attribute \src "ls180.v:3112.1-3142.4" + wire $0\main_sdram_cmd_valid[0:0] + attribute \src "ls180.v:305.5-305.38" + wire $0\main_sdram_command_issue_w[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_command_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 6 $0\main_sdram_command_storage[5:0] + attribute \src "ls180.v:354.5-354.35" + wire $0\main_sdram_dfi_p0_act_n[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 13 $0\main_sdram_dfi_p0_address[12:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 2 $0\main_sdram_dfi_p0_bank[1:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_dfi_p0_cas_n[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_dfi_p0_cs_n[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_dfi_p0_ras_n[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_dfi_p0_rddata_en[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_dfi_p0_we_n[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_dfi_p0_wrdata_en[0:0] + attribute \src "ls180.v:3895.1-3967.4" + wire $0\main_sdram_en0[0:0] + attribute \src "ls180.v:3895.1-3967.4" + wire $0\main_sdram_en1[0:0] + attribute \src "ls180.v:3991.1-4004.4" + wire width 16 $0\main_sdram_interface_wdata[15:0] + attribute \src "ls180.v:3991.1-4004.4" + wire width 2 $0\main_sdram_interface_wdata_we[1:0] + attribute \src "ls180.v:255.5-255.36" + wire $0\main_sdram_inti_p0_act_n[0:0] + attribute \src "ls180.v:3053.1-3069.4" + wire $0\main_sdram_inti_p0_cas_n[0:0] + attribute \src "ls180.v:3053.1-3069.4" + wire $0\main_sdram_inti_p0_cs_n[0:0] + attribute \src "ls180.v:3053.1-3069.4" + wire $0\main_sdram_inti_p0_ras_n[0:0] + attribute \src "ls180.v:2995.1-3049.4" + wire width 16 $0\main_sdram_inti_p0_rddata[15:0] + attribute \src "ls180.v:2995.1-3049.4" + wire $0\main_sdram_inti_p0_rddata_valid[0:0] + attribute \src "ls180.v:3053.1-3069.4" + wire $0\main_sdram_inti_p0_we_n[0:0] + attribute \src "ls180.v:2995.1-3049.4" + wire $0\main_sdram_master_p0_act_n[0:0] + attribute \src "ls180.v:2995.1-3049.4" + wire width 13 $0\main_sdram_master_p0_address[12:0] + attribute \src "ls180.v:2995.1-3049.4" + wire width 2 $0\main_sdram_master_p0_bank[1:0] + attribute \src "ls180.v:2995.1-3049.4" + wire $0\main_sdram_master_p0_cas_n[0:0] + attribute \src "ls180.v:2995.1-3049.4" + wire $0\main_sdram_master_p0_cke[0:0] + attribute \src "ls180.v:2995.1-3049.4" + wire $0\main_sdram_master_p0_cs_n[0:0] + attribute \src "ls180.v:2995.1-3049.4" + wire $0\main_sdram_master_p0_odt[0:0] + attribute \src "ls180.v:2995.1-3049.4" + wire $0\main_sdram_master_p0_ras_n[0:0] + attribute \src "ls180.v:2995.1-3049.4" + wire $0\main_sdram_master_p0_rddata_en[0:0] + attribute \src "ls180.v:2995.1-3049.4" + wire $0\main_sdram_master_p0_reset_n[0:0] + attribute \src "ls180.v:2995.1-3049.4" + wire $0\main_sdram_master_p0_we_n[0:0] + attribute \src "ls180.v:2995.1-3049.4" + wire width 16 $0\main_sdram_master_p0_wrdata[15:0] + attribute \src "ls180.v:2995.1-3049.4" + wire $0\main_sdram_master_p0_wrdata_en[0:0] + attribute \src "ls180.v:2995.1-3049.4" + wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] + attribute \src "ls180.v:752.12-752.36" + wire width 13 $0\main_sdram_nop_a[12:0] + attribute \src "ls180.v:753.11-753.35" + wire width 2 $0\main_sdram_nop_ba[1:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_postponer_count[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_postponer_req_o[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_sequencer_count[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 4 $0\main_sdram_sequencer_counter[3:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_sequencer_done1[0:0] + attribute \src "ls180.v:3112.1-3142.4" + wire $0\main_sdram_sequencer_start0[0:0] + attribute \src "ls180.v:2995.1-3049.4" + wire width 16 $0\main_sdram_slave_p0_rddata[15:0] + attribute \src "ls180.v:2995.1-3049.4" + wire $0\main_sdram_slave_p0_rddata_valid[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdram_status[15:0] + attribute \src "ls180.v:755.5-755.31" + wire $0\main_sdram_steerer0[0:0] + attribute \src "ls180.v:756.5-756.31" + wire $0\main_sdram_steerer1[0:0] + attribute \src "ls180.v:3895.1-3967.4" + wire width 2 $0\main_sdram_steerer_sel[1:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 4 $0\main_sdram_storage[3:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_tccdcon_count[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_tccdcon_ready[0:0] + attribute \src "ls180.v:760.32-760.63" + wire $0\main_sdram_tfawcon_ready[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 5 $0\main_sdram_time0[4:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 4 $0\main_sdram_time1[3:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 10 $0\main_sdram_timer_count1[9:0] + attribute \src "ls180.v:758.32-758.63" + wire $0\main_sdram_trrdcon_ready[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_sdram_twtrcon_count[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_twtrcon_ready[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_sdram_wrdata_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_sdram_wrdata_storage[15:0] + attribute \src "ls180.v:976.12-976.48" + wire width 16 $0\main_spi_master_clk_divider0[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_spi_master_clk_divider1[15:0] + attribute \src "ls180.v:4213.1-4261.4" + wire $0\main_spi_master_clk_enable[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_spi_master_control_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 16 $0\main_spi_master_control_storage[15:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_spi_master_count[2:0] + attribute \src "ls180.v:4213.1-4261.4" + wire width 3 $0\main_spi_master_count_spimaster0_next_value[2:0] + attribute \src "ls180.v:4213.1-4261.4" + wire $0\main_spi_master_count_spimaster0_next_value_ce[0:0] + attribute \src "ls180.v:4213.1-4261.4" + wire $0\main_spi_master_cs_enable[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_spi_master_cs_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_spi_master_cs_storage[0:0] + attribute \src "ls180.v:4213.1-4261.4" + wire $0\main_spi_master_done0[0:0] + attribute \src "ls180.v:4213.1-4261.4" + wire $0\main_spi_master_irq[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_spi_master_loopback_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_spi_master_loopback_storage[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\main_spi_master_miso[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\main_spi_master_miso_data[7:0] + attribute \src "ls180.v:4213.1-4261.4" + wire $0\main_spi_master_miso_latch[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\main_spi_master_mosi_data[7:0] + attribute \src "ls180.v:4213.1-4261.4" + wire $0\main_spi_master_mosi_latch[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_spi_master_mosi_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 3 $0\main_spi_master_mosi_sel[2:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\main_spi_master_mosi_storage[7:0] + attribute \src "ls180.v:6265.1-6270.4" + wire $0\main_spi_master_start1[0:0] + attribute \src "ls180.v:4131.1-4135.4" + wire width 2 $0\main_uart_eventmanager_pending_w[1:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_uart_eventmanager_re[0:0] + attribute \src "ls180.v:4120.1-4124.4" + wire width 2 $0\main_uart_eventmanager_status_w[1:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 2 $0\main_uart_eventmanager_storage[1:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_uart_phy_re[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 4 $0\main_uart_phy_rx_bitcount[3:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_uart_phy_rx_busy[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_uart_phy_rx_r[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\main_uart_phy_rx_reg[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_uart_phy_sink_ready[0:0] + attribute \src "ls180.v:831.5-831.38" + wire $0\main_uart_phy_source_first[0:0] + attribute \src "ls180.v:832.5-832.37" + wire $0\main_uart_phy_source_last[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\main_uart_phy_source_payload_data[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_uart_phy_source_valid[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 32 $0\main_uart_phy_storage[31:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 4 $0\main_uart_phy_tx_bitcount[3:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_uart_phy_tx_busy[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 8 $0\main_uart_phy_tx_reg[7:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_uart_phy_uart_clk_rxen[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_uart_phy_uart_clk_txen[0:0] + attribute \src "ls180.v:958.5-958.27" + wire $0\main_uart_reset[0:0] + attribute \src "ls180.v:4125.1-4130.4" + wire $0\main_uart_rx_clear[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 4 $0\main_uart_rx_fifo_consume[3:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 5 $0\main_uart_rx_fifo_level0[4:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 4 $0\main_uart_rx_fifo_produce[3:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_uart_rx_fifo_readable[0:0] + attribute \src "ls180.v:940.5-940.37" + wire $0\main_uart_rx_fifo_replace[0:0] + attribute \src "ls180.v:4183.1-4190.4" + wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_uart_rx_old_trigger[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_uart_rx_pending[0:0] + attribute \src "ls180.v:4114.1-4119.4" + wire $0\main_uart_tx_clear[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 4 $0\main_uart_tx_fifo_consume[3:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 5 $0\main_uart_tx_fifo_level0[4:0] + attribute \src "ls180.v:7411.1-10036.4" + wire width 4 $0\main_uart_tx_fifo_produce[3:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_uart_tx_fifo_readable[0:0] + attribute \src "ls180.v:903.5-903.37" + wire $0\main_uart_tx_fifo_replace[0:0] + attribute \src "ls180.v:886.5-886.40" + wire $0\main_uart_tx_fifo_sink_first[0:0] + attribute \src "ls180.v:887.5-887.39" + wire $0\main_uart_tx_fifo_sink_last[0:0] + attribute \src "ls180.v:4153.1-4160.4" + wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_uart_tx_old_trigger[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_uart_tx_pending[0:0] + attribute \src "ls180.v:4023.1-4069.4" + wire $0\main_wb_sdram_ack[0:0] + attribute \src "ls180.v:799.5-799.29" + wire $0\main_wb_sdram_err[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\main_wdata_consumed[0:0] + attribute \src "ls180.v:10040.1-10050.4" + wire width 7 $0\memadr[6:0] + attribute \src "ls180.v:10060.1-10064.4" + wire width 25 $0\memdat[24:0] + attribute \src "ls180.v:10074.1-10078.4" + wire width 25 $0\memdat_1[24:0] + attribute \src "ls180.v:10088.1-10092.4" + wire width 25 $0\memdat_2[24:0] + attribute \src "ls180.v:10102.1-10106.4" + wire width 25 $0\memdat_3[24:0] + attribute \src "ls180.v:10117.1-10121.4" + wire width 10 $0\memdat_4[9:0] + attribute \src "ls180.v:10123.1-10126.4" + wire width 10 $0\memdat_5[9:0] + attribute \src "ls180.v:10134.1-10138.4" + wire width 10 $0\memdat_6[9:0] + attribute \src "ls180.v:10140.1-10143.4" + wire width 10 $0\memdat_7[9:0] + attribute \src "ls180.v:10150.1-10154.4" + wire width 10 $0\memdat_8[9:0] + attribute \src "ls180.v:10164.1-10168.4" + wire width 10 $0\memdat_9[9:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\pwm0[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\pwm1[0:0] + attribute \src "ls180.v:7339.1-7409.4" + wire $0\sdcard_clk[0:0] + attribute \src "ls180.v:7339.1-7409.4" + wire $0\sdcard_cmd_o[0:0] + attribute \src "ls180.v:7339.1-7409.4" + wire $0\sdcard_cmd_oe[0:0] + attribute \src "ls180.v:7339.1-7409.4" + wire width 4 $0\sdcard_data_o[3:0] + attribute \src "ls180.v:7339.1-7409.4" + wire $0\sdcard_data_oe[0:0] + attribute \src "ls180.v:7339.1-7409.4" + wire width 13 $0\sdram_a[12:0] + attribute \src "ls180.v:7339.1-7409.4" + wire width 2 $0\sdram_ba[1:0] + attribute \src "ls180.v:7339.1-7409.4" + wire $0\sdram_cas_n[0:0] + attribute \src "ls180.v:7339.1-7409.4" + wire $0\sdram_cke[0:0] + attribute \src "ls180.v:7339.1-7409.4" + wire $0\sdram_clock[0:0] + attribute \src "ls180.v:7339.1-7409.4" + wire $0\sdram_cs_n[0:0] + attribute \src "ls180.v:7339.1-7409.4" + wire width 2 $0\sdram_dm[1:0] + attribute \src "ls180.v:7339.1-7409.4" + wire width 16 $0\sdram_dq_o[15:0] + attribute \src "ls180.v:7339.1-7409.4" + wire $0\sdram_dq_oe[0:0] + attribute \src "ls180.v:7339.1-7409.4" + wire $0\sdram_ras_n[0:0] + attribute \src "ls180.v:7339.1-7409.4" + wire $0\sdram_we_n[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\spi_master_clk[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\spi_master_cs_n[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\spi_master_mosi[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\spisdcard_clk[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\spisdcard_cs_n[0:0] + attribute \src "ls180.v:7411.1-10036.4" + wire $0\spisdcard_mosi[0:0] + attribute \src "ls180.v:1725.11-1725.49" + wire width 3 $1\builder_bankmachine0_next_state[2:0] + attribute \src "ls180.v:1724.11-1724.44" + wire width 3 $1\builder_bankmachine0_state[2:0] + attribute \src "ls180.v:1727.11-1727.49" + wire width 3 $1\builder_bankmachine1_next_state[2:0] + attribute \src "ls180.v:1726.11-1726.44" + wire width 3 $1\builder_bankmachine1_state[2:0] + attribute \src "ls180.v:1729.11-1729.49" + wire width 3 $1\builder_bankmachine2_next_state[2:0] + attribute \src "ls180.v:1728.11-1728.44" + wire width 3 $1\builder_bankmachine2_state[2:0] + attribute \src "ls180.v:1731.11-1731.49" + wire width 3 $1\builder_bankmachine3_next_state[2:0] + attribute \src "ls180.v:1730.11-1730.44" + wire width 3 $1\builder_bankmachine3_state[2:0] + attribute \src "ls180.v:2576.5-2576.41" + wire $1\builder_comb_rhs_array_muxed0[0:0] + attribute \src "ls180.v:2589.5-2589.42" + wire $1\builder_comb_rhs_array_muxed10[0:0] + attribute \src "ls180.v:2590.5-2590.42" + wire $1\builder_comb_rhs_array_muxed11[0:0] + attribute \src "ls180.v:2594.12-2594.50" + wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] + attribute \src "ls180.v:2595.5-2595.42" + wire $1\builder_comb_rhs_array_muxed13[0:0] + attribute \src "ls180.v:2596.5-2596.42" + wire $1\builder_comb_rhs_array_muxed14[0:0] + attribute \src "ls180.v:2597.12-2597.50" + wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] + attribute \src "ls180.v:2598.5-2598.42" + wire $1\builder_comb_rhs_array_muxed16[0:0] + attribute \src "ls180.v:2599.5-2599.42" + wire $1\builder_comb_rhs_array_muxed17[0:0] + attribute \src "ls180.v:2600.12-2600.50" + wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] + attribute \src "ls180.v:2601.5-2601.42" + wire $1\builder_comb_rhs_array_muxed19[0:0] + attribute \src "ls180.v:2577.12-2577.49" + wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] + attribute \src "ls180.v:2602.5-2602.42" + wire $1\builder_comb_rhs_array_muxed20[0:0] + attribute \src "ls180.v:2603.12-2603.50" + wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] + attribute \src "ls180.v:2604.5-2604.42" + wire $1\builder_comb_rhs_array_muxed22[0:0] + attribute \src "ls180.v:2605.5-2605.42" + wire $1\builder_comb_rhs_array_muxed23[0:0] + attribute \src "ls180.v:2606.12-2606.50" + wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] + attribute \src "ls180.v:2607.12-2607.50" + wire width 32 $1\builder_comb_rhs_array_muxed25[31:0] + attribute \src "ls180.v:2608.11-2608.48" + wire width 4 $1\builder_comb_rhs_array_muxed26[3:0] + attribute \src "ls180.v:2609.5-2609.42" + wire $1\builder_comb_rhs_array_muxed27[0:0] + attribute \src "ls180.v:2610.5-2610.42" + wire $1\builder_comb_rhs_array_muxed28[0:0] + attribute \src "ls180.v:2611.5-2611.42" + wire $1\builder_comb_rhs_array_muxed29[0:0] + attribute \src "ls180.v:2578.11-2578.47" + wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] + attribute \src "ls180.v:2612.11-2612.48" + wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] + attribute \src "ls180.v:2613.11-2613.48" + wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] + attribute \src "ls180.v:2579.5-2579.41" + wire $1\builder_comb_rhs_array_muxed3[0:0] + attribute \src "ls180.v:2580.5-2580.41" + wire $1\builder_comb_rhs_array_muxed4[0:0] + attribute \src "ls180.v:2581.5-2581.41" + wire $1\builder_comb_rhs_array_muxed5[0:0] + attribute \src "ls180.v:2585.5-2585.41" + wire $1\builder_comb_rhs_array_muxed6[0:0] + attribute \src "ls180.v:2586.12-2586.49" + wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] + attribute \src "ls180.v:2587.11-2587.47" + wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] + attribute \src "ls180.v:2588.5-2588.41" + wire $1\builder_comb_rhs_array_muxed9[0:0] + attribute \src "ls180.v:2582.5-2582.39" + wire $1\builder_comb_t_array_muxed0[0:0] + attribute \src "ls180.v:2583.5-2583.39" + wire $1\builder_comb_t_array_muxed1[0:0] + attribute \src "ls180.v:2584.5-2584.39" + wire $1\builder_comb_t_array_muxed2[0:0] + attribute \src "ls180.v:2591.5-2591.39" + wire $1\builder_comb_t_array_muxed3[0:0] + attribute \src "ls180.v:2592.5-2592.39" + wire $1\builder_comb_t_array_muxed4[0:0] + attribute \src "ls180.v:2593.5-2593.39" + wire $1\builder_comb_t_array_muxed5[0:0] + attribute \src "ls180.v:1711.5-1711.41" + wire $1\builder_converter0_next_state[0:0] + attribute \src "ls180.v:1710.5-1710.36" + wire $1\builder_converter0_state[0:0] + attribute \src "ls180.v:1715.5-1715.41" + wire $1\builder_converter1_next_state[0:0] + attribute \src "ls180.v:1714.5-1714.36" + wire $1\builder_converter1_state[0:0] + attribute \src "ls180.v:1719.5-1719.41" + wire $1\builder_converter2_next_state[0:0] + attribute \src "ls180.v:1718.5-1718.36" + wire $1\builder_converter2_state[0:0] + attribute \src "ls180.v:1756.5-1756.40" + wire $1\builder_converter_next_state[0:0] + attribute \src "ls180.v:1755.5-1755.35" + wire $1\builder_converter_state[0:0] + attribute \src "ls180.v:1876.12-1876.39" + wire width 20 $1\builder_count[19:0] + attribute \src "ls180.v:1873.5-1873.25" + wire $1\builder_error[0:0] + attribute \src "ls180.v:1870.11-1870.31" + wire width 3 $1\builder_grant[2:0] + attribute \src "ls180.v:1880.11-1880.51" + wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2382.11-2382.52" + wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2415.11-2415.52" + wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2456.11-2456.52" + wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2521.11-2521.52" + wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2546.11-2546.52" + wire width 8 $1\builder_interface14_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1921.11-1921.51" + wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1950.11-1950.51" + wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1963.11-1963.51" + wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2004.11-2004.51" + wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2045.11-2045.51" + wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2110.11-2110.51" + wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2243.11-2243.51" + wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2324.11-2324.51" + wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2341.11-2341.51" + wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1843.12-1843.43" + wire width 14 $1\builder_libresocsim_adr[13:0] + attribute \src "ls180.v:2572.12-2572.55" + wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] + attribute \src "ls180.v:2573.5-2573.50" + wire $1\builder_libresocsim_adr_next_value_ce1[0:0] + attribute \src "ls180.v:1845.11-1845.43" + wire width 8 $1\builder_libresocsim_dat_w[7:0] + attribute \src "ls180.v:2570.11-2570.55" + wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] + attribute \src "ls180.v:2571.5-2571.52" + wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] + attribute \src "ls180.v:1844.5-1844.34" + wire $1\builder_libresocsim_we[0:0] + attribute \src "ls180.v:2574.5-2574.46" + wire $1\builder_libresocsim_we_next_value2[0:0] + attribute \src "ls180.v:2575.5-2575.49" + wire $1\builder_libresocsim_we_next_value_ce2[0:0] + attribute \src "ls180.v:1853.5-1853.44" + wire $1\builder_libresocsim_wishbone_ack[0:0] + attribute \src "ls180.v:1849.12-1849.54" + wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] + attribute \src "ls180.v:1733.11-1733.48" + wire width 3 $1\builder_multiplexer_next_state[2:0] + attribute \src "ls180.v:1732.11-1732.43" + wire width 3 $1\builder_multiplexer_state[2:0] + attribute \src "ls180.v:2679.32-2679.66" + wire $1\builder_multiregimpl0_regs0[0:0] + attribute \src "ls180.v:2680.32-2680.66" + wire $1\builder_multiregimpl0_regs1[0:0] + attribute \src "ls180.v:2699.32-2699.67" + wire $1\builder_multiregimpl10_regs0[0:0] + attribute \src "ls180.v:2700.32-2700.67" + wire $1\builder_multiregimpl10_regs1[0:0] + attribute \src "ls180.v:2701.32-2701.67" + wire $1\builder_multiregimpl11_regs0[0:0] + attribute \src "ls180.v:2702.32-2702.67" + wire $1\builder_multiregimpl11_regs1[0:0] + attribute \src "ls180.v:2703.32-2703.67" + wire $1\builder_multiregimpl12_regs0[0:0] + attribute \src "ls180.v:2704.32-2704.67" + wire $1\builder_multiregimpl12_regs1[0:0] + attribute \src "ls180.v:2705.32-2705.67" + wire $1\builder_multiregimpl13_regs0[0:0] + attribute \src "ls180.v:2706.32-2706.67" + wire $1\builder_multiregimpl13_regs1[0:0] + attribute \src "ls180.v:2707.32-2707.67" + wire $1\builder_multiregimpl14_regs0[0:0] + attribute \src "ls180.v:2708.32-2708.67" + wire $1\builder_multiregimpl14_regs1[0:0] + attribute \src "ls180.v:2709.32-2709.67" + wire $1\builder_multiregimpl15_regs0[0:0] + attribute \src "ls180.v:2710.32-2710.67" + wire $1\builder_multiregimpl15_regs1[0:0] + attribute \src "ls180.v:2711.32-2711.67" + wire $1\builder_multiregimpl16_regs0[0:0] + attribute \src "ls180.v:2712.32-2712.67" + wire $1\builder_multiregimpl16_regs1[0:0] + attribute \src "ls180.v:2681.32-2681.66" + wire $1\builder_multiregimpl1_regs0[0:0] + attribute \src "ls180.v:2682.32-2682.66" + wire $1\builder_multiregimpl1_regs1[0:0] + attribute \src "ls180.v:2683.32-2683.66" + wire $1\builder_multiregimpl2_regs0[0:0] + attribute \src "ls180.v:2684.32-2684.66" + wire $1\builder_multiregimpl2_regs1[0:0] + attribute \src "ls180.v:2685.32-2685.66" + wire $1\builder_multiregimpl3_regs0[0:0] + attribute \src "ls180.v:2686.32-2686.66" + wire $1\builder_multiregimpl3_regs1[0:0] + attribute \src "ls180.v:2687.32-2687.66" + wire $1\builder_multiregimpl4_regs0[0:0] + attribute \src "ls180.v:2688.32-2688.66" + wire $1\builder_multiregimpl4_regs1[0:0] + attribute \src "ls180.v:2689.32-2689.66" + wire $1\builder_multiregimpl5_regs0[0:0] + attribute \src "ls180.v:2690.32-2690.66" + wire $1\builder_multiregimpl5_regs1[0:0] + attribute \src "ls180.v:2691.32-2691.66" + wire $1\builder_multiregimpl6_regs0[0:0] + attribute \src "ls180.v:2692.32-2692.66" + wire $1\builder_multiregimpl6_regs1[0:0] + attribute \src "ls180.v:2693.32-2693.66" + wire $1\builder_multiregimpl7_regs0[0:0] + attribute \src "ls180.v:2694.32-2694.66" + wire $1\builder_multiregimpl7_regs1[0:0] + attribute \src "ls180.v:2695.32-2695.66" + wire $1\builder_multiregimpl8_regs0[0:0] + attribute \src "ls180.v:2696.32-2696.66" + wire $1\builder_multiregimpl8_regs1[0:0] + attribute \src "ls180.v:2697.32-2697.66" + wire $1\builder_multiregimpl9_regs0[0:0] + attribute \src "ls180.v:2698.32-2698.66" + wire $1\builder_multiregimpl9_regs1[0:0] + attribute \src "ls180.v:1751.5-1751.43" + wire $1\builder_new_master_rdata_valid0[0:0] + attribute \src "ls180.v:1752.5-1752.43" + wire $1\builder_new_master_rdata_valid1[0:0] + attribute \src "ls180.v:1753.5-1753.43" + wire $1\builder_new_master_rdata_valid2[0:0] + attribute \src "ls180.v:1754.5-1754.43" + wire $1\builder_new_master_rdata_valid3[0:0] + attribute \src "ls180.v:1750.5-1750.42" + wire $1\builder_new_master_wdata_ready[0:0] + attribute \src "ls180.v:2569.11-2569.36" + wire width 2 $1\builder_next_state[1:0] + attribute \src "ls180.v:1723.11-1723.46" + wire width 2 $1\builder_refresher_next_state[1:0] + attribute \src "ls180.v:1722.11-1722.41" + wire width 2 $1\builder_refresher_state[1:0] + attribute \src "ls180.v:1828.11-1828.51" + wire width 2 $1\builder_sdblock2memdma_next_state[1:0] + attribute \src "ls180.v:1827.11-1827.46" + wire width 2 $1\builder_sdblock2memdma_state[1:0] + attribute \src "ls180.v:1796.5-1796.57" + wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] + attribute \src "ls180.v:1795.5-1795.52" + wire $1\builder_sdcore_crcupstreaminserter_state[0:0] + attribute \src "ls180.v:1808.11-1808.47" + wire width 3 $1\builder_sdcore_fsm_next_state[2:0] + attribute \src "ls180.v:1807.11-1807.42" + wire width 3 $1\builder_sdcore_fsm_state[2:0] + attribute \src "ls180.v:1832.5-1832.49" + wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] + attribute \src "ls180.v:1831.5-1831.44" + wire $1\builder_sdmem2blockdma_fsm_state[0:0] + attribute \src "ls180.v:1836.11-1836.65" + wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] + attribute \src "ls180.v:1835.11-1835.60" + wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] + attribute \src "ls180.v:1784.11-1784.46" + wire width 3 $1\builder_sdphy_fsm_next_state[2:0] + attribute \src "ls180.v:1783.11-1783.41" + wire width 3 $1\builder_sdphy_fsm_state[2:0] + attribute \src "ls180.v:1772.11-1772.52" + wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] + attribute \src "ls180.v:1771.11-1771.47" + wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] + attribute \src "ls180.v:1768.11-1768.52" + wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] + attribute \src "ls180.v:1767.11-1767.47" + wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] + attribute \src "ls180.v:1780.5-1780.46" + wire $1\builder_sdphy_sdphycrcr_next_state[0:0] + attribute \src "ls180.v:1779.5-1779.41" + wire $1\builder_sdphy_sdphycrcr_state[0:0] + attribute \src "ls180.v:1788.11-1788.53" + wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] + attribute \src "ls180.v:1787.11-1787.48" + wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] + attribute \src "ls180.v:1764.5-1764.46" + wire $1\builder_sdphy_sdphyinit_next_state[0:0] + attribute \src "ls180.v:1763.5-1763.41" + wire $1\builder_sdphy_sdphyinit_state[0:0] + attribute \src "ls180.v:1864.5-1864.30" + wire $1\builder_shared_ack[0:0] + attribute \src "ls180.v:1860.12-1860.40" + wire width 32 $1\builder_shared_dat_r[31:0] + attribute \src "ls180.v:1871.11-1871.35" + wire width 5 $1\builder_slave_sel[4:0] + attribute \src "ls180.v:1872.11-1872.37" + wire width 5 $1\builder_slave_sel_r[4:0] + attribute \src "ls180.v:1760.11-1760.47" + wire width 2 $1\builder_spimaster0_next_state[1:0] + attribute \src "ls180.v:1759.11-1759.42" + wire width 2 $1\builder_spimaster0_state[1:0] + attribute \src "ls180.v:1840.11-1840.47" + wire width 2 $1\builder_spimaster1_next_state[1:0] + attribute \src "ls180.v:1839.11-1839.42" + wire width 2 $1\builder_spimaster1_state[1:0] + attribute \src "ls180.v:2568.11-2568.31" + wire width 2 $1\builder_state[1:0] + attribute \src "ls180.v:2621.5-2621.39" + wire $1\builder_sync_f_array_muxed0[0:0] + attribute \src "ls180.v:2622.5-2622.39" + wire $1\builder_sync_f_array_muxed1[0:0] + attribute \src "ls180.v:2614.11-2614.47" + wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] + attribute \src "ls180.v:2615.12-2615.49" + wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] + attribute \src "ls180.v:2616.5-2616.41" + wire $1\builder_sync_rhs_array_muxed2[0:0] + attribute \src "ls180.v:2617.5-2617.41" + wire $1\builder_sync_rhs_array_muxed3[0:0] + attribute \src "ls180.v:2618.5-2618.41" + wire $1\builder_sync_rhs_array_muxed4[0:0] + attribute \src "ls180.v:2619.5-2619.41" + wire $1\builder_sync_rhs_array_muxed5[0:0] + attribute \src "ls180.v:2620.5-2620.41" + wire $1\builder_sync_rhs_array_muxed6[0:0] + attribute \src "ls180.v:1702.12-1702.44" + wire width 16 $1\libresocsim_clk_divider1[15:0] + attribute \src "ls180.v:1697.5-1697.34" + wire $1\libresocsim_clk_enable[0:0] + attribute \src "ls180.v:1684.5-1684.34" + wire $1\libresocsim_control_re[0:0] + attribute \src "ls180.v:1683.12-1683.47" + wire width 16 $1\libresocsim_control_storage[15:0] + attribute \src "ls180.v:1699.11-1699.35" + wire width 3 $1\libresocsim_count[2:0] + attribute \src "ls180.v:1841.11-1841.57" + wire width 3 $1\libresocsim_count_spimaster1_next_value[2:0] + attribute \src "ls180.v:1842.5-1842.54" + wire $1\libresocsim_count_spimaster1_next_value_ce[0:0] + attribute \src "ls180.v:1698.5-1698.33" + wire $1\libresocsim_cs_enable[0:0] + attribute \src "ls180.v:1694.5-1694.29" + wire $1\libresocsim_cs_re[0:0] + attribute \src "ls180.v:1693.5-1693.34" + wire $1\libresocsim_cs_storage[0:0] + attribute \src "ls180.v:1674.5-1674.29" + wire $1\libresocsim_done0[0:0] + attribute \src "ls180.v:1675.5-1675.27" + wire $1\libresocsim_irq[0:0] + attribute \src "ls180.v:1696.5-1696.35" + wire $1\libresocsim_loopback_re[0:0] + attribute \src "ls180.v:1695.5-1695.40" + wire $1\libresocsim_loopback_storage[0:0] + attribute \src "ls180.v:1677.11-1677.34" + wire width 8 $1\libresocsim_miso[7:0] + attribute \src "ls180.v:1707.11-1707.39" + wire width 8 $1\libresocsim_miso_data[7:0] + attribute \src "ls180.v:1701.5-1701.34" + wire $1\libresocsim_miso_latch[0:0] + attribute \src "ls180.v:1705.11-1705.39" + wire width 8 $1\libresocsim_mosi_data[7:0] + attribute \src "ls180.v:1700.5-1700.34" + wire $1\libresocsim_mosi_latch[0:0] + attribute \src "ls180.v:1689.5-1689.31" + wire $1\libresocsim_mosi_re[0:0] + attribute \src "ls180.v:1706.11-1706.38" + wire width 3 $1\libresocsim_mosi_sel[2:0] + attribute \src "ls180.v:1688.11-1688.42" + wire width 8 $1\libresocsim_mosi_storage[7:0] + attribute \src "ls180.v:1709.5-1709.26" + wire $1\libresocsim_re[0:0] + attribute \src "ls180.v:1681.5-1681.30" + wire $1\libresocsim_start1[0:0] + attribute \src "ls180.v:1708.12-1708.41" + wire width 16 $1\libresocsim_storage[15:0] + attribute \src "ls180.v:812.5-812.29" + wire $1\main_cmd_consumed[0:0] + attribute \src "ls180.v:809.5-809.34" + wire $1\main_converter_counter[0:0] + attribute \src "ls180.v:1757.5-1757.55" + wire $1\main_converter_counter_converter_next_value[0:0] + attribute \src "ls180.v:1758.5-1758.58" + wire $1\main_converter_counter_converter_next_value_ce[0:0] + attribute \src "ls180.v:811.12-811.40" + wire width 32 $1\main_converter_dat_r[31:0] + attribute \src "ls180.v:808.5-808.31" + wire $1\main_converter_skip[0:0] + attribute \src "ls180.v:243.12-243.38" + wire width 16 $1\main_dfi_p0_rddata[15:0] + attribute \src "ls180.v:244.5-244.36" + wire $1\main_dfi_p0_rddata_valid[0:0] + attribute \src "ls180.v:1005.12-1005.30" + wire width 36 $1\main_dummy[35:0] + attribute \src "ls180.v:960.5-960.27" + wire $1\main_gpio_oe_re[0:0] + attribute \src "ls180.v:959.12-959.40" + wire width 16 $1\main_gpio_oe_storage[15:0] + attribute \src "ls180.v:964.5-964.28" + wire $1\main_gpio_out_re[0:0] + attribute \src "ls180.v:963.12-963.41" + wire width 16 $1\main_gpio_out_storage[15:0] + attribute \src "ls180.v:961.12-961.36" + wire width 16 $1\main_gpio_status[15:0] + attribute \src "ls180.v:1030.5-1030.23" + wire $1\main_i2c_re[0:0] + attribute \src "ls180.v:1029.11-1029.34" + wire width 3 $1\main_i2c_storage[2:0] + attribute \src "ls180.v:228.5-228.24" + wire $1\main_int_rst[0:0] + attribute \src "ls180.v:1578.12-1578.43" + wire width 32 $1\main_interface1_bus_adr[31:0] + attribute \src "ls180.v:1582.5-1582.35" + wire $1\main_interface1_bus_cyc[0:0] + attribute \src "ls180.v:1581.11-1581.41" + wire width 4 $1\main_interface1_bus_sel[3:0] + attribute \src "ls180.v:1583.5-1583.35" + wire $1\main_interface1_bus_stb[0:0] + attribute \src "ls180.v:1585.5-1585.34" + wire $1\main_interface1_bus_we[0:0] + attribute \src "ls180.v:63.12-63.47" + wire width 32 $1\main_libresocsim_bus_errors[31:0] + attribute \src "ls180.v:150.5-150.47" + wire $1\main_libresocsim_converter0_counter[0:0] + attribute \src "ls180.v:1712.5-1712.69" + wire $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:1713.5-1713.72" + wire $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:152.12-152.53" + wire width 64 $1\main_libresocsim_converter0_dat_r[63:0] + attribute \src "ls180.v:149.5-149.44" + wire $1\main_libresocsim_converter0_skip[0:0] + attribute \src "ls180.v:165.5-165.47" + wire $1\main_libresocsim_converter1_counter[0:0] + attribute \src "ls180.v:1716.5-1716.69" + wire $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:1717.5-1717.72" + wire $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:167.12-167.53" + wire width 64 $1\main_libresocsim_converter1_dat_r[63:0] + attribute \src "ls180.v:164.5-164.44" + wire $1\main_libresocsim_converter1_skip[0:0] + attribute \src "ls180.v:180.5-180.47" + wire $1\main_libresocsim_converter2_counter[0:0] + attribute \src "ls180.v:1720.5-1720.69" + wire $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] + attribute \src "ls180.v:1721.5-1721.72" + wire $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:182.12-182.53" + wire width 64 $1\main_libresocsim_converter2_dat_r[63:0] + attribute \src "ls180.v:179.5-179.44" + wire $1\main_libresocsim_converter2_skip[0:0] + attribute \src "ls180.v:203.5-203.34" + wire $1\main_libresocsim_en_re[0:0] + attribute \src "ls180.v:202.5-202.39" + wire $1\main_libresocsim_en_storage[0:0] + attribute \src "ls180.v:223.5-223.44" + wire $1\main_libresocsim_eventmanager_re[0:0] + attribute \src "ls180.v:222.5-222.49" + wire $1\main_libresocsim_eventmanager_storage[0:0] + attribute \src "ls180.v:138.12-138.71" + wire width 30 $1\main_libresocsim_interface0_converted_interface_adr[29:0] + attribute \src "ls180.v:142.5-142.63" + wire $1\main_libresocsim_interface0_converted_interface_cyc[0:0] + attribute \src "ls180.v:139.12-139.73" + wire width 32 $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] + attribute \src "ls180.v:141.11-141.69" + wire width 4 $1\main_libresocsim_interface0_converted_interface_sel[3:0] + attribute \src "ls180.v:143.5-143.63" + wire $1\main_libresocsim_interface0_converted_interface_stb[0:0] + attribute \src "ls180.v:145.5-145.62" + wire $1\main_libresocsim_interface0_converted_interface_we[0:0] + attribute \src "ls180.v:153.12-153.71" + wire width 30 $1\main_libresocsim_interface1_converted_interface_adr[29:0] + attribute \src "ls180.v:157.5-157.63" + wire $1\main_libresocsim_interface1_converted_interface_cyc[0:0] + attribute \src "ls180.v:154.12-154.73" + wire width 32 $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] + attribute \src "ls180.v:156.11-156.69" + wire width 4 $1\main_libresocsim_interface1_converted_interface_sel[3:0] + attribute \src "ls180.v:158.5-158.63" + wire $1\main_libresocsim_interface1_converted_interface_stb[0:0] + attribute \src "ls180.v:160.5-160.62" + wire $1\main_libresocsim_interface1_converted_interface_we[0:0] + attribute \src "ls180.v:168.12-168.71" + wire width 30 $1\main_libresocsim_interface2_converted_interface_adr[29:0] + attribute \src "ls180.v:172.5-172.63" + wire $1\main_libresocsim_interface2_converted_interface_cyc[0:0] + attribute \src "ls180.v:169.12-169.73" + wire width 32 $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] + attribute \src "ls180.v:171.11-171.69" + wire width 4 $1\main_libresocsim_interface2_converted_interface_sel[3:0] + attribute \src "ls180.v:173.5-173.63" + wire $1\main_libresocsim_interface2_converted_interface_stb[0:0] + attribute \src "ls180.v:175.5-175.62" + wire $1\main_libresocsim_interface2_converted_interface_we[0:0] + attribute \src "ls180.v:128.5-128.65" + wire $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] + attribute \src "ls180.v:72.5-72.46" + wire $1\main_libresocsim_libresoc_dbus_ack[0:0] + attribute \src "ls180.v:83.5-83.46" + wire $1\main_libresocsim_libresoc_ibus_ack[0:0] + attribute \src "ls180.v:65.12-65.55" + wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0] + attribute \src "ls180.v:116.5-116.49" + wire $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] + attribute \src "ls180.v:199.5-199.36" + wire $1\main_libresocsim_load_re[0:0] + attribute \src "ls180.v:198.12-198.49" + wire width 32 $1\main_libresocsim_load_storage[31:0] + attribute \src "ls180.v:189.5-189.40" + wire $1\main_libresocsim_ram_bus_ack[0:0] + attribute \src "ls180.v:201.5-201.38" + wire $1\main_libresocsim_reload_re[0:0] + attribute \src "ls180.v:200.12-200.51" + wire width 32 $1\main_libresocsim_reload_storage[31:0] + attribute \src "ls180.v:56.5-56.37" + wire $1\main_libresocsim_reset_re[0:0] + attribute \src "ls180.v:55.5-55.42" + wire $1\main_libresocsim_reset_storage[0:0] + attribute \src "ls180.v:58.5-58.39" + wire $1\main_libresocsim_scratch_re[0:0] + attribute \src "ls180.v:57.12-57.60" + wire width 32 $1\main_libresocsim_scratch_storage[31:0] + attribute \src "ls180.v:205.5-205.44" + wire $1\main_libresocsim_update_value_re[0:0] + attribute \src "ls180.v:204.5-204.49" + wire $1\main_libresocsim_update_value_storage[0:0] + attribute \src "ls180.v:224.12-224.42" + wire width 32 $1\main_libresocsim_value[31:0] + attribute \src "ls180.v:206.12-206.49" + wire width 32 $1\main_libresocsim_value_status[31:0] + attribute \src "ls180.v:196.11-196.37" + wire width 4 $1\main_libresocsim_we[3:0] + attribute \src "ls180.v:212.5-212.39" + wire $1\main_libresocsim_zero_clear[0:0] + attribute \src "ls180.v:213.5-213.45" + wire $1\main_libresocsim_zero_old_trigger[0:0] + attribute \src "ls180.v:210.5-210.41" + wire $1\main_libresocsim_zero_pending[0:0] + attribute \src "ls180.v:800.12-800.40" + wire width 30 $1\main_litedram_wb_adr[29:0] + attribute \src "ls180.v:804.5-804.32" + wire $1\main_litedram_wb_cyc[0:0] + attribute \src "ls180.v:801.12-801.42" + wire width 16 $1\main_litedram_wb_dat_w[15:0] + attribute \src "ls180.v:803.11-803.38" + wire width 2 $1\main_litedram_wb_sel[1:0] + attribute \src "ls180.v:805.5-805.32" + wire $1\main_litedram_wb_stb[0:0] + attribute \src "ls180.v:807.5-807.31" + wire $1\main_litedram_wb_we[0:0] + attribute \src "ls180.v:1009.12-1009.37" + wire width 32 $1\main_pwm0_counter[31:0] + attribute \src "ls180.v:1011.5-1011.31" + wire $1\main_pwm0_enable_re[0:0] + attribute \src "ls180.v:1010.5-1010.36" + wire $1\main_pwm0_enable_storage[0:0] + attribute \src "ls180.v:1015.5-1015.31" + wire $1\main_pwm0_period_re[0:0] + attribute \src "ls180.v:1014.12-1014.44" + wire width 32 $1\main_pwm0_period_storage[31:0] + attribute \src "ls180.v:1013.5-1013.30" + wire $1\main_pwm0_width_re[0:0] + attribute \src "ls180.v:1012.12-1012.43" + wire width 32 $1\main_pwm0_width_storage[31:0] + attribute \src "ls180.v:1019.12-1019.37" + wire width 32 $1\main_pwm1_counter[31:0] + attribute \src "ls180.v:1021.5-1021.31" + wire $1\main_pwm1_enable_re[0:0] + attribute \src "ls180.v:1020.5-1020.36" + wire $1\main_pwm1_enable_storage[0:0] + attribute \src "ls180.v:1025.5-1025.31" + wire $1\main_pwm1_period_re[0:0] + attribute \src "ls180.v:1024.12-1024.44" + wire width 32 $1\main_pwm1_period_storage[31:0] + attribute \src "ls180.v:1023.5-1023.30" + wire $1\main_pwm1_width_re[0:0] + attribute \src "ls180.v:1022.12-1022.43" + wire width 32 $1\main_pwm1_width_storage[31:0] + attribute \src "ls180.v:245.11-245.32" + wire width 3 $1\main_rddata_en[2:0] + attribute \src "ls180.v:1547.11-1547.50" + wire width 2 $1\main_sdblock2mem_converter_demux[1:0] + attribute \src "ls180.v:1543.5-1543.51" + wire $1\main_sdblock2mem_converter_source_first[0:0] + attribute \src "ls180.v:1544.5-1544.50" + wire $1\main_sdblock2mem_converter_source_last[0:0] + attribute \src "ls180.v:1545.12-1545.66" + wire width 32 $1\main_sdblock2mem_converter_source_payload_data[31:0] + attribute \src "ls180.v:1546.11-1546.77" + wire width 3 $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + attribute \src "ls180.v:1549.5-1549.49" + wire $1\main_sdblock2mem_converter_strobe_all[0:0] + attribute \src "ls180.v:1522.11-1522.47" + wire width 5 $1\main_sdblock2mem_fifo_consume[4:0] + attribute \src "ls180.v:1519.11-1519.45" + wire width 6 $1\main_sdblock2mem_fifo_level[5:0] + attribute \src "ls180.v:1521.11-1521.47" + wire width 5 $1\main_sdblock2mem_fifo_produce[4:0] + attribute \src "ls180.v:1523.11-1523.50" + wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0] + attribute \src "ls180.v:1557.12-1557.62" + wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0] + attribute \src "ls180.v:1558.12-1558.60" + wire width 32 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] + attribute \src "ls180.v:1555.5-1555.45" + wire $1\main_sdblock2mem_sink_sink_valid1[0:0] + attribute \src "ls180.v:1565.5-1565.54" + wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + attribute \src "ls180.v:1564.12-1564.67" + wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + attribute \src "ls180.v:1569.5-1569.56" + wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + attribute \src "ls180.v:1568.5-1568.61" + wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + attribute \src "ls180.v:1567.5-1567.56" + wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + attribute \src "ls180.v:1566.12-1566.69" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + attribute \src "ls180.v:1573.5-1573.54" + wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + attribute \src "ls180.v:1572.5-1572.59" + wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + attribute \src "ls180.v:1575.12-1575.61" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] + attribute \src "ls180.v:1829.12-1829.87" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + attribute \src "ls180.v:1830.5-1830.82" + wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + attribute \src "ls180.v:1560.5-1560.57" + wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + attribute \src "ls180.v:1570.5-1570.53" + wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0] + attribute \src "ls180.v:1339.5-1339.38" + wire $1\main_sdcore_block_count_re[0:0] + attribute \src "ls180.v:1338.12-1338.51" + wire width 32 $1\main_sdcore_block_count_storage[31:0] + attribute \src "ls180.v:1337.5-1337.39" + wire $1\main_sdcore_block_length_re[0:0] + attribute \src "ls180.v:1336.11-1336.51" + wire width 10 $1\main_sdcore_block_length_storage[9:0] + attribute \src "ls180.v:1323.5-1323.39" + wire $1\main_sdcore_cmd_argument_re[0:0] + attribute \src "ls180.v:1322.12-1322.52" + wire width 32 $1\main_sdcore_cmd_argument_storage[31:0] + attribute \src "ls180.v:1325.5-1325.38" + wire $1\main_sdcore_cmd_command_re[0:0] + attribute \src "ls180.v:1324.12-1324.51" + wire width 32 $1\main_sdcore_cmd_command_storage[31:0] + attribute \src "ls180.v:1478.11-1478.39" + wire width 3 $1\main_sdcore_cmd_count[2:0] + attribute \src "ls180.v:1813.11-1813.62" + wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + attribute \src "ls180.v:1814.5-1814.59" + wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + attribute \src "ls180.v:1479.5-1479.32" + wire $1\main_sdcore_cmd_done[0:0] + attribute \src "ls180.v:1809.5-1809.55" + wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + attribute \src "ls180.v:1810.5-1810.58" + wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + attribute \src "ls180.v:1480.5-1480.33" + wire $1\main_sdcore_cmd_error[0:0] + attribute \src "ls180.v:1817.5-1817.56" + wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + attribute \src "ls180.v:1818.5-1818.59" + wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + attribute \src "ls180.v:1330.13-1330.53" + wire width 128 $1\main_sdcore_cmd_response_status[127:0] + attribute \src "ls180.v:1825.13-1825.76" + wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + attribute \src "ls180.v:1826.5-1826.69" + wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + attribute \src "ls180.v:1481.5-1481.35" + wire $1\main_sdcore_cmd_timeout[0:0] + attribute \src "ls180.v:1819.5-1819.58" + wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + attribute \src "ls180.v:1820.5-1820.61" + wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + attribute \src "ls180.v:1439.11-1439.47" + wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0] + attribute \src "ls180.v:1445.5-1445.46" + wire $1\main_sdcore_crc16_checker_crc0_clr[0:0] + attribute \src "ls180.v:1444.12-1444.54" + wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0] + attribute \src "ls180.v:1440.12-1440.58" + wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + attribute \src "ls180.v:1452.5-1452.46" + wire $1\main_sdcore_crc16_checker_crc1_clr[0:0] + attribute \src "ls180.v:1451.12-1451.54" + wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0] + attribute \src "ls180.v:1447.12-1447.58" + wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + attribute \src "ls180.v:1459.5-1459.46" + wire $1\main_sdcore_crc16_checker_crc2_clr[0:0] + attribute \src "ls180.v:1458.12-1458.54" + wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0] + attribute \src "ls180.v:1454.12-1454.58" + wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + attribute \src "ls180.v:1466.5-1466.46" + wire $1\main_sdcore_crc16_checker_crc3_clr[0:0] + attribute \src "ls180.v:1465.12-1465.54" + wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0] + attribute \src "ls180.v:1461.12-1461.58" + wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + attribute \src "ls180.v:1468.12-1468.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0] + attribute \src "ls180.v:1469.12-1469.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0] + attribute \src "ls180.v:1470.12-1470.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0] + attribute \src "ls180.v:1471.12-1471.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0] + attribute \src "ls180.v:1473.12-1473.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0] + attribute \src "ls180.v:1474.12-1474.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0] + attribute \src "ls180.v:1475.12-1475.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0] + attribute \src "ls180.v:1476.12-1476.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0] + attribute \src "ls180.v:1430.5-1430.48" + wire $1\main_sdcore_crc16_checker_sink_first[0:0] + attribute \src "ls180.v:1431.5-1431.47" + wire $1\main_sdcore_crc16_checker_sink_last[0:0] + attribute \src "ls180.v:1432.11-1432.61" + wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0] + attribute \src "ls180.v:1429.5-1429.48" + wire $1\main_sdcore_crc16_checker_sink_ready[0:0] + attribute \src "ls180.v:1428.5-1428.48" + wire $1\main_sdcore_crc16_checker_sink_valid[0:0] + attribute \src "ls180.v:1433.5-1433.50" + wire $1\main_sdcore_crc16_checker_source_valid[0:0] + attribute \src "ls180.v:1438.11-1438.47" + wire width 8 $1\main_sdcore_crc16_checker_val[7:0] + attribute \src "ls180.v:1472.5-1472.43" + wire $1\main_sdcore_crc16_checker_valid[0:0] + attribute \src "ls180.v:1395.11-1395.48" + wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0] + attribute \src "ls180.v:1805.11-1805.87" + wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + attribute \src "ls180.v:1806.5-1806.84" + wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + attribute \src "ls180.v:1400.12-1400.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0] + attribute \src "ls180.v:1396.12-1396.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + attribute \src "ls180.v:1407.12-1407.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0] + attribute \src "ls180.v:1403.12-1403.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + attribute \src "ls180.v:1414.12-1414.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0] + attribute \src "ls180.v:1410.12-1410.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + attribute \src "ls180.v:1421.12-1421.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0] + attribute \src "ls180.v:1417.12-1417.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + attribute \src "ls180.v:1424.12-1424.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0] + attribute \src "ls180.v:1797.12-1797.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + attribute \src "ls180.v:1798.5-1798.88" + wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + attribute \src "ls180.v:1425.12-1425.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0] + attribute \src "ls180.v:1799.12-1799.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + attribute \src "ls180.v:1800.5-1800.88" + wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + attribute \src "ls180.v:1426.12-1426.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0] + attribute \src "ls180.v:1801.12-1801.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + attribute \src "ls180.v:1802.5-1802.88" + wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + attribute \src "ls180.v:1427.12-1427.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0] + attribute \src "ls180.v:1803.12-1803.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + attribute \src "ls180.v:1804.5-1804.88" + wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + attribute \src "ls180.v:1386.5-1386.49" + wire $1\main_sdcore_crc16_inserter_sink_ready[0:0] + attribute \src "ls180.v:1393.5-1393.50" + wire $1\main_sdcore_crc16_inserter_source_last[0:0] + attribute \src "ls180.v:1394.11-1394.64" + wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0] + attribute \src "ls180.v:1391.5-1391.51" + wire $1\main_sdcore_crc16_inserter_source_ready[0:0] + attribute \src "ls180.v:1390.5-1390.51" + wire $1\main_sdcore_crc16_inserter_source_valid[0:0] + attribute \src "ls180.v:1382.11-1382.47" + wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0] + attribute \src "ls180.v:1340.11-1340.51" + wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0] + attribute \src "ls180.v:1483.12-1483.42" + wire width 32 $1\main_sdcore_data_count[31:0] + attribute \src "ls180.v:1815.12-1815.65" + wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + attribute \src "ls180.v:1816.5-1816.60" + wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + attribute \src "ls180.v:1484.5-1484.33" + wire $1\main_sdcore_data_done[0:0] + attribute \src "ls180.v:1811.5-1811.56" + wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + attribute \src "ls180.v:1812.5-1812.59" + wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + attribute \src "ls180.v:1485.5-1485.34" + wire $1\main_sdcore_data_error[0:0] + attribute \src "ls180.v:1821.5-1821.57" + wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + attribute \src "ls180.v:1822.5-1822.60" + wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + attribute \src "ls180.v:1486.5-1486.36" + wire $1\main_sdcore_data_timeout[0:0] + attribute \src "ls180.v:1823.5-1823.59" + wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + attribute \src "ls180.v:1824.5-1824.62" + wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + attribute \src "ls180.v:1631.11-1631.48" + wire width 2 $1\main_sdmem2block_converter_mux[1:0] + attribute \src "ls180.v:1629.11-1629.64" + wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0] + attribute \src "ls180.v:1605.5-1605.40" + wire $1\main_sdmem2block_dma_base_re[0:0] + attribute \src "ls180.v:1604.12-1604.53" + wire width 64 $1\main_sdmem2block_dma_base_storage[63:0] + attribute \src "ls180.v:1603.12-1603.45" + wire width 32 $1\main_sdmem2block_dma_data[31:0] + attribute \src "ls180.v:1833.12-1833.75" + wire width 32 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + attribute \src "ls180.v:1834.5-1834.70" + wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + attribute \src "ls180.v:1610.5-1610.44" + wire $1\main_sdmem2block_dma_done_status[0:0] + attribute \src "ls180.v:1609.5-1609.42" + wire $1\main_sdmem2block_dma_enable_re[0:0] + attribute \src "ls180.v:1608.5-1608.47" + wire $1\main_sdmem2block_dma_enable_storage[0:0] + attribute \src "ls180.v:1607.5-1607.42" + wire $1\main_sdmem2block_dma_length_re[0:0] + attribute \src "ls180.v:1606.12-1606.55" + wire width 32 $1\main_sdmem2block_dma_length_storage[31:0] + attribute \src "ls180.v:1613.5-1613.40" + wire $1\main_sdmem2block_dma_loop_re[0:0] + attribute \src "ls180.v:1612.5-1612.45" + wire $1\main_sdmem2block_dma_loop_storage[0:0] + attribute \src "ls180.v:1617.12-1617.47" + wire width 32 $1\main_sdmem2block_dma_offset[31:0] + attribute \src "ls180.v:1837.12-1837.87" + wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + attribute \src "ls180.v:1838.5-1838.82" + wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + attribute \src "ls180.v:1596.5-1596.42" + wire $1\main_sdmem2block_dma_sink_last[0:0] + attribute \src "ls180.v:1597.12-1597.61" + wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0] + attribute \src "ls180.v:1595.5-1595.43" + wire $1\main_sdmem2block_dma_sink_ready[0:0] + attribute \src "ls180.v:1594.5-1594.43" + wire $1\main_sdmem2block_dma_sink_valid[0:0] + attribute \src "ls180.v:1601.5-1601.44" + wire $1\main_sdmem2block_dma_source_last[0:0] + attribute \src "ls180.v:1602.12-1602.60" + wire width 32 $1\main_sdmem2block_dma_source_payload_data[31:0] + attribute \src "ls180.v:1598.5-1598.45" + wire $1\main_sdmem2block_dma_source_valid[0:0] + attribute \src "ls180.v:1658.11-1658.47" + wire width 5 $1\main_sdmem2block_fifo_consume[4:0] + attribute \src "ls180.v:1655.11-1655.45" + wire width 6 $1\main_sdmem2block_fifo_level[5:0] + attribute \src "ls180.v:1657.11-1657.47" + wire width 5 $1\main_sdmem2block_fifo_produce[4:0] + attribute \src "ls180.v:1659.11-1659.50" + wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0] + attribute \src "ls180.v:1039.5-1039.35" + wire $1\main_sdphy_clocker_clk0[0:0] + attribute \src "ls180.v:1042.5-1042.35" + wire $1\main_sdphy_clocker_clk1[0:0] + attribute \src "ls180.v:1043.5-1043.36" + wire $1\main_sdphy_clocker_clk_d[0:0] + attribute \src "ls180.v:1041.11-1041.41" + wire width 9 $1\main_sdphy_clocker_clks[8:0] + attribute \src "ls180.v:1037.5-1037.33" + wire $1\main_sdphy_clocker_re[0:0] + attribute \src "ls180.v:1036.11-1036.46" + wire width 9 $1\main_sdphy_clocker_storage[8:0] + attribute \src "ls180.v:1145.5-1145.49" + wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + attribute \src "ls180.v:1146.5-1146.48" + wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + attribute \src "ls180.v:1147.11-1147.62" + wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + attribute \src "ls180.v:1143.5-1143.49" + wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + attribute \src "ls180.v:1130.11-1130.54" + wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] + attribute \src "ls180.v:1126.5-1126.55" + wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + attribute \src "ls180.v:1127.5-1127.54" + wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + attribute \src "ls180.v:1128.11-1128.68" + wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + attribute \src "ls180.v:1129.11-1129.81" + wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1132.5-1132.53" + wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + attribute \src "ls180.v:1148.5-1148.38" + wire $1\main_sdphy_cmdr_cmdr_reset[0:0] + attribute \src "ls180.v:1777.5-1777.66" + wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + attribute \src "ls180.v:1778.5-1778.69" + wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + attribute \src "ls180.v:1118.5-1118.36" + wire $1\main_sdphy_cmdr_cmdr_run[0:0] + attribute \src "ls180.v:1113.5-1113.53" + wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + attribute \src "ls180.v:1100.11-1100.39" + wire width 8 $1\main_sdphy_cmdr_count[7:0] + attribute \src "ls180.v:1773.11-1773.67" + wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + attribute \src "ls180.v:1774.5-1774.64" + wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + attribute \src "ls180.v:1085.5-1085.48" + wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1086.5-1086.50" + wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1087.5-1087.51" + wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1092.5-1092.37" + wire $1\main_sdphy_cmdr_sink_last[0:0] + attribute \src "ls180.v:1093.11-1093.53" + wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0] + attribute \src "ls180.v:1091.5-1091.38" + wire $1\main_sdphy_cmdr_sink_ready[0:0] + attribute \src "ls180.v:1090.5-1090.38" + wire $1\main_sdphy_cmdr_sink_valid[0:0] + attribute \src "ls180.v:1096.5-1096.39" + wire $1\main_sdphy_cmdr_source_last[0:0] + attribute \src "ls180.v:1097.11-1097.53" + wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0] + attribute \src "ls180.v:1098.11-1098.55" + wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0] + attribute \src "ls180.v:1095.5-1095.40" + wire $1\main_sdphy_cmdr_source_ready[0:0] + attribute \src "ls180.v:1094.5-1094.40" + wire $1\main_sdphy_cmdr_source_valid[0:0] + attribute \src "ls180.v:1099.12-1099.48" + wire width 32 $1\main_sdphy_cmdr_timeout[31:0] + attribute \src "ls180.v:1775.12-1775.71" + wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + attribute \src "ls180.v:1776.5-1776.66" + wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + attribute \src "ls180.v:1072.11-1072.39" + wire width 8 $1\main_sdphy_cmdw_count[7:0] + attribute \src "ls180.v:1769.11-1769.66" + wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + attribute \src "ls180.v:1770.5-1770.63" + wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + attribute \src "ls180.v:1071.5-1071.32" + wire $1\main_sdphy_cmdw_done[0:0] + attribute \src "ls180.v:1062.5-1062.48" + wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1063.5-1063.50" + wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1064.5-1064.51" + wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1069.5-1069.37" + wire $1\main_sdphy_cmdw_sink_last[0:0] + attribute \src "ls180.v:1070.11-1070.51" + wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0] + attribute \src "ls180.v:1068.5-1068.38" + wire $1\main_sdphy_cmdw_sink_ready[0:0] + attribute \src "ls180.v:1067.5-1067.38" + wire $1\main_sdphy_cmdw_sink_valid[0:0] + attribute \src "ls180.v:1256.11-1256.41" + wire width 10 $1\main_sdphy_datar_count[9:0] + attribute \src "ls180.v:1789.11-1789.70" + wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + attribute \src "ls180.v:1790.5-1790.66" + wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + attribute \src "ls180.v:1301.5-1301.51" + wire $1\main_sdphy_datar_datar_buf_source_first[0:0] + attribute \src "ls180.v:1302.5-1302.50" + wire $1\main_sdphy_datar_datar_buf_source_last[0:0] + attribute \src "ls180.v:1303.11-1303.64" + wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] + attribute \src "ls180.v:1299.5-1299.51" + wire $1\main_sdphy_datar_datar_buf_source_valid[0:0] + attribute \src "ls180.v:1286.5-1286.50" + wire $1\main_sdphy_datar_datar_converter_demux[0:0] + attribute \src "ls180.v:1282.5-1282.57" + wire $1\main_sdphy_datar_datar_converter_source_first[0:0] + attribute \src "ls180.v:1283.5-1283.56" + wire $1\main_sdphy_datar_datar_converter_source_last[0:0] + attribute \src "ls180.v:1284.11-1284.70" + wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] + attribute \src "ls180.v:1285.11-1285.83" + wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + attribute \src "ls180.v:1288.5-1288.55" + wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0] + attribute \src "ls180.v:1304.5-1304.40" + wire $1\main_sdphy_datar_datar_reset[0:0] + attribute \src "ls180.v:1793.5-1793.69" + wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + attribute \src "ls180.v:1794.5-1794.72" + wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + attribute \src "ls180.v:1274.5-1274.38" + wire $1\main_sdphy_datar_datar_run[0:0] + attribute \src "ls180.v:1269.5-1269.55" + wire $1\main_sdphy_datar_datar_source_source_ready0[0:0] + attribute \src "ls180.v:1239.5-1239.49" + wire $1\main_sdphy_datar_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1246.5-1246.38" + wire $1\main_sdphy_datar_sink_last[0:0] + attribute \src "ls180.v:1247.11-1247.61" + wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0] + attribute \src "ls180.v:1245.5-1245.39" + wire $1\main_sdphy_datar_sink_ready[0:0] + attribute \src "ls180.v:1244.5-1244.39" + wire $1\main_sdphy_datar_sink_valid[0:0] + attribute \src "ls180.v:1251.5-1251.40" + wire $1\main_sdphy_datar_source_last[0:0] + attribute \src "ls180.v:1252.11-1252.54" + wire width 8 $1\main_sdphy_datar_source_payload_data[7:0] + attribute \src "ls180.v:1253.11-1253.56" + wire width 3 $1\main_sdphy_datar_source_payload_status[2:0] + attribute \src "ls180.v:1249.5-1249.41" + wire $1\main_sdphy_datar_source_ready[0:0] + attribute \src "ls180.v:1248.5-1248.41" + wire $1\main_sdphy_datar_source_valid[0:0] + attribute \src "ls180.v:1254.5-1254.33" + wire $1\main_sdphy_datar_stop[0:0] + attribute \src "ls180.v:1255.12-1255.49" + wire width 32 $1\main_sdphy_datar_timeout[31:0] + attribute \src "ls180.v:1791.12-1791.73" + wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + attribute \src "ls180.v:1792.5-1792.68" + wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + attribute \src "ls180.v:1164.11-1164.40" + wire width 8 $1\main_sdphy_dataw_count[7:0] + attribute \src "ls180.v:1785.11-1785.61" + wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + attribute \src "ls180.v:1786.5-1786.58" + wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + attribute \src "ls180.v:1223.5-1223.50" + wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0] + attribute \src "ls180.v:1224.5-1224.49" + wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0] + attribute \src "ls180.v:1225.11-1225.63" + wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + attribute \src "ls180.v:1221.5-1221.50" + wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] + attribute \src "ls180.v:1208.11-1208.55" + wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0] + attribute \src "ls180.v:1204.5-1204.56" + wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0] + attribute \src "ls180.v:1205.5-1205.55" + wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0] + attribute \src "ls180.v:1206.11-1206.69" + wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + attribute \src "ls180.v:1207.11-1207.82" + wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1210.5-1210.54" + wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + attribute \src "ls180.v:1226.5-1226.39" + wire $1\main_sdphy_dataw_crcr_reset[0:0] + attribute \src "ls180.v:1781.5-1781.66" + wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + attribute \src "ls180.v:1782.5-1782.69" + wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + attribute \src "ls180.v:1196.5-1196.37" + wire $1\main_sdphy_dataw_crcr_run[0:0] + attribute \src "ls180.v:1191.5-1191.54" + wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] + attribute \src "ls180.v:1178.5-1178.34" + wire $1\main_sdphy_dataw_error[0:0] + attribute \src "ls180.v:1153.5-1153.49" + wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1156.11-1156.58" + wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1157.5-1157.53" + wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:1160.5-1160.39" + wire $1\main_sdphy_dataw_sink_first[0:0] + attribute \src "ls180.v:1161.5-1161.38" + wire $1\main_sdphy_dataw_sink_last[0:0] + attribute \src "ls180.v:1162.11-1162.52" + wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0] + attribute \src "ls180.v:1159.5-1159.39" + wire $1\main_sdphy_dataw_sink_ready[0:0] + attribute \src "ls180.v:1158.5-1158.39" + wire $1\main_sdphy_dataw_sink_valid[0:0] + attribute \src "ls180.v:1176.5-1176.34" + wire $1\main_sdphy_dataw_start[0:0] + attribute \src "ls180.v:1163.5-1163.33" + wire $1\main_sdphy_dataw_stop[0:0] + attribute \src "ls180.v:1177.5-1177.34" + wire $1\main_sdphy_dataw_valid[0:0] + attribute \src "ls180.v:1057.11-1057.39" + wire width 8 $1\main_sdphy_init_count[7:0] + attribute \src "ls180.v:1765.11-1765.66" + wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + attribute \src "ls180.v:1766.5-1766.63" + wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + attribute \src "ls180.v:1052.5-1052.48" + wire $1\main_sdphy_init_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1053.5-1053.50" + wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1054.5-1054.51" + wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1055.11-1055.57" + wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1056.5-1056.52" + wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:1306.5-1306.35" + wire $1\main_sdphy_sdpads_cmd_i[0:0] + attribute \src "ls180.v:1309.11-1309.42" + wire width 4 $1\main_sdphy_sdpads_data_i[3:0] + attribute \src "ls180.v:307.5-307.33" + wire $1\main_sdram_address_re[0:0] + attribute \src "ls180.v:306.12-306.46" + wire width 13 $1\main_sdram_address_storage[12:0] + attribute \src "ls180.v:309.5-309.34" + wire $1\main_sdram_baddress_re[0:0] + attribute \src "ls180.v:308.11-308.45" + wire width 2 $1\main_sdram_baddress_storage[1:0] + attribute \src "ls180.v:405.5-405.50" + wire $1\main_sdram_bankmachine0_auto_precharge[0:0] + attribute \src "ls180.v:427.11-427.70" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:424.11-424.68" + wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:426.11-426.70" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:428.11-428.73" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:451.5-451.59" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:452.5-452.58" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:454.12-454.74" + wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:453.5-453.64" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:449.5-449.59" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:397.12-397.57" + wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "ls180.v:399.5-399.51" + wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "ls180.v:402.5-402.54" + wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:403.5-403.55" + wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "ls180.v:404.5-404.56" + wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "ls180.v:400.5-400.51" + wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "ls180.v:401.5-401.50" + wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "ls180.v:396.5-396.45" + wire $1\main_sdram_bankmachine0_cmd_ready[0:0] + attribute \src "ls180.v:395.5-395.45" + wire $1\main_sdram_bankmachine0_cmd_valid[0:0] + attribute \src "ls180.v:394.5-394.47" + wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "ls180.v:392.5-392.51" + wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "ls180.v:391.5-391.51" + wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "ls180.v:455.12-455.47" + wire width 13 $1\main_sdram_bankmachine0_row[12:0] + attribute \src "ls180.v:459.5-459.45" + wire $1\main_sdram_bankmachine0_row_close[0:0] + attribute \src "ls180.v:460.5-460.54" + wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:458.5-458.44" + wire $1\main_sdram_bankmachine0_row_open[0:0] + attribute \src "ls180.v:456.5-456.46" + wire $1\main_sdram_bankmachine0_row_opened[0:0] + attribute \src "ls180.v:463.11-463.55" + wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "ls180.v:462.32-462.76" + wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "ls180.v:487.5-487.50" + wire $1\main_sdram_bankmachine1_auto_precharge[0:0] + attribute \src "ls180.v:509.11-509.70" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:506.11-506.68" + wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:508.11-508.70" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:510.11-510.73" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:533.5-533.59" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:534.5-534.58" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:536.12-536.74" + wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:535.5-535.64" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:531.5-531.59" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:479.12-479.57" + wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "ls180.v:481.5-481.51" + wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "ls180.v:484.5-484.54" + wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:485.5-485.55" + wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + attribute \src "ls180.v:486.5-486.56" + wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "ls180.v:482.5-482.51" + wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "ls180.v:483.5-483.50" + wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "ls180.v:478.5-478.45" + wire $1\main_sdram_bankmachine1_cmd_ready[0:0] + attribute \src "ls180.v:477.5-477.45" + wire $1\main_sdram_bankmachine1_cmd_valid[0:0] + attribute \src "ls180.v:476.5-476.47" + wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "ls180.v:474.5-474.51" + wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "ls180.v:473.5-473.51" + wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "ls180.v:537.12-537.47" + wire width 13 $1\main_sdram_bankmachine1_row[12:0] + attribute \src "ls180.v:541.5-541.45" + wire $1\main_sdram_bankmachine1_row_close[0:0] + attribute \src "ls180.v:542.5-542.54" + wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:540.5-540.44" + wire $1\main_sdram_bankmachine1_row_open[0:0] + attribute \src "ls180.v:538.5-538.46" + wire $1\main_sdram_bankmachine1_row_opened[0:0] + attribute \src "ls180.v:545.11-545.55" + wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "ls180.v:544.32-544.76" + wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "ls180.v:569.5-569.50" + wire $1\main_sdram_bankmachine2_auto_precharge[0:0] + attribute \src "ls180.v:591.11-591.70" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:588.11-588.68" + wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:590.11-590.70" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:592.11-592.73" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:615.5-615.59" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:616.5-616.58" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:618.12-618.74" + wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:617.5-617.64" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:613.5-613.59" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:561.12-561.57" + wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "ls180.v:563.5-563.51" + wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "ls180.v:566.5-566.54" + wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:567.5-567.55" + wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + attribute \src "ls180.v:568.5-568.56" + wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "ls180.v:564.5-564.51" + wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "ls180.v:565.5-565.50" + wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "ls180.v:560.5-560.45" + wire $1\main_sdram_bankmachine2_cmd_ready[0:0] + attribute \src "ls180.v:559.5-559.45" + wire $1\main_sdram_bankmachine2_cmd_valid[0:0] + attribute \src "ls180.v:558.5-558.47" + wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "ls180.v:556.5-556.51" + wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "ls180.v:555.5-555.51" + wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "ls180.v:619.12-619.47" + wire width 13 $1\main_sdram_bankmachine2_row[12:0] + attribute \src "ls180.v:623.5-623.45" + wire $1\main_sdram_bankmachine2_row_close[0:0] + attribute \src "ls180.v:624.5-624.54" + wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:622.5-622.44" + wire $1\main_sdram_bankmachine2_row_open[0:0] + attribute \src "ls180.v:620.5-620.46" + wire $1\main_sdram_bankmachine2_row_opened[0:0] + attribute \src "ls180.v:627.11-627.55" + wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "ls180.v:626.32-626.76" + wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "ls180.v:651.5-651.50" + wire $1\main_sdram_bankmachine3_auto_precharge[0:0] + attribute \src "ls180.v:673.11-673.70" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:670.11-670.68" + wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:672.11-672.70" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:674.11-674.73" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:697.5-697.59" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:698.5-698.58" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:700.12-700.74" + wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:699.5-699.64" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:695.5-695.59" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:643.12-643.57" + wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "ls180.v:645.5-645.51" + wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "ls180.v:648.5-648.54" + wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:649.5-649.55" + wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + attribute \src "ls180.v:650.5-650.56" + wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "ls180.v:646.5-646.51" + wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "ls180.v:647.5-647.50" + wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "ls180.v:642.5-642.45" + wire $1\main_sdram_bankmachine3_cmd_ready[0:0] + attribute \src "ls180.v:641.5-641.45" + wire $1\main_sdram_bankmachine3_cmd_valid[0:0] + attribute \src "ls180.v:640.5-640.47" + wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "ls180.v:638.5-638.51" + wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "ls180.v:637.5-637.51" + wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "ls180.v:701.12-701.47" + wire width 13 $1\main_sdram_bankmachine3_row[12:0] + attribute \src "ls180.v:705.5-705.45" + wire $1\main_sdram_bankmachine3_row_close[0:0] + attribute \src "ls180.v:706.5-706.54" + wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:704.5-704.44" + wire $1\main_sdram_bankmachine3_row_open[0:0] + attribute \src "ls180.v:702.5-702.46" + wire $1\main_sdram_bankmachine3_row_opened[0:0] + attribute \src "ls180.v:709.11-709.55" + wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "ls180.v:708.32-708.76" + wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "ls180.v:724.5-724.49" + wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "ls180.v:725.5-725.49" + wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "ls180.v:726.5-726.48" + wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "ls180.v:732.11-732.45" + wire width 2 $1\main_sdram_choose_cmd_grant[1:0] + attribute \src "ls180.v:730.11-730.46" + wire width 4 $1\main_sdram_choose_cmd_valids[3:0] + attribute \src "ls180.v:742.5-742.49" + wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "ls180.v:743.5-743.49" + wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "ls180.v:744.5-744.48" + wire $1\main_sdram_choose_req_cmd_payload_we[0:0] + attribute \src "ls180.v:739.5-739.43" + wire $1\main_sdram_choose_req_cmd_ready[0:0] + attribute \src "ls180.v:750.11-750.45" + wire width 2 $1\main_sdram_choose_req_grant[1:0] + attribute \src "ls180.v:748.11-748.46" + wire width 4 $1\main_sdram_choose_req_valids[3:0] + attribute \src "ls180.v:737.5-737.48" + wire $1\main_sdram_choose_req_want_activates[0:0] + attribute \src "ls180.v:734.5-734.44" + wire $1\main_sdram_choose_req_want_reads[0:0] + attribute \src "ls180.v:735.5-735.45" + wire $1\main_sdram_choose_req_want_writes[0:0] + attribute \src "ls180.v:363.5-363.31" + wire $1\main_sdram_cmd_last[0:0] + attribute \src "ls180.v:364.12-364.44" + wire width 13 $1\main_sdram_cmd_payload_a[12:0] + attribute \src "ls180.v:365.11-365.43" + wire width 2 $1\main_sdram_cmd_payload_ba[1:0] + attribute \src "ls180.v:366.5-366.38" + wire $1\main_sdram_cmd_payload_cas[0:0] + attribute \src "ls180.v:367.5-367.38" + wire $1\main_sdram_cmd_payload_ras[0:0] + attribute \src "ls180.v:368.5-368.37" + wire $1\main_sdram_cmd_payload_we[0:0] + attribute \src "ls180.v:362.5-362.32" + wire $1\main_sdram_cmd_ready[0:0] + attribute \src "ls180.v:361.5-361.32" + wire $1\main_sdram_cmd_valid[0:0] + attribute \src "ls180.v:301.5-301.33" + wire $1\main_sdram_command_re[0:0] + attribute \src "ls180.v:300.11-300.44" + wire width 6 $1\main_sdram_command_storage[5:0] + attribute \src "ls180.v:345.12-345.45" + wire width 13 $1\main_sdram_dfi_p0_address[12:0] + attribute \src "ls180.v:346.11-346.40" + wire width 2 $1\main_sdram_dfi_p0_bank[1:0] + attribute \src "ls180.v:347.5-347.35" + wire $1\main_sdram_dfi_p0_cas_n[0:0] + attribute \src "ls180.v:348.5-348.34" + wire $1\main_sdram_dfi_p0_cs_n[0:0] + attribute \src "ls180.v:349.5-349.35" + wire $1\main_sdram_dfi_p0_ras_n[0:0] + attribute \src "ls180.v:358.5-358.39" + wire $1\main_sdram_dfi_p0_rddata_en[0:0] + attribute \src "ls180.v:350.5-350.34" + wire $1\main_sdram_dfi_p0_we_n[0:0] + attribute \src "ls180.v:356.5-356.39" + wire $1\main_sdram_dfi_p0_wrdata_en[0:0] + attribute \src "ls180.v:769.5-769.26" + wire $1\main_sdram_en0[0:0] + attribute \src "ls180.v:772.5-772.26" + wire $1\main_sdram_en1[0:0] + attribute \src "ls180.v:342.12-342.46" + wire width 16 $1\main_sdram_interface_wdata[15:0] + attribute \src "ls180.v:343.11-343.47" + wire width 2 $1\main_sdram_interface_wdata_we[1:0] + attribute \src "ls180.v:248.5-248.36" + wire $1\main_sdram_inti_p0_cas_n[0:0] + attribute \src "ls180.v:249.5-249.35" + wire $1\main_sdram_inti_p0_cs_n[0:0] + attribute \src "ls180.v:250.5-250.36" + wire $1\main_sdram_inti_p0_ras_n[0:0] + attribute \src "ls180.v:260.12-260.45" + wire width 16 $1\main_sdram_inti_p0_rddata[15:0] + attribute \src "ls180.v:261.5-261.43" + wire $1\main_sdram_inti_p0_rddata_valid[0:0] + attribute \src "ls180.v:251.5-251.35" + wire $1\main_sdram_inti_p0_we_n[0:0] + attribute \src "ls180.v:287.5-287.38" + wire $1\main_sdram_master_p0_act_n[0:0] + attribute \src "ls180.v:278.12-278.48" + wire width 13 $1\main_sdram_master_p0_address[12:0] + attribute \src "ls180.v:279.11-279.43" + wire width 2 $1\main_sdram_master_p0_bank[1:0] + attribute \src "ls180.v:280.5-280.38" + wire $1\main_sdram_master_p0_cas_n[0:0] + attribute \src "ls180.v:284.5-284.36" + wire $1\main_sdram_master_p0_cke[0:0] + attribute \src "ls180.v:281.5-281.37" + wire $1\main_sdram_master_p0_cs_n[0:0] + attribute \src "ls180.v:285.5-285.36" + wire $1\main_sdram_master_p0_odt[0:0] + attribute \src "ls180.v:282.5-282.38" + wire $1\main_sdram_master_p0_ras_n[0:0] + attribute \src "ls180.v:291.5-291.42" + wire $1\main_sdram_master_p0_rddata_en[0:0] + attribute \src "ls180.v:286.5-286.40" + wire $1\main_sdram_master_p0_reset_n[0:0] + attribute \src "ls180.v:283.5-283.37" + wire $1\main_sdram_master_p0_we_n[0:0] + attribute \src "ls180.v:288.12-288.47" + wire width 16 $1\main_sdram_master_p0_wrdata[15:0] + attribute \src "ls180.v:289.5-289.42" + wire $1\main_sdram_master_p0_wrdata_en[0:0] + attribute \src "ls180.v:290.11-290.50" + wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] + attribute \src "ls180.v:379.5-379.38" + wire $1\main_sdram_postponer_count[0:0] + attribute \src "ls180.v:378.5-378.38" + wire $1\main_sdram_postponer_req_o[0:0] + attribute \src "ls180.v:299.5-299.25" + wire $1\main_sdram_re[0:0] + attribute \src "ls180.v:385.5-385.38" + wire $1\main_sdram_sequencer_count[0:0] + attribute \src "ls180.v:384.11-384.46" + wire width 4 $1\main_sdram_sequencer_counter[3:0] + attribute \src "ls180.v:383.5-383.38" + wire $1\main_sdram_sequencer_done1[0:0] + attribute \src "ls180.v:380.5-380.39" + wire $1\main_sdram_sequencer_start0[0:0] + attribute \src "ls180.v:276.12-276.46" + wire width 16 $1\main_sdram_slave_p0_rddata[15:0] + attribute \src "ls180.v:277.5-277.44" + wire $1\main_sdram_slave_p0_rddata_valid[0:0] + attribute \src "ls180.v:312.12-312.37" + wire width 16 $1\main_sdram_status[15:0] + attribute \src "ls180.v:754.11-754.40" + wire width 2 $1\main_sdram_steerer_sel[1:0] + attribute \src "ls180.v:298.11-298.36" + wire width 4 $1\main_sdram_storage[3:0] + attribute \src "ls180.v:763.5-763.36" + wire $1\main_sdram_tccdcon_count[0:0] + attribute \src "ls180.v:762.32-762.63" + wire $1\main_sdram_tccdcon_ready[0:0] + attribute \src "ls180.v:771.11-771.34" + wire width 5 $1\main_sdram_time0[4:0] + attribute \src "ls180.v:774.11-774.34" + wire width 4 $1\main_sdram_time1[3:0] + attribute \src "ls180.v:376.11-376.44" + wire width 10 $1\main_sdram_timer_count1[9:0] + attribute \src "ls180.v:766.11-766.42" + wire width 3 $1\main_sdram_twtrcon_count[2:0] + attribute \src "ls180.v:765.32-765.63" + wire $1\main_sdram_twtrcon_ready[0:0] + attribute \src "ls180.v:311.5-311.32" + wire $1\main_sdram_wrdata_re[0:0] + attribute \src "ls180.v:310.12-310.45" + wire width 16 $1\main_sdram_wrdata_storage[15:0] + attribute \src "ls180.v:998.12-998.48" + wire width 16 $1\main_spi_master_clk_divider1[15:0] + attribute \src "ls180.v:993.5-993.38" + wire $1\main_spi_master_clk_enable[0:0] + attribute \src "ls180.v:980.5-980.38" + wire $1\main_spi_master_control_re[0:0] + attribute \src "ls180.v:979.12-979.51" + wire width 16 $1\main_spi_master_control_storage[15:0] + attribute \src "ls180.v:995.11-995.39" + wire width 3 $1\main_spi_master_count[2:0] + attribute \src "ls180.v:1761.11-1761.61" + wire width 3 $1\main_spi_master_count_spimaster0_next_value[2:0] + attribute \src "ls180.v:1762.5-1762.58" + wire $1\main_spi_master_count_spimaster0_next_value_ce[0:0] + attribute \src "ls180.v:994.5-994.37" + wire $1\main_spi_master_cs_enable[0:0] + attribute \src "ls180.v:990.5-990.33" + wire $1\main_spi_master_cs_re[0:0] + attribute \src "ls180.v:989.5-989.38" + wire $1\main_spi_master_cs_storage[0:0] + attribute \src "ls180.v:970.5-970.33" + wire $1\main_spi_master_done0[0:0] + attribute \src "ls180.v:971.5-971.31" + wire $1\main_spi_master_irq[0:0] + attribute \src "ls180.v:992.5-992.39" + wire $1\main_spi_master_loopback_re[0:0] + attribute \src "ls180.v:991.5-991.44" + wire $1\main_spi_master_loopback_storage[0:0] + attribute \src "ls180.v:973.11-973.38" + wire width 8 $1\main_spi_master_miso[7:0] + attribute \src "ls180.v:1003.11-1003.43" + wire width 8 $1\main_spi_master_miso_data[7:0] + attribute \src "ls180.v:997.5-997.38" + wire $1\main_spi_master_miso_latch[0:0] + attribute \src "ls180.v:1001.11-1001.43" + wire width 8 $1\main_spi_master_mosi_data[7:0] + attribute \src "ls180.v:996.5-996.38" + wire $1\main_spi_master_mosi_latch[0:0] + attribute \src "ls180.v:985.5-985.35" + wire $1\main_spi_master_mosi_re[0:0] + attribute \src "ls180.v:1002.11-1002.42" + wire width 3 $1\main_spi_master_mosi_sel[2:0] + attribute \src "ls180.v:984.11-984.46" + wire width 8 $1\main_spi_master_mosi_storage[7:0] + attribute \src "ls180.v:977.5-977.34" + wire $1\main_spi_master_start1[0:0] + attribute \src "ls180.v:867.11-867.50" + wire width 2 $1\main_uart_eventmanager_pending_w[1:0] + attribute \src "ls180.v:869.5-869.37" + wire $1\main_uart_eventmanager_re[0:0] + attribute \src "ls180.v:863.11-863.49" + wire width 2 $1\main_uart_eventmanager_status_w[1:0] + attribute \src "ls180.v:868.11-868.48" + wire width 2 $1\main_uart_eventmanager_storage[1:0] + attribute \src "ls180.v:835.12-835.54" + wire width 32 $1\main_uart_phy_phase_accumulator_rx[31:0] + attribute \src "ls180.v:825.12-825.54" + wire width 32 $1\main_uart_phy_phase_accumulator_tx[31:0] + attribute \src "ls180.v:818.5-818.28" + wire $1\main_uart_phy_re[0:0] + attribute \src "ls180.v:839.11-839.43" + wire width 4 $1\main_uart_phy_rx_bitcount[3:0] + attribute \src "ls180.v:840.5-840.33" + wire $1\main_uart_phy_rx_busy[0:0] + attribute \src "ls180.v:837.5-837.30" + wire $1\main_uart_phy_rx_r[0:0] + attribute \src "ls180.v:838.11-838.38" + wire width 8 $1\main_uart_phy_rx_reg[7:0] + attribute \src "ls180.v:820.5-820.36" + wire $1\main_uart_phy_sink_ready[0:0] + attribute \src "ls180.v:833.11-833.51" + wire width 8 $1\main_uart_phy_source_payload_data[7:0] + attribute \src "ls180.v:829.5-829.38" + wire $1\main_uart_phy_source_valid[0:0] + attribute \src "ls180.v:817.12-817.47" + wire width 32 $1\main_uart_phy_storage[31:0] + attribute \src "ls180.v:827.11-827.43" + wire width 4 $1\main_uart_phy_tx_bitcount[3:0] + attribute \src "ls180.v:828.5-828.33" + wire $1\main_uart_phy_tx_busy[0:0] + attribute \src "ls180.v:826.11-826.38" + wire width 8 $1\main_uart_phy_tx_reg[7:0] + attribute \src "ls180.v:834.5-834.39" + wire $1\main_uart_phy_uart_clk_rxen[0:0] + attribute \src "ls180.v:824.5-824.39" + wire $1\main_uart_phy_uart_clk_txen[0:0] + attribute \src "ls180.v:858.5-858.30" + wire $1\main_uart_rx_clear[0:0] + attribute \src "ls180.v:942.11-942.43" + wire width 4 $1\main_uart_rx_fifo_consume[3:0] + attribute \src "ls180.v:939.11-939.42" + wire width 5 $1\main_uart_rx_fifo_level0[4:0] + attribute \src "ls180.v:941.11-941.43" + wire width 4 $1\main_uart_rx_fifo_produce[3:0] + attribute \src "ls180.v:932.5-932.38" + wire $1\main_uart_rx_fifo_readable[0:0] + attribute \src "ls180.v:943.11-943.46" + wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:859.5-859.36" + wire $1\main_uart_rx_old_trigger[0:0] + attribute \src "ls180.v:856.5-856.32" + wire $1\main_uart_rx_pending[0:0] + attribute \src "ls180.v:853.5-853.30" + wire $1\main_uart_tx_clear[0:0] + attribute \src "ls180.v:905.11-905.43" + wire width 4 $1\main_uart_tx_fifo_consume[3:0] + attribute \src "ls180.v:902.11-902.42" + wire width 5 $1\main_uart_tx_fifo_level0[4:0] + attribute \src "ls180.v:904.11-904.43" + wire width 4 $1\main_uart_tx_fifo_produce[3:0] + attribute \src "ls180.v:895.5-895.38" + wire $1\main_uart_tx_fifo_readable[0:0] + attribute \src "ls180.v:906.11-906.46" + wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:854.5-854.36" + wire $1\main_uart_tx_old_trigger[0:0] + attribute \src "ls180.v:851.5-851.32" + wire $1\main_uart_tx_pending[0:0] + attribute \src "ls180.v:795.5-795.29" + wire $1\main_wb_sdram_ack[0:0] + attribute \src "ls180.v:813.5-813.31" + wire $1\main_wdata_consumed[0:0] + attribute \src "ls180.v:2799.68-2799.110" + wire $add$ls180.v:2799$22_Y + attribute \src "ls180.v:2859.68-2859.110" + wire $add$ls180.v:2859$33_Y + attribute \src "ls180.v:2919.68-2919.110" + wire $add$ls180.v:2919$44_Y + attribute \src "ls180.v:4052.54-4052.83" + wire $add$ls180.v:4052$537_Y + attribute \src "ls180.v:4152.36-4152.89" + wire width 5 $add$ls180.v:4152$583_Y + attribute \src "ls180.v:4182.36-4182.89" + wire width 5 $add$ls180.v:4182$594_Y + attribute \src "ls180.v:4237.53-4237.81" + wire width 3 $add$ls180.v:4237$607_Y + attribute \src "ls180.v:4341.58-4341.86" + wire width 8 $add$ls180.v:4341$635_Y + attribute \src "ls180.v:4398.58-4398.86" + wire width 8 $add$ls180.v:4398$638_Y + attribute \src "ls180.v:4415.58-4415.86" + wire width 8 $add$ls180.v:4415$640_Y + attribute \src "ls180.v:4508.59-4508.87" + wire width 8 $add$ls180.v:4508$657_Y + attribute \src "ls180.v:4533.59-4533.87" + wire width 8 $add$ls180.v:4533$660_Y + attribute \src "ls180.v:4655.53-4655.82" + wire width 8 $add$ls180.v:4655$677_Y + attribute \src "ls180.v:4766.65-4766.114" + wire width 10 $add$ls180.v:4766$691_Y + attribute \src "ls180.v:4771.62-4771.91" + wire width 10 $add$ls180.v:4771$694_Y + attribute \src "ls180.v:4797.61-4797.90" + wire width 10 $add$ls180.v:4797$697_Y + attribute \src "ls180.v:5001.80-5001.117" + wire width 3 $add$ls180.v:5001$882_Y + attribute \src "ls180.v:5195.54-5195.82" + wire width 3 $add$ls180.v:5195$957_Y + attribute \src "ls180.v:5247.55-5247.84" + wire width 32 $add$ls180.v:5247$967_Y + attribute \src "ls180.v:5273.57-5273.86" + wire width 32 $add$ls180.v:5273$975_Y + attribute \src "ls180.v:5394.51-5394.134" + wire width 32 $add$ls180.v:5394$991_Y + attribute \src "ls180.v:5397.77-5397.125" + wire width 32 $add$ls180.v:5397$993_Y + attribute \src "ls180.v:5490.50-5490.105" + wire width 32 $add$ls180.v:5490$1002_Y + attribute \src "ls180.v:5492.77-5492.111" + wire width 32 $add$ls180.v:5492$1003_Y + attribute \src "ls180.v:5604.49-5604.73" + wire width 3 $add$ls180.v:5604$1022_Y + attribute \src "ls180.v:7483.36-7483.70" + wire width 32 $add$ls180.v:7483$2415_Y + attribute \src "ls180.v:7568.37-7568.72" + wire width 4 $add$ls180.v:7568$2436_Y + attribute \src "ls180.v:7585.60-7585.119" + wire width 3 $add$ls180.v:7585$2440_Y + attribute \src "ls180.v:7588.60-7588.119" + wire width 3 $add$ls180.v:7588$2441_Y + attribute \src "ls180.v:7592.59-7592.116" + wire width 4 $add$ls180.v:7592$2446_Y + attribute \src "ls180.v:7631.60-7631.119" + wire width 3 $add$ls180.v:7631$2456_Y + attribute \src "ls180.v:7634.60-7634.119" + wire width 3 $add$ls180.v:7634$2457_Y + attribute \src "ls180.v:7638.59-7638.116" + wire width 4 $add$ls180.v:7638$2462_Y + attribute \src "ls180.v:7677.60-7677.119" + wire width 3 $add$ls180.v:7677$2472_Y + attribute \src "ls180.v:7680.60-7680.119" + wire width 3 $add$ls180.v:7680$2473_Y + attribute \src "ls180.v:7684.59-7684.116" + wire width 4 $add$ls180.v:7684$2478_Y + attribute \src "ls180.v:7723.60-7723.119" + wire width 3 $add$ls180.v:7723$2488_Y + attribute \src "ls180.v:7726.60-7726.119" + wire width 3 $add$ls180.v:7726$2489_Y + attribute \src "ls180.v:7730.59-7730.116" + wire width 4 $add$ls180.v:7730$2494_Y + attribute \src "ls180.v:7960.34-7960.66" + wire width 4 $add$ls180.v:7960$2548_Y + attribute \src "ls180.v:7976.73-7976.131" + wire width 33 $add$ls180.v:7976$2551_Y + attribute \src "ls180.v:7989.34-7989.66" + wire width 4 $add$ls180.v:7989$2555_Y + attribute \src "ls180.v:8008.73-8008.131" + wire width 33 $add$ls180.v:8008$2558_Y + attribute \src "ls180.v:8034.33-8034.65" + wire width 4 $add$ls180.v:8034$2566_Y + attribute \src "ls180.v:8037.33-8037.65" + wire width 4 $add$ls180.v:8037$2567_Y + attribute \src "ls180.v:8041.33-8041.64" + wire width 5 $add$ls180.v:8041$2572_Y + attribute \src "ls180.v:8056.33-8056.65" + wire width 4 $add$ls180.v:8056$2577_Y + attribute \src "ls180.v:8059.33-8059.65" + wire width 4 $add$ls180.v:8059$2578_Y + attribute \src "ls180.v:8063.33-8063.64" + wire width 5 $add$ls180.v:8063$2583_Y + attribute \src "ls180.v:8084.35-8084.70" + wire width 16 $add$ls180.v:8084$2585_Y + attribute \src "ls180.v:8120.25-8120.49" + wire width 32 $add$ls180.v:8120$2590_Y + attribute \src "ls180.v:8134.25-8134.49" + wire width 32 $add$ls180.v:8134$2594_Y + attribute \src "ls180.v:8148.31-8148.61" + wire width 9 $add$ls180.v:8148$2599_Y + attribute \src "ls180.v:8171.45-8171.88" + wire width 3 $add$ls180.v:8171$2603_Y + attribute \src "ls180.v:8217.71-8217.114" + wire width 4 $add$ls180.v:8217$2609_Y + attribute \src "ls180.v:8252.46-8252.90" + wire width 3 $add$ls180.v:8252$2615_Y + attribute \src "ls180.v:8298.72-8298.116" + wire width 4 $add$ls180.v:8298$2621_Y + attribute \src "ls180.v:8331.47-8331.92" + wire $add$ls180.v:8331$2627_Y + attribute \src "ls180.v:8359.73-8359.118" + wire width 2 $add$ls180.v:8359$2633_Y + attribute \src "ls180.v:8471.39-8471.75" + wire width 4 $add$ls180.v:8471$2646_Y + attribute \src "ls180.v:8532.37-8532.73" + wire width 5 $add$ls180.v:8532$2650_Y + attribute \src "ls180.v:8535.37-8535.73" + wire width 5 $add$ls180.v:8535$2651_Y + attribute \src "ls180.v:8539.36-8539.70" + wire width 6 $add$ls180.v:8539$2656_Y + attribute \src "ls180.v:8554.41-8554.80" + wire width 2 $add$ls180.v:8554$2660_Y + attribute \src "ls180.v:8588.67-8588.106" + wire width 3 $add$ls180.v:8588$2666_Y + attribute \src "ls180.v:8614.39-8614.76" + wire width 2 $add$ls180.v:8614$2668_Y + attribute \src "ls180.v:8618.37-8618.73" + wire width 5 $add$ls180.v:8618$2672_Y + attribute \src "ls180.v:8621.37-8621.73" + wire width 5 $add$ls180.v:8621$2673_Y + attribute \src "ls180.v:8625.36-8625.70" + wire width 6 $add$ls180.v:8625$2678_Y + attribute \src "ls180.v:8632.31-8632.62" + wire width 16 $add$ls180.v:8632$2680_Y + attribute \src "ls180.v:2793.9-2793.80" + wire $and$ls180.v:2793$17_Y + attribute \src "ls180.v:2811.9-2811.80" + wire $and$ls180.v:2811$24_Y + attribute \src "ls180.v:2853.9-2853.80" + wire $and$ls180.v:2853$28_Y + attribute \src "ls180.v:2871.9-2871.80" + wire $and$ls180.v:2871$35_Y + attribute \src "ls180.v:2913.9-2913.86" + wire $and$ls180.v:2913$39_Y + attribute \src "ls180.v:2931.9-2931.86" + wire $and$ls180.v:2931$46_Y + attribute \src "ls180.v:2941.31-2941.90" + wire $and$ls180.v:2941$48_Y + attribute \src "ls180.v:2941.30-2941.121" + wire $and$ls180.v:2941$49_Y + attribute \src "ls180.v:2941.29-2941.156" + wire $and$ls180.v:2941$50_Y + attribute \src "ls180.v:2942.31-2942.90" + wire $and$ls180.v:2942$51_Y + attribute \src "ls180.v:2942.30-2942.121" + wire $and$ls180.v:2942$52_Y + attribute \src "ls180.v:2942.29-2942.156" + wire $and$ls180.v:2942$53_Y + attribute \src "ls180.v:2943.31-2943.90" + wire $and$ls180.v:2943$54_Y + attribute \src "ls180.v:2943.30-2943.121" + wire $and$ls180.v:2943$55_Y + attribute \src "ls180.v:2943.29-2943.156" + wire $and$ls180.v:2943$56_Y + attribute \src "ls180.v:2944.31-2944.90" + wire $and$ls180.v:2944$57_Y + attribute \src "ls180.v:2944.30-2944.121" + wire $and$ls180.v:2944$58_Y + attribute \src "ls180.v:2944.29-2944.156" + wire $and$ls180.v:2944$59_Y + attribute \src "ls180.v:2953.7-2953.89" + wire $and$ls180.v:2953$62_Y + attribute \src "ls180.v:2958.32-2958.111" + wire $and$ls180.v:2958$63_Y + attribute \src "ls180.v:3072.40-3072.99" + wire $and$ls180.v:3072$70_Y + attribute \src "ls180.v:3073.40-3073.99" + wire $and$ls180.v:3073$71_Y + attribute \src "ls180.v:3111.38-3111.103" + wire $and$ls180.v:3111$77_Y + attribute \src "ls180.v:3165.50-3165.119" + wire $and$ls180.v:3165$85_Y + attribute \src "ls180.v:3165.49-3165.167" + wire $and$ls180.v:3165$86_Y + attribute \src "ls180.v:3166.49-3166.118" + wire $and$ls180.v:3166$87_Y + attribute \src "ls180.v:3166.48-3166.154" + wire $and$ls180.v:3166$88_Y + attribute \src "ls180.v:3167.50-3167.119" + wire $and$ls180.v:3167$89_Y + attribute \src "ls180.v:3167.49-3167.155" + wire $and$ls180.v:3167$90_Y + attribute \src "ls180.v:3170.7-3170.114" + wire $and$ls180.v:3170$92_Y + attribute \src "ls180.v:3199.66-3199.246" + wire $and$ls180.v:3199$98_Y + attribute \src "ls180.v:3200.64-3200.187" + wire $and$ls180.v:3200$99_Y + attribute \src "ls180.v:3224.9-3224.86" + wire $and$ls180.v:3224$105_Y + attribute \src "ls180.v:3236.9-3236.86" + wire $and$ls180.v:3236$106_Y + attribute \src "ls180.v:3286.13-3286.87" + wire $and$ls180.v:3286$108_Y + attribute \src "ls180.v:3322.50-3322.119" + wire $and$ls180.v:3322$115_Y + attribute \src "ls180.v:3322.49-3322.167" + wire $and$ls180.v:3322$116_Y + attribute \src "ls180.v:3323.49-3323.118" + wire $and$ls180.v:3323$117_Y + attribute \src "ls180.v:3323.48-3323.154" + wire $and$ls180.v:3323$118_Y + attribute \src "ls180.v:3324.50-3324.119" + wire $and$ls180.v:3324$119_Y + attribute \src "ls180.v:3324.49-3324.155" + wire $and$ls180.v:3324$120_Y + attribute \src "ls180.v:3327.7-3327.114" + wire $and$ls180.v:3327$122_Y + attribute \src "ls180.v:3356.66-3356.246" + wire $and$ls180.v:3356$128_Y + attribute \src "ls180.v:3357.64-3357.187" + wire $and$ls180.v:3357$129_Y + attribute \src "ls180.v:3381.9-3381.86" + wire $and$ls180.v:3381$135_Y + attribute \src "ls180.v:3393.9-3393.86" + wire $and$ls180.v:3393$136_Y + attribute \src "ls180.v:3443.13-3443.87" + wire $and$ls180.v:3443$138_Y + attribute \src "ls180.v:3479.50-3479.119" + wire $and$ls180.v:3479$145_Y + attribute \src "ls180.v:3479.49-3479.167" + wire $and$ls180.v:3479$146_Y + attribute \src "ls180.v:3480.49-3480.118" + wire $and$ls180.v:3480$147_Y + attribute \src "ls180.v:3480.48-3480.154" + wire $and$ls180.v:3480$148_Y + attribute \src "ls180.v:3481.50-3481.119" + wire $and$ls180.v:3481$149_Y + attribute \src "ls180.v:3481.49-3481.155" + wire $and$ls180.v:3481$150_Y + attribute \src "ls180.v:3484.7-3484.114" + wire $and$ls180.v:3484$152_Y + attribute \src "ls180.v:3513.66-3513.246" + wire $and$ls180.v:3513$158_Y + attribute \src "ls180.v:3514.64-3514.187" + wire $and$ls180.v:3514$159_Y + attribute \src "ls180.v:3538.9-3538.86" + wire $and$ls180.v:3538$165_Y + attribute \src "ls180.v:3550.9-3550.86" + wire $and$ls180.v:3550$166_Y + attribute \src "ls180.v:3600.13-3600.87" + wire $and$ls180.v:3600$168_Y + attribute \src "ls180.v:3636.50-3636.119" + wire $and$ls180.v:3636$175_Y + attribute \src "ls180.v:3636.49-3636.167" + wire $and$ls180.v:3636$176_Y + attribute \src "ls180.v:3637.49-3637.118" + wire $and$ls180.v:3637$177_Y + attribute \src "ls180.v:3637.48-3637.154" + wire $and$ls180.v:3637$178_Y + attribute \src "ls180.v:3638.50-3638.119" + wire $and$ls180.v:3638$179_Y + attribute \src "ls180.v:3638.49-3638.155" + wire $and$ls180.v:3638$180_Y + attribute \src "ls180.v:3641.7-3641.114" + wire $and$ls180.v:3641$182_Y + attribute \src "ls180.v:3670.66-3670.246" + wire $and$ls180.v:3670$188_Y + attribute \src "ls180.v:3671.64-3671.187" + wire $and$ls180.v:3671$189_Y + attribute \src "ls180.v:3695.9-3695.86" + wire $and$ls180.v:3695$195_Y + attribute \src "ls180.v:3707.9-3707.86" + wire $and$ls180.v:3707$196_Y + attribute \src "ls180.v:3757.13-3757.87" + wire $and$ls180.v:3757$198_Y + attribute \src "ls180.v:3772.37-3772.102" + wire $and$ls180.v:3772$199_Y + attribute \src "ls180.v:3772.108-3772.188" + wire $and$ls180.v:3772$201_Y + attribute \src "ls180.v:3772.107-3772.231" + wire $and$ls180.v:3772$203_Y + attribute \src "ls180.v:3772.36-3772.232" + wire $and$ls180.v:3772$204_Y + attribute \src "ls180.v:3773.37-3773.102" + wire $and$ls180.v:3773$205_Y + attribute \src "ls180.v:3773.108-3773.188" + wire $and$ls180.v:3773$207_Y + attribute \src "ls180.v:3773.107-3773.231" + wire $and$ls180.v:3773$209_Y + attribute \src "ls180.v:3773.36-3773.232" + wire $and$ls180.v:3773$210_Y + attribute \src "ls180.v:3774.34-3774.85" + wire $and$ls180.v:3774$211_Y + attribute \src "ls180.v:3775.37-3775.102" + wire $and$ls180.v:3775$212_Y + attribute \src "ls180.v:3775.36-3775.194" + wire $and$ls180.v:3775$214_Y + attribute \src "ls180.v:3777.37-3777.102" + wire $and$ls180.v:3777$215_Y + attribute \src "ls180.v:3777.36-3777.148" + wire $and$ls180.v:3777$216_Y + attribute \src "ls180.v:3778.40-3778.119" + wire $and$ls180.v:3778$217_Y + attribute \src "ls180.v:3778.124-3778.203" + wire $and$ls180.v:3778$218_Y + attribute \src "ls180.v:3778.209-3778.288" + wire $and$ls180.v:3778$220_Y + attribute \src "ls180.v:3778.294-3778.373" + wire $and$ls180.v:3778$222_Y + attribute \src "ls180.v:3779.41-3779.121" + wire $and$ls180.v:3779$224_Y + attribute \src "ls180.v:3779.126-3779.206" + wire $and$ls180.v:3779$225_Y + attribute \src "ls180.v:3779.212-3779.292" + wire $and$ls180.v:3779$227_Y + attribute \src "ls180.v:3779.298-3779.378" + wire $and$ls180.v:3779$229_Y + attribute \src "ls180.v:3786.38-3786.111" + wire $and$ls180.v:3786$233_Y + attribute \src "ls180.v:3786.37-3786.150" + wire $and$ls180.v:3786$234_Y + attribute \src "ls180.v:3786.36-3786.189" + wire $and$ls180.v:3786$235_Y + attribute \src "ls180.v:3792.77-3792.153" + wire $and$ls180.v:3792$238_Y + attribute \src "ls180.v:3792.162-3792.246" + wire $and$ls180.v:3792$240_Y + attribute \src "ls180.v:3792.161-3792.291" + wire $and$ls180.v:3792$242_Y + attribute \src "ls180.v:3792.76-3792.333" + wire $and$ls180.v:3792$245_Y + attribute \src "ls180.v:3792.338-3792.505" + wire $and$ls180.v:3792$248_Y + attribute \src "ls180.v:3792.38-3792.507" + wire $and$ls180.v:3792$250_Y + attribute \src "ls180.v:3793.77-3793.153" + wire $and$ls180.v:3793$251_Y + attribute \src "ls180.v:3793.162-3793.246" + wire $and$ls180.v:3793$253_Y + attribute \src "ls180.v:3793.161-3793.291" + wire $and$ls180.v:3793$255_Y + attribute \src "ls180.v:3793.76-3793.333" + wire $and$ls180.v:3793$258_Y + attribute \src "ls180.v:3793.338-3793.505" + wire $and$ls180.v:3793$261_Y + attribute \src "ls180.v:3793.38-3793.507" + wire $and$ls180.v:3793$263_Y + attribute \src "ls180.v:3794.77-3794.153" + wire $and$ls180.v:3794$264_Y + attribute \src "ls180.v:3794.162-3794.246" + wire $and$ls180.v:3794$266_Y + attribute \src "ls180.v:3794.161-3794.291" + wire $and$ls180.v:3794$268_Y + attribute \src "ls180.v:3794.76-3794.333" + wire $and$ls180.v:3794$271_Y + attribute \src "ls180.v:3794.338-3794.505" + wire $and$ls180.v:3794$274_Y + attribute \src "ls180.v:3794.38-3794.507" + wire $and$ls180.v:3794$276_Y + attribute \src "ls180.v:3795.77-3795.153" + wire $and$ls180.v:3795$277_Y + attribute \src "ls180.v:3795.162-3795.246" + wire $and$ls180.v:3795$279_Y + attribute \src "ls180.v:3795.161-3795.291" + wire $and$ls180.v:3795$281_Y + attribute \src "ls180.v:3795.76-3795.333" + wire $and$ls180.v:3795$284_Y + attribute \src "ls180.v:3795.338-3795.505" + wire $and$ls180.v:3795$287_Y + attribute \src "ls180.v:3795.38-3795.507" + wire $and$ls180.v:3795$289_Y + attribute \src "ls180.v:3825.77-3825.153" + wire $and$ls180.v:3825$296_Y + attribute \src "ls180.v:3825.162-3825.246" + wire $and$ls180.v:3825$298_Y + attribute \src "ls180.v:3825.161-3825.291" + wire $and$ls180.v:3825$300_Y + attribute \src "ls180.v:3825.76-3825.333" + wire $and$ls180.v:3825$303_Y + attribute \src "ls180.v:3825.338-3825.505" + wire $and$ls180.v:3825$306_Y + attribute \src "ls180.v:3825.38-3825.507" + wire $and$ls180.v:3825$308_Y + attribute \src "ls180.v:3826.77-3826.153" + wire $and$ls180.v:3826$309_Y + attribute \src "ls180.v:3826.162-3826.246" + wire $and$ls180.v:3826$311_Y + attribute \src "ls180.v:3826.161-3826.291" + wire $and$ls180.v:3826$313_Y + attribute \src "ls180.v:3826.76-3826.333" + wire $and$ls180.v:3826$316_Y + attribute \src "ls180.v:3826.338-3826.505" + wire $and$ls180.v:3826$319_Y + attribute \src "ls180.v:3826.38-3826.507" + wire $and$ls180.v:3826$321_Y + attribute \src "ls180.v:3827.77-3827.153" + wire $and$ls180.v:3827$322_Y + attribute \src "ls180.v:3827.162-3827.246" + wire $and$ls180.v:3827$324_Y + attribute \src "ls180.v:3827.161-3827.291" + wire $and$ls180.v:3827$326_Y + attribute \src "ls180.v:3827.76-3827.333" + wire $and$ls180.v:3827$329_Y + attribute \src "ls180.v:3827.338-3827.505" + wire $and$ls180.v:3827$332_Y + attribute \src "ls180.v:3827.38-3827.507" + wire $and$ls180.v:3827$334_Y + attribute \src "ls180.v:3828.77-3828.153" + wire $and$ls180.v:3828$335_Y + attribute \src "ls180.v:3828.162-3828.246" + wire $and$ls180.v:3828$337_Y + attribute \src "ls180.v:3828.161-3828.291" + wire $and$ls180.v:3828$339_Y + attribute \src "ls180.v:3828.76-3828.333" + wire $and$ls180.v:3828$342_Y + attribute \src "ls180.v:3828.338-3828.505" + wire $and$ls180.v:3828$345_Y + attribute \src "ls180.v:3828.38-3828.507" + wire $and$ls180.v:3828$347_Y + attribute \src "ls180.v:3857.8-3857.73" + wire $and$ls180.v:3857$352_Y + attribute \src "ls180.v:3857.7-3857.114" + wire $and$ls180.v:3857$354_Y + attribute \src "ls180.v:3860.8-3860.73" + wire $and$ls180.v:3860$355_Y + attribute \src "ls180.v:3860.7-3860.114" + wire $and$ls180.v:3860$357_Y + attribute \src "ls180.v:3866.8-3866.73" + wire $and$ls180.v:3866$359_Y + attribute \src "ls180.v:3866.7-3866.114" + wire $and$ls180.v:3866$361_Y + attribute \src "ls180.v:3869.8-3869.73" + wire $and$ls180.v:3869$362_Y + attribute \src "ls180.v:3869.7-3869.114" + wire $and$ls180.v:3869$364_Y + attribute \src "ls180.v:3875.8-3875.73" + wire $and$ls180.v:3875$366_Y + attribute \src "ls180.v:3875.7-3875.114" + wire $and$ls180.v:3875$368_Y + attribute \src "ls180.v:3878.8-3878.73" + wire $and$ls180.v:3878$369_Y + attribute \src "ls180.v:3878.7-3878.114" + wire $and$ls180.v:3878$371_Y + attribute \src "ls180.v:3884.8-3884.73" + wire $and$ls180.v:3884$373_Y + attribute \src "ls180.v:3884.7-3884.114" + wire $and$ls180.v:3884$375_Y + attribute \src "ls180.v:3887.8-3887.73" + wire $and$ls180.v:3887$376_Y + attribute \src "ls180.v:3887.7-3887.114" + wire $and$ls180.v:3887$378_Y + attribute \src "ls180.v:3912.71-3912.151" + wire $and$ls180.v:3912$383_Y + attribute \src "ls180.v:3912.70-3912.194" + wire $and$ls180.v:3912$385_Y + attribute \src "ls180.v:3912.41-3912.222" + wire $and$ls180.v:3912$388_Y + attribute \src "ls180.v:3950.71-3950.151" + wire $and$ls180.v:3950$392_Y + attribute \src "ls180.v:3950.70-3950.194" + wire $and$ls180.v:3950$394_Y + attribute \src "ls180.v:3950.41-3950.222" + wire $and$ls180.v:3950$397_Y + attribute \src "ls180.v:3968.110-3968.179" + wire $and$ls180.v:3968$402_Y + attribute \src "ls180.v:3968.185-3968.254" + wire $and$ls180.v:3968$405_Y + attribute \src "ls180.v:3968.260-3968.329" + wire $and$ls180.v:3968$408_Y + attribute \src "ls180.v:3968.41-3968.332" + wire $and$ls180.v:3968$411_Y + attribute \src "ls180.v:3968.40-3968.355" + wire $and$ls180.v:3968$412_Y + attribute \src "ls180.v:3969.34-3969.106" + wire $and$ls180.v:3969$415_Y + attribute \src "ls180.v:3973.110-3973.179" + wire $and$ls180.v:3973$418_Y + attribute \src "ls180.v:3973.185-3973.254" + wire $and$ls180.v:3973$421_Y + attribute \src "ls180.v:3973.260-3973.329" + wire $and$ls180.v:3973$424_Y + attribute \src "ls180.v:3973.41-3973.332" + wire $and$ls180.v:3973$427_Y + attribute \src "ls180.v:3973.40-3973.355" + wire $and$ls180.v:3973$428_Y + attribute \src "ls180.v:3974.34-3974.106" + wire $and$ls180.v:3974$431_Y + attribute \src "ls180.v:3978.110-3978.179" + wire $and$ls180.v:3978$434_Y + attribute \src "ls180.v:3978.185-3978.254" + wire $and$ls180.v:3978$437_Y + attribute \src "ls180.v:3978.260-3978.329" + wire $and$ls180.v:3978$440_Y + attribute \src "ls180.v:3978.41-3978.332" + wire $and$ls180.v:3978$443_Y + attribute \src "ls180.v:3978.40-3978.355" + wire $and$ls180.v:3978$444_Y + attribute \src "ls180.v:3979.34-3979.106" + wire $and$ls180.v:3979$447_Y + attribute \src "ls180.v:3983.110-3983.179" + wire $and$ls180.v:3983$450_Y + attribute \src "ls180.v:3983.185-3983.254" + wire $and$ls180.v:3983$453_Y + attribute \src "ls180.v:3983.260-3983.329" + wire $and$ls180.v:3983$456_Y + attribute \src "ls180.v:3983.41-3983.332" + wire $and$ls180.v:3983$459_Y + attribute \src "ls180.v:3983.40-3983.355" + wire $and$ls180.v:3983$460_Y + attribute \src "ls180.v:3984.34-3984.106" + wire $and$ls180.v:3984$463_Y + attribute \src "ls180.v:3988.151-3988.220" + wire $and$ls180.v:3988$467_Y + attribute \src "ls180.v:3988.226-3988.295" + wire $and$ls180.v:3988$470_Y + attribute \src "ls180.v:3988.301-3988.370" + wire $and$ls180.v:3988$473_Y + attribute \src "ls180.v:3988.82-3988.373" + wire $and$ls180.v:3988$476_Y + attribute \src "ls180.v:3988.43-3988.374" + wire $and$ls180.v:3988$477_Y + attribute \src "ls180.v:3988.42-3988.410" + wire $and$ls180.v:3988$478_Y + attribute \src "ls180.v:3988.525-3988.594" + wire $and$ls180.v:3988$483_Y + attribute \src "ls180.v:3988.600-3988.669" + wire $and$ls180.v:3988$486_Y + attribute \src "ls180.v:3988.675-3988.744" + wire $and$ls180.v:3988$489_Y + attribute \src "ls180.v:3988.456-3988.747" + wire $and$ls180.v:3988$492_Y + attribute \src "ls180.v:3988.417-3988.748" + wire $and$ls180.v:3988$493_Y + attribute \src "ls180.v:3988.416-3988.784" + wire $and$ls180.v:3988$494_Y + attribute \src "ls180.v:3988.899-3988.968" + wire $and$ls180.v:3988$499_Y + attribute \src "ls180.v:3988.974-3988.1043" + wire $and$ls180.v:3988$502_Y + attribute \src "ls180.v:3988.1049-3988.1118" + wire $and$ls180.v:3988$505_Y + attribute \src "ls180.v:3988.830-3988.1121" + wire $and$ls180.v:3988$508_Y + attribute \src "ls180.v:3988.791-3988.1122" + wire $and$ls180.v:3988$509_Y + attribute \src "ls180.v:3988.790-3988.1158" + wire $and$ls180.v:3988$510_Y + attribute \src "ls180.v:3988.1273-3988.1342" + wire $and$ls180.v:3988$515_Y + attribute \src "ls180.v:3988.1348-3988.1417" + wire $and$ls180.v:3988$518_Y + attribute \src "ls180.v:3988.1423-3988.1492" + wire $and$ls180.v:3988$521_Y + attribute \src "ls180.v:3988.1204-3988.1495" + wire $and$ls180.v:3988$524_Y + attribute \src "ls180.v:3988.1165-3988.1496" + wire $and$ls180.v:3988$525_Y + attribute \src "ls180.v:3988.1164-3988.1532" + wire $and$ls180.v:3988$526_Y + attribute \src "ls180.v:4046.9-4046.46" + wire $and$ls180.v:4046$532_Y + attribute \src "ls180.v:4064.9-4064.46" + wire $and$ls180.v:4064$539_Y + attribute \src "ls180.v:4077.32-4077.75" + wire $and$ls180.v:4077$543_Y + attribute \src "ls180.v:4077.31-4077.99" + wire $and$ls180.v:4077$545_Y + attribute \src "ls180.v:4078.34-4078.102" + wire $and$ls180.v:4078$547_Y + attribute \src "ls180.v:4078.33-4078.128" + wire $and$ls180.v:4078$549_Y + attribute \src "ls180.v:4079.33-4079.104" + wire $and$ls180.v:4079$552_Y + attribute \src "ls180.v:4080.49-4080.85" + wire $and$ls180.v:4080$553_Y + attribute \src "ls180.v:4080.90-4080.129" + wire $and$ls180.v:4080$555_Y + attribute \src "ls180.v:4080.32-4080.131" + wire $and$ls180.v:4080$557_Y + attribute \src "ls180.v:4081.25-4081.66" + wire $and$ls180.v:4081$558_Y + attribute \src "ls180.v:4082.27-4082.72" + wire $and$ls180.v:4082$560_Y + attribute \src "ls180.v:4083.26-4083.71" + wire $and$ls180.v:4083$562_Y + attribute \src "ls180.v:4112.64-4112.88" + wire $and$ls180.v:4112$568_Y + attribute \src "ls180.v:4116.7-4116.78" + wire $and$ls180.v:4116$572_Y + attribute \src "ls180.v:4127.7-4127.78" + wire $and$ls180.v:4127$575_Y + attribute \src "ls180.v:4136.26-4136.97" + wire $and$ls180.v:4136$577_Y + attribute \src "ls180.v:4136.102-4136.173" + wire $and$ls180.v:4136$578_Y + attribute \src "ls180.v:4151.41-4151.133" + wire $and$ls180.v:4151$582_Y + attribute \src "ls180.v:4162.39-4162.136" + wire $and$ls180.v:4162$587_Y + attribute \src "ls180.v:4163.37-4163.104" + wire $and$ls180.v:4163$588_Y + attribute \src "ls180.v:4181.41-4181.133" + wire $and$ls180.v:4181$593_Y + attribute \src "ls180.v:4192.39-4192.136" + wire $and$ls180.v:4192$598_Y + attribute \src "ls180.v:4193.37-4193.104" + wire $and$ls180.v:4193$599_Y + attribute \src "ls180.v:4322.33-4322.86" + wire $and$ls180.v:4322$633_Y + attribute \src "ls180.v:4426.9-4426.68" + wire $and$ls180.v:4426$642_Y + attribute \src "ls180.v:4446.53-4446.145" + wire $and$ls180.v:4446$645_Y + attribute \src "ls180.v:4465.52-4465.137" + wire $and$ls180.v:4465$648_Y + attribute \src "ls180.v:4506.9-4506.68" + wire $and$ls180.v:4506$656_Y + attribute \src "ls180.v:4544.9-4544.68" + wire $and$ls180.v:4544$662_Y + attribute \src "ls180.v:4553.10-4553.69" + wire $and$ls180.v:4553$663_Y + attribute \src "ls180.v:4553.9-4553.93" + wire $and$ls180.v:4553$664_Y + attribute \src "ls180.v:4573.54-4573.117" + wire $and$ls180.v:4573$666_Y + attribute \src "ls180.v:4592.53-4592.140" + wire $and$ls180.v:4592$669_Y + attribute \src "ls180.v:4689.9-4689.70" + wire $and$ls180.v:4689$679_Y + attribute \src "ls180.v:4707.55-4707.120" + wire $and$ls180.v:4707$681_Y + attribute \src "ls180.v:4726.54-4726.143" + wire $and$ls180.v:4726$684_Y + attribute \src "ls180.v:4808.9-4808.70" + wire $and$ls180.v:4808$699_Y + attribute \src "ls180.v:4815.9-4815.70" + wire $and$ls180.v:4815$700_Y + attribute \src "ls180.v:4896.48-4896.124" + wire $and$ls180.v:4896$823_Y + attribute \src "ls180.v:4896.47-4896.165" + wire $and$ls180.v:4896$824_Y + attribute \src "ls180.v:4897.50-4897.127" + wire $and$ls180.v:4897$825_Y + attribute \src "ls180.v:4899.48-4899.124" + wire $and$ls180.v:4899$826_Y + attribute \src "ls180.v:4899.47-4899.165" + wire $and$ls180.v:4899$827_Y + attribute \src "ls180.v:4900.50-4900.127" + wire $and$ls180.v:4900$828_Y + attribute \src "ls180.v:4902.48-4902.124" + wire $and$ls180.v:4902$829_Y + attribute \src "ls180.v:4902.47-4902.165" + wire $and$ls180.v:4902$830_Y + attribute \src "ls180.v:4903.50-4903.127" + wire $and$ls180.v:4903$831_Y + attribute \src "ls180.v:4905.48-4905.124" + wire $and$ls180.v:4905$832_Y + attribute \src "ls180.v:4905.47-4905.165" + wire $and$ls180.v:4905$833_Y + attribute \src "ls180.v:4906.50-4906.127" + wire $and$ls180.v:4906$834_Y + attribute \src "ls180.v:5019.10-5019.86" + wire $and$ls180.v:5019$883_Y + attribute \src "ls180.v:5019.9-5019.127" + wire $and$ls180.v:5019$884_Y + attribute \src "ls180.v:5029.9-5029.152" + wire $and$ls180.v:5029$888_Y + attribute \src "ls180.v:5029.8-5029.226" + wire $and$ls180.v:5029$890_Y + attribute \src "ls180.v:5029.7-5029.300" + wire $and$ls180.v:5029$892_Y + attribute \src "ls180.v:5034.49-5034.124" + wire $and$ls180.v:5034$893_Y + attribute \src "ls180.v:5044.49-5044.124" + wire $and$ls180.v:5044$896_Y + attribute \src "ls180.v:5054.49-5054.124" + wire $and$ls180.v:5054$899_Y + attribute \src "ls180.v:5064.49-5064.124" + wire $and$ls180.v:5064$902_Y + attribute \src "ls180.v:5076.7-5076.84" + wire $and$ls180.v:5076$907_Y + attribute \src "ls180.v:5194.9-5194.64" + wire $and$ls180.v:5194$956_Y + attribute \src "ls180.v:5246.10-5246.66" + wire $and$ls180.v:5246$965_Y + attribute \src "ls180.v:5246.9-5246.97" + wire $and$ls180.v:5246$966_Y + attribute \src "ls180.v:5272.11-5272.71" + wire $and$ls180.v:5272$974_Y + attribute \src "ls180.v:5356.43-5356.152" + wire $and$ls180.v:5356$982_Y + attribute \src "ls180.v:5357.41-5357.116" + wire $and$ls180.v:5357$983_Y + attribute \src "ls180.v:5369.48-5369.125" + wire $and$ls180.v:5369$988_Y + attribute \src "ls180.v:5396.9-5396.102" + wire $and$ls180.v:5396$992_Y + attribute \src "ls180.v:5469.9-5469.58" + wire $and$ls180.v:5469$998_Y + attribute \src "ls180.v:5522.51-5522.123" + wire $and$ls180.v:5522$1006_Y + attribute \src "ls180.v:5523.50-5523.120" + wire $and$ls180.v:5523$1007_Y + attribute \src "ls180.v:5524.49-5524.122" + wire $and$ls180.v:5524$1008_Y + attribute \src "ls180.v:5564.43-5564.152" + wire $and$ls180.v:5564$1013_Y + attribute \src "ls180.v:5565.41-5565.116" + wire $and$ls180.v:5565$1014_Y + attribute \src "ls180.v:5656.9-5656.76" + wire $and$ls180.v:5656$1026_Y + attribute \src "ls180.v:5659.44-5659.120" + wire $and$ls180.v:5659$1028_Y + attribute \src "ls180.v:5679.63-5679.107" + wire $and$ls180.v:5679$1030_Y + attribute \src "ls180.v:5680.63-5680.107" + wire $and$ls180.v:5680$1032_Y + attribute \src "ls180.v:5681.63-5681.107" + wire $and$ls180.v:5681$1034_Y + attribute \src "ls180.v:5682.35-5682.79" + wire $and$ls180.v:5682$1036_Y + attribute \src "ls180.v:5683.35-5683.79" + wire $and$ls180.v:5683$1038_Y + attribute \src "ls180.v:5684.63-5684.107" + wire $and$ls180.v:5684$1040_Y + attribute \src "ls180.v:5685.63-5685.107" + wire $and$ls180.v:5685$1042_Y + attribute \src "ls180.v:5686.63-5686.107" + wire $and$ls180.v:5686$1044_Y + attribute \src "ls180.v:5687.35-5687.79" + wire $and$ls180.v:5687$1046_Y + attribute \src "ls180.v:5688.35-5688.79" + wire $and$ls180.v:5688$1048_Y + attribute \src "ls180.v:5733.40-5733.81" + wire $and$ls180.v:5733$1055_Y + attribute \src "ls180.v:5734.50-5734.91" + wire $and$ls180.v:5734$1056_Y + attribute \src "ls180.v:5735.50-5735.91" + wire $and$ls180.v:5735$1057_Y + attribute \src "ls180.v:5736.29-5736.70" + wire $and$ls180.v:5736$1058_Y + attribute \src "ls180.v:5737.44-5737.85" + wire $and$ls180.v:5737$1059_Y + attribute \src "ls180.v:5739.25-5739.64" + wire $and$ls180.v:5739$1064_Y + attribute \src "ls180.v:5739.24-5739.89" + wire $and$ls180.v:5739$1066_Y + attribute \src "ls180.v:5745.31-5745.92" + wire width 32 $and$ls180.v:5745$1072_Y + attribute \src "ls180.v:5745.97-5745.168" + wire width 32 $and$ls180.v:5745$1073_Y + attribute \src "ls180.v:5745.174-5745.245" + wire width 32 $and$ls180.v:5745$1075_Y + attribute \src "ls180.v:5745.251-5745.301" + wire width 32 $and$ls180.v:5745$1077_Y + attribute \src "ls180.v:5745.307-5745.372" + wire width 32 $and$ls180.v:5745$1079_Y + attribute \src "ls180.v:5755.39-5755.92" + wire $and$ls180.v:5755$1083_Y + attribute \src "ls180.v:5755.38-5755.142" + wire $and$ls180.v:5755$1085_Y + attribute \src "ls180.v:5756.39-5756.95" + wire $and$ls180.v:5756$1087_Y + attribute \src "ls180.v:5756.38-5756.145" + wire $and$ls180.v:5756$1089_Y + attribute \src "ls180.v:5758.41-5758.94" + wire $and$ls180.v:5758$1090_Y + attribute \src "ls180.v:5758.40-5758.144" + wire $and$ls180.v:5758$1092_Y + attribute \src "ls180.v:5759.41-5759.97" + wire $and$ls180.v:5759$1094_Y + attribute \src "ls180.v:5759.40-5759.147" + wire $and$ls180.v:5759$1096_Y + attribute \src "ls180.v:5761.41-5761.94" + wire $and$ls180.v:5761$1097_Y + attribute \src "ls180.v:5761.40-5761.144" + wire $and$ls180.v:5761$1099_Y + attribute \src "ls180.v:5762.41-5762.97" + wire $and$ls180.v:5762$1101_Y + attribute \src "ls180.v:5762.40-5762.147" + wire $and$ls180.v:5762$1103_Y + attribute \src "ls180.v:5764.41-5764.94" + wire $and$ls180.v:5764$1104_Y + attribute \src "ls180.v:5764.40-5764.144" + wire $and$ls180.v:5764$1106_Y + attribute \src "ls180.v:5765.41-5765.97" + wire $and$ls180.v:5765$1108_Y + attribute \src "ls180.v:5765.40-5765.147" + wire $and$ls180.v:5765$1110_Y + attribute \src "ls180.v:5767.41-5767.94" + wire $and$ls180.v:5767$1111_Y + attribute \src "ls180.v:5767.40-5767.144" + wire $and$ls180.v:5767$1113_Y + attribute \src "ls180.v:5768.41-5768.97" + wire $and$ls180.v:5768$1115_Y + attribute \src "ls180.v:5768.40-5768.147" + wire $and$ls180.v:5768$1117_Y + attribute \src "ls180.v:5770.44-5770.97" + wire $and$ls180.v:5770$1118_Y + attribute \src "ls180.v:5770.43-5770.147" + wire $and$ls180.v:5770$1120_Y + attribute \src "ls180.v:5771.44-5771.100" + wire $and$ls180.v:5771$1122_Y + attribute \src "ls180.v:5771.43-5771.150" + wire $and$ls180.v:5771$1124_Y + attribute \src "ls180.v:5773.44-5773.97" + wire $and$ls180.v:5773$1125_Y + attribute \src "ls180.v:5773.43-5773.147" + wire $and$ls180.v:5773$1127_Y + attribute \src "ls180.v:5774.44-5774.100" + wire $and$ls180.v:5774$1129_Y + attribute \src "ls180.v:5774.43-5774.150" + wire $and$ls180.v:5774$1131_Y + attribute \src "ls180.v:5776.44-5776.97" + wire $and$ls180.v:5776$1132_Y + attribute \src "ls180.v:5776.43-5776.147" + wire $and$ls180.v:5776$1134_Y + attribute \src "ls180.v:5777.44-5777.100" + wire $and$ls180.v:5777$1136_Y + attribute \src "ls180.v:5777.43-5777.150" + wire $and$ls180.v:5777$1138_Y + attribute \src "ls180.v:5779.44-5779.97" + wire $and$ls180.v:5779$1139_Y + attribute \src "ls180.v:5779.43-5779.147" + wire $and$ls180.v:5779$1141_Y + attribute \src "ls180.v:5780.44-5780.100" + wire $and$ls180.v:5780$1143_Y + attribute \src "ls180.v:5780.43-5780.150" + wire $and$ls180.v:5780$1145_Y + attribute \src "ls180.v:5793.36-5793.89" + wire $and$ls180.v:5793$1147_Y + attribute \src "ls180.v:5793.35-5793.139" + wire $and$ls180.v:5793$1149_Y + attribute \src "ls180.v:5794.36-5794.92" + wire $and$ls180.v:5794$1151_Y + attribute \src "ls180.v:5794.35-5794.142" + wire $and$ls180.v:5794$1153_Y + attribute \src "ls180.v:5796.36-5796.89" + wire $and$ls180.v:5796$1154_Y + attribute \src "ls180.v:5796.35-5796.139" + wire $and$ls180.v:5796$1156_Y + attribute \src "ls180.v:5797.36-5797.92" + wire $and$ls180.v:5797$1158_Y + attribute \src "ls180.v:5797.35-5797.142" + wire $and$ls180.v:5797$1160_Y + attribute \src "ls180.v:5799.36-5799.89" + wire $and$ls180.v:5799$1161_Y + attribute \src "ls180.v:5799.35-5799.139" + wire $and$ls180.v:5799$1163_Y + attribute \src "ls180.v:5800.36-5800.92" + wire $and$ls180.v:5800$1165_Y + attribute \src "ls180.v:5800.35-5800.142" + wire $and$ls180.v:5800$1167_Y + attribute \src "ls180.v:5802.36-5802.89" + wire $and$ls180.v:5802$1168_Y + attribute \src "ls180.v:5802.35-5802.139" + wire $and$ls180.v:5802$1170_Y + attribute \src "ls180.v:5803.36-5803.92" + wire $and$ls180.v:5803$1172_Y + attribute \src "ls180.v:5803.35-5803.142" + wire $and$ls180.v:5803$1174_Y + attribute \src "ls180.v:5805.37-5805.90" + wire $and$ls180.v:5805$1175_Y + attribute \src "ls180.v:5805.36-5805.140" + wire $and$ls180.v:5805$1177_Y + attribute \src "ls180.v:5806.37-5806.93" + wire $and$ls180.v:5806$1179_Y + attribute \src "ls180.v:5806.36-5806.143" + wire $and$ls180.v:5806$1181_Y + attribute \src "ls180.v:5808.37-5808.90" + wire $and$ls180.v:5808$1182_Y + attribute \src "ls180.v:5808.36-5808.140" + wire $and$ls180.v:5808$1184_Y + attribute \src "ls180.v:5809.37-5809.93" + wire $and$ls180.v:5809$1186_Y + attribute \src "ls180.v:5809.36-5809.143" + wire $and$ls180.v:5809$1188_Y + attribute \src "ls180.v:5819.35-5819.88" + wire $and$ls180.v:5819$1190_Y + attribute \src "ls180.v:5819.34-5819.136" + wire $and$ls180.v:5819$1192_Y + attribute \src "ls180.v:5820.35-5820.91" + wire $and$ls180.v:5820$1194_Y + attribute \src "ls180.v:5820.34-5820.139" + wire $and$ls180.v:5820$1196_Y + attribute \src "ls180.v:5822.34-5822.87" + wire $and$ls180.v:5822$1197_Y + attribute \src "ls180.v:5822.33-5822.135" + wire $and$ls180.v:5822$1199_Y + attribute \src "ls180.v:5823.34-5823.90" + wire $and$ls180.v:5823$1201_Y + attribute \src "ls180.v:5823.33-5823.138" + wire $and$ls180.v:5823$1203_Y + attribute \src "ls180.v:5833.40-5833.93" + wire $and$ls180.v:5833$1205_Y + attribute \src "ls180.v:5833.39-5833.143" + wire $and$ls180.v:5833$1207_Y + attribute \src "ls180.v:5834.40-5834.96" + wire $and$ls180.v:5834$1209_Y + attribute \src "ls180.v:5834.39-5834.146" + wire $and$ls180.v:5834$1211_Y + attribute \src "ls180.v:5836.39-5836.92" + wire $and$ls180.v:5836$1212_Y + attribute \src "ls180.v:5836.38-5836.142" + wire $and$ls180.v:5836$1214_Y + attribute \src "ls180.v:5837.39-5837.95" + wire $and$ls180.v:5837$1216_Y + attribute \src "ls180.v:5837.38-5837.145" + wire $and$ls180.v:5837$1218_Y + attribute \src "ls180.v:5839.39-5839.92" + wire $and$ls180.v:5839$1219_Y + attribute \src "ls180.v:5839.38-5839.142" + wire $and$ls180.v:5839$1221_Y + attribute \src "ls180.v:5840.39-5840.95" + wire $and$ls180.v:5840$1223_Y + attribute \src "ls180.v:5840.38-5840.145" + wire $and$ls180.v:5840$1225_Y + attribute \src "ls180.v:5842.39-5842.92" + wire $and$ls180.v:5842$1226_Y + attribute \src "ls180.v:5842.38-5842.142" + wire $and$ls180.v:5842$1228_Y + attribute \src "ls180.v:5843.39-5843.95" + wire $and$ls180.v:5843$1230_Y + attribute \src "ls180.v:5843.38-5843.145" + wire $and$ls180.v:5843$1232_Y + attribute \src "ls180.v:5845.39-5845.92" + wire $and$ls180.v:5845$1233_Y + attribute \src "ls180.v:5845.38-5845.142" + wire $and$ls180.v:5845$1235_Y + attribute \src "ls180.v:5846.39-5846.95" + wire $and$ls180.v:5846$1237_Y + attribute \src "ls180.v:5846.38-5846.145" + wire $and$ls180.v:5846$1239_Y + attribute \src "ls180.v:5848.40-5848.93" + wire $and$ls180.v:5848$1240_Y + attribute \src "ls180.v:5848.39-5848.143" + wire $and$ls180.v:5848$1242_Y + attribute \src "ls180.v:5849.40-5849.96" + wire $and$ls180.v:5849$1244_Y + attribute \src "ls180.v:5849.39-5849.146" + wire $and$ls180.v:5849$1246_Y + attribute \src "ls180.v:5851.40-5851.93" + wire $and$ls180.v:5851$1247_Y + attribute \src "ls180.v:5851.39-5851.143" + wire $and$ls180.v:5851$1249_Y + attribute \src "ls180.v:5852.40-5852.96" + wire $and$ls180.v:5852$1251_Y + attribute \src "ls180.v:5852.39-5852.146" + wire $and$ls180.v:5852$1253_Y + attribute \src "ls180.v:5854.40-5854.93" + wire $and$ls180.v:5854$1254_Y + attribute \src "ls180.v:5854.39-5854.143" + wire $and$ls180.v:5854$1256_Y + attribute \src "ls180.v:5855.40-5855.96" + wire $and$ls180.v:5855$1258_Y + attribute \src "ls180.v:5855.39-5855.146" + wire $and$ls180.v:5855$1260_Y + attribute \src "ls180.v:5857.40-5857.93" + wire $and$ls180.v:5857$1261_Y + attribute \src "ls180.v:5857.39-5857.143" + wire $and$ls180.v:5857$1263_Y + attribute \src "ls180.v:5858.40-5858.96" + wire $and$ls180.v:5858$1265_Y + attribute \src "ls180.v:5858.39-5858.146" + wire $and$ls180.v:5858$1267_Y + attribute \src "ls180.v:5870.40-5870.93" + wire $and$ls180.v:5870$1269_Y + attribute \src "ls180.v:5870.39-5870.143" + wire $and$ls180.v:5870$1271_Y + attribute \src "ls180.v:5871.40-5871.96" + wire $and$ls180.v:5871$1273_Y + attribute \src "ls180.v:5871.39-5871.146" + wire $and$ls180.v:5871$1275_Y + attribute \src "ls180.v:5873.39-5873.92" + wire $and$ls180.v:5873$1276_Y + attribute \src "ls180.v:5873.38-5873.142" + wire $and$ls180.v:5873$1278_Y + attribute \src "ls180.v:5874.39-5874.95" + wire $and$ls180.v:5874$1280_Y + attribute \src "ls180.v:5874.38-5874.145" + wire $and$ls180.v:5874$1282_Y + attribute \src "ls180.v:5876.39-5876.92" + wire $and$ls180.v:5876$1283_Y + attribute \src "ls180.v:5876.38-5876.142" + wire $and$ls180.v:5876$1285_Y + attribute \src "ls180.v:5877.39-5877.95" + wire $and$ls180.v:5877$1287_Y + attribute \src "ls180.v:5877.38-5877.145" + wire $and$ls180.v:5877$1289_Y + attribute \src "ls180.v:5879.39-5879.92" + wire $and$ls180.v:5879$1290_Y + attribute \src "ls180.v:5879.38-5879.142" + wire $and$ls180.v:5879$1292_Y + attribute \src "ls180.v:5880.39-5880.95" + wire $and$ls180.v:5880$1294_Y + attribute \src "ls180.v:5880.38-5880.145" + wire $and$ls180.v:5880$1296_Y + attribute \src "ls180.v:5882.39-5882.92" + wire $and$ls180.v:5882$1297_Y + attribute \src "ls180.v:5882.38-5882.142" + wire $and$ls180.v:5882$1299_Y + attribute \src "ls180.v:5883.39-5883.95" + wire $and$ls180.v:5883$1301_Y + attribute \src "ls180.v:5883.38-5883.145" + wire $and$ls180.v:5883$1303_Y + attribute \src "ls180.v:5885.40-5885.93" + wire $and$ls180.v:5885$1304_Y + attribute \src "ls180.v:5885.39-5885.143" + wire $and$ls180.v:5885$1306_Y + attribute \src "ls180.v:5886.40-5886.96" + wire $and$ls180.v:5886$1308_Y + attribute \src "ls180.v:5886.39-5886.146" + wire $and$ls180.v:5886$1310_Y + attribute \src "ls180.v:5888.40-5888.93" + wire $and$ls180.v:5888$1311_Y + attribute \src "ls180.v:5888.39-5888.143" + wire $and$ls180.v:5888$1313_Y + attribute \src "ls180.v:5889.40-5889.96" + wire $and$ls180.v:5889$1315_Y + attribute \src "ls180.v:5889.39-5889.146" + wire $and$ls180.v:5889$1317_Y + attribute \src "ls180.v:5891.40-5891.93" + wire $and$ls180.v:5891$1318_Y + attribute \src "ls180.v:5891.39-5891.143" + wire $and$ls180.v:5891$1320_Y + attribute \src "ls180.v:5892.40-5892.96" + wire $and$ls180.v:5892$1322_Y + attribute \src "ls180.v:5892.39-5892.146" + wire $and$ls180.v:5892$1324_Y + attribute \src "ls180.v:5894.40-5894.93" + wire $and$ls180.v:5894$1325_Y + attribute \src "ls180.v:5894.39-5894.143" + wire $and$ls180.v:5894$1327_Y + attribute \src "ls180.v:5895.40-5895.96" + wire $and$ls180.v:5895$1329_Y + attribute \src "ls180.v:5895.39-5895.146" + wire $and$ls180.v:5895$1331_Y + attribute \src "ls180.v:5907.42-5907.95" + wire $and$ls180.v:5907$1333_Y + attribute \src "ls180.v:5907.41-5907.145" + wire $and$ls180.v:5907$1335_Y + attribute \src "ls180.v:5908.42-5908.98" + wire $and$ls180.v:5908$1337_Y + attribute \src "ls180.v:5908.41-5908.148" + wire $and$ls180.v:5908$1339_Y + attribute \src "ls180.v:5910.42-5910.95" + wire $and$ls180.v:5910$1340_Y + attribute \src "ls180.v:5910.41-5910.145" + wire $and$ls180.v:5910$1342_Y + attribute \src "ls180.v:5911.42-5911.98" + wire $and$ls180.v:5911$1344_Y + attribute \src "ls180.v:5911.41-5911.148" + wire $and$ls180.v:5911$1346_Y + attribute \src "ls180.v:5913.42-5913.95" + wire $and$ls180.v:5913$1347_Y + attribute \src "ls180.v:5913.41-5913.145" + wire $and$ls180.v:5913$1349_Y + attribute \src "ls180.v:5914.42-5914.98" + wire $and$ls180.v:5914$1351_Y + attribute \src "ls180.v:5914.41-5914.148" + wire $and$ls180.v:5914$1353_Y + attribute \src "ls180.v:5916.42-5916.95" + wire $and$ls180.v:5916$1354_Y + attribute \src "ls180.v:5916.41-5916.145" + wire $and$ls180.v:5916$1356_Y + attribute \src "ls180.v:5917.42-5917.98" + wire $and$ls180.v:5917$1358_Y + attribute \src "ls180.v:5917.41-5917.148" + wire $and$ls180.v:5917$1360_Y + attribute \src "ls180.v:5919.42-5919.95" + wire $and$ls180.v:5919$1361_Y + attribute \src "ls180.v:5919.41-5919.145" + wire $and$ls180.v:5919$1363_Y + attribute \src "ls180.v:5920.42-5920.98" + wire $and$ls180.v:5920$1365_Y + attribute \src "ls180.v:5920.41-5920.148" + wire $and$ls180.v:5920$1367_Y + attribute \src "ls180.v:5922.42-5922.95" + wire $and$ls180.v:5922$1368_Y + attribute \src "ls180.v:5922.41-5922.145" + wire $and$ls180.v:5922$1370_Y + attribute \src "ls180.v:5923.42-5923.98" + wire $and$ls180.v:5923$1372_Y + attribute \src "ls180.v:5923.41-5923.148" + wire $and$ls180.v:5923$1374_Y + attribute \src "ls180.v:5925.42-5925.95" + wire $and$ls180.v:5925$1375_Y + attribute \src "ls180.v:5925.41-5925.145" + wire $and$ls180.v:5925$1377_Y + attribute \src "ls180.v:5926.42-5926.98" + wire $and$ls180.v:5926$1379_Y + attribute \src "ls180.v:5926.41-5926.148" + wire $and$ls180.v:5926$1381_Y + attribute \src "ls180.v:5928.42-5928.95" + wire $and$ls180.v:5928$1382_Y + attribute \src "ls180.v:5928.41-5928.145" + wire $and$ls180.v:5928$1384_Y + attribute \src "ls180.v:5929.42-5929.98" + wire $and$ls180.v:5929$1386_Y + attribute \src "ls180.v:5929.41-5929.148" + wire $and$ls180.v:5929$1388_Y + attribute \src "ls180.v:5931.44-5931.97" + wire $and$ls180.v:5931$1389_Y + attribute \src "ls180.v:5931.43-5931.147" + wire $and$ls180.v:5931$1391_Y + attribute \src "ls180.v:5932.44-5932.100" + wire $and$ls180.v:5932$1393_Y + attribute \src "ls180.v:5932.43-5932.150" + wire $and$ls180.v:5932$1395_Y + attribute \src "ls180.v:5934.44-5934.97" + wire $and$ls180.v:5934$1396_Y + attribute \src "ls180.v:5934.43-5934.147" + wire $and$ls180.v:5934$1398_Y + attribute \src "ls180.v:5935.44-5935.100" + wire $and$ls180.v:5935$1400_Y + attribute \src "ls180.v:5935.43-5935.150" + wire $and$ls180.v:5935$1402_Y + attribute \src "ls180.v:5937.44-5937.97" + wire $and$ls180.v:5937$1403_Y + attribute \src "ls180.v:5937.43-5937.148" + wire $and$ls180.v:5937$1405_Y + attribute \src "ls180.v:5938.44-5938.100" + wire $and$ls180.v:5938$1407_Y + attribute \src "ls180.v:5938.43-5938.151" + wire $and$ls180.v:5938$1409_Y + attribute \src "ls180.v:5940.44-5940.97" + wire $and$ls180.v:5940$1410_Y + attribute \src "ls180.v:5940.43-5940.148" + wire $and$ls180.v:5940$1412_Y + attribute \src "ls180.v:5941.44-5941.100" + wire $and$ls180.v:5941$1414_Y + attribute \src "ls180.v:5941.43-5941.151" + wire $and$ls180.v:5941$1416_Y + attribute \src "ls180.v:5943.44-5943.97" + wire $and$ls180.v:5943$1417_Y + attribute \src "ls180.v:5943.43-5943.148" + wire $and$ls180.v:5943$1419_Y + attribute \src "ls180.v:5944.44-5944.100" + wire $and$ls180.v:5944$1421_Y + attribute \src "ls180.v:5944.43-5944.151" + wire $and$ls180.v:5944$1423_Y + attribute \src "ls180.v:5946.41-5946.94" + wire $and$ls180.v:5946$1424_Y + attribute \src "ls180.v:5946.40-5946.145" + wire $and$ls180.v:5946$1426_Y + attribute \src "ls180.v:5947.41-5947.97" + wire $and$ls180.v:5947$1428_Y + attribute \src "ls180.v:5947.40-5947.148" + wire $and$ls180.v:5947$1430_Y + attribute \src "ls180.v:5949.42-5949.95" + wire $and$ls180.v:5949$1431_Y + attribute \src "ls180.v:5949.41-5949.146" + wire $and$ls180.v:5949$1433_Y + attribute \src "ls180.v:5950.42-5950.98" + wire $and$ls180.v:5950$1435_Y + attribute \src "ls180.v:5950.41-5950.149" + wire $and$ls180.v:5950$1437_Y + attribute \src "ls180.v:5969.46-5969.99" + wire $and$ls180.v:5969$1439_Y + attribute \src "ls180.v:5969.45-5969.149" + wire $and$ls180.v:5969$1441_Y + attribute \src "ls180.v:5970.46-5970.102" + wire $and$ls180.v:5970$1443_Y + attribute \src "ls180.v:5970.45-5970.152" + wire $and$ls180.v:5970$1445_Y + attribute \src "ls180.v:5972.46-5972.99" + wire $and$ls180.v:5972$1446_Y + attribute \src "ls180.v:5972.45-5972.149" + wire $and$ls180.v:5972$1448_Y + attribute \src "ls180.v:5973.46-5973.102" + wire $and$ls180.v:5973$1450_Y + attribute \src "ls180.v:5973.45-5973.152" + wire $and$ls180.v:5973$1452_Y + attribute \src "ls180.v:5975.46-5975.99" + wire $and$ls180.v:5975$1453_Y + attribute \src "ls180.v:5975.45-5975.149" + wire $and$ls180.v:5975$1455_Y + attribute \src "ls180.v:5976.46-5976.102" + wire $and$ls180.v:5976$1457_Y + attribute \src "ls180.v:5976.45-5976.152" + wire $and$ls180.v:5976$1459_Y + attribute \src "ls180.v:5978.46-5978.99" + wire $and$ls180.v:5978$1460_Y + attribute \src "ls180.v:5978.45-5978.149" + wire $and$ls180.v:5978$1462_Y + attribute \src "ls180.v:5979.46-5979.102" + wire $and$ls180.v:5979$1464_Y + attribute \src "ls180.v:5979.45-5979.152" + wire $and$ls180.v:5979$1466_Y + attribute \src "ls180.v:5981.45-5981.98" + wire $and$ls180.v:5981$1467_Y + attribute \src "ls180.v:5981.44-5981.148" + wire $and$ls180.v:5981$1469_Y + attribute \src "ls180.v:5982.45-5982.101" + wire $and$ls180.v:5982$1471_Y + attribute \src "ls180.v:5982.44-5982.151" + wire $and$ls180.v:5982$1473_Y + attribute \src "ls180.v:5984.45-5984.98" + wire $and$ls180.v:5984$1474_Y + attribute \src "ls180.v:5984.44-5984.148" + wire $and$ls180.v:5984$1476_Y + attribute \src "ls180.v:5985.45-5985.101" + wire $and$ls180.v:5985$1478_Y + attribute \src "ls180.v:5985.44-5985.151" + wire $and$ls180.v:5985$1480_Y + attribute \src "ls180.v:5987.45-5987.98" + wire $and$ls180.v:5987$1481_Y + attribute \src "ls180.v:5987.44-5987.148" + wire $and$ls180.v:5987$1483_Y + attribute \src "ls180.v:5988.45-5988.101" + wire $and$ls180.v:5988$1485_Y + attribute \src "ls180.v:5988.44-5988.151" + wire $and$ls180.v:5988$1487_Y + attribute \src "ls180.v:5990.45-5990.98" + wire $and$ls180.v:5990$1488_Y + attribute \src "ls180.v:5990.44-5990.148" + wire $and$ls180.v:5990$1490_Y + attribute \src "ls180.v:5991.45-5991.101" + wire $and$ls180.v:5991$1492_Y + attribute \src "ls180.v:5991.44-5991.151" + wire $and$ls180.v:5991$1494_Y + attribute \src "ls180.v:5993.36-5993.89" + wire $and$ls180.v:5993$1495_Y + attribute \src "ls180.v:5993.35-5993.139" + wire $and$ls180.v:5993$1497_Y + attribute \src "ls180.v:5994.36-5994.92" + wire $and$ls180.v:5994$1499_Y + attribute \src "ls180.v:5994.35-5994.142" + wire $and$ls180.v:5994$1501_Y + attribute \src "ls180.v:5996.47-5996.100" + wire $and$ls180.v:5996$1502_Y + attribute \src "ls180.v:5996.46-5996.150" + wire $and$ls180.v:5996$1504_Y + attribute \src "ls180.v:5997.47-5997.103" + wire $and$ls180.v:5997$1506_Y + attribute \src "ls180.v:5997.46-5997.153" + wire $and$ls180.v:5997$1508_Y + attribute \src "ls180.v:5999.47-5999.100" + wire $and$ls180.v:5999$1509_Y + attribute \src "ls180.v:5999.46-5999.151" + wire $and$ls180.v:5999$1511_Y + attribute \src "ls180.v:6000.47-6000.103" + wire $and$ls180.v:6000$1513_Y + attribute \src "ls180.v:6000.46-6000.154" + wire $and$ls180.v:6000$1515_Y + attribute \src "ls180.v:6002.47-6002.100" + wire $and$ls180.v:6002$1516_Y + attribute \src "ls180.v:6002.46-6002.151" + wire $and$ls180.v:6002$1518_Y + attribute \src "ls180.v:6003.47-6003.103" + wire $and$ls180.v:6003$1520_Y + attribute \src "ls180.v:6003.46-6003.154" + wire $and$ls180.v:6003$1522_Y + attribute \src "ls180.v:6005.47-6005.100" + wire $and$ls180.v:6005$1523_Y + attribute \src "ls180.v:6005.46-6005.151" + wire $and$ls180.v:6005$1525_Y + attribute \src "ls180.v:6006.47-6006.103" + wire $and$ls180.v:6006$1527_Y + attribute \src "ls180.v:6006.46-6006.154" + wire $and$ls180.v:6006$1529_Y + attribute \src "ls180.v:6008.47-6008.100" + wire $and$ls180.v:6008$1530_Y + attribute \src "ls180.v:6008.46-6008.151" + wire $and$ls180.v:6008$1532_Y + attribute \src "ls180.v:6009.47-6009.103" + wire $and$ls180.v:6009$1534_Y + attribute \src "ls180.v:6009.46-6009.154" + wire $and$ls180.v:6009$1536_Y + attribute \src "ls180.v:6011.47-6011.100" + wire $and$ls180.v:6011$1537_Y + attribute \src "ls180.v:6011.46-6011.151" + wire $and$ls180.v:6011$1539_Y + attribute \src "ls180.v:6012.47-6012.103" + wire $and$ls180.v:6012$1541_Y + attribute \src "ls180.v:6012.46-6012.154" + wire $and$ls180.v:6012$1543_Y + attribute \src "ls180.v:6014.46-6014.99" + wire $and$ls180.v:6014$1544_Y + attribute \src "ls180.v:6014.45-6014.150" + wire $and$ls180.v:6014$1546_Y + attribute \src "ls180.v:6015.46-6015.102" + wire $and$ls180.v:6015$1548_Y + attribute \src "ls180.v:6015.45-6015.153" + wire $and$ls180.v:6015$1550_Y + attribute \src "ls180.v:6017.46-6017.99" + wire $and$ls180.v:6017$1551_Y + attribute \src "ls180.v:6017.45-6017.150" + wire $and$ls180.v:6017$1553_Y + attribute \src "ls180.v:6018.46-6018.102" + wire $and$ls180.v:6018$1555_Y + attribute \src "ls180.v:6018.45-6018.153" + wire $and$ls180.v:6018$1557_Y + attribute \src "ls180.v:6020.46-6020.99" + wire $and$ls180.v:6020$1558_Y + attribute \src "ls180.v:6020.45-6020.150" + wire $and$ls180.v:6020$1560_Y + attribute \src "ls180.v:6021.46-6021.102" + wire $and$ls180.v:6021$1562_Y + attribute \src "ls180.v:6021.45-6021.153" + wire $and$ls180.v:6021$1564_Y + attribute \src "ls180.v:6023.46-6023.99" + wire $and$ls180.v:6023$1565_Y + attribute \src "ls180.v:6023.45-6023.150" + wire $and$ls180.v:6023$1567_Y + attribute \src "ls180.v:6024.46-6024.102" + wire $and$ls180.v:6024$1569_Y + attribute \src "ls180.v:6024.45-6024.153" + wire $and$ls180.v:6024$1571_Y + attribute \src "ls180.v:6026.46-6026.99" + wire $and$ls180.v:6026$1572_Y + attribute \src "ls180.v:6026.45-6026.150" + wire $and$ls180.v:6026$1574_Y + attribute \src "ls180.v:6027.46-6027.102" + wire $and$ls180.v:6027$1576_Y + attribute \src "ls180.v:6027.45-6027.153" + wire $and$ls180.v:6027$1578_Y + attribute \src "ls180.v:6029.46-6029.99" + wire $and$ls180.v:6029$1579_Y + attribute \src "ls180.v:6029.45-6029.150" + wire $and$ls180.v:6029$1581_Y + attribute \src "ls180.v:6030.46-6030.102" + wire $and$ls180.v:6030$1583_Y + attribute \src "ls180.v:6030.45-6030.153" + wire $and$ls180.v:6030$1585_Y + attribute \src "ls180.v:6032.46-6032.99" + wire $and$ls180.v:6032$1586_Y + attribute \src "ls180.v:6032.45-6032.150" + wire $and$ls180.v:6032$1588_Y + attribute \src "ls180.v:6033.46-6033.102" + wire $and$ls180.v:6033$1590_Y + attribute \src "ls180.v:6033.45-6033.153" + wire $and$ls180.v:6033$1592_Y + attribute \src "ls180.v:6035.46-6035.99" + wire $and$ls180.v:6035$1593_Y + attribute \src "ls180.v:6035.45-6035.150" + wire $and$ls180.v:6035$1595_Y + attribute \src "ls180.v:6036.46-6036.102" + wire $and$ls180.v:6036$1597_Y + attribute \src "ls180.v:6036.45-6036.153" + wire $and$ls180.v:6036$1599_Y + attribute \src "ls180.v:6038.46-6038.99" + wire $and$ls180.v:6038$1600_Y + attribute \src "ls180.v:6038.45-6038.150" + wire $and$ls180.v:6038$1602_Y + attribute \src "ls180.v:6039.46-6039.102" + wire $and$ls180.v:6039$1604_Y + attribute \src "ls180.v:6039.45-6039.153" + wire $and$ls180.v:6039$1606_Y + attribute \src "ls180.v:6041.46-6041.99" + wire $and$ls180.v:6041$1607_Y + attribute \src "ls180.v:6041.45-6041.150" + wire $and$ls180.v:6041$1609_Y + attribute \src "ls180.v:6042.46-6042.102" + wire $and$ls180.v:6042$1611_Y + attribute \src "ls180.v:6042.45-6042.153" + wire $and$ls180.v:6042$1613_Y + attribute \src "ls180.v:6044.42-6044.95" + wire $and$ls180.v:6044$1614_Y + attribute \src "ls180.v:6044.41-6044.146" + wire $and$ls180.v:6044$1616_Y + attribute \src "ls180.v:6045.42-6045.98" + wire $and$ls180.v:6045$1618_Y + attribute \src "ls180.v:6045.41-6045.149" + wire $and$ls180.v:6045$1620_Y + attribute \src "ls180.v:6047.43-6047.96" + wire $and$ls180.v:6047$1621_Y + attribute \src "ls180.v:6047.42-6047.147" + wire $and$ls180.v:6047$1623_Y + attribute \src "ls180.v:6048.43-6048.99" + wire $and$ls180.v:6048$1625_Y + attribute \src "ls180.v:6048.42-6048.150" + wire $and$ls180.v:6048$1627_Y + attribute \src "ls180.v:6050.46-6050.99" + wire $and$ls180.v:6050$1628_Y + attribute \src "ls180.v:6050.45-6050.150" + wire $and$ls180.v:6050$1630_Y + attribute \src "ls180.v:6051.46-6051.102" + wire $and$ls180.v:6051$1632_Y + attribute \src "ls180.v:6051.45-6051.153" + wire $and$ls180.v:6051$1634_Y + attribute \src "ls180.v:6053.46-6053.99" + wire $and$ls180.v:6053$1635_Y + attribute \src "ls180.v:6053.45-6053.150" + wire $and$ls180.v:6053$1637_Y + attribute \src "ls180.v:6054.46-6054.102" + wire $and$ls180.v:6054$1639_Y + attribute \src "ls180.v:6054.45-6054.153" + wire $and$ls180.v:6054$1641_Y + attribute \src "ls180.v:6056.45-6056.98" + wire $and$ls180.v:6056$1642_Y + attribute \src "ls180.v:6056.44-6056.149" + wire $and$ls180.v:6056$1644_Y + attribute \src "ls180.v:6057.45-6057.101" + wire $and$ls180.v:6057$1646_Y + attribute \src "ls180.v:6057.44-6057.152" + wire $and$ls180.v:6057$1648_Y + attribute \src "ls180.v:6059.45-6059.98" + wire $and$ls180.v:6059$1649_Y + attribute \src "ls180.v:6059.44-6059.149" + wire $and$ls180.v:6059$1651_Y + attribute \src "ls180.v:6060.45-6060.101" + wire $and$ls180.v:6060$1653_Y + attribute \src "ls180.v:6060.44-6060.152" + wire $and$ls180.v:6060$1655_Y + attribute \src "ls180.v:6062.45-6062.98" + wire $and$ls180.v:6062$1656_Y + attribute \src "ls180.v:6062.44-6062.149" + wire $and$ls180.v:6062$1658_Y + attribute \src "ls180.v:6063.45-6063.101" + wire $and$ls180.v:6063$1660_Y + attribute \src "ls180.v:6063.44-6063.152" + wire $and$ls180.v:6063$1662_Y + attribute \src "ls180.v:6065.45-6065.98" + wire $and$ls180.v:6065$1663_Y + attribute \src "ls180.v:6065.44-6065.149" + wire $and$ls180.v:6065$1665_Y + attribute \src "ls180.v:6066.45-6066.101" + wire $and$ls180.v:6066$1667_Y + attribute \src "ls180.v:6066.44-6066.152" + wire $and$ls180.v:6066$1669_Y + attribute \src "ls180.v:6104.42-6104.95" + wire $and$ls180.v:6104$1671_Y + attribute \src "ls180.v:6104.41-6104.145" + wire $and$ls180.v:6104$1673_Y + attribute \src "ls180.v:6105.42-6105.98" + wire $and$ls180.v:6105$1675_Y + attribute \src "ls180.v:6105.41-6105.148" + wire $and$ls180.v:6105$1677_Y + attribute \src "ls180.v:6107.42-6107.95" + wire $and$ls180.v:6107$1678_Y + attribute \src "ls180.v:6107.41-6107.145" + wire $and$ls180.v:6107$1680_Y + attribute \src "ls180.v:6108.42-6108.98" + wire $and$ls180.v:6108$1682_Y + attribute \src "ls180.v:6108.41-6108.148" + wire $and$ls180.v:6108$1684_Y + attribute \src "ls180.v:6110.42-6110.95" + wire $and$ls180.v:6110$1685_Y + attribute \src "ls180.v:6110.41-6110.145" + wire $and$ls180.v:6110$1687_Y + attribute \src "ls180.v:6111.42-6111.98" + wire $and$ls180.v:6111$1689_Y + attribute \src "ls180.v:6111.41-6111.148" + wire $and$ls180.v:6111$1691_Y + attribute \src "ls180.v:6113.42-6113.95" + wire $and$ls180.v:6113$1692_Y + attribute \src "ls180.v:6113.41-6113.145" + wire $and$ls180.v:6113$1694_Y + attribute \src "ls180.v:6114.42-6114.98" + wire $and$ls180.v:6114$1696_Y + attribute \src "ls180.v:6114.41-6114.148" + wire $and$ls180.v:6114$1698_Y + attribute \src "ls180.v:6116.42-6116.95" + wire $and$ls180.v:6116$1699_Y + attribute \src "ls180.v:6116.41-6116.145" + wire $and$ls180.v:6116$1701_Y + attribute \src "ls180.v:6117.42-6117.98" + wire $and$ls180.v:6117$1703_Y + attribute \src "ls180.v:6117.41-6117.148" + wire $and$ls180.v:6117$1705_Y + attribute \src "ls180.v:6119.42-6119.95" + wire $and$ls180.v:6119$1706_Y + attribute \src "ls180.v:6119.41-6119.145" + wire $and$ls180.v:6119$1708_Y + attribute \src "ls180.v:6120.42-6120.98" + wire $and$ls180.v:6120$1710_Y + attribute \src "ls180.v:6120.41-6120.148" + wire $and$ls180.v:6120$1712_Y + attribute \src "ls180.v:6122.42-6122.95" + wire $and$ls180.v:6122$1713_Y + attribute \src "ls180.v:6122.41-6122.145" + wire $and$ls180.v:6122$1715_Y + attribute \src "ls180.v:6123.42-6123.98" + wire $and$ls180.v:6123$1717_Y + attribute \src "ls180.v:6123.41-6123.148" + wire $and$ls180.v:6123$1719_Y + attribute \src "ls180.v:6125.42-6125.95" + wire $and$ls180.v:6125$1720_Y + attribute \src "ls180.v:6125.41-6125.145" + wire $and$ls180.v:6125$1722_Y + attribute \src "ls180.v:6126.42-6126.98" + wire $and$ls180.v:6126$1724_Y + attribute \src "ls180.v:6126.41-6126.148" + wire $and$ls180.v:6126$1726_Y + attribute \src "ls180.v:6128.44-6128.97" + wire $and$ls180.v:6128$1727_Y + attribute \src "ls180.v:6128.43-6128.147" + wire $and$ls180.v:6128$1729_Y + attribute \src "ls180.v:6129.44-6129.100" + wire $and$ls180.v:6129$1731_Y + attribute \src "ls180.v:6129.43-6129.150" + wire $and$ls180.v:6129$1733_Y + attribute \src "ls180.v:6131.44-6131.97" + wire $and$ls180.v:6131$1734_Y + attribute \src "ls180.v:6131.43-6131.147" + wire $and$ls180.v:6131$1736_Y + attribute \src "ls180.v:6132.44-6132.100" + wire $and$ls180.v:6132$1738_Y + attribute \src "ls180.v:6132.43-6132.150" + wire $and$ls180.v:6132$1740_Y + attribute \src "ls180.v:6134.44-6134.97" + wire $and$ls180.v:6134$1741_Y + attribute \src "ls180.v:6134.43-6134.148" + wire $and$ls180.v:6134$1743_Y + attribute \src "ls180.v:6135.44-6135.100" + wire $and$ls180.v:6135$1745_Y + attribute \src "ls180.v:6135.43-6135.151" + wire $and$ls180.v:6135$1747_Y + attribute \src "ls180.v:6137.44-6137.97" + wire $and$ls180.v:6137$1748_Y + attribute \src "ls180.v:6137.43-6137.148" + wire $and$ls180.v:6137$1750_Y + attribute \src "ls180.v:6138.44-6138.100" + wire $and$ls180.v:6138$1752_Y + attribute \src "ls180.v:6138.43-6138.151" + wire $and$ls180.v:6138$1754_Y + attribute \src "ls180.v:6140.44-6140.97" + wire $and$ls180.v:6140$1755_Y + attribute \src "ls180.v:6140.43-6140.148" + wire $and$ls180.v:6140$1757_Y + attribute \src "ls180.v:6141.44-6141.100" + wire $and$ls180.v:6141$1759_Y + attribute \src "ls180.v:6141.43-6141.151" + wire $and$ls180.v:6141$1761_Y + attribute \src "ls180.v:6143.41-6143.94" + wire $and$ls180.v:6143$1762_Y + attribute \src "ls180.v:6143.40-6143.145" + wire $and$ls180.v:6143$1764_Y + attribute \src "ls180.v:6144.41-6144.97" + wire $and$ls180.v:6144$1766_Y + attribute \src "ls180.v:6144.40-6144.148" + wire $and$ls180.v:6144$1768_Y + attribute \src "ls180.v:6146.42-6146.95" + wire $and$ls180.v:6146$1769_Y + attribute \src "ls180.v:6146.41-6146.146" + wire $and$ls180.v:6146$1771_Y + attribute \src "ls180.v:6147.42-6147.98" + wire $and$ls180.v:6147$1773_Y + attribute \src "ls180.v:6147.41-6147.149" + wire $and$ls180.v:6147$1775_Y + attribute \src "ls180.v:6149.44-6149.97" + wire $and$ls180.v:6149$1776_Y + attribute \src "ls180.v:6149.43-6149.148" + wire $and$ls180.v:6149$1778_Y + attribute \src "ls180.v:6150.44-6150.100" + wire $and$ls180.v:6150$1780_Y + attribute \src "ls180.v:6150.43-6150.151" + wire $and$ls180.v:6150$1782_Y + attribute \src "ls180.v:6152.44-6152.97" + wire $and$ls180.v:6152$1783_Y + attribute \src "ls180.v:6152.43-6152.148" + wire $and$ls180.v:6152$1785_Y + attribute \src "ls180.v:6153.44-6153.100" + wire $and$ls180.v:6153$1787_Y + attribute \src "ls180.v:6153.43-6153.151" + wire $and$ls180.v:6153$1789_Y + attribute \src "ls180.v:6155.44-6155.97" + wire $and$ls180.v:6155$1790_Y + attribute \src "ls180.v:6155.43-6155.148" + wire $and$ls180.v:6155$1792_Y + attribute \src "ls180.v:6156.44-6156.100" + wire $and$ls180.v:6156$1794_Y + attribute \src "ls180.v:6156.43-6156.151" + wire $and$ls180.v:6156$1796_Y + attribute \src "ls180.v:6158.44-6158.97" + wire $and$ls180.v:6158$1797_Y + attribute \src "ls180.v:6158.43-6158.148" + wire $and$ls180.v:6158$1799_Y + attribute \src "ls180.v:6159.44-6159.100" + wire $and$ls180.v:6159$1801_Y + attribute \src "ls180.v:6159.43-6159.151" + wire $and$ls180.v:6159$1803_Y + attribute \src "ls180.v:6183.44-6183.97" + wire $and$ls180.v:6183$1805_Y + attribute \src "ls180.v:6183.43-6183.147" + wire $and$ls180.v:6183$1807_Y + attribute \src "ls180.v:6184.44-6184.100" + wire $and$ls180.v:6184$1809_Y + attribute \src "ls180.v:6184.43-6184.150" + wire $and$ls180.v:6184$1811_Y + attribute \src "ls180.v:6186.49-6186.102" + wire $and$ls180.v:6186$1812_Y + attribute \src "ls180.v:6186.48-6186.152" + wire $and$ls180.v:6186$1814_Y + attribute \src "ls180.v:6187.49-6187.105" + wire $and$ls180.v:6187$1816_Y + attribute \src "ls180.v:6187.48-6187.155" + wire $and$ls180.v:6187$1818_Y + attribute \src "ls180.v:6189.49-6189.102" + wire $and$ls180.v:6189$1819_Y + attribute \src "ls180.v:6189.48-6189.152" + wire $and$ls180.v:6189$1821_Y + attribute \src "ls180.v:6190.49-6190.105" + wire $and$ls180.v:6190$1823_Y + attribute \src "ls180.v:6190.48-6190.155" + wire $and$ls180.v:6190$1825_Y + attribute \src "ls180.v:6192.42-6192.95" + wire $and$ls180.v:6192$1826_Y + attribute \src "ls180.v:6192.41-6192.145" + wire $and$ls180.v:6192$1828_Y + attribute \src "ls180.v:6193.42-6193.98" + wire $and$ls180.v:6193$1830_Y + attribute \src "ls180.v:6193.41-6193.148" + wire $and$ls180.v:6193$1832_Y + attribute \src "ls180.v:6200.46-6200.99" + wire $and$ls180.v:6200$1834_Y + attribute \src "ls180.v:6200.45-6200.149" + wire $and$ls180.v:6200$1836_Y + attribute \src "ls180.v:6201.46-6201.102" + wire $and$ls180.v:6201$1838_Y + attribute \src "ls180.v:6201.45-6201.152" + wire $and$ls180.v:6201$1840_Y + attribute \src "ls180.v:6203.50-6203.103" + wire $and$ls180.v:6203$1841_Y + attribute \src "ls180.v:6203.49-6203.153" + wire $and$ls180.v:6203$1843_Y + attribute \src "ls180.v:6204.50-6204.106" + wire $and$ls180.v:6204$1845_Y + attribute \src "ls180.v:6204.49-6204.156" + wire $and$ls180.v:6204$1847_Y + attribute \src "ls180.v:6206.40-6206.93" + wire $and$ls180.v:6206$1848_Y + attribute \src "ls180.v:6206.39-6206.143" + wire $and$ls180.v:6206$1850_Y + attribute \src "ls180.v:6207.40-6207.96" + wire $and$ls180.v:6207$1852_Y + attribute \src "ls180.v:6207.39-6207.146" + wire $and$ls180.v:6207$1854_Y + attribute \src "ls180.v:6209.50-6209.103" + wire $and$ls180.v:6209$1855_Y + attribute \src "ls180.v:6209.49-6209.153" + wire $and$ls180.v:6209$1857_Y + attribute \src "ls180.v:6210.50-6210.106" + wire $and$ls180.v:6210$1859_Y + attribute \src "ls180.v:6210.49-6210.156" + wire $and$ls180.v:6210$1861_Y + attribute \src "ls180.v:6212.50-6212.103" + wire $and$ls180.v:6212$1862_Y + attribute \src "ls180.v:6212.49-6212.153" + wire $and$ls180.v:6212$1864_Y + attribute \src "ls180.v:6213.50-6213.106" + wire $and$ls180.v:6213$1866_Y + attribute \src "ls180.v:6213.49-6213.156" + wire $and$ls180.v:6213$1868_Y + attribute \src "ls180.v:6215.51-6215.104" + wire $and$ls180.v:6215$1869_Y + attribute \src "ls180.v:6215.50-6215.154" + wire $and$ls180.v:6215$1871_Y + attribute \src "ls180.v:6216.51-6216.107" + wire $and$ls180.v:6216$1873_Y + attribute \src "ls180.v:6216.50-6216.157" + wire $and$ls180.v:6216$1875_Y + attribute \src "ls180.v:6218.49-6218.102" + wire $and$ls180.v:6218$1876_Y + attribute \src "ls180.v:6218.48-6218.152" + wire $and$ls180.v:6218$1878_Y + attribute \src "ls180.v:6219.49-6219.105" + wire $and$ls180.v:6219$1880_Y + attribute \src "ls180.v:6219.48-6219.155" + wire $and$ls180.v:6219$1882_Y + attribute \src "ls180.v:6221.49-6221.102" + wire $and$ls180.v:6221$1883_Y + attribute \src "ls180.v:6221.48-6221.152" + wire $and$ls180.v:6221$1885_Y + attribute \src "ls180.v:6222.49-6222.105" + wire $and$ls180.v:6222$1887_Y + attribute \src "ls180.v:6222.48-6222.155" + wire $and$ls180.v:6222$1889_Y + attribute \src "ls180.v:6224.49-6224.102" + wire $and$ls180.v:6224$1890_Y + attribute \src "ls180.v:6224.48-6224.152" + wire $and$ls180.v:6224$1892_Y + attribute \src "ls180.v:6225.49-6225.105" + wire $and$ls180.v:6225$1894_Y + attribute \src "ls180.v:6225.48-6225.155" + wire $and$ls180.v:6225$1896_Y + attribute \src "ls180.v:6227.49-6227.102" + wire $and$ls180.v:6227$1897_Y + attribute \src "ls180.v:6227.48-6227.152" + wire $and$ls180.v:6227$1899_Y + attribute \src "ls180.v:6228.49-6228.105" + wire $and$ls180.v:6228$1901_Y + attribute \src "ls180.v:6228.48-6228.155" + wire $and$ls180.v:6228$1903_Y + attribute \src "ls180.v:6245.42-6245.97" + wire $and$ls180.v:6245$1905_Y + attribute \src "ls180.v:6245.41-6245.148" + wire $and$ls180.v:6245$1907_Y + attribute \src "ls180.v:6246.42-6246.100" + wire $and$ls180.v:6246$1909_Y + attribute \src "ls180.v:6246.41-6246.151" + wire $and$ls180.v:6246$1911_Y + attribute \src "ls180.v:6248.42-6248.97" + wire $and$ls180.v:6248$1912_Y + attribute \src "ls180.v:6248.41-6248.148" + wire $and$ls180.v:6248$1914_Y + attribute \src "ls180.v:6249.42-6249.100" + wire $and$ls180.v:6249$1916_Y + attribute \src "ls180.v:6249.41-6249.151" + wire $and$ls180.v:6249$1918_Y + attribute \src "ls180.v:6251.40-6251.95" + wire $and$ls180.v:6251$1919_Y + attribute \src "ls180.v:6251.39-6251.146" + wire $and$ls180.v:6251$1921_Y + attribute \src "ls180.v:6252.40-6252.98" + wire $and$ls180.v:6252$1923_Y + attribute \src "ls180.v:6252.39-6252.149" + wire $and$ls180.v:6252$1925_Y + attribute \src "ls180.v:6254.39-6254.94" + wire $and$ls180.v:6254$1926_Y + attribute \src "ls180.v:6254.38-6254.145" + wire $and$ls180.v:6254$1928_Y + attribute \src "ls180.v:6255.39-6255.97" + wire $and$ls180.v:6255$1930_Y + attribute \src "ls180.v:6255.38-6255.148" + wire $and$ls180.v:6255$1932_Y + attribute \src "ls180.v:6257.38-6257.93" + wire $and$ls180.v:6257$1933_Y + attribute \src "ls180.v:6257.37-6257.144" + wire $and$ls180.v:6257$1935_Y + attribute \src "ls180.v:6258.38-6258.96" + wire $and$ls180.v:6258$1937_Y + attribute \src "ls180.v:6258.37-6258.147" + wire $and$ls180.v:6258$1939_Y + attribute \src "ls180.v:6260.37-6260.92" + wire $and$ls180.v:6260$1940_Y + attribute \src "ls180.v:6260.36-6260.143" + wire $and$ls180.v:6260$1942_Y + attribute \src "ls180.v:6261.37-6261.95" + wire $and$ls180.v:6261$1944_Y + attribute \src "ls180.v:6261.36-6261.146" + wire $and$ls180.v:6261$1946_Y + attribute \src "ls180.v:6263.43-6263.98" + wire $and$ls180.v:6263$1947_Y + attribute \src "ls180.v:6263.42-6263.149" + wire $and$ls180.v:6263$1949_Y + attribute \src "ls180.v:6264.43-6264.101" + wire $and$ls180.v:6264$1951_Y + attribute \src "ls180.v:6264.42-6264.152" + wire $and$ls180.v:6264$1953_Y + attribute \src "ls180.v:6285.42-6285.97" + wire $and$ls180.v:6285$1956_Y + attribute \src "ls180.v:6285.41-6285.148" + wire $and$ls180.v:6285$1958_Y + attribute \src "ls180.v:6286.42-6286.100" + wire $and$ls180.v:6286$1960_Y + attribute \src "ls180.v:6286.41-6286.151" + wire $and$ls180.v:6286$1962_Y + attribute \src "ls180.v:6288.42-6288.97" + wire $and$ls180.v:6288$1963_Y + attribute \src "ls180.v:6288.41-6288.148" + wire $and$ls180.v:6288$1965_Y + attribute \src "ls180.v:6289.42-6289.100" + wire $and$ls180.v:6289$1967_Y + attribute \src "ls180.v:6289.41-6289.151" + wire $and$ls180.v:6289$1969_Y + attribute \src "ls180.v:6291.40-6291.95" + wire $and$ls180.v:6291$1970_Y + attribute \src "ls180.v:6291.39-6291.146" + wire $and$ls180.v:6291$1972_Y + attribute \src "ls180.v:6292.40-6292.98" + wire $and$ls180.v:6292$1974_Y + attribute \src "ls180.v:6292.39-6292.149" + wire $and$ls180.v:6292$1976_Y + attribute \src "ls180.v:6294.39-6294.94" + wire $and$ls180.v:6294$1977_Y + attribute \src "ls180.v:6294.38-6294.145" + wire $and$ls180.v:6294$1979_Y + attribute \src "ls180.v:6295.39-6295.97" + wire $and$ls180.v:6295$1981_Y + attribute \src "ls180.v:6295.38-6295.148" + wire $and$ls180.v:6295$1983_Y + attribute \src "ls180.v:6297.38-6297.93" + wire $and$ls180.v:6297$1984_Y + attribute \src "ls180.v:6297.37-6297.144" + wire $and$ls180.v:6297$1986_Y + attribute \src "ls180.v:6298.38-6298.96" + wire $and$ls180.v:6298$1988_Y + attribute \src "ls180.v:6298.37-6298.147" + wire $and$ls180.v:6298$1990_Y + attribute \src "ls180.v:6300.37-6300.92" + wire $and$ls180.v:6300$1991_Y + attribute \src "ls180.v:6300.36-6300.143" + wire $and$ls180.v:6300$1993_Y + attribute \src "ls180.v:6301.37-6301.95" + wire $and$ls180.v:6301$1995_Y + attribute \src "ls180.v:6301.36-6301.146" + wire $and$ls180.v:6301$1997_Y + attribute \src "ls180.v:6303.43-6303.98" + wire $and$ls180.v:6303$1998_Y + attribute \src "ls180.v:6303.42-6303.149" + wire $and$ls180.v:6303$2000_Y + attribute \src "ls180.v:6304.43-6304.101" + wire $and$ls180.v:6304$2002_Y + attribute \src "ls180.v:6304.42-6304.152" + wire $and$ls180.v:6304$2004_Y + attribute \src "ls180.v:6306.46-6306.101" + wire $and$ls180.v:6306$2005_Y + attribute \src "ls180.v:6306.45-6306.152" + wire $and$ls180.v:6306$2007_Y + attribute \src "ls180.v:6307.46-6307.104" + wire $and$ls180.v:6307$2009_Y + attribute \src "ls180.v:6307.45-6307.155" + wire $and$ls180.v:6307$2011_Y + attribute \src "ls180.v:6309.46-6309.101" + wire $and$ls180.v:6309$2012_Y + attribute \src "ls180.v:6309.45-6309.152" + wire $and$ls180.v:6309$2014_Y + attribute \src "ls180.v:6310.46-6310.104" + wire $and$ls180.v:6310$2016_Y + attribute \src "ls180.v:6310.45-6310.155" + wire $and$ls180.v:6310$2018_Y + attribute \src "ls180.v:6333.39-6333.94" + wire $and$ls180.v:6333$2021_Y + attribute \src "ls180.v:6333.38-6333.145" + wire $and$ls180.v:6333$2023_Y + attribute \src "ls180.v:6334.39-6334.97" + wire $and$ls180.v:6334$2025_Y + attribute \src "ls180.v:6334.38-6334.148" + wire $and$ls180.v:6334$2027_Y + attribute \src "ls180.v:6336.39-6336.94" + wire $and$ls180.v:6336$2028_Y + attribute \src "ls180.v:6336.38-6336.145" + wire $and$ls180.v:6336$2030_Y + attribute \src "ls180.v:6337.39-6337.97" + wire $and$ls180.v:6337$2032_Y + attribute \src "ls180.v:6337.38-6337.148" + wire $and$ls180.v:6337$2034_Y + attribute \src "ls180.v:6339.39-6339.94" + wire $and$ls180.v:6339$2035_Y + attribute \src "ls180.v:6339.38-6339.145" + wire $and$ls180.v:6339$2037_Y + attribute \src "ls180.v:6340.39-6340.97" + wire $and$ls180.v:6340$2039_Y + attribute \src "ls180.v:6340.38-6340.148" + wire $and$ls180.v:6340$2041_Y + attribute \src "ls180.v:6342.39-6342.94" + wire $and$ls180.v:6342$2042_Y + attribute \src "ls180.v:6342.38-6342.145" + wire $and$ls180.v:6342$2044_Y + attribute \src "ls180.v:6343.39-6343.97" + wire $and$ls180.v:6343$2046_Y + attribute \src "ls180.v:6343.38-6343.148" + wire $and$ls180.v:6343$2048_Y + attribute \src "ls180.v:6345.41-6345.96" + wire $and$ls180.v:6345$2049_Y + attribute \src "ls180.v:6345.40-6345.147" + wire $and$ls180.v:6345$2051_Y + attribute \src "ls180.v:6346.41-6346.99" + wire $and$ls180.v:6346$2053_Y + attribute \src "ls180.v:6346.40-6346.150" + wire $and$ls180.v:6346$2055_Y + attribute \src "ls180.v:6348.41-6348.96" + wire $and$ls180.v:6348$2056_Y + attribute \src "ls180.v:6348.40-6348.147" + wire $and$ls180.v:6348$2058_Y + attribute \src "ls180.v:6349.41-6349.99" + wire $and$ls180.v:6349$2060_Y + attribute \src "ls180.v:6349.40-6349.150" + wire $and$ls180.v:6349$2062_Y + attribute \src "ls180.v:6351.41-6351.96" + wire $and$ls180.v:6351$2063_Y + attribute \src "ls180.v:6351.40-6351.147" + wire $and$ls180.v:6351$2065_Y + attribute \src "ls180.v:6352.41-6352.99" + wire $and$ls180.v:6352$2067_Y + attribute \src "ls180.v:6352.40-6352.150" + wire $and$ls180.v:6352$2069_Y + attribute \src "ls180.v:6354.41-6354.96" + wire $and$ls180.v:6354$2070_Y + attribute \src "ls180.v:6354.40-6354.147" + wire $and$ls180.v:6354$2072_Y + attribute \src "ls180.v:6355.41-6355.99" + wire $and$ls180.v:6355$2074_Y + attribute \src "ls180.v:6355.40-6355.150" + wire $and$ls180.v:6355$2076_Y + attribute \src "ls180.v:6357.37-6357.92" + wire $and$ls180.v:6357$2077_Y + attribute \src "ls180.v:6357.36-6357.143" + wire $and$ls180.v:6357$2079_Y + attribute \src "ls180.v:6358.37-6358.95" + wire $and$ls180.v:6358$2081_Y + attribute \src "ls180.v:6358.36-6358.146" + wire $and$ls180.v:6358$2083_Y + attribute \src "ls180.v:6360.47-6360.102" + wire $and$ls180.v:6360$2084_Y + attribute \src "ls180.v:6360.46-6360.153" + wire $and$ls180.v:6360$2086_Y + attribute \src "ls180.v:6361.47-6361.105" + wire $and$ls180.v:6361$2088_Y + attribute \src "ls180.v:6361.46-6361.156" + wire $and$ls180.v:6361$2090_Y + attribute \src "ls180.v:6363.40-6363.95" + wire $and$ls180.v:6363$2091_Y + attribute \src "ls180.v:6363.39-6363.147" + wire $and$ls180.v:6363$2093_Y + attribute \src "ls180.v:6364.40-6364.98" + wire $and$ls180.v:6364$2095_Y + attribute \src "ls180.v:6364.39-6364.150" + wire $and$ls180.v:6364$2097_Y + attribute \src "ls180.v:6366.40-6366.95" + wire $and$ls180.v:6366$2098_Y + attribute \src "ls180.v:6366.39-6366.147" + wire $and$ls180.v:6366$2100_Y + attribute \src "ls180.v:6367.40-6367.98" + wire $and$ls180.v:6367$2102_Y + attribute \src "ls180.v:6367.39-6367.150" + wire $and$ls180.v:6367$2104_Y + attribute \src "ls180.v:6369.40-6369.95" + wire $and$ls180.v:6369$2105_Y + attribute \src "ls180.v:6369.39-6369.147" + wire $and$ls180.v:6369$2107_Y + attribute \src "ls180.v:6370.40-6370.98" + wire $and$ls180.v:6370$2109_Y + attribute \src "ls180.v:6370.39-6370.150" + wire $and$ls180.v:6370$2111_Y + attribute \src "ls180.v:6372.40-6372.95" + wire $and$ls180.v:6372$2112_Y + attribute \src "ls180.v:6372.39-6372.147" + wire $and$ls180.v:6372$2114_Y + attribute \src "ls180.v:6373.40-6373.98" + wire $and$ls180.v:6373$2116_Y + attribute \src "ls180.v:6373.39-6373.150" + wire $and$ls180.v:6373$2118_Y + attribute \src "ls180.v:6375.52-6375.107" + wire $and$ls180.v:6375$2119_Y + attribute \src "ls180.v:6375.51-6375.159" + wire $and$ls180.v:6375$2121_Y + attribute \src "ls180.v:6376.52-6376.110" + wire $and$ls180.v:6376$2123_Y + attribute \src "ls180.v:6376.51-6376.162" + wire $and$ls180.v:6376$2125_Y + attribute \src "ls180.v:6378.53-6378.108" + wire $and$ls180.v:6378$2126_Y + attribute \src "ls180.v:6378.52-6378.160" + wire $and$ls180.v:6378$2128_Y + attribute \src "ls180.v:6379.53-6379.111" + wire $and$ls180.v:6379$2130_Y + attribute \src "ls180.v:6379.52-6379.163" + wire $and$ls180.v:6379$2132_Y + attribute \src "ls180.v:6381.44-6381.99" + wire $and$ls180.v:6381$2133_Y + attribute \src "ls180.v:6381.43-6381.151" + wire $and$ls180.v:6381$2135_Y + attribute \src "ls180.v:6382.44-6382.102" + wire $and$ls180.v:6382$2137_Y + attribute \src "ls180.v:6382.43-6382.154" + wire $and$ls180.v:6382$2139_Y + attribute \src "ls180.v:6401.30-6401.85" + wire $and$ls180.v:6401$2141_Y + attribute \src "ls180.v:6401.29-6401.136" + wire $and$ls180.v:6401$2143_Y + attribute \src "ls180.v:6402.30-6402.88" + wire $and$ls180.v:6402$2145_Y + attribute \src "ls180.v:6402.29-6402.139" + wire $and$ls180.v:6402$2147_Y + attribute \src "ls180.v:6404.40-6404.95" + wire $and$ls180.v:6404$2148_Y + attribute \src "ls180.v:6404.39-6404.146" + wire $and$ls180.v:6404$2150_Y + attribute \src "ls180.v:6405.40-6405.98" + wire $and$ls180.v:6405$2152_Y + attribute \src "ls180.v:6405.39-6405.149" + wire $and$ls180.v:6405$2154_Y + attribute \src "ls180.v:6407.41-6407.96" + wire $and$ls180.v:6407$2155_Y + attribute \src "ls180.v:6407.40-6407.147" + wire $and$ls180.v:6407$2157_Y + attribute \src "ls180.v:6408.41-6408.99" + wire $and$ls180.v:6408$2159_Y + attribute \src "ls180.v:6408.40-6408.150" + wire $and$ls180.v:6408$2161_Y + attribute \src "ls180.v:6410.45-6410.100" + wire $and$ls180.v:6410$2162_Y + attribute \src "ls180.v:6410.44-6410.151" + wire $and$ls180.v:6410$2164_Y + attribute \src "ls180.v:6411.45-6411.103" + wire $and$ls180.v:6411$2166_Y + attribute \src "ls180.v:6411.44-6411.154" + wire $and$ls180.v:6411$2168_Y + attribute \src "ls180.v:6413.46-6413.101" + wire $and$ls180.v:6413$2169_Y + attribute \src "ls180.v:6413.45-6413.152" + wire $and$ls180.v:6413$2171_Y + attribute \src "ls180.v:6414.46-6414.104" + wire $and$ls180.v:6414$2173_Y + attribute \src "ls180.v:6414.45-6414.155" + wire $and$ls180.v:6414$2175_Y + attribute \src "ls180.v:6416.44-6416.99" + wire $and$ls180.v:6416$2176_Y + attribute \src "ls180.v:6416.43-6416.150" + wire $and$ls180.v:6416$2178_Y + attribute \src "ls180.v:6417.44-6417.102" + wire $and$ls180.v:6417$2180_Y + attribute \src "ls180.v:6417.43-6417.153" + wire $and$ls180.v:6417$2182_Y + attribute \src "ls180.v:6419.41-6419.96" + wire $and$ls180.v:6419$2183_Y + attribute \src "ls180.v:6419.40-6419.147" + wire $and$ls180.v:6419$2185_Y + attribute \src "ls180.v:6420.41-6420.99" + wire $and$ls180.v:6420$2187_Y + attribute \src "ls180.v:6420.40-6420.150" + wire $and$ls180.v:6420$2189_Y + attribute \src "ls180.v:6422.40-6422.95" + wire $and$ls180.v:6422$2190_Y + attribute \src "ls180.v:6422.39-6422.146" + wire $and$ls180.v:6422$2192_Y + attribute \src "ls180.v:6423.40-6423.98" + wire $and$ls180.v:6423$2194_Y + attribute \src "ls180.v:6423.39-6423.149" + wire $and$ls180.v:6423$2196_Y + attribute \src "ls180.v:6435.46-6435.101" + wire $and$ls180.v:6435$2198_Y + attribute \src "ls180.v:6435.45-6435.152" + wire $and$ls180.v:6435$2200_Y + attribute \src "ls180.v:6436.46-6436.104" + wire $and$ls180.v:6436$2202_Y + attribute \src "ls180.v:6436.45-6436.155" + wire $and$ls180.v:6436$2204_Y + attribute \src "ls180.v:6438.46-6438.101" + wire $and$ls180.v:6438$2205_Y + attribute \src "ls180.v:6438.45-6438.152" + wire $and$ls180.v:6438$2207_Y + attribute \src "ls180.v:6439.46-6439.104" + wire $and$ls180.v:6439$2209_Y + attribute \src "ls180.v:6439.45-6439.155" + wire $and$ls180.v:6439$2211_Y + attribute \src "ls180.v:6441.46-6441.101" + wire $and$ls180.v:6441$2212_Y + attribute \src "ls180.v:6441.45-6441.152" + wire $and$ls180.v:6441$2214_Y + attribute \src "ls180.v:6442.46-6442.104" + wire $and$ls180.v:6442$2216_Y + attribute \src "ls180.v:6442.45-6442.155" + wire $and$ls180.v:6442$2218_Y + attribute \src "ls180.v:6444.46-6444.101" + wire $and$ls180.v:6444$2219_Y + attribute \src "ls180.v:6444.45-6444.152" + wire $and$ls180.v:6444$2221_Y + attribute \src "ls180.v:6445.46-6445.104" + wire $and$ls180.v:6445$2223_Y + attribute \src "ls180.v:6445.45-6445.155" + wire $and$ls180.v:6445$2225_Y + attribute \src "ls180.v:6826.109-6826.178" + wire $and$ls180.v:6826$2263_Y + attribute \src "ls180.v:6826.184-6826.253" + wire $and$ls180.v:6826$2266_Y + attribute \src "ls180.v:6826.259-6826.328" + wire $and$ls180.v:6826$2269_Y + attribute \src "ls180.v:6826.40-6826.331" + wire $and$ls180.v:6826$2272_Y + attribute \src "ls180.v:6826.39-6826.354" + wire $and$ls180.v:6826$2273_Y + attribute \src "ls180.v:6850.109-6850.178" + wire $and$ls180.v:6850$2279_Y + attribute \src "ls180.v:6850.184-6850.253" + wire $and$ls180.v:6850$2282_Y + attribute \src "ls180.v:6850.259-6850.328" + wire $and$ls180.v:6850$2285_Y + attribute \src "ls180.v:6850.40-6850.331" + wire $and$ls180.v:6850$2288_Y + attribute \src "ls180.v:6850.39-6850.354" + wire $and$ls180.v:6850$2289_Y + attribute \src "ls180.v:6874.109-6874.178" + wire $and$ls180.v:6874$2295_Y + attribute \src "ls180.v:6874.184-6874.253" + wire $and$ls180.v:6874$2298_Y + attribute \src "ls180.v:6874.259-6874.328" + wire $and$ls180.v:6874$2301_Y + attribute \src "ls180.v:6874.40-6874.331" + wire $and$ls180.v:6874$2304_Y + attribute \src "ls180.v:6874.39-6874.354" + wire $and$ls180.v:6874$2305_Y + attribute \src "ls180.v:6898.109-6898.178" + wire $and$ls180.v:6898$2311_Y + attribute \src "ls180.v:6898.184-6898.253" + wire $and$ls180.v:6898$2314_Y + attribute \src "ls180.v:6898.259-6898.328" + wire $and$ls180.v:6898$2317_Y + attribute \src "ls180.v:6898.40-6898.331" + wire $and$ls180.v:6898$2320_Y + attribute \src "ls180.v:6898.39-6898.354" + wire $and$ls180.v:6898$2321_Y + attribute \src "ls180.v:7103.39-7103.104" + wire $and$ls180.v:7103$2333_Y + attribute \src "ls180.v:7103.38-7103.145" + wire $and$ls180.v:7103$2334_Y + attribute \src "ls180.v:7106.39-7106.104" + wire $and$ls180.v:7106$2335_Y + attribute \src "ls180.v:7106.38-7106.145" + wire $and$ls180.v:7106$2336_Y + attribute \src "ls180.v:7109.39-7109.82" + wire $and$ls180.v:7109$2337_Y + attribute \src "ls180.v:7109.38-7109.112" + wire $and$ls180.v:7109$2338_Y + attribute \src "ls180.v:7120.39-7120.104" + wire $and$ls180.v:7120$2340_Y + attribute \src "ls180.v:7120.38-7120.145" + wire $and$ls180.v:7120$2341_Y + attribute \src "ls180.v:7123.39-7123.104" + wire $and$ls180.v:7123$2342_Y + attribute \src "ls180.v:7123.38-7123.145" + wire $and$ls180.v:7123$2343_Y + attribute \src "ls180.v:7126.39-7126.82" + wire $and$ls180.v:7126$2344_Y + attribute \src "ls180.v:7126.38-7126.112" + wire $and$ls180.v:7126$2345_Y + attribute \src "ls180.v:7137.39-7137.104" + wire $and$ls180.v:7137$2347_Y + attribute \src "ls180.v:7137.38-7137.144" + wire $and$ls180.v:7137$2348_Y + attribute \src "ls180.v:7140.39-7140.104" + wire $and$ls180.v:7140$2349_Y + attribute \src "ls180.v:7140.38-7140.144" + wire $and$ls180.v:7140$2350_Y + attribute \src "ls180.v:7143.39-7143.82" + wire $and$ls180.v:7143$2351_Y + attribute \src "ls180.v:7143.38-7143.111" + wire $and$ls180.v:7143$2352_Y + attribute \src "ls180.v:7154.39-7154.104" + wire $and$ls180.v:7154$2354_Y + attribute \src "ls180.v:7154.38-7154.149" + wire $and$ls180.v:7154$2355_Y + attribute \src "ls180.v:7157.39-7157.104" + wire $and$ls180.v:7157$2356_Y + attribute \src "ls180.v:7157.38-7157.149" + wire $and$ls180.v:7157$2357_Y + attribute \src "ls180.v:7160.39-7160.82" + wire $and$ls180.v:7160$2358_Y + attribute \src "ls180.v:7160.38-7160.116" + wire $and$ls180.v:7160$2359_Y + attribute \src "ls180.v:7171.39-7171.104" + wire $and$ls180.v:7171$2361_Y + attribute \src "ls180.v:7171.38-7171.150" + wire $and$ls180.v:7171$2362_Y + attribute \src "ls180.v:7174.39-7174.104" + wire $and$ls180.v:7174$2363_Y + attribute \src "ls180.v:7174.38-7174.150" + wire $and$ls180.v:7174$2364_Y + attribute \src "ls180.v:7177.39-7177.82" + wire $and$ls180.v:7177$2365_Y + attribute \src "ls180.v:7177.38-7177.117" + wire $and$ls180.v:7177$2366_Y + attribute \src "ls180.v:7396.17-7396.67" + wire $and$ls180.v:7396$2373_Y + attribute \src "ls180.v:7487.8-7487.67" + wire $and$ls180.v:7487$2416_Y + attribute \src "ls180.v:7487.7-7487.102" + wire $and$ls180.v:7487$2418_Y + attribute \src "ls180.v:7506.7-7506.75" + wire $and$ls180.v:7506$2422_Y + attribute \src "ls180.v:7514.7-7514.56" + wire $and$ls180.v:7514$2424_Y + attribute \src "ls180.v:7542.7-7542.75" + wire $and$ls180.v:7542$2431_Y + attribute \src "ls180.v:7584.8-7584.131" + wire $and$ls180.v:7584$2437_Y + attribute \src "ls180.v:7584.7-7584.190" + wire $and$ls180.v:7584$2439_Y + attribute \src "ls180.v:7590.8-7590.131" + wire $and$ls180.v:7590$2442_Y + attribute \src "ls180.v:7590.7-7590.190" + wire $and$ls180.v:7590$2444_Y + attribute \src "ls180.v:7630.8-7630.131" + wire $and$ls180.v:7630$2453_Y + attribute \src "ls180.v:7630.7-7630.190" + wire $and$ls180.v:7630$2455_Y + attribute \src "ls180.v:7636.8-7636.131" + wire $and$ls180.v:7636$2458_Y + attribute \src "ls180.v:7636.7-7636.190" + wire $and$ls180.v:7636$2460_Y + attribute \src "ls180.v:7676.8-7676.131" + wire $and$ls180.v:7676$2469_Y + attribute \src "ls180.v:7676.7-7676.190" + wire $and$ls180.v:7676$2471_Y + attribute \src "ls180.v:7682.8-7682.131" + wire $and$ls180.v:7682$2474_Y + attribute \src "ls180.v:7682.7-7682.190" + wire $and$ls180.v:7682$2476_Y + attribute \src "ls180.v:7722.8-7722.131" + wire $and$ls180.v:7722$2485_Y + attribute \src "ls180.v:7722.7-7722.190" + wire $and$ls180.v:7722$2487_Y + attribute \src "ls180.v:7728.8-7728.131" + wire $and$ls180.v:7728$2490_Y + attribute \src "ls180.v:7728.7-7728.190" + wire $and$ls180.v:7728$2492_Y + attribute \src "ls180.v:7925.48-7925.124" + wire $and$ls180.v:7925$2517_Y + attribute \src "ls180.v:7925.130-7925.206" + wire $and$ls180.v:7925$2520_Y + attribute \src "ls180.v:7925.212-7925.288" + wire $and$ls180.v:7925$2523_Y + attribute \src "ls180.v:7925.294-7925.370" + wire $and$ls180.v:7925$2526_Y + attribute \src "ls180.v:7926.49-7926.125" + wire $and$ls180.v:7926$2529_Y + attribute \src "ls180.v:7926.131-7926.207" + wire $and$ls180.v:7926$2532_Y + attribute \src "ls180.v:7926.213-7926.289" + wire $and$ls180.v:7926$2535_Y + attribute \src "ls180.v:7926.295-7926.371" + wire $and$ls180.v:7926$2538_Y + attribute \src "ls180.v:7945.8-7945.49" + wire $and$ls180.v:7945$2541_Y + attribute \src "ls180.v:7948.8-7948.53" + wire $and$ls180.v:7948$2542_Y + attribute \src "ls180.v:7953.8-7953.59" + wire $and$ls180.v:7953$2544_Y + attribute \src "ls180.v:7953.7-7953.90" + wire $and$ls180.v:7953$2546_Y + attribute \src "ls180.v:7959.8-7959.59" + wire $and$ls180.v:7959$2547_Y + attribute \src "ls180.v:7983.8-7983.48" + wire $and$ls180.v:7983$2554_Y + attribute \src "ls180.v:8016.7-8016.57" + wire $and$ls180.v:8016$2560_Y + attribute \src "ls180.v:8023.7-8023.57" + wire $and$ls180.v:8023$2562_Y + attribute \src "ls180.v:8033.8-8033.75" + wire $and$ls180.v:8033$2563_Y + attribute \src "ls180.v:8033.7-8033.107" + wire $and$ls180.v:8033$2565_Y + attribute \src "ls180.v:8039.8-8039.75" + wire $and$ls180.v:8039$2568_Y + attribute \src "ls180.v:8039.7-8039.107" + wire $and$ls180.v:8039$2570_Y + attribute \src "ls180.v:8055.8-8055.75" + wire $and$ls180.v:8055$2574_Y + attribute \src "ls180.v:8055.7-8055.107" + wire $and$ls180.v:8055$2576_Y + attribute \src "ls180.v:8061.8-8061.75" + wire $and$ls180.v:8061$2579_Y + attribute \src "ls180.v:8061.7-8061.107" + wire $and$ls180.v:8061$2581_Y + attribute \src "ls180.v:8174.7-8174.96" + wire $and$ls180.v:8174$2604_Y + attribute \src "ls180.v:8175.8-8175.93" + wire $and$ls180.v:8175$2605_Y + attribute \src "ls180.v:8183.8-8183.93" + wire $and$ls180.v:8183$2606_Y + attribute \src "ls180.v:8255.7-8255.98" + wire $and$ls180.v:8255$2616_Y + attribute \src "ls180.v:8256.8-8256.95" + wire $and$ls180.v:8256$2617_Y + attribute \src "ls180.v:8264.8-8264.95" + wire $and$ls180.v:8264$2618_Y + attribute \src "ls180.v:8334.7-8334.100" + wire $and$ls180.v:8334$2628_Y + attribute \src "ls180.v:8335.8-8335.97" + wire $and$ls180.v:8335$2629_Y + attribute \src "ls180.v:8343.8-8343.97" + wire $and$ls180.v:8343$2630_Y + attribute \src "ls180.v:8434.7-8434.82" + wire $and$ls180.v:8434$2636_Y + attribute \src "ls180.v:8437.7-8437.82" + wire $and$ls180.v:8437$2637_Y + attribute \src "ls180.v:8440.7-8440.82" + wire $and$ls180.v:8440$2638_Y + attribute \src "ls180.v:8443.7-8443.82" + wire $and$ls180.v:8443$2639_Y + attribute \src "ls180.v:8446.7-8446.82" + wire $and$ls180.v:8446$2640_Y + attribute \src "ls180.v:8451.7-8451.82" + wire $and$ls180.v:8451$2641_Y + attribute \src "ls180.v:8456.7-8456.82" + wire $and$ls180.v:8456$2642_Y + attribute \src "ls180.v:8461.7-8461.82" + wire $and$ls180.v:8461$2643_Y + attribute \src "ls180.v:8466.7-8466.82" + wire $and$ls180.v:8466$2644_Y + attribute \src "ls180.v:8531.8-8531.83" + wire $and$ls180.v:8531$2647_Y + attribute \src "ls180.v:8531.7-8531.119" + wire $and$ls180.v:8531$2649_Y + attribute \src "ls180.v:8537.8-8537.83" + wire $and$ls180.v:8537$2652_Y + attribute \src "ls180.v:8537.7-8537.119" + wire $and$ls180.v:8537$2654_Y + attribute \src "ls180.v:8557.7-8557.88" + wire $and$ls180.v:8557$2661_Y + attribute \src "ls180.v:8558.8-8558.85" + wire $and$ls180.v:8558$2662_Y + attribute \src "ls180.v:8566.8-8566.85" + wire $and$ls180.v:8566$2663_Y + attribute \src "ls180.v:8610.7-8610.88" + wire $and$ls180.v:8610$2667_Y + attribute \src "ls180.v:8617.8-8617.83" + wire $and$ls180.v:8617$2669_Y + attribute \src "ls180.v:8617.7-8617.119" + wire $and$ls180.v:8617$2671_Y + attribute \src "ls180.v:8623.8-8623.83" + wire $and$ls180.v:8623$2674_Y + attribute \src "ls180.v:8623.7-8623.119" + wire $and$ls180.v:8623$2676_Y + attribute \src "ls180.v:2794.42-2794.101" + wire $eq$ls180.v:2794$18_Y + attribute \src "ls180.v:2801.11-2801.54" + wire $eq$ls180.v:2801$23_Y + attribute \src "ls180.v:2854.42-2854.101" + wire $eq$ls180.v:2854$29_Y + attribute \src "ls180.v:2861.11-2861.54" + wire $eq$ls180.v:2861$34_Y + attribute \src "ls180.v:2914.42-2914.101" + wire $eq$ls180.v:2914$40_Y + attribute \src "ls180.v:2921.11-2921.54" + wire $eq$ls180.v:2921$45_Y + attribute \src "ls180.v:3107.34-3107.65" + wire $eq$ls180.v:3107$73_Y + attribute \src "ls180.v:3111.68-3111.102" + wire $eq$ls180.v:3111$76_Y + attribute \src "ls180.v:3155.43-3155.134" + wire $eq$ls180.v:3155$81_Y + attribute \src "ls180.v:3172.47-3172.88" + wire $eq$ls180.v:3172$94_Y + attribute \src "ls180.v:3312.43-3312.134" + wire $eq$ls180.v:3312$111_Y + attribute \src "ls180.v:3329.47-3329.88" + wire $eq$ls180.v:3329$124_Y + attribute \src "ls180.v:3469.43-3469.134" + wire $eq$ls180.v:3469$141_Y + attribute \src "ls180.v:3486.47-3486.88" + wire $eq$ls180.v:3486$154_Y + attribute \src "ls180.v:3626.43-3626.134" + wire $eq$ls180.v:3626$171_Y + attribute \src "ls180.v:3643.47-3643.88" + wire $eq$ls180.v:3643$184_Y + attribute \src "ls180.v:3780.32-3780.56" + wire $eq$ls180.v:3780$231_Y + attribute \src "ls180.v:3781.32-3781.56" + wire $eq$ls180.v:3781$232_Y + attribute \src "ls180.v:3792.339-3792.418" + wire $eq$ls180.v:3792$246_Y + attribute \src "ls180.v:3792.423-3792.504" + wire $eq$ls180.v:3792$247_Y + attribute \src "ls180.v:3793.339-3793.418" + wire $eq$ls180.v:3793$259_Y + attribute \src "ls180.v:3793.423-3793.504" + wire $eq$ls180.v:3793$260_Y + attribute \src "ls180.v:3794.339-3794.418" + wire $eq$ls180.v:3794$272_Y + attribute \src "ls180.v:3794.423-3794.504" + wire $eq$ls180.v:3794$273_Y + attribute \src "ls180.v:3795.339-3795.418" + wire $eq$ls180.v:3795$285_Y + attribute \src "ls180.v:3795.423-3795.504" + wire $eq$ls180.v:3795$286_Y + attribute \src "ls180.v:3825.339-3825.418" + wire $eq$ls180.v:3825$304_Y + attribute \src "ls180.v:3825.423-3825.504" + wire $eq$ls180.v:3825$305_Y + attribute \src "ls180.v:3826.339-3826.418" + wire $eq$ls180.v:3826$317_Y + attribute \src "ls180.v:3826.423-3826.504" + wire $eq$ls180.v:3826$318_Y + attribute \src "ls180.v:3827.339-3827.418" + wire $eq$ls180.v:3827$330_Y + attribute \src "ls180.v:3827.423-3827.504" + wire $eq$ls180.v:3827$331_Y + attribute \src "ls180.v:3828.339-3828.418" + wire $eq$ls180.v:3828$343_Y + attribute \src "ls180.v:3828.423-3828.504" + wire $eq$ls180.v:3828$344_Y + attribute \src "ls180.v:3857.78-3857.113" + wire $eq$ls180.v:3857$353_Y + attribute \src "ls180.v:3860.78-3860.113" + wire $eq$ls180.v:3860$356_Y + attribute \src "ls180.v:3866.78-3866.113" + wire $eq$ls180.v:3866$360_Y + attribute \src "ls180.v:3869.78-3869.113" + wire $eq$ls180.v:3869$363_Y + attribute \src "ls180.v:3875.78-3875.113" + wire $eq$ls180.v:3875$367_Y + attribute \src "ls180.v:3878.78-3878.113" + wire $eq$ls180.v:3878$370_Y + attribute \src "ls180.v:3884.78-3884.113" + wire $eq$ls180.v:3884$374_Y + attribute \src "ls180.v:3887.78-3887.113" + wire $eq$ls180.v:3887$377_Y + attribute \src "ls180.v:3968.42-3968.82" + wire $eq$ls180.v:3968$400_Y + attribute \src "ls180.v:3968.145-3968.178" + wire $eq$ls180.v:3968$401_Y + attribute \src "ls180.v:3968.220-3968.253" + wire $eq$ls180.v:3968$404_Y + attribute \src "ls180.v:3968.295-3968.328" + wire $eq$ls180.v:3968$407_Y + attribute \src "ls180.v:3973.42-3973.82" + wire $eq$ls180.v:3973$416_Y + attribute \src "ls180.v:3973.145-3973.178" + wire $eq$ls180.v:3973$417_Y + attribute \src "ls180.v:3973.220-3973.253" + wire $eq$ls180.v:3973$420_Y + attribute \src "ls180.v:3973.295-3973.328" + wire $eq$ls180.v:3973$423_Y + attribute \src "ls180.v:3978.42-3978.82" + wire $eq$ls180.v:3978$432_Y + attribute \src "ls180.v:3978.145-3978.178" + wire $eq$ls180.v:3978$433_Y + attribute \src "ls180.v:3978.220-3978.253" + wire $eq$ls180.v:3978$436_Y + attribute \src "ls180.v:3978.295-3978.328" + wire $eq$ls180.v:3978$439_Y + attribute \src "ls180.v:3983.42-3983.82" + wire $eq$ls180.v:3983$448_Y + attribute \src "ls180.v:3983.145-3983.178" + wire $eq$ls180.v:3983$449_Y + attribute \src "ls180.v:3983.220-3983.253" + wire $eq$ls180.v:3983$452_Y + attribute \src "ls180.v:3983.295-3983.328" + wire $eq$ls180.v:3983$455_Y + attribute \src "ls180.v:3988.44-3988.77" + wire $eq$ls180.v:3988$464_Y + attribute \src "ls180.v:3988.83-3988.123" + wire $eq$ls180.v:3988$465_Y + attribute \src "ls180.v:3988.186-3988.219" + wire $eq$ls180.v:3988$466_Y + attribute \src "ls180.v:3988.261-3988.294" + wire $eq$ls180.v:3988$469_Y + attribute \src "ls180.v:3988.336-3988.369" + wire $eq$ls180.v:3988$472_Y + attribute \src "ls180.v:3988.418-3988.451" + wire $eq$ls180.v:3988$480_Y + attribute \src "ls180.v:3988.457-3988.497" + wire $eq$ls180.v:3988$481_Y + attribute \src "ls180.v:3988.560-3988.593" + wire $eq$ls180.v:3988$482_Y + attribute \src "ls180.v:3988.635-3988.668" + wire $eq$ls180.v:3988$485_Y + attribute \src "ls180.v:3988.710-3988.743" + wire $eq$ls180.v:3988$488_Y + attribute \src "ls180.v:3988.792-3988.825" + wire $eq$ls180.v:3988$496_Y + attribute \src "ls180.v:3988.831-3988.871" + wire $eq$ls180.v:3988$497_Y + attribute \src "ls180.v:3988.934-3988.967" + wire $eq$ls180.v:3988$498_Y + attribute \src "ls180.v:3988.1009-3988.1042" + wire $eq$ls180.v:3988$501_Y + attribute \src "ls180.v:3988.1084-3988.1117" + wire $eq$ls180.v:3988$504_Y + attribute \src "ls180.v:3988.1166-3988.1199" + wire $eq$ls180.v:3988$512_Y + attribute \src "ls180.v:3988.1205-3988.1245" + wire $eq$ls180.v:3988$513_Y + attribute \src "ls180.v:3988.1308-3988.1341" + wire $eq$ls180.v:3988$514_Y + attribute \src "ls180.v:3988.1383-3988.1416" + wire $eq$ls180.v:3988$517_Y + attribute \src "ls180.v:3988.1458-3988.1491" + wire $eq$ls180.v:3988$520_Y + attribute \src "ls180.v:4047.29-4047.57" + wire $eq$ls180.v:4047$533_Y + attribute \src "ls180.v:4054.11-4054.41" + wire $eq$ls180.v:4054$538_Y + attribute \src "ls180.v:4211.36-4211.111" + wire $eq$ls180.v:4211$603_Y + attribute \src "ls180.v:4212.36-4212.105" + wire $eq$ls180.v:4212$605_Y + attribute \src "ls180.v:4239.10-4239.67" + wire $eq$ls180.v:4239$609_Y + attribute \src "ls180.v:4343.10-4343.40" + wire $eq$ls180.v:4343$636_Y + attribute \src "ls180.v:4400.10-4400.39" + wire $eq$ls180.v:4400$639_Y + attribute \src "ls180.v:4417.10-4417.39" + wire $eq$ls180.v:4417$641_Y + attribute \src "ls180.v:4445.38-4445.88" + wire $eq$ls180.v:4445$643_Y + attribute \src "ls180.v:4495.9-4495.40" + wire $eq$ls180.v:4495$653_Y + attribute \src "ls180.v:4504.36-4504.105" + wire $eq$ls180.v:4504$655_Y + attribute \src "ls180.v:4523.9-4523.40" + wire $eq$ls180.v:4523$659_Y + attribute \src "ls180.v:4535.10-4535.39" + wire $eq$ls180.v:4535$661_Y + attribute \src "ls180.v:4572.39-4572.94" + wire $eq$ls180.v:4572$665_Y + attribute \src "ls180.v:4609.32-4609.89" + wire $eq$ls180.v:4609$674_Y + attribute \src "ls180.v:4657.10-4657.40" + wire $eq$ls180.v:4657$678_Y + attribute \src "ls180.v:4706.40-4706.98" + wire $eq$ls180.v:4706$680_Y + attribute \src "ls180.v:4757.9-4757.41" + wire $eq$ls180.v:4757$690_Y + attribute \src "ls180.v:4766.37-4766.123" + wire $eq$ls180.v:4766$693_Y + attribute \src "ls180.v:4789.9-4789.41" + wire $eq$ls180.v:4789$696_Y + attribute \src "ls180.v:4799.10-4799.41" + wire $eq$ls180.v:4799$698_Y + attribute \src "ls180.v:4968.9-4968.47" + wire $eq$ls180.v:4968$880_Y + attribute \src "ls180.v:4998.10-4998.48" + wire $eq$ls180.v:4998$881_Y + attribute \src "ls180.v:5029.10-5029.78" + wire $eq$ls180.v:5029$886_Y + attribute \src "ls180.v:5029.83-5029.151" + wire $eq$ls180.v:5029$887_Y + attribute \src "ls180.v:5029.157-5029.225" + wire $eq$ls180.v:5029$889_Y + attribute \src "ls180.v:5029.231-5029.299" + wire $eq$ls180.v:5029$891_Y + attribute \src "ls180.v:5037.7-5037.44" + wire $eq$ls180.v:5037$895_Y + attribute \src "ls180.v:5047.7-5047.44" + wire $eq$ls180.v:5047$898_Y + attribute \src "ls180.v:5057.7-5057.44" + wire $eq$ls180.v:5057$901_Y + attribute \src "ls180.v:5067.7-5067.44" + wire $eq$ls180.v:5067$904_Y + attribute \src "ls180.v:5191.36-5191.64" + wire $eq$ls180.v:5191$955_Y + attribute \src "ls180.v:5197.10-5197.39" + wire $eq$ls180.v:5197$958_Y + attribute \src "ls180.v:5198.11-5198.39" + wire $eq$ls180.v:5198$959_Y + attribute \src "ls180.v:5210.34-5210.63" + wire $eq$ls180.v:5210$960_Y + attribute \src "ls180.v:5211.9-5211.37" + wire $eq$ls180.v:5211$961_Y + attribute \src "ls180.v:5218.10-5218.55" + wire $eq$ls180.v:5218$962_Y + attribute \src "ls180.v:5224.12-5224.41" + wire $eq$ls180.v:5224$963_Y + attribute \src "ls180.v:5227.13-5227.42" + wire $eq$ls180.v:5227$964_Y + attribute \src "ls180.v:5249.10-5249.76" + wire $eq$ls180.v:5249$969_Y + attribute \src "ls180.v:5264.35-5264.101" + wire $eq$ls180.v:5264$972_Y + attribute \src "ls180.v:5266.10-5266.56" + wire $eq$ls180.v:5266$973_Y + attribute \src "ls180.v:5275.12-5275.78" + wire $eq$ls180.v:5275$977_Y + attribute \src "ls180.v:5282.11-5282.57" + wire $eq$ls180.v:5282$978_Y + attribute \src "ls180.v:5399.10-5399.105" + wire $eq$ls180.v:5399$995_Y + attribute \src "ls180.v:5489.39-5489.106" + wire $eq$ls180.v:5489$1001_Y + attribute \src "ls180.v:5519.44-5519.82" + wire $eq$ls180.v:5519$1004_Y + attribute \src "ls180.v:5520.43-5520.81" + wire $eq$ls180.v:5520$1005_Y + attribute \src "ls180.v:5577.32-5577.99" + wire $eq$ls180.v:5577$1018_Y + attribute \src "ls180.v:5578.32-5578.93" + wire $eq$ls180.v:5578$1020_Y + attribute \src "ls180.v:5606.10-5606.59" + wire $eq$ls180.v:5606$1024_Y + attribute \src "ls180.v:5679.85-5679.106" + wire $eq$ls180.v:5679$1029_Y + attribute \src "ls180.v:5680.85-5680.106" + wire $eq$ls180.v:5680$1031_Y + attribute \src "ls180.v:5681.85-5681.106" + wire $eq$ls180.v:5681$1033_Y + attribute \src "ls180.v:5682.57-5682.78" + wire $eq$ls180.v:5682$1035_Y + attribute \src "ls180.v:5683.57-5683.78" + wire $eq$ls180.v:5683$1037_Y + attribute \src "ls180.v:5684.85-5684.106" + wire $eq$ls180.v:5684$1039_Y + attribute \src "ls180.v:5685.85-5685.106" + wire $eq$ls180.v:5685$1041_Y + attribute \src "ls180.v:5686.85-5686.106" + wire $eq$ls180.v:5686$1043_Y + attribute \src "ls180.v:5687.57-5687.78" + wire $eq$ls180.v:5687$1045_Y + attribute \src "ls180.v:5688.57-5688.78" + wire $eq$ls180.v:5688$1047_Y + attribute \src "ls180.v:5692.27-5692.59" + wire $eq$ls180.v:5692$1050_Y + attribute \src "ls180.v:5693.27-5693.68" + wire $eq$ls180.v:5693$1051_Y + attribute \src "ls180.v:5694.27-5694.66" + wire $eq$ls180.v:5694$1052_Y + attribute \src "ls180.v:5695.27-5695.61" + wire $eq$ls180.v:5695$1053_Y + attribute \src "ls180.v:5696.27-5696.65" + wire $eq$ls180.v:5696$1054_Y + attribute \src "ls180.v:5752.24-5752.45" + wire $eq$ls180.v:5752$1081_Y + attribute \src "ls180.v:5753.32-5753.77" + wire $eq$ls180.v:5753$1082_Y + attribute \src "ls180.v:5755.97-5755.141" + wire $eq$ls180.v:5755$1084_Y + attribute \src "ls180.v:5756.100-5756.144" + wire $eq$ls180.v:5756$1088_Y + attribute \src "ls180.v:5758.99-5758.143" + wire $eq$ls180.v:5758$1091_Y + attribute \src "ls180.v:5759.102-5759.146" + wire $eq$ls180.v:5759$1095_Y + attribute \src "ls180.v:5761.99-5761.143" + wire $eq$ls180.v:5761$1098_Y + attribute \src "ls180.v:5762.102-5762.146" + wire $eq$ls180.v:5762$1102_Y + attribute \src "ls180.v:5764.99-5764.143" + wire $eq$ls180.v:5764$1105_Y + attribute \src "ls180.v:5765.102-5765.146" + wire $eq$ls180.v:5765$1109_Y + attribute \src "ls180.v:5767.99-5767.143" + wire $eq$ls180.v:5767$1112_Y + attribute \src "ls180.v:5768.102-5768.146" + wire $eq$ls180.v:5768$1116_Y + attribute \src "ls180.v:5770.102-5770.146" + wire $eq$ls180.v:5770$1119_Y + attribute \src "ls180.v:5771.105-5771.149" + wire $eq$ls180.v:5771$1123_Y + attribute \src "ls180.v:5773.102-5773.146" + wire $eq$ls180.v:5773$1126_Y + attribute \src "ls180.v:5774.105-5774.149" + wire $eq$ls180.v:5774$1130_Y + attribute \src "ls180.v:5776.102-5776.146" + wire $eq$ls180.v:5776$1133_Y + attribute \src "ls180.v:5777.105-5777.149" + wire $eq$ls180.v:5777$1137_Y + attribute \src "ls180.v:5779.102-5779.146" + wire $eq$ls180.v:5779$1140_Y + attribute \src "ls180.v:5780.105-5780.149" + wire $eq$ls180.v:5780$1144_Y + attribute \src "ls180.v:5791.32-5791.77" + wire $eq$ls180.v:5791$1146_Y + attribute \src "ls180.v:5793.94-5793.138" + wire $eq$ls180.v:5793$1148_Y + attribute \src "ls180.v:5794.97-5794.141" + wire $eq$ls180.v:5794$1152_Y + attribute \src "ls180.v:5796.94-5796.138" + wire $eq$ls180.v:5796$1155_Y + attribute \src "ls180.v:5797.97-5797.141" + wire $eq$ls180.v:5797$1159_Y + attribute \src "ls180.v:5799.94-5799.138" + wire $eq$ls180.v:5799$1162_Y + attribute \src "ls180.v:5800.97-5800.141" + wire $eq$ls180.v:5800$1166_Y + attribute \src "ls180.v:5802.94-5802.138" + wire $eq$ls180.v:5802$1169_Y + attribute \src "ls180.v:5803.97-5803.141" + wire $eq$ls180.v:5803$1173_Y + attribute \src "ls180.v:5805.95-5805.139" + wire $eq$ls180.v:5805$1176_Y + attribute \src "ls180.v:5806.98-5806.142" + wire $eq$ls180.v:5806$1180_Y + attribute \src "ls180.v:5808.95-5808.139" + wire $eq$ls180.v:5808$1183_Y + attribute \src "ls180.v:5809.98-5809.142" + wire $eq$ls180.v:5809$1187_Y + attribute \src "ls180.v:5817.32-5817.78" + wire $eq$ls180.v:5817$1189_Y + attribute \src "ls180.v:5819.93-5819.135" + wire $eq$ls180.v:5819$1191_Y + attribute \src "ls180.v:5820.96-5820.138" + wire $eq$ls180.v:5820$1195_Y + attribute \src "ls180.v:5822.92-5822.134" + wire $eq$ls180.v:5822$1198_Y + attribute \src "ls180.v:5823.95-5823.137" + wire $eq$ls180.v:5823$1202_Y + attribute \src "ls180.v:5831.32-5831.77" + wire $eq$ls180.v:5831$1204_Y + attribute \src "ls180.v:5833.98-5833.142" + wire $eq$ls180.v:5833$1206_Y + attribute \src "ls180.v:5834.101-5834.145" + wire $eq$ls180.v:5834$1210_Y + attribute \src "ls180.v:5836.97-5836.141" + wire $eq$ls180.v:5836$1213_Y + attribute \src "ls180.v:5837.100-5837.144" + wire $eq$ls180.v:5837$1217_Y + attribute \src "ls180.v:5839.97-5839.141" + wire $eq$ls180.v:5839$1220_Y + attribute \src "ls180.v:5840.100-5840.144" + wire $eq$ls180.v:5840$1224_Y + attribute \src "ls180.v:5842.97-5842.141" + wire $eq$ls180.v:5842$1227_Y + attribute \src "ls180.v:5843.100-5843.144" + wire $eq$ls180.v:5843$1231_Y + attribute \src "ls180.v:5845.97-5845.141" + wire $eq$ls180.v:5845$1234_Y + attribute \src "ls180.v:5846.100-5846.144" + wire $eq$ls180.v:5846$1238_Y + attribute \src "ls180.v:5848.98-5848.142" + wire $eq$ls180.v:5848$1241_Y + attribute \src "ls180.v:5849.101-5849.145" + wire $eq$ls180.v:5849$1245_Y + attribute \src "ls180.v:5851.98-5851.142" + wire $eq$ls180.v:5851$1248_Y + attribute \src "ls180.v:5852.101-5852.145" + wire $eq$ls180.v:5852$1252_Y + attribute \src "ls180.v:5854.98-5854.142" + wire $eq$ls180.v:5854$1255_Y + attribute \src "ls180.v:5855.101-5855.145" + wire $eq$ls180.v:5855$1259_Y + attribute \src "ls180.v:5857.98-5857.142" + wire $eq$ls180.v:5857$1262_Y + attribute \src "ls180.v:5858.101-5858.145" + wire $eq$ls180.v:5858$1266_Y + attribute \src "ls180.v:5868.32-5868.77" + wire $eq$ls180.v:5868$1268_Y + attribute \src "ls180.v:5870.98-5870.142" + wire $eq$ls180.v:5870$1270_Y + attribute \src "ls180.v:5871.101-5871.145" + wire $eq$ls180.v:5871$1274_Y + attribute \src "ls180.v:5873.97-5873.141" + wire $eq$ls180.v:5873$1277_Y + attribute \src "ls180.v:5874.100-5874.144" + wire $eq$ls180.v:5874$1281_Y + attribute \src "ls180.v:5876.97-5876.141" + wire $eq$ls180.v:5876$1284_Y + attribute \src "ls180.v:5877.100-5877.144" + wire $eq$ls180.v:5877$1288_Y + attribute \src "ls180.v:5879.97-5879.141" + wire $eq$ls180.v:5879$1291_Y + attribute \src "ls180.v:5880.100-5880.144" + wire $eq$ls180.v:5880$1295_Y + attribute \src "ls180.v:5882.97-5882.141" + wire $eq$ls180.v:5882$1298_Y + attribute \src "ls180.v:5883.100-5883.144" + wire $eq$ls180.v:5883$1302_Y + attribute \src "ls180.v:5885.98-5885.142" + wire $eq$ls180.v:5885$1305_Y + attribute \src "ls180.v:5886.101-5886.145" + wire $eq$ls180.v:5886$1309_Y + attribute \src "ls180.v:5888.98-5888.142" + wire $eq$ls180.v:5888$1312_Y + attribute \src "ls180.v:5889.101-5889.145" + wire $eq$ls180.v:5889$1316_Y + attribute \src "ls180.v:5891.98-5891.142" + wire $eq$ls180.v:5891$1319_Y + attribute \src "ls180.v:5892.101-5892.145" + wire $eq$ls180.v:5892$1323_Y + attribute \src "ls180.v:5894.98-5894.142" + wire $eq$ls180.v:5894$1326_Y + attribute \src "ls180.v:5895.101-5895.145" + wire $eq$ls180.v:5895$1330_Y + attribute \src "ls180.v:5905.32-5905.78" + wire $eq$ls180.v:5905$1332_Y + attribute \src "ls180.v:5907.100-5907.144" + wire $eq$ls180.v:5907$1334_Y + attribute \src "ls180.v:5908.103-5908.147" + wire $eq$ls180.v:5908$1338_Y + attribute \src "ls180.v:5910.100-5910.144" + wire $eq$ls180.v:5910$1341_Y + attribute \src "ls180.v:5911.103-5911.147" + wire $eq$ls180.v:5911$1345_Y + attribute \src "ls180.v:5913.100-5913.144" + wire $eq$ls180.v:5913$1348_Y + attribute \src "ls180.v:5914.103-5914.147" + wire $eq$ls180.v:5914$1352_Y + attribute \src "ls180.v:5916.100-5916.144" + wire $eq$ls180.v:5916$1355_Y + attribute \src "ls180.v:5917.103-5917.147" + wire $eq$ls180.v:5917$1359_Y + attribute \src "ls180.v:5919.100-5919.144" + wire $eq$ls180.v:5919$1362_Y + attribute \src "ls180.v:5920.103-5920.147" + wire $eq$ls180.v:5920$1366_Y + attribute \src "ls180.v:5922.100-5922.144" + wire $eq$ls180.v:5922$1369_Y + attribute \src "ls180.v:5923.103-5923.147" + wire $eq$ls180.v:5923$1373_Y + attribute \src "ls180.v:5925.100-5925.144" + wire $eq$ls180.v:5925$1376_Y + attribute \src "ls180.v:5926.103-5926.147" + wire $eq$ls180.v:5926$1380_Y + attribute \src "ls180.v:5928.100-5928.144" + wire $eq$ls180.v:5928$1383_Y + attribute \src "ls180.v:5929.103-5929.147" + wire $eq$ls180.v:5929$1387_Y + attribute \src "ls180.v:5931.102-5931.146" + wire $eq$ls180.v:5931$1390_Y + attribute \src "ls180.v:5932.105-5932.149" + wire $eq$ls180.v:5932$1394_Y + attribute \src "ls180.v:5934.102-5934.146" + wire $eq$ls180.v:5934$1397_Y + attribute \src "ls180.v:5935.105-5935.149" + wire $eq$ls180.v:5935$1401_Y + attribute \src "ls180.v:5937.102-5937.147" + wire $eq$ls180.v:5937$1404_Y + attribute \src "ls180.v:5938.105-5938.150" + wire $eq$ls180.v:5938$1408_Y + attribute \src "ls180.v:5940.102-5940.147" + wire $eq$ls180.v:5940$1411_Y + attribute \src "ls180.v:5941.105-5941.150" + wire $eq$ls180.v:5941$1415_Y + attribute \src "ls180.v:5943.102-5943.147" + wire $eq$ls180.v:5943$1418_Y + attribute \src "ls180.v:5944.105-5944.150" + wire $eq$ls180.v:5944$1422_Y + attribute \src "ls180.v:5946.99-5946.144" + wire $eq$ls180.v:5946$1425_Y + attribute \src "ls180.v:5947.102-5947.147" + wire $eq$ls180.v:5947$1429_Y + attribute \src "ls180.v:5949.100-5949.145" + wire $eq$ls180.v:5949$1432_Y + attribute \src "ls180.v:5950.103-5950.148" + wire $eq$ls180.v:5950$1436_Y + attribute \src "ls180.v:5967.32-5967.78" + wire $eq$ls180.v:5967$1438_Y + attribute \src "ls180.v:5969.104-5969.148" + wire $eq$ls180.v:5969$1440_Y + attribute \src "ls180.v:5970.107-5970.151" + wire $eq$ls180.v:5970$1444_Y + attribute \src "ls180.v:5972.104-5972.148" + wire $eq$ls180.v:5972$1447_Y + attribute \src "ls180.v:5973.107-5973.151" + wire $eq$ls180.v:5973$1451_Y + attribute \src "ls180.v:5975.104-5975.148" + wire $eq$ls180.v:5975$1454_Y + attribute \src "ls180.v:5976.107-5976.151" + wire $eq$ls180.v:5976$1458_Y + attribute \src "ls180.v:5978.104-5978.148" + wire $eq$ls180.v:5978$1461_Y + attribute \src "ls180.v:5979.107-5979.151" + wire $eq$ls180.v:5979$1465_Y + attribute \src "ls180.v:5981.103-5981.147" + wire $eq$ls180.v:5981$1468_Y + attribute \src "ls180.v:5982.106-5982.150" + wire $eq$ls180.v:5982$1472_Y + attribute \src "ls180.v:5984.103-5984.147" + wire $eq$ls180.v:5984$1475_Y + attribute \src "ls180.v:5985.106-5985.150" + wire $eq$ls180.v:5985$1479_Y + attribute \src "ls180.v:5987.103-5987.147" + wire $eq$ls180.v:5987$1482_Y + attribute \src "ls180.v:5988.106-5988.150" + wire $eq$ls180.v:5988$1486_Y + attribute \src "ls180.v:5990.103-5990.147" + wire $eq$ls180.v:5990$1489_Y + attribute \src "ls180.v:5991.106-5991.150" + wire $eq$ls180.v:5991$1493_Y + attribute \src "ls180.v:5993.94-5993.138" + wire $eq$ls180.v:5993$1496_Y + attribute \src "ls180.v:5994.97-5994.141" + wire $eq$ls180.v:5994$1500_Y + attribute \src "ls180.v:5996.105-5996.149" + wire $eq$ls180.v:5996$1503_Y + attribute \src "ls180.v:5997.108-5997.152" + wire $eq$ls180.v:5997$1507_Y + attribute \src "ls180.v:5999.105-5999.150" + wire $eq$ls180.v:5999$1510_Y + attribute \src "ls180.v:6000.108-6000.153" + wire $eq$ls180.v:6000$1514_Y + attribute \src "ls180.v:6002.105-6002.150" + wire $eq$ls180.v:6002$1517_Y + attribute \src "ls180.v:6003.108-6003.153" + wire $eq$ls180.v:6003$1521_Y + attribute \src "ls180.v:6005.105-6005.150" + wire $eq$ls180.v:6005$1524_Y + attribute \src "ls180.v:6006.108-6006.153" + wire $eq$ls180.v:6006$1528_Y + attribute \src "ls180.v:6008.105-6008.150" + wire $eq$ls180.v:6008$1531_Y + attribute \src "ls180.v:6009.108-6009.153" + wire $eq$ls180.v:6009$1535_Y + attribute \src "ls180.v:6011.105-6011.150" + wire $eq$ls180.v:6011$1538_Y + attribute \src "ls180.v:6012.108-6012.153" + wire $eq$ls180.v:6012$1542_Y + attribute \src "ls180.v:6014.104-6014.149" + wire $eq$ls180.v:6014$1545_Y + attribute \src "ls180.v:6015.107-6015.152" + wire $eq$ls180.v:6015$1549_Y + attribute \src "ls180.v:6017.104-6017.149" + wire $eq$ls180.v:6017$1552_Y + attribute \src "ls180.v:6018.107-6018.152" + wire $eq$ls180.v:6018$1556_Y + attribute \src "ls180.v:6020.104-6020.149" + wire $eq$ls180.v:6020$1559_Y + attribute \src "ls180.v:6021.107-6021.152" + wire $eq$ls180.v:6021$1563_Y + attribute \src "ls180.v:6023.104-6023.149" + wire $eq$ls180.v:6023$1566_Y + attribute \src "ls180.v:6024.107-6024.152" + wire $eq$ls180.v:6024$1570_Y + attribute \src "ls180.v:6026.104-6026.149" + wire $eq$ls180.v:6026$1573_Y + attribute \src "ls180.v:6027.107-6027.152" + wire $eq$ls180.v:6027$1577_Y + attribute \src "ls180.v:6029.104-6029.149" + wire $eq$ls180.v:6029$1580_Y + attribute \src "ls180.v:6030.107-6030.152" + wire $eq$ls180.v:6030$1584_Y + attribute \src "ls180.v:6032.104-6032.149" + wire $eq$ls180.v:6032$1587_Y + attribute \src "ls180.v:6033.107-6033.152" + wire $eq$ls180.v:6033$1591_Y + attribute \src "ls180.v:6035.104-6035.149" + wire $eq$ls180.v:6035$1594_Y + attribute \src "ls180.v:6036.107-6036.152" + wire $eq$ls180.v:6036$1598_Y + attribute \src "ls180.v:6038.104-6038.149" + wire $eq$ls180.v:6038$1601_Y + attribute \src "ls180.v:6039.107-6039.152" + wire $eq$ls180.v:6039$1605_Y + attribute \src "ls180.v:6041.104-6041.149" + wire $eq$ls180.v:6041$1608_Y + attribute \src "ls180.v:6042.107-6042.152" + wire $eq$ls180.v:6042$1612_Y + attribute \src "ls180.v:6044.100-6044.145" + wire $eq$ls180.v:6044$1615_Y + attribute \src "ls180.v:6045.103-6045.148" + wire $eq$ls180.v:6045$1619_Y + attribute \src "ls180.v:6047.101-6047.146" + wire $eq$ls180.v:6047$1622_Y + attribute \src "ls180.v:6048.104-6048.149" + wire $eq$ls180.v:6048$1626_Y + attribute \src "ls180.v:6050.104-6050.149" + wire $eq$ls180.v:6050$1629_Y + attribute \src "ls180.v:6051.107-6051.152" + wire $eq$ls180.v:6051$1633_Y + attribute \src "ls180.v:6053.104-6053.149" + wire $eq$ls180.v:6053$1636_Y + attribute \src "ls180.v:6054.107-6054.152" + wire $eq$ls180.v:6054$1640_Y + attribute \src "ls180.v:6056.103-6056.148" + wire $eq$ls180.v:6056$1643_Y + attribute \src "ls180.v:6057.106-6057.151" + wire $eq$ls180.v:6057$1647_Y + attribute \src "ls180.v:6059.103-6059.148" + wire $eq$ls180.v:6059$1650_Y + attribute \src "ls180.v:6060.106-6060.151" + wire $eq$ls180.v:6060$1654_Y + attribute \src "ls180.v:6062.103-6062.148" + wire $eq$ls180.v:6062$1657_Y + attribute \src "ls180.v:6063.106-6063.151" + wire $eq$ls180.v:6063$1661_Y + attribute \src "ls180.v:6065.103-6065.148" + wire $eq$ls180.v:6065$1664_Y + attribute \src "ls180.v:6066.106-6066.151" + wire $eq$ls180.v:6066$1668_Y + attribute \src "ls180.v:6102.32-6102.78" + wire $eq$ls180.v:6102$1670_Y + attribute \src "ls180.v:6104.100-6104.144" + wire $eq$ls180.v:6104$1672_Y + attribute \src "ls180.v:6105.103-6105.147" + wire $eq$ls180.v:6105$1676_Y + attribute \src "ls180.v:6107.100-6107.144" + wire $eq$ls180.v:6107$1679_Y + attribute \src "ls180.v:6108.103-6108.147" + wire $eq$ls180.v:6108$1683_Y + attribute \src "ls180.v:6110.100-6110.144" + wire $eq$ls180.v:6110$1686_Y + attribute \src "ls180.v:6111.103-6111.147" + wire $eq$ls180.v:6111$1690_Y + attribute \src "ls180.v:6113.100-6113.144" + wire $eq$ls180.v:6113$1693_Y + attribute \src "ls180.v:6114.103-6114.147" + wire $eq$ls180.v:6114$1697_Y + attribute \src "ls180.v:6116.100-6116.144" + wire $eq$ls180.v:6116$1700_Y + attribute \src "ls180.v:6117.103-6117.147" + wire $eq$ls180.v:6117$1704_Y + attribute \src "ls180.v:6119.100-6119.144" + wire $eq$ls180.v:6119$1707_Y + attribute \src "ls180.v:6120.103-6120.147" + wire $eq$ls180.v:6120$1711_Y + attribute \src "ls180.v:6122.100-6122.144" + wire $eq$ls180.v:6122$1714_Y + attribute \src "ls180.v:6123.103-6123.147" + wire $eq$ls180.v:6123$1718_Y + attribute \src "ls180.v:6125.100-6125.144" + wire $eq$ls180.v:6125$1721_Y + attribute \src "ls180.v:6126.103-6126.147" + wire $eq$ls180.v:6126$1725_Y + attribute \src "ls180.v:6128.102-6128.146" + wire $eq$ls180.v:6128$1728_Y + attribute \src "ls180.v:6129.105-6129.149" + wire $eq$ls180.v:6129$1732_Y + attribute \src "ls180.v:6131.102-6131.146" + wire $eq$ls180.v:6131$1735_Y + attribute \src "ls180.v:6132.105-6132.149" + wire $eq$ls180.v:6132$1739_Y + attribute \src "ls180.v:6134.102-6134.147" + wire $eq$ls180.v:6134$1742_Y + attribute \src "ls180.v:6135.105-6135.150" + wire $eq$ls180.v:6135$1746_Y + attribute \src "ls180.v:6137.102-6137.147" + wire $eq$ls180.v:6137$1749_Y + attribute \src "ls180.v:6138.105-6138.150" + wire $eq$ls180.v:6138$1753_Y + attribute \src "ls180.v:6140.102-6140.147" + wire $eq$ls180.v:6140$1756_Y + attribute \src "ls180.v:6141.105-6141.150" + wire $eq$ls180.v:6141$1760_Y + attribute \src "ls180.v:6143.99-6143.144" + wire $eq$ls180.v:6143$1763_Y + attribute \src "ls180.v:6144.102-6144.147" + wire $eq$ls180.v:6144$1767_Y + attribute \src "ls180.v:6146.100-6146.145" + wire $eq$ls180.v:6146$1770_Y + attribute \src "ls180.v:6147.103-6147.148" + wire $eq$ls180.v:6147$1774_Y + attribute \src "ls180.v:6149.102-6149.147" + wire $eq$ls180.v:6149$1777_Y + attribute \src "ls180.v:6150.105-6150.150" + wire $eq$ls180.v:6150$1781_Y + attribute \src "ls180.v:6152.102-6152.147" + wire $eq$ls180.v:6152$1784_Y + attribute \src "ls180.v:6153.105-6153.150" + wire $eq$ls180.v:6153$1788_Y + attribute \src "ls180.v:6155.102-6155.147" + wire $eq$ls180.v:6155$1791_Y + attribute \src "ls180.v:6156.105-6156.150" + wire $eq$ls180.v:6156$1795_Y + attribute \src "ls180.v:6158.102-6158.147" + wire $eq$ls180.v:6158$1798_Y + attribute \src "ls180.v:6159.105-6159.150" + wire $eq$ls180.v:6159$1802_Y + attribute \src "ls180.v:6181.32-6181.78" + wire $eq$ls180.v:6181$1804_Y + attribute \src "ls180.v:6183.102-6183.146" + wire $eq$ls180.v:6183$1806_Y + attribute \src "ls180.v:6184.105-6184.149" + wire $eq$ls180.v:6184$1810_Y + attribute \src "ls180.v:6186.107-6186.151" + wire $eq$ls180.v:6186$1813_Y + attribute \src "ls180.v:6187.110-6187.154" + wire $eq$ls180.v:6187$1817_Y + attribute \src "ls180.v:6189.107-6189.151" + wire $eq$ls180.v:6189$1820_Y + attribute \src "ls180.v:6190.110-6190.154" + wire $eq$ls180.v:6190$1824_Y + attribute \src "ls180.v:6192.100-6192.144" + wire $eq$ls180.v:6192$1827_Y + attribute \src "ls180.v:6193.103-6193.147" + wire $eq$ls180.v:6193$1831_Y + attribute \src "ls180.v:6198.32-6198.77" + wire $eq$ls180.v:6198$1833_Y + attribute \src "ls180.v:6200.104-6200.148" + wire $eq$ls180.v:6200$1835_Y + attribute \src "ls180.v:6201.107-6201.151" + wire $eq$ls180.v:6201$1839_Y + attribute \src "ls180.v:6203.108-6203.152" + wire $eq$ls180.v:6203$1842_Y + attribute \src "ls180.v:6204.111-6204.155" + wire $eq$ls180.v:6204$1846_Y + attribute \src "ls180.v:6206.98-6206.142" + wire $eq$ls180.v:6206$1849_Y + attribute \src "ls180.v:6207.101-6207.145" + wire $eq$ls180.v:6207$1853_Y + attribute \src "ls180.v:6209.108-6209.152" + wire $eq$ls180.v:6209$1856_Y + attribute \src "ls180.v:6210.111-6210.155" + wire $eq$ls180.v:6210$1860_Y + attribute \src "ls180.v:6212.108-6212.152" + wire $eq$ls180.v:6212$1863_Y + attribute \src "ls180.v:6213.111-6213.155" + wire $eq$ls180.v:6213$1867_Y + attribute \src "ls180.v:6215.109-6215.153" + wire $eq$ls180.v:6215$1870_Y + attribute \src "ls180.v:6216.112-6216.156" + wire $eq$ls180.v:6216$1874_Y + attribute \src "ls180.v:6218.107-6218.151" + wire $eq$ls180.v:6218$1877_Y + attribute \src "ls180.v:6219.110-6219.154" + wire $eq$ls180.v:6219$1881_Y + attribute \src "ls180.v:6221.107-6221.151" + wire $eq$ls180.v:6221$1884_Y + attribute \src "ls180.v:6222.110-6222.154" + wire $eq$ls180.v:6222$1888_Y + attribute \src "ls180.v:6224.107-6224.151" + wire $eq$ls180.v:6224$1891_Y + attribute \src "ls180.v:6225.110-6225.154" + wire $eq$ls180.v:6225$1895_Y + attribute \src "ls180.v:6227.107-6227.151" + wire $eq$ls180.v:6227$1898_Y + attribute \src "ls180.v:6228.110-6228.154" + wire $eq$ls180.v:6228$1902_Y + attribute \src "ls180.v:6243.33-6243.79" + wire $eq$ls180.v:6243$1904_Y + attribute \src "ls180.v:6245.102-6245.147" + wire $eq$ls180.v:6245$1906_Y + attribute \src "ls180.v:6246.105-6246.150" + wire $eq$ls180.v:6246$1910_Y + attribute \src "ls180.v:6248.102-6248.147" + wire $eq$ls180.v:6248$1913_Y + attribute \src "ls180.v:6249.105-6249.150" + wire $eq$ls180.v:6249$1917_Y + attribute \src "ls180.v:6251.100-6251.145" + wire $eq$ls180.v:6251$1920_Y + attribute \src "ls180.v:6252.103-6252.148" + wire $eq$ls180.v:6252$1924_Y + attribute \src "ls180.v:6254.99-6254.144" + wire $eq$ls180.v:6254$1927_Y + attribute \src "ls180.v:6255.102-6255.147" + wire $eq$ls180.v:6255$1931_Y + attribute \src "ls180.v:6257.98-6257.143" + wire $eq$ls180.v:6257$1934_Y + attribute \src "ls180.v:6258.101-6258.146" + wire $eq$ls180.v:6258$1938_Y + attribute \src "ls180.v:6260.97-6260.142" + wire $eq$ls180.v:6260$1941_Y + attribute \src "ls180.v:6261.100-6261.145" + wire $eq$ls180.v:6261$1945_Y + attribute \src "ls180.v:6263.103-6263.148" + wire $eq$ls180.v:6263$1948_Y + attribute \src "ls180.v:6264.106-6264.151" + wire $eq$ls180.v:6264$1952_Y + attribute \src "ls180.v:6283.33-6283.80" + wire $eq$ls180.v:6283$1955_Y + attribute \src "ls180.v:6285.102-6285.147" + wire $eq$ls180.v:6285$1957_Y + attribute \src "ls180.v:6286.105-6286.150" + wire $eq$ls180.v:6286$1961_Y + attribute \src "ls180.v:6288.102-6288.147" + wire $eq$ls180.v:6288$1964_Y + attribute \src "ls180.v:6289.105-6289.150" + wire $eq$ls180.v:6289$1968_Y + attribute \src "ls180.v:6291.100-6291.145" + wire $eq$ls180.v:6291$1971_Y + attribute \src "ls180.v:6292.103-6292.148" + wire $eq$ls180.v:6292$1975_Y + attribute \src "ls180.v:6294.99-6294.144" + wire $eq$ls180.v:6294$1978_Y + attribute \src "ls180.v:6295.102-6295.147" + wire $eq$ls180.v:6295$1982_Y + attribute \src "ls180.v:6297.98-6297.143" + wire $eq$ls180.v:6297$1985_Y + attribute \src "ls180.v:6298.101-6298.146" + wire $eq$ls180.v:6298$1989_Y + attribute \src "ls180.v:6300.97-6300.142" + wire $eq$ls180.v:6300$1992_Y + attribute \src "ls180.v:6301.100-6301.145" + wire $eq$ls180.v:6301$1996_Y + attribute \src "ls180.v:6303.103-6303.148" + wire $eq$ls180.v:6303$1999_Y + attribute \src "ls180.v:6304.106-6304.151" + wire $eq$ls180.v:6304$2003_Y + attribute \src "ls180.v:6306.106-6306.151" + wire $eq$ls180.v:6306$2006_Y + attribute \src "ls180.v:6307.109-6307.154" + wire $eq$ls180.v:6307$2010_Y + attribute \src "ls180.v:6309.106-6309.151" + wire $eq$ls180.v:6309$2013_Y + attribute \src "ls180.v:6310.109-6310.154" + wire $eq$ls180.v:6310$2017_Y + attribute \src "ls180.v:6331.33-6331.79" + wire $eq$ls180.v:6331$2020_Y + attribute \src "ls180.v:6333.99-6333.144" + wire $eq$ls180.v:6333$2022_Y + attribute \src "ls180.v:6334.102-6334.147" + wire $eq$ls180.v:6334$2026_Y + attribute \src "ls180.v:6336.99-6336.144" + wire $eq$ls180.v:6336$2029_Y + attribute \src "ls180.v:6337.102-6337.147" + wire $eq$ls180.v:6337$2033_Y + attribute \src "ls180.v:6339.99-6339.144" + wire $eq$ls180.v:6339$2036_Y + attribute \src "ls180.v:6340.102-6340.147" + wire $eq$ls180.v:6340$2040_Y + attribute \src "ls180.v:6342.99-6342.144" + wire $eq$ls180.v:6342$2043_Y + attribute \src "ls180.v:6343.102-6343.147" + wire $eq$ls180.v:6343$2047_Y + attribute \src "ls180.v:6345.101-6345.146" + wire $eq$ls180.v:6345$2050_Y + attribute \src "ls180.v:6346.104-6346.149" + wire $eq$ls180.v:6346$2054_Y + attribute \src "ls180.v:6348.101-6348.146" + wire $eq$ls180.v:6348$2057_Y + attribute \src "ls180.v:6349.104-6349.149" + wire $eq$ls180.v:6349$2061_Y + attribute \src "ls180.v:6351.101-6351.146" + wire $eq$ls180.v:6351$2064_Y + attribute \src "ls180.v:6352.104-6352.149" + wire $eq$ls180.v:6352$2068_Y + attribute \src "ls180.v:6354.101-6354.146" + wire $eq$ls180.v:6354$2071_Y + attribute \src "ls180.v:6355.104-6355.149" + wire $eq$ls180.v:6355$2075_Y + attribute \src "ls180.v:6357.97-6357.142" + wire $eq$ls180.v:6357$2078_Y + attribute \src "ls180.v:6358.100-6358.145" + wire $eq$ls180.v:6358$2082_Y + attribute \src "ls180.v:6360.107-6360.152" + wire $eq$ls180.v:6360$2085_Y + attribute \src "ls180.v:6361.110-6361.155" + wire $eq$ls180.v:6361$2089_Y + attribute \src "ls180.v:6363.100-6363.146" + wire $eq$ls180.v:6363$2092_Y + attribute \src "ls180.v:6364.103-6364.149" + wire $eq$ls180.v:6364$2096_Y + attribute \src "ls180.v:6366.100-6366.146" + wire $eq$ls180.v:6366$2099_Y + attribute \src "ls180.v:6367.103-6367.149" + wire $eq$ls180.v:6367$2103_Y + attribute \src "ls180.v:6369.100-6369.146" + wire $eq$ls180.v:6369$2106_Y + attribute \src "ls180.v:6370.103-6370.149" + wire $eq$ls180.v:6370$2110_Y + attribute \src "ls180.v:6372.100-6372.146" + wire $eq$ls180.v:6372$2113_Y + attribute \src "ls180.v:6373.103-6373.149" + wire $eq$ls180.v:6373$2117_Y + attribute \src "ls180.v:6375.112-6375.158" + wire $eq$ls180.v:6375$2120_Y + attribute \src "ls180.v:6376.115-6376.161" + wire $eq$ls180.v:6376$2124_Y + attribute \src "ls180.v:6378.113-6378.159" + wire $eq$ls180.v:6378$2127_Y + attribute \src "ls180.v:6379.116-6379.162" + wire $eq$ls180.v:6379$2131_Y + attribute \src "ls180.v:6381.104-6381.150" + wire $eq$ls180.v:6381$2134_Y + attribute \src "ls180.v:6382.107-6382.153" + wire $eq$ls180.v:6382$2138_Y + attribute \src "ls180.v:6399.33-6399.79" + wire $eq$ls180.v:6399$2140_Y + attribute \src "ls180.v:6401.90-6401.135" + wire $eq$ls180.v:6401$2142_Y + attribute \src "ls180.v:6402.93-6402.138" + wire $eq$ls180.v:6402$2146_Y + attribute \src "ls180.v:6404.100-6404.145" + wire $eq$ls180.v:6404$2149_Y + attribute \src "ls180.v:6405.103-6405.148" + wire $eq$ls180.v:6405$2153_Y + attribute \src "ls180.v:6407.101-6407.146" + wire $eq$ls180.v:6407$2156_Y + attribute \src "ls180.v:6408.104-6408.149" + wire $eq$ls180.v:6408$2160_Y + attribute \src "ls180.v:6410.105-6410.150" + wire $eq$ls180.v:6410$2163_Y + attribute \src "ls180.v:6411.108-6411.153" + wire $eq$ls180.v:6411$2167_Y + attribute \src "ls180.v:6413.106-6413.151" + wire $eq$ls180.v:6413$2170_Y + attribute \src "ls180.v:6414.109-6414.154" + wire $eq$ls180.v:6414$2174_Y + attribute \src "ls180.v:6416.104-6416.149" + wire $eq$ls180.v:6416$2177_Y + attribute \src "ls180.v:6417.107-6417.152" + wire $eq$ls180.v:6417$2181_Y + attribute \src "ls180.v:6419.101-6419.146" + wire $eq$ls180.v:6419$2184_Y + attribute \src "ls180.v:6420.104-6420.149" + wire $eq$ls180.v:6420$2188_Y + attribute \src "ls180.v:6422.100-6422.145" + wire $eq$ls180.v:6422$2191_Y + attribute \src "ls180.v:6423.103-6423.148" + wire $eq$ls180.v:6423$2195_Y + attribute \src "ls180.v:6433.33-6433.79" + wire $eq$ls180.v:6433$2197_Y + attribute \src "ls180.v:6435.106-6435.151" + wire $eq$ls180.v:6435$2199_Y + attribute \src "ls180.v:6436.109-6436.154" + wire $eq$ls180.v:6436$2203_Y + attribute \src "ls180.v:6438.106-6438.151" + wire $eq$ls180.v:6438$2206_Y + attribute \src "ls180.v:6439.109-6439.154" + wire $eq$ls180.v:6439$2210_Y + attribute \src "ls180.v:6441.106-6441.151" + wire $eq$ls180.v:6441$2213_Y + attribute \src "ls180.v:6442.109-6442.154" + wire $eq$ls180.v:6442$2217_Y + attribute \src "ls180.v:6444.106-6444.151" + wire $eq$ls180.v:6444$2220_Y + attribute \src "ls180.v:6445.109-6445.154" + wire $eq$ls180.v:6445$2224_Y + attribute \src "ls180.v:6826.41-6826.81" + wire $eq$ls180.v:6826$2261_Y + attribute \src "ls180.v:6826.144-6826.177" + wire $eq$ls180.v:6826$2262_Y + attribute \src "ls180.v:6826.219-6826.252" + wire $eq$ls180.v:6826$2265_Y + attribute \src "ls180.v:6826.294-6826.327" + wire $eq$ls180.v:6826$2268_Y + attribute \src "ls180.v:6850.41-6850.81" + wire $eq$ls180.v:6850$2277_Y + attribute \src "ls180.v:6850.144-6850.177" + wire $eq$ls180.v:6850$2278_Y + attribute \src "ls180.v:6850.219-6850.252" + wire $eq$ls180.v:6850$2281_Y + attribute \src "ls180.v:6850.294-6850.327" + wire $eq$ls180.v:6850$2284_Y + attribute \src "ls180.v:6874.41-6874.81" + wire $eq$ls180.v:6874$2293_Y + attribute \src "ls180.v:6874.144-6874.177" + wire $eq$ls180.v:6874$2294_Y + attribute \src "ls180.v:6874.219-6874.252" + wire $eq$ls180.v:6874$2297_Y + attribute \src "ls180.v:6874.294-6874.327" + wire $eq$ls180.v:6874$2300_Y + attribute \src "ls180.v:6898.41-6898.81" + wire $eq$ls180.v:6898$2309_Y + attribute \src "ls180.v:6898.144-6898.177" + wire $eq$ls180.v:6898$2310_Y + attribute \src "ls180.v:6898.219-6898.252" + wire $eq$ls180.v:6898$2313_Y + attribute \src "ls180.v:6898.294-6898.327" + wire $eq$ls180.v:6898$2316_Y + attribute \src "ls180.v:7491.8-7491.38" + wire $eq$ls180.v:7491$2419_Y + attribute \src "ls180.v:7522.8-7522.42" + wire $eq$ls180.v:7522$2427_Y + attribute \src "ls180.v:7542.38-7542.74" + wire $eq$ls180.v:7542$2430_Y + attribute \src "ls180.v:7549.7-7549.43" + wire $eq$ls180.v:7549$2432_Y + attribute \src "ls180.v:7556.7-7556.43" + wire $eq$ls180.v:7556$2433_Y + attribute \src "ls180.v:7564.7-7564.43" + wire $eq$ls180.v:7564$2434_Y + attribute \src "ls180.v:7616.9-7616.54" + wire $eq$ls180.v:7616$2452_Y + attribute \src "ls180.v:7662.9-7662.54" + wire $eq$ls180.v:7662$2468_Y + attribute \src "ls180.v:7708.9-7708.54" + wire $eq$ls180.v:7708$2484_Y + attribute \src "ls180.v:7754.9-7754.54" + wire $eq$ls180.v:7754$2500_Y + attribute \src "ls180.v:7904.9-7904.41" + wire $eq$ls180.v:7904$2512_Y + attribute \src "ls180.v:7919.9-7919.41" + wire $eq$ls180.v:7919$2515_Y + attribute \src "ls180.v:7925.49-7925.82" + wire $eq$ls180.v:7925$2516_Y + attribute \src "ls180.v:7925.131-7925.164" + wire $eq$ls180.v:7925$2519_Y + attribute \src "ls180.v:7925.213-7925.246" + wire $eq$ls180.v:7925$2522_Y + attribute \src "ls180.v:7925.295-7925.328" + wire $eq$ls180.v:7925$2525_Y + attribute \src "ls180.v:7926.50-7926.83" + wire $eq$ls180.v:7926$2528_Y + attribute \src "ls180.v:7926.132-7926.165" + wire $eq$ls180.v:7926$2531_Y + attribute \src "ls180.v:7926.214-7926.247" + wire $eq$ls180.v:7926$2534_Y + attribute \src "ls180.v:7926.296-7926.329" + wire $eq$ls180.v:7926$2537_Y + attribute \src "ls180.v:7961.9-7961.42" + wire $eq$ls180.v:7961$2549_Y + attribute \src "ls180.v:7964.10-7964.43" + wire $eq$ls180.v:7964$2550_Y + attribute \src "ls180.v:7990.9-7990.42" + wire $eq$ls180.v:7990$2556_Y + attribute \src "ls180.v:7995.10-7995.43" + wire $eq$ls180.v:7995$2557_Y + attribute \src "ls180.v:8167.9-8167.53" + wire $eq$ls180.v:8167$2601_Y + attribute \src "ls180.v:8248.9-8248.54" + wire $eq$ls180.v:8248$2613_Y + attribute \src "ls180.v:8327.9-8327.55" + wire $eq$ls180.v:8327$2625_Y + attribute \src "ls180.v:8550.9-8550.49" + wire $eq$ls180.v:8550$2658_Y + attribute \src "ls180.v:8126.8-8126.54" + wire $ge$ls180.v:8126$2593_Y + attribute \src "ls180.v:8140.8-8140.54" + wire $ge$ls180.v:8140$2597_Y + attribute \src "ls180.v:5076.47-5076.83" + wire $gt$ls180.v:5076$906_Y + attribute \src "ls180.v:5082.7-5082.43" + wire $lt$ls180.v:5082$909_Y + attribute \src "ls180.v:8121.8-8121.43" + wire $lt$ls180.v:8121$2591_Y + attribute \src "ls180.v:8135.8-8135.43" + wire $lt$ls180.v:8135$2595_Y + attribute \src "ls180.v:10052.33-10052.36" + wire width 32 $memrd$\mem$ls180.v:10052$2705_DATA + attribute \src "ls180.v:10063.12-10063.19" + wire width 25 $memrd$\storage$ls180.v:10063$2710_DATA + attribute \src "ls180.v:10070.68-10070.75" + wire width 25 $memrd$\storage$ls180.v:10070$2712_DATA + attribute \src "ls180.v:10077.14-10077.23" + wire width 25 $memrd$\storage_1$ls180.v:10077$2717_DATA + attribute \src "ls180.v:10084.68-10084.77" + wire width 25 $memrd$\storage_1$ls180.v:10084$2719_DATA + attribute \src "ls180.v:10091.14-10091.23" + wire width 25 $memrd$\storage_2$ls180.v:10091$2724_DATA + attribute \src "ls180.v:10098.68-10098.77" + wire width 25 $memrd$\storage_2$ls180.v:10098$2726_DATA + attribute \src "ls180.v:10105.14-10105.23" + wire width 25 $memrd$\storage_3$ls180.v:10105$2731_DATA + attribute \src "ls180.v:10112.68-10112.77" + wire width 25 $memrd$\storage_3$ls180.v:10112$2733_DATA + attribute \src "ls180.v:10120.14-10120.23" + wire width 10 $memrd$\storage_4$ls180.v:10120$2738_DATA + attribute \src "ls180.v:10125.15-10125.24" + wire width 10 $memrd$\storage_4$ls180.v:10125$2740_DATA + attribute \src "ls180.v:10137.14-10137.23" + wire width 10 $memrd$\storage_5$ls180.v:10137$2745_DATA + attribute \src "ls180.v:10142.15-10142.24" + wire width 10 $memrd$\storage_5$ls180.v:10142$2747_DATA + attribute \src "ls180.v:10153.14-10153.23" + wire width 10 $memrd$\storage_6$ls180.v:10153$2752_DATA + attribute \src "ls180.v:10160.45-10160.54" + wire width 10 $memrd$\storage_6$ls180.v:10160$2754_DATA + attribute \src "ls180.v:10167.14-10167.23" + wire width 10 $memrd$\storage_7$ls180.v:10167$2759_DATA + attribute \src "ls180.v:10174.45-10174.54" + wire width 10 $memrd$\storage_7$ls180.v:10174$2761_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 7 $memwr$\mem$ls180.v:10042$1_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10042$1_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10042$1_EN + attribute \src "ls180.v:0.0-0.0" + wire width 7 $memwr$\mem$ls180.v:10044$2_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10044$2_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10044$2_EN + attribute \src "ls180.v:0.0-0.0" + wire width 7 $memwr$\mem$ls180.v:10046$3_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10046$3_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10046$3_EN + attribute \src "ls180.v:0.0-0.0" + wire width 7 $memwr$\mem$ls180.v:10048$4_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10048$4_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10048$4_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage$ls180.v:10062$5_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage$ls180.v:10062$5_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage$ls180.v:10062$5_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_1$ls180.v:10076$6_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_1$ls180.v:10076$6_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_1$ls180.v:10076$6_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_2$ls180.v:10090$7_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_2$ls180.v:10090$7_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_2$ls180.v:10090$7_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_3$ls180.v:10104$8_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_3$ls180.v:10104$8_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_3$ls180.v:10104$8_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\storage_4$ls180.v:10119$9_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_4$ls180.v:10119$9_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_4$ls180.v:10119$9_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\storage_5$ls180.v:10136$10_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_5$ls180.v:10136$10_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_5$ls180.v:10136$10_EN + attribute \src "ls180.v:0.0-0.0" + wire width 5 $memwr$\storage_6$ls180.v:10152$11_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_6$ls180.v:10152$11_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_6$ls180.v:10152$11_EN + attribute \src "ls180.v:0.0-0.0" + wire width 5 $memwr$\storage_7$ls180.v:10166$12_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_7$ls180.v:10166$12_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_7$ls180.v:10166$12_EN + attribute \src "ls180.v:2949.41-2949.71" + wire $ne$ls180.v:2949$60_Y + attribute \src "ls180.v:3110.70-3110.104" + wire $ne$ls180.v:3110$74_Y + attribute \src "ls180.v:3171.8-3171.142" + wire $ne$ls180.v:3171$93_Y + attribute \src "ls180.v:3203.75-3203.133" + wire $ne$ls180.v:3203$100_Y + attribute \src "ls180.v:3204.75-3204.133" + wire $ne$ls180.v:3204$101_Y + attribute \src "ls180.v:3328.8-3328.142" + wire $ne$ls180.v:3328$123_Y + attribute \src "ls180.v:3360.75-3360.133" + wire $ne$ls180.v:3360$130_Y + attribute \src "ls180.v:3361.75-3361.133" + wire $ne$ls180.v:3361$131_Y + attribute \src "ls180.v:3485.8-3485.142" + wire $ne$ls180.v:3485$153_Y + attribute \src "ls180.v:3517.75-3517.133" + wire $ne$ls180.v:3517$160_Y + attribute \src "ls180.v:3518.75-3518.133" + wire $ne$ls180.v:3518$161_Y + attribute \src "ls180.v:3642.8-3642.142" + wire $ne$ls180.v:3642$183_Y + attribute \src "ls180.v:3674.75-3674.133" + wire $ne$ls180.v:3674$190_Y + attribute \src "ls180.v:3675.75-3675.133" + wire $ne$ls180.v:3675$191_Y + attribute \src "ls180.v:4167.47-4167.80" + wire $ne$ls180.v:4167$589_Y + attribute \src "ls180.v:4168.47-4168.79" + wire $ne$ls180.v:4168$590_Y + attribute \src "ls180.v:4197.47-4197.80" + wire $ne$ls180.v:4197$600_Y + attribute \src "ls180.v:4198.47-4198.79" + wire $ne$ls180.v:4198$601_Y + attribute \src "ls180.v:4608.32-4608.89" + wire $ne$ls180.v:4608$673_Y + attribute \src "ls180.v:5255.10-5255.56" + wire $ne$ls180.v:5255$970_Y + attribute \src "ls180.v:5360.51-5360.87" + wire $ne$ls180.v:5360$984_Y + attribute \src "ls180.v:5361.51-5361.86" + wire $ne$ls180.v:5361$985_Y + attribute \src "ls180.v:5568.51-5568.87" + wire $ne$ls180.v:5568$1015_Y + attribute \src "ls180.v:5569.51-5569.86" + wire $ne$ls180.v:5569$1016_Y + attribute \src "ls180.v:5659.79-5659.119" + wire $ne$ls180.v:5659$1027_Y + attribute \src "ls180.v:7481.7-7481.52" + wire $ne$ls180.v:7481$2414_Y + attribute \src "ls180.v:7531.9-7531.43" + wire $ne$ls180.v:7531$2428_Y + attribute \src "ls180.v:7567.8-7567.44" + wire $ne$ls180.v:7567$2435_Y + attribute \src "ls180.v:8470.9-8470.47" + wire $ne$ls180.v:8470$2645_Y + attribute \src "ls180.v:2757.45-2757.80" + wire $not$ls180.v:2757$14_Y + attribute \src "ls180.v:2796.61-2796.94" + wire $not$ls180.v:2796$19_Y + attribute \src "ls180.v:2797.61-2797.94" + wire $not$ls180.v:2797$20_Y + attribute \src "ls180.v:2817.45-2817.80" + wire $not$ls180.v:2817$25_Y + attribute \src "ls180.v:2856.61-2856.94" + wire $not$ls180.v:2856$30_Y + attribute \src "ls180.v:2857.61-2857.94" + wire $not$ls180.v:2857$31_Y + attribute \src "ls180.v:2877.45-2877.83" + wire $not$ls180.v:2877$36_Y + attribute \src "ls180.v:2916.61-2916.94" + wire $not$ls180.v:2916$41_Y + attribute \src "ls180.v:2917.61-2917.94" + wire $not$ls180.v:2917$42_Y + attribute \src "ls180.v:3059.34-3059.64" + wire $not$ls180.v:3059$66_Y + attribute \src "ls180.v:3060.31-3060.61" + wire $not$ls180.v:3060$67_Y + attribute \src "ls180.v:3061.32-3061.62" + wire $not$ls180.v:3061$68_Y + attribute \src "ls180.v:3062.32-3062.62" + wire $not$ls180.v:3062$69_Y + attribute \src "ls180.v:3104.33-3104.56" + wire $not$ls180.v:3104$72_Y + attribute \src "ls180.v:3205.58-3205.106" + wire $not$ls180.v:3205$102_Y + attribute \src "ls180.v:3259.9-3259.45" + wire $not$ls180.v:3259$107_Y + attribute \src "ls180.v:3362.58-3362.106" + wire $not$ls180.v:3362$132_Y + attribute \src "ls180.v:3416.9-3416.45" + wire $not$ls180.v:3416$137_Y + attribute \src "ls180.v:3519.58-3519.106" + wire $not$ls180.v:3519$162_Y + attribute \src "ls180.v:3573.9-3573.45" + wire $not$ls180.v:3573$167_Y + attribute \src "ls180.v:3676.58-3676.106" + wire $not$ls180.v:3676$192_Y + attribute \src "ls180.v:3730.9-3730.45" + wire $not$ls180.v:3730$197_Y + attribute \src "ls180.v:3772.149-3772.187" + wire $not$ls180.v:3772$200_Y + attribute \src "ls180.v:3772.193-3772.230" + wire $not$ls180.v:3772$202_Y + attribute \src "ls180.v:3773.149-3773.187" + wire $not$ls180.v:3773$206_Y + attribute \src "ls180.v:3773.193-3773.230" + wire $not$ls180.v:3773$208_Y + attribute \src "ls180.v:3789.43-3789.73" + wire width 2 $not$ls180.v:3789$236_Y + attribute \src "ls180.v:3792.205-3792.245" + wire $not$ls180.v:3792$239_Y + attribute \src "ls180.v:3792.251-3792.290" + wire $not$ls180.v:3792$241_Y + attribute \src "ls180.v:3792.159-3792.292" + wire $not$ls180.v:3792$243_Y + attribute \src "ls180.v:3793.205-3793.245" + wire $not$ls180.v:3793$252_Y + attribute \src "ls180.v:3793.251-3793.290" + wire $not$ls180.v:3793$254_Y + attribute \src "ls180.v:3793.159-3793.292" + wire $not$ls180.v:3793$256_Y + attribute \src "ls180.v:3794.205-3794.245" + wire $not$ls180.v:3794$265_Y + attribute \src "ls180.v:3794.251-3794.290" + wire $not$ls180.v:3794$267_Y + attribute \src "ls180.v:3794.159-3794.292" + wire $not$ls180.v:3794$269_Y + attribute \src "ls180.v:3795.205-3795.245" + wire $not$ls180.v:3795$278_Y + attribute \src "ls180.v:3795.251-3795.290" + wire $not$ls180.v:3795$280_Y + attribute \src "ls180.v:3795.159-3795.292" + wire $not$ls180.v:3795$282_Y + attribute \src "ls180.v:3822.71-3822.103" + wire $not$ls180.v:3822$293_Y + attribute \src "ls180.v:3825.205-3825.245" + wire $not$ls180.v:3825$297_Y + attribute \src "ls180.v:3825.251-3825.290" + wire $not$ls180.v:3825$299_Y + attribute \src "ls180.v:3825.159-3825.292" + wire $not$ls180.v:3825$301_Y + attribute \src "ls180.v:3826.205-3826.245" + wire $not$ls180.v:3826$310_Y + attribute \src "ls180.v:3826.251-3826.290" + wire $not$ls180.v:3826$312_Y + attribute \src "ls180.v:3826.159-3826.292" + wire $not$ls180.v:3826$314_Y + attribute \src "ls180.v:3827.205-3827.245" + wire $not$ls180.v:3827$323_Y + attribute \src "ls180.v:3827.251-3827.290" + wire $not$ls180.v:3827$325_Y + attribute \src "ls180.v:3827.159-3827.292" + wire $not$ls180.v:3827$327_Y + attribute \src "ls180.v:3828.205-3828.245" + wire $not$ls180.v:3828$336_Y + attribute \src "ls180.v:3828.251-3828.290" + wire $not$ls180.v:3828$338_Y + attribute \src "ls180.v:3828.159-3828.292" + wire $not$ls180.v:3828$340_Y + attribute \src "ls180.v:3891.71-3891.103" + wire $not$ls180.v:3891$379_Y + attribute \src "ls180.v:3912.112-3912.150" + wire $not$ls180.v:3912$382_Y + attribute \src "ls180.v:3912.156-3912.193" + wire $not$ls180.v:3912$384_Y + attribute \src "ls180.v:3912.68-3912.195" + wire $not$ls180.v:3912$386_Y + attribute \src "ls180.v:3920.11-3920.38" + wire $not$ls180.v:3920$389_Y + attribute \src "ls180.v:3950.112-3950.150" + wire $not$ls180.v:3950$391_Y + attribute \src "ls180.v:3950.156-3950.193" + wire $not$ls180.v:3950$393_Y + attribute \src "ls180.v:3950.68-3950.195" + wire $not$ls180.v:3950$395_Y + attribute \src "ls180.v:3958.11-3958.37" + wire $not$ls180.v:3958$398_Y + attribute \src "ls180.v:3968.87-3968.331" + wire $not$ls180.v:3968$410_Y + attribute \src "ls180.v:3969.35-3969.68" + wire $not$ls180.v:3969$413_Y + attribute \src "ls180.v:3969.73-3969.105" + wire $not$ls180.v:3969$414_Y + attribute \src "ls180.v:3973.87-3973.331" + wire $not$ls180.v:3973$426_Y + attribute \src "ls180.v:3974.35-3974.68" + wire $not$ls180.v:3974$429_Y + attribute \src "ls180.v:3974.73-3974.105" + wire $not$ls180.v:3974$430_Y + attribute \src "ls180.v:3978.87-3978.331" + wire $not$ls180.v:3978$442_Y + attribute \src "ls180.v:3979.35-3979.68" + wire $not$ls180.v:3979$445_Y + attribute \src "ls180.v:3979.73-3979.105" + wire $not$ls180.v:3979$446_Y + attribute \src "ls180.v:3983.87-3983.331" + wire $not$ls180.v:3983$458_Y + attribute \src "ls180.v:3984.35-3984.68" + wire $not$ls180.v:3984$461_Y + attribute \src "ls180.v:3984.73-3984.105" + wire $not$ls180.v:3984$462_Y + attribute \src "ls180.v:3988.128-3988.372" + wire $not$ls180.v:3988$475_Y + attribute \src "ls180.v:3988.502-3988.746" + wire $not$ls180.v:3988$491_Y + attribute \src "ls180.v:3988.876-3988.1120" + wire $not$ls180.v:3988$507_Y + attribute \src "ls180.v:3988.1250-3988.1494" + wire $not$ls180.v:3988$523_Y + attribute \src "ls180.v:4010.32-4010.50" + wire $not$ls180.v:4010$529_Y + attribute \src "ls180.v:4049.30-4049.50" + wire $not$ls180.v:4049$534_Y + attribute \src "ls180.v:4050.30-4050.50" + wire $not$ls180.v:4050$535_Y + attribute \src "ls180.v:4075.27-4075.48" + wire $not$ls180.v:4075$541_Y + attribute \src "ls180.v:4076.30-4076.50" + wire $not$ls180.v:4076$542_Y + attribute \src "ls180.v:4077.80-4077.98" + wire $not$ls180.v:4077$544_Y + attribute \src "ls180.v:4078.107-4078.127" + wire $not$ls180.v:4078$548_Y + attribute \src "ls180.v:4079.78-4079.103" + wire $not$ls180.v:4079$551_Y + attribute \src "ls180.v:4080.91-4080.111" + wire $not$ls180.v:4080$554_Y + attribute \src "ls180.v:4096.35-4096.64" + wire $not$ls180.v:4096$563_Y + attribute \src "ls180.v:4097.36-4097.67" + wire $not$ls180.v:4097$564_Y + attribute \src "ls180.v:4103.32-4103.61" + wire $not$ls180.v:4103$565_Y + attribute \src "ls180.v:4109.36-4109.67" + wire $not$ls180.v:4109$566_Y + attribute \src "ls180.v:4110.35-4110.64" + wire $not$ls180.v:4110$567_Y + attribute \src "ls180.v:4113.32-4113.63" + wire $not$ls180.v:4113$570_Y + attribute \src "ls180.v:4151.81-4151.108" + wire $not$ls180.v:4151$580_Y + attribute \src "ls180.v:4181.81-4181.108" + wire $not$ls180.v:4181$591_Y + attribute \src "ls180.v:4322.60-4322.85" + wire $not$ls180.v:4322$632_Y + attribute \src "ls180.v:4463.54-4463.96" + wire $not$ls180.v:4463$646_Y + attribute \src "ls180.v:4466.48-4466.86" + wire $not$ls180.v:4466$649_Y + attribute \src "ls180.v:4590.55-4590.98" + wire $not$ls180.v:4590$667_Y + attribute \src "ls180.v:4593.49-4593.88" + wire $not$ls180.v:4593$670_Y + attribute \src "ls180.v:4643.30-4643.58" + wire $not$ls180.v:4643$676_Y + attribute \src "ls180.v:4724.56-4724.100" + wire $not$ls180.v:4724$682_Y + attribute \src "ls180.v:4727.50-4727.90" + wire $not$ls180.v:4727$685_Y + attribute \src "ls180.v:4843.42-4843.74" + wire $not$ls180.v:4843$701_Y + attribute \src "ls180.v:5367.50-5367.88" + wire $not$ls180.v:5367$986_Y + attribute \src "ls180.v:5379.52-5379.102" + wire $not$ls180.v:5379$989_Y + attribute \src "ls180.v:5438.38-5438.74" + wire $not$ls180.v:5438$996_Y + attribute \src "ls180.v:5739.69-5739.88" + wire $not$ls180.v:5739$1065_Y + attribute \src "ls180.v:5756.63-5756.94" + wire $not$ls180.v:5756$1086_Y + attribute \src "ls180.v:5759.65-5759.96" + wire $not$ls180.v:5759$1093_Y + attribute \src "ls180.v:5762.65-5762.96" + wire $not$ls180.v:5762$1100_Y + attribute \src "ls180.v:5765.65-5765.96" + wire $not$ls180.v:5765$1107_Y + attribute \src "ls180.v:5768.65-5768.96" + wire $not$ls180.v:5768$1114_Y + attribute \src "ls180.v:5771.68-5771.99" + wire $not$ls180.v:5771$1121_Y + attribute \src "ls180.v:5774.68-5774.99" + wire $not$ls180.v:5774$1128_Y + attribute \src "ls180.v:5777.68-5777.99" + wire $not$ls180.v:5777$1135_Y + attribute \src "ls180.v:5780.68-5780.99" + wire $not$ls180.v:5780$1142_Y + attribute \src "ls180.v:5794.60-5794.91" + wire $not$ls180.v:5794$1150_Y + attribute \src "ls180.v:5797.60-5797.91" + wire $not$ls180.v:5797$1157_Y + attribute \src "ls180.v:5800.60-5800.91" + wire $not$ls180.v:5800$1164_Y + attribute \src "ls180.v:5803.60-5803.91" + wire $not$ls180.v:5803$1171_Y + attribute \src "ls180.v:5806.61-5806.92" + wire $not$ls180.v:5806$1178_Y + attribute \src "ls180.v:5809.61-5809.92" + wire $not$ls180.v:5809$1185_Y + attribute \src "ls180.v:5820.59-5820.90" + wire $not$ls180.v:5820$1193_Y + attribute \src "ls180.v:5823.58-5823.89" + wire $not$ls180.v:5823$1200_Y + attribute \src "ls180.v:5834.64-5834.95" + wire $not$ls180.v:5834$1208_Y + attribute \src "ls180.v:5837.63-5837.94" + wire $not$ls180.v:5837$1215_Y + attribute \src "ls180.v:5840.63-5840.94" + wire $not$ls180.v:5840$1222_Y + attribute \src "ls180.v:5843.63-5843.94" + wire $not$ls180.v:5843$1229_Y + attribute \src "ls180.v:5846.63-5846.94" + wire $not$ls180.v:5846$1236_Y + attribute \src "ls180.v:5849.64-5849.95" + wire $not$ls180.v:5849$1243_Y + attribute \src "ls180.v:5852.64-5852.95" + wire $not$ls180.v:5852$1250_Y + attribute \src "ls180.v:5855.64-5855.95" + wire $not$ls180.v:5855$1257_Y + attribute \src "ls180.v:5858.64-5858.95" + wire $not$ls180.v:5858$1264_Y + attribute \src "ls180.v:5871.64-5871.95" + wire $not$ls180.v:5871$1272_Y + attribute \src "ls180.v:5874.63-5874.94" + wire $not$ls180.v:5874$1279_Y + attribute \src "ls180.v:5877.63-5877.94" + wire $not$ls180.v:5877$1286_Y + attribute \src "ls180.v:5880.63-5880.94" + wire $not$ls180.v:5880$1293_Y + attribute \src "ls180.v:5883.63-5883.94" + wire $not$ls180.v:5883$1300_Y + attribute \src "ls180.v:5886.64-5886.95" + wire $not$ls180.v:5886$1307_Y + attribute \src "ls180.v:5889.64-5889.95" + wire $not$ls180.v:5889$1314_Y + attribute \src "ls180.v:5892.64-5892.95" + wire $not$ls180.v:5892$1321_Y + attribute \src "ls180.v:5895.64-5895.95" + wire $not$ls180.v:5895$1328_Y + attribute \src "ls180.v:5908.66-5908.97" + wire $not$ls180.v:5908$1336_Y + attribute \src "ls180.v:5911.66-5911.97" + wire $not$ls180.v:5911$1343_Y + attribute \src "ls180.v:5914.66-5914.97" + wire $not$ls180.v:5914$1350_Y + attribute \src "ls180.v:5917.66-5917.97" + wire $not$ls180.v:5917$1357_Y + attribute \src "ls180.v:5920.66-5920.97" + wire $not$ls180.v:5920$1364_Y + attribute \src "ls180.v:5923.66-5923.97" + wire $not$ls180.v:5923$1371_Y + attribute \src "ls180.v:5926.66-5926.97" + wire $not$ls180.v:5926$1378_Y + attribute \src "ls180.v:5929.66-5929.97" + wire $not$ls180.v:5929$1385_Y + attribute \src "ls180.v:5932.68-5932.99" + wire $not$ls180.v:5932$1392_Y + attribute \src "ls180.v:5935.68-5935.99" + wire $not$ls180.v:5935$1399_Y + attribute \src "ls180.v:5938.68-5938.99" + wire $not$ls180.v:5938$1406_Y + attribute \src "ls180.v:5941.68-5941.99" + wire $not$ls180.v:5941$1413_Y + attribute \src "ls180.v:5944.68-5944.99" + wire $not$ls180.v:5944$1420_Y + attribute \src "ls180.v:5947.65-5947.96" + wire $not$ls180.v:5947$1427_Y + attribute \src "ls180.v:5950.66-5950.97" + wire $not$ls180.v:5950$1434_Y + attribute \src "ls180.v:5970.70-5970.101" + wire $not$ls180.v:5970$1442_Y + attribute \src "ls180.v:5973.70-5973.101" + wire $not$ls180.v:5973$1449_Y + attribute \src "ls180.v:5976.70-5976.101" + wire $not$ls180.v:5976$1456_Y + attribute \src "ls180.v:5979.70-5979.101" + wire $not$ls180.v:5979$1463_Y + attribute \src "ls180.v:5982.69-5982.100" + wire $not$ls180.v:5982$1470_Y + attribute \src "ls180.v:5985.69-5985.100" + wire $not$ls180.v:5985$1477_Y + attribute \src "ls180.v:5988.69-5988.100" + wire $not$ls180.v:5988$1484_Y + attribute \src "ls180.v:5991.69-5991.100" + wire $not$ls180.v:5991$1491_Y + attribute \src "ls180.v:5994.60-5994.91" + wire $not$ls180.v:5994$1498_Y + attribute \src "ls180.v:5997.71-5997.102" + wire $not$ls180.v:5997$1505_Y + attribute \src "ls180.v:6000.71-6000.102" + wire $not$ls180.v:6000$1512_Y + attribute \src "ls180.v:6003.71-6003.102" + wire $not$ls180.v:6003$1519_Y + attribute \src "ls180.v:6006.71-6006.102" + wire $not$ls180.v:6006$1526_Y + attribute \src "ls180.v:6009.71-6009.102" + wire $not$ls180.v:6009$1533_Y + attribute \src "ls180.v:6012.71-6012.102" + wire $not$ls180.v:6012$1540_Y + attribute \src "ls180.v:6015.70-6015.101" + wire $not$ls180.v:6015$1547_Y + attribute \src "ls180.v:6018.70-6018.101" + wire $not$ls180.v:6018$1554_Y + attribute \src "ls180.v:6021.70-6021.101" + wire $not$ls180.v:6021$1561_Y + attribute \src "ls180.v:6024.70-6024.101" + wire $not$ls180.v:6024$1568_Y + attribute \src "ls180.v:6027.70-6027.101" + wire $not$ls180.v:6027$1575_Y + attribute \src "ls180.v:6030.70-6030.101" + wire $not$ls180.v:6030$1582_Y + attribute \src "ls180.v:6033.70-6033.101" + wire $not$ls180.v:6033$1589_Y + attribute \src "ls180.v:6036.70-6036.101" + wire $not$ls180.v:6036$1596_Y + attribute \src "ls180.v:6039.70-6039.101" + wire $not$ls180.v:6039$1603_Y + attribute \src "ls180.v:6042.70-6042.101" + wire $not$ls180.v:6042$1610_Y + attribute \src "ls180.v:6045.66-6045.97" + wire $not$ls180.v:6045$1617_Y + attribute \src "ls180.v:6048.67-6048.98" + wire $not$ls180.v:6048$1624_Y + attribute \src "ls180.v:6051.70-6051.101" + wire $not$ls180.v:6051$1631_Y + attribute \src "ls180.v:6054.70-6054.101" + wire $not$ls180.v:6054$1638_Y + attribute \src "ls180.v:6057.69-6057.100" + wire $not$ls180.v:6057$1645_Y + attribute \src "ls180.v:6060.69-6060.100" + wire $not$ls180.v:6060$1652_Y + attribute \src "ls180.v:6063.69-6063.100" + wire $not$ls180.v:6063$1659_Y + attribute \src "ls180.v:6066.69-6066.100" + wire $not$ls180.v:6066$1666_Y + attribute \src "ls180.v:6105.66-6105.97" + wire $not$ls180.v:6105$1674_Y + attribute \src "ls180.v:6108.66-6108.97" + wire $not$ls180.v:6108$1681_Y + attribute \src "ls180.v:6111.66-6111.97" + wire $not$ls180.v:6111$1688_Y + attribute \src "ls180.v:6114.66-6114.97" + wire $not$ls180.v:6114$1695_Y + attribute \src "ls180.v:6117.66-6117.97" + wire $not$ls180.v:6117$1702_Y + attribute \src "ls180.v:6120.66-6120.97" + wire $not$ls180.v:6120$1709_Y + attribute \src "ls180.v:6123.66-6123.97" + wire $not$ls180.v:6123$1716_Y + attribute \src "ls180.v:6126.66-6126.97" + wire $not$ls180.v:6126$1723_Y + attribute \src "ls180.v:6129.68-6129.99" + wire $not$ls180.v:6129$1730_Y + attribute \src "ls180.v:6132.68-6132.99" + wire $not$ls180.v:6132$1737_Y + attribute \src "ls180.v:6135.68-6135.99" + wire $not$ls180.v:6135$1744_Y + attribute \src "ls180.v:6138.68-6138.99" + wire $not$ls180.v:6138$1751_Y + attribute \src "ls180.v:6141.68-6141.99" + wire $not$ls180.v:6141$1758_Y + attribute \src "ls180.v:6144.65-6144.96" + wire $not$ls180.v:6144$1765_Y + attribute \src "ls180.v:6147.66-6147.97" + wire $not$ls180.v:6147$1772_Y + attribute \src "ls180.v:6150.68-6150.99" + wire $not$ls180.v:6150$1779_Y + attribute \src "ls180.v:6153.68-6153.99" + wire $not$ls180.v:6153$1786_Y + attribute \src "ls180.v:6156.68-6156.99" + wire $not$ls180.v:6156$1793_Y + attribute \src "ls180.v:6159.68-6159.99" + wire $not$ls180.v:6159$1800_Y + attribute \src "ls180.v:6184.68-6184.99" + wire $not$ls180.v:6184$1808_Y + attribute \src "ls180.v:6187.73-6187.104" + wire $not$ls180.v:6187$1815_Y + attribute \src "ls180.v:6190.73-6190.104" + wire $not$ls180.v:6190$1822_Y + attribute \src "ls180.v:6193.66-6193.97" + wire $not$ls180.v:6193$1829_Y + attribute \src "ls180.v:6201.70-6201.101" + wire $not$ls180.v:6201$1837_Y + attribute \src "ls180.v:6204.74-6204.105" + wire $not$ls180.v:6204$1844_Y + attribute \src "ls180.v:6207.64-6207.95" + wire $not$ls180.v:6207$1851_Y + attribute \src "ls180.v:6210.74-6210.105" + wire $not$ls180.v:6210$1858_Y + attribute \src "ls180.v:6213.74-6213.105" + wire $not$ls180.v:6213$1865_Y + attribute \src "ls180.v:6216.75-6216.106" + wire $not$ls180.v:6216$1872_Y + attribute \src "ls180.v:6219.73-6219.104" + wire $not$ls180.v:6219$1879_Y + attribute \src "ls180.v:6222.73-6222.104" + wire $not$ls180.v:6222$1886_Y + attribute \src "ls180.v:6225.73-6225.104" + wire $not$ls180.v:6225$1893_Y + attribute \src "ls180.v:6228.73-6228.104" + wire $not$ls180.v:6228$1900_Y + attribute \src "ls180.v:6246.67-6246.99" + wire $not$ls180.v:6246$1908_Y + attribute \src "ls180.v:6249.67-6249.99" + wire $not$ls180.v:6249$1915_Y + attribute \src "ls180.v:6252.65-6252.97" + wire $not$ls180.v:6252$1922_Y + attribute \src "ls180.v:6255.64-6255.96" + wire $not$ls180.v:6255$1929_Y + attribute \src "ls180.v:6258.63-6258.95" + wire $not$ls180.v:6258$1936_Y + attribute \src "ls180.v:6261.62-6261.94" + wire $not$ls180.v:6261$1943_Y + attribute \src "ls180.v:6264.68-6264.100" + wire $not$ls180.v:6264$1950_Y + attribute \src "ls180.v:6286.67-6286.99" + wire $not$ls180.v:6286$1959_Y + attribute \src "ls180.v:6289.67-6289.99" + wire $not$ls180.v:6289$1966_Y + attribute \src "ls180.v:6292.65-6292.97" + wire $not$ls180.v:6292$1973_Y + attribute \src "ls180.v:6295.64-6295.96" + wire $not$ls180.v:6295$1980_Y + attribute \src "ls180.v:6298.63-6298.95" + wire $not$ls180.v:6298$1987_Y + attribute \src "ls180.v:6301.62-6301.94" + wire $not$ls180.v:6301$1994_Y + attribute \src "ls180.v:6304.68-6304.100" + wire $not$ls180.v:6304$2001_Y + attribute \src "ls180.v:6307.71-6307.103" + wire $not$ls180.v:6307$2008_Y + attribute \src "ls180.v:6310.71-6310.103" + wire $not$ls180.v:6310$2015_Y + attribute \src "ls180.v:6334.64-6334.96" + wire $not$ls180.v:6334$2024_Y + attribute \src "ls180.v:6337.64-6337.96" + wire $not$ls180.v:6337$2031_Y + attribute \src "ls180.v:6340.64-6340.96" + wire $not$ls180.v:6340$2038_Y + attribute \src "ls180.v:6343.64-6343.96" + wire $not$ls180.v:6343$2045_Y + attribute \src "ls180.v:6346.66-6346.98" + wire $not$ls180.v:6346$2052_Y + attribute \src "ls180.v:6349.66-6349.98" + wire $not$ls180.v:6349$2059_Y + attribute \src "ls180.v:6352.66-6352.98" + wire $not$ls180.v:6352$2066_Y + attribute \src "ls180.v:6355.66-6355.98" + wire $not$ls180.v:6355$2073_Y + attribute \src "ls180.v:6358.62-6358.94" + wire $not$ls180.v:6358$2080_Y + attribute \src "ls180.v:6361.72-6361.104" + wire $not$ls180.v:6361$2087_Y + attribute \src "ls180.v:6364.65-6364.97" + wire $not$ls180.v:6364$2094_Y + attribute \src "ls180.v:6367.65-6367.97" + wire $not$ls180.v:6367$2101_Y + attribute \src "ls180.v:6370.65-6370.97" + wire $not$ls180.v:6370$2108_Y + attribute \src "ls180.v:6373.65-6373.97" + wire $not$ls180.v:6373$2115_Y + attribute \src "ls180.v:6376.77-6376.109" + wire $not$ls180.v:6376$2122_Y + attribute \src "ls180.v:6379.78-6379.110" + wire $not$ls180.v:6379$2129_Y + attribute \src "ls180.v:6382.69-6382.101" + wire $not$ls180.v:6382$2136_Y + attribute \src "ls180.v:6402.55-6402.87" + wire $not$ls180.v:6402$2144_Y + attribute \src "ls180.v:6405.65-6405.97" + wire $not$ls180.v:6405$2151_Y + attribute \src "ls180.v:6408.66-6408.98" + wire $not$ls180.v:6408$2158_Y + attribute \src "ls180.v:6411.70-6411.102" + wire $not$ls180.v:6411$2165_Y + attribute \src "ls180.v:6414.71-6414.103" + wire $not$ls180.v:6414$2172_Y + attribute \src "ls180.v:6417.69-6417.101" + wire $not$ls180.v:6417$2179_Y + attribute \src "ls180.v:6420.66-6420.98" + wire $not$ls180.v:6420$2186_Y + attribute \src "ls180.v:6423.65-6423.97" + wire $not$ls180.v:6423$2193_Y + attribute \src "ls180.v:6436.71-6436.103" + wire $not$ls180.v:6436$2201_Y + attribute \src "ls180.v:6439.71-6439.103" + wire $not$ls180.v:6439$2208_Y + attribute \src "ls180.v:6442.71-6442.103" + wire $not$ls180.v:6442$2215_Y + attribute \src "ls180.v:6445.71-6445.103" + wire $not$ls180.v:6445$2222_Y + attribute \src "ls180.v:6826.86-6826.330" + wire $not$ls180.v:6826$2271_Y + attribute \src "ls180.v:6850.86-6850.330" + wire $not$ls180.v:6850$2287_Y + attribute \src "ls180.v:6874.86-6874.330" + wire $not$ls180.v:6874$2303_Y + attribute \src "ls180.v:6898.86-6898.330" + wire $not$ls180.v:6898$2319_Y + attribute \src "ls180.v:7396.18-7396.42" + wire $not$ls180.v:7396$2372_Y + attribute \src "ls180.v:7487.72-7487.101" + wire $not$ls180.v:7487$2417_Y + attribute \src "ls180.v:7506.8-7506.38" + wire $not$ls180.v:7506$2421_Y + attribute \src "ls180.v:7514.32-7514.55" + wire $not$ls180.v:7514$2423_Y + attribute \src "ls180.v:7584.136-7584.189" + wire $not$ls180.v:7584$2438_Y + attribute \src "ls180.v:7590.136-7590.189" + wire $not$ls180.v:7590$2443_Y + attribute \src "ls180.v:7591.8-7591.61" + wire $not$ls180.v:7591$2445_Y + attribute \src "ls180.v:7599.8-7599.56" + wire $not$ls180.v:7599$2448_Y + attribute \src "ls180.v:7614.8-7614.46" + wire $not$ls180.v:7614$2450_Y + attribute \src "ls180.v:7630.136-7630.189" + wire $not$ls180.v:7630$2454_Y + attribute \src "ls180.v:7636.136-7636.189" + wire $not$ls180.v:7636$2459_Y + attribute \src "ls180.v:7637.8-7637.61" + wire $not$ls180.v:7637$2461_Y + attribute \src "ls180.v:7645.8-7645.56" + wire $not$ls180.v:7645$2464_Y + attribute \src "ls180.v:7660.8-7660.46" + wire $not$ls180.v:7660$2466_Y + attribute \src "ls180.v:7676.136-7676.189" + wire $not$ls180.v:7676$2470_Y + attribute \src "ls180.v:7682.136-7682.189" + wire $not$ls180.v:7682$2475_Y + attribute \src "ls180.v:7683.8-7683.61" + wire $not$ls180.v:7683$2477_Y + attribute \src "ls180.v:7691.8-7691.56" + wire $not$ls180.v:7691$2480_Y + attribute \src "ls180.v:7706.8-7706.46" + wire $not$ls180.v:7706$2482_Y + attribute \src "ls180.v:7722.136-7722.189" + wire $not$ls180.v:7722$2486_Y + attribute \src "ls180.v:7728.136-7728.189" + wire $not$ls180.v:7728$2491_Y + attribute \src "ls180.v:7729.8-7729.61" + wire $not$ls180.v:7729$2493_Y + attribute \src "ls180.v:7737.8-7737.56" + wire $not$ls180.v:7737$2496_Y + attribute \src "ls180.v:7752.8-7752.46" + wire $not$ls180.v:7752$2498_Y + attribute \src "ls180.v:7760.7-7760.22" + wire $not$ls180.v:7760$2501_Y + attribute \src "ls180.v:7763.8-7763.29" + wire $not$ls180.v:7763$2502_Y + attribute \src "ls180.v:7767.7-7767.22" + wire $not$ls180.v:7767$2504_Y + attribute \src "ls180.v:7770.8-7770.29" + wire $not$ls180.v:7770$2505_Y + attribute \src "ls180.v:7889.30-7889.60" + wire $not$ls180.v:7889$2507_Y + attribute \src "ls180.v:7890.30-7890.60" + wire $not$ls180.v:7890$2508_Y + attribute \src "ls180.v:7891.29-7891.59" + wire $not$ls180.v:7891$2509_Y + attribute \src "ls180.v:7902.8-7902.33" + wire $not$ls180.v:7902$2510_Y + attribute \src "ls180.v:7917.8-7917.33" + wire $not$ls180.v:7917$2513_Y + attribute \src "ls180.v:7953.36-7953.58" + wire $not$ls180.v:7953$2543_Y + attribute \src "ls180.v:7953.64-7953.89" + wire $not$ls180.v:7953$2545_Y + attribute \src "ls180.v:7982.7-7982.29" + wire $not$ls180.v:7982$2552_Y + attribute \src "ls180.v:7983.9-7983.26" + wire $not$ls180.v:7983$2553_Y + attribute \src "ls180.v:8016.8-8016.29" + wire $not$ls180.v:8016$2559_Y + attribute \src "ls180.v:8023.8-8023.29" + wire $not$ls180.v:8023$2561_Y + attribute \src "ls180.v:8033.80-8033.106" + wire $not$ls180.v:8033$2564_Y + attribute \src "ls180.v:8039.80-8039.106" + wire $not$ls180.v:8039$2569_Y + attribute \src "ls180.v:8040.8-8040.34" + wire $not$ls180.v:8040$2571_Y + attribute \src "ls180.v:8055.80-8055.106" + wire $not$ls180.v:8055$2575_Y + attribute \src "ls180.v:8061.80-8061.106" + wire $not$ls180.v:8061$2580_Y + attribute \src "ls180.v:8062.8-8062.34" + wire $not$ls180.v:8062$2582_Y + attribute \src "ls180.v:8093.23-8093.42" + wire $not$ls180.v:8093$2586_Y + attribute \src "ls180.v:8093.47-8093.73" + wire $not$ls180.v:8093$2587_Y + attribute \src "ls180.v:8147.7-8147.31" + wire $not$ls180.v:8147$2598_Y + attribute \src "ls180.v:8219.8-8219.46" + wire $not$ls180.v:8219$2610_Y + attribute \src "ls180.v:8300.8-8300.47" + wire $not$ls180.v:8300$2622_Y + attribute \src "ls180.v:8361.8-8361.48" + wire $not$ls180.v:8361$2634_Y + attribute \src "ls180.v:8531.88-8531.118" + wire $not$ls180.v:8531$2648_Y + attribute \src "ls180.v:8537.88-8537.118" + wire $not$ls180.v:8537$2653_Y + attribute \src "ls180.v:8538.8-8538.38" + wire $not$ls180.v:8538$2655_Y + attribute \src "ls180.v:8617.88-8617.118" + wire $not$ls180.v:8617$2670_Y + attribute \src "ls180.v:8623.88-8623.118" + wire $not$ls180.v:8623$2675_Y + attribute \src "ls180.v:8624.8-8624.38" + wire $not$ls180.v:8624$2677_Y + attribute \src "ls180.v:8641.22-8641.37" + wire $not$ls180.v:8641$2681_Y + attribute \src "ls180.v:8641.42-8641.64" + wire $not$ls180.v:8641$2682_Y + attribute \src "ls180.v:8679.9-8679.28" + wire $not$ls180.v:8679$2685_Y + attribute \src "ls180.v:8698.9-8698.28" + wire $not$ls180.v:8698$2686_Y + attribute \src "ls180.v:8717.9-8717.28" + wire $not$ls180.v:8717$2687_Y + attribute \src "ls180.v:8736.9-8736.28" + wire $not$ls180.v:8736$2688_Y + attribute \src "ls180.v:8755.9-8755.28" + wire $not$ls180.v:8755$2689_Y + attribute \src "ls180.v:8776.8-8776.21" + wire $not$ls180.v:8776$2690_Y + attribute \src "ls180.v:10259.8-10259.51" + wire $or$ls180.v:10259$2762_Y + attribute \src "ls180.v:2798.10-2798.96" + wire $or$ls180.v:2798$21_Y + attribute \src "ls180.v:2858.10-2858.96" + wire $or$ls180.v:2858$32_Y + attribute \src "ls180.v:2918.10-2918.96" + wire $or$ls180.v:2918$43_Y + attribute \src "ls180.v:3110.39-3110.105" + wire $or$ls180.v:3110$75_Y + attribute \src "ls180.v:3153.59-3153.140" + wire $or$ls180.v:3153$79_Y + attribute \src "ls180.v:3154.44-3154.151" + wire $or$ls180.v:3154$80_Y + attribute \src "ls180.v:3162.45-3162.170" + wire width 13 $or$ls180.v:3162$84_Y + attribute \src "ls180.v:3199.127-3199.245" + wire $or$ls180.v:3199$97_Y + attribute \src "ls180.v:3205.57-3205.157" + wire $or$ls180.v:3205$103_Y + attribute \src "ls180.v:3310.59-3310.140" + wire $or$ls180.v:3310$109_Y + attribute \src "ls180.v:3311.44-3311.151" + wire $or$ls180.v:3311$110_Y + attribute \src "ls180.v:3319.45-3319.170" + wire width 13 $or$ls180.v:3319$114_Y + attribute \src "ls180.v:3356.127-3356.245" + wire $or$ls180.v:3356$127_Y + attribute \src "ls180.v:3362.57-3362.157" + wire $or$ls180.v:3362$133_Y + attribute \src "ls180.v:3467.59-3467.140" + wire $or$ls180.v:3467$139_Y + attribute \src "ls180.v:3468.44-3468.151" + wire $or$ls180.v:3468$140_Y + attribute \src "ls180.v:3476.45-3476.170" + wire width 13 $or$ls180.v:3476$144_Y + attribute \src "ls180.v:3513.127-3513.245" + wire $or$ls180.v:3513$157_Y + attribute \src "ls180.v:3519.57-3519.157" + wire $or$ls180.v:3519$163_Y + attribute \src "ls180.v:3624.59-3624.140" + wire $or$ls180.v:3624$169_Y + attribute \src "ls180.v:3625.44-3625.151" + wire $or$ls180.v:3625$170_Y + attribute \src "ls180.v:3633.45-3633.170" + wire width 13 $or$ls180.v:3633$174_Y + attribute \src "ls180.v:3670.127-3670.245" + wire $or$ls180.v:3670$187_Y + attribute \src "ls180.v:3676.57-3676.157" + wire $or$ls180.v:3676$193_Y + attribute \src "ls180.v:3775.107-3775.193" + wire $or$ls180.v:3775$213_Y + attribute \src "ls180.v:3778.39-3778.204" + wire $or$ls180.v:3778$219_Y + attribute \src "ls180.v:3778.38-3778.289" + wire $or$ls180.v:3778$221_Y + attribute \src "ls180.v:3778.37-3778.374" + wire $or$ls180.v:3778$223_Y + attribute \src "ls180.v:3779.40-3779.207" + wire $or$ls180.v:3779$226_Y + attribute \src "ls180.v:3779.39-3779.293" + wire $or$ls180.v:3779$228_Y + attribute \src "ls180.v:3779.38-3779.379" + wire $or$ls180.v:3779$230_Y + attribute \src "ls180.v:3792.158-3792.332" + wire $or$ls180.v:3792$244_Y + attribute \src "ls180.v:3792.75-3792.506" + wire $or$ls180.v:3792$249_Y + attribute \src "ls180.v:3793.158-3793.332" + wire $or$ls180.v:3793$257_Y + attribute \src "ls180.v:3793.75-3793.506" + wire $or$ls180.v:3793$262_Y + attribute \src "ls180.v:3794.158-3794.332" + wire $or$ls180.v:3794$270_Y + attribute \src "ls180.v:3794.75-3794.506" + wire $or$ls180.v:3794$275_Y + attribute \src "ls180.v:3795.158-3795.332" + wire $or$ls180.v:3795$283_Y + attribute \src "ls180.v:3795.75-3795.506" + wire $or$ls180.v:3795$288_Y + attribute \src "ls180.v:3822.36-3822.104" + wire $or$ls180.v:3822$294_Y + attribute \src "ls180.v:3825.158-3825.332" + wire $or$ls180.v:3825$302_Y + attribute \src "ls180.v:3825.75-3825.506" + wire $or$ls180.v:3825$307_Y + attribute \src "ls180.v:3826.158-3826.332" + wire $or$ls180.v:3826$315_Y + attribute \src "ls180.v:3826.75-3826.506" + wire $or$ls180.v:3826$320_Y + attribute \src "ls180.v:3827.158-3827.332" + wire $or$ls180.v:3827$328_Y + attribute \src "ls180.v:3827.75-3827.506" + wire $or$ls180.v:3827$333_Y + attribute \src "ls180.v:3828.158-3828.332" + wire $or$ls180.v:3828$341_Y + attribute \src "ls180.v:3828.75-3828.506" + wire $or$ls180.v:3828$346_Y + attribute \src "ls180.v:3891.36-3891.104" + wire $or$ls180.v:3891$380_Y + attribute \src "ls180.v:3912.67-3912.221" + wire $or$ls180.v:3912$387_Y + attribute \src "ls180.v:3920.10-3920.62" + wire $or$ls180.v:3920$390_Y + attribute \src "ls180.v:3950.67-3950.221" + wire $or$ls180.v:3950$396_Y + attribute \src "ls180.v:3958.10-3958.61" + wire $or$ls180.v:3958$399_Y + attribute \src "ls180.v:3968.91-3968.180" + wire $or$ls180.v:3968$403_Y + attribute \src "ls180.v:3968.90-3968.255" + wire $or$ls180.v:3968$406_Y + attribute \src "ls180.v:3968.89-3968.330" + wire $or$ls180.v:3968$409_Y + attribute \src "ls180.v:3973.91-3973.180" + wire $or$ls180.v:3973$419_Y + attribute \src "ls180.v:3973.90-3973.255" + wire $or$ls180.v:3973$422_Y + attribute \src "ls180.v:3973.89-3973.330" + wire $or$ls180.v:3973$425_Y + attribute \src "ls180.v:3978.91-3978.180" + wire $or$ls180.v:3978$435_Y + attribute \src "ls180.v:3978.90-3978.255" + wire $or$ls180.v:3978$438_Y + attribute \src "ls180.v:3978.89-3978.330" + wire $or$ls180.v:3978$441_Y + attribute \src "ls180.v:3983.91-3983.180" + wire $or$ls180.v:3983$451_Y + attribute \src "ls180.v:3983.90-3983.255" + wire $or$ls180.v:3983$454_Y + attribute \src "ls180.v:3983.89-3983.330" + wire $or$ls180.v:3983$457_Y + attribute \src "ls180.v:3988.132-3988.221" + wire $or$ls180.v:3988$468_Y + attribute \src "ls180.v:3988.131-3988.296" + wire $or$ls180.v:3988$471_Y + attribute \src "ls180.v:3988.130-3988.371" + wire $or$ls180.v:3988$474_Y + attribute \src "ls180.v:3988.34-3988.411" + wire $or$ls180.v:3988$479_Y + attribute \src "ls180.v:3988.506-3988.595" + wire $or$ls180.v:3988$484_Y + attribute \src "ls180.v:3988.505-3988.670" + wire $or$ls180.v:3988$487_Y + attribute \src "ls180.v:3988.504-3988.745" + wire $or$ls180.v:3988$490_Y + attribute \src "ls180.v:3988.33-3988.785" + wire $or$ls180.v:3988$495_Y + attribute \src "ls180.v:3988.880-3988.969" + wire $or$ls180.v:3988$500_Y + attribute \src "ls180.v:3988.879-3988.1044" + wire $or$ls180.v:3988$503_Y + attribute \src "ls180.v:3988.878-3988.1119" + wire $or$ls180.v:3988$506_Y + attribute \src "ls180.v:3988.32-3988.1159" + wire $or$ls180.v:3988$511_Y + attribute \src "ls180.v:3988.1254-3988.1343" + wire $or$ls180.v:3988$516_Y + attribute \src "ls180.v:3988.1253-3988.1418" + wire $or$ls180.v:3988$519_Y + attribute \src "ls180.v:3988.1252-3988.1493" + wire $or$ls180.v:3988$522_Y + attribute \src "ls180.v:3988.31-3988.1533" + wire $or$ls180.v:3988$527_Y + attribute \src "ls180.v:4051.10-4051.52" + wire $or$ls180.v:4051$536_Y + attribute \src "ls180.v:4078.35-4078.74" + wire $or$ls180.v:4078$546_Y + attribute \src "ls180.v:4079.34-4079.73" + wire $or$ls180.v:4079$550_Y + attribute \src "ls180.v:4080.48-4080.130" + wire $or$ls180.v:4080$556_Y + attribute \src "ls180.v:4081.24-4081.87" + wire $or$ls180.v:4081$559_Y + attribute \src "ls180.v:4082.26-4082.95" + wire $or$ls180.v:4082$561_Y + attribute \src "ls180.v:4112.42-4112.89" + wire $or$ls180.v:4112$569_Y + attribute \src "ls180.v:4136.25-4136.174" + wire $or$ls180.v:4136$579_Y + attribute \src "ls180.v:4151.80-4151.132" + wire $or$ls180.v:4151$581_Y + attribute \src "ls180.v:4162.72-4162.135" + wire $or$ls180.v:4162$586_Y + attribute \src "ls180.v:4181.80-4181.132" + wire $or$ls180.v:4181$592_Y + attribute \src "ls180.v:4192.72-4192.135" + wire $or$ls180.v:4192$597_Y + attribute \src "ls180.v:4267.36-4267.111" + wire $or$ls180.v:4267$610_Y + attribute \src "ls180.v:4267.35-4267.151" + wire $or$ls180.v:4267$611_Y + attribute \src "ls180.v:4267.34-4267.192" + wire $or$ls180.v:4267$612_Y + attribute \src "ls180.v:4267.33-4267.233" + wire $or$ls180.v:4267$613_Y + attribute \src "ls180.v:4268.39-4268.120" + wire $or$ls180.v:4268$614_Y + attribute \src "ls180.v:4268.38-4268.163" + wire $or$ls180.v:4268$615_Y + attribute \src "ls180.v:4268.37-4268.207" + wire $or$ls180.v:4268$616_Y + attribute \src "ls180.v:4268.36-4268.251" + wire $or$ls180.v:4268$617_Y + attribute \src "ls180.v:4269.38-4269.117" + wire $or$ls180.v:4269$618_Y + attribute \src "ls180.v:4269.37-4269.159" + wire $or$ls180.v:4269$619_Y + attribute \src "ls180.v:4269.36-4269.202" + wire $or$ls180.v:4269$620_Y + attribute \src "ls180.v:4269.35-4269.245" + wire $or$ls180.v:4269$621_Y + attribute \src "ls180.v:4270.40-4270.123" + wire $or$ls180.v:4270$622_Y + attribute \src "ls180.v:4270.39-4270.167" + wire $or$ls180.v:4270$623_Y + attribute \src "ls180.v:4270.38-4270.212" + wire $or$ls180.v:4270$624_Y + attribute \src "ls180.v:4270.37-4270.257" + wire $or$ls180.v:4270$625_Y + attribute \src "ls180.v:4271.39-4271.120" + wire width 4 $or$ls180.v:4271$626_Y + attribute \src "ls180.v:4271.38-4271.163" + wire width 4 $or$ls180.v:4271$627_Y + attribute \src "ls180.v:4271.37-4271.207" + wire width 4 $or$ls180.v:4271$628_Y + attribute \src "ls180.v:4271.36-4271.251" + wire width 4 $or$ls180.v:4271$629_Y + attribute \src "ls180.v:4292.35-4292.80" + wire $or$ls180.v:4292$630_Y + attribute \src "ls180.v:4446.91-4446.144" + wire $or$ls180.v:4446$644_Y + attribute \src "ls180.v:4463.53-4463.143" + wire $or$ls180.v:4463$647_Y + attribute \src "ls180.v:4466.47-4466.127" + wire $or$ls180.v:4466$650_Y + attribute \src "ls180.v:4590.54-4590.146" + wire $or$ls180.v:4590$668_Y + attribute \src "ls180.v:4593.48-4593.130" + wire $or$ls180.v:4593$671_Y + attribute \src "ls180.v:4724.55-4724.149" + wire $or$ls180.v:4724$683_Y + attribute \src "ls180.v:4727.49-4727.133" + wire $or$ls180.v:4727$686_Y + attribute \src "ls180.v:5356.80-5356.151" + wire $or$ls180.v:5356$981_Y + attribute \src "ls180.v:5367.49-5367.131" + wire $or$ls180.v:5367$987_Y + attribute \src "ls180.v:5564.80-5564.151" + wire $or$ls180.v:5564$1012_Y + attribute \src "ls180.v:5738.33-5738.102" + wire $or$ls180.v:5738$1060_Y + attribute \src "ls180.v:5738.32-5738.144" + wire $or$ls180.v:5738$1061_Y + attribute \src "ls180.v:5738.31-5738.165" + wire $or$ls180.v:5738$1062_Y + attribute \src "ls180.v:5738.30-5738.201" + wire $or$ls180.v:5738$1063_Y + attribute \src "ls180.v:5744.28-5744.97" + wire $or$ls180.v:5744$1068_Y + attribute \src "ls180.v:5744.27-5744.139" + wire $or$ls180.v:5744$1069_Y + attribute \src "ls180.v:5744.26-5744.160" + wire $or$ls180.v:5744$1070_Y + attribute \src "ls180.v:5744.25-5744.196" + wire $or$ls180.v:5744$1071_Y + attribute \src "ls180.v:5745.30-5745.169" + wire width 32 $or$ls180.v:5745$1074_Y + attribute \src "ls180.v:5745.29-5745.246" + wire width 32 $or$ls180.v:5745$1076_Y + attribute \src "ls180.v:5745.28-5745.302" + wire width 32 $or$ls180.v:5745$1078_Y + attribute \src "ls180.v:5745.27-5745.373" + wire width 32 $or$ls180.v:5745$1080_Y + attribute \src "ls180.v:6499.55-6499.124" + wire width 8 $or$ls180.v:6499$2226_Y + attribute \src "ls180.v:6499.54-6499.161" + wire width 8 $or$ls180.v:6499$2227_Y + attribute \src "ls180.v:6499.53-6499.198" + wire width 8 $or$ls180.v:6499$2228_Y + attribute \src "ls180.v:6499.52-6499.235" + wire width 8 $or$ls180.v:6499$2229_Y + attribute \src "ls180.v:6499.51-6499.272" + wire width 8 $or$ls180.v:6499$2230_Y + attribute \src "ls180.v:6499.50-6499.309" + wire width 8 $or$ls180.v:6499$2231_Y + attribute \src "ls180.v:6499.49-6499.346" + wire width 8 $or$ls180.v:6499$2232_Y + attribute \src "ls180.v:6499.48-6499.383" + wire width 8 $or$ls180.v:6499$2233_Y + attribute \src "ls180.v:6499.47-6499.420" + wire width 8 $or$ls180.v:6499$2234_Y + attribute \src "ls180.v:6499.46-6499.458" + wire width 8 $or$ls180.v:6499$2235_Y + attribute \src "ls180.v:6499.45-6499.496" + wire width 8 $or$ls180.v:6499$2236_Y + attribute \src "ls180.v:6499.44-6499.534" + wire width 8 $or$ls180.v:6499$2237_Y + attribute \src "ls180.v:6499.43-6499.572" + wire width 8 $or$ls180.v:6499$2238_Y + attribute \src "ls180.v:6499.42-6499.610" + wire width 8 $or$ls180.v:6499$2239_Y + attribute \src "ls180.v:6826.90-6826.179" + wire $or$ls180.v:6826$2264_Y + attribute \src "ls180.v:6826.89-6826.254" + wire $or$ls180.v:6826$2267_Y + attribute \src "ls180.v:6826.88-6826.329" + wire $or$ls180.v:6826$2270_Y + attribute \src "ls180.v:6850.90-6850.179" + wire $or$ls180.v:6850$2280_Y + attribute \src "ls180.v:6850.89-6850.254" + wire $or$ls180.v:6850$2283_Y + attribute \src "ls180.v:6850.88-6850.329" + wire $or$ls180.v:6850$2286_Y + attribute \src "ls180.v:6874.90-6874.179" + wire $or$ls180.v:6874$2296_Y + attribute \src "ls180.v:6874.89-6874.254" + wire $or$ls180.v:6874$2299_Y + attribute \src "ls180.v:6874.88-6874.329" + wire $or$ls180.v:6874$2302_Y + attribute \src "ls180.v:6898.90-6898.179" + wire $or$ls180.v:6898$2312_Y + attribute \src "ls180.v:6898.89-6898.254" + wire $or$ls180.v:6898$2315_Y + attribute \src "ls180.v:6898.88-6898.329" + wire $or$ls180.v:6898$2318_Y + attribute \src "ls180.v:7412.20-7412.71" + wire $or$ls180.v:7412$2375_Y + attribute \src "ls180.v:7413.20-7413.71" + wire $or$ls180.v:7413$2376_Y + attribute \src "ls180.v:7414.20-7414.71" + wire $or$ls180.v:7414$2377_Y + attribute \src "ls180.v:7415.20-7415.71" + wire $or$ls180.v:7415$2378_Y + attribute \src "ls180.v:7416.20-7416.71" + wire $or$ls180.v:7416$2379_Y + attribute \src "ls180.v:7417.20-7417.71" + wire $or$ls180.v:7417$2380_Y + attribute \src "ls180.v:7418.20-7418.71" + wire $or$ls180.v:7418$2381_Y + attribute \src "ls180.v:7419.20-7419.71" + wire $or$ls180.v:7419$2382_Y + attribute \src "ls180.v:7420.20-7420.71" + wire $or$ls180.v:7420$2383_Y + attribute \src "ls180.v:7421.20-7421.71" + wire $or$ls180.v:7421$2384_Y + attribute \src "ls180.v:7422.21-7422.73" + wire $or$ls180.v:7422$2385_Y + attribute \src "ls180.v:7423.21-7423.73" + wire $or$ls180.v:7423$2386_Y + attribute \src "ls180.v:7424.21-7424.73" + wire $or$ls180.v:7424$2387_Y + attribute \src "ls180.v:7425.21-7425.73" + wire $or$ls180.v:7425$2388_Y + attribute \src "ls180.v:7426.21-7426.73" + wire $or$ls180.v:7426$2389_Y + attribute \src "ls180.v:7427.21-7427.73" + wire $or$ls180.v:7427$2390_Y + attribute \src "ls180.v:7428.21-7428.73" + wire $or$ls180.v:7428$2391_Y + attribute \src "ls180.v:7429.21-7429.73" + wire $or$ls180.v:7429$2392_Y + attribute \src "ls180.v:7430.21-7430.73" + wire $or$ls180.v:7430$2393_Y + attribute \src "ls180.v:7431.21-7431.73" + wire $or$ls180.v:7431$2394_Y + attribute \src "ls180.v:7432.21-7432.73" + wire $or$ls180.v:7432$2395_Y + attribute \src "ls180.v:7433.21-7433.73" + wire $or$ls180.v:7433$2396_Y + attribute \src "ls180.v:7434.21-7434.73" + wire $or$ls180.v:7434$2397_Y + attribute \src "ls180.v:7435.21-7435.73" + wire $or$ls180.v:7435$2398_Y + attribute \src "ls180.v:7436.21-7436.73" + wire $or$ls180.v:7436$2399_Y + attribute \src "ls180.v:7437.21-7437.73" + wire $or$ls180.v:7437$2400_Y + attribute \src "ls180.v:7438.21-7438.73" + wire $or$ls180.v:7438$2401_Y + attribute \src "ls180.v:7439.21-7439.73" + wire $or$ls180.v:7439$2402_Y + attribute \src "ls180.v:7440.21-7440.73" + wire $or$ls180.v:7440$2403_Y + attribute \src "ls180.v:7441.21-7441.73" + wire $or$ls180.v:7441$2404_Y + attribute \src "ls180.v:7442.21-7442.73" + wire $or$ls180.v:7442$2405_Y + attribute \src "ls180.v:7443.21-7443.73" + wire $or$ls180.v:7443$2406_Y + attribute \src "ls180.v:7444.21-7444.73" + wire $or$ls180.v:7444$2407_Y + attribute \src "ls180.v:7445.21-7445.73" + wire $or$ls180.v:7445$2408_Y + attribute \src "ls180.v:7446.21-7446.73" + wire $or$ls180.v:7446$2409_Y + attribute \src "ls180.v:7447.21-7447.73" + wire $or$ls180.v:7447$2410_Y + attribute \src "ls180.v:7448.7-7448.93" + wire $or$ls180.v:7448$2411_Y + attribute \src "ls180.v:7459.7-7459.93" + wire $or$ls180.v:7459$2412_Y + attribute \src "ls180.v:7470.7-7470.93" + wire $or$ls180.v:7470$2413_Y + attribute \src "ls180.v:7599.7-7599.107" + wire $or$ls180.v:7599$2449_Y + attribute \src "ls180.v:7645.7-7645.107" + wire $or$ls180.v:7645$2465_Y + attribute \src "ls180.v:7691.7-7691.107" + wire $or$ls180.v:7691$2481_Y + attribute \src "ls180.v:7737.7-7737.107" + wire $or$ls180.v:7737$2497_Y + attribute \src "ls180.v:7925.40-7925.125" + wire $or$ls180.v:7925$2518_Y + attribute \src "ls180.v:7925.39-7925.207" + wire $or$ls180.v:7925$2521_Y + attribute \src "ls180.v:7925.38-7925.289" + wire $or$ls180.v:7925$2524_Y + attribute \src "ls180.v:7925.37-7925.371" + wire $or$ls180.v:7925$2527_Y + attribute \src "ls180.v:7926.41-7926.126" + wire $or$ls180.v:7926$2530_Y + attribute \src "ls180.v:7926.40-7926.208" + wire $or$ls180.v:7926$2533_Y + attribute \src "ls180.v:7926.39-7926.290" + wire $or$ls180.v:7926$2536_Y + attribute \src "ls180.v:7926.38-7926.372" + wire $or$ls180.v:7926$2539_Y + attribute \src "ls180.v:7930.7-7930.49" + wire $or$ls180.v:7930$2540_Y + attribute \src "ls180.v:8093.22-8093.74" + wire $or$ls180.v:8093$2588_Y + attribute \src "ls180.v:8161.32-8161.85" + wire $or$ls180.v:8161$2600_Y + attribute \src "ls180.v:8167.8-8167.97" + wire $or$ls180.v:8167$2602_Y + attribute \src "ls180.v:8184.52-8184.139" + wire $or$ls180.v:8184$2607_Y + attribute \src "ls180.v:8185.51-8185.136" + wire $or$ls180.v:8185$2608_Y + attribute \src "ls180.v:8219.7-8219.87" + wire $or$ls180.v:8219$2611_Y + attribute \src "ls180.v:8242.33-8242.88" + wire $or$ls180.v:8242$2612_Y + attribute \src "ls180.v:8248.8-8248.99" + wire $or$ls180.v:8248$2614_Y + attribute \src "ls180.v:8265.53-8265.142" + wire $or$ls180.v:8265$2619_Y + attribute \src "ls180.v:8266.52-8266.139" + wire $or$ls180.v:8266$2620_Y + attribute \src "ls180.v:8300.7-8300.89" + wire $or$ls180.v:8300$2623_Y + attribute \src "ls180.v:8321.34-8321.91" + wire $or$ls180.v:8321$2624_Y + attribute \src "ls180.v:8327.8-8327.101" + wire $or$ls180.v:8327$2626_Y + attribute \src "ls180.v:8344.54-8344.145" + wire $or$ls180.v:8344$2631_Y + attribute \src "ls180.v:8345.53-8345.142" + wire $or$ls180.v:8345$2632_Y + attribute \src "ls180.v:8361.7-8361.91" + wire $or$ls180.v:8361$2635_Y + attribute \src "ls180.v:8550.8-8550.89" + wire $or$ls180.v:8550$2659_Y + attribute \src "ls180.v:8567.48-8567.127" + wire $or$ls180.v:8567$2664_Y + attribute \src "ls180.v:8568.47-8568.124" + wire $or$ls180.v:8568$2665_Y + attribute \src "ls180.v:8641.21-8641.65" + wire $or$ls180.v:8641$2683_Y + attribute \src "ls180.v:3162.46-3162.94" + wire width 13 $sshl$ls180.v:3162$83_Y + attribute \src "ls180.v:3319.46-3319.94" + wire width 13 $sshl$ls180.v:3319$113_Y + attribute \src "ls180.v:3476.46-3476.94" + wire width 13 $sshl$ls180.v:3476$143_Y + attribute \src "ls180.v:3633.46-3633.94" + wire width 13 $sshl$ls180.v:3633$173_Y + attribute \src "ls180.v:3193.63-3193.122" + wire width 3 $sub$ls180.v:3193$96_Y + attribute \src "ls180.v:3350.63-3350.122" + wire width 3 $sub$ls180.v:3350$126_Y + attribute \src "ls180.v:3507.63-3507.122" + wire width 3 $sub$ls180.v:3507$156_Y + attribute \src "ls180.v:3664.63-3664.122" + wire width 3 $sub$ls180.v:3664$186_Y + attribute \src "ls180.v:4070.38-4070.75" + wire width 31 $sub$ls180.v:4070$540_Y + attribute \src "ls180.v:4156.36-4156.68" + wire width 4 $sub$ls180.v:4156$585_Y + attribute \src "ls180.v:4186.36-4186.68" + wire width 4 $sub$ls180.v:4186$596_Y + attribute \src "ls180.v:4211.69-4211.110" + wire width 16 $sub$ls180.v:4211$602_Y + attribute \src "ls180.v:4212.69-4212.104" + wire width 16 $sub$ls180.v:4212$604_Y + attribute \src "ls180.v:4239.36-4239.66" + wire width 8 $sub$ls180.v:4239$608_Y + attribute \src "ls180.v:4493.60-4493.90" + wire width 32 $sub$ls180.v:4493$652_Y + attribute \src "ls180.v:4504.62-4504.104" + wire width 8 $sub$ls180.v:4504$654_Y + attribute \src "ls180.v:4521.60-4521.90" + wire width 32 $sub$ls180.v:4521$658_Y + attribute \src "ls180.v:4750.62-4750.93" + wire width 32 $sub$ls180.v:4750$688_Y + attribute \src "ls180.v:4755.62-4755.93" + wire width 32 $sub$ls180.v:4755$689_Y + attribute \src "ls180.v:4766.64-4766.122" + wire width 10 $sub$ls180.v:4766$692_Y + attribute \src "ls180.v:4787.62-4787.93" + wire width 32 $sub$ls180.v:4787$695_Y + attribute \src "ls180.v:5249.37-5249.75" + wire width 32 $sub$ls180.v:5249$968_Y + attribute \src "ls180.v:5264.62-5264.100" + wire width 32 $sub$ls180.v:5264$971_Y + attribute \src "ls180.v:5275.39-5275.77" + wire width 32 $sub$ls180.v:5275$976_Y + attribute \src "ls180.v:5350.40-5350.76" + wire width 5 $sub$ls180.v:5350$980_Y + attribute \src "ls180.v:5399.56-5399.104" + wire width 32 $sub$ls180.v:5399$994_Y + attribute \src "ls180.v:5489.71-5489.105" + wire width 32 $sub$ls180.v:5489$1000_Y + attribute \src "ls180.v:5558.40-5558.76" + wire width 5 $sub$ls180.v:5558$1011_Y + attribute \src "ls180.v:5577.61-5577.98" + wire width 16 $sub$ls180.v:5577$1017_Y + attribute \src "ls180.v:5578.61-5578.92" + wire width 16 $sub$ls180.v:5578$1019_Y + attribute \src "ls180.v:5606.32-5606.58" + wire width 8 $sub$ls180.v:5606$1023_Y + attribute \src "ls180.v:7494.31-7494.60" + wire width 32 $sub$ls180.v:7494$2420_Y + attribute \src "ls180.v:7515.31-7515.61" + wire width 10 $sub$ls180.v:7515$2425_Y + attribute \src "ls180.v:7521.34-7521.67" + wire $sub$ls180.v:7521$2426_Y + attribute \src "ls180.v:7532.36-7532.69" + wire $sub$ls180.v:7532$2429_Y + attribute \src "ls180.v:7596.59-7596.116" + wire width 4 $sub$ls180.v:7596$2447_Y + attribute \src "ls180.v:7615.46-7615.90" + wire width 3 $sub$ls180.v:7615$2451_Y + attribute \src "ls180.v:7642.59-7642.116" + wire width 4 $sub$ls180.v:7642$2463_Y + attribute \src "ls180.v:7661.46-7661.90" + wire width 3 $sub$ls180.v:7661$2467_Y + attribute \src "ls180.v:7688.59-7688.116" + wire width 4 $sub$ls180.v:7688$2479_Y + attribute \src "ls180.v:7707.46-7707.90" + wire width 3 $sub$ls180.v:7707$2483_Y + attribute \src "ls180.v:7734.59-7734.116" + wire width 4 $sub$ls180.v:7734$2495_Y + attribute \src "ls180.v:7753.46-7753.90" + wire width 3 $sub$ls180.v:7753$2499_Y + attribute \src "ls180.v:7764.25-7764.48" + wire width 5 $sub$ls180.v:7764$2503_Y + attribute \src "ls180.v:7771.25-7771.48" + wire width 4 $sub$ls180.v:7771$2506_Y + attribute \src "ls180.v:7903.33-7903.64" + wire $sub$ls180.v:7903$2511_Y + attribute \src "ls180.v:7918.33-7918.64" + wire width 3 $sub$ls180.v:7918$2514_Y + attribute \src "ls180.v:8045.33-8045.64" + wire width 5 $sub$ls180.v:8045$2573_Y + attribute \src "ls180.v:8067.33-8067.64" + wire width 5 $sub$ls180.v:8067$2584_Y + attribute \src "ls180.v:8102.33-8102.64" + wire width 3 $sub$ls180.v:8102$2589_Y + attribute \src "ls180.v:8126.30-8126.53" + wire width 32 $sub$ls180.v:8126$2592_Y + attribute \src "ls180.v:8140.30-8140.53" + wire width 32 $sub$ls180.v:8140$2596_Y + attribute \src "ls180.v:8543.36-8543.70" + wire width 6 $sub$ls180.v:8543$2657_Y + attribute \src "ls180.v:8629.36-8629.70" + wire width 6 $sub$ls180.v:8629$2679_Y + attribute \src "ls180.v:8650.29-8650.56" + wire width 3 $sub$ls180.v:8650$2684_Y + attribute \src "ls180.v:8777.22-8777.42" + wire width 20 $sub$ls180.v:8777$2691_Y + attribute \src "ls180.v:4847.353-4847.425" + wire $xor$ls180.v:4847$702_Y + attribute \src "ls180.v:4847.200-4847.272" + wire $xor$ls180.v:4847$703_Y + attribute \src "ls180.v:4847.160-4847.273" + wire $xor$ls180.v:4847$704_Y + attribute \src "ls180.v:4848.353-4848.425" + wire $xor$ls180.v:4848$705_Y + attribute \src "ls180.v:4848.200-4848.272" + wire $xor$ls180.v:4848$706_Y + attribute \src "ls180.v:4848.160-4848.273" + wire $xor$ls180.v:4848$707_Y + attribute \src "ls180.v:4849.353-4849.425" + wire $xor$ls180.v:4849$708_Y + attribute \src "ls180.v:4849.200-4849.272" + wire $xor$ls180.v:4849$709_Y + attribute \src "ls180.v:4849.160-4849.273" + wire $xor$ls180.v:4849$710_Y + attribute \src "ls180.v:4850.353-4850.425" + wire $xor$ls180.v:4850$711_Y + attribute \src "ls180.v:4850.200-4850.272" + wire $xor$ls180.v:4850$712_Y + attribute \src "ls180.v:4850.160-4850.273" + wire $xor$ls180.v:4850$713_Y + attribute \src "ls180.v:4851.353-4851.425" + wire $xor$ls180.v:4851$714_Y + attribute \src "ls180.v:4851.200-4851.272" + wire $xor$ls180.v:4851$715_Y + attribute \src "ls180.v:4851.160-4851.273" + wire $xor$ls180.v:4851$716_Y + attribute \src "ls180.v:4852.353-4852.425" + wire $xor$ls180.v:4852$717_Y + attribute \src "ls180.v:4852.200-4852.272" + wire $xor$ls180.v:4852$718_Y + attribute \src "ls180.v:4852.160-4852.273" + wire $xor$ls180.v:4852$719_Y + attribute \src "ls180.v:4853.353-4853.425" + wire $xor$ls180.v:4853$720_Y + attribute \src "ls180.v:4853.200-4853.272" + wire $xor$ls180.v:4853$721_Y + attribute \src "ls180.v:4853.160-4853.273" + wire $xor$ls180.v:4853$722_Y + attribute \src "ls180.v:4854.353-4854.425" + wire $xor$ls180.v:4854$723_Y + attribute \src "ls180.v:4854.200-4854.272" + wire $xor$ls180.v:4854$724_Y + attribute \src "ls180.v:4854.160-4854.273" + wire $xor$ls180.v:4854$725_Y + attribute \src "ls180.v:4855.353-4855.425" + wire $xor$ls180.v:4855$726_Y + attribute \src "ls180.v:4855.200-4855.272" + wire $xor$ls180.v:4855$727_Y + attribute \src "ls180.v:4855.160-4855.273" + wire $xor$ls180.v:4855$728_Y + attribute \src "ls180.v:4856.354-4856.426" + wire $xor$ls180.v:4856$729_Y + attribute \src "ls180.v:4856.201-4856.273" + wire $xor$ls180.v:4856$730_Y + attribute \src "ls180.v:4856.161-4856.274" + wire $xor$ls180.v:4856$731_Y + attribute \src "ls180.v:4857.361-4857.434" + wire $xor$ls180.v:4857$732_Y + attribute \src "ls180.v:4857.205-4857.278" + wire $xor$ls180.v:4857$733_Y + attribute \src "ls180.v:4857.164-4857.279" + wire $xor$ls180.v:4857$734_Y + attribute \src "ls180.v:4858.361-4858.434" + wire $xor$ls180.v:4858$735_Y + attribute \src "ls180.v:4858.205-4858.278" + wire $xor$ls180.v:4858$736_Y + attribute \src "ls180.v:4858.164-4858.279" + wire $xor$ls180.v:4858$737_Y + attribute \src "ls180.v:4859.361-4859.434" + wire $xor$ls180.v:4859$738_Y + attribute \src "ls180.v:4859.205-4859.278" + wire $xor$ls180.v:4859$739_Y + attribute \src "ls180.v:4859.164-4859.279" + wire $xor$ls180.v:4859$740_Y + attribute \src "ls180.v:4860.361-4860.434" + wire $xor$ls180.v:4860$741_Y + attribute \src "ls180.v:4860.205-4860.278" + wire $xor$ls180.v:4860$742_Y + attribute \src "ls180.v:4860.164-4860.279" + wire $xor$ls180.v:4860$743_Y + attribute \src "ls180.v:4861.361-4861.434" + wire $xor$ls180.v:4861$744_Y + attribute \src "ls180.v:4861.205-4861.278" + wire $xor$ls180.v:4861$745_Y + attribute \src "ls180.v:4861.164-4861.279" + wire $xor$ls180.v:4861$746_Y + attribute \src "ls180.v:4862.361-4862.434" + wire $xor$ls180.v:4862$747_Y + attribute \src "ls180.v:4862.205-4862.278" + wire $xor$ls180.v:4862$748_Y + attribute \src "ls180.v:4862.164-4862.279" + wire $xor$ls180.v:4862$749_Y + attribute \src "ls180.v:4863.361-4863.434" + wire $xor$ls180.v:4863$750_Y + attribute \src "ls180.v:4863.205-4863.278" + wire $xor$ls180.v:4863$751_Y + attribute \src "ls180.v:4863.164-4863.279" + wire $xor$ls180.v:4863$752_Y + attribute \src "ls180.v:4864.361-4864.434" + wire $xor$ls180.v:4864$753_Y + attribute \src "ls180.v:4864.205-4864.278" + wire $xor$ls180.v:4864$754_Y + attribute \src "ls180.v:4864.164-4864.279" + wire $xor$ls180.v:4864$755_Y + attribute \src "ls180.v:4865.361-4865.434" + wire $xor$ls180.v:4865$756_Y + attribute \src "ls180.v:4865.205-4865.278" + wire $xor$ls180.v:4865$757_Y + attribute \src "ls180.v:4865.164-4865.279" + wire $xor$ls180.v:4865$758_Y + attribute \src "ls180.v:4866.361-4866.434" + wire $xor$ls180.v:4866$759_Y + attribute \src "ls180.v:4866.205-4866.278" + wire $xor$ls180.v:4866$760_Y + attribute \src "ls180.v:4866.164-4866.279" + wire $xor$ls180.v:4866$761_Y + attribute \src "ls180.v:4867.361-4867.434" + wire $xor$ls180.v:4867$762_Y + attribute \src "ls180.v:4867.205-4867.278" + wire $xor$ls180.v:4867$763_Y + attribute \src "ls180.v:4867.164-4867.279" + wire $xor$ls180.v:4867$764_Y + attribute \src "ls180.v:4868.361-4868.434" + wire $xor$ls180.v:4868$765_Y + attribute \src "ls180.v:4868.205-4868.278" + wire $xor$ls180.v:4868$766_Y + attribute \src "ls180.v:4868.164-4868.279" + wire $xor$ls180.v:4868$767_Y + attribute \src "ls180.v:4869.361-4869.434" + wire $xor$ls180.v:4869$768_Y + attribute \src "ls180.v:4869.205-4869.278" + wire $xor$ls180.v:4869$769_Y + attribute \src "ls180.v:4869.164-4869.279" + wire $xor$ls180.v:4869$770_Y + attribute \src "ls180.v:4870.361-4870.434" + wire $xor$ls180.v:4870$771_Y + attribute \src "ls180.v:4870.205-4870.278" + wire $xor$ls180.v:4870$772_Y + attribute \src "ls180.v:4870.164-4870.279" + wire $xor$ls180.v:4870$773_Y + attribute \src "ls180.v:4871.361-4871.434" + wire $xor$ls180.v:4871$774_Y + attribute \src "ls180.v:4871.205-4871.278" + wire $xor$ls180.v:4871$775_Y + attribute \src "ls180.v:4871.164-4871.279" + wire $xor$ls180.v:4871$776_Y + attribute \src "ls180.v:4872.361-4872.434" + wire $xor$ls180.v:4872$777_Y + attribute \src "ls180.v:4872.205-4872.278" + wire $xor$ls180.v:4872$778_Y + attribute \src "ls180.v:4872.164-4872.279" + wire $xor$ls180.v:4872$779_Y + attribute \src "ls180.v:4873.361-4873.434" + wire $xor$ls180.v:4873$780_Y + attribute \src "ls180.v:4873.205-4873.278" + wire $xor$ls180.v:4873$781_Y + attribute \src "ls180.v:4873.164-4873.279" + wire $xor$ls180.v:4873$782_Y + attribute \src "ls180.v:4874.361-4874.434" + wire $xor$ls180.v:4874$783_Y + attribute \src "ls180.v:4874.205-4874.278" + wire $xor$ls180.v:4874$784_Y + attribute \src "ls180.v:4874.164-4874.279" + wire $xor$ls180.v:4874$785_Y + attribute \src "ls180.v:4875.361-4875.434" + wire $xor$ls180.v:4875$786_Y + attribute \src "ls180.v:4875.205-4875.278" + wire $xor$ls180.v:4875$787_Y + attribute \src "ls180.v:4875.164-4875.279" + wire $xor$ls180.v:4875$788_Y + attribute \src "ls180.v:4876.361-4876.434" + wire $xor$ls180.v:4876$789_Y + attribute \src "ls180.v:4876.205-4876.278" + wire $xor$ls180.v:4876$790_Y + attribute \src "ls180.v:4876.164-4876.279" + wire $xor$ls180.v:4876$791_Y + attribute \src "ls180.v:4877.360-4877.432" + wire $xor$ls180.v:4877$792_Y + attribute \src "ls180.v:4877.205-4877.277" + wire $xor$ls180.v:4877$793_Y + attribute \src "ls180.v:4877.164-4877.278" + wire $xor$ls180.v:4877$794_Y + attribute \src "ls180.v:4878.360-4878.432" + wire $xor$ls180.v:4878$795_Y + attribute \src "ls180.v:4878.205-4878.277" + wire $xor$ls180.v:4878$796_Y + attribute \src "ls180.v:4878.164-4878.278" + wire $xor$ls180.v:4878$797_Y + attribute \src "ls180.v:4879.360-4879.432" + wire $xor$ls180.v:4879$798_Y + attribute \src "ls180.v:4879.205-4879.277" + wire $xor$ls180.v:4879$799_Y + attribute \src "ls180.v:4879.164-4879.278" + wire $xor$ls180.v:4879$800_Y + attribute \src "ls180.v:4880.360-4880.432" + wire $xor$ls180.v:4880$801_Y + attribute \src "ls180.v:4880.205-4880.277" + wire $xor$ls180.v:4880$802_Y + attribute \src "ls180.v:4880.164-4880.278" + wire $xor$ls180.v:4880$803_Y + attribute \src "ls180.v:4881.360-4881.432" + wire $xor$ls180.v:4881$804_Y + attribute \src "ls180.v:4881.205-4881.277" + wire $xor$ls180.v:4881$805_Y + attribute \src "ls180.v:4881.164-4881.278" + wire $xor$ls180.v:4881$806_Y + attribute \src "ls180.v:4882.360-4882.432" + wire $xor$ls180.v:4882$807_Y + attribute \src "ls180.v:4882.205-4882.277" + wire $xor$ls180.v:4882$808_Y + attribute \src "ls180.v:4882.164-4882.278" + wire $xor$ls180.v:4882$809_Y + attribute \src "ls180.v:4883.360-4883.432" + wire $xor$ls180.v:4883$810_Y + attribute \src "ls180.v:4883.205-4883.277" + wire $xor$ls180.v:4883$811_Y + attribute \src "ls180.v:4883.164-4883.278" + wire $xor$ls180.v:4883$812_Y + attribute \src "ls180.v:4884.360-4884.432" + wire $xor$ls180.v:4884$813_Y + attribute \src "ls180.v:4884.205-4884.277" + wire $xor$ls180.v:4884$814_Y + attribute \src "ls180.v:4884.164-4884.278" + wire $xor$ls180.v:4884$815_Y + attribute \src "ls180.v:4885.360-4885.432" + wire $xor$ls180.v:4885$816_Y + attribute \src "ls180.v:4885.205-4885.277" + wire $xor$ls180.v:4885$817_Y + attribute \src "ls180.v:4885.164-4885.278" + wire $xor$ls180.v:4885$818_Y + attribute \src "ls180.v:4886.360-4886.432" + wire $xor$ls180.v:4886$819_Y + attribute \src "ls180.v:4886.205-4886.277" + wire $xor$ls180.v:4886$820_Y + attribute \src "ls180.v:4886.164-4886.278" + wire $xor$ls180.v:4886$821_Y + attribute \src "ls180.v:4907.899-4907.983" + wire $xor$ls180.v:4907$835_Y + attribute \src "ls180.v:4907.634-4907.718" + wire $xor$ls180.v:4907$836_Y + attribute \src "ls180.v:4907.588-4907.719" + wire $xor$ls180.v:4907$837_Y + attribute \src "ls180.v:4907.234-4907.318" + wire $xor$ls180.v:4907$838_Y + attribute \src "ls180.v:4907.187-4907.319" + wire $xor$ls180.v:4907$839_Y + attribute \src "ls180.v:4908.899-4908.983" + wire $xor$ls180.v:4908$840_Y + attribute \src "ls180.v:4908.634-4908.718" + wire $xor$ls180.v:4908$841_Y + attribute \src "ls180.v:4908.588-4908.719" + wire $xor$ls180.v:4908$842_Y + attribute \src "ls180.v:4908.234-4908.318" + wire $xor$ls180.v:4908$843_Y + attribute \src "ls180.v:4908.187-4908.319" + wire $xor$ls180.v:4908$844_Y + attribute \src "ls180.v:4917.899-4917.983" + wire $xor$ls180.v:4917$846_Y + attribute \src "ls180.v:4917.634-4917.718" + wire $xor$ls180.v:4917$847_Y + attribute \src "ls180.v:4917.588-4917.719" + wire $xor$ls180.v:4917$848_Y + attribute \src "ls180.v:4917.234-4917.318" + wire $xor$ls180.v:4917$849_Y + attribute \src "ls180.v:4917.187-4917.319" + wire $xor$ls180.v:4917$850_Y + attribute \src "ls180.v:4918.899-4918.983" + wire $xor$ls180.v:4918$851_Y + attribute \src "ls180.v:4918.634-4918.718" + wire $xor$ls180.v:4918$852_Y + attribute \src "ls180.v:4918.588-4918.719" + wire $xor$ls180.v:4918$853_Y + attribute \src "ls180.v:4918.234-4918.318" + wire $xor$ls180.v:4918$854_Y + attribute \src "ls180.v:4918.187-4918.319" + wire $xor$ls180.v:4918$855_Y + attribute \src "ls180.v:4927.899-4927.983" + wire $xor$ls180.v:4927$857_Y + attribute \src "ls180.v:4927.634-4927.718" + wire $xor$ls180.v:4927$858_Y + attribute \src "ls180.v:4927.588-4927.719" + wire $xor$ls180.v:4927$859_Y + attribute \src "ls180.v:4927.234-4927.318" + wire $xor$ls180.v:4927$860_Y + attribute \src "ls180.v:4927.187-4927.319" + wire $xor$ls180.v:4927$861_Y + attribute \src "ls180.v:4928.899-4928.983" + wire $xor$ls180.v:4928$862_Y + attribute \src "ls180.v:4928.634-4928.718" + wire $xor$ls180.v:4928$863_Y + attribute \src "ls180.v:4928.588-4928.719" + wire $xor$ls180.v:4928$864_Y + attribute \src "ls180.v:4928.234-4928.318" + wire $xor$ls180.v:4928$865_Y + attribute \src "ls180.v:4928.187-4928.319" + wire $xor$ls180.v:4928$866_Y + attribute \src "ls180.v:4937.899-4937.983" + wire $xor$ls180.v:4937$868_Y + attribute \src "ls180.v:4937.634-4937.718" + wire $xor$ls180.v:4937$869_Y + attribute \src "ls180.v:4937.588-4937.719" + wire $xor$ls180.v:4937$870_Y + attribute \src "ls180.v:4937.234-4937.318" + wire $xor$ls180.v:4937$871_Y + attribute \src "ls180.v:4937.187-4937.319" + wire $xor$ls180.v:4937$872_Y + attribute \src "ls180.v:4938.899-4938.983" + wire $xor$ls180.v:4938$873_Y + attribute \src "ls180.v:4938.634-4938.718" + wire $xor$ls180.v:4938$874_Y + attribute \src "ls180.v:4938.588-4938.719" + wire $xor$ls180.v:4938$875_Y + attribute \src "ls180.v:4938.234-4938.318" + wire $xor$ls180.v:4938$876_Y + attribute \src "ls180.v:4938.187-4938.319" + wire $xor$ls180.v:4938$877_Y + attribute \src "ls180.v:5089.879-5089.961" + wire $xor$ls180.v:5089$910_Y + attribute \src "ls180.v:5089.620-5089.702" + wire $xor$ls180.v:5089$911_Y + attribute \src "ls180.v:5089.575-5089.703" + wire $xor$ls180.v:5089$912_Y + attribute \src "ls180.v:5089.229-5089.311" + wire $xor$ls180.v:5089$913_Y + attribute \src "ls180.v:5089.183-5089.312" + wire $xor$ls180.v:5089$914_Y + attribute \src "ls180.v:5090.879-5090.961" + wire $xor$ls180.v:5090$915_Y + attribute \src "ls180.v:5090.620-5090.702" + wire $xor$ls180.v:5090$916_Y + attribute \src "ls180.v:5090.575-5090.703" + wire $xor$ls180.v:5090$917_Y + attribute \src "ls180.v:5090.229-5090.311" + wire $xor$ls180.v:5090$918_Y + attribute \src "ls180.v:5090.183-5090.312" + wire $xor$ls180.v:5090$919_Y + attribute \src "ls180.v:5099.879-5099.961" + wire $xor$ls180.v:5099$921_Y + attribute \src "ls180.v:5099.620-5099.702" + wire $xor$ls180.v:5099$922_Y + attribute \src "ls180.v:5099.575-5099.703" + wire $xor$ls180.v:5099$923_Y + attribute \src "ls180.v:5099.229-5099.311" + wire $xor$ls180.v:5099$924_Y + attribute \src "ls180.v:5099.183-5099.312" + wire $xor$ls180.v:5099$925_Y + attribute \src "ls180.v:5100.879-5100.961" + wire $xor$ls180.v:5100$926_Y + attribute \src "ls180.v:5100.620-5100.702" + wire $xor$ls180.v:5100$927_Y + attribute \src "ls180.v:5100.575-5100.703" + wire $xor$ls180.v:5100$928_Y + attribute \src "ls180.v:5100.229-5100.311" + wire $xor$ls180.v:5100$929_Y + attribute \src "ls180.v:5100.183-5100.312" + wire $xor$ls180.v:5100$930_Y + attribute \src "ls180.v:5109.879-5109.961" + wire $xor$ls180.v:5109$932_Y + attribute \src "ls180.v:5109.620-5109.702" + wire $xor$ls180.v:5109$933_Y + attribute \src "ls180.v:5109.575-5109.703" + wire $xor$ls180.v:5109$934_Y + attribute \src "ls180.v:5109.229-5109.311" + wire $xor$ls180.v:5109$935_Y + attribute \src "ls180.v:5109.183-5109.312" + wire $xor$ls180.v:5109$936_Y + attribute \src "ls180.v:5110.879-5110.961" + wire $xor$ls180.v:5110$937_Y + attribute \src "ls180.v:5110.620-5110.702" + wire $xor$ls180.v:5110$938_Y + attribute \src "ls180.v:5110.575-5110.703" + wire $xor$ls180.v:5110$939_Y + attribute \src "ls180.v:5110.229-5110.311" + wire $xor$ls180.v:5110$940_Y + attribute \src "ls180.v:5110.183-5110.312" + wire $xor$ls180.v:5110$941_Y + attribute \src "ls180.v:5119.879-5119.961" + wire $xor$ls180.v:5119$943_Y + attribute \src "ls180.v:5119.620-5119.702" + wire $xor$ls180.v:5119$944_Y + attribute \src "ls180.v:5119.575-5119.703" + wire $xor$ls180.v:5119$945_Y + attribute \src "ls180.v:5119.229-5119.311" + wire $xor$ls180.v:5119$946_Y + attribute \src "ls180.v:5119.183-5119.312" + wire $xor$ls180.v:5119$947_Y + attribute \src "ls180.v:5120.879-5120.961" + wire $xor$ls180.v:5120$948_Y + attribute \src "ls180.v:5120.620-5120.702" + wire $xor$ls180.v:5120$949_Y + attribute \src "ls180.v:5120.575-5120.703" + wire $xor$ls180.v:5120$950_Y + attribute \src "ls180.v:5120.229-5120.311" + wire $xor$ls180.v:5120$951_Y + attribute \src "ls180.v:5120.183-5120.312" + wire $xor$ls180.v:5120$952_Y + attribute \src "ls180.v:1725.11-1725.42" + wire width 3 \builder_bankmachine0_next_state + attribute \src "ls180.v:1724.11-1724.37" + wire width 3 \builder_bankmachine0_state + attribute \src "ls180.v:1727.11-1727.42" + wire width 3 \builder_bankmachine1_next_state + attribute \src "ls180.v:1726.11-1726.37" + wire width 3 \builder_bankmachine1_state + attribute \src "ls180.v:1729.11-1729.42" + wire width 3 \builder_bankmachine2_next_state + attribute \src "ls180.v:1728.11-1728.37" + wire width 3 \builder_bankmachine2_state + attribute \src "ls180.v:1731.11-1731.42" + wire width 3 \builder_bankmachine3_next_state + attribute \src "ls180.v:1730.11-1730.37" + wire width 3 \builder_bankmachine3_state + attribute \src "ls180.v:2576.5-2576.34" + wire \builder_comb_rhs_array_muxed0 + attribute \src "ls180.v:2577.12-2577.41" + wire width 13 \builder_comb_rhs_array_muxed1 + attribute \src "ls180.v:2589.5-2589.35" + wire \builder_comb_rhs_array_muxed10 + attribute \src "ls180.v:2590.5-2590.35" + wire \builder_comb_rhs_array_muxed11 + attribute \src "ls180.v:2594.12-2594.42" + wire width 22 \builder_comb_rhs_array_muxed12 + attribute \src "ls180.v:2595.5-2595.35" + wire \builder_comb_rhs_array_muxed13 + attribute \src "ls180.v:2596.5-2596.35" + wire \builder_comb_rhs_array_muxed14 + attribute \src "ls180.v:2597.12-2597.42" + wire width 22 \builder_comb_rhs_array_muxed15 + attribute \src "ls180.v:2598.5-2598.35" + wire \builder_comb_rhs_array_muxed16 + attribute \src "ls180.v:2599.5-2599.35" + wire \builder_comb_rhs_array_muxed17 + attribute \src "ls180.v:2600.12-2600.42" + wire width 22 \builder_comb_rhs_array_muxed18 + attribute \src "ls180.v:2601.5-2601.35" + wire \builder_comb_rhs_array_muxed19 + attribute \src "ls180.v:2578.11-2578.40" + wire width 2 \builder_comb_rhs_array_muxed2 + attribute \src "ls180.v:2602.5-2602.35" + wire \builder_comb_rhs_array_muxed20 + attribute \src "ls180.v:2603.12-2603.42" + wire width 22 \builder_comb_rhs_array_muxed21 + attribute \src "ls180.v:2604.5-2604.35" + wire \builder_comb_rhs_array_muxed22 + attribute \src "ls180.v:2605.5-2605.35" + wire \builder_comb_rhs_array_muxed23 + attribute \src "ls180.v:2606.12-2606.42" + wire width 32 \builder_comb_rhs_array_muxed24 + attribute \src "ls180.v:2607.12-2607.42" + wire width 32 \builder_comb_rhs_array_muxed25 + attribute \src "ls180.v:2608.11-2608.41" + wire width 4 \builder_comb_rhs_array_muxed26 + attribute \src "ls180.v:2609.5-2609.35" + wire \builder_comb_rhs_array_muxed27 + attribute \src "ls180.v:2610.5-2610.35" + wire \builder_comb_rhs_array_muxed28 + attribute \src "ls180.v:2611.5-2611.35" + wire \builder_comb_rhs_array_muxed29 + attribute \src "ls180.v:2579.5-2579.34" + wire \builder_comb_rhs_array_muxed3 + attribute \src "ls180.v:2612.11-2612.41" + wire width 3 \builder_comb_rhs_array_muxed30 + attribute \src "ls180.v:2613.11-2613.41" + wire width 2 \builder_comb_rhs_array_muxed31 + attribute \src "ls180.v:2580.5-2580.34" + wire \builder_comb_rhs_array_muxed4 + attribute \src "ls180.v:2581.5-2581.34" + wire \builder_comb_rhs_array_muxed5 + attribute \src "ls180.v:2585.5-2585.34" + wire \builder_comb_rhs_array_muxed6 + attribute \src "ls180.v:2586.12-2586.41" + wire width 13 \builder_comb_rhs_array_muxed7 + attribute \src "ls180.v:2587.11-2587.40" + wire width 2 \builder_comb_rhs_array_muxed8 + attribute \src "ls180.v:2588.5-2588.34" + wire \builder_comb_rhs_array_muxed9 + attribute \src "ls180.v:2582.5-2582.32" + wire \builder_comb_t_array_muxed0 + attribute \src "ls180.v:2583.5-2583.32" + wire \builder_comb_t_array_muxed1 + attribute \src "ls180.v:2584.5-2584.32" + wire \builder_comb_t_array_muxed2 + attribute \src "ls180.v:2591.5-2591.32" + wire \builder_comb_t_array_muxed3 + attribute \src "ls180.v:2592.5-2592.32" + wire \builder_comb_t_array_muxed4 + attribute \src "ls180.v:2593.5-2593.32" + wire \builder_comb_t_array_muxed5 + attribute \src "ls180.v:1711.5-1711.34" + wire \builder_converter0_next_state + attribute \src "ls180.v:1710.5-1710.29" + wire \builder_converter0_state + attribute \src "ls180.v:1715.5-1715.34" + wire \builder_converter1_next_state + attribute \src "ls180.v:1714.5-1714.29" + wire \builder_converter1_state + attribute \src "ls180.v:1719.5-1719.34" + wire \builder_converter2_next_state + attribute \src "ls180.v:1718.5-1718.29" + wire \builder_converter2_state + attribute \src "ls180.v:1756.5-1756.33" + wire \builder_converter_next_state + attribute \src "ls180.v:1755.5-1755.28" + wire \builder_converter_state + attribute \src "ls180.v:1876.12-1876.25" + wire width 20 \builder_count + attribute \src "ls180.v:2564.13-2564.41" + wire width 14 \builder_csr_interconnect_adr + attribute \src "ls180.v:2567.12-2567.42" + wire width 8 \builder_csr_interconnect_dat_r + attribute \src "ls180.v:2566.12-2566.42" + wire width 8 \builder_csr_interconnect_dat_w + attribute \src "ls180.v:2565.6-2565.33" + wire \builder_csr_interconnect_we + attribute \src "ls180.v:1914.12-1914.42" + wire width 8 \builder_csrbank0_bus_errors0_r + attribute \src "ls180.v:1913.6-1913.37" + wire \builder_csrbank0_bus_errors0_re + attribute \src "ls180.v:1916.12-1916.42" + wire width 8 \builder_csrbank0_bus_errors0_w + attribute \src "ls180.v:1915.6-1915.37" + wire \builder_csrbank0_bus_errors0_we + attribute \src "ls180.v:1910.12-1910.42" + wire width 8 \builder_csrbank0_bus_errors1_r + attribute \src "ls180.v:1909.6-1909.37" + wire \builder_csrbank0_bus_errors1_re + attribute \src "ls180.v:1912.12-1912.42" + wire width 8 \builder_csrbank0_bus_errors1_w + attribute \src "ls180.v:1911.6-1911.37" + wire \builder_csrbank0_bus_errors1_we + attribute \src "ls180.v:1906.12-1906.42" + wire width 8 \builder_csrbank0_bus_errors2_r + attribute \src "ls180.v:1905.6-1905.37" + wire \builder_csrbank0_bus_errors2_re + attribute \src "ls180.v:1908.12-1908.42" + wire width 8 \builder_csrbank0_bus_errors2_w + attribute \src "ls180.v:1907.6-1907.37" + wire \builder_csrbank0_bus_errors2_we + attribute \src "ls180.v:1902.12-1902.42" + wire width 8 \builder_csrbank0_bus_errors3_r + attribute \src "ls180.v:1901.6-1901.37" + wire \builder_csrbank0_bus_errors3_re + attribute \src "ls180.v:1904.12-1904.42" + wire width 8 \builder_csrbank0_bus_errors3_w + attribute \src "ls180.v:1903.6-1903.37" + wire \builder_csrbank0_bus_errors3_we + attribute \src "ls180.v:1882.6-1882.31" + wire \builder_csrbank0_reset0_r + attribute \src "ls180.v:1881.6-1881.32" + wire \builder_csrbank0_reset0_re + attribute \src "ls180.v:1884.6-1884.31" + wire \builder_csrbank0_reset0_w + attribute \src "ls180.v:1883.6-1883.32" + wire \builder_csrbank0_reset0_we + attribute \src "ls180.v:1898.12-1898.39" + wire width 8 \builder_csrbank0_scratch0_r + attribute \src "ls180.v:1897.6-1897.34" + wire \builder_csrbank0_scratch0_re + attribute \src "ls180.v:1900.12-1900.39" + wire width 8 \builder_csrbank0_scratch0_w + attribute \src "ls180.v:1899.6-1899.34" + wire \builder_csrbank0_scratch0_we + attribute \src "ls180.v:1894.12-1894.39" + wire width 8 \builder_csrbank0_scratch1_r + attribute \src "ls180.v:1893.6-1893.34" + wire \builder_csrbank0_scratch1_re + attribute \src "ls180.v:1896.12-1896.39" + wire width 8 \builder_csrbank0_scratch1_w + attribute \src "ls180.v:1895.6-1895.34" + wire \builder_csrbank0_scratch1_we + attribute \src "ls180.v:1890.12-1890.39" + wire width 8 \builder_csrbank0_scratch2_r + attribute \src "ls180.v:1889.6-1889.34" + wire \builder_csrbank0_scratch2_re + attribute \src "ls180.v:1892.12-1892.39" + wire width 8 \builder_csrbank0_scratch2_w + attribute \src "ls180.v:1891.6-1891.34" + wire \builder_csrbank0_scratch2_we + attribute \src "ls180.v:1886.12-1886.39" + wire width 8 \builder_csrbank0_scratch3_r + attribute \src "ls180.v:1885.6-1885.34" + wire \builder_csrbank0_scratch3_re + attribute \src "ls180.v:1888.12-1888.39" + wire width 8 \builder_csrbank0_scratch3_w + attribute \src "ls180.v:1887.6-1887.34" + wire \builder_csrbank0_scratch3_we + attribute \src "ls180.v:1917.6-1917.26" + wire \builder_csrbank0_sel + attribute \src "ls180.v:2388.12-2388.40" + wire width 8 \builder_csrbank10_control0_r + attribute \src "ls180.v:2387.6-2387.35" + wire \builder_csrbank10_control0_re + attribute \src "ls180.v:2390.12-2390.40" + wire width 8 \builder_csrbank10_control0_w + attribute \src "ls180.v:2389.6-2389.35" + wire \builder_csrbank10_control0_we + attribute \src "ls180.v:2384.12-2384.40" + wire width 8 \builder_csrbank10_control1_r + attribute \src "ls180.v:2383.6-2383.35" + wire \builder_csrbank10_control1_re + attribute \src "ls180.v:2386.12-2386.40" + wire width 8 \builder_csrbank10_control1_w + attribute \src "ls180.v:2385.6-2385.35" + wire \builder_csrbank10_control1_we + attribute \src "ls180.v:2404.6-2404.29" + wire \builder_csrbank10_cs0_r + attribute \src "ls180.v:2403.6-2403.30" + wire \builder_csrbank10_cs0_re + attribute \src "ls180.v:2406.6-2406.29" + wire \builder_csrbank10_cs0_w + attribute \src "ls180.v:2405.6-2405.30" + wire \builder_csrbank10_cs0_we + attribute \src "ls180.v:2408.6-2408.35" + wire \builder_csrbank10_loopback0_r + attribute \src "ls180.v:2407.6-2407.36" + wire \builder_csrbank10_loopback0_re + attribute \src "ls180.v:2410.6-2410.35" + wire \builder_csrbank10_loopback0_w + attribute \src "ls180.v:2409.6-2409.36" + wire \builder_csrbank10_loopback0_we + attribute \src "ls180.v:2400.12-2400.36" + wire width 8 \builder_csrbank10_miso_r + attribute \src "ls180.v:2399.6-2399.31" + wire \builder_csrbank10_miso_re + attribute \src "ls180.v:2402.12-2402.36" + wire width 8 \builder_csrbank10_miso_w + attribute \src "ls180.v:2401.6-2401.31" + wire \builder_csrbank10_miso_we + attribute \src "ls180.v:2396.12-2396.37" + wire width 8 \builder_csrbank10_mosi0_r + attribute \src "ls180.v:2395.6-2395.32" + wire \builder_csrbank10_mosi0_re + attribute \src "ls180.v:2398.12-2398.37" + wire width 8 \builder_csrbank10_mosi0_w + attribute \src "ls180.v:2397.6-2397.32" + wire \builder_csrbank10_mosi0_we + attribute \src "ls180.v:2411.6-2411.27" + wire \builder_csrbank10_sel + attribute \src "ls180.v:2392.6-2392.32" + wire \builder_csrbank10_status_r + attribute \src "ls180.v:2391.6-2391.33" + wire \builder_csrbank10_status_re + attribute \src "ls180.v:2394.6-2394.32" + wire \builder_csrbank10_status_w + attribute \src "ls180.v:2393.6-2393.33" + wire \builder_csrbank10_status_we + attribute \src "ls180.v:2449.12-2449.44" + wire width 8 \builder_csrbank11_clk_divider0_r + attribute \src "ls180.v:2448.6-2448.39" + wire \builder_csrbank11_clk_divider0_re + attribute \src "ls180.v:2451.12-2451.44" + wire width 8 \builder_csrbank11_clk_divider0_w + attribute \src "ls180.v:2450.6-2450.39" + wire \builder_csrbank11_clk_divider0_we + attribute \src "ls180.v:2445.12-2445.44" + wire width 8 \builder_csrbank11_clk_divider1_r + attribute \src "ls180.v:2444.6-2444.39" + wire \builder_csrbank11_clk_divider1_re + attribute \src "ls180.v:2447.12-2447.44" + wire width 8 \builder_csrbank11_clk_divider1_w + attribute \src "ls180.v:2446.6-2446.39" + wire \builder_csrbank11_clk_divider1_we + attribute \src "ls180.v:2421.12-2421.40" + wire width 8 \builder_csrbank11_control0_r + attribute \src "ls180.v:2420.6-2420.35" + wire \builder_csrbank11_control0_re + attribute \src "ls180.v:2423.12-2423.40" + wire width 8 \builder_csrbank11_control0_w + attribute \src "ls180.v:2422.6-2422.35" + wire \builder_csrbank11_control0_we + attribute \src "ls180.v:2417.12-2417.40" + wire width 8 \builder_csrbank11_control1_r + attribute \src "ls180.v:2416.6-2416.35" + wire \builder_csrbank11_control1_re + attribute \src "ls180.v:2419.12-2419.40" + wire width 8 \builder_csrbank11_control1_w + attribute \src "ls180.v:2418.6-2418.35" + wire \builder_csrbank11_control1_we + attribute \src "ls180.v:2437.6-2437.29" + wire \builder_csrbank11_cs0_r + attribute \src "ls180.v:2436.6-2436.30" + wire \builder_csrbank11_cs0_re + attribute \src "ls180.v:2439.6-2439.29" + wire \builder_csrbank11_cs0_w + attribute \src "ls180.v:2438.6-2438.30" + wire \builder_csrbank11_cs0_we + attribute \src "ls180.v:2441.6-2441.35" + wire \builder_csrbank11_loopback0_r + attribute \src "ls180.v:2440.6-2440.36" + wire \builder_csrbank11_loopback0_re + attribute \src "ls180.v:2443.6-2443.35" + wire \builder_csrbank11_loopback0_w + attribute \src "ls180.v:2442.6-2442.36" + wire \builder_csrbank11_loopback0_we + attribute \src "ls180.v:2433.12-2433.36" + wire width 8 \builder_csrbank11_miso_r + attribute \src "ls180.v:2432.6-2432.31" + wire \builder_csrbank11_miso_re + attribute \src "ls180.v:2435.12-2435.36" + wire width 8 \builder_csrbank11_miso_w + attribute \src "ls180.v:2434.6-2434.31" + wire \builder_csrbank11_miso_we + attribute \src "ls180.v:2429.12-2429.37" + wire width 8 \builder_csrbank11_mosi0_r + attribute \src "ls180.v:2428.6-2428.32" + wire \builder_csrbank11_mosi0_re + attribute \src "ls180.v:2431.12-2431.37" + wire width 8 \builder_csrbank11_mosi0_w + attribute \src "ls180.v:2430.6-2430.32" + wire \builder_csrbank11_mosi0_we + attribute \src "ls180.v:2452.6-2452.27" + wire \builder_csrbank11_sel + attribute \src "ls180.v:2425.6-2425.32" + wire \builder_csrbank11_status_r + attribute \src "ls180.v:2424.6-2424.33" + wire \builder_csrbank11_status_re + attribute \src "ls180.v:2427.6-2427.32" + wire \builder_csrbank11_status_w + attribute \src "ls180.v:2426.6-2426.33" + wire \builder_csrbank11_status_we + attribute \src "ls180.v:2490.6-2490.29" + wire \builder_csrbank12_en0_r + attribute \src "ls180.v:2489.6-2489.30" + wire \builder_csrbank12_en0_re + attribute \src "ls180.v:2492.6-2492.29" + wire \builder_csrbank12_en0_w + attribute \src "ls180.v:2491.6-2491.30" + wire \builder_csrbank12_en0_we + attribute \src "ls180.v:2514.6-2514.36" + wire \builder_csrbank12_ev_enable0_r + attribute \src "ls180.v:2513.6-2513.37" + wire \builder_csrbank12_ev_enable0_re + attribute \src "ls180.v:2516.6-2516.36" + wire \builder_csrbank12_ev_enable0_w + attribute \src "ls180.v:2515.6-2515.37" + wire \builder_csrbank12_ev_enable0_we + attribute \src "ls180.v:2470.12-2470.37" + wire width 8 \builder_csrbank12_load0_r + attribute \src "ls180.v:2469.6-2469.32" + wire \builder_csrbank12_load0_re + attribute \src "ls180.v:2472.12-2472.37" + wire width 8 \builder_csrbank12_load0_w + attribute \src "ls180.v:2471.6-2471.32" + wire \builder_csrbank12_load0_we + attribute \src "ls180.v:2466.12-2466.37" + wire width 8 \builder_csrbank12_load1_r + attribute \src "ls180.v:2465.6-2465.32" + wire \builder_csrbank12_load1_re + attribute \src "ls180.v:2468.12-2468.37" + wire width 8 \builder_csrbank12_load1_w + attribute \src "ls180.v:2467.6-2467.32" + wire \builder_csrbank12_load1_we + attribute \src "ls180.v:2462.12-2462.37" + wire width 8 \builder_csrbank12_load2_r + attribute \src "ls180.v:2461.6-2461.32" + wire \builder_csrbank12_load2_re + attribute \src "ls180.v:2464.12-2464.37" + wire width 8 \builder_csrbank12_load2_w + attribute \src "ls180.v:2463.6-2463.32" + wire \builder_csrbank12_load2_we + attribute \src "ls180.v:2458.12-2458.37" + wire width 8 \builder_csrbank12_load3_r + attribute \src "ls180.v:2457.6-2457.32" + wire \builder_csrbank12_load3_re + attribute \src "ls180.v:2460.12-2460.37" + wire width 8 \builder_csrbank12_load3_w + attribute \src "ls180.v:2459.6-2459.32" + wire \builder_csrbank12_load3_we + attribute \src "ls180.v:2486.12-2486.39" + wire width 8 \builder_csrbank12_reload0_r + attribute \src "ls180.v:2485.6-2485.34" + wire \builder_csrbank12_reload0_re + attribute \src "ls180.v:2488.12-2488.39" + wire width 8 \builder_csrbank12_reload0_w + attribute \src "ls180.v:2487.6-2487.34" + wire \builder_csrbank12_reload0_we + attribute \src "ls180.v:2482.12-2482.39" + wire width 8 \builder_csrbank12_reload1_r + attribute \src "ls180.v:2481.6-2481.34" + wire \builder_csrbank12_reload1_re + attribute \src "ls180.v:2484.12-2484.39" + wire width 8 \builder_csrbank12_reload1_w + attribute \src "ls180.v:2483.6-2483.34" + wire \builder_csrbank12_reload1_we + attribute \src "ls180.v:2478.12-2478.39" + wire width 8 \builder_csrbank12_reload2_r + attribute \src "ls180.v:2477.6-2477.34" + wire \builder_csrbank12_reload2_re + attribute \src "ls180.v:2480.12-2480.39" + wire width 8 \builder_csrbank12_reload2_w + attribute \src "ls180.v:2479.6-2479.34" + wire \builder_csrbank12_reload2_we + attribute \src "ls180.v:2474.12-2474.39" + wire width 8 \builder_csrbank12_reload3_r + attribute \src "ls180.v:2473.6-2473.34" + wire \builder_csrbank12_reload3_re + attribute \src "ls180.v:2476.12-2476.39" + wire width 8 \builder_csrbank12_reload3_w + attribute \src "ls180.v:2475.6-2475.34" + wire \builder_csrbank12_reload3_we + attribute \src "ls180.v:2517.6-2517.27" + wire \builder_csrbank12_sel + attribute \src "ls180.v:2494.6-2494.39" + wire \builder_csrbank12_update_value0_r + attribute \src "ls180.v:2493.6-2493.40" + wire \builder_csrbank12_update_value0_re + attribute \src "ls180.v:2496.6-2496.39" + wire \builder_csrbank12_update_value0_w + attribute \src "ls180.v:2495.6-2495.40" + wire \builder_csrbank12_update_value0_we + attribute \src "ls180.v:2510.12-2510.38" + wire width 8 \builder_csrbank12_value0_r + attribute \src "ls180.v:2509.6-2509.33" + wire \builder_csrbank12_value0_re + attribute \src "ls180.v:2512.12-2512.38" + wire width 8 \builder_csrbank12_value0_w + attribute \src "ls180.v:2511.6-2511.33" + wire \builder_csrbank12_value0_we + attribute \src "ls180.v:2506.12-2506.38" + wire width 8 \builder_csrbank12_value1_r + attribute \src "ls180.v:2505.6-2505.33" + wire \builder_csrbank12_value1_re + attribute \src "ls180.v:2508.12-2508.38" + wire width 8 \builder_csrbank12_value1_w + attribute \src "ls180.v:2507.6-2507.33" + wire \builder_csrbank12_value1_we + attribute \src "ls180.v:2502.12-2502.38" + wire width 8 \builder_csrbank12_value2_r + attribute \src "ls180.v:2501.6-2501.33" + wire \builder_csrbank12_value2_re + attribute \src "ls180.v:2504.12-2504.38" + wire width 8 \builder_csrbank12_value2_w + attribute \src "ls180.v:2503.6-2503.33" + wire \builder_csrbank12_value2_we + attribute \src "ls180.v:2498.12-2498.38" + wire width 8 \builder_csrbank12_value3_r + attribute \src "ls180.v:2497.6-2497.33" + wire \builder_csrbank12_value3_re + attribute \src "ls180.v:2500.12-2500.38" + wire width 8 \builder_csrbank12_value3_w + attribute \src "ls180.v:2499.6-2499.33" + wire \builder_csrbank12_value3_we + attribute \src "ls180.v:2531.12-2531.42" + wire width 2 \builder_csrbank13_ev_enable0_r + attribute \src "ls180.v:2530.6-2530.37" + wire \builder_csrbank13_ev_enable0_re + attribute \src "ls180.v:2533.12-2533.42" + wire width 2 \builder_csrbank13_ev_enable0_w + attribute \src "ls180.v:2532.6-2532.37" + wire \builder_csrbank13_ev_enable0_we + attribute \src "ls180.v:2527.6-2527.33" + wire \builder_csrbank13_rxempty_r + attribute \src "ls180.v:2526.6-2526.34" + wire \builder_csrbank13_rxempty_re + attribute \src "ls180.v:2529.6-2529.33" + wire \builder_csrbank13_rxempty_w + attribute \src "ls180.v:2528.6-2528.34" + wire \builder_csrbank13_rxempty_we + attribute \src "ls180.v:2539.6-2539.32" + wire \builder_csrbank13_rxfull_r + attribute \src "ls180.v:2538.6-2538.33" + wire \builder_csrbank13_rxfull_re + attribute \src "ls180.v:2541.6-2541.32" + wire \builder_csrbank13_rxfull_w + attribute \src "ls180.v:2540.6-2540.33" + wire \builder_csrbank13_rxfull_we + attribute \src "ls180.v:2542.6-2542.27" + wire \builder_csrbank13_sel + attribute \src "ls180.v:2535.6-2535.33" + wire \builder_csrbank13_txempty_r + attribute \src "ls180.v:2534.6-2534.34" + wire \builder_csrbank13_txempty_re + attribute \src "ls180.v:2537.6-2537.33" + wire \builder_csrbank13_txempty_w + attribute \src "ls180.v:2536.6-2536.34" + wire \builder_csrbank13_txempty_we + attribute \src "ls180.v:2523.6-2523.32" + wire \builder_csrbank13_txfull_r + attribute \src "ls180.v:2522.6-2522.33" + wire \builder_csrbank13_txfull_re + attribute \src "ls180.v:2525.6-2525.32" + wire \builder_csrbank13_txfull_w + attribute \src "ls180.v:2524.6-2524.33" + wire \builder_csrbank13_txfull_we + attribute \src "ls180.v:2563.6-2563.27" + wire \builder_csrbank14_sel + attribute \src "ls180.v:2560.12-2560.44" + wire width 8 \builder_csrbank14_tuning_word0_r + attribute \src "ls180.v:2559.6-2559.39" + wire \builder_csrbank14_tuning_word0_re + attribute \src "ls180.v:2562.12-2562.44" + wire width 8 \builder_csrbank14_tuning_word0_w + attribute \src "ls180.v:2561.6-2561.39" + wire \builder_csrbank14_tuning_word0_we + attribute \src "ls180.v:2556.12-2556.44" + wire width 8 \builder_csrbank14_tuning_word1_r + attribute \src "ls180.v:2555.6-2555.39" + wire \builder_csrbank14_tuning_word1_re + attribute \src "ls180.v:2558.12-2558.44" + wire width 8 \builder_csrbank14_tuning_word1_w + attribute \src "ls180.v:2557.6-2557.39" + wire \builder_csrbank14_tuning_word1_we + attribute \src "ls180.v:2552.12-2552.44" + wire width 8 \builder_csrbank14_tuning_word2_r + attribute \src "ls180.v:2551.6-2551.39" + wire \builder_csrbank14_tuning_word2_re + attribute \src "ls180.v:2554.12-2554.44" + wire width 8 \builder_csrbank14_tuning_word2_w + attribute \src "ls180.v:2553.6-2553.39" + wire \builder_csrbank14_tuning_word2_we + attribute \src "ls180.v:2548.12-2548.44" + wire width 8 \builder_csrbank14_tuning_word3_r + attribute \src "ls180.v:2547.6-2547.39" + wire \builder_csrbank14_tuning_word3_re + attribute \src "ls180.v:2550.12-2550.44" + wire width 8 \builder_csrbank14_tuning_word3_w + attribute \src "ls180.v:2549.6-2549.39" + wire \builder_csrbank14_tuning_word3_we + attribute \src "ls180.v:1935.12-1935.34" + wire width 8 \builder_csrbank1_in0_r + attribute \src "ls180.v:1934.6-1934.29" + wire \builder_csrbank1_in0_re + attribute \src "ls180.v:1937.12-1937.34" + wire width 8 \builder_csrbank1_in0_w + attribute \src "ls180.v:1936.6-1936.29" + wire \builder_csrbank1_in0_we + attribute \src "ls180.v:1931.12-1931.34" + wire width 8 \builder_csrbank1_in1_r + attribute \src "ls180.v:1930.6-1930.29" + wire \builder_csrbank1_in1_re + attribute \src "ls180.v:1933.12-1933.34" + wire width 8 \builder_csrbank1_in1_w + attribute \src "ls180.v:1932.6-1932.29" + wire \builder_csrbank1_in1_we + attribute \src "ls180.v:1927.12-1927.34" + wire width 8 \builder_csrbank1_oe0_r + attribute \src "ls180.v:1926.6-1926.29" + wire \builder_csrbank1_oe0_re + attribute \src "ls180.v:1929.12-1929.34" + wire width 8 \builder_csrbank1_oe0_w + attribute \src "ls180.v:1928.6-1928.29" + wire \builder_csrbank1_oe0_we + attribute \src "ls180.v:1923.12-1923.34" + wire width 8 \builder_csrbank1_oe1_r + attribute \src "ls180.v:1922.6-1922.29" + wire \builder_csrbank1_oe1_re + attribute \src "ls180.v:1925.12-1925.34" + wire width 8 \builder_csrbank1_oe1_w + attribute \src "ls180.v:1924.6-1924.29" + wire \builder_csrbank1_oe1_we + attribute \src "ls180.v:1943.12-1943.35" + wire width 8 \builder_csrbank1_out0_r + attribute \src "ls180.v:1942.6-1942.30" + wire \builder_csrbank1_out0_re + attribute \src "ls180.v:1945.12-1945.35" + wire width 8 \builder_csrbank1_out0_w + attribute \src "ls180.v:1944.6-1944.30" + wire \builder_csrbank1_out0_we + attribute \src "ls180.v:1939.12-1939.35" + wire width 8 \builder_csrbank1_out1_r + attribute \src "ls180.v:1938.6-1938.30" + wire \builder_csrbank1_out1_re + attribute \src "ls180.v:1941.12-1941.35" + wire width 8 \builder_csrbank1_out1_w + attribute \src "ls180.v:1940.6-1940.30" + wire \builder_csrbank1_out1_we + attribute \src "ls180.v:1946.6-1946.26" + wire \builder_csrbank1_sel + attribute \src "ls180.v:1956.6-1956.26" + wire \builder_csrbank2_r_r + attribute \src "ls180.v:1955.6-1955.27" + wire \builder_csrbank2_r_re + attribute \src "ls180.v:1958.6-1958.26" + wire \builder_csrbank2_r_w + attribute \src "ls180.v:1957.6-1957.27" + wire \builder_csrbank2_r_we + attribute \src "ls180.v:1959.6-1959.26" + wire \builder_csrbank2_sel + attribute \src "ls180.v:1952.12-1952.33" + wire width 3 \builder_csrbank2_w0_r + attribute \src "ls180.v:1951.6-1951.28" + wire \builder_csrbank2_w0_re + attribute \src "ls180.v:1954.12-1954.33" + wire width 3 \builder_csrbank2_w0_w + attribute \src "ls180.v:1953.6-1953.28" + wire \builder_csrbank2_w0_we + attribute \src "ls180.v:1965.6-1965.32" + wire \builder_csrbank3_enable0_r + attribute \src "ls180.v:1964.6-1964.33" + wire \builder_csrbank3_enable0_re + attribute \src "ls180.v:1967.6-1967.32" + wire \builder_csrbank3_enable0_w + attribute \src "ls180.v:1966.6-1966.33" + wire \builder_csrbank3_enable0_we + attribute \src "ls180.v:1997.12-1997.38" + wire width 8 \builder_csrbank3_period0_r + attribute \src "ls180.v:1996.6-1996.33" + wire \builder_csrbank3_period0_re + attribute \src "ls180.v:1999.12-1999.38" + wire width 8 \builder_csrbank3_period0_w + attribute \src "ls180.v:1998.6-1998.33" + wire \builder_csrbank3_period0_we + attribute \src "ls180.v:1993.12-1993.38" + wire width 8 \builder_csrbank3_period1_r + attribute \src "ls180.v:1992.6-1992.33" + wire \builder_csrbank3_period1_re + attribute \src "ls180.v:1995.12-1995.38" + wire width 8 \builder_csrbank3_period1_w + attribute \src "ls180.v:1994.6-1994.33" + wire \builder_csrbank3_period1_we + attribute \src "ls180.v:1989.12-1989.38" + wire width 8 \builder_csrbank3_period2_r + attribute \src "ls180.v:1988.6-1988.33" + wire \builder_csrbank3_period2_re + attribute \src "ls180.v:1991.12-1991.38" + wire width 8 \builder_csrbank3_period2_w + attribute \src "ls180.v:1990.6-1990.33" + wire \builder_csrbank3_period2_we + attribute \src "ls180.v:1985.12-1985.38" + wire width 8 \builder_csrbank3_period3_r + attribute \src "ls180.v:1984.6-1984.33" + wire \builder_csrbank3_period3_re + attribute \src "ls180.v:1987.12-1987.38" + wire width 8 \builder_csrbank3_period3_w + attribute \src "ls180.v:1986.6-1986.33" + wire \builder_csrbank3_period3_we + attribute \src "ls180.v:2000.6-2000.26" + wire \builder_csrbank3_sel + attribute \src "ls180.v:1981.12-1981.37" + wire width 8 \builder_csrbank3_width0_r + attribute \src "ls180.v:1980.6-1980.32" + wire \builder_csrbank3_width0_re + attribute \src "ls180.v:1983.12-1983.37" + wire width 8 \builder_csrbank3_width0_w + attribute \src "ls180.v:1982.6-1982.32" + wire \builder_csrbank3_width0_we + attribute \src "ls180.v:1977.12-1977.37" + wire width 8 \builder_csrbank3_width1_r + attribute \src "ls180.v:1976.6-1976.32" + wire \builder_csrbank3_width1_re + attribute \src "ls180.v:1979.12-1979.37" + wire width 8 \builder_csrbank3_width1_w + attribute \src "ls180.v:1978.6-1978.32" + wire \builder_csrbank3_width1_we + attribute \src "ls180.v:1973.12-1973.37" + wire width 8 \builder_csrbank3_width2_r + attribute \src "ls180.v:1972.6-1972.32" + wire \builder_csrbank3_width2_re + attribute \src "ls180.v:1975.12-1975.37" + wire width 8 \builder_csrbank3_width2_w + attribute \src "ls180.v:1974.6-1974.32" + wire \builder_csrbank3_width2_we + attribute \src "ls180.v:1969.12-1969.37" + wire width 8 \builder_csrbank3_width3_r + attribute \src "ls180.v:1968.6-1968.32" + wire \builder_csrbank3_width3_re + attribute \src "ls180.v:1971.12-1971.37" + wire width 8 \builder_csrbank3_width3_w + attribute \src "ls180.v:1970.6-1970.32" + wire \builder_csrbank3_width3_we + attribute \src "ls180.v:2006.6-2006.32" + wire \builder_csrbank4_enable0_r + attribute \src "ls180.v:2005.6-2005.33" + wire \builder_csrbank4_enable0_re + attribute \src "ls180.v:2008.6-2008.32" + wire \builder_csrbank4_enable0_w + attribute \src "ls180.v:2007.6-2007.33" + wire \builder_csrbank4_enable0_we + attribute \src "ls180.v:2038.12-2038.38" + wire width 8 \builder_csrbank4_period0_r + attribute \src "ls180.v:2037.6-2037.33" + wire \builder_csrbank4_period0_re + attribute \src "ls180.v:2040.12-2040.38" + wire width 8 \builder_csrbank4_period0_w + attribute \src "ls180.v:2039.6-2039.33" + wire \builder_csrbank4_period0_we + attribute \src "ls180.v:2034.12-2034.38" + wire width 8 \builder_csrbank4_period1_r + attribute \src "ls180.v:2033.6-2033.33" + wire \builder_csrbank4_period1_re + attribute \src "ls180.v:2036.12-2036.38" + wire width 8 \builder_csrbank4_period1_w + attribute \src "ls180.v:2035.6-2035.33" + wire \builder_csrbank4_period1_we + attribute \src "ls180.v:2030.12-2030.38" + wire width 8 \builder_csrbank4_period2_r + attribute \src "ls180.v:2029.6-2029.33" + wire \builder_csrbank4_period2_re + attribute \src "ls180.v:2032.12-2032.38" + wire width 8 \builder_csrbank4_period2_w + attribute \src "ls180.v:2031.6-2031.33" + wire \builder_csrbank4_period2_we + attribute \src "ls180.v:2026.12-2026.38" + wire width 8 \builder_csrbank4_period3_r + attribute \src "ls180.v:2025.6-2025.33" + wire \builder_csrbank4_period3_re + attribute \src "ls180.v:2028.12-2028.38" + wire width 8 \builder_csrbank4_period3_w + attribute \src "ls180.v:2027.6-2027.33" + wire \builder_csrbank4_period3_we + attribute \src "ls180.v:2041.6-2041.26" + wire \builder_csrbank4_sel + attribute \src "ls180.v:2022.12-2022.37" + wire width 8 \builder_csrbank4_width0_r + attribute \src "ls180.v:2021.6-2021.32" + wire \builder_csrbank4_width0_re + attribute \src "ls180.v:2024.12-2024.37" + wire width 8 \builder_csrbank4_width0_w + attribute \src "ls180.v:2023.6-2023.32" + wire \builder_csrbank4_width0_we + attribute \src "ls180.v:2018.12-2018.37" + wire width 8 \builder_csrbank4_width1_r + attribute \src "ls180.v:2017.6-2017.32" + wire \builder_csrbank4_width1_re + attribute \src "ls180.v:2020.12-2020.37" + wire width 8 \builder_csrbank4_width1_w + attribute \src "ls180.v:2019.6-2019.32" + wire \builder_csrbank4_width1_we + attribute \src "ls180.v:2014.12-2014.37" + wire width 8 \builder_csrbank4_width2_r + attribute \src "ls180.v:2013.6-2013.32" + wire \builder_csrbank4_width2_re + attribute \src "ls180.v:2016.12-2016.37" + wire width 8 \builder_csrbank4_width2_w + attribute \src "ls180.v:2015.6-2015.32" + wire \builder_csrbank4_width2_we + attribute \src "ls180.v:2010.12-2010.37" + wire width 8 \builder_csrbank4_width3_r + attribute \src "ls180.v:2009.6-2009.32" + wire \builder_csrbank4_width3_re + attribute \src "ls180.v:2012.12-2012.37" + wire width 8 \builder_csrbank4_width3_w + attribute \src "ls180.v:2011.6-2011.32" + wire \builder_csrbank4_width3_we + attribute \src "ls180.v:2075.12-2075.40" + wire width 8 \builder_csrbank5_dma_base0_r + attribute \src "ls180.v:2074.6-2074.35" + wire \builder_csrbank5_dma_base0_re + attribute \src "ls180.v:2077.12-2077.40" + wire width 8 \builder_csrbank5_dma_base0_w + attribute \src "ls180.v:2076.6-2076.35" + wire \builder_csrbank5_dma_base0_we + attribute \src "ls180.v:2071.12-2071.40" + wire width 8 \builder_csrbank5_dma_base1_r + attribute \src "ls180.v:2070.6-2070.35" + wire \builder_csrbank5_dma_base1_re + attribute \src "ls180.v:2073.12-2073.40" + wire width 8 \builder_csrbank5_dma_base1_w + attribute \src "ls180.v:2072.6-2072.35" + wire \builder_csrbank5_dma_base1_we + attribute \src "ls180.v:2067.12-2067.40" + wire width 8 \builder_csrbank5_dma_base2_r + attribute \src "ls180.v:2066.6-2066.35" + wire \builder_csrbank5_dma_base2_re + attribute \src "ls180.v:2069.12-2069.40" + wire width 8 \builder_csrbank5_dma_base2_w + attribute \src "ls180.v:2068.6-2068.35" + wire \builder_csrbank5_dma_base2_we + attribute \src "ls180.v:2063.12-2063.40" + wire width 8 \builder_csrbank5_dma_base3_r + attribute \src "ls180.v:2062.6-2062.35" + wire \builder_csrbank5_dma_base3_re + attribute \src "ls180.v:2065.12-2065.40" + wire width 8 \builder_csrbank5_dma_base3_w + attribute \src "ls180.v:2064.6-2064.35" + wire \builder_csrbank5_dma_base3_we + attribute \src "ls180.v:2059.12-2059.40" + wire width 8 \builder_csrbank5_dma_base4_r + attribute \src "ls180.v:2058.6-2058.35" + wire \builder_csrbank5_dma_base4_re + attribute \src "ls180.v:2061.12-2061.40" + wire width 8 \builder_csrbank5_dma_base4_w + attribute \src "ls180.v:2060.6-2060.35" + wire \builder_csrbank5_dma_base4_we + attribute \src "ls180.v:2055.12-2055.40" + wire width 8 \builder_csrbank5_dma_base5_r + attribute \src "ls180.v:2054.6-2054.35" + wire \builder_csrbank5_dma_base5_re + attribute \src "ls180.v:2057.12-2057.40" + wire width 8 \builder_csrbank5_dma_base5_w + attribute \src "ls180.v:2056.6-2056.35" + wire \builder_csrbank5_dma_base5_we + attribute \src "ls180.v:2051.12-2051.40" + wire width 8 \builder_csrbank5_dma_base6_r + attribute \src "ls180.v:2050.6-2050.35" + wire \builder_csrbank5_dma_base6_re + attribute \src "ls180.v:2053.12-2053.40" + wire width 8 \builder_csrbank5_dma_base6_w + attribute \src "ls180.v:2052.6-2052.35" + wire \builder_csrbank5_dma_base6_we + attribute \src "ls180.v:2047.12-2047.40" + wire width 8 \builder_csrbank5_dma_base7_r + attribute \src "ls180.v:2046.6-2046.35" + wire \builder_csrbank5_dma_base7_re + attribute \src "ls180.v:2049.12-2049.40" + wire width 8 \builder_csrbank5_dma_base7_w + attribute \src "ls180.v:2048.6-2048.35" + wire \builder_csrbank5_dma_base7_we + attribute \src "ls180.v:2099.6-2099.33" + wire \builder_csrbank5_dma_done_r + attribute \src "ls180.v:2098.6-2098.34" + wire \builder_csrbank5_dma_done_re + attribute \src "ls180.v:2101.6-2101.33" + wire \builder_csrbank5_dma_done_w + attribute \src "ls180.v:2100.6-2100.34" + wire \builder_csrbank5_dma_done_we + attribute \src "ls180.v:2095.6-2095.36" + wire \builder_csrbank5_dma_enable0_r + attribute \src "ls180.v:2094.6-2094.37" + wire \builder_csrbank5_dma_enable0_re + attribute \src "ls180.v:2097.6-2097.36" + wire \builder_csrbank5_dma_enable0_w + attribute \src "ls180.v:2096.6-2096.37" + wire \builder_csrbank5_dma_enable0_we + attribute \src "ls180.v:2091.12-2091.42" + wire width 8 \builder_csrbank5_dma_length0_r + attribute \src "ls180.v:2090.6-2090.37" + wire \builder_csrbank5_dma_length0_re + attribute \src "ls180.v:2093.12-2093.42" + wire width 8 \builder_csrbank5_dma_length0_w + attribute \src "ls180.v:2092.6-2092.37" + wire \builder_csrbank5_dma_length0_we + attribute \src "ls180.v:2087.12-2087.42" + wire width 8 \builder_csrbank5_dma_length1_r + attribute \src "ls180.v:2086.6-2086.37" + wire \builder_csrbank5_dma_length1_re + attribute \src "ls180.v:2089.12-2089.42" + wire width 8 \builder_csrbank5_dma_length1_w + attribute \src "ls180.v:2088.6-2088.37" + wire \builder_csrbank5_dma_length1_we + attribute \src "ls180.v:2083.12-2083.42" + wire width 8 \builder_csrbank5_dma_length2_r + attribute \src "ls180.v:2082.6-2082.37" + wire \builder_csrbank5_dma_length2_re + attribute \src "ls180.v:2085.12-2085.42" + wire width 8 \builder_csrbank5_dma_length2_w + attribute \src "ls180.v:2084.6-2084.37" + wire \builder_csrbank5_dma_length2_we + attribute \src "ls180.v:2079.12-2079.42" + wire width 8 \builder_csrbank5_dma_length3_r + attribute \src "ls180.v:2078.6-2078.37" + wire \builder_csrbank5_dma_length3_re + attribute \src "ls180.v:2081.12-2081.42" + wire width 8 \builder_csrbank5_dma_length3_w + attribute \src "ls180.v:2080.6-2080.37" + wire \builder_csrbank5_dma_length3_we + attribute \src "ls180.v:2103.6-2103.34" + wire \builder_csrbank5_dma_loop0_r + attribute \src "ls180.v:2102.6-2102.35" + wire \builder_csrbank5_dma_loop0_re + attribute \src "ls180.v:2105.6-2105.34" + wire \builder_csrbank5_dma_loop0_w + attribute \src "ls180.v:2104.6-2104.35" + wire \builder_csrbank5_dma_loop0_we + attribute \src "ls180.v:2106.6-2106.26" + wire \builder_csrbank5_sel + attribute \src "ls180.v:2236.12-2236.43" + wire width 8 \builder_csrbank6_block_count0_r + attribute \src "ls180.v:2235.6-2235.38" + wire \builder_csrbank6_block_count0_re + attribute \src "ls180.v:2238.12-2238.43" + wire width 8 \builder_csrbank6_block_count0_w + attribute \src "ls180.v:2237.6-2237.38" + wire \builder_csrbank6_block_count0_we + attribute \src "ls180.v:2232.12-2232.43" + wire width 8 \builder_csrbank6_block_count1_r + attribute \src "ls180.v:2231.6-2231.38" + wire \builder_csrbank6_block_count1_re + attribute \src "ls180.v:2234.12-2234.43" + wire width 8 \builder_csrbank6_block_count1_w + attribute \src "ls180.v:2233.6-2233.38" + wire \builder_csrbank6_block_count1_we + attribute \src "ls180.v:2228.12-2228.43" + wire width 8 \builder_csrbank6_block_count2_r + attribute \src "ls180.v:2227.6-2227.38" + wire \builder_csrbank6_block_count2_re + attribute \src "ls180.v:2230.12-2230.43" + wire width 8 \builder_csrbank6_block_count2_w + attribute \src "ls180.v:2229.6-2229.38" + wire \builder_csrbank6_block_count2_we + attribute \src "ls180.v:2224.12-2224.43" + wire width 8 \builder_csrbank6_block_count3_r + attribute \src "ls180.v:2223.6-2223.38" + wire \builder_csrbank6_block_count3_re + attribute \src "ls180.v:2226.12-2226.43" + wire width 8 \builder_csrbank6_block_count3_w + attribute \src "ls180.v:2225.6-2225.38" + wire \builder_csrbank6_block_count3_we + attribute \src "ls180.v:2220.12-2220.44" + wire width 8 \builder_csrbank6_block_length0_r + attribute \src "ls180.v:2219.6-2219.39" + wire \builder_csrbank6_block_length0_re + attribute \src "ls180.v:2222.12-2222.44" + wire width 8 \builder_csrbank6_block_length0_w + attribute \src "ls180.v:2221.6-2221.39" + wire \builder_csrbank6_block_length0_we + attribute \src "ls180.v:2216.12-2216.44" + wire width 2 \builder_csrbank6_block_length1_r + attribute \src "ls180.v:2215.6-2215.39" + wire \builder_csrbank6_block_length1_re + attribute \src "ls180.v:2218.12-2218.44" + wire width 2 \builder_csrbank6_block_length1_w + attribute \src "ls180.v:2217.6-2217.39" + wire \builder_csrbank6_block_length1_we + attribute \src "ls180.v:2124.12-2124.44" + wire width 8 \builder_csrbank6_cmd_argument0_r + attribute \src "ls180.v:2123.6-2123.39" + wire \builder_csrbank6_cmd_argument0_re + attribute \src "ls180.v:2126.12-2126.44" + wire width 8 \builder_csrbank6_cmd_argument0_w + attribute \src "ls180.v:2125.6-2125.39" + wire \builder_csrbank6_cmd_argument0_we + attribute \src "ls180.v:2120.12-2120.44" + wire width 8 \builder_csrbank6_cmd_argument1_r + attribute \src "ls180.v:2119.6-2119.39" + wire \builder_csrbank6_cmd_argument1_re + attribute \src "ls180.v:2122.12-2122.44" + wire width 8 \builder_csrbank6_cmd_argument1_w + attribute \src "ls180.v:2121.6-2121.39" + wire \builder_csrbank6_cmd_argument1_we + attribute \src "ls180.v:2116.12-2116.44" + wire width 8 \builder_csrbank6_cmd_argument2_r + attribute \src "ls180.v:2115.6-2115.39" + wire \builder_csrbank6_cmd_argument2_re + attribute \src "ls180.v:2118.12-2118.44" + wire width 8 \builder_csrbank6_cmd_argument2_w + attribute \src "ls180.v:2117.6-2117.39" + wire \builder_csrbank6_cmd_argument2_we + attribute \src "ls180.v:2112.12-2112.44" + wire width 8 \builder_csrbank6_cmd_argument3_r + attribute \src "ls180.v:2111.6-2111.39" + wire \builder_csrbank6_cmd_argument3_re + attribute \src "ls180.v:2114.12-2114.44" + wire width 8 \builder_csrbank6_cmd_argument3_w + attribute \src "ls180.v:2113.6-2113.39" + wire \builder_csrbank6_cmd_argument3_we + attribute \src "ls180.v:2140.12-2140.43" + wire width 8 \builder_csrbank6_cmd_command0_r + attribute \src "ls180.v:2139.6-2139.38" + wire \builder_csrbank6_cmd_command0_re + attribute \src "ls180.v:2142.12-2142.43" + wire width 8 \builder_csrbank6_cmd_command0_w + attribute \src "ls180.v:2141.6-2141.38" + wire \builder_csrbank6_cmd_command0_we + attribute \src "ls180.v:2136.12-2136.43" + wire width 8 \builder_csrbank6_cmd_command1_r + attribute \src "ls180.v:2135.6-2135.38" + wire \builder_csrbank6_cmd_command1_re + attribute \src "ls180.v:2138.12-2138.43" + wire width 8 \builder_csrbank6_cmd_command1_w + attribute \src "ls180.v:2137.6-2137.38" + wire \builder_csrbank6_cmd_command1_we + attribute \src "ls180.v:2132.12-2132.43" + wire width 8 \builder_csrbank6_cmd_command2_r + attribute \src "ls180.v:2131.6-2131.38" + wire \builder_csrbank6_cmd_command2_re + attribute \src "ls180.v:2134.12-2134.43" + wire width 8 \builder_csrbank6_cmd_command2_w + attribute \src "ls180.v:2133.6-2133.38" + wire \builder_csrbank6_cmd_command2_we + attribute \src "ls180.v:2128.12-2128.43" + wire width 8 \builder_csrbank6_cmd_command3_r + attribute \src "ls180.v:2127.6-2127.38" + wire \builder_csrbank6_cmd_command3_re + attribute \src "ls180.v:2130.12-2130.43" + wire width 8 \builder_csrbank6_cmd_command3_w + attribute \src "ls180.v:2129.6-2129.38" + wire \builder_csrbank6_cmd_command3_we + attribute \src "ls180.v:2208.12-2208.40" + wire width 4 \builder_csrbank6_cmd_event_r + attribute \src "ls180.v:2207.6-2207.35" + wire \builder_csrbank6_cmd_event_re + attribute \src "ls180.v:2210.12-2210.40" + wire width 4 \builder_csrbank6_cmd_event_w + attribute \src "ls180.v:2209.6-2209.35" + wire \builder_csrbank6_cmd_event_we + attribute \src "ls180.v:2204.12-2204.44" + wire width 8 \builder_csrbank6_cmd_response0_r + attribute \src "ls180.v:2203.6-2203.39" + wire \builder_csrbank6_cmd_response0_re + attribute \src "ls180.v:2206.12-2206.44" + wire width 8 \builder_csrbank6_cmd_response0_w + attribute \src "ls180.v:2205.6-2205.39" + wire \builder_csrbank6_cmd_response0_we + attribute \src "ls180.v:2164.12-2164.45" + wire width 8 \builder_csrbank6_cmd_response10_r + attribute \src "ls180.v:2163.6-2163.40" + wire \builder_csrbank6_cmd_response10_re + attribute \src "ls180.v:2166.12-2166.45" + wire width 8 \builder_csrbank6_cmd_response10_w + attribute \src "ls180.v:2165.6-2165.40" + wire \builder_csrbank6_cmd_response10_we + attribute \src "ls180.v:2160.12-2160.45" + wire width 8 \builder_csrbank6_cmd_response11_r + attribute \src "ls180.v:2159.6-2159.40" + wire \builder_csrbank6_cmd_response11_re + attribute \src "ls180.v:2162.12-2162.45" + wire width 8 \builder_csrbank6_cmd_response11_w + attribute \src "ls180.v:2161.6-2161.40" + wire \builder_csrbank6_cmd_response11_we + attribute \src "ls180.v:2156.12-2156.45" + wire width 8 \builder_csrbank6_cmd_response12_r + attribute \src "ls180.v:2155.6-2155.40" + wire \builder_csrbank6_cmd_response12_re + attribute \src "ls180.v:2158.12-2158.45" + wire width 8 \builder_csrbank6_cmd_response12_w + attribute \src "ls180.v:2157.6-2157.40" + wire \builder_csrbank6_cmd_response12_we + attribute \src "ls180.v:2152.12-2152.45" + wire width 8 \builder_csrbank6_cmd_response13_r + attribute \src "ls180.v:2151.6-2151.40" + wire \builder_csrbank6_cmd_response13_re + attribute \src "ls180.v:2154.12-2154.45" + wire width 8 \builder_csrbank6_cmd_response13_w + attribute \src "ls180.v:2153.6-2153.40" + wire \builder_csrbank6_cmd_response13_we + attribute \src "ls180.v:2148.12-2148.45" + wire width 8 \builder_csrbank6_cmd_response14_r + attribute \src "ls180.v:2147.6-2147.40" + wire \builder_csrbank6_cmd_response14_re + attribute \src "ls180.v:2150.12-2150.45" + wire width 8 \builder_csrbank6_cmd_response14_w + attribute \src "ls180.v:2149.6-2149.40" + wire \builder_csrbank6_cmd_response14_we + attribute \src "ls180.v:2144.12-2144.45" + wire width 8 \builder_csrbank6_cmd_response15_r + attribute \src "ls180.v:2143.6-2143.40" + wire \builder_csrbank6_cmd_response15_re + attribute \src "ls180.v:2146.12-2146.45" + wire width 8 \builder_csrbank6_cmd_response15_w + attribute \src "ls180.v:2145.6-2145.40" + wire \builder_csrbank6_cmd_response15_we + attribute \src "ls180.v:2200.12-2200.44" + wire width 8 \builder_csrbank6_cmd_response1_r + attribute \src "ls180.v:2199.6-2199.39" + wire \builder_csrbank6_cmd_response1_re + attribute \src "ls180.v:2202.12-2202.44" + wire width 8 \builder_csrbank6_cmd_response1_w + attribute \src "ls180.v:2201.6-2201.39" + wire \builder_csrbank6_cmd_response1_we + attribute \src "ls180.v:2196.12-2196.44" + wire width 8 \builder_csrbank6_cmd_response2_r + attribute \src "ls180.v:2195.6-2195.39" + wire \builder_csrbank6_cmd_response2_re + attribute \src "ls180.v:2198.12-2198.44" + wire width 8 \builder_csrbank6_cmd_response2_w + attribute \src "ls180.v:2197.6-2197.39" + wire \builder_csrbank6_cmd_response2_we + attribute \src "ls180.v:2192.12-2192.44" + wire width 8 \builder_csrbank6_cmd_response3_r + attribute \src "ls180.v:2191.6-2191.39" + wire \builder_csrbank6_cmd_response3_re + attribute \src "ls180.v:2194.12-2194.44" + wire width 8 \builder_csrbank6_cmd_response3_w + attribute \src "ls180.v:2193.6-2193.39" + wire \builder_csrbank6_cmd_response3_we + attribute \src "ls180.v:2188.12-2188.44" + wire width 8 \builder_csrbank6_cmd_response4_r + attribute \src "ls180.v:2187.6-2187.39" + wire \builder_csrbank6_cmd_response4_re + attribute \src "ls180.v:2190.12-2190.44" + wire width 8 \builder_csrbank6_cmd_response4_w + attribute \src "ls180.v:2189.6-2189.39" + wire \builder_csrbank6_cmd_response4_we + attribute \src "ls180.v:2184.12-2184.44" + wire width 8 \builder_csrbank6_cmd_response5_r + attribute \src "ls180.v:2183.6-2183.39" + wire \builder_csrbank6_cmd_response5_re + attribute \src "ls180.v:2186.12-2186.44" + wire width 8 \builder_csrbank6_cmd_response5_w + attribute \src "ls180.v:2185.6-2185.39" + wire \builder_csrbank6_cmd_response5_we + attribute \src "ls180.v:2180.12-2180.44" + wire width 8 \builder_csrbank6_cmd_response6_r + attribute \src "ls180.v:2179.6-2179.39" + wire \builder_csrbank6_cmd_response6_re + attribute \src "ls180.v:2182.12-2182.44" + wire width 8 \builder_csrbank6_cmd_response6_w + attribute \src "ls180.v:2181.6-2181.39" + wire \builder_csrbank6_cmd_response6_we + attribute \src "ls180.v:2176.12-2176.44" + wire width 8 \builder_csrbank6_cmd_response7_r + attribute \src "ls180.v:2175.6-2175.39" + wire \builder_csrbank6_cmd_response7_re + attribute \src "ls180.v:2178.12-2178.44" + wire width 8 \builder_csrbank6_cmd_response7_w + attribute \src "ls180.v:2177.6-2177.39" + wire \builder_csrbank6_cmd_response7_we + attribute \src "ls180.v:2172.12-2172.44" + wire width 8 \builder_csrbank6_cmd_response8_r + attribute \src "ls180.v:2171.6-2171.39" + wire \builder_csrbank6_cmd_response8_re + attribute \src "ls180.v:2174.12-2174.44" + wire width 8 \builder_csrbank6_cmd_response8_w + attribute \src "ls180.v:2173.6-2173.39" + wire \builder_csrbank6_cmd_response8_we + attribute \src "ls180.v:2168.12-2168.44" + wire width 8 \builder_csrbank6_cmd_response9_r + attribute \src "ls180.v:2167.6-2167.39" + wire \builder_csrbank6_cmd_response9_re + attribute \src "ls180.v:2170.12-2170.44" + wire width 8 \builder_csrbank6_cmd_response9_w + attribute \src "ls180.v:2169.6-2169.39" + wire \builder_csrbank6_cmd_response9_we + attribute \src "ls180.v:2212.12-2212.41" + wire width 4 \builder_csrbank6_data_event_r + attribute \src "ls180.v:2211.6-2211.36" + wire \builder_csrbank6_data_event_re + attribute \src "ls180.v:2214.12-2214.41" + wire width 4 \builder_csrbank6_data_event_w + attribute \src "ls180.v:2213.6-2213.36" + wire \builder_csrbank6_data_event_we + attribute \src "ls180.v:2239.6-2239.26" + wire \builder_csrbank6_sel + attribute \src "ls180.v:2273.12-2273.40" + wire width 8 \builder_csrbank7_dma_base0_r + attribute \src "ls180.v:2272.6-2272.35" + wire \builder_csrbank7_dma_base0_re + attribute \src "ls180.v:2275.12-2275.40" + wire width 8 \builder_csrbank7_dma_base0_w + attribute \src "ls180.v:2274.6-2274.35" + wire \builder_csrbank7_dma_base0_we + attribute \src "ls180.v:2269.12-2269.40" + wire width 8 \builder_csrbank7_dma_base1_r + attribute \src "ls180.v:2268.6-2268.35" + wire \builder_csrbank7_dma_base1_re + attribute \src "ls180.v:2271.12-2271.40" + wire width 8 \builder_csrbank7_dma_base1_w + attribute \src "ls180.v:2270.6-2270.35" + wire \builder_csrbank7_dma_base1_we + attribute \src "ls180.v:2265.12-2265.40" + wire width 8 \builder_csrbank7_dma_base2_r + attribute \src "ls180.v:2264.6-2264.35" + wire \builder_csrbank7_dma_base2_re + attribute \src "ls180.v:2267.12-2267.40" + wire width 8 \builder_csrbank7_dma_base2_w + attribute \src "ls180.v:2266.6-2266.35" + wire \builder_csrbank7_dma_base2_we + attribute \src "ls180.v:2261.12-2261.40" + wire width 8 \builder_csrbank7_dma_base3_r + attribute \src "ls180.v:2260.6-2260.35" + wire \builder_csrbank7_dma_base3_re + attribute \src "ls180.v:2263.12-2263.40" + wire width 8 \builder_csrbank7_dma_base3_w + attribute \src "ls180.v:2262.6-2262.35" + wire \builder_csrbank7_dma_base3_we + attribute \src "ls180.v:2257.12-2257.40" + wire width 8 \builder_csrbank7_dma_base4_r + attribute \src "ls180.v:2256.6-2256.35" + wire \builder_csrbank7_dma_base4_re + attribute \src "ls180.v:2259.12-2259.40" + wire width 8 \builder_csrbank7_dma_base4_w + attribute \src "ls180.v:2258.6-2258.35" + wire \builder_csrbank7_dma_base4_we + attribute \src "ls180.v:2253.12-2253.40" + wire width 8 \builder_csrbank7_dma_base5_r + attribute \src "ls180.v:2252.6-2252.35" + wire \builder_csrbank7_dma_base5_re + attribute \src "ls180.v:2255.12-2255.40" + wire width 8 \builder_csrbank7_dma_base5_w + attribute \src "ls180.v:2254.6-2254.35" + wire \builder_csrbank7_dma_base5_we + attribute \src "ls180.v:2249.12-2249.40" + wire width 8 \builder_csrbank7_dma_base6_r + attribute \src "ls180.v:2248.6-2248.35" + wire \builder_csrbank7_dma_base6_re + attribute \src "ls180.v:2251.12-2251.40" + wire width 8 \builder_csrbank7_dma_base6_w + attribute \src "ls180.v:2250.6-2250.35" + wire \builder_csrbank7_dma_base6_we + attribute \src "ls180.v:2245.12-2245.40" + wire width 8 \builder_csrbank7_dma_base7_r + attribute \src "ls180.v:2244.6-2244.35" + wire \builder_csrbank7_dma_base7_re + attribute \src "ls180.v:2247.12-2247.40" + wire width 8 \builder_csrbank7_dma_base7_w + attribute \src "ls180.v:2246.6-2246.35" + wire \builder_csrbank7_dma_base7_we + attribute \src "ls180.v:2297.6-2297.33" + wire \builder_csrbank7_dma_done_r + attribute \src "ls180.v:2296.6-2296.34" + wire \builder_csrbank7_dma_done_re + attribute \src "ls180.v:2299.6-2299.33" + wire \builder_csrbank7_dma_done_w + attribute \src "ls180.v:2298.6-2298.34" + wire \builder_csrbank7_dma_done_we + attribute \src "ls180.v:2293.6-2293.36" + wire \builder_csrbank7_dma_enable0_r + attribute \src "ls180.v:2292.6-2292.37" + wire \builder_csrbank7_dma_enable0_re + attribute \src "ls180.v:2295.6-2295.36" + wire \builder_csrbank7_dma_enable0_w + attribute \src "ls180.v:2294.6-2294.37" + wire \builder_csrbank7_dma_enable0_we + attribute \src "ls180.v:2289.12-2289.42" + wire width 8 \builder_csrbank7_dma_length0_r + attribute \src "ls180.v:2288.6-2288.37" + wire \builder_csrbank7_dma_length0_re + attribute \src "ls180.v:2291.12-2291.42" + wire width 8 \builder_csrbank7_dma_length0_w + attribute \src "ls180.v:2290.6-2290.37" + wire \builder_csrbank7_dma_length0_we + attribute \src "ls180.v:2285.12-2285.42" + wire width 8 \builder_csrbank7_dma_length1_r + attribute \src "ls180.v:2284.6-2284.37" + wire \builder_csrbank7_dma_length1_re + attribute \src "ls180.v:2287.12-2287.42" + wire width 8 \builder_csrbank7_dma_length1_w + attribute \src "ls180.v:2286.6-2286.37" + wire \builder_csrbank7_dma_length1_we + attribute \src "ls180.v:2281.12-2281.42" + wire width 8 \builder_csrbank7_dma_length2_r + attribute \src "ls180.v:2280.6-2280.37" + wire \builder_csrbank7_dma_length2_re + attribute \src "ls180.v:2283.12-2283.42" + wire width 8 \builder_csrbank7_dma_length2_w + attribute \src "ls180.v:2282.6-2282.37" + wire \builder_csrbank7_dma_length2_we + attribute \src "ls180.v:2277.12-2277.42" + wire width 8 \builder_csrbank7_dma_length3_r + attribute \src "ls180.v:2276.6-2276.37" + wire \builder_csrbank7_dma_length3_re + attribute \src "ls180.v:2279.12-2279.42" + wire width 8 \builder_csrbank7_dma_length3_w + attribute \src "ls180.v:2278.6-2278.37" + wire \builder_csrbank7_dma_length3_we + attribute \src "ls180.v:2301.6-2301.34" + wire \builder_csrbank7_dma_loop0_r + attribute \src "ls180.v:2300.6-2300.35" + wire \builder_csrbank7_dma_loop0_re + attribute \src "ls180.v:2303.6-2303.34" + wire \builder_csrbank7_dma_loop0_w + attribute \src "ls180.v:2302.6-2302.35" + wire \builder_csrbank7_dma_loop0_we + attribute \src "ls180.v:2317.12-2317.42" + wire width 8 \builder_csrbank7_dma_offset0_r + attribute \src "ls180.v:2316.6-2316.37" + wire \builder_csrbank7_dma_offset0_re + attribute \src "ls180.v:2319.12-2319.42" + wire width 8 \builder_csrbank7_dma_offset0_w + attribute \src "ls180.v:2318.6-2318.37" + wire \builder_csrbank7_dma_offset0_we + attribute \src "ls180.v:2313.12-2313.42" + wire width 8 \builder_csrbank7_dma_offset1_r + attribute \src "ls180.v:2312.6-2312.37" + wire \builder_csrbank7_dma_offset1_re + attribute \src "ls180.v:2315.12-2315.42" + wire width 8 \builder_csrbank7_dma_offset1_w + attribute \src "ls180.v:2314.6-2314.37" + wire \builder_csrbank7_dma_offset1_we + attribute \src "ls180.v:2309.12-2309.42" + wire width 8 \builder_csrbank7_dma_offset2_r + attribute \src "ls180.v:2308.6-2308.37" + wire \builder_csrbank7_dma_offset2_re + attribute \src "ls180.v:2311.12-2311.42" + wire width 8 \builder_csrbank7_dma_offset2_w + attribute \src "ls180.v:2310.6-2310.37" + wire \builder_csrbank7_dma_offset2_we + attribute \src "ls180.v:2305.12-2305.42" + wire width 8 \builder_csrbank7_dma_offset3_r + attribute \src "ls180.v:2304.6-2304.37" + wire \builder_csrbank7_dma_offset3_re + attribute \src "ls180.v:2307.12-2307.42" + wire width 8 \builder_csrbank7_dma_offset3_w + attribute \src "ls180.v:2306.6-2306.37" + wire \builder_csrbank7_dma_offset3_we + attribute \src "ls180.v:2320.6-2320.26" + wire \builder_csrbank7_sel + attribute \src "ls180.v:2326.6-2326.36" + wire \builder_csrbank8_card_detect_r + attribute \src "ls180.v:2325.6-2325.37" + wire \builder_csrbank8_card_detect_re + attribute \src "ls180.v:2328.6-2328.36" + wire \builder_csrbank8_card_detect_w + attribute \src "ls180.v:2327.6-2327.37" + wire \builder_csrbank8_card_detect_we + attribute \src "ls180.v:2334.12-2334.47" + wire width 8 \builder_csrbank8_clocker_divider0_r + attribute \src "ls180.v:2333.6-2333.42" + wire \builder_csrbank8_clocker_divider0_re + attribute \src "ls180.v:2336.12-2336.47" + wire width 8 \builder_csrbank8_clocker_divider0_w + attribute \src "ls180.v:2335.6-2335.42" + wire \builder_csrbank8_clocker_divider0_we + attribute \src "ls180.v:2330.6-2330.41" + wire \builder_csrbank8_clocker_divider1_r + attribute \src "ls180.v:2329.6-2329.42" + wire \builder_csrbank8_clocker_divider1_re + attribute \src "ls180.v:2332.6-2332.41" + wire \builder_csrbank8_clocker_divider1_w + attribute \src "ls180.v:2331.6-2331.42" + wire \builder_csrbank8_clocker_divider1_we + attribute \src "ls180.v:2337.6-2337.26" + wire \builder_csrbank8_sel + attribute \src "ls180.v:2343.12-2343.44" + wire width 4 \builder_csrbank9_dfii_control0_r + attribute \src "ls180.v:2342.6-2342.39" + wire \builder_csrbank9_dfii_control0_re + attribute \src "ls180.v:2345.12-2345.44" + wire width 4 \builder_csrbank9_dfii_control0_w + attribute \src "ls180.v:2344.6-2344.39" + wire \builder_csrbank9_dfii_control0_we + attribute \src "ls180.v:2355.12-2355.48" + wire width 8 \builder_csrbank9_dfii_pi0_address0_r + attribute \src "ls180.v:2354.6-2354.43" + wire \builder_csrbank9_dfii_pi0_address0_re + attribute \src "ls180.v:2357.12-2357.48" + wire width 8 \builder_csrbank9_dfii_pi0_address0_w + attribute \src "ls180.v:2356.6-2356.43" + wire \builder_csrbank9_dfii_pi0_address0_we + attribute \src "ls180.v:2351.12-2351.48" + wire width 5 \builder_csrbank9_dfii_pi0_address1_r + attribute \src "ls180.v:2350.6-2350.43" + wire \builder_csrbank9_dfii_pi0_address1_re + attribute \src "ls180.v:2353.12-2353.48" + wire width 5 \builder_csrbank9_dfii_pi0_address1_w + attribute \src "ls180.v:2352.6-2352.43" + wire \builder_csrbank9_dfii_pi0_address1_we + attribute \src "ls180.v:2359.12-2359.49" + wire width 2 \builder_csrbank9_dfii_pi0_baddress0_r + attribute \src "ls180.v:2358.6-2358.44" + wire \builder_csrbank9_dfii_pi0_baddress0_re + attribute \src "ls180.v:2361.12-2361.49" + wire width 2 \builder_csrbank9_dfii_pi0_baddress0_w + attribute \src "ls180.v:2360.6-2360.44" + wire \builder_csrbank9_dfii_pi0_baddress0_we + attribute \src "ls180.v:2347.12-2347.48" + wire width 6 \builder_csrbank9_dfii_pi0_command0_r + attribute \src "ls180.v:2346.6-2346.43" + wire \builder_csrbank9_dfii_pi0_command0_re + attribute \src "ls180.v:2349.12-2349.48" + wire width 6 \builder_csrbank9_dfii_pi0_command0_w + attribute \src "ls180.v:2348.6-2348.43" + wire \builder_csrbank9_dfii_pi0_command0_we + attribute \src "ls180.v:2375.12-2375.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata0_r + attribute \src "ls180.v:2374.6-2374.42" + wire \builder_csrbank9_dfii_pi0_rddata0_re + attribute \src "ls180.v:2377.12-2377.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata0_w + attribute \src "ls180.v:2376.6-2376.42" + wire \builder_csrbank9_dfii_pi0_rddata0_we + attribute \src "ls180.v:2371.12-2371.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata1_r + attribute \src "ls180.v:2370.6-2370.42" + wire \builder_csrbank9_dfii_pi0_rddata1_re + attribute \src "ls180.v:2373.12-2373.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata1_w + attribute \src "ls180.v:2372.6-2372.42" + wire \builder_csrbank9_dfii_pi0_rddata1_we + attribute \src "ls180.v:2367.12-2367.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_r + attribute \src "ls180.v:2366.6-2366.42" + wire \builder_csrbank9_dfii_pi0_wrdata0_re + attribute \src "ls180.v:2369.12-2369.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_w + attribute \src "ls180.v:2368.6-2368.42" + wire \builder_csrbank9_dfii_pi0_wrdata0_we + attribute \src "ls180.v:2363.12-2363.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_r + attribute \src "ls180.v:2362.6-2362.42" + wire \builder_csrbank9_dfii_pi0_wrdata1_re + attribute \src "ls180.v:2365.12-2365.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_w + attribute \src "ls180.v:2364.6-2364.42" + wire \builder_csrbank9_dfii_pi0_wrdata1_we + attribute \src "ls180.v:2378.6-2378.26" + wire \builder_csrbank9_sel + attribute \src "ls180.v:1875.6-1875.18" + wire \builder_done + attribute \src "ls180.v:1873.5-1873.18" + wire \builder_error + attribute \src "ls180.v:1870.11-1870.24" + wire width 3 \builder_grant + attribute \src "ls180.v:1877.13-1877.44" + wire width 14 \builder_interface0_bank_bus_adr + attribute \src "ls180.v:1880.11-1880.44" + wire width 8 \builder_interface0_bank_bus_dat_r + attribute \src "ls180.v:1879.12-1879.45" + wire width 8 \builder_interface0_bank_bus_dat_w + attribute \src "ls180.v:1878.6-1878.36" + wire \builder_interface0_bank_bus_we + attribute \src "ls180.v:2379.13-2379.45" + wire width 14 \builder_interface10_bank_bus_adr + attribute \src "ls180.v:2382.11-2382.45" + wire width 8 \builder_interface10_bank_bus_dat_r + attribute \src "ls180.v:2381.12-2381.46" + wire width 8 \builder_interface10_bank_bus_dat_w + attribute \src "ls180.v:2380.6-2380.37" + wire \builder_interface10_bank_bus_we + attribute \src "ls180.v:2412.13-2412.45" + wire width 14 \builder_interface11_bank_bus_adr + attribute \src "ls180.v:2415.11-2415.45" + wire width 8 \builder_interface11_bank_bus_dat_r + attribute \src "ls180.v:2414.12-2414.46" + wire width 8 \builder_interface11_bank_bus_dat_w + attribute \src "ls180.v:2413.6-2413.37" + wire \builder_interface11_bank_bus_we + attribute \src "ls180.v:2453.13-2453.45" + wire width 14 \builder_interface12_bank_bus_adr + attribute \src "ls180.v:2456.11-2456.45" + wire width 8 \builder_interface12_bank_bus_dat_r + attribute \src "ls180.v:2455.12-2455.46" + wire width 8 \builder_interface12_bank_bus_dat_w + attribute \src "ls180.v:2454.6-2454.37" + wire \builder_interface12_bank_bus_we + attribute \src "ls180.v:2518.13-2518.45" + wire width 14 \builder_interface13_bank_bus_adr + attribute \src "ls180.v:2521.11-2521.45" + wire width 8 \builder_interface13_bank_bus_dat_r + attribute \src "ls180.v:2520.12-2520.46" + wire width 8 \builder_interface13_bank_bus_dat_w + attribute \src "ls180.v:2519.6-2519.37" + wire \builder_interface13_bank_bus_we + attribute \src "ls180.v:2543.13-2543.45" + wire width 14 \builder_interface14_bank_bus_adr + attribute \src "ls180.v:2546.11-2546.45" + wire width 8 \builder_interface14_bank_bus_dat_r + attribute \src "ls180.v:2545.12-2545.46" + wire width 8 \builder_interface14_bank_bus_dat_w + attribute \src "ls180.v:2544.6-2544.37" + wire \builder_interface14_bank_bus_we + attribute \src "ls180.v:1918.13-1918.44" + wire width 14 \builder_interface1_bank_bus_adr + attribute \src "ls180.v:1921.11-1921.44" + wire width 8 \builder_interface1_bank_bus_dat_r + attribute \src "ls180.v:1920.12-1920.45" + wire width 8 \builder_interface1_bank_bus_dat_w + attribute \src "ls180.v:1919.6-1919.36" + wire \builder_interface1_bank_bus_we + attribute \src "ls180.v:1947.13-1947.44" + wire width 14 \builder_interface2_bank_bus_adr + attribute \src "ls180.v:1950.11-1950.44" + wire width 8 \builder_interface2_bank_bus_dat_r + attribute \src "ls180.v:1949.12-1949.45" + wire width 8 \builder_interface2_bank_bus_dat_w + attribute \src "ls180.v:1948.6-1948.36" + wire \builder_interface2_bank_bus_we + attribute \src "ls180.v:1960.13-1960.44" + wire width 14 \builder_interface3_bank_bus_adr + attribute \src "ls180.v:1963.11-1963.44" + wire width 8 \builder_interface3_bank_bus_dat_r + attribute \src "ls180.v:1962.12-1962.45" + wire width 8 \builder_interface3_bank_bus_dat_w + attribute \src "ls180.v:1961.6-1961.36" + wire \builder_interface3_bank_bus_we + attribute \src "ls180.v:2001.13-2001.44" + wire width 14 \builder_interface4_bank_bus_adr + attribute \src "ls180.v:2004.11-2004.44" + wire width 8 \builder_interface4_bank_bus_dat_r + attribute \src "ls180.v:2003.12-2003.45" + wire width 8 \builder_interface4_bank_bus_dat_w + attribute \src "ls180.v:2002.6-2002.36" + wire \builder_interface4_bank_bus_we + attribute \src "ls180.v:2042.13-2042.44" + wire width 14 \builder_interface5_bank_bus_adr + attribute \src "ls180.v:2045.11-2045.44" + wire width 8 \builder_interface5_bank_bus_dat_r + attribute \src "ls180.v:2044.12-2044.45" + wire width 8 \builder_interface5_bank_bus_dat_w + attribute \src "ls180.v:2043.6-2043.36" + wire \builder_interface5_bank_bus_we + attribute \src "ls180.v:2107.13-2107.44" + wire width 14 \builder_interface6_bank_bus_adr + attribute \src "ls180.v:2110.11-2110.44" + wire width 8 \builder_interface6_bank_bus_dat_r + attribute \src "ls180.v:2109.12-2109.45" + wire width 8 \builder_interface6_bank_bus_dat_w + attribute \src "ls180.v:2108.6-2108.36" + wire \builder_interface6_bank_bus_we + attribute \src "ls180.v:2240.13-2240.44" + wire width 14 \builder_interface7_bank_bus_adr + attribute \src "ls180.v:2243.11-2243.44" + wire width 8 \builder_interface7_bank_bus_dat_r + attribute \src "ls180.v:2242.12-2242.45" + wire width 8 \builder_interface7_bank_bus_dat_w + attribute \src "ls180.v:2241.6-2241.36" + wire \builder_interface7_bank_bus_we + attribute \src "ls180.v:2321.13-2321.44" + wire width 14 \builder_interface8_bank_bus_adr + attribute \src "ls180.v:2324.11-2324.44" + wire width 8 \builder_interface8_bank_bus_dat_r + attribute \src "ls180.v:2323.12-2323.45" + wire width 8 \builder_interface8_bank_bus_dat_w + attribute \src "ls180.v:2322.6-2322.36" + wire \builder_interface8_bank_bus_we + attribute \src "ls180.v:2338.13-2338.44" + wire width 14 \builder_interface9_bank_bus_adr + attribute \src "ls180.v:2341.11-2341.44" + wire width 8 \builder_interface9_bank_bus_dat_r + attribute \src "ls180.v:2340.12-2340.45" + wire width 8 \builder_interface9_bank_bus_dat_w + attribute \src "ls180.v:2339.6-2339.36" + wire \builder_interface9_bank_bus_we + attribute \src "ls180.v:1843.12-1843.35" + wire width 14 \builder_libresocsim_adr + attribute \src "ls180.v:2572.12-2572.47" + wire width 14 \builder_libresocsim_adr_next_value1 + attribute \src "ls180.v:2573.5-2573.43" + wire \builder_libresocsim_adr_next_value_ce1 + attribute \src "ls180.v:1846.12-1846.37" + wire width 8 \builder_libresocsim_dat_r + attribute \src "ls180.v:1845.11-1845.36" + wire width 8 \builder_libresocsim_dat_w + attribute \src "ls180.v:2570.11-2570.48" + wire width 8 \builder_libresocsim_dat_w_next_value0 + attribute \src "ls180.v:2571.5-2571.45" + wire \builder_libresocsim_dat_w_next_value_ce0 + attribute \src "ls180.v:1844.5-1844.27" + wire \builder_libresocsim_we + attribute \src "ls180.v:2574.5-2574.39" + wire \builder_libresocsim_we_next_value2 + attribute \src "ls180.v:2575.5-2575.42" + wire \builder_libresocsim_we_next_value_ce2 + attribute \src "ls180.v:1853.5-1853.37" + wire \builder_libresocsim_wishbone_ack + attribute \src "ls180.v:1847.13-1847.45" + wire width 30 \builder_libresocsim_wishbone_adr + attribute \src "ls180.v:1856.12-1856.44" + wire width 2 \builder_libresocsim_wishbone_bte + attribute \src "ls180.v:1855.12-1855.44" + wire width 3 \builder_libresocsim_wishbone_cti + attribute \src "ls180.v:1851.6-1851.38" + wire \builder_libresocsim_wishbone_cyc + attribute \src "ls180.v:1849.12-1849.46" + wire width 32 \builder_libresocsim_wishbone_dat_r + attribute \src "ls180.v:1848.13-1848.47" + wire width 32 \builder_libresocsim_wishbone_dat_w + attribute \src "ls180.v:1857.5-1857.37" + wire \builder_libresocsim_wishbone_err + attribute \src "ls180.v:1850.12-1850.44" + wire width 4 \builder_libresocsim_wishbone_sel + attribute \src "ls180.v:1852.6-1852.38" + wire \builder_libresocsim_wishbone_stb + attribute \src "ls180.v:1854.6-1854.37" + wire \builder_libresocsim_wishbone_we + attribute \src "ls180.v:1746.5-1746.20" + wire \builder_locked0 + attribute \src "ls180.v:1747.5-1747.20" + wire \builder_locked1 + attribute \src "ls180.v:1748.5-1748.20" + wire \builder_locked2 + attribute \src "ls180.v:1749.5-1749.20" + wire \builder_locked3 + attribute \src "ls180.v:1733.11-1733.41" + wire width 3 \builder_multiplexer_next_state + attribute \src "ls180.v:1732.11-1732.36" + wire width 3 \builder_multiplexer_state + attribute \no_retiming "true" + attribute \src "ls180.v:2679.32-2679.59" + wire \builder_multiregimpl0_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2680.32-2680.59" + wire \builder_multiregimpl0_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2699.32-2699.60" + wire \builder_multiregimpl10_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2700.32-2700.60" + wire \builder_multiregimpl10_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2701.32-2701.60" + wire \builder_multiregimpl11_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2702.32-2702.60" + wire \builder_multiregimpl11_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2703.32-2703.60" + wire \builder_multiregimpl12_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2704.32-2704.60" + wire \builder_multiregimpl12_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2705.32-2705.60" + wire \builder_multiregimpl13_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2706.32-2706.60" + wire \builder_multiregimpl13_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2707.32-2707.60" + wire \builder_multiregimpl14_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2708.32-2708.60" + wire \builder_multiregimpl14_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2709.32-2709.60" + wire \builder_multiregimpl15_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2710.32-2710.60" + wire \builder_multiregimpl15_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2711.32-2711.60" + wire \builder_multiregimpl16_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2712.32-2712.60" + wire \builder_multiregimpl16_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2681.32-2681.59" + wire \builder_multiregimpl1_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2682.32-2682.59" + wire \builder_multiregimpl1_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2683.32-2683.59" + wire \builder_multiregimpl2_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2684.32-2684.59" + wire \builder_multiregimpl2_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2685.32-2685.59" + wire \builder_multiregimpl3_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2686.32-2686.59" + wire \builder_multiregimpl3_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2687.32-2687.59" + wire \builder_multiregimpl4_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2688.32-2688.59" + wire \builder_multiregimpl4_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2689.32-2689.59" + wire \builder_multiregimpl5_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2690.32-2690.59" + wire \builder_multiregimpl5_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2691.32-2691.59" + wire \builder_multiregimpl6_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2692.32-2692.59" + wire \builder_multiregimpl6_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2693.32-2693.59" + wire \builder_multiregimpl7_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2694.32-2694.59" + wire \builder_multiregimpl7_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2695.32-2695.59" + wire \builder_multiregimpl8_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2696.32-2696.59" + wire \builder_multiregimpl8_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2697.32-2697.59" + wire \builder_multiregimpl9_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2698.32-2698.59" + wire \builder_multiregimpl9_regs1 + attribute \src "ls180.v:1751.5-1751.36" + wire \builder_new_master_rdata_valid0 + attribute \src "ls180.v:1752.5-1752.36" + wire \builder_new_master_rdata_valid1 + attribute \src "ls180.v:1753.5-1753.36" + wire \builder_new_master_rdata_valid2 + attribute \src "ls180.v:1754.5-1754.36" + wire \builder_new_master_rdata_valid3 + attribute \src "ls180.v:1750.5-1750.35" + wire \builder_new_master_wdata_ready + attribute \src "ls180.v:2569.11-2569.29" + wire width 2 \builder_next_state + attribute \src "ls180.v:1723.11-1723.39" + wire width 2 \builder_refresher_next_state + attribute \src "ls180.v:1722.11-1722.34" + wire width 2 \builder_refresher_state + attribute \src "ls180.v:1869.12-1869.27" + wire width 5 \builder_request + attribute \src "ls180.v:1736.6-1736.28" + wire \builder_roundrobin0_ce + attribute \src "ls180.v:1735.6-1735.31" + wire \builder_roundrobin0_grant + attribute \src "ls180.v:1734.6-1734.33" + wire \builder_roundrobin0_request + attribute \src "ls180.v:1739.6-1739.28" + wire \builder_roundrobin1_ce + attribute \src "ls180.v:1738.6-1738.31" + wire \builder_roundrobin1_grant + attribute \src "ls180.v:1737.6-1737.33" + wire \builder_roundrobin1_request + attribute \src "ls180.v:1742.6-1742.28" + wire \builder_roundrobin2_ce + attribute \src "ls180.v:1741.6-1741.31" + wire \builder_roundrobin2_grant + attribute \src "ls180.v:1740.6-1740.33" + wire \builder_roundrobin2_request + attribute \src "ls180.v:1745.6-1745.28" + wire \builder_roundrobin3_ce + attribute \src "ls180.v:1744.6-1744.31" + wire \builder_roundrobin3_grant + attribute \src "ls180.v:1743.6-1743.33" + wire \builder_roundrobin3_request + attribute \src "ls180.v:1828.11-1828.44" + wire width 2 \builder_sdblock2memdma_next_state + attribute \src "ls180.v:1827.11-1827.39" + wire width 2 \builder_sdblock2memdma_state + attribute \src "ls180.v:1796.5-1796.50" + wire \builder_sdcore_crcupstreaminserter_next_state + attribute \src "ls180.v:1795.5-1795.45" + wire \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:1808.11-1808.40" + wire width 3 \builder_sdcore_fsm_next_state + attribute \src "ls180.v:1807.11-1807.35" + wire width 3 \builder_sdcore_fsm_state + attribute \src "ls180.v:1832.5-1832.42" + wire \builder_sdmem2blockdma_fsm_next_state + attribute \src "ls180.v:1831.5-1831.37" + wire \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:1836.11-1836.58" + wire width 2 \builder_sdmem2blockdma_resetinserter_next_state + attribute \src "ls180.v:1835.11-1835.53" + wire width 2 \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:1784.11-1784.39" + wire width 3 \builder_sdphy_fsm_next_state + attribute \src "ls180.v:1783.11-1783.34" + wire width 3 \builder_sdphy_fsm_state + attribute \src "ls180.v:1772.11-1772.45" + wire width 3 \builder_sdphy_sdphycmdr_next_state + attribute \src "ls180.v:1771.11-1771.40" + wire width 3 \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:1768.11-1768.45" + wire width 2 \builder_sdphy_sdphycmdw_next_state + attribute \src "ls180.v:1767.11-1767.40" + wire width 2 \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:1780.5-1780.39" + wire \builder_sdphy_sdphycrcr_next_state + attribute \src "ls180.v:1779.5-1779.34" + wire \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:1788.11-1788.46" + wire width 3 \builder_sdphy_sdphydatar_next_state + attribute \src "ls180.v:1787.11-1787.41" + wire width 3 \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:1764.5-1764.39" + wire \builder_sdphy_sdphyinit_next_state + attribute \src "ls180.v:1763.5-1763.34" + wire \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:1864.5-1864.23" + wire \builder_shared_ack + attribute \src "ls180.v:1858.13-1858.31" + wire width 30 \builder_shared_adr + attribute \src "ls180.v:1867.12-1867.30" + wire width 2 \builder_shared_bte + attribute \src "ls180.v:1866.12-1866.30" + wire width 3 \builder_shared_cti + attribute \src "ls180.v:1862.6-1862.24" + wire \builder_shared_cyc + attribute \src "ls180.v:1860.12-1860.32" + wire width 32 \builder_shared_dat_r + attribute \src "ls180.v:1859.13-1859.33" + wire width 32 \builder_shared_dat_w + attribute \src "ls180.v:1868.6-1868.24" + wire \builder_shared_err + attribute \src "ls180.v:1861.12-1861.30" + wire width 4 \builder_shared_sel + attribute \src "ls180.v:1863.6-1863.24" + wire \builder_shared_stb + attribute \src "ls180.v:1865.6-1865.23" + wire \builder_shared_we + attribute \src "ls180.v:1871.11-1871.28" + wire width 5 \builder_slave_sel + attribute \src "ls180.v:1872.11-1872.30" + wire width 5 \builder_slave_sel_r + attribute \src "ls180.v:1760.11-1760.40" + wire width 2 \builder_spimaster0_next_state + attribute \src "ls180.v:1759.11-1759.35" + wire width 2 \builder_spimaster0_state + attribute \src "ls180.v:1840.11-1840.40" + wire width 2 \builder_spimaster1_next_state + attribute \src "ls180.v:1839.11-1839.35" + wire width 2 \builder_spimaster1_state + attribute \src "ls180.v:2568.11-2568.24" + wire width 2 \builder_state + attribute \src "ls180.v:2621.5-2621.32" + wire \builder_sync_f_array_muxed0 + attribute \src "ls180.v:2622.5-2622.32" + wire \builder_sync_f_array_muxed1 + attribute \src "ls180.v:2614.11-2614.40" + wire width 2 \builder_sync_rhs_array_muxed0 + attribute \src "ls180.v:2615.12-2615.41" + wire width 13 \builder_sync_rhs_array_muxed1 + attribute \src "ls180.v:2616.5-2616.34" + wire \builder_sync_rhs_array_muxed2 + attribute \src "ls180.v:2617.5-2617.34" + wire \builder_sync_rhs_array_muxed3 + attribute \src "ls180.v:2618.5-2618.34" + wire \builder_sync_rhs_array_muxed4 + attribute \src "ls180.v:2619.5-2619.34" + wire \builder_sync_rhs_array_muxed5 + attribute \src "ls180.v:2620.5-2620.34" + wire \builder_sync_rhs_array_muxed6 + attribute \src "ls180.v:1874.6-1874.18" + wire \builder_wait + attribute \src "ls180.v:30.19-30.23" + wire width 3 input 26 \eint + attribute \src "ls180.v:23.20-23.26" + wire width 16 input 19 \gpio_i + attribute \src "ls180.v:24.21-24.27" + wire width 16 output 20 \gpio_o + attribute \src "ls180.v:25.21-25.28" + wire width 16 output 21 \gpio_oe + attribute \src "ls180.v:38.14-38.21" + wire output 34 \i2c_scl + attribute \src "ls180.v:39.13-39.22" + wire input 35 \i2c_sda_i + attribute \src "ls180.v:40.14-40.23" + wire output 36 \i2c_sda_o + attribute \src "ls180.v:41.14-41.24" + wire output 37 \i2c_sda_oe + attribute \src "ls180.v:32.13-32.21" + wire input 28 \jtag_tck + attribute \src "ls180.v:33.13-33.21" + wire input 29 \jtag_tdi + attribute \src "ls180.v:34.14-34.22" + wire output 30 \jtag_tdo + attribute \src "ls180.v:31.13-31.21" + wire input 27 \jtag_tms + attribute \src "ls180.v:1680.13-1680.37" + wire width 16 \libresocsim_clk_divider0 + attribute \src "ls180.v:1702.12-1702.36" + wire width 16 \libresocsim_clk_divider1 + attribute \src "ls180.v:1697.5-1697.27" + wire \libresocsim_clk_enable + attribute \src "ls180.v:1704.6-1704.26" + wire \libresocsim_clk_fall + attribute \src "ls180.v:1703.6-1703.26" + wire \libresocsim_clk_rise + attribute \src "ls180.v:1684.5-1684.27" + wire \libresocsim_control_re + attribute \src "ls180.v:1683.12-1683.39" + wire width 16 \libresocsim_control_storage + attribute \src "ls180.v:1699.11-1699.28" + wire width 3 \libresocsim_count + attribute \src "ls180.v:1841.11-1841.50" + wire width 3 \libresocsim_count_spimaster1_next_value + attribute \src "ls180.v:1842.5-1842.47" + wire \libresocsim_count_spimaster1_next_value_ce + attribute \src "ls180.v:1678.6-1678.20" + wire \libresocsim_cs + attribute \src "ls180.v:1698.5-1698.26" + wire \libresocsim_cs_enable + attribute \src "ls180.v:1694.5-1694.22" + wire \libresocsim_cs_re + attribute \src "ls180.v:1693.5-1693.27" + wire \libresocsim_cs_storage + attribute \src "ls180.v:1674.5-1674.22" + wire \libresocsim_done0 + attribute \src "ls180.v:1685.6-1685.23" + wire \libresocsim_done1 + attribute \src "ls180.v:1675.5-1675.20" + wire \libresocsim_irq + attribute \src "ls180.v:1673.12-1673.31" + wire width 8 \libresocsim_length0 + attribute \src "ls180.v:1682.12-1682.31" + wire width 8 \libresocsim_length1 + attribute \src "ls180.v:1679.6-1679.26" + wire \libresocsim_loopback + attribute \src "ls180.v:1696.5-1696.28" + wire \libresocsim_loopback_re + attribute \src "ls180.v:1695.5-1695.33" + wire \libresocsim_loopback_storage + attribute \src "ls180.v:1677.11-1677.27" + wire width 8 \libresocsim_miso + attribute \src "ls180.v:1707.11-1707.32" + wire width 8 \libresocsim_miso_data + attribute \src "ls180.v:1701.5-1701.27" + wire \libresocsim_miso_latch + attribute \src "ls180.v:1690.12-1690.35" + wire width 8 \libresocsim_miso_status + attribute \src "ls180.v:1691.6-1691.25" + wire \libresocsim_miso_we + attribute \src "ls180.v:1676.12-1676.28" + wire width 8 \libresocsim_mosi + attribute \src "ls180.v:1705.11-1705.32" + wire width 8 \libresocsim_mosi_data + attribute \src "ls180.v:1700.5-1700.27" + wire \libresocsim_mosi_latch + attribute \src "ls180.v:1689.5-1689.24" + wire \libresocsim_mosi_re + attribute \src "ls180.v:1706.11-1706.31" + wire width 3 \libresocsim_mosi_sel + attribute \src "ls180.v:1688.11-1688.35" + wire width 8 \libresocsim_mosi_storage + attribute \src "ls180.v:1709.5-1709.19" + wire \libresocsim_re + attribute \src "ls180.v:1692.6-1692.21" + wire \libresocsim_sel + attribute \src "ls180.v:1672.6-1672.24" + wire \libresocsim_start0 + attribute \src "ls180.v:1681.5-1681.23" + wire \libresocsim_start1 + attribute \src "ls180.v:1686.6-1686.31" + wire \libresocsim_status_status + attribute \src "ls180.v:1687.6-1687.27" + wire \libresocsim_status_we + attribute \src "ls180.v:1708.12-1708.31" + wire width 16 \libresocsim_storage + attribute \src "ls180.v:814.6-814.18" + wire \main_ack_cmd + attribute \src "ls180.v:816.6-816.20" + wire \main_ack_rdata + attribute \src "ls180.v:815.6-815.20" + wire \main_ack_wdata + attribute \src "ls180.v:812.5-812.22" + wire \main_cmd_consumed + attribute \src "ls180.v:809.5-809.27" + wire \main_converter_counter + attribute \src "ls180.v:1757.5-1757.48" + wire \main_converter_counter_converter_next_value + attribute \src "ls180.v:1758.5-1758.51" + wire \main_converter_counter_converter_next_value_ce + attribute \src "ls180.v:811.12-811.32" + wire width 32 \main_converter_dat_r + attribute \src "ls180.v:810.6-810.26" + wire \main_converter_reset + attribute \src "ls180.v:808.5-808.24" + wire \main_converter_skip + attribute \src "ls180.v:238.6-238.23" + wire \main_dfi_p0_act_n + attribute \src "ls180.v:229.13-229.32" + wire width 13 \main_dfi_p0_address + attribute \src "ls180.v:230.12-230.28" + wire width 2 \main_dfi_p0_bank + attribute \src "ls180.v:231.6-231.23" + wire \main_dfi_p0_cas_n + attribute \src "ls180.v:235.6-235.21" + wire \main_dfi_p0_cke + attribute \src "ls180.v:232.6-232.22" + wire \main_dfi_p0_cs_n + attribute \src "ls180.v:236.6-236.21" + wire \main_dfi_p0_odt + attribute \src "ls180.v:233.6-233.23" + wire \main_dfi_p0_ras_n + attribute \src "ls180.v:243.12-243.30" + wire width 16 \main_dfi_p0_rddata + attribute \src "ls180.v:242.6-242.27" + wire \main_dfi_p0_rddata_en + attribute \src "ls180.v:244.5-244.29" + wire \main_dfi_p0_rddata_valid + attribute \src "ls180.v:237.6-237.25" + wire \main_dfi_p0_reset_n + attribute \src "ls180.v:234.6-234.22" + wire \main_dfi_p0_we_n + attribute \src "ls180.v:239.13-239.31" + wire width 16 \main_dfi_p0_wrdata + attribute \src "ls180.v:240.6-240.27" + wire \main_dfi_p0_wrdata_en + attribute \src "ls180.v:241.12-241.35" + wire width 2 \main_dfi_p0_wrdata_mask + attribute \src "ls180.v:1005.12-1005.22" + wire width 36 \main_dummy + attribute \src "ls180.v:960.5-960.20" + wire \main_gpio_oe_re + attribute \src "ls180.v:959.12-959.32" + wire width 16 \main_gpio_oe_storage + attribute \src "ls180.v:964.5-964.21" + wire \main_gpio_out_re + attribute \src "ls180.v:963.12-963.33" + wire width 16 \main_gpio_out_storage + attribute \src "ls180.v:965.13-965.29" + wire width 16 \main_gpio_pads_i + attribute \src "ls180.v:966.13-966.29" + wire width 16 \main_gpio_pads_o + attribute \src "ls180.v:967.13-967.30" + wire width 16 \main_gpio_pads_oe + attribute \src "ls180.v:961.12-961.28" + wire width 16 \main_gpio_status + attribute \src "ls180.v:962.6-962.18" + wire \main_gpio_we + attribute \src "ls180.v:1027.6-1027.17" + wire \main_i2c_oe + attribute \src "ls180.v:1030.5-1030.16" + wire \main_i2c_re + attribute \src "ls180.v:1026.6-1026.18" + wire \main_i2c_scl + attribute \src "ls180.v:1028.6-1028.19" + wire \main_i2c_sda0 + attribute \src "ls180.v:1031.6-1031.19" + wire \main_i2c_sda1 + attribute \src "ls180.v:1032.6-1032.21" + wire \main_i2c_status + attribute \src "ls180.v:1029.11-1029.27" + wire width 3 \main_i2c_storage + attribute \src "ls180.v:1033.6-1033.17" + wire \main_i2c_we + attribute \src "ls180.v:228.5-228.17" + wire \main_int_rst + attribute \src "ls180.v:1493.6-1493.29" + wire \main_interface0_bus_ack + attribute \src "ls180.v:1487.13-1487.36" + wire width 32 \main_interface0_bus_adr + attribute \src "ls180.v:1496.11-1496.34" + wire width 2 \main_interface0_bus_bte + attribute \src "ls180.v:1495.11-1495.34" + wire width 3 \main_interface0_bus_cti + attribute \src "ls180.v:1491.6-1491.29" + wire \main_interface0_bus_cyc + attribute \src "ls180.v:1489.13-1489.38" + wire width 32 \main_interface0_bus_dat_r + attribute \src "ls180.v:1488.13-1488.38" + wire width 32 \main_interface0_bus_dat_w + attribute \src "ls180.v:1497.6-1497.29" + wire \main_interface0_bus_err + attribute \src "ls180.v:1490.12-1490.35" + wire width 4 \main_interface0_bus_sel + attribute \src "ls180.v:1492.6-1492.29" + wire \main_interface0_bus_stb + attribute \src "ls180.v:1494.6-1494.28" + wire \main_interface0_bus_we + attribute \src "ls180.v:1584.6-1584.29" + wire \main_interface1_bus_ack + attribute \src "ls180.v:1578.12-1578.35" + wire width 32 \main_interface1_bus_adr + attribute \src "ls180.v:1587.11-1587.34" + wire width 2 \main_interface1_bus_bte + attribute \src "ls180.v:1586.11-1586.34" + wire width 3 \main_interface1_bus_cti + attribute \src "ls180.v:1582.5-1582.28" + wire \main_interface1_bus_cyc + attribute \src "ls180.v:1580.13-1580.38" + wire width 32 \main_interface1_bus_dat_r + attribute \src "ls180.v:1579.12-1579.37" + wire width 32 \main_interface1_bus_dat_w + attribute \src "ls180.v:1588.6-1588.29" + wire \main_interface1_bus_err + attribute \src "ls180.v:1581.11-1581.34" + wire width 4 \main_interface1_bus_sel + attribute \src "ls180.v:1583.5-1583.28" + wire \main_interface1_bus_stb + attribute \src "ls180.v:1585.5-1585.27" + wire \main_interface1_bus_we + attribute \src "ls180.v:194.12-194.32" + wire width 7 \main_libresocsim_adr + attribute \src "ls180.v:62.6-62.32" + wire \main_libresocsim_bus_error + attribute \src "ls180.v:63.12-63.39" + wire width 32 \main_libresocsim_bus_errors + attribute \src "ls180.v:59.13-59.47" + wire width 32 \main_libresocsim_bus_errors_status + attribute \src "ls180.v:60.6-60.36" + wire \main_libresocsim_bus_errors_we + attribute \src "ls180.v:150.5-150.40" + wire \main_libresocsim_converter0_counter + attribute \src "ls180.v:1712.5-1712.62" + wire \main_libresocsim_converter0_counter_converter0_next_value + attribute \src "ls180.v:1713.5-1713.65" + wire \main_libresocsim_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:152.12-152.45" + wire width 64 \main_libresocsim_converter0_dat_r + attribute \src "ls180.v:151.6-151.39" + wire \main_libresocsim_converter0_reset + attribute \src "ls180.v:149.5-149.37" + wire \main_libresocsim_converter0_skip + attribute \src "ls180.v:165.5-165.40" + wire \main_libresocsim_converter1_counter + attribute \src "ls180.v:1716.5-1716.62" + wire \main_libresocsim_converter1_counter_converter1_next_value + attribute \src "ls180.v:1717.5-1717.65" + wire \main_libresocsim_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:167.12-167.45" + wire width 64 \main_libresocsim_converter1_dat_r + attribute \src "ls180.v:166.6-166.39" + wire \main_libresocsim_converter1_reset + attribute \src "ls180.v:164.5-164.37" + wire \main_libresocsim_converter1_skip + attribute \src "ls180.v:180.5-180.40" + wire \main_libresocsim_converter2_counter + attribute \src "ls180.v:1720.5-1720.62" + wire \main_libresocsim_converter2_counter_converter2_next_value + attribute \src "ls180.v:1721.5-1721.65" + wire \main_libresocsim_converter2_counter_converter2_next_value_ce + attribute \src "ls180.v:182.12-182.45" + wire width 64 \main_libresocsim_converter2_dat_r + attribute \src "ls180.v:181.6-181.39" + wire \main_libresocsim_converter2_reset + attribute \src "ls180.v:179.5-179.37" + wire \main_libresocsim_converter2_skip + attribute \src "ls180.v:195.13-195.35" + wire width 32 \main_libresocsim_dat_r + attribute \src "ls180.v:197.13-197.35" + wire width 32 \main_libresocsim_dat_w + attribute \src "ls180.v:203.5-203.27" + wire \main_libresocsim_en_re + attribute \src "ls180.v:202.5-202.32" + wire \main_libresocsim_en_storage + attribute \src "ls180.v:219.6-219.45" + wire \main_libresocsim_eventmanager_pending_r + attribute \src "ls180.v:218.6-218.46" + wire \main_libresocsim_eventmanager_pending_re + attribute \src "ls180.v:221.6-221.45" + wire \main_libresocsim_eventmanager_pending_w + attribute \src "ls180.v:220.6-220.46" + wire \main_libresocsim_eventmanager_pending_we + attribute \src "ls180.v:223.5-223.37" + wire \main_libresocsim_eventmanager_re + attribute \src "ls180.v:215.6-215.44" + wire \main_libresocsim_eventmanager_status_r + attribute \src "ls180.v:214.6-214.45" + wire \main_libresocsim_eventmanager_status_re + attribute \src "ls180.v:217.6-217.44" + wire \main_libresocsim_eventmanager_status_w + attribute \src "ls180.v:216.6-216.45" + wire \main_libresocsim_eventmanager_status_we + attribute \src "ls180.v:222.5-222.42" + wire \main_libresocsim_eventmanager_storage + attribute \src "ls180.v:144.6-144.57" + wire \main_libresocsim_interface0_converted_interface_ack + attribute \src "ls180.v:138.12-138.63" + wire width 30 \main_libresocsim_interface0_converted_interface_adr + attribute \src "ls180.v:147.11-147.62" + wire width 2 \main_libresocsim_interface0_converted_interface_bte + attribute \src "ls180.v:146.11-146.62" + wire width 3 \main_libresocsim_interface0_converted_interface_cti + attribute \src "ls180.v:142.5-142.56" + wire \main_libresocsim_interface0_converted_interface_cyc + attribute \src "ls180.v:140.13-140.66" + wire width 32 \main_libresocsim_interface0_converted_interface_dat_r + attribute \src "ls180.v:139.12-139.65" + wire width 32 \main_libresocsim_interface0_converted_interface_dat_w + attribute \src "ls180.v:148.6-148.57" + wire \main_libresocsim_interface0_converted_interface_err + attribute \src "ls180.v:141.11-141.62" + wire width 4 \main_libresocsim_interface0_converted_interface_sel + attribute \src "ls180.v:143.5-143.56" + wire \main_libresocsim_interface0_converted_interface_stb + attribute \src "ls180.v:145.5-145.55" + wire \main_libresocsim_interface0_converted_interface_we + attribute \src "ls180.v:159.6-159.57" + wire \main_libresocsim_interface1_converted_interface_ack + attribute \src "ls180.v:153.12-153.63" + wire width 30 \main_libresocsim_interface1_converted_interface_adr + attribute \src "ls180.v:162.11-162.62" + wire width 2 \main_libresocsim_interface1_converted_interface_bte + attribute \src "ls180.v:161.11-161.62" + wire width 3 \main_libresocsim_interface1_converted_interface_cti + attribute \src "ls180.v:157.5-157.56" + wire \main_libresocsim_interface1_converted_interface_cyc + attribute \src "ls180.v:155.13-155.66" + wire width 32 \main_libresocsim_interface1_converted_interface_dat_r + attribute \src "ls180.v:154.12-154.65" + wire width 32 \main_libresocsim_interface1_converted_interface_dat_w + attribute \src "ls180.v:163.6-163.57" + wire \main_libresocsim_interface1_converted_interface_err + attribute \src "ls180.v:156.11-156.62" + wire width 4 \main_libresocsim_interface1_converted_interface_sel + attribute \src "ls180.v:158.5-158.56" + wire \main_libresocsim_interface1_converted_interface_stb + attribute \src "ls180.v:160.5-160.55" + wire \main_libresocsim_interface1_converted_interface_we + attribute \src "ls180.v:174.6-174.57" + wire \main_libresocsim_interface2_converted_interface_ack + attribute \src "ls180.v:168.12-168.63" + wire width 30 \main_libresocsim_interface2_converted_interface_adr + attribute \src "ls180.v:177.11-177.62" + wire width 2 \main_libresocsim_interface2_converted_interface_bte + attribute \src "ls180.v:176.11-176.62" + wire width 3 \main_libresocsim_interface2_converted_interface_cti + attribute \src "ls180.v:172.5-172.56" + wire \main_libresocsim_interface2_converted_interface_cyc + attribute \src "ls180.v:170.13-170.66" + wire width 32 \main_libresocsim_interface2_converted_interface_dat_r + attribute \src "ls180.v:169.12-169.65" + wire width 32 \main_libresocsim_interface2_converted_interface_dat_w + attribute \src "ls180.v:178.6-178.57" + wire \main_libresocsim_interface2_converted_interface_err + attribute \src "ls180.v:171.11-171.62" + wire width 4 \main_libresocsim_interface2_converted_interface_sel + attribute \src "ls180.v:173.5-173.56" + wire \main_libresocsim_interface2_converted_interface_stb + attribute \src "ls180.v:175.5-175.55" + wire \main_libresocsim_interface2_converted_interface_we + attribute \src "ls180.v:208.6-208.26" + wire \main_libresocsim_irq + attribute \src "ls180.v:123.6-123.32" + wire \main_libresocsim_libresoc0 + attribute \src "ls180.v:124.6-124.32" + wire \main_libresocsim_libresoc1 + attribute \src "ls180.v:125.13-125.39" + wire width 64 \main_libresocsim_libresoc2 + attribute \src "ls180.v:127.12-127.45" + wire width 3 \main_libresocsim_libresoc_clk_sel + attribute \src "ls180.v:130.13-130.65" + wire width 16 \main_libresocsim_libresoc_constraintmanager0_gpio0_i + attribute \src "ls180.v:131.13-131.65" + wire width 16 \main_libresocsim_libresoc_constraintmanager0_gpio0_o + attribute \src "ls180.v:132.13-132.66" + wire width 16 \main_libresocsim_libresoc_constraintmanager0_gpio0_oe + attribute \src "ls180.v:129.6-129.59" + wire \main_libresocsim_libresoc_constraintmanager0_uart0_rx + attribute \src "ls180.v:128.5-128.58" + wire \main_libresocsim_libresoc_constraintmanager0_uart0_tx + attribute \src "ls180.v:135.13-135.65" + wire width 16 \main_libresocsim_libresoc_constraintmanager1_gpio0_i + attribute \src "ls180.v:136.13-136.65" + wire width 16 \main_libresocsim_libresoc_constraintmanager1_gpio0_o + attribute \src "ls180.v:137.13-137.66" + wire width 16 \main_libresocsim_libresoc_constraintmanager1_gpio0_oe + attribute \src "ls180.v:134.6-134.59" + wire \main_libresocsim_libresoc_constraintmanager1_uart0_rx + attribute \src "ls180.v:133.6-133.59" + wire \main_libresocsim_libresoc_constraintmanager1_uart0_tx + attribute \src "ls180.v:72.5-72.39" + wire \main_libresocsim_libresoc_dbus_ack + attribute \src "ls180.v:66.13-66.47" + wire width 29 \main_libresocsim_libresoc_dbus_adr + attribute \src "ls180.v:75.12-75.46" + wire width 2 \main_libresocsim_libresoc_dbus_bte + attribute \src "ls180.v:74.12-74.46" + wire width 3 \main_libresocsim_libresoc_dbus_cti + attribute \src "ls180.v:70.6-70.40" + wire \main_libresocsim_libresoc_dbus_cyc + attribute \src "ls180.v:68.13-68.49" + wire width 64 \main_libresocsim_libresoc_dbus_dat_r + attribute \src "ls180.v:67.13-67.49" + wire width 64 \main_libresocsim_libresoc_dbus_dat_w + attribute \src "ls180.v:76.5-76.39" + wire \main_libresocsim_libresoc_dbus_err + attribute \src "ls180.v:69.12-69.46" + wire width 8 \main_libresocsim_libresoc_dbus_sel + attribute \src "ls180.v:71.6-71.40" + wire \main_libresocsim_libresoc_dbus_stb + attribute \src "ls180.v:73.6-73.39" + wire \main_libresocsim_libresoc_dbus_we + attribute \src "ls180.v:83.5-83.39" + wire \main_libresocsim_libresoc_ibus_ack + attribute \src "ls180.v:77.13-77.47" + wire width 29 \main_libresocsim_libresoc_ibus_adr + attribute \src "ls180.v:86.12-86.46" + wire width 2 \main_libresocsim_libresoc_ibus_bte + attribute \src "ls180.v:85.12-85.46" + wire width 3 \main_libresocsim_libresoc_ibus_cti + attribute \src "ls180.v:81.6-81.40" + wire \main_libresocsim_libresoc_ibus_cyc + attribute \src "ls180.v:79.13-79.49" + wire width 64 \main_libresocsim_libresoc_ibus_dat_r + attribute \src "ls180.v:78.13-78.49" + wire width 64 \main_libresocsim_libresoc_ibus_dat_w + attribute \src "ls180.v:87.5-87.39" + wire \main_libresocsim_libresoc_ibus_err + attribute \src "ls180.v:80.12-80.46" + wire width 8 \main_libresocsim_libresoc_ibus_sel + attribute \src "ls180.v:82.6-82.40" + wire \main_libresocsim_libresoc_ibus_stb + attribute \src "ls180.v:84.6-84.39" + wire \main_libresocsim_libresoc_ibus_we + attribute \src "ls180.v:65.12-65.47" + wire width 16 \main_libresocsim_libresoc_interrupt + attribute \src "ls180.v:119.6-119.40" + wire \main_libresocsim_libresoc_jtag_tck + attribute \src "ls180.v:121.6-121.40" + wire \main_libresocsim_libresoc_jtag_tdi + attribute \src "ls180.v:122.6-122.40" + wire \main_libresocsim_libresoc_jtag_tdo + attribute \src "ls180.v:120.6-120.40" + wire \main_libresocsim_libresoc_jtag_tms + attribute \src "ls180.v:116.5-116.42" + wire \main_libresocsim_libresoc_jtag_wb_ack + attribute \src "ls180.v:110.13-110.50" + wire width 29 \main_libresocsim_libresoc_jtag_wb_adr + attribute \src "ls180.v:114.6-114.43" + wire \main_libresocsim_libresoc_jtag_wb_cyc + attribute \src "ls180.v:112.13-112.52" + wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_r + attribute \src "ls180.v:111.13-111.52" + wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_w + attribute \src "ls180.v:118.5-118.42" + wire \main_libresocsim_libresoc_jtag_wb_err + attribute \src "ls180.v:113.12-113.49" + wire width 8 \main_libresocsim_libresoc_jtag_wb_sel + attribute \src "ls180.v:115.6-115.43" + wire \main_libresocsim_libresoc_jtag_wb_stb + attribute \src "ls180.v:117.6-117.42" + wire \main_libresocsim_libresoc_jtag_wb_we + attribute \src "ls180.v:126.6-126.40" + wire \main_libresocsim_libresoc_pll_48_o + attribute \src "ls180.v:64.6-64.37" + wire \main_libresocsim_libresoc_reset + attribute \src "ls180.v:94.6-94.44" + wire \main_libresocsim_libresoc_xics_icp_ack + attribute \src "ls180.v:88.13-88.51" + wire width 30 \main_libresocsim_libresoc_xics_icp_adr + attribute \src "ls180.v:97.12-97.50" + wire width 2 \main_libresocsim_libresoc_xics_icp_bte + attribute \src "ls180.v:96.12-96.50" + wire width 3 \main_libresocsim_libresoc_xics_icp_cti + attribute \src "ls180.v:92.6-92.44" + wire \main_libresocsim_libresoc_xics_icp_cyc + attribute \src "ls180.v:90.13-90.53" + wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r + attribute \src "ls180.v:89.13-89.53" + wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w + attribute \src "ls180.v:98.6-98.44" + wire \main_libresocsim_libresoc_xics_icp_err + attribute \src "ls180.v:91.12-91.50" + wire width 4 \main_libresocsim_libresoc_xics_icp_sel + attribute \src "ls180.v:93.6-93.44" + wire \main_libresocsim_libresoc_xics_icp_stb + attribute \src "ls180.v:95.6-95.43" + wire \main_libresocsim_libresoc_xics_icp_we + attribute \src "ls180.v:105.6-105.44" + wire \main_libresocsim_libresoc_xics_ics_ack + attribute \src "ls180.v:99.13-99.51" + wire width 30 \main_libresocsim_libresoc_xics_ics_adr + attribute \src "ls180.v:108.12-108.50" + wire width 2 \main_libresocsim_libresoc_xics_ics_bte + attribute \src "ls180.v:107.12-107.50" + wire width 3 \main_libresocsim_libresoc_xics_ics_cti + attribute \src "ls180.v:103.6-103.44" + wire \main_libresocsim_libresoc_xics_ics_cyc + attribute \src "ls180.v:101.13-101.53" + wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r + attribute \src "ls180.v:100.13-100.53" + wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w + attribute \src "ls180.v:109.6-109.44" + wire \main_libresocsim_libresoc_xics_ics_err + attribute \src "ls180.v:102.12-102.50" + wire width 4 \main_libresocsim_libresoc_xics_ics_sel + attribute \src "ls180.v:104.6-104.44" + wire \main_libresocsim_libresoc_xics_ics_stb + attribute \src "ls180.v:106.6-106.43" + wire \main_libresocsim_libresoc_xics_ics_we + attribute \src "ls180.v:199.5-199.29" + wire \main_libresocsim_load_re + attribute \src "ls180.v:198.12-198.41" + wire width 32 \main_libresocsim_load_storage + attribute \src "ls180.v:189.5-189.33" + wire \main_libresocsim_ram_bus_ack + attribute \src "ls180.v:183.13-183.41" + wire width 30 \main_libresocsim_ram_bus_adr + attribute \src "ls180.v:192.12-192.40" + wire width 2 \main_libresocsim_ram_bus_bte + attribute \src "ls180.v:191.12-191.40" + wire width 3 \main_libresocsim_ram_bus_cti + attribute \src "ls180.v:187.6-187.34" + wire \main_libresocsim_ram_bus_cyc + attribute \src "ls180.v:185.13-185.43" + wire width 32 \main_libresocsim_ram_bus_dat_r + attribute \src "ls180.v:184.13-184.43" + wire width 32 \main_libresocsim_ram_bus_dat_w + attribute \src "ls180.v:193.5-193.33" + wire \main_libresocsim_ram_bus_err + attribute \src "ls180.v:186.12-186.40" + wire width 4 \main_libresocsim_ram_bus_sel + attribute \src "ls180.v:188.6-188.34" + wire \main_libresocsim_ram_bus_stb + attribute \src "ls180.v:190.6-190.33" + wire \main_libresocsim_ram_bus_we + attribute \src "ls180.v:201.5-201.31" + wire \main_libresocsim_reload_re + attribute \src "ls180.v:200.12-200.43" + wire width 32 \main_libresocsim_reload_storage + attribute \src "ls180.v:61.6-61.28" + wire \main_libresocsim_reset + attribute \src "ls180.v:56.5-56.30" + wire \main_libresocsim_reset_re + attribute \src "ls180.v:55.5-55.35" + wire \main_libresocsim_reset_storage + attribute \src "ls180.v:58.5-58.32" + wire \main_libresocsim_scratch_re + attribute \src "ls180.v:57.12-57.44" + wire width 32 \main_libresocsim_scratch_storage + attribute \src "ls180.v:205.5-205.37" + wire \main_libresocsim_update_value_re + attribute \src "ls180.v:204.5-204.42" + wire \main_libresocsim_update_value_storage + attribute \src "ls180.v:224.12-224.34" + wire width 32 \main_libresocsim_value + attribute \src "ls180.v:206.12-206.41" + wire width 32 \main_libresocsim_value_status + attribute \src "ls180.v:207.6-207.31" + wire \main_libresocsim_value_we + attribute \src "ls180.v:196.11-196.30" + wire width 4 \main_libresocsim_we + attribute \src "ls180.v:212.5-212.32" + wire \main_libresocsim_zero_clear + attribute \src "ls180.v:213.5-213.38" + wire \main_libresocsim_zero_old_trigger + attribute \src "ls180.v:210.5-210.34" + wire \main_libresocsim_zero_pending + attribute \src "ls180.v:209.6-209.34" + wire \main_libresocsim_zero_status + attribute \src "ls180.v:211.6-211.35" + wire \main_libresocsim_zero_trigger + attribute \src "ls180.v:806.6-806.26" + wire \main_litedram_wb_ack + attribute \src "ls180.v:800.12-800.32" + wire width 30 \main_litedram_wb_adr + attribute \src "ls180.v:804.5-804.25" + wire \main_litedram_wb_cyc + attribute \src "ls180.v:802.13-802.35" + wire width 16 \main_litedram_wb_dat_r + attribute \src "ls180.v:801.12-801.34" + wire width 16 \main_litedram_wb_dat_w + attribute \src "ls180.v:803.11-803.31" + wire width 2 \main_litedram_wb_sel + attribute \src "ls180.v:805.5-805.25" + wire \main_litedram_wb_stb + attribute \src "ls180.v:807.5-807.24" + wire \main_litedram_wb_we + attribute \src "ls180.v:1004.13-1004.20" + wire width 36 \main_nc + attribute \src "ls180.v:779.6-779.24" + wire \main_port_cmd_last + attribute \src "ls180.v:781.13-781.39" + wire width 24 \main_port_cmd_payload_addr + attribute \src "ls180.v:780.6-780.30" + wire \main_port_cmd_payload_we + attribute \src "ls180.v:778.6-778.25" + wire \main_port_cmd_ready + attribute \src "ls180.v:777.6-777.25" + wire \main_port_cmd_valid + attribute \src "ls180.v:776.6-776.21" + wire \main_port_flush + attribute \src "ls180.v:788.13-788.41" + wire width 16 \main_port_rdata_payload_data + attribute \src "ls180.v:787.6-787.27" + wire \main_port_rdata_ready + attribute \src "ls180.v:786.6-786.27" + wire \main_port_rdata_valid + attribute \src "ls180.v:784.13-784.41" + wire width 16 \main_port_wdata_payload_data + attribute \src "ls180.v:785.12-785.38" + wire width 2 \main_port_wdata_payload_we + attribute \src "ls180.v:783.6-783.27" + wire \main_port_wdata_ready + attribute \src "ls180.v:782.6-782.27" + wire \main_port_wdata_valid + attribute \src "ls180.v:1009.12-1009.29" + wire width 32 \main_pwm0_counter + attribute \src "ls180.v:1006.6-1006.22" + wire \main_pwm0_enable + attribute \src "ls180.v:1011.5-1011.24" + wire \main_pwm0_enable_re + attribute \src "ls180.v:1010.5-1010.29" + wire \main_pwm0_enable_storage + attribute \src "ls180.v:1008.13-1008.29" + wire width 32 \main_pwm0_period + attribute \src "ls180.v:1015.5-1015.24" + wire \main_pwm0_period_re + attribute \src "ls180.v:1014.12-1014.36" + wire width 32 \main_pwm0_period_storage + attribute \src "ls180.v:1007.13-1007.28" + wire width 32 \main_pwm0_width + attribute \src "ls180.v:1013.5-1013.23" + wire \main_pwm0_width_re + attribute \src "ls180.v:1012.12-1012.35" + wire width 32 \main_pwm0_width_storage + attribute \src "ls180.v:1019.12-1019.29" + wire width 32 \main_pwm1_counter + attribute \src "ls180.v:1016.6-1016.22" + wire \main_pwm1_enable + attribute \src "ls180.v:1021.5-1021.24" + wire \main_pwm1_enable_re + attribute \src "ls180.v:1020.5-1020.29" + wire \main_pwm1_enable_storage + attribute \src "ls180.v:1018.13-1018.29" + wire width 32 \main_pwm1_period + attribute \src "ls180.v:1025.5-1025.24" + wire \main_pwm1_period_re + attribute \src "ls180.v:1024.12-1024.36" + wire width 32 \main_pwm1_period_storage + attribute \src "ls180.v:1017.13-1017.28" + wire width 32 \main_pwm1_width + attribute \src "ls180.v:1023.5-1023.23" + wire \main_pwm1_width_re + attribute \src "ls180.v:1022.12-1022.35" + wire width 32 \main_pwm1_width_storage + attribute \src "ls180.v:245.11-245.25" + wire width 3 \main_rddata_en + attribute \src "ls180.v:1547.11-1547.43" + wire width 2 \main_sdblock2mem_converter_demux + attribute \src "ls180.v:1548.6-1548.42" + wire \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:1538.6-1538.43" + wire \main_sdblock2mem_converter_sink_first + attribute \src "ls180.v:1539.6-1539.42" + wire \main_sdblock2mem_converter_sink_last + attribute \src "ls180.v:1540.12-1540.56" + wire width 8 \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:1537.6-1537.43" + wire \main_sdblock2mem_converter_sink_ready + attribute \src "ls180.v:1536.6-1536.43" + wire \main_sdblock2mem_converter_sink_valid + attribute \src "ls180.v:1543.5-1543.44" + wire \main_sdblock2mem_converter_source_first + attribute \src "ls180.v:1544.5-1544.43" + wire \main_sdblock2mem_converter_source_last + attribute \src "ls180.v:1545.12-1545.58" + wire width 32 \main_sdblock2mem_converter_source_payload_data + attribute \src "ls180.v:1546.11-1546.70" + wire width 3 \main_sdblock2mem_converter_source_payload_valid_token_count + attribute \src "ls180.v:1542.6-1542.45" + wire \main_sdblock2mem_converter_source_ready + attribute \src "ls180.v:1541.6-1541.45" + wire \main_sdblock2mem_converter_source_valid + attribute \src "ls180.v:1549.5-1549.42" + wire \main_sdblock2mem_converter_strobe_all + attribute \src "ls180.v:1522.11-1522.40" + wire width 5 \main_sdblock2mem_fifo_consume + attribute \src "ls180.v:1527.6-1527.35" + wire \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:1531.6-1531.41" + wire \main_sdblock2mem_fifo_fifo_in_first + attribute \src "ls180.v:1532.6-1532.40" + wire \main_sdblock2mem_fifo_fifo_in_last + attribute \src "ls180.v:1530.12-1530.54" + wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data + attribute \src "ls180.v:1534.6-1534.42" + wire \main_sdblock2mem_fifo_fifo_out_first + attribute \src "ls180.v:1535.6-1535.41" + wire \main_sdblock2mem_fifo_fifo_out_last + attribute \src "ls180.v:1533.12-1533.55" + wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data + attribute \src "ls180.v:1519.11-1519.38" + wire width 6 \main_sdblock2mem_fifo_level + attribute \src "ls180.v:1521.11-1521.40" + wire width 5 \main_sdblock2mem_fifo_produce + attribute \src "ls180.v:1528.12-1528.44" + wire width 5 \main_sdblock2mem_fifo_rdport_adr + attribute \src "ls180.v:1529.12-1529.46" + wire width 10 \main_sdblock2mem_fifo_rdport_dat_r + attribute \src "ls180.v:1520.5-1520.34" + wire \main_sdblock2mem_fifo_replace + attribute \src "ls180.v:1505.6-1505.38" + wire \main_sdblock2mem_fifo_sink_first + attribute \src "ls180.v:1506.6-1506.37" + wire \main_sdblock2mem_fifo_sink_last + attribute \src "ls180.v:1507.12-1507.51" + wire width 8 \main_sdblock2mem_fifo_sink_payload_data + attribute \src "ls180.v:1504.6-1504.38" + wire \main_sdblock2mem_fifo_sink_ready + attribute \src "ls180.v:1503.6-1503.38" + wire \main_sdblock2mem_fifo_sink_valid + attribute \src "ls180.v:1510.6-1510.40" + wire \main_sdblock2mem_fifo_source_first + attribute \src "ls180.v:1511.6-1511.39" + wire \main_sdblock2mem_fifo_source_last + attribute \src "ls180.v:1512.12-1512.53" + wire width 8 \main_sdblock2mem_fifo_source_payload_data + attribute \src "ls180.v:1509.6-1509.40" + wire \main_sdblock2mem_fifo_source_ready + attribute \src "ls180.v:1508.6-1508.40" + wire \main_sdblock2mem_fifo_source_valid + attribute \src "ls180.v:1517.12-1517.46" + wire width 10 \main_sdblock2mem_fifo_syncfifo_din + attribute \src "ls180.v:1518.12-1518.47" + wire width 10 \main_sdblock2mem_fifo_syncfifo_dout + attribute \src "ls180.v:1515.6-1515.39" + wire \main_sdblock2mem_fifo_syncfifo_re + attribute \src "ls180.v:1516.6-1516.45" + wire \main_sdblock2mem_fifo_syncfifo_readable + attribute \src "ls180.v:1513.6-1513.39" + wire \main_sdblock2mem_fifo_syncfifo_we + attribute \src "ls180.v:1514.6-1514.45" + wire \main_sdblock2mem_fifo_syncfifo_writable + attribute \src "ls180.v:1523.11-1523.43" + wire width 5 \main_sdblock2mem_fifo_wrport_adr + attribute \src "ls180.v:1524.12-1524.46" + wire width 10 \main_sdblock2mem_fifo_wrport_dat_r + attribute \src "ls180.v:1526.12-1526.46" + wire width 10 \main_sdblock2mem_fifo_wrport_dat_w + attribute \src "ls180.v:1525.6-1525.37" + wire \main_sdblock2mem_fifo_wrport_we + attribute \src "ls180.v:1500.6-1500.38" + wire \main_sdblock2mem_sink_sink_first + attribute \src "ls180.v:1501.6-1501.37" + wire \main_sdblock2mem_sink_sink_last + attribute \src "ls180.v:1557.12-1557.54" + wire width 32 \main_sdblock2mem_sink_sink_payload_address + attribute \src "ls180.v:1502.12-1502.52" + wire width 8 \main_sdblock2mem_sink_sink_payload_data0 + attribute \src "ls180.v:1558.12-1558.52" + wire width 32 \main_sdblock2mem_sink_sink_payload_data1 + attribute \src "ls180.v:1499.6-1499.39" + wire \main_sdblock2mem_sink_sink_ready0 + attribute \src "ls180.v:1556.6-1556.39" + wire \main_sdblock2mem_sink_sink_ready1 + attribute \src "ls180.v:1498.6-1498.39" + wire \main_sdblock2mem_sink_sink_valid0 + attribute \src "ls180.v:1555.5-1555.38" + wire \main_sdblock2mem_sink_sink_valid1 + attribute \src "ls180.v:1552.6-1552.42" + wire \main_sdblock2mem_source_source_first + attribute \src "ls180.v:1553.6-1553.41" + wire \main_sdblock2mem_source_source_last + attribute \src "ls180.v:1554.13-1554.56" + wire width 32 \main_sdblock2mem_source_source_payload_data + attribute \src "ls180.v:1551.6-1551.42" + wire \main_sdblock2mem_source_source_ready + attribute \src "ls180.v:1550.6-1550.42" + wire \main_sdblock2mem_source_source_valid + attribute \src "ls180.v:1574.13-1574.52" + wire width 32 \main_sdblock2mem_wishbonedmawriter_base + attribute \src "ls180.v:1565.5-1565.47" + wire \main_sdblock2mem_wishbonedmawriter_base_re + attribute \src "ls180.v:1564.12-1564.59" + wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage + attribute \src "ls180.v:1569.5-1569.49" + wire \main_sdblock2mem_wishbonedmawriter_enable_re + attribute \src "ls180.v:1568.5-1568.54" + wire \main_sdblock2mem_wishbonedmawriter_enable_storage + attribute \src "ls180.v:1576.13-1576.54" + wire width 32 \main_sdblock2mem_wishbonedmawriter_length + attribute \src "ls180.v:1567.5-1567.49" + wire \main_sdblock2mem_wishbonedmawriter_length_re + attribute \src "ls180.v:1566.12-1566.61" + wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage + attribute \src "ls180.v:1573.5-1573.47" + wire \main_sdblock2mem_wishbonedmawriter_loop_re + attribute \src "ls180.v:1572.5-1572.52" + wire \main_sdblock2mem_wishbonedmawriter_loop_storage + attribute \src "ls180.v:1575.12-1575.53" + wire width 32 \main_sdblock2mem_wishbonedmawriter_offset + attribute \src "ls180.v:1829.12-1829.79" + wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value + attribute \src "ls180.v:1830.5-1830.75" + wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce + attribute \src "ls180.v:1577.6-1577.46" + wire \main_sdblock2mem_wishbonedmawriter_reset + attribute \src "ls180.v:1561.6-1561.51" + wire \main_sdblock2mem_wishbonedmawriter_sink_first + attribute \src "ls180.v:1562.6-1562.50" + wire \main_sdblock2mem_wishbonedmawriter_sink_last + attribute \src "ls180.v:1563.13-1563.65" + wire width 32 \main_sdblock2mem_wishbonedmawriter_sink_payload_data + attribute \src "ls180.v:1560.5-1560.50" + wire \main_sdblock2mem_wishbonedmawriter_sink_ready + attribute \src "ls180.v:1559.6-1559.51" + wire \main_sdblock2mem_wishbonedmawriter_sink_valid + attribute \src "ls180.v:1570.5-1570.46" + wire \main_sdblock2mem_wishbonedmawriter_status + attribute \src "ls180.v:1571.6-1571.43" + wire \main_sdblock2mem_wishbonedmawriter_we + attribute \src "ls180.v:1339.5-1339.31" + wire \main_sdcore_block_count_re + attribute \src "ls180.v:1338.12-1338.43" + wire width 32 \main_sdcore_block_count_storage + attribute \src "ls180.v:1337.5-1337.32" + wire \main_sdcore_block_length_re + attribute \src "ls180.v:1336.11-1336.43" + wire width 10 \main_sdcore_block_length_storage + attribute \src "ls180.v:1323.5-1323.32" + wire \main_sdcore_cmd_argument_re + attribute \src "ls180.v:1322.12-1322.44" + wire width 32 \main_sdcore_cmd_argument_storage + attribute \src "ls180.v:1325.5-1325.31" + wire \main_sdcore_cmd_command_re + attribute \src "ls180.v:1324.12-1324.43" + wire width 32 \main_sdcore_cmd_command_storage + attribute \src "ls180.v:1478.11-1478.32" + wire width 3 \main_sdcore_cmd_count + attribute \src "ls180.v:1813.11-1813.55" + wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2 + attribute \src "ls180.v:1814.5-1814.52" + wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 + attribute \src "ls180.v:1479.5-1479.25" + wire \main_sdcore_cmd_done + attribute \src "ls180.v:1809.5-1809.48" + wire \main_sdcore_cmd_done_sdcore_fsm_next_value0 + attribute \src "ls180.v:1810.5-1810.51" + wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 + attribute \src "ls180.v:1480.5-1480.26" + wire \main_sdcore_cmd_error + attribute \src "ls180.v:1817.5-1817.49" + wire \main_sdcore_cmd_error_sdcore_fsm_next_value4 + attribute \src "ls180.v:1818.5-1818.52" + wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 + attribute \src "ls180.v:1332.12-1332.40" + wire width 4 \main_sdcore_cmd_event_status + attribute \src "ls180.v:1333.6-1333.30" + wire \main_sdcore_cmd_event_we + attribute \src "ls180.v:1330.13-1330.44" + wire width 128 \main_sdcore_cmd_response_status + attribute \src "ls180.v:1825.13-1825.67" + wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 + attribute \src "ls180.v:1826.5-1826.62" + wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 + attribute \src "ls180.v:1331.6-1331.33" + wire \main_sdcore_cmd_response_we + attribute \src "ls180.v:1327.6-1327.28" + wire \main_sdcore_cmd_send_r + attribute \src "ls180.v:1326.6-1326.29" + wire \main_sdcore_cmd_send_re + attribute \src "ls180.v:1329.5-1329.27" + wire \main_sdcore_cmd_send_w + attribute \src "ls180.v:1328.6-1328.29" + wire \main_sdcore_cmd_send_we + attribute \src "ls180.v:1481.5-1481.28" + wire \main_sdcore_cmd_timeout + attribute \src "ls180.v:1819.5-1819.51" + wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 + attribute \src "ls180.v:1820.5-1820.54" + wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 + attribute \src "ls180.v:1477.12-1477.32" + wire width 2 \main_sdcore_cmd_type + attribute \src "ls180.v:1439.11-1439.40" + wire width 4 \main_sdcore_crc16_checker_cnt + attribute \src "ls180.v:1445.5-1445.39" + wire \main_sdcore_crc16_checker_crc0_clr + attribute \src "ls180.v:1444.12-1444.46" + wire width 16 \main_sdcore_crc16_checker_crc0_crc + attribute \src "ls180.v:1440.12-1440.50" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0 + attribute \src "ls180.v:1441.13-1441.51" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1 + attribute \src "ls180.v:1442.13-1442.51" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2 + attribute \src "ls180.v:1446.6-1446.43" + wire \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:1443.12-1443.46" + wire width 2 \main_sdcore_crc16_checker_crc0_val + attribute \src "ls180.v:1452.5-1452.39" + wire \main_sdcore_crc16_checker_crc1_clr + attribute \src "ls180.v:1451.12-1451.46" + wire width 16 \main_sdcore_crc16_checker_crc1_crc + attribute \src "ls180.v:1447.12-1447.50" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0 + attribute \src "ls180.v:1448.13-1448.51" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1 + attribute \src "ls180.v:1449.13-1449.51" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2 + attribute \src "ls180.v:1453.6-1453.43" + wire \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:1450.12-1450.46" + wire width 2 \main_sdcore_crc16_checker_crc1_val + attribute \src "ls180.v:1459.5-1459.39" + wire \main_sdcore_crc16_checker_crc2_clr + attribute \src "ls180.v:1458.12-1458.46" + wire width 16 \main_sdcore_crc16_checker_crc2_crc + attribute \src "ls180.v:1454.12-1454.50" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0 + attribute \src "ls180.v:1455.13-1455.51" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1 + attribute \src "ls180.v:1456.13-1456.51" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2 + attribute \src "ls180.v:1460.6-1460.43" + wire \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:1457.12-1457.46" + wire width 2 \main_sdcore_crc16_checker_crc2_val + attribute \src "ls180.v:1466.5-1466.39" + wire \main_sdcore_crc16_checker_crc3_clr + attribute \src "ls180.v:1465.12-1465.46" + wire width 16 \main_sdcore_crc16_checker_crc3_crc + attribute \src "ls180.v:1461.12-1461.50" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0 + attribute \src "ls180.v:1462.13-1462.51" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1 + attribute \src "ls180.v:1463.13-1463.51" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2 + attribute \src "ls180.v:1467.6-1467.43" + wire \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:1464.12-1464.46" + wire width 2 \main_sdcore_crc16_checker_crc3_val + attribute \src "ls180.v:1468.12-1468.45" + wire width 16 \main_sdcore_crc16_checker_crctmp0 + attribute \src "ls180.v:1469.12-1469.45" + wire width 16 \main_sdcore_crc16_checker_crctmp1 + attribute \src "ls180.v:1470.12-1470.45" + wire width 16 \main_sdcore_crc16_checker_crctmp2 + attribute \src "ls180.v:1471.12-1471.45" + wire width 16 \main_sdcore_crc16_checker_crctmp3 + attribute \src "ls180.v:1473.12-1473.43" + wire width 16 \main_sdcore_crc16_checker_fifo0 + attribute \src "ls180.v:1474.12-1474.43" + wire width 16 \main_sdcore_crc16_checker_fifo1 + attribute \src "ls180.v:1475.12-1475.43" + wire width 16 \main_sdcore_crc16_checker_fifo2 + attribute \src "ls180.v:1476.12-1476.43" + wire width 16 \main_sdcore_crc16_checker_fifo3 + attribute \src "ls180.v:1430.5-1430.41" + wire \main_sdcore_crc16_checker_sink_first + attribute \src "ls180.v:1431.5-1431.40" + wire \main_sdcore_crc16_checker_sink_last + attribute \src "ls180.v:1432.11-1432.54" + wire width 8 \main_sdcore_crc16_checker_sink_payload_data + attribute \src "ls180.v:1429.5-1429.41" + wire \main_sdcore_crc16_checker_sink_ready + attribute \src "ls180.v:1428.5-1428.41" + wire \main_sdcore_crc16_checker_sink_valid + attribute \src "ls180.v:1435.5-1435.43" + wire \main_sdcore_crc16_checker_source_first + attribute \src "ls180.v:1436.6-1436.43" + wire \main_sdcore_crc16_checker_source_last + attribute \src "ls180.v:1437.12-1437.57" + wire width 8 \main_sdcore_crc16_checker_source_payload_data + attribute \src "ls180.v:1434.6-1434.44" + wire \main_sdcore_crc16_checker_source_ready + attribute \src "ls180.v:1433.5-1433.43" + wire \main_sdcore_crc16_checker_source_valid + attribute \src "ls180.v:1438.11-1438.40" + wire width 8 \main_sdcore_crc16_checker_val + attribute \src "ls180.v:1472.5-1472.36" + wire \main_sdcore_crc16_checker_valid + attribute \src "ls180.v:1395.11-1395.41" + wire width 3 \main_sdcore_crc16_inserter_cnt + attribute \src "ls180.v:1805.11-1805.80" + wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 + attribute \src "ls180.v:1806.5-1806.77" + wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 + attribute \src "ls180.v:1401.6-1401.41" + wire \main_sdcore_crc16_inserter_crc0_clr + attribute \src "ls180.v:1400.12-1400.47" + wire width 16 \main_sdcore_crc16_inserter_crc0_crc + attribute \src "ls180.v:1396.12-1396.51" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0 + attribute \src "ls180.v:1397.13-1397.52" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1 + attribute \src "ls180.v:1398.13-1398.52" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2 + attribute \src "ls180.v:1402.6-1402.44" + wire \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:1399.12-1399.47" + wire width 2 \main_sdcore_crc16_inserter_crc0_val + attribute \src "ls180.v:1408.6-1408.41" + wire \main_sdcore_crc16_inserter_crc1_clr + attribute \src "ls180.v:1407.12-1407.47" + wire width 16 \main_sdcore_crc16_inserter_crc1_crc + attribute \src "ls180.v:1403.12-1403.51" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0 + attribute \src "ls180.v:1404.13-1404.52" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1 + attribute \src "ls180.v:1405.13-1405.52" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2 + attribute \src "ls180.v:1409.6-1409.44" + wire \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:1406.12-1406.47" + wire width 2 \main_sdcore_crc16_inserter_crc1_val + attribute \src "ls180.v:1415.6-1415.41" + wire \main_sdcore_crc16_inserter_crc2_clr + attribute \src "ls180.v:1414.12-1414.47" + wire width 16 \main_sdcore_crc16_inserter_crc2_crc + attribute \src "ls180.v:1410.12-1410.51" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0 + attribute \src "ls180.v:1411.13-1411.52" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1 + attribute \src "ls180.v:1412.13-1412.52" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2 + attribute \src "ls180.v:1416.6-1416.44" + wire \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:1413.12-1413.47" + wire width 2 \main_sdcore_crc16_inserter_crc2_val + attribute \src "ls180.v:1422.6-1422.41" + wire \main_sdcore_crc16_inserter_crc3_clr + attribute \src "ls180.v:1421.12-1421.47" + wire width 16 \main_sdcore_crc16_inserter_crc3_crc + attribute \src "ls180.v:1417.12-1417.51" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0 + attribute \src "ls180.v:1418.13-1418.52" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1 + attribute \src "ls180.v:1419.13-1419.52" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2 + attribute \src "ls180.v:1423.6-1423.44" + wire \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:1420.12-1420.47" + wire width 2 \main_sdcore_crc16_inserter_crc3_val + attribute \src "ls180.v:1424.12-1424.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp0 + attribute \src "ls180.v:1797.12-1797.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 + attribute \src "ls180.v:1798.5-1798.81" + wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 + attribute \src "ls180.v:1425.12-1425.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp1 + attribute \src "ls180.v:1799.12-1799.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 + attribute \src "ls180.v:1800.5-1800.81" + wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 + attribute \src "ls180.v:1426.12-1426.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp2 + attribute \src "ls180.v:1801.12-1801.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 + attribute \src "ls180.v:1802.5-1802.81" + wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 + attribute \src "ls180.v:1427.12-1427.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp3 + attribute \src "ls180.v:1803.12-1803.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 + attribute \src "ls180.v:1804.5-1804.81" + wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 + attribute \src "ls180.v:1387.6-1387.43" + wire \main_sdcore_crc16_inserter_sink_first + attribute \src "ls180.v:1388.6-1388.42" + wire \main_sdcore_crc16_inserter_sink_last + attribute \src "ls180.v:1389.12-1389.56" + wire width 8 \main_sdcore_crc16_inserter_sink_payload_data + attribute \src "ls180.v:1386.5-1386.42" + wire \main_sdcore_crc16_inserter_sink_ready + attribute \src "ls180.v:1385.6-1385.43" + wire \main_sdcore_crc16_inserter_sink_valid + attribute \src "ls180.v:1392.5-1392.44" + wire \main_sdcore_crc16_inserter_source_first + attribute \src "ls180.v:1393.5-1393.43" + wire \main_sdcore_crc16_inserter_source_last + attribute \src "ls180.v:1394.11-1394.57" + wire width 8 \main_sdcore_crc16_inserter_source_payload_data + attribute \src "ls180.v:1391.5-1391.44" + wire \main_sdcore_crc16_inserter_source_ready + attribute \src "ls180.v:1390.5-1390.44" + wire \main_sdcore_crc16_inserter_source_valid + attribute \src "ls180.v:1383.6-1383.35" + wire \main_sdcore_crc7_inserter_clr + attribute \src "ls180.v:1382.11-1382.40" + wire width 7 \main_sdcore_crc7_inserter_crc + attribute \src "ls180.v:1340.11-1340.44" + wire width 7 \main_sdcore_crc7_inserter_crcreg0 + attribute \src "ls180.v:1341.12-1341.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg1 + attribute \src "ls180.v:1350.12-1350.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg10 + attribute \src "ls180.v:1351.12-1351.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg11 + attribute \src "ls180.v:1352.12-1352.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg12 + attribute \src "ls180.v:1353.12-1353.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg13 + attribute \src "ls180.v:1354.12-1354.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg14 + attribute \src "ls180.v:1355.12-1355.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg15 + attribute \src "ls180.v:1356.12-1356.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg16 + attribute \src "ls180.v:1357.12-1357.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg17 + attribute \src "ls180.v:1358.12-1358.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg18 + attribute \src "ls180.v:1359.12-1359.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg19 + attribute \src "ls180.v:1342.12-1342.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg2 + attribute \src "ls180.v:1360.12-1360.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg20 + attribute \src "ls180.v:1361.12-1361.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg21 + attribute \src "ls180.v:1362.12-1362.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg22 + attribute \src "ls180.v:1363.12-1363.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg23 + attribute \src "ls180.v:1364.12-1364.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg24 + attribute \src "ls180.v:1365.12-1365.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg25 + attribute \src "ls180.v:1366.12-1366.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg26 + attribute \src "ls180.v:1367.12-1367.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg27 + attribute \src "ls180.v:1368.12-1368.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg28 + attribute \src "ls180.v:1369.12-1369.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg29 + attribute \src "ls180.v:1343.12-1343.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg3 + attribute \src "ls180.v:1370.12-1370.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg30 + attribute \src "ls180.v:1371.12-1371.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg31 + attribute \src "ls180.v:1372.12-1372.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg32 + attribute \src "ls180.v:1373.12-1373.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg33 + attribute \src "ls180.v:1374.12-1374.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg34 + attribute \src "ls180.v:1375.12-1375.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg35 + attribute \src "ls180.v:1376.12-1376.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg36 + attribute \src "ls180.v:1377.12-1377.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg37 + attribute \src "ls180.v:1378.12-1378.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg38 + attribute \src "ls180.v:1379.12-1379.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg39 + attribute \src "ls180.v:1344.12-1344.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg4 + attribute \src "ls180.v:1380.12-1380.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg40 + attribute \src "ls180.v:1345.12-1345.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg5 + attribute \src "ls180.v:1346.12-1346.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg6 + attribute \src "ls180.v:1347.12-1347.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg7 + attribute \src "ls180.v:1348.12-1348.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg8 + attribute \src "ls180.v:1349.12-1349.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg9 + attribute \src "ls180.v:1384.6-1384.38" + wire \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:1381.13-1381.42" + wire width 40 \main_sdcore_crc7_inserter_val + attribute \src "ls180.v:1483.12-1483.34" + wire width 32 \main_sdcore_data_count + attribute \src "ls180.v:1815.12-1815.57" + wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3 + attribute \src "ls180.v:1816.5-1816.53" + wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3 + attribute \src "ls180.v:1484.5-1484.26" + wire \main_sdcore_data_done + attribute \src "ls180.v:1811.5-1811.49" + wire \main_sdcore_data_done_sdcore_fsm_next_value1 + attribute \src "ls180.v:1812.5-1812.52" + wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1 + attribute \src "ls180.v:1485.5-1485.27" + wire \main_sdcore_data_error + attribute \src "ls180.v:1821.5-1821.50" + wire \main_sdcore_data_error_sdcore_fsm_next_value6 + attribute \src "ls180.v:1822.5-1822.53" + wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6 + attribute \src "ls180.v:1334.12-1334.41" + wire width 4 \main_sdcore_data_event_status + attribute \src "ls180.v:1335.6-1335.31" + wire \main_sdcore_data_event_we + attribute \src "ls180.v:1486.5-1486.29" + wire \main_sdcore_data_timeout + attribute \src "ls180.v:1823.5-1823.52" + wire \main_sdcore_data_timeout_sdcore_fsm_next_value7 + attribute \src "ls180.v:1824.5-1824.55" + wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 + attribute \src "ls180.v:1482.12-1482.33" + wire width 2 \main_sdcore_data_type + attribute \src "ls180.v:1314.6-1314.33" + wire \main_sdcore_sink_sink_first + attribute \src "ls180.v:1315.6-1315.32" + wire \main_sdcore_sink_sink_last + attribute \src "ls180.v:1316.12-1316.46" + wire width 8 \main_sdcore_sink_sink_payload_data + attribute \src "ls180.v:1313.6-1313.33" + wire \main_sdcore_sink_sink_ready + attribute \src "ls180.v:1312.6-1312.33" + wire \main_sdcore_sink_sink_valid + attribute \src "ls180.v:1319.6-1319.37" + wire \main_sdcore_source_source_first + attribute \src "ls180.v:1320.6-1320.36" + wire \main_sdcore_source_source_last + attribute \src "ls180.v:1321.12-1321.50" + wire width 8 \main_sdcore_source_source_payload_data + attribute \src "ls180.v:1318.6-1318.37" + wire \main_sdcore_source_source_ready + attribute \src "ls180.v:1317.6-1317.37" + wire \main_sdcore_source_source_valid + attribute \src "ls180.v:1632.6-1632.38" + wire \main_sdmem2block_converter_first + attribute \src "ls180.v:1633.6-1633.37" + wire \main_sdmem2block_converter_last + attribute \src "ls180.v:1631.11-1631.41" + wire width 2 \main_sdmem2block_converter_mux + attribute \src "ls180.v:1622.6-1622.43" + wire \main_sdmem2block_converter_sink_first + attribute \src "ls180.v:1623.6-1623.42" + wire \main_sdmem2block_converter_sink_last + attribute \src "ls180.v:1624.13-1624.57" + wire width 32 \main_sdmem2block_converter_sink_payload_data + attribute \src "ls180.v:1621.6-1621.43" + wire \main_sdmem2block_converter_sink_ready + attribute \src "ls180.v:1620.6-1620.43" + wire \main_sdmem2block_converter_sink_valid + attribute \src "ls180.v:1627.6-1627.45" + wire \main_sdmem2block_converter_source_first + attribute \src "ls180.v:1628.6-1628.44" + wire \main_sdmem2block_converter_source_last + attribute \src "ls180.v:1629.11-1629.57" + wire width 8 \main_sdmem2block_converter_source_payload_data + attribute \src "ls180.v:1630.6-1630.65" + wire \main_sdmem2block_converter_source_payload_valid_token_count + attribute \src "ls180.v:1626.6-1626.45" + wire \main_sdmem2block_converter_source_ready + attribute \src "ls180.v:1625.6-1625.45" + wire \main_sdmem2block_converter_source_valid + attribute \src "ls180.v:1616.13-1616.38" + wire width 32 \main_sdmem2block_dma_base + attribute \src "ls180.v:1605.5-1605.33" + wire \main_sdmem2block_dma_base_re + attribute \src "ls180.v:1604.12-1604.45" + wire width 64 \main_sdmem2block_dma_base_storage + attribute \src "ls180.v:1603.12-1603.37" + wire width 32 \main_sdmem2block_dma_data + attribute \src "ls180.v:1833.12-1833.67" + wire width 32 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + attribute \src "ls180.v:1834.5-1834.63" + wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce + attribute \src "ls180.v:1610.5-1610.37" + wire \main_sdmem2block_dma_done_status + attribute \src "ls180.v:1611.6-1611.34" + wire \main_sdmem2block_dma_done_we + attribute \src "ls180.v:1609.5-1609.35" + wire \main_sdmem2block_dma_enable_re + attribute \src "ls180.v:1608.5-1608.40" + wire \main_sdmem2block_dma_enable_storage + attribute \src "ls180.v:1618.13-1618.40" + wire width 32 \main_sdmem2block_dma_length + attribute \src "ls180.v:1607.5-1607.35" + wire \main_sdmem2block_dma_length_re + attribute \src "ls180.v:1606.12-1606.47" + wire width 32 \main_sdmem2block_dma_length_storage + attribute \src "ls180.v:1613.5-1613.33" + wire \main_sdmem2block_dma_loop_re + attribute \src "ls180.v:1612.5-1612.38" + wire \main_sdmem2block_dma_loop_storage + attribute \src "ls180.v:1617.12-1617.39" + wire width 32 \main_sdmem2block_dma_offset + attribute \src "ls180.v:1837.12-1837.79" + wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value + attribute \src "ls180.v:1838.5-1838.75" + wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce + attribute \src "ls180.v:1614.13-1614.47" + wire width 32 \main_sdmem2block_dma_offset_status + attribute \src "ls180.v:1615.6-1615.36" + wire \main_sdmem2block_dma_offset_we + attribute \src "ls180.v:1619.6-1619.32" + wire \main_sdmem2block_dma_reset + attribute \src "ls180.v:1596.5-1596.35" + wire \main_sdmem2block_dma_sink_last + attribute \src "ls180.v:1597.12-1597.53" + wire width 32 \main_sdmem2block_dma_sink_payload_address + attribute \src "ls180.v:1595.5-1595.36" + wire \main_sdmem2block_dma_sink_ready + attribute \src "ls180.v:1594.5-1594.36" + wire \main_sdmem2block_dma_sink_valid + attribute \src "ls180.v:1600.5-1600.38" + wire \main_sdmem2block_dma_source_first + attribute \src "ls180.v:1601.5-1601.37" + wire \main_sdmem2block_dma_source_last + attribute \src "ls180.v:1602.12-1602.52" + wire width 32 \main_sdmem2block_dma_source_payload_data + attribute \src "ls180.v:1599.6-1599.39" + wire \main_sdmem2block_dma_source_ready + attribute \src "ls180.v:1598.5-1598.38" + wire \main_sdmem2block_dma_source_valid + attribute \src "ls180.v:1658.11-1658.40" + wire width 5 \main_sdmem2block_fifo_consume + attribute \src "ls180.v:1663.6-1663.35" + wire \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:1667.6-1667.41" + wire \main_sdmem2block_fifo_fifo_in_first + attribute \src "ls180.v:1668.6-1668.40" + wire \main_sdmem2block_fifo_fifo_in_last + attribute \src "ls180.v:1666.12-1666.54" + wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data + attribute \src "ls180.v:1670.6-1670.42" + wire \main_sdmem2block_fifo_fifo_out_first + attribute \src "ls180.v:1671.6-1671.41" + wire \main_sdmem2block_fifo_fifo_out_last + attribute \src "ls180.v:1669.12-1669.55" + wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data + attribute \src "ls180.v:1655.11-1655.38" + wire width 6 \main_sdmem2block_fifo_level + attribute \src "ls180.v:1657.11-1657.40" + wire width 5 \main_sdmem2block_fifo_produce + attribute \src "ls180.v:1664.12-1664.44" + wire width 5 \main_sdmem2block_fifo_rdport_adr + attribute \src "ls180.v:1665.12-1665.46" + wire width 10 \main_sdmem2block_fifo_rdport_dat_r + attribute \src "ls180.v:1656.5-1656.34" + wire \main_sdmem2block_fifo_replace + attribute \src "ls180.v:1641.6-1641.38" + wire \main_sdmem2block_fifo_sink_first + attribute \src "ls180.v:1642.6-1642.37" + wire \main_sdmem2block_fifo_sink_last + attribute \src "ls180.v:1643.12-1643.51" + wire width 8 \main_sdmem2block_fifo_sink_payload_data + attribute \src "ls180.v:1640.6-1640.38" + wire \main_sdmem2block_fifo_sink_ready + attribute \src "ls180.v:1639.6-1639.38" + wire \main_sdmem2block_fifo_sink_valid + attribute \src "ls180.v:1646.6-1646.40" + wire \main_sdmem2block_fifo_source_first + attribute \src "ls180.v:1647.6-1647.39" + wire \main_sdmem2block_fifo_source_last + attribute \src "ls180.v:1648.12-1648.53" + wire width 8 \main_sdmem2block_fifo_source_payload_data + attribute \src "ls180.v:1645.6-1645.40" + wire \main_sdmem2block_fifo_source_ready + attribute \src "ls180.v:1644.6-1644.40" + wire \main_sdmem2block_fifo_source_valid + attribute \src "ls180.v:1653.12-1653.46" + wire width 10 \main_sdmem2block_fifo_syncfifo_din + attribute \src "ls180.v:1654.12-1654.47" + wire width 10 \main_sdmem2block_fifo_syncfifo_dout + attribute \src "ls180.v:1651.6-1651.39" + wire \main_sdmem2block_fifo_syncfifo_re + attribute \src "ls180.v:1652.6-1652.45" + wire \main_sdmem2block_fifo_syncfifo_readable + attribute \src "ls180.v:1649.6-1649.39" + wire \main_sdmem2block_fifo_syncfifo_we + attribute \src "ls180.v:1650.6-1650.45" + wire \main_sdmem2block_fifo_syncfifo_writable + attribute \src "ls180.v:1659.11-1659.43" + wire width 5 \main_sdmem2block_fifo_wrport_adr + attribute \src "ls180.v:1660.12-1660.46" + wire width 10 \main_sdmem2block_fifo_wrport_dat_r + attribute \src "ls180.v:1662.12-1662.46" + wire width 10 \main_sdmem2block_fifo_wrport_dat_w + attribute \src "ls180.v:1661.6-1661.37" + wire \main_sdmem2block_fifo_wrport_we + attribute \src "ls180.v:1591.6-1591.43" + wire \main_sdmem2block_source_source_first0 + attribute \src "ls180.v:1636.6-1636.43" + wire \main_sdmem2block_source_source_first1 + attribute \src "ls180.v:1592.6-1592.42" + wire \main_sdmem2block_source_source_last0 + attribute \src "ls180.v:1637.6-1637.42" + wire \main_sdmem2block_source_source_last1 + attribute \src "ls180.v:1593.12-1593.56" + wire width 8 \main_sdmem2block_source_source_payload_data0 + attribute \src "ls180.v:1638.12-1638.56" + wire width 8 \main_sdmem2block_source_source_payload_data1 + attribute \src "ls180.v:1590.6-1590.43" + wire \main_sdmem2block_source_source_ready0 + attribute \src "ls180.v:1635.6-1635.43" + wire \main_sdmem2block_source_source_ready1 + attribute \src "ls180.v:1589.6-1589.43" + wire \main_sdmem2block_source_source_valid0 + attribute \src "ls180.v:1634.6-1634.43" + wire \main_sdmem2block_source_source_valid1 + attribute \src "ls180.v:1040.6-1040.27" + wire \main_sdphy_clocker_ce + attribute \src "ls180.v:1039.5-1039.28" + wire \main_sdphy_clocker_clk0 + attribute \src "ls180.v:1042.5-1042.28" + wire \main_sdphy_clocker_clk1 + attribute \src "ls180.v:1043.5-1043.29" + wire \main_sdphy_clocker_clk_d + attribute \src "ls180.v:1041.11-1041.34" + wire width 9 \main_sdphy_clocker_clks + attribute \src "ls180.v:1037.5-1037.26" + wire \main_sdphy_clocker_re + attribute \src "ls180.v:1038.6-1038.29" + wire \main_sdphy_clocker_stop + attribute \src "ls180.v:1036.11-1036.37" + wire width 9 \main_sdphy_clocker_storage + attribute \src "ls180.v:1140.6-1140.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_first + attribute \src "ls180.v:1141.6-1141.40" + wire \main_sdphy_cmdr_cmdr_buf_sink_last + attribute \src "ls180.v:1142.12-1142.54" + wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data + attribute \src "ls180.v:1139.6-1139.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_ready + attribute \src "ls180.v:1138.6-1138.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_valid + attribute \src "ls180.v:1145.5-1145.42" + wire \main_sdphy_cmdr_cmdr_buf_source_first + attribute \src "ls180.v:1146.5-1146.41" + wire \main_sdphy_cmdr_cmdr_buf_source_last + attribute \src "ls180.v:1147.11-1147.55" + wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data + attribute \src "ls180.v:1144.6-1144.43" + wire \main_sdphy_cmdr_cmdr_buf_source_ready + attribute \src "ls180.v:1143.5-1143.42" + wire \main_sdphy_cmdr_cmdr_buf_source_valid + attribute \src "ls180.v:1130.11-1130.47" + wire width 3 \main_sdphy_cmdr_cmdr_converter_demux + attribute \src "ls180.v:1131.6-1131.46" + wire \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:1121.5-1121.46" + wire \main_sdphy_cmdr_cmdr_converter_sink_first + attribute \src "ls180.v:1122.5-1122.45" + wire \main_sdphy_cmdr_cmdr_converter_sink_last + attribute \src "ls180.v:1123.6-1123.54" + wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:1120.6-1120.47" + wire \main_sdphy_cmdr_cmdr_converter_sink_ready + attribute \src "ls180.v:1119.6-1119.47" + wire \main_sdphy_cmdr_cmdr_converter_sink_valid + attribute \src "ls180.v:1126.5-1126.48" + wire \main_sdphy_cmdr_cmdr_converter_source_first + attribute \src "ls180.v:1127.5-1127.47" + wire \main_sdphy_cmdr_cmdr_converter_source_last + attribute \src "ls180.v:1128.11-1128.61" + wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data + attribute \src "ls180.v:1129.11-1129.74" + wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count + attribute \src "ls180.v:1125.6-1125.49" + wire \main_sdphy_cmdr_cmdr_converter_source_ready + attribute \src "ls180.v:1124.6-1124.49" + wire \main_sdphy_cmdr_cmdr_converter_source_valid + attribute \src "ls180.v:1132.5-1132.46" + wire \main_sdphy_cmdr_cmdr_converter_strobe_all + attribute \src "ls180.v:1103.6-1103.40" + wire \main_sdphy_cmdr_cmdr_pads_in_first + attribute \src "ls180.v:1104.6-1104.39" + wire \main_sdphy_cmdr_cmdr_pads_in_last + attribute \src "ls180.v:1105.6-1105.46" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk + attribute \src "ls180.v:1106.6-1106.48" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + attribute \src "ls180.v:1107.6-1107.48" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o + attribute \src "ls180.v:1108.6-1108.49" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe + attribute \src "ls180.v:1109.12-1109.55" + wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i + attribute \src "ls180.v:1110.12-1110.55" + wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o + attribute \src "ls180.v:1111.6-1111.50" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe + attribute \src "ls180.v:1102.5-1102.39" + wire \main_sdphy_cmdr_cmdr_pads_in_ready + attribute \src "ls180.v:1101.6-1101.40" + wire \main_sdphy_cmdr_cmdr_pads_in_valid + attribute \src "ls180.v:1148.5-1148.31" + wire \main_sdphy_cmdr_cmdr_reset + attribute \src "ls180.v:1777.5-1777.59" + wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 + attribute \src "ls180.v:1778.5-1778.62" + wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 + attribute \src "ls180.v:1118.5-1118.29" + wire \main_sdphy_cmdr_cmdr_run + attribute \src "ls180.v:1114.6-1114.47" + wire \main_sdphy_cmdr_cmdr_source_source_first0 + attribute \src "ls180.v:1135.6-1135.47" + wire \main_sdphy_cmdr_cmdr_source_source_first1 + attribute \src "ls180.v:1115.6-1115.46" + wire \main_sdphy_cmdr_cmdr_source_source_last0 + attribute \src "ls180.v:1136.6-1136.46" + wire \main_sdphy_cmdr_cmdr_source_source_last1 + attribute \src "ls180.v:1116.12-1116.60" + wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0 + attribute \src "ls180.v:1137.12-1137.60" + wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1 + attribute \src "ls180.v:1113.5-1113.46" + wire \main_sdphy_cmdr_cmdr_source_source_ready0 + attribute \src "ls180.v:1134.6-1134.47" + wire \main_sdphy_cmdr_cmdr_source_source_ready1 + attribute \src "ls180.v:1112.6-1112.47" + wire \main_sdphy_cmdr_cmdr_source_source_valid0 + attribute \src "ls180.v:1133.6-1133.47" + wire \main_sdphy_cmdr_cmdr_source_source_valid1 + attribute \src "ls180.v:1117.6-1117.32" + wire \main_sdphy_cmdr_cmdr_start + attribute \src "ls180.v:1100.11-1100.32" + wire width 8 \main_sdphy_cmdr_count + attribute \src "ls180.v:1773.11-1773.60" + wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 + attribute \src "ls180.v:1774.5-1774.57" + wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 + attribute \src "ls180.v:1075.5-1075.42" + wire \main_sdphy_cmdr_pads_in_pads_in_first + attribute \src "ls180.v:1076.5-1076.41" + wire \main_sdphy_cmdr_pads_in_pads_in_last + attribute \src "ls180.v:1077.5-1077.48" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1078.6-1078.51" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1079.5-1079.50" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1080.5-1080.51" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1081.12-1081.58" + wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1082.11-1082.57" + wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1083.5-1083.52" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1074.6-1074.43" + wire \main_sdphy_cmdr_pads_in_pads_in_ready + attribute \src "ls180.v:1073.6-1073.43" + wire \main_sdphy_cmdr_pads_in_pads_in_valid + attribute \src "ls180.v:1085.5-1085.41" + wire \main_sdphy_cmdr_pads_out_payload_clk + attribute \src "ls180.v:1086.5-1086.43" + wire \main_sdphy_cmdr_pads_out_payload_cmd_o + attribute \src "ls180.v:1087.5-1087.44" + wire \main_sdphy_cmdr_pads_out_payload_cmd_oe + attribute \src "ls180.v:1088.11-1088.50" + wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o + attribute \src "ls180.v:1089.5-1089.45" + wire \main_sdphy_cmdr_pads_out_payload_data_oe + attribute \src "ls180.v:1084.6-1084.36" + wire \main_sdphy_cmdr_pads_out_ready + attribute \src "ls180.v:1092.5-1092.30" + wire \main_sdphy_cmdr_sink_last + attribute \src "ls180.v:1093.11-1093.46" + wire width 8 \main_sdphy_cmdr_sink_payload_length + attribute \src "ls180.v:1091.5-1091.31" + wire \main_sdphy_cmdr_sink_ready + attribute \src "ls180.v:1090.5-1090.31" + wire \main_sdphy_cmdr_sink_valid + attribute \src "ls180.v:1096.5-1096.32" + wire \main_sdphy_cmdr_source_last + attribute \src "ls180.v:1097.11-1097.46" + wire width 8 \main_sdphy_cmdr_source_payload_data + attribute \src "ls180.v:1098.11-1098.48" + wire width 3 \main_sdphy_cmdr_source_payload_status + attribute \src "ls180.v:1095.5-1095.33" + wire \main_sdphy_cmdr_source_ready + attribute \src "ls180.v:1094.5-1094.33" + wire \main_sdphy_cmdr_source_valid + attribute \src "ls180.v:1099.12-1099.35" + wire width 32 \main_sdphy_cmdr_timeout + attribute \src "ls180.v:1775.12-1775.63" + wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 + attribute \src "ls180.v:1776.5-1776.59" + wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 + attribute \src "ls180.v:1072.11-1072.32" + wire width 8 \main_sdphy_cmdw_count + attribute \src "ls180.v:1769.11-1769.59" + wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value + attribute \src "ls180.v:1770.5-1770.56" + wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce + attribute \src "ls180.v:1071.5-1071.25" + wire \main_sdphy_cmdw_done + attribute \src "ls180.v:1059.6-1059.43" + wire \main_sdphy_cmdw_pads_in_payload_cmd_i + attribute \src "ls180.v:1060.12-1060.50" + wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i + attribute \src "ls180.v:1058.6-1058.35" + wire \main_sdphy_cmdw_pads_in_valid + attribute \src "ls180.v:1062.5-1062.41" + wire \main_sdphy_cmdw_pads_out_payload_clk + attribute \src "ls180.v:1063.5-1063.43" + wire \main_sdphy_cmdw_pads_out_payload_cmd_o + attribute \src "ls180.v:1064.5-1064.44" + wire \main_sdphy_cmdw_pads_out_payload_cmd_oe + attribute \src "ls180.v:1065.11-1065.50" + wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o + attribute \src "ls180.v:1066.5-1066.45" + wire \main_sdphy_cmdw_pads_out_payload_data_oe + attribute \src "ls180.v:1061.6-1061.36" + wire \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:1069.5-1069.30" + wire \main_sdphy_cmdw_sink_last + attribute \src "ls180.v:1070.11-1070.44" + wire width 8 \main_sdphy_cmdw_sink_payload_data + attribute \src "ls180.v:1068.5-1068.31" + wire \main_sdphy_cmdw_sink_ready + attribute \src "ls180.v:1067.5-1067.31" + wire \main_sdphy_cmdw_sink_valid + attribute \src "ls180.v:1256.11-1256.33" + wire width 10 \main_sdphy_datar_count + attribute \src "ls180.v:1789.11-1789.62" + wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 + attribute \src "ls180.v:1790.5-1790.59" + wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 + attribute \src "ls180.v:1296.6-1296.43" + wire \main_sdphy_datar_datar_buf_sink_first + attribute \src "ls180.v:1297.6-1297.42" + wire \main_sdphy_datar_datar_buf_sink_last + attribute \src "ls180.v:1298.12-1298.56" + wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data + attribute \src "ls180.v:1295.6-1295.43" + wire \main_sdphy_datar_datar_buf_sink_ready + attribute \src "ls180.v:1294.6-1294.43" + wire \main_sdphy_datar_datar_buf_sink_valid + attribute \src "ls180.v:1301.5-1301.44" + wire \main_sdphy_datar_datar_buf_source_first + attribute \src "ls180.v:1302.5-1302.43" + wire \main_sdphy_datar_datar_buf_source_last + attribute \src "ls180.v:1303.11-1303.57" + wire width 8 \main_sdphy_datar_datar_buf_source_payload_data + attribute \src "ls180.v:1300.6-1300.45" + wire \main_sdphy_datar_datar_buf_source_ready + attribute \src "ls180.v:1299.5-1299.44" + wire \main_sdphy_datar_datar_buf_source_valid + attribute \src "ls180.v:1286.5-1286.43" + wire \main_sdphy_datar_datar_converter_demux + attribute \src "ls180.v:1287.6-1287.48" + wire \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:1277.5-1277.48" + wire \main_sdphy_datar_datar_converter_sink_first + attribute \src "ls180.v:1278.5-1278.47" + wire \main_sdphy_datar_datar_converter_sink_last + attribute \src "ls180.v:1279.12-1279.62" + wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data + attribute \src "ls180.v:1276.6-1276.49" + wire \main_sdphy_datar_datar_converter_sink_ready + attribute \src "ls180.v:1275.6-1275.49" + wire \main_sdphy_datar_datar_converter_sink_valid + attribute \src "ls180.v:1282.5-1282.50" + wire \main_sdphy_datar_datar_converter_source_first + attribute \src "ls180.v:1283.5-1283.49" + wire \main_sdphy_datar_datar_converter_source_last + attribute \src "ls180.v:1284.11-1284.63" + wire width 8 \main_sdphy_datar_datar_converter_source_payload_data + attribute \src "ls180.v:1285.11-1285.76" + wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count + attribute \src "ls180.v:1281.6-1281.51" + wire \main_sdphy_datar_datar_converter_source_ready + attribute \src "ls180.v:1280.6-1280.51" + wire \main_sdphy_datar_datar_converter_source_valid + attribute \src "ls180.v:1288.5-1288.48" + wire \main_sdphy_datar_datar_converter_strobe_all + attribute \src "ls180.v:1259.6-1259.42" + wire \main_sdphy_datar_datar_pads_in_first + attribute \src "ls180.v:1260.6-1260.41" + wire \main_sdphy_datar_datar_pads_in_last + attribute \src "ls180.v:1261.6-1261.48" + wire \main_sdphy_datar_datar_pads_in_payload_clk + attribute \src "ls180.v:1262.6-1262.50" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_i + attribute \src "ls180.v:1263.6-1263.50" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_o + attribute \src "ls180.v:1264.6-1264.51" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe + attribute \src "ls180.v:1265.12-1265.57" + wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i + attribute \src "ls180.v:1266.12-1266.57" + wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o + attribute \src "ls180.v:1267.6-1267.52" + wire \main_sdphy_datar_datar_pads_in_payload_data_oe + attribute \src "ls180.v:1258.5-1258.41" + wire \main_sdphy_datar_datar_pads_in_ready + attribute \src "ls180.v:1257.6-1257.42" + wire \main_sdphy_datar_datar_pads_in_valid + attribute \src "ls180.v:1304.5-1304.33" + wire \main_sdphy_datar_datar_reset + attribute \src "ls180.v:1793.5-1793.62" + wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 + attribute \src "ls180.v:1794.5-1794.65" + wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 + attribute \src "ls180.v:1274.5-1274.31" + wire \main_sdphy_datar_datar_run + attribute \src "ls180.v:1270.6-1270.49" + wire \main_sdphy_datar_datar_source_source_first0 + attribute \src "ls180.v:1291.6-1291.49" + wire \main_sdphy_datar_datar_source_source_first1 + attribute \src "ls180.v:1271.6-1271.48" + wire \main_sdphy_datar_datar_source_source_last0 + attribute \src "ls180.v:1292.6-1292.48" + wire \main_sdphy_datar_datar_source_source_last1 + attribute \src "ls180.v:1272.12-1272.62" + wire width 8 \main_sdphy_datar_datar_source_source_payload_data0 + attribute \src "ls180.v:1293.12-1293.62" + wire width 8 \main_sdphy_datar_datar_source_source_payload_data1 + attribute \src "ls180.v:1269.5-1269.48" + wire \main_sdphy_datar_datar_source_source_ready0 + attribute \src "ls180.v:1290.6-1290.49" + wire \main_sdphy_datar_datar_source_source_ready1 + attribute \src "ls180.v:1268.6-1268.49" + wire \main_sdphy_datar_datar_source_source_valid0 + attribute \src "ls180.v:1289.6-1289.49" + wire \main_sdphy_datar_datar_source_source_valid1 + attribute \src "ls180.v:1273.6-1273.34" + wire \main_sdphy_datar_datar_start + attribute \src "ls180.v:1229.5-1229.43" + wire \main_sdphy_datar_pads_in_pads_in_first + attribute \src "ls180.v:1230.5-1230.42" + wire \main_sdphy_datar_pads_in_pads_in_last + attribute \src "ls180.v:1231.5-1231.49" + wire \main_sdphy_datar_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1232.6-1232.52" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1233.5-1233.51" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1234.5-1234.52" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1235.12-1235.59" + wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1236.11-1236.58" + wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1237.5-1237.53" + wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1228.6-1228.44" + wire \main_sdphy_datar_pads_in_pads_in_ready + attribute \src "ls180.v:1227.6-1227.44" + wire \main_sdphy_datar_pads_in_pads_in_valid + attribute \src "ls180.v:1239.5-1239.42" + wire \main_sdphy_datar_pads_out_payload_clk + attribute \src "ls180.v:1240.5-1240.44" + wire \main_sdphy_datar_pads_out_payload_cmd_o + attribute \src "ls180.v:1241.5-1241.45" + wire \main_sdphy_datar_pads_out_payload_cmd_oe + attribute \src "ls180.v:1242.11-1242.51" + wire width 4 \main_sdphy_datar_pads_out_payload_data_o + attribute \src "ls180.v:1243.5-1243.46" + wire \main_sdphy_datar_pads_out_payload_data_oe + attribute \src "ls180.v:1238.6-1238.37" + wire \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:1246.5-1246.31" + wire \main_sdphy_datar_sink_last + attribute \src "ls180.v:1247.11-1247.53" + wire width 10 \main_sdphy_datar_sink_payload_block_length + attribute \src "ls180.v:1245.5-1245.32" + wire \main_sdphy_datar_sink_ready + attribute \src "ls180.v:1244.5-1244.32" + wire \main_sdphy_datar_sink_valid + attribute \src "ls180.v:1250.5-1250.34" + wire \main_sdphy_datar_source_first + attribute \src "ls180.v:1251.5-1251.33" + wire \main_sdphy_datar_source_last + attribute \src "ls180.v:1252.11-1252.47" + wire width 8 \main_sdphy_datar_source_payload_data + attribute \src "ls180.v:1253.11-1253.49" + wire width 3 \main_sdphy_datar_source_payload_status + attribute \src "ls180.v:1249.5-1249.34" + wire \main_sdphy_datar_source_ready + attribute \src "ls180.v:1248.5-1248.34" + wire \main_sdphy_datar_source_valid + attribute \src "ls180.v:1254.5-1254.26" + wire \main_sdphy_datar_stop + attribute \src "ls180.v:1255.12-1255.36" + wire width 32 \main_sdphy_datar_timeout + attribute \src "ls180.v:1791.12-1791.65" + wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 + attribute \src "ls180.v:1792.5-1792.61" + wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 + attribute \src "ls180.v:1164.11-1164.33" + wire width 8 \main_sdphy_dataw_count + attribute \src "ls180.v:1785.11-1785.54" + wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value + attribute \src "ls180.v:1786.5-1786.51" + wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce + attribute \src "ls180.v:1218.6-1218.42" + wire \main_sdphy_dataw_crcr_buf_sink_first + attribute \src "ls180.v:1219.6-1219.41" + wire \main_sdphy_dataw_crcr_buf_sink_last + attribute \src "ls180.v:1220.12-1220.55" + wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data + attribute \src "ls180.v:1217.6-1217.42" + wire \main_sdphy_dataw_crcr_buf_sink_ready + attribute \src "ls180.v:1216.6-1216.42" + wire \main_sdphy_dataw_crcr_buf_sink_valid + attribute \src "ls180.v:1223.5-1223.43" + wire \main_sdphy_dataw_crcr_buf_source_first + attribute \src "ls180.v:1224.5-1224.42" + wire \main_sdphy_dataw_crcr_buf_source_last + attribute \src "ls180.v:1225.11-1225.56" + wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data + attribute \src "ls180.v:1222.6-1222.44" + wire \main_sdphy_dataw_crcr_buf_source_ready + attribute \src "ls180.v:1221.5-1221.43" + wire \main_sdphy_dataw_crcr_buf_source_valid + attribute \src "ls180.v:1208.11-1208.48" + wire width 3 \main_sdphy_dataw_crcr_converter_demux + attribute \src "ls180.v:1209.6-1209.47" + wire \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:1199.5-1199.47" + wire \main_sdphy_dataw_crcr_converter_sink_first + attribute \src "ls180.v:1200.5-1200.46" + wire \main_sdphy_dataw_crcr_converter_sink_last + attribute \src "ls180.v:1201.6-1201.55" + wire \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:1198.6-1198.48" + wire \main_sdphy_dataw_crcr_converter_sink_ready + attribute \src "ls180.v:1197.6-1197.48" + wire \main_sdphy_dataw_crcr_converter_sink_valid + attribute \src "ls180.v:1204.5-1204.49" + wire \main_sdphy_dataw_crcr_converter_source_first + attribute \src "ls180.v:1205.5-1205.48" + wire \main_sdphy_dataw_crcr_converter_source_last + attribute \src "ls180.v:1206.11-1206.62" + wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data + attribute \src "ls180.v:1207.11-1207.75" + wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count + attribute \src "ls180.v:1203.6-1203.50" + wire \main_sdphy_dataw_crcr_converter_source_ready + attribute \src "ls180.v:1202.6-1202.50" + wire \main_sdphy_dataw_crcr_converter_source_valid + attribute \src "ls180.v:1210.5-1210.47" + wire \main_sdphy_dataw_crcr_converter_strobe_all + attribute \src "ls180.v:1181.6-1181.41" + wire \main_sdphy_dataw_crcr_pads_in_first + attribute \src "ls180.v:1182.6-1182.40" + wire \main_sdphy_dataw_crcr_pads_in_last + attribute \src "ls180.v:1183.6-1183.47" + wire \main_sdphy_dataw_crcr_pads_in_payload_clk + attribute \src "ls180.v:1184.6-1184.49" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i + attribute \src "ls180.v:1185.6-1185.49" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o + attribute \src "ls180.v:1186.6-1186.50" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe + attribute \src "ls180.v:1187.12-1187.56" + wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i + attribute \src "ls180.v:1188.12-1188.56" + wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o + attribute \src "ls180.v:1189.6-1189.51" + wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe + attribute \src "ls180.v:1180.5-1180.40" + wire \main_sdphy_dataw_crcr_pads_in_ready + attribute \src "ls180.v:1179.6-1179.41" + wire \main_sdphy_dataw_crcr_pads_in_valid + attribute \src "ls180.v:1226.5-1226.32" + wire \main_sdphy_dataw_crcr_reset + attribute \src "ls180.v:1781.5-1781.59" + wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value + attribute \src "ls180.v:1782.5-1782.62" + wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce + attribute \src "ls180.v:1196.5-1196.30" + wire \main_sdphy_dataw_crcr_run + attribute \src "ls180.v:1192.6-1192.48" + wire \main_sdphy_dataw_crcr_source_source_first0 + attribute \src "ls180.v:1213.6-1213.48" + wire \main_sdphy_dataw_crcr_source_source_first1 + attribute \src "ls180.v:1193.6-1193.47" + wire \main_sdphy_dataw_crcr_source_source_last0 + attribute \src "ls180.v:1214.6-1214.47" + wire \main_sdphy_dataw_crcr_source_source_last1 + attribute \src "ls180.v:1194.12-1194.61" + wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0 + attribute \src "ls180.v:1215.12-1215.61" + wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1 + attribute \src "ls180.v:1191.5-1191.47" + wire \main_sdphy_dataw_crcr_source_source_ready0 + attribute \src "ls180.v:1212.6-1212.48" + wire \main_sdphy_dataw_crcr_source_source_ready1 + attribute \src "ls180.v:1190.6-1190.48" + wire \main_sdphy_dataw_crcr_source_source_valid0 + attribute \src "ls180.v:1211.6-1211.48" + wire \main_sdphy_dataw_crcr_source_source_valid1 + attribute \src "ls180.v:1195.6-1195.33" + wire \main_sdphy_dataw_crcr_start + attribute \src "ls180.v:1178.5-1178.27" + wire \main_sdphy_dataw_error + attribute \src "ls180.v:1167.5-1167.43" + wire \main_sdphy_dataw_pads_in_pads_in_first + attribute \src "ls180.v:1168.5-1168.42" + wire \main_sdphy_dataw_pads_in_pads_in_last + attribute \src "ls180.v:1169.5-1169.49" + wire \main_sdphy_dataw_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1170.5-1170.51" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1171.5-1171.51" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1172.5-1172.52" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1173.11-1173.58" + wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1174.11-1174.58" + wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1175.5-1175.53" + wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1166.6-1166.44" + wire \main_sdphy_dataw_pads_in_pads_in_ready + attribute \src "ls180.v:1165.5-1165.43" + wire \main_sdphy_dataw_pads_in_pads_in_valid + attribute \src "ls180.v:1150.6-1150.44" + wire \main_sdphy_dataw_pads_in_payload_cmd_i + attribute \src "ls180.v:1151.12-1151.51" + wire width 4 \main_sdphy_dataw_pads_in_payload_data_i + attribute \src "ls180.v:1149.6-1149.36" + wire \main_sdphy_dataw_pads_in_valid + attribute \src "ls180.v:1153.5-1153.42" + wire \main_sdphy_dataw_pads_out_payload_clk + attribute \src "ls180.v:1154.5-1154.44" + wire \main_sdphy_dataw_pads_out_payload_cmd_o + attribute \src "ls180.v:1155.5-1155.45" + wire \main_sdphy_dataw_pads_out_payload_cmd_oe + attribute \src "ls180.v:1156.11-1156.51" + wire width 4 \main_sdphy_dataw_pads_out_payload_data_o + attribute \src "ls180.v:1157.5-1157.46" + wire \main_sdphy_dataw_pads_out_payload_data_oe + attribute \src "ls180.v:1152.6-1152.37" + wire \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:1160.5-1160.32" + wire \main_sdphy_dataw_sink_first + attribute \src "ls180.v:1161.5-1161.31" + wire \main_sdphy_dataw_sink_last + attribute \src "ls180.v:1162.11-1162.45" + wire width 8 \main_sdphy_dataw_sink_payload_data + attribute \src "ls180.v:1159.5-1159.32" + wire \main_sdphy_dataw_sink_ready + attribute \src "ls180.v:1158.5-1158.32" + wire \main_sdphy_dataw_sink_valid + attribute \src "ls180.v:1176.5-1176.27" + wire \main_sdphy_dataw_start + attribute \src "ls180.v:1163.5-1163.26" + wire \main_sdphy_dataw_stop + attribute \src "ls180.v:1177.5-1177.27" + wire \main_sdphy_dataw_valid + attribute \src "ls180.v:1057.11-1057.32" + wire width 8 \main_sdphy_init_count + attribute \src "ls180.v:1765.11-1765.59" + wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value + attribute \src "ls180.v:1766.5-1766.56" + wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce + attribute \src "ls180.v:1045.6-1045.34" + wire \main_sdphy_init_initialize_r + attribute \src "ls180.v:1044.6-1044.35" + wire \main_sdphy_init_initialize_re + attribute \src "ls180.v:1047.5-1047.33" + wire \main_sdphy_init_initialize_w + attribute \src "ls180.v:1046.6-1046.35" + wire \main_sdphy_init_initialize_we + attribute \src "ls180.v:1049.6-1049.43" + wire \main_sdphy_init_pads_in_payload_cmd_i + attribute \src "ls180.v:1050.12-1050.50" + wire width 4 \main_sdphy_init_pads_in_payload_data_i + attribute \src "ls180.v:1048.6-1048.35" + wire \main_sdphy_init_pads_in_valid + attribute \src "ls180.v:1052.5-1052.41" + wire \main_sdphy_init_pads_out_payload_clk + attribute \src "ls180.v:1053.5-1053.43" + wire \main_sdphy_init_pads_out_payload_cmd_o + attribute \src "ls180.v:1054.5-1054.44" + wire \main_sdphy_init_pads_out_payload_cmd_oe + attribute \src "ls180.v:1055.11-1055.50" + wire width 4 \main_sdphy_init_pads_out_payload_data_o + attribute \src "ls180.v:1056.5-1056.45" + wire \main_sdphy_init_pads_out_payload_data_oe + attribute \src "ls180.v:1051.6-1051.36" + wire \main_sdphy_init_pads_out_ready + attribute \src "ls180.v:1305.6-1305.27" + wire \main_sdphy_sdpads_clk + attribute \src "ls180.v:1306.5-1306.28" + wire \main_sdphy_sdpads_cmd_i + attribute \src "ls180.v:1307.6-1307.29" + wire \main_sdphy_sdpads_cmd_o + attribute \src "ls180.v:1308.6-1308.30" + wire \main_sdphy_sdpads_cmd_oe + attribute \src "ls180.v:1309.11-1309.35" + wire width 4 \main_sdphy_sdpads_data_i + attribute \src "ls180.v:1310.12-1310.36" + wire width 4 \main_sdphy_sdpads_data_o + attribute \src "ls180.v:1311.6-1311.31" + wire \main_sdphy_sdpads_data_oe + attribute \src "ls180.v:1034.6-1034.23" + wire \main_sdphy_status + attribute \src "ls180.v:1035.6-1035.19" + wire \main_sdphy_we + attribute \src "ls180.v:307.5-307.26" + wire \main_sdram_address_re + attribute \src "ls180.v:306.12-306.38" + wire width 13 \main_sdram_address_storage + attribute \src "ls180.v:309.5-309.27" + wire \main_sdram_baddress_re + attribute \src "ls180.v:308.11-308.38" + wire width 2 \main_sdram_baddress_storage + attribute \src "ls180.v:405.5-405.43" + wire \main_sdram_bankmachine0_auto_precharge + attribute \src "ls180.v:427.11-427.63" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + attribute \src "ls180.v:432.6-432.58" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:437.6-437.64" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:438.6-438.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:436.13-436.78" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:435.6-435.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:441.6-441.65" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:442.6-442.64" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:440.13-440.79" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:439.6-439.70" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:424.11-424.61" + wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level + attribute \src "ls180.v:426.11-426.63" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + attribute \src "ls180.v:433.12-433.67" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:434.13-434.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:425.5-425.57" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "ls180.v:408.5-408.60" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:409.5-409.59" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:411.13-411.75" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:410.6-410.66" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:407.6-407.61" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:406.6-406.61" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:414.6-414.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:415.6-415.62" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:417.13-417.77" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:416.6-416.68" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:413.6-413.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:412.6-412.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:422.13-422.71" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + attribute \src "ls180.v:423.13-423.72" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + attribute \src "ls180.v:420.6-420.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + attribute \src "ls180.v:421.6-421.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + attribute \src "ls180.v:418.6-418.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + attribute \src "ls180.v:419.6-419.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + attribute \src "ls180.v:428.11-428.66" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:429.13-429.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:431.13-431.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:430.6-430.60" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:445.6-445.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_first + attribute \src "ls180.v:446.6-446.50" + wire \main_sdram_bankmachine0_cmd_buffer_sink_last + attribute \src "ls180.v:448.13-448.65" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:447.6-447.56" + wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we + attribute \src "ls180.v:444.6-444.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_ready + attribute \src "ls180.v:443.6-443.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_valid + attribute \src "ls180.v:451.5-451.52" + wire \main_sdram_bankmachine0_cmd_buffer_source_first + attribute \src "ls180.v:452.5-452.51" + wire \main_sdram_bankmachine0_cmd_buffer_source_last + attribute \src "ls180.v:454.12-454.66" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr + attribute \src "ls180.v:453.5-453.57" + wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "ls180.v:450.6-450.53" + wire \main_sdram_bankmachine0_cmd_buffer_source_ready + attribute \src "ls180.v:449.5-449.52" + wire \main_sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "ls180.v:397.12-397.49" + wire width 13 \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:398.12-398.50" + wire width 2 \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:399.5-399.44" + wire \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:402.5-402.47" + wire \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:403.5-403.48" + wire \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:404.5-404.49" + wire \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:400.5-400.44" + wire \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:401.5-401.43" + wire \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:396.5-396.38" + wire \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:395.5-395.38" + wire \main_sdram_bankmachine0_cmd_valid + attribute \src "ls180.v:394.5-394.40" + wire \main_sdram_bankmachine0_refresh_gnt + attribute \src "ls180.v:393.6-393.41" + wire \main_sdram_bankmachine0_refresh_req + attribute \src "ls180.v:389.13-389.45" + wire width 22 \main_sdram_bankmachine0_req_addr + attribute \src "ls180.v:390.6-390.38" + wire \main_sdram_bankmachine0_req_lock + attribute \src "ls180.v:392.5-392.44" + wire \main_sdram_bankmachine0_req_rdata_valid + attribute \src "ls180.v:387.6-387.39" + wire \main_sdram_bankmachine0_req_ready + attribute \src "ls180.v:386.6-386.39" + wire \main_sdram_bankmachine0_req_valid + attribute \src "ls180.v:391.5-391.44" + wire \main_sdram_bankmachine0_req_wdata_ready + attribute \src "ls180.v:388.6-388.36" + wire \main_sdram_bankmachine0_req_we + attribute \src "ls180.v:455.12-455.39" + wire width 13 \main_sdram_bankmachine0_row + attribute \src "ls180.v:459.5-459.38" + wire \main_sdram_bankmachine0_row_close + attribute \src "ls180.v:460.5-460.47" + wire \main_sdram_bankmachine0_row_col_n_addr_sel + attribute \src "ls180.v:457.6-457.37" + wire \main_sdram_bankmachine0_row_hit + attribute \src "ls180.v:458.5-458.37" + wire \main_sdram_bankmachine0_row_open + attribute \src "ls180.v:456.5-456.39" + wire \main_sdram_bankmachine0_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:467.32-467.69" + wire \main_sdram_bankmachine0_trascon_ready + attribute \src "ls180.v:466.6-466.43" + wire \main_sdram_bankmachine0_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:465.32-465.68" + wire \main_sdram_bankmachine0_trccon_ready + attribute \src "ls180.v:464.6-464.42" + wire \main_sdram_bankmachine0_trccon_valid + attribute \src "ls180.v:463.11-463.48" + wire width 3 \main_sdram_bankmachine0_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:462.32-462.69" + wire \main_sdram_bankmachine0_twtpcon_ready + attribute \src "ls180.v:461.6-461.43" + wire \main_sdram_bankmachine0_twtpcon_valid + attribute \src "ls180.v:487.5-487.43" + wire \main_sdram_bankmachine1_auto_precharge + attribute \src "ls180.v:509.11-509.63" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + attribute \src "ls180.v:514.6-514.58" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:519.6-519.64" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:520.6-520.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:518.13-518.78" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:517.6-517.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:523.6-523.65" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:524.6-524.64" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:522.13-522.79" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:521.6-521.70" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:506.11-506.61" + wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level + attribute \src "ls180.v:508.11-508.63" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + attribute \src "ls180.v:515.12-515.67" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:516.13-516.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:507.5-507.57" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "ls180.v:490.5-490.60" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:491.5-491.59" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:493.13-493.75" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:492.6-492.66" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:489.6-489.61" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:488.6-488.61" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:496.6-496.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:497.6-497.62" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:499.13-499.77" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:498.6-498.68" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:495.6-495.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:494.6-494.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:504.13-504.71" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + attribute \src "ls180.v:505.13-505.72" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + attribute \src "ls180.v:502.6-502.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + attribute \src "ls180.v:503.6-503.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + attribute \src "ls180.v:500.6-500.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + attribute \src "ls180.v:501.6-501.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + attribute \src "ls180.v:510.11-510.66" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:511.13-511.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:513.13-513.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:512.6-512.60" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:527.6-527.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_first + attribute \src "ls180.v:528.6-528.50" + wire \main_sdram_bankmachine1_cmd_buffer_sink_last + attribute \src "ls180.v:530.13-530.65" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:529.6-529.56" + wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we + attribute \src "ls180.v:526.6-526.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_ready + attribute \src "ls180.v:525.6-525.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_valid + attribute \src "ls180.v:533.5-533.52" + wire \main_sdram_bankmachine1_cmd_buffer_source_first + attribute \src "ls180.v:534.5-534.51" + wire \main_sdram_bankmachine1_cmd_buffer_source_last + attribute \src "ls180.v:536.12-536.66" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr + attribute \src "ls180.v:535.5-535.57" + wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "ls180.v:532.6-532.53" + wire \main_sdram_bankmachine1_cmd_buffer_source_ready + attribute \src "ls180.v:531.5-531.52" + wire \main_sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "ls180.v:479.12-479.49" + wire width 13 \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:480.12-480.50" + wire width 2 \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:481.5-481.44" + wire \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:484.5-484.47" + wire \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:485.5-485.48" + wire \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:486.5-486.49" + wire \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:482.5-482.44" + wire \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:483.5-483.43" + wire \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:478.5-478.38" + wire \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:477.5-477.38" + wire \main_sdram_bankmachine1_cmd_valid + attribute \src "ls180.v:476.5-476.40" + wire \main_sdram_bankmachine1_refresh_gnt + attribute \src "ls180.v:475.6-475.41" + wire \main_sdram_bankmachine1_refresh_req + attribute \src "ls180.v:471.13-471.45" + wire width 22 \main_sdram_bankmachine1_req_addr + attribute \src "ls180.v:472.6-472.38" + wire \main_sdram_bankmachine1_req_lock + attribute \src "ls180.v:474.5-474.44" + wire \main_sdram_bankmachine1_req_rdata_valid + attribute \src "ls180.v:469.6-469.39" + wire \main_sdram_bankmachine1_req_ready + attribute \src "ls180.v:468.6-468.39" + wire \main_sdram_bankmachine1_req_valid + attribute \src "ls180.v:473.5-473.44" + wire \main_sdram_bankmachine1_req_wdata_ready + attribute \src "ls180.v:470.6-470.36" + wire \main_sdram_bankmachine1_req_we + attribute \src "ls180.v:537.12-537.39" + wire width 13 \main_sdram_bankmachine1_row + attribute \src "ls180.v:541.5-541.38" + wire \main_sdram_bankmachine1_row_close + attribute \src "ls180.v:542.5-542.47" + wire \main_sdram_bankmachine1_row_col_n_addr_sel + attribute \src "ls180.v:539.6-539.37" + wire \main_sdram_bankmachine1_row_hit + attribute \src "ls180.v:540.5-540.37" + wire \main_sdram_bankmachine1_row_open + attribute \src "ls180.v:538.5-538.39" + wire \main_sdram_bankmachine1_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:549.32-549.69" + wire \main_sdram_bankmachine1_trascon_ready + attribute \src "ls180.v:548.6-548.43" + wire \main_sdram_bankmachine1_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:547.32-547.68" + wire \main_sdram_bankmachine1_trccon_ready + attribute \src "ls180.v:546.6-546.42" + wire \main_sdram_bankmachine1_trccon_valid + attribute \src "ls180.v:545.11-545.48" + wire width 3 \main_sdram_bankmachine1_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:544.32-544.69" + wire \main_sdram_bankmachine1_twtpcon_ready + attribute \src "ls180.v:543.6-543.43" + wire \main_sdram_bankmachine1_twtpcon_valid + attribute \src "ls180.v:569.5-569.43" + wire \main_sdram_bankmachine2_auto_precharge + attribute \src "ls180.v:591.11-591.63" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + attribute \src "ls180.v:596.6-596.58" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:601.6-601.64" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:602.6-602.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:600.13-600.78" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:599.6-599.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:605.6-605.65" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:606.6-606.64" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:604.13-604.79" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:603.6-603.70" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:588.11-588.61" + wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level + attribute \src "ls180.v:590.11-590.63" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + attribute \src "ls180.v:597.12-597.67" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:598.13-598.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:589.5-589.57" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "ls180.v:572.5-572.60" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:573.5-573.59" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:575.13-575.75" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:574.6-574.66" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:571.6-571.61" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:570.6-570.61" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:578.6-578.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:579.6-579.62" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:581.13-581.77" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:580.6-580.68" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:577.6-577.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:576.6-576.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:586.13-586.71" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + attribute \src "ls180.v:587.13-587.72" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + attribute \src "ls180.v:584.6-584.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + attribute \src "ls180.v:585.6-585.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + attribute \src "ls180.v:582.6-582.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + attribute \src "ls180.v:583.6-583.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + attribute \src "ls180.v:592.11-592.66" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:593.13-593.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:595.13-595.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:594.6-594.60" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:609.6-609.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_first + attribute \src "ls180.v:610.6-610.50" + wire \main_sdram_bankmachine2_cmd_buffer_sink_last + attribute \src "ls180.v:612.13-612.65" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:611.6-611.56" + wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we + attribute \src "ls180.v:608.6-608.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_ready + attribute \src "ls180.v:607.6-607.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_valid + attribute \src "ls180.v:615.5-615.52" + wire \main_sdram_bankmachine2_cmd_buffer_source_first + attribute \src "ls180.v:616.5-616.51" + wire \main_sdram_bankmachine2_cmd_buffer_source_last + attribute \src "ls180.v:618.12-618.66" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr + attribute \src "ls180.v:617.5-617.57" + wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "ls180.v:614.6-614.53" + wire \main_sdram_bankmachine2_cmd_buffer_source_ready + attribute \src "ls180.v:613.5-613.52" + wire \main_sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "ls180.v:561.12-561.49" + wire width 13 \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:562.12-562.50" + wire width 2 \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:563.5-563.44" + wire \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:566.5-566.47" + wire \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:567.5-567.48" + wire \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:568.5-568.49" + wire \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:564.5-564.44" + wire \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:565.5-565.43" + wire \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:560.5-560.38" + wire \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:559.5-559.38" + wire \main_sdram_bankmachine2_cmd_valid + attribute \src "ls180.v:558.5-558.40" + wire \main_sdram_bankmachine2_refresh_gnt + attribute \src "ls180.v:557.6-557.41" + wire \main_sdram_bankmachine2_refresh_req + attribute \src "ls180.v:553.13-553.45" + wire width 22 \main_sdram_bankmachine2_req_addr + attribute \src "ls180.v:554.6-554.38" + wire \main_sdram_bankmachine2_req_lock + attribute \src "ls180.v:556.5-556.44" + wire \main_sdram_bankmachine2_req_rdata_valid + attribute \src "ls180.v:551.6-551.39" + wire \main_sdram_bankmachine2_req_ready + attribute \src "ls180.v:550.6-550.39" + wire \main_sdram_bankmachine2_req_valid + attribute \src "ls180.v:555.5-555.44" + wire \main_sdram_bankmachine2_req_wdata_ready + attribute \src "ls180.v:552.6-552.36" + wire \main_sdram_bankmachine2_req_we + attribute \src "ls180.v:619.12-619.39" + wire width 13 \main_sdram_bankmachine2_row + attribute \src "ls180.v:623.5-623.38" + wire \main_sdram_bankmachine2_row_close + attribute \src "ls180.v:624.5-624.47" + wire \main_sdram_bankmachine2_row_col_n_addr_sel + attribute \src "ls180.v:621.6-621.37" + wire \main_sdram_bankmachine2_row_hit + attribute \src "ls180.v:622.5-622.37" + wire \main_sdram_bankmachine2_row_open + attribute \src "ls180.v:620.5-620.39" + wire \main_sdram_bankmachine2_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:631.32-631.69" + wire \main_sdram_bankmachine2_trascon_ready + attribute \src "ls180.v:630.6-630.43" + wire \main_sdram_bankmachine2_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:629.32-629.68" + wire \main_sdram_bankmachine2_trccon_ready + attribute \src "ls180.v:628.6-628.42" + wire \main_sdram_bankmachine2_trccon_valid + attribute \src "ls180.v:627.11-627.48" + wire width 3 \main_sdram_bankmachine2_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:626.32-626.69" + wire \main_sdram_bankmachine2_twtpcon_ready + attribute \src "ls180.v:625.6-625.43" + wire \main_sdram_bankmachine2_twtpcon_valid + attribute \src "ls180.v:651.5-651.43" + wire \main_sdram_bankmachine3_auto_precharge + attribute \src "ls180.v:673.11-673.63" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + attribute \src "ls180.v:678.6-678.58" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:683.6-683.64" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:684.6-684.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:682.13-682.78" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:681.6-681.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:687.6-687.65" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:688.6-688.64" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:686.13-686.79" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:685.6-685.70" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:670.11-670.61" + wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level + attribute \src "ls180.v:672.11-672.63" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + attribute \src "ls180.v:679.12-679.67" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:680.13-680.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:671.5-671.57" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "ls180.v:654.5-654.60" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:655.5-655.59" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:657.13-657.75" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:656.6-656.66" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:653.6-653.61" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:652.6-652.61" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:660.6-660.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:661.6-661.62" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:663.13-663.77" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:662.6-662.68" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:659.6-659.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:658.6-658.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:668.13-668.71" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + attribute \src "ls180.v:669.13-669.72" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + attribute \src "ls180.v:666.6-666.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + attribute \src "ls180.v:667.6-667.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + attribute \src "ls180.v:664.6-664.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + attribute \src "ls180.v:665.6-665.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + attribute \src "ls180.v:674.11-674.66" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:675.13-675.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:677.13-677.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:676.6-676.60" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:691.6-691.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_first + attribute \src "ls180.v:692.6-692.50" + wire \main_sdram_bankmachine3_cmd_buffer_sink_last + attribute \src "ls180.v:694.13-694.65" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:693.6-693.56" + wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we + attribute \src "ls180.v:690.6-690.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_ready + attribute \src "ls180.v:689.6-689.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_valid + attribute \src "ls180.v:697.5-697.52" + wire \main_sdram_bankmachine3_cmd_buffer_source_first + attribute \src "ls180.v:698.5-698.51" + wire \main_sdram_bankmachine3_cmd_buffer_source_last + attribute \src "ls180.v:700.12-700.66" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr + attribute \src "ls180.v:699.5-699.57" + wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "ls180.v:696.6-696.53" + wire \main_sdram_bankmachine3_cmd_buffer_source_ready + attribute \src "ls180.v:695.5-695.52" + wire \main_sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "ls180.v:643.12-643.49" + wire width 13 \main_sdram_bankmachine3_cmd_payload_a + attribute \src "ls180.v:644.12-644.50" + wire width 2 \main_sdram_bankmachine3_cmd_payload_ba + attribute \src "ls180.v:645.5-645.44" + wire \main_sdram_bankmachine3_cmd_payload_cas + attribute \src "ls180.v:648.5-648.47" + wire \main_sdram_bankmachine3_cmd_payload_is_cmd + attribute \src "ls180.v:649.5-649.48" + wire \main_sdram_bankmachine3_cmd_payload_is_read + attribute \src "ls180.v:650.5-650.49" + wire \main_sdram_bankmachine3_cmd_payload_is_write + attribute \src "ls180.v:646.5-646.44" + wire \main_sdram_bankmachine3_cmd_payload_ras + attribute \src "ls180.v:647.5-647.43" + wire \main_sdram_bankmachine3_cmd_payload_we + attribute \src "ls180.v:642.5-642.38" + wire \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:641.5-641.38" + wire \main_sdram_bankmachine3_cmd_valid + attribute \src "ls180.v:640.5-640.40" + wire \main_sdram_bankmachine3_refresh_gnt + attribute \src "ls180.v:639.6-639.41" + wire \main_sdram_bankmachine3_refresh_req + attribute \src "ls180.v:635.13-635.45" + wire width 22 \main_sdram_bankmachine3_req_addr + attribute \src "ls180.v:636.6-636.38" + wire \main_sdram_bankmachine3_req_lock + attribute \src "ls180.v:638.5-638.44" + wire \main_sdram_bankmachine3_req_rdata_valid + attribute \src "ls180.v:633.6-633.39" + wire \main_sdram_bankmachine3_req_ready + attribute \src "ls180.v:632.6-632.39" + wire \main_sdram_bankmachine3_req_valid + attribute \src "ls180.v:637.5-637.44" + wire \main_sdram_bankmachine3_req_wdata_ready + attribute \src "ls180.v:634.6-634.36" + wire \main_sdram_bankmachine3_req_we + attribute \src "ls180.v:701.12-701.39" + wire width 13 \main_sdram_bankmachine3_row + attribute \src "ls180.v:705.5-705.38" + wire \main_sdram_bankmachine3_row_close + attribute \src "ls180.v:706.5-706.47" + wire \main_sdram_bankmachine3_row_col_n_addr_sel + attribute \src "ls180.v:703.6-703.37" + wire \main_sdram_bankmachine3_row_hit + attribute \src "ls180.v:704.5-704.37" + wire \main_sdram_bankmachine3_row_open + attribute \src "ls180.v:702.5-702.39" + wire \main_sdram_bankmachine3_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:713.32-713.69" + wire \main_sdram_bankmachine3_trascon_ready + attribute \src "ls180.v:712.6-712.43" + wire \main_sdram_bankmachine3_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:711.32-711.68" + wire \main_sdram_bankmachine3_trccon_ready + attribute \src "ls180.v:710.6-710.42" + wire \main_sdram_bankmachine3_trccon_valid + attribute \src "ls180.v:709.11-709.48" + wire width 3 \main_sdram_bankmachine3_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:708.32-708.69" + wire \main_sdram_bankmachine3_twtpcon_ready + attribute \src "ls180.v:707.6-707.43" + wire \main_sdram_bankmachine3_twtpcon_valid + attribute \src "ls180.v:715.6-715.28" + wire \main_sdram_cas_allowed + attribute \src "ls180.v:733.6-733.30" + wire \main_sdram_choose_cmd_ce + attribute \src "ls180.v:722.13-722.48" + wire width 13 \main_sdram_choose_cmd_cmd_payload_a + attribute \src "ls180.v:723.12-723.48" + wire width 2 \main_sdram_choose_cmd_cmd_payload_ba + attribute \src "ls180.v:724.5-724.42" + wire \main_sdram_choose_cmd_cmd_payload_cas + attribute \src "ls180.v:727.6-727.46" + wire \main_sdram_choose_cmd_cmd_payload_is_cmd + attribute \src "ls180.v:728.6-728.47" + wire \main_sdram_choose_cmd_cmd_payload_is_read + attribute \src "ls180.v:729.6-729.48" + wire \main_sdram_choose_cmd_cmd_payload_is_write + attribute \src "ls180.v:725.5-725.42" + wire \main_sdram_choose_cmd_cmd_payload_ras + attribute \src "ls180.v:726.5-726.41" + wire \main_sdram_choose_cmd_cmd_payload_we + attribute \src "ls180.v:721.5-721.36" + wire \main_sdram_choose_cmd_cmd_ready + attribute \src "ls180.v:720.6-720.37" + wire \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:732.11-732.38" + wire width 2 \main_sdram_choose_cmd_grant + attribute \src "ls180.v:731.12-731.41" + wire width 4 \main_sdram_choose_cmd_request + attribute \src "ls180.v:730.11-730.39" + wire width 4 \main_sdram_choose_cmd_valids + attribute \src "ls180.v:719.5-719.41" + wire \main_sdram_choose_cmd_want_activates + attribute \src "ls180.v:718.5-718.36" + wire \main_sdram_choose_cmd_want_cmds + attribute \src "ls180.v:716.5-716.37" + wire \main_sdram_choose_cmd_want_reads + attribute \src "ls180.v:717.5-717.38" + wire \main_sdram_choose_cmd_want_writes + attribute \src "ls180.v:751.6-751.30" + wire \main_sdram_choose_req_ce + attribute \src "ls180.v:740.13-740.48" + wire width 13 \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:741.12-741.48" + wire width 2 \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:742.5-742.42" + wire \main_sdram_choose_req_cmd_payload_cas + attribute \src "ls180.v:745.6-745.46" + wire \main_sdram_choose_req_cmd_payload_is_cmd + attribute \src "ls180.v:746.6-746.47" + wire \main_sdram_choose_req_cmd_payload_is_read + attribute \src "ls180.v:747.6-747.48" + wire \main_sdram_choose_req_cmd_payload_is_write + attribute \src "ls180.v:743.5-743.42" + wire \main_sdram_choose_req_cmd_payload_ras + attribute \src "ls180.v:744.5-744.41" + wire \main_sdram_choose_req_cmd_payload_we + attribute \src "ls180.v:739.5-739.36" + wire \main_sdram_choose_req_cmd_ready + attribute \src "ls180.v:738.6-738.37" + wire \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:750.11-750.38" + wire width 2 \main_sdram_choose_req_grant + attribute \src "ls180.v:749.12-749.41" + wire width 4 \main_sdram_choose_req_request + attribute \src "ls180.v:748.11-748.39" + wire width 4 \main_sdram_choose_req_valids + attribute \src "ls180.v:737.5-737.41" + wire \main_sdram_choose_req_want_activates + attribute \src "ls180.v:736.6-736.37" + wire \main_sdram_choose_req_want_cmds + attribute \src "ls180.v:734.5-734.37" + wire \main_sdram_choose_req_want_reads + attribute \src "ls180.v:735.5-735.38" + wire \main_sdram_choose_req_want_writes + attribute \src "ls180.v:295.6-295.20" + wire \main_sdram_cke + attribute \src "ls180.v:363.5-363.24" + wire \main_sdram_cmd_last + attribute \src "ls180.v:364.12-364.36" + wire width 13 \main_sdram_cmd_payload_a + attribute \src "ls180.v:365.11-365.36" + wire width 2 \main_sdram_cmd_payload_ba + attribute \src "ls180.v:366.5-366.31" + wire \main_sdram_cmd_payload_cas + attribute \src "ls180.v:369.5-369.35" + wire \main_sdram_cmd_payload_is_read + attribute \src "ls180.v:370.5-370.36" + wire \main_sdram_cmd_payload_is_write + attribute \src "ls180.v:367.5-367.31" + wire \main_sdram_cmd_payload_ras + attribute \src "ls180.v:368.5-368.30" + wire \main_sdram_cmd_payload_we + attribute \src "ls180.v:362.5-362.25" + wire \main_sdram_cmd_ready + attribute \src "ls180.v:361.5-361.25" + wire \main_sdram_cmd_valid + attribute \src "ls180.v:303.6-303.32" + wire \main_sdram_command_issue_r + attribute \src "ls180.v:302.6-302.33" + wire \main_sdram_command_issue_re + attribute \src "ls180.v:305.5-305.31" + wire \main_sdram_command_issue_w + attribute \src "ls180.v:304.6-304.33" + wire \main_sdram_command_issue_we + attribute \src "ls180.v:301.5-301.26" + wire \main_sdram_command_re + attribute \src "ls180.v:300.11-300.37" + wire width 6 \main_sdram_command_storage + attribute \src "ls180.v:354.5-354.28" + wire \main_sdram_dfi_p0_act_n + attribute \src "ls180.v:345.12-345.37" + wire width 13 \main_sdram_dfi_p0_address + attribute \src "ls180.v:346.11-346.33" + wire width 2 \main_sdram_dfi_p0_bank + attribute \src "ls180.v:347.5-347.28" + wire \main_sdram_dfi_p0_cas_n + attribute \src "ls180.v:351.6-351.27" + wire \main_sdram_dfi_p0_cke + attribute \src "ls180.v:348.5-348.27" + wire \main_sdram_dfi_p0_cs_n + attribute \src "ls180.v:352.6-352.27" + wire \main_sdram_dfi_p0_odt + attribute \src "ls180.v:349.5-349.28" + wire \main_sdram_dfi_p0_ras_n + attribute \src "ls180.v:359.13-359.37" + wire width 16 \main_sdram_dfi_p0_rddata + attribute \src "ls180.v:358.5-358.32" + wire \main_sdram_dfi_p0_rddata_en + attribute \src "ls180.v:360.6-360.36" + wire \main_sdram_dfi_p0_rddata_valid + attribute \src "ls180.v:353.6-353.31" + wire \main_sdram_dfi_p0_reset_n + attribute \src "ls180.v:350.5-350.27" + wire \main_sdram_dfi_p0_we_n + attribute \src "ls180.v:355.13-355.37" + wire width 16 \main_sdram_dfi_p0_wrdata + attribute \src "ls180.v:356.5-356.32" + wire \main_sdram_dfi_p0_wrdata_en + attribute \src "ls180.v:357.12-357.41" + wire width 2 \main_sdram_dfi_p0_wrdata_mask + attribute \src "ls180.v:769.5-769.19" + wire \main_sdram_en0 + attribute \src "ls180.v:772.5-772.19" + wire \main_sdram_en1 + attribute \src "ls180.v:775.6-775.30" + wire \main_sdram_go_to_refresh + attribute \src "ls180.v:317.13-317.44" + wire width 22 \main_sdram_interface_bank0_addr + attribute \src "ls180.v:318.6-318.37" + wire \main_sdram_interface_bank0_lock + attribute \src "ls180.v:320.6-320.44" + wire \main_sdram_interface_bank0_rdata_valid + attribute \src "ls180.v:315.6-315.38" + wire \main_sdram_interface_bank0_ready + attribute \src "ls180.v:314.6-314.38" + wire \main_sdram_interface_bank0_valid + attribute \src "ls180.v:319.6-319.44" + wire \main_sdram_interface_bank0_wdata_ready + attribute \src "ls180.v:316.6-316.35" + wire \main_sdram_interface_bank0_we + attribute \src "ls180.v:324.13-324.44" + wire width 22 \main_sdram_interface_bank1_addr + attribute \src "ls180.v:325.6-325.37" + wire \main_sdram_interface_bank1_lock + attribute \src "ls180.v:327.6-327.44" + wire \main_sdram_interface_bank1_rdata_valid + attribute \src "ls180.v:322.6-322.38" + wire \main_sdram_interface_bank1_ready + attribute \src "ls180.v:321.6-321.38" + wire \main_sdram_interface_bank1_valid + attribute \src "ls180.v:326.6-326.44" + wire \main_sdram_interface_bank1_wdata_ready + attribute \src "ls180.v:323.6-323.35" + wire \main_sdram_interface_bank1_we + attribute \src "ls180.v:331.13-331.44" + wire width 22 \main_sdram_interface_bank2_addr + attribute \src "ls180.v:332.6-332.37" + wire \main_sdram_interface_bank2_lock + attribute \src "ls180.v:334.6-334.44" + wire \main_sdram_interface_bank2_rdata_valid + attribute \src "ls180.v:329.6-329.38" + wire \main_sdram_interface_bank2_ready + attribute \src "ls180.v:328.6-328.38" + wire \main_sdram_interface_bank2_valid + attribute \src "ls180.v:333.6-333.44" + wire \main_sdram_interface_bank2_wdata_ready + attribute \src "ls180.v:330.6-330.35" + wire \main_sdram_interface_bank2_we + attribute \src "ls180.v:338.13-338.44" + wire width 22 \main_sdram_interface_bank3_addr + attribute \src "ls180.v:339.6-339.37" + wire \main_sdram_interface_bank3_lock + attribute \src "ls180.v:341.6-341.44" + wire \main_sdram_interface_bank3_rdata_valid + attribute \src "ls180.v:336.6-336.38" + wire \main_sdram_interface_bank3_ready + attribute \src "ls180.v:335.6-335.38" + wire \main_sdram_interface_bank3_valid + attribute \src "ls180.v:340.6-340.44" + wire \main_sdram_interface_bank3_wdata_ready + attribute \src "ls180.v:337.6-337.35" + wire \main_sdram_interface_bank3_we + attribute \src "ls180.v:344.13-344.39" + wire width 16 \main_sdram_interface_rdata + attribute \src "ls180.v:342.12-342.38" + wire width 16 \main_sdram_interface_wdata + attribute \src "ls180.v:343.11-343.40" + wire width 2 \main_sdram_interface_wdata_we + attribute \src "ls180.v:255.5-255.29" + wire \main_sdram_inti_p0_act_n + attribute \src "ls180.v:246.13-246.39" + wire width 13 \main_sdram_inti_p0_address + attribute \src "ls180.v:247.12-247.35" + wire width 2 \main_sdram_inti_p0_bank + attribute \src "ls180.v:248.5-248.29" + wire \main_sdram_inti_p0_cas_n + attribute \src "ls180.v:252.6-252.28" + wire \main_sdram_inti_p0_cke + attribute \src "ls180.v:249.5-249.28" + wire \main_sdram_inti_p0_cs_n + attribute \src "ls180.v:253.6-253.28" + wire \main_sdram_inti_p0_odt + attribute \src "ls180.v:250.5-250.29" + wire \main_sdram_inti_p0_ras_n + attribute \src "ls180.v:260.12-260.37" + wire width 16 \main_sdram_inti_p0_rddata + attribute \src "ls180.v:259.6-259.34" + wire \main_sdram_inti_p0_rddata_en + attribute \src "ls180.v:261.5-261.36" + wire \main_sdram_inti_p0_rddata_valid + attribute \src "ls180.v:254.6-254.32" + wire \main_sdram_inti_p0_reset_n + attribute \src "ls180.v:251.5-251.28" + wire \main_sdram_inti_p0_we_n + attribute \src "ls180.v:256.13-256.38" + wire width 16 \main_sdram_inti_p0_wrdata + attribute \src "ls180.v:257.6-257.34" + wire \main_sdram_inti_p0_wrdata_en + attribute \src "ls180.v:258.12-258.42" + wire width 2 \main_sdram_inti_p0_wrdata_mask + attribute \src "ls180.v:287.5-287.31" + wire \main_sdram_master_p0_act_n + attribute \src "ls180.v:278.12-278.40" + wire width 13 \main_sdram_master_p0_address + attribute \src "ls180.v:279.11-279.36" + wire width 2 \main_sdram_master_p0_bank + attribute \src "ls180.v:280.5-280.31" + wire \main_sdram_master_p0_cas_n + attribute \src "ls180.v:284.5-284.29" + wire \main_sdram_master_p0_cke + attribute \src "ls180.v:281.5-281.30" + wire \main_sdram_master_p0_cs_n + attribute \src "ls180.v:285.5-285.29" + wire \main_sdram_master_p0_odt + attribute \src "ls180.v:282.5-282.31" + wire \main_sdram_master_p0_ras_n + attribute \src "ls180.v:292.13-292.40" + wire width 16 \main_sdram_master_p0_rddata + attribute \src "ls180.v:291.5-291.35" + wire \main_sdram_master_p0_rddata_en + attribute \src "ls180.v:293.6-293.39" + wire \main_sdram_master_p0_rddata_valid + attribute \src "ls180.v:286.5-286.33" + wire \main_sdram_master_p0_reset_n + attribute \src "ls180.v:283.5-283.30" + wire \main_sdram_master_p0_we_n + attribute \src "ls180.v:288.12-288.39" + wire width 16 \main_sdram_master_p0_wrdata + attribute \src "ls180.v:289.5-289.35" + wire \main_sdram_master_p0_wrdata_en + attribute \src "ls180.v:290.11-290.43" + wire width 2 \main_sdram_master_p0_wrdata_mask + attribute \src "ls180.v:770.6-770.26" + wire \main_sdram_max_time0 + attribute \src "ls180.v:773.6-773.26" + wire \main_sdram_max_time1 + attribute \src "ls180.v:752.12-752.28" + wire width 13 \main_sdram_nop_a + attribute \src "ls180.v:753.11-753.28" + wire width 2 \main_sdram_nop_ba + attribute \src "ls180.v:296.6-296.20" + wire \main_sdram_odt + attribute \src "ls180.v:379.5-379.31" + wire \main_sdram_postponer_count + attribute \src "ls180.v:377.6-377.32" + wire \main_sdram_postponer_req_i + attribute \src "ls180.v:378.5-378.31" + wire \main_sdram_postponer_req_o + attribute \src "ls180.v:714.6-714.28" + wire \main_sdram_ras_allowed + attribute \src "ls180.v:299.5-299.18" + wire \main_sdram_re + attribute \src "ls180.v:767.6-767.31" + wire \main_sdram_read_available + attribute \src "ls180.v:297.6-297.24" + wire \main_sdram_reset_n + attribute \src "ls180.v:294.6-294.20" + wire \main_sdram_sel + attribute \src "ls180.v:385.5-385.31" + wire \main_sdram_sequencer_count + attribute \src "ls180.v:384.11-384.39" + wire width 4 \main_sdram_sequencer_counter + attribute \src "ls180.v:381.6-381.32" + wire \main_sdram_sequencer_done0 + attribute \src "ls180.v:383.5-383.31" + wire \main_sdram_sequencer_done1 + attribute \src "ls180.v:380.5-380.32" + wire \main_sdram_sequencer_start0 + attribute \src "ls180.v:382.6-382.33" + wire \main_sdram_sequencer_start1 + attribute \src "ls180.v:271.6-271.31" + wire \main_sdram_slave_p0_act_n + attribute \src "ls180.v:262.13-262.40" + wire width 13 \main_sdram_slave_p0_address + attribute \src "ls180.v:263.12-263.36" + wire width 2 \main_sdram_slave_p0_bank + attribute \src "ls180.v:264.6-264.31" + wire \main_sdram_slave_p0_cas_n + attribute \src "ls180.v:268.6-268.29" + wire \main_sdram_slave_p0_cke + attribute \src "ls180.v:265.6-265.30" + wire \main_sdram_slave_p0_cs_n + attribute \src "ls180.v:269.6-269.29" + wire \main_sdram_slave_p0_odt + attribute \src "ls180.v:266.6-266.31" + wire \main_sdram_slave_p0_ras_n + attribute \src "ls180.v:276.12-276.38" + wire width 16 \main_sdram_slave_p0_rddata + attribute \src "ls180.v:275.6-275.35" + wire \main_sdram_slave_p0_rddata_en + attribute \src "ls180.v:277.5-277.37" + wire \main_sdram_slave_p0_rddata_valid + attribute \src "ls180.v:270.6-270.33" + wire \main_sdram_slave_p0_reset_n + attribute \src "ls180.v:267.6-267.30" + wire \main_sdram_slave_p0_we_n + attribute \src "ls180.v:272.13-272.39" + wire width 16 \main_sdram_slave_p0_wrdata + attribute \src "ls180.v:273.6-273.35" + wire \main_sdram_slave_p0_wrdata_en + attribute \src "ls180.v:274.12-274.43" + wire width 2 \main_sdram_slave_p0_wrdata_mask + attribute \src "ls180.v:312.12-312.29" + wire width 16 \main_sdram_status + attribute \src "ls180.v:755.5-755.24" + wire \main_sdram_steerer0 + attribute \src "ls180.v:756.5-756.24" + wire \main_sdram_steerer1 + attribute \src "ls180.v:754.11-754.33" + wire width 2 \main_sdram_steerer_sel + attribute \src "ls180.v:298.11-298.29" + wire width 4 \main_sdram_storage + attribute \src "ls180.v:763.5-763.29" + wire \main_sdram_tccdcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:762.32-762.56" + wire \main_sdram_tccdcon_ready + attribute \src "ls180.v:761.6-761.30" + wire \main_sdram_tccdcon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:760.32-760.56" + wire \main_sdram_tfawcon_ready + attribute \src "ls180.v:759.6-759.30" + wire \main_sdram_tfawcon_valid + attribute \src "ls180.v:771.11-771.27" + wire width 5 \main_sdram_time0 + attribute \src "ls180.v:774.11-774.27" + wire width 4 \main_sdram_time1 + attribute \src "ls180.v:374.12-374.35" + wire width 10 \main_sdram_timer_count0 + attribute \src "ls180.v:376.11-376.34" + wire width 10 \main_sdram_timer_count1 + attribute \src "ls180.v:373.6-373.28" + wire \main_sdram_timer_done0 + attribute \src "ls180.v:375.6-375.28" + wire \main_sdram_timer_done1 + attribute \src "ls180.v:372.6-372.27" + wire \main_sdram_timer_wait + attribute \no_retiming "true" + attribute \src "ls180.v:758.32-758.56" + wire \main_sdram_trrdcon_ready + attribute \src "ls180.v:757.6-757.30" + wire \main_sdram_trrdcon_valid + attribute \src "ls180.v:766.11-766.35" + wire width 3 \main_sdram_twtrcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:765.32-765.56" + wire \main_sdram_twtrcon_ready + attribute \src "ls180.v:764.6-764.30" + wire \main_sdram_twtrcon_valid + attribute \src "ls180.v:371.6-371.30" + wire \main_sdram_wants_refresh + attribute \src "ls180.v:313.6-313.19" + wire \main_sdram_we + attribute \src "ls180.v:311.5-311.25" + wire \main_sdram_wrdata_re + attribute \src "ls180.v:310.12-310.37" + wire width 16 \main_sdram_wrdata_storage + attribute \src "ls180.v:768.6-768.32" + wire \main_sdram_write_available + attribute \src "ls180.v:976.12-976.40" + wire width 16 \main_spi_master_clk_divider0 + attribute \src "ls180.v:998.12-998.40" + wire width 16 \main_spi_master_clk_divider1 + attribute \src "ls180.v:993.5-993.31" + wire \main_spi_master_clk_enable + attribute \src "ls180.v:1000.6-1000.30" + wire \main_spi_master_clk_fall + attribute \src "ls180.v:999.6-999.30" + wire \main_spi_master_clk_rise + attribute \src "ls180.v:980.5-980.31" + wire \main_spi_master_control_re + attribute \src "ls180.v:979.12-979.43" + wire width 16 \main_spi_master_control_storage + attribute \src "ls180.v:995.11-995.32" + wire width 3 \main_spi_master_count + attribute \src "ls180.v:1761.11-1761.54" + wire width 3 \main_spi_master_count_spimaster0_next_value + attribute \src "ls180.v:1762.5-1762.51" + wire \main_spi_master_count_spimaster0_next_value_ce + attribute \src "ls180.v:974.6-974.24" + wire \main_spi_master_cs + attribute \src "ls180.v:994.5-994.30" + wire \main_spi_master_cs_enable + attribute \src "ls180.v:990.5-990.26" + wire \main_spi_master_cs_re + attribute \src "ls180.v:989.5-989.31" + wire \main_spi_master_cs_storage + attribute \src "ls180.v:970.5-970.26" + wire \main_spi_master_done0 + attribute \src "ls180.v:981.6-981.27" + wire \main_spi_master_done1 + attribute \src "ls180.v:971.5-971.24" + wire \main_spi_master_irq + attribute \src "ls180.v:969.12-969.35" + wire width 8 \main_spi_master_length0 + attribute \src "ls180.v:978.12-978.35" + wire width 8 \main_spi_master_length1 + attribute \src "ls180.v:975.6-975.30" + wire \main_spi_master_loopback + attribute \src "ls180.v:992.5-992.32" + wire \main_spi_master_loopback_re + attribute \src "ls180.v:991.5-991.37" + wire \main_spi_master_loopback_storage + attribute \src "ls180.v:973.11-973.31" + wire width 8 \main_spi_master_miso + attribute \src "ls180.v:1003.11-1003.36" + wire width 8 \main_spi_master_miso_data + attribute \src "ls180.v:997.5-997.31" + wire \main_spi_master_miso_latch + attribute \src "ls180.v:986.12-986.39" + wire width 8 \main_spi_master_miso_status + attribute \src "ls180.v:987.6-987.29" + wire \main_spi_master_miso_we + attribute \src "ls180.v:972.12-972.32" + wire width 8 \main_spi_master_mosi + attribute \src "ls180.v:1001.11-1001.36" + wire width 8 \main_spi_master_mosi_data + attribute \src "ls180.v:996.5-996.31" + wire \main_spi_master_mosi_latch + attribute \src "ls180.v:985.5-985.28" + wire \main_spi_master_mosi_re + attribute \src "ls180.v:1002.11-1002.35" + wire width 3 \main_spi_master_mosi_sel + attribute \src "ls180.v:984.11-984.39" + wire width 8 \main_spi_master_mosi_storage + attribute \src "ls180.v:988.6-988.25" + wire \main_spi_master_sel + attribute \src "ls180.v:968.6-968.28" + wire \main_spi_master_start0 + attribute \src "ls180.v:977.5-977.27" + wire \main_spi_master_start1 + attribute \src "ls180.v:982.6-982.35" + wire \main_spi_master_status_status + attribute \src "ls180.v:983.6-983.31" + wire \main_spi_master_status_we + attribute \src "ls180.v:865.12-865.44" + wire width 2 \main_uart_eventmanager_pending_r + attribute \src "ls180.v:864.6-864.39" + wire \main_uart_eventmanager_pending_re + attribute \src "ls180.v:867.11-867.43" + wire width 2 \main_uart_eventmanager_pending_w + attribute \src "ls180.v:866.6-866.39" + wire \main_uart_eventmanager_pending_we + attribute \src "ls180.v:869.5-869.30" + wire \main_uart_eventmanager_re + attribute \src "ls180.v:861.12-861.43" + wire width 2 \main_uart_eventmanager_status_r + attribute \src "ls180.v:860.6-860.38" + wire \main_uart_eventmanager_status_re + attribute \src "ls180.v:863.11-863.42" + wire width 2 \main_uart_eventmanager_status_w + attribute \src "ls180.v:862.6-862.38" + wire \main_uart_eventmanager_status_we + attribute \src "ls180.v:868.11-868.41" + wire width 2 \main_uart_eventmanager_storage + attribute \src "ls180.v:849.6-849.19" + wire \main_uart_irq + attribute \src "ls180.v:835.12-835.46" + wire width 32 \main_uart_phy_phase_accumulator_rx + attribute \src "ls180.v:825.12-825.46" + wire width 32 \main_uart_phy_phase_accumulator_tx + attribute \src "ls180.v:818.5-818.21" + wire \main_uart_phy_re + attribute \src "ls180.v:836.6-836.22" + wire \main_uart_phy_rx + attribute \src "ls180.v:839.11-839.36" + wire width 4 \main_uart_phy_rx_bitcount + attribute \src "ls180.v:840.5-840.26" + wire \main_uart_phy_rx_busy + attribute \src "ls180.v:837.5-837.23" + wire \main_uart_phy_rx_r + attribute \src "ls180.v:838.11-838.31" + wire width 8 \main_uart_phy_rx_reg + attribute \src "ls180.v:821.6-821.30" + wire \main_uart_phy_sink_first + attribute \src "ls180.v:822.6-822.29" + wire \main_uart_phy_sink_last + attribute \src "ls180.v:823.12-823.43" + wire width 8 \main_uart_phy_sink_payload_data + attribute \src "ls180.v:820.5-820.29" + wire \main_uart_phy_sink_ready + attribute \src "ls180.v:819.6-819.30" + wire \main_uart_phy_sink_valid + attribute \src "ls180.v:831.5-831.31" + wire \main_uart_phy_source_first + attribute \src "ls180.v:832.5-832.30" + wire \main_uart_phy_source_last + attribute \src "ls180.v:833.11-833.44" + wire width 8 \main_uart_phy_source_payload_data + attribute \src "ls180.v:830.6-830.32" + wire \main_uart_phy_source_ready + attribute \src "ls180.v:829.5-829.31" + wire \main_uart_phy_source_valid + attribute \src "ls180.v:817.12-817.33" + wire width 32 \main_uart_phy_storage + attribute \src "ls180.v:827.11-827.36" + wire width 4 \main_uart_phy_tx_bitcount + attribute \src "ls180.v:828.5-828.26" + wire \main_uart_phy_tx_busy + attribute \src "ls180.v:826.11-826.31" + wire width 8 \main_uart_phy_tx_reg + attribute \src "ls180.v:834.5-834.32" + wire \main_uart_phy_uart_clk_rxen + attribute \src "ls180.v:824.5-824.32" + wire \main_uart_phy_uart_clk_txen + attribute \src "ls180.v:958.5-958.20" + wire \main_uart_reset + attribute \src "ls180.v:858.5-858.23" + wire \main_uart_rx_clear + attribute \src "ls180.v:942.11-942.36" + wire width 4 \main_uart_rx_fifo_consume + attribute \src "ls180.v:947.6-947.31" + wire \main_uart_rx_fifo_do_read + attribute \src "ls180.v:953.6-953.37" + wire \main_uart_rx_fifo_fifo_in_first + attribute \src "ls180.v:954.6-954.36" + wire \main_uart_rx_fifo_fifo_in_last + attribute \src "ls180.v:952.12-952.50" + wire width 8 \main_uart_rx_fifo_fifo_in_payload_data + attribute \src "ls180.v:956.6-956.38" + wire \main_uart_rx_fifo_fifo_out_first + attribute \src "ls180.v:957.6-957.37" + wire \main_uart_rx_fifo_fifo_out_last + attribute \src "ls180.v:955.12-955.51" + wire width 8 \main_uart_rx_fifo_fifo_out_payload_data + attribute \src "ls180.v:939.11-939.35" + wire width 5 \main_uart_rx_fifo_level0 + attribute \src "ls180.v:951.12-951.36" + wire width 5 \main_uart_rx_fifo_level1 + attribute \src "ls180.v:941.11-941.36" + wire width 4 \main_uart_rx_fifo_produce + attribute \src "ls180.v:948.12-948.40" + wire width 4 \main_uart_rx_fifo_rdport_adr + attribute \src "ls180.v:949.12-949.42" + wire width 10 \main_uart_rx_fifo_rdport_dat_r + attribute \src "ls180.v:950.6-950.33" + wire \main_uart_rx_fifo_rdport_re + attribute \src "ls180.v:931.6-931.26" + wire \main_uart_rx_fifo_re + attribute \src "ls180.v:932.5-932.31" + wire \main_uart_rx_fifo_readable + attribute \src "ls180.v:940.5-940.30" + wire \main_uart_rx_fifo_replace + attribute \src "ls180.v:923.6-923.34" + wire \main_uart_rx_fifo_sink_first + attribute \src "ls180.v:924.6-924.33" + wire \main_uart_rx_fifo_sink_last + attribute \src "ls180.v:925.12-925.47" + wire width 8 \main_uart_rx_fifo_sink_payload_data + attribute \src "ls180.v:922.6-922.34" + wire \main_uart_rx_fifo_sink_ready + attribute \src "ls180.v:921.6-921.34" + wire \main_uart_rx_fifo_sink_valid + attribute \src "ls180.v:928.6-928.36" + wire \main_uart_rx_fifo_source_first + attribute \src "ls180.v:929.6-929.35" + wire \main_uart_rx_fifo_source_last + attribute \src "ls180.v:930.12-930.49" + wire width 8 \main_uart_rx_fifo_source_payload_data + attribute \src "ls180.v:927.6-927.36" + wire \main_uart_rx_fifo_source_ready + attribute \src "ls180.v:926.6-926.36" + wire \main_uart_rx_fifo_source_valid + attribute \src "ls180.v:937.12-937.42" + wire width 10 \main_uart_rx_fifo_syncfifo_din + attribute \src "ls180.v:938.12-938.43" + wire width 10 \main_uart_rx_fifo_syncfifo_dout + attribute \src "ls180.v:935.6-935.35" + wire \main_uart_rx_fifo_syncfifo_re + attribute \src "ls180.v:936.6-936.41" + wire \main_uart_rx_fifo_syncfifo_readable + attribute \src "ls180.v:933.6-933.35" + wire \main_uart_rx_fifo_syncfifo_we + attribute \src "ls180.v:934.6-934.41" + wire \main_uart_rx_fifo_syncfifo_writable + attribute \src "ls180.v:943.11-943.39" + wire width 4 \main_uart_rx_fifo_wrport_adr + attribute \src "ls180.v:944.12-944.42" + wire width 10 \main_uart_rx_fifo_wrport_dat_r + attribute \src "ls180.v:946.12-946.42" + wire width 10 \main_uart_rx_fifo_wrport_dat_w + attribute \src "ls180.v:945.6-945.33" + wire \main_uart_rx_fifo_wrport_we + attribute \src "ls180.v:859.5-859.29" + wire \main_uart_rx_old_trigger + attribute \src "ls180.v:856.5-856.25" + wire \main_uart_rx_pending + attribute \src "ls180.v:855.6-855.25" + wire \main_uart_rx_status + attribute \src "ls180.v:857.6-857.26" + wire \main_uart_rx_trigger + attribute \src "ls180.v:847.6-847.30" + wire \main_uart_rxempty_status + attribute \src "ls180.v:848.6-848.26" + wire \main_uart_rxempty_we + attribute \src "ls180.v:872.6-872.29" + wire \main_uart_rxfull_status + attribute \src "ls180.v:873.6-873.25" + wire \main_uart_rxfull_we + attribute \src "ls180.v:842.12-842.28" + wire width 8 \main_uart_rxtx_r + attribute \src "ls180.v:841.6-841.23" + wire \main_uart_rxtx_re + attribute \src "ls180.v:844.12-844.28" + wire width 8 \main_uart_rxtx_w + attribute \src "ls180.v:843.6-843.23" + wire \main_uart_rxtx_we + attribute \src "ls180.v:853.5-853.23" + wire \main_uart_tx_clear + attribute \src "ls180.v:905.11-905.36" + wire width 4 \main_uart_tx_fifo_consume + attribute \src "ls180.v:910.6-910.31" + wire \main_uart_tx_fifo_do_read + attribute \src "ls180.v:916.6-916.37" + wire \main_uart_tx_fifo_fifo_in_first + attribute \src "ls180.v:917.6-917.36" + wire \main_uart_tx_fifo_fifo_in_last + attribute \src "ls180.v:915.12-915.50" + wire width 8 \main_uart_tx_fifo_fifo_in_payload_data + attribute \src "ls180.v:919.6-919.38" + wire \main_uart_tx_fifo_fifo_out_first + attribute \src "ls180.v:920.6-920.37" + wire \main_uart_tx_fifo_fifo_out_last + attribute \src "ls180.v:918.12-918.51" + wire width 8 \main_uart_tx_fifo_fifo_out_payload_data + attribute \src "ls180.v:902.11-902.35" + wire width 5 \main_uart_tx_fifo_level0 + attribute \src "ls180.v:914.12-914.36" + wire width 5 \main_uart_tx_fifo_level1 + attribute \src "ls180.v:904.11-904.36" + wire width 4 \main_uart_tx_fifo_produce + attribute \src "ls180.v:911.12-911.40" + wire width 4 \main_uart_tx_fifo_rdport_adr + attribute \src "ls180.v:912.12-912.42" + wire width 10 \main_uart_tx_fifo_rdport_dat_r + attribute \src "ls180.v:913.6-913.33" + wire \main_uart_tx_fifo_rdport_re + attribute \src "ls180.v:894.6-894.26" + wire \main_uart_tx_fifo_re + attribute \src "ls180.v:895.5-895.31" + wire \main_uart_tx_fifo_readable + attribute \src "ls180.v:903.5-903.30" + wire \main_uart_tx_fifo_replace + attribute \src "ls180.v:886.5-886.33" + wire \main_uart_tx_fifo_sink_first + attribute \src "ls180.v:887.5-887.32" + wire \main_uart_tx_fifo_sink_last + attribute \src "ls180.v:888.12-888.47" + wire width 8 \main_uart_tx_fifo_sink_payload_data + attribute \src "ls180.v:885.6-885.34" + wire \main_uart_tx_fifo_sink_ready + attribute \src "ls180.v:884.6-884.34" + wire \main_uart_tx_fifo_sink_valid + attribute \src "ls180.v:891.6-891.36" + wire \main_uart_tx_fifo_source_first + attribute \src "ls180.v:892.6-892.35" + wire \main_uart_tx_fifo_source_last + attribute \src "ls180.v:893.12-893.49" + wire width 8 \main_uart_tx_fifo_source_payload_data + attribute \src "ls180.v:890.6-890.36" + wire \main_uart_tx_fifo_source_ready + attribute \src "ls180.v:889.6-889.36" + wire \main_uart_tx_fifo_source_valid + attribute \src "ls180.v:900.12-900.42" + wire width 10 \main_uart_tx_fifo_syncfifo_din + attribute \src "ls180.v:901.12-901.43" + wire width 10 \main_uart_tx_fifo_syncfifo_dout + attribute \src "ls180.v:898.6-898.35" + wire \main_uart_tx_fifo_syncfifo_re + attribute \src "ls180.v:899.6-899.41" + wire \main_uart_tx_fifo_syncfifo_readable + attribute \src "ls180.v:896.6-896.35" + wire \main_uart_tx_fifo_syncfifo_we + attribute \src "ls180.v:897.6-897.41" + wire \main_uart_tx_fifo_syncfifo_writable + attribute \src "ls180.v:906.11-906.39" + wire width 4 \main_uart_tx_fifo_wrport_adr + attribute \src "ls180.v:907.12-907.42" + wire width 10 \main_uart_tx_fifo_wrport_dat_r + attribute \src "ls180.v:909.12-909.42" + wire width 10 \main_uart_tx_fifo_wrport_dat_w + attribute \src "ls180.v:908.6-908.33" + wire \main_uart_tx_fifo_wrport_we + attribute \src "ls180.v:854.5-854.29" + wire \main_uart_tx_old_trigger + attribute \src "ls180.v:851.5-851.25" + wire \main_uart_tx_pending + attribute \src "ls180.v:850.6-850.25" + wire \main_uart_tx_status + attribute \src "ls180.v:852.6-852.26" + wire \main_uart_tx_trigger + attribute \src "ls180.v:870.6-870.30" + wire \main_uart_txempty_status + attribute \src "ls180.v:871.6-871.26" + wire \main_uart_txempty_we + attribute \src "ls180.v:845.6-845.29" + wire \main_uart_txfull_status + attribute \src "ls180.v:846.6-846.25" + wire \main_uart_txfull_we + attribute \src "ls180.v:876.6-876.31" + wire \main_uart_uart_sink_first + attribute \src "ls180.v:877.6-877.30" + wire \main_uart_uart_sink_last + attribute \src "ls180.v:878.12-878.44" + wire width 8 \main_uart_uart_sink_payload_data + attribute \src "ls180.v:875.6-875.31" + wire \main_uart_uart_sink_ready + attribute \src "ls180.v:874.6-874.31" + wire \main_uart_uart_sink_valid + attribute \src "ls180.v:881.6-881.33" + wire \main_uart_uart_source_first + attribute \src "ls180.v:882.6-882.32" + wire \main_uart_uart_source_last + attribute \src "ls180.v:883.12-883.46" + wire width 8 \main_uart_uart_source_payload_data + attribute \src "ls180.v:880.6-880.33" + wire \main_uart_uart_source_ready + attribute \src "ls180.v:879.6-879.33" + wire \main_uart_uart_source_valid + attribute \src "ls180.v:795.5-795.22" + wire \main_wb_sdram_ack + attribute \src "ls180.v:789.13-789.30" + wire width 30 \main_wb_sdram_adr + attribute \src "ls180.v:798.12-798.29" + wire width 2 \main_wb_sdram_bte + attribute \src "ls180.v:797.12-797.29" + wire width 3 \main_wb_sdram_cti + attribute \src "ls180.v:793.6-793.23" + wire \main_wb_sdram_cyc + attribute \src "ls180.v:791.13-791.32" + wire width 32 \main_wb_sdram_dat_r + attribute \src "ls180.v:790.13-790.32" + wire width 32 \main_wb_sdram_dat_w + attribute \src "ls180.v:799.5-799.22" + wire \main_wb_sdram_err + attribute \src "ls180.v:792.12-792.29" + wire width 4 \main_wb_sdram_sel + attribute \src "ls180.v:794.6-794.23" + wire \main_wb_sdram_stb + attribute \src "ls180.v:796.6-796.22" + wire \main_wb_sdram_we + attribute \src "ls180.v:813.5-813.24" + wire \main_wdata_consumed + attribute \src "ls180.v:10039.11-10039.17" + wire width 7 \memadr + attribute \src "ls180.v:10059.12-10059.18" + wire width 25 \memdat + attribute \src "ls180.v:10073.12-10073.20" + wire width 25 \memdat_1 + attribute \src "ls180.v:10087.12-10087.20" + wire width 25 \memdat_2 + attribute \src "ls180.v:10101.12-10101.20" + wire width 25 \memdat_3 + attribute \src "ls180.v:10115.11-10115.19" + wire width 10 \memdat_4 + attribute \src "ls180.v:10116.11-10116.19" + wire width 10 \memdat_5 + attribute \src "ls180.v:10132.11-10132.19" + wire width 10 \memdat_6 + attribute \src "ls180.v:10133.11-10133.19" + wire width 10 \memdat_7 + attribute \src "ls180.v:10149.11-10149.19" + wire width 10 \memdat_8 + attribute \src "ls180.v:10163.11-10163.19" + wire width 10 \memdat_9 + attribute \src "ls180.v:35.20-35.22" + wire width 36 input 31 \nc + attribute \src "ls180.v:227.6-227.13" + wire \por_clk + attribute \src "ls180.v:36.13-36.17" + wire output 32 \pwm0 + attribute \src "ls180.v:37.13-37.17" + wire output 33 \pwm1 + attribute \src "ls180.v:42.13-42.23" + wire output 38 \sdcard_clk + attribute \src "ls180.v:43.13-43.25" + wire input 39 \sdcard_cmd_i + attribute \src "ls180.v:44.13-44.25" + wire output 40 \sdcard_cmd_o + attribute \src "ls180.v:45.13-45.26" + wire output 41 \sdcard_cmd_oe + attribute \src "ls180.v:46.19-46.32" + wire width 4 input 42 \sdcard_data_i + attribute \src "ls180.v:47.19-47.32" + wire width 4 output 43 \sdcard_data_o + attribute \src "ls180.v:48.13-48.27" + wire output 44 \sdcard_data_oe + attribute \src "ls180.v:9.20-9.27" + wire width 13 output 5 \sdram_a + attribute \src "ls180.v:18.19-18.27" + wire width 2 output 14 \sdram_ba + attribute \src "ls180.v:15.13-15.24" + wire output 11 \sdram_cas_n + attribute \src "ls180.v:17.13-17.22" + wire output 13 \sdram_cke + attribute \src "ls180.v:20.13-20.24" + wire output 16 \sdram_clock + attribute \src "ls180.v:16.13-16.23" + wire output 12 \sdram_cs_n + attribute \src "ls180.v:19.19-19.27" + wire width 2 output 15 \sdram_dm + attribute \src "ls180.v:10.20-10.30" + wire width 16 input 6 \sdram_dq_i + attribute \src "ls180.v:11.20-11.30" + wire width 16 output 7 \sdram_dq_o + attribute \src "ls180.v:12.13-12.24" + wire output 8 \sdram_dq_oe + attribute \src "ls180.v:14.13-14.24" + wire output 10 \sdram_ras_n + attribute \src "ls180.v:13.13-13.23" + wire output 9 \sdram_we_n + attribute \src "ls180.v:2623.6-2623.15" + wire \sdrio_clk + attribute \src "ls180.v:2624.6-2624.17" + wire \sdrio_clk_1 + attribute \src "ls180.v:2633.6-2633.18" + wire \sdrio_clk_10 + attribute \src "ls180.v:2634.6-2634.18" + wire \sdrio_clk_11 + attribute \src "ls180.v:2635.6-2635.18" + wire \sdrio_clk_12 + attribute \src "ls180.v:2636.6-2636.18" + wire \sdrio_clk_13 + attribute \src "ls180.v:2637.6-2637.18" + wire \sdrio_clk_14 + attribute \src "ls180.v:2638.6-2638.18" + wire \sdrio_clk_15 + attribute \src "ls180.v:2639.6-2639.18" + wire \sdrio_clk_16 + attribute \src "ls180.v:2640.6-2640.18" + wire \sdrio_clk_17 + attribute \src "ls180.v:2641.6-2641.18" + wire \sdrio_clk_18 + attribute \src "ls180.v:2642.6-2642.18" + wire \sdrio_clk_19 + attribute \src "ls180.v:2625.6-2625.17" + wire \sdrio_clk_2 + attribute \src "ls180.v:2643.6-2643.18" + wire \sdrio_clk_20 + attribute \src "ls180.v:2644.6-2644.18" + wire \sdrio_clk_21 + attribute \src "ls180.v:2645.6-2645.18" + wire \sdrio_clk_22 + attribute \src "ls180.v:2646.6-2646.18" + wire \sdrio_clk_23 + attribute \src "ls180.v:2647.6-2647.18" + wire \sdrio_clk_24 + attribute \src "ls180.v:2648.6-2648.18" + wire \sdrio_clk_25 + attribute \src "ls180.v:2649.6-2649.18" + wire \sdrio_clk_26 + attribute \src "ls180.v:2650.6-2650.18" + wire \sdrio_clk_27 + attribute \src "ls180.v:2651.6-2651.18" + wire \sdrio_clk_28 + attribute \src "ls180.v:2652.6-2652.18" + wire \sdrio_clk_29 + attribute \src "ls180.v:2626.6-2626.17" + wire \sdrio_clk_3 + attribute \src "ls180.v:2653.6-2653.18" + wire \sdrio_clk_30 + attribute \src "ls180.v:2654.6-2654.18" + wire \sdrio_clk_31 + attribute \src "ls180.v:2655.6-2655.18" + wire \sdrio_clk_32 + attribute \src "ls180.v:2656.6-2656.18" + wire \sdrio_clk_33 + attribute \src "ls180.v:2657.6-2657.18" + wire \sdrio_clk_34 + attribute \src "ls180.v:2658.6-2658.18" + wire \sdrio_clk_35 + attribute \src "ls180.v:2659.6-2659.18" + wire \sdrio_clk_36 + attribute \src "ls180.v:2660.6-2660.18" + wire \sdrio_clk_37 + attribute \src "ls180.v:2661.6-2661.18" + wire \sdrio_clk_38 + attribute \src "ls180.v:2662.6-2662.18" + wire \sdrio_clk_39 + attribute \src "ls180.v:2627.6-2627.17" + wire \sdrio_clk_4 + attribute \src "ls180.v:2663.6-2663.18" + wire \sdrio_clk_40 + attribute \src "ls180.v:2664.6-2664.18" + wire \sdrio_clk_41 + attribute \src "ls180.v:2665.6-2665.18" + wire \sdrio_clk_42 + attribute \src "ls180.v:2666.6-2666.18" + wire \sdrio_clk_43 + attribute \src "ls180.v:2667.6-2667.18" + wire \sdrio_clk_44 + attribute \src "ls180.v:2668.6-2668.18" + wire \sdrio_clk_45 + attribute \src "ls180.v:2669.6-2669.18" + wire \sdrio_clk_46 + attribute \src "ls180.v:2670.6-2670.18" + wire \sdrio_clk_47 + attribute \src "ls180.v:2671.6-2671.18" + wire \sdrio_clk_48 + attribute \src "ls180.v:2672.6-2672.18" + wire \sdrio_clk_49 + attribute \src "ls180.v:2628.6-2628.17" + wire \sdrio_clk_5 + attribute \src "ls180.v:2673.6-2673.18" + wire \sdrio_clk_50 + attribute \src "ls180.v:2674.6-2674.18" + wire \sdrio_clk_51 + attribute \src "ls180.v:2675.6-2675.18" + wire \sdrio_clk_52 + attribute \src "ls180.v:2676.6-2676.18" + wire \sdrio_clk_53 + attribute \src "ls180.v:2677.6-2677.18" + wire \sdrio_clk_54 + attribute \src "ls180.v:2678.6-2678.18" + wire \sdrio_clk_55 + attribute \src "ls180.v:2713.6-2713.18" + wire \sdrio_clk_56 + attribute \src "ls180.v:2714.6-2714.18" + wire \sdrio_clk_57 + attribute \src "ls180.v:2715.6-2715.18" + wire \sdrio_clk_58 + attribute \src "ls180.v:2716.6-2716.18" + wire \sdrio_clk_59 + attribute \src "ls180.v:2629.6-2629.17" + wire \sdrio_clk_6 + attribute \src "ls180.v:2717.6-2717.18" + wire \sdrio_clk_60 + attribute \src "ls180.v:2718.6-2718.18" + wire \sdrio_clk_61 + attribute \src "ls180.v:2719.6-2719.18" + wire \sdrio_clk_62 + attribute \src "ls180.v:2720.6-2720.18" + wire \sdrio_clk_63 + attribute \src "ls180.v:2721.6-2721.18" + wire \sdrio_clk_64 + attribute \src "ls180.v:2722.6-2722.18" + wire \sdrio_clk_65 + attribute \src "ls180.v:2723.6-2723.18" + wire \sdrio_clk_66 + attribute \src "ls180.v:2724.6-2724.18" + wire \sdrio_clk_67 + attribute \src "ls180.v:2725.6-2725.18" + wire \sdrio_clk_68 + attribute \src "ls180.v:2630.6-2630.17" + wire \sdrio_clk_7 + attribute \src "ls180.v:2631.6-2631.17" + wire \sdrio_clk_8 + attribute \src "ls180.v:2632.6-2632.17" + wire \sdrio_clk_9 + attribute \src "ls180.v:26.13-26.27" + wire output 22 \spi_master_clk + attribute \src "ls180.v:28.13-28.28" + wire output 24 \spi_master_cs_n + attribute \src "ls180.v:29.13-29.28" + wire input 25 \spi_master_miso + attribute \src "ls180.v:27.13-27.28" + wire output 23 \spi_master_mosi + attribute \src "ls180.v:49.13-49.26" + wire output 45 \spisdcard_clk + attribute \src "ls180.v:51.13-51.27" + wire output 47 \spisdcard_cs_n + attribute \src "ls180.v:52.13-52.27" + wire input 48 \spisdcard_miso + attribute \src "ls180.v:50.13-50.27" + wire output 46 \spisdcard_mosi + attribute \src "ls180.v:5.13-5.20" + wire input 1 \sys_clk + attribute \src "ls180.v:225.6-225.15" + wire \sys_clk_1 + attribute \src "ls180.v:7.19-7.31" + wire width 3 input 3 \sys_clksel_i + attribute \src "ls180.v:8.14-8.26" + wire output 4 \sys_pll_48_o + attribute \src "ls180.v:6.13-6.20" + wire input 2 \sys_rst + attribute \src "ls180.v:226.6-226.15" + wire \sys_rst_1 + attribute \src "ls180.v:22.13-22.20" + wire input 18 \uart_rx + attribute \src "ls180.v:21.14-21.21" + wire output 17 \uart_tx + attribute \src "ls180.v:10038.12-10038.15" + memory width 32 size 128 \mem + attribute \src "ls180.v:10058.12-10058.19" + memory width 25 size 8 \storage + attribute \src "ls180.v:10072.12-10072.21" + memory width 25 size 8 \storage_1 + attribute \src "ls180.v:10086.12-10086.21" + memory width 25 size 8 \storage_2 + attribute \src "ls180.v:10100.12-10100.21" + memory width 25 size 8 \storage_3 + attribute \src "ls180.v:10114.11-10114.20" + memory width 10 size 16 \storage_4 + attribute \src "ls180.v:10131.11-10131.20" + memory width 10 size 16 \storage_5 + attribute \src "ls180.v:10148.11-10148.20" + memory width 10 size 32 \storage_6 + attribute \src "ls180.v:10162.11-10162.20" + memory width 10 size 32 \storage_7 + attribute \src "ls180.v:2799.68-2799.110" + cell $add $add$ls180.v:2799$22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_counter + connect \B 1'1 + connect \Y $add$ls180.v:2799$22_Y + end + attribute \src "ls180.v:2859.68-2859.110" + cell $add $add$ls180.v:2859$33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_counter + connect \B 1'1 + connect \Y $add$ls180.v:2859$33_Y + end + attribute \src "ls180.v:2919.68-2919.110" + cell $add $add$ls180.v:2919$44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter2_counter + connect \B 1'1 + connect \Y $add$ls180.v:2919$44_Y + end + attribute \src "ls180.v:4052.54-4052.83" + cell $add $add$ls180.v:4052$537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_counter + connect \B 1'1 + connect \Y $add$ls180.v:4052$537_Y + end + attribute \src "ls180.v:4152.36-4152.89" + cell $add $add$ls180.v:4152$583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B \main_uart_tx_fifo_readable + connect \Y $add$ls180.v:4152$583_Y + end + attribute \src "ls180.v:4182.36-4182.89" + cell $add $add$ls180.v:4182$594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B \main_uart_rx_fifo_readable + connect \Y $add$ls180.v:4182$594_Y + end + attribute \src "ls180.v:4237.53-4237.81" + cell $add $add$ls180.v:4237$607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spi_master_count + connect \B 1'1 + connect \Y $add$ls180.v:4237$607_Y + end + attribute \src "ls180.v:4341.58-4341.86" + cell $add $add$ls180.v:4341$635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_init_count + connect \B 1'1 + connect \Y $add$ls180.v:4341$635_Y + end + attribute \src "ls180.v:4398.58-4398.86" + cell $add $add$ls180.v:4398$638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdw_count + connect \B 1'1 + connect \Y $add$ls180.v:4398$638_Y + end + attribute \src "ls180.v:4415.58-4415.86" + cell $add $add$ls180.v:4415$640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdw_count + connect \B 1'1 + connect \Y $add$ls180.v:4415$640_Y + end + attribute \src "ls180.v:4508.59-4508.87" + cell $add $add$ls180.v:4508$657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_count + connect \B 1'1 + connect \Y $add$ls180.v:4508$657_Y + end + attribute \src "ls180.v:4533.59-4533.87" + cell $add $add$ls180.v:4533$660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_count + connect \B 1'1 + connect \Y $add$ls180.v:4533$660_Y + end + attribute \src "ls180.v:4655.53-4655.82" + cell $add $add$ls180.v:4655$677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_dataw_count + connect \B 1'1 + connect \Y $add$ls180.v:4655$677_Y + end + attribute \src "ls180.v:4766.65-4766.114" + cell $add $add$ls180.v:4766$691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_sink_payload_block_length + connect \B 4'1000 + connect \Y $add$ls180.v:4766$691_Y + end + attribute \src "ls180.v:4771.62-4771.91" + cell $add $add$ls180.v:4771$694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_count + connect \B 1'1 + connect \Y $add$ls180.v:4771$694_Y + end + attribute \src "ls180.v:4797.61-4797.90" + cell $add $add$ls180.v:4797$697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_count + connect \B 1'1 + connect \Y $add$ls180.v:4797$697_Y + end + attribute \src "ls180.v:5001.80-5001.117" + cell $add $add$ls180.v:5001$882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 1'1 + connect \Y $add$ls180.v:5001$882_Y + end + attribute \src "ls180.v:5195.54-5195.82" + cell $add $add$ls180.v:5195$957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdcore_cmd_count + connect \B 1'1 + connect \Y $add$ls180.v:5195$957_Y + end + attribute \src "ls180.v:5247.55-5247.84" + cell $add $add$ls180.v:5247$967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_data_count + connect \B 1'1 + connect \Y $add$ls180.v:5247$967_Y + end + attribute \src "ls180.v:5273.57-5273.86" + cell $add $add$ls180.v:5273$975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_data_count + connect \B 1'1 + connect \Y $add$ls180.v:5273$975_Y + end + attribute \src "ls180.v:5394.51-5394.134" + cell $add $add$ls180.v:5394$991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_base + connect \B \main_sdblock2mem_wishbonedmawriter_offset + connect \Y $add$ls180.v:5394$991_Y + end + attribute \src "ls180.v:5397.77-5397.125" + cell $add $add$ls180.v:5397$993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_offset + connect \B 1'1 + connect \Y $add$ls180.v:5397$993_Y + end + attribute \src "ls180.v:5490.50-5490.105" + cell $add $add$ls180.v:5490$1002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_base + connect \B \main_sdmem2block_dma_offset + connect \Y $add$ls180.v:5490$1002_Y + end + attribute \src "ls180.v:5492.77-5492.111" + cell $add $add$ls180.v:5492$1003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_offset + connect \B 1'1 + connect \Y $add$ls180.v:5492$1003_Y + end + attribute \src "ls180.v:5604.49-5604.73" + cell $add $add$ls180.v:5604$1022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \libresocsim_count + connect \B 1'1 + connect \Y $add$ls180.v:5604$1022_Y + end + attribute \src "ls180.v:7483.36-7483.70" + cell $add $add$ls180.v:7483$2415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_libresocsim_bus_errors + connect \B 1'1 + connect \Y $add$ls180.v:7483$2415_Y + end + attribute \src "ls180.v:7568.37-7568.72" + cell $add $add$ls180.v:7568$2436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_sequencer_counter + connect \B 1'1 + connect \Y $add$ls180.v:7568$2436_Y + end + attribute \src "ls180.v:7585.60-7585.119" + cell $add $add$ls180.v:7585$2440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7585$2440_Y + end + attribute \src "ls180.v:7588.60-7588.119" + cell $add $add$ls180.v:7588$2441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7588$2441_Y + end + attribute \src "ls180.v:7592.59-7592.116" + cell $add $add$ls180.v:7592$2446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7592$2446_Y + end + attribute \src "ls180.v:7631.60-7631.119" + cell $add $add$ls180.v:7631$2456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7631$2456_Y + end + attribute \src "ls180.v:7634.60-7634.119" + cell $add $add$ls180.v:7634$2457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7634$2457_Y + end + attribute \src "ls180.v:7638.59-7638.116" + cell $add $add$ls180.v:7638$2462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7638$2462_Y + end + attribute \src "ls180.v:7677.60-7677.119" + cell $add $add$ls180.v:7677$2472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7677$2472_Y + end + attribute \src "ls180.v:7680.60-7680.119" + cell $add $add$ls180.v:7680$2473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7680$2473_Y + end + attribute \src "ls180.v:7684.59-7684.116" + cell $add $add$ls180.v:7684$2478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7684$2478_Y + end + attribute \src "ls180.v:7723.60-7723.119" + cell $add $add$ls180.v:7723$2488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7723$2488_Y + end + attribute \src "ls180.v:7726.60-7726.119" + cell $add $add$ls180.v:7726$2489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7726$2489_Y + end + attribute \src "ls180.v:7730.59-7730.116" + cell $add $add$ls180.v:7730$2494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7730$2494_Y + end + attribute \src "ls180.v:7960.34-7960.66" + cell $add $add$ls180.v:7960$2548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_phy_tx_bitcount + connect \B 1'1 + connect \Y $add$ls180.v:7960$2548_Y + end + attribute \src "ls180.v:7976.73-7976.131" + cell $add $add$ls180.v:7976$2551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 33 + connect \A \main_uart_phy_phase_accumulator_tx + connect \B \main_uart_phy_storage + connect \Y $add$ls180.v:7976$2551_Y + end + attribute \src "ls180.v:7989.34-7989.66" + cell $add $add$ls180.v:7989$2555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_phy_rx_bitcount + connect \B 1'1 + connect \Y $add$ls180.v:7989$2555_Y + end + attribute \src "ls180.v:8008.73-8008.131" + cell $add $add$ls180.v:8008$2558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 33 + connect \A \main_uart_phy_phase_accumulator_rx + connect \B \main_uart_phy_storage + connect \Y $add$ls180.v:8008$2558_Y + end + attribute \src "ls180.v:8034.33-8034.65" + cell $add $add$ls180.v:8034$2566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8034$2566_Y + end + attribute \src "ls180.v:8037.33-8037.65" + cell $add $add$ls180.v:8037$2567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8037$2567_Y + end + attribute \src "ls180.v:8041.33-8041.64" + cell $add $add$ls180.v:8041$2572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'1 + connect \Y $add$ls180.v:8041$2572_Y + end + attribute \src "ls180.v:8056.33-8056.65" + cell $add $add$ls180.v:8056$2577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8056$2577_Y + end + attribute \src "ls180.v:8059.33-8059.65" + cell $add $add$ls180.v:8059$2578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8059$2578_Y + end + attribute \src "ls180.v:8063.33-8063.64" + cell $add $add$ls180.v:8063$2583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'1 + connect \Y $add$ls180.v:8063$2583_Y + end + attribute \src "ls180.v:8084.35-8084.70" + cell $add $add$ls180.v:8084$2585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spi_master_clk_divider1 + connect \B 1'1 + connect \Y $add$ls180.v:8084$2585_Y + end + attribute \src "ls180.v:8120.25-8120.49" + cell $add $add$ls180.v:8120$2590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm0_counter + connect \B 1'1 + connect \Y $add$ls180.v:8120$2590_Y + end + attribute \src "ls180.v:8134.25-8134.49" + cell $add $add$ls180.v:8134$2594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm1_counter + connect \B 1'1 + connect \Y $add$ls180.v:8134$2594_Y + end + attribute \src "ls180.v:8148.31-8148.61" + cell $add $add$ls180.v:8148$2599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 9 + connect \A \main_sdphy_clocker_clks + connect \B 1'1 + connect \Y $add$ls180.v:8148$2599_Y + end + attribute \src "ls180.v:8171.45-8171.88" + cell $add $add$ls180.v:8171$2603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8171$2603_Y + end + attribute \src "ls180.v:8217.71-8217.114" + cell $add $add$ls180.v:8217$2609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8217$2609_Y + end + attribute \src "ls180.v:8252.46-8252.90" + cell $add $add$ls180.v:8252$2615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8252$2615_Y + end + attribute \src "ls180.v:8298.72-8298.116" + cell $add $add$ls180.v:8298$2621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8298$2621_Y + end + attribute \src "ls180.v:8331.47-8331.92" + cell $add $add$ls180.v:8331$2627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8331$2627_Y + end + attribute \src "ls180.v:8359.73-8359.118" + cell $add $add$ls180.v:8359$2633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8359$2633_Y + end + attribute \src "ls180.v:8471.39-8471.75" + cell $add $add$ls180.v:8471$2646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 1'1 + connect \Y $add$ls180.v:8471$2646_Y + end + attribute \src "ls180.v:8532.37-8532.73" + cell $add $add$ls180.v:8532$2650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8532$2650_Y + end + attribute \src "ls180.v:8535.37-8535.73" + cell $add $add$ls180.v:8535$2651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8535$2651_Y + end + attribute \src "ls180.v:8539.36-8539.70" + cell $add $add$ls180.v:8539$2656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'1 + connect \Y $add$ls180.v:8539$2656_Y + end + attribute \src "ls180.v:8554.41-8554.80" + cell $add $add$ls180.v:8554$2660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \main_sdblock2mem_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8554$2660_Y + end + attribute \src "ls180.v:8588.67-8588.106" + cell $add $add$ls180.v:8588$2666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdblock2mem_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8588$2666_Y + end + attribute \src "ls180.v:8614.39-8614.76" + cell $add $add$ls180.v:8614$2668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \main_sdmem2block_converter_mux + connect \B 1'1 + connect \Y $add$ls180.v:8614$2668_Y + end + attribute \src "ls180.v:8618.37-8618.73" + cell $add $add$ls180.v:8618$2672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8618$2672_Y + end + attribute \src "ls180.v:8621.37-8621.73" + cell $add $add$ls180.v:8621$2673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8621$2673_Y + end + attribute \src "ls180.v:8625.36-8625.70" + cell $add $add$ls180.v:8625$2678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdmem2block_fifo_level + connect \B 1'1 + connect \Y $add$ls180.v:8625$2678_Y + end + attribute \src "ls180.v:8632.31-8632.62" + cell $add $add$ls180.v:8632$2680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \libresocsim_clk_divider1 + connect \B 1'1 + connect \Y $add$ls180.v:8632$2680_Y + end + attribute \src "ls180.v:2793.9-2793.80" + cell $and $and$ls180.v:2793$17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_ibus_stb + connect \B \main_libresocsim_libresoc_ibus_cyc + connect \Y $and$ls180.v:2793$17_Y + end + attribute \src "ls180.v:2811.9-2811.80" + cell $and $and$ls180.v:2811$24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_ibus_stb + connect \B \main_libresocsim_libresoc_ibus_cyc + connect \Y $and$ls180.v:2811$24_Y + end + attribute \src "ls180.v:2853.9-2853.80" + cell $and $and$ls180.v:2853$28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_dbus_stb + connect \B \main_libresocsim_libresoc_dbus_cyc + connect \Y $and$ls180.v:2853$28_Y + end + attribute \src "ls180.v:2871.9-2871.80" + cell $and $and$ls180.v:2871$35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_dbus_stb + connect \B \main_libresocsim_libresoc_dbus_cyc + connect \Y $and$ls180.v:2871$35_Y + end + attribute \src "ls180.v:2913.9-2913.86" + cell $and $and$ls180.v:2913$39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_jtag_wb_stb + connect \B \main_libresocsim_libresoc_jtag_wb_cyc + connect \Y $and$ls180.v:2913$39_Y + end + attribute \src "ls180.v:2931.9-2931.86" + cell $and $and$ls180.v:2931$46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_jtag_wb_stb + connect \B \main_libresocsim_libresoc_jtag_wb_cyc + connect \Y $and$ls180.v:2931$46_Y + end + attribute \src "ls180.v:2941.31-2941.90" + cell $and $and$ls180.v:2941$48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:2941$48_Y + end + attribute \src "ls180.v:2941.30-2941.121" + cell $and $and$ls180.v:2941$49 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2941$48_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:2941$49_Y + end + attribute \src "ls180.v:2941.29-2941.156" + cell $and $and$ls180.v:2941$50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2941$49_Y + connect \B \main_libresocsim_ram_bus_sel [0] + connect \Y $and$ls180.v:2941$50_Y + end + attribute \src "ls180.v:2942.31-2942.90" + cell $and $and$ls180.v:2942$51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:2942$51_Y + end + attribute \src "ls180.v:2942.30-2942.121" + cell $and $and$ls180.v:2942$52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2942$51_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:2942$52_Y + end + attribute \src "ls180.v:2942.29-2942.156" + cell $and $and$ls180.v:2942$53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2942$52_Y + connect \B \main_libresocsim_ram_bus_sel [1] + connect \Y $and$ls180.v:2942$53_Y + end + attribute \src "ls180.v:2943.31-2943.90" + cell $and $and$ls180.v:2943$54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:2943$54_Y + end + attribute \src "ls180.v:2943.30-2943.121" + cell $and $and$ls180.v:2943$55 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2943$54_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:2943$55_Y + end + attribute \src "ls180.v:2943.29-2943.156" + cell $and $and$ls180.v:2943$56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2943$55_Y + connect \B \main_libresocsim_ram_bus_sel [2] + connect \Y $and$ls180.v:2943$56_Y + end + attribute \src "ls180.v:2944.31-2944.90" + cell $and $and$ls180.v:2944$57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:2944$57_Y + end + attribute \src "ls180.v:2944.30-2944.121" + cell $and $and$ls180.v:2944$58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2944$57_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:2944$58_Y + end + attribute \src "ls180.v:2944.29-2944.156" + cell $and $and$ls180.v:2944$59 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2944$58_Y + connect \B \main_libresocsim_ram_bus_sel [3] + connect \Y $and$ls180.v:2944$59_Y + end + attribute \src "ls180.v:2953.7-2953.89" + cell $and $and$ls180.v:2953$62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_eventmanager_pending_re + connect \B \main_libresocsim_eventmanager_pending_r + connect \Y $and$ls180.v:2953$62_Y + end + attribute \src "ls180.v:2958.32-2958.111" + cell $and $and$ls180.v:2958$63 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_eventmanager_pending_w + connect \B \main_libresocsim_eventmanager_storage + connect \Y $and$ls180.v:2958$63_Y + end + attribute \src "ls180.v:3072.40-3072.99" + cell $and $and$ls180.v:3072$70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_issue_re + connect \B \main_sdram_command_storage [4] + connect \Y $and$ls180.v:3072$70_Y + end + attribute \src "ls180.v:3073.40-3073.99" + cell $and $and$ls180.v:3073$71 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_issue_re + connect \B \main_sdram_command_storage [5] + connect \Y $and$ls180.v:3073$71_Y + end + attribute \src "ls180.v:3111.38-3111.103" + cell $and $and$ls180.v:3111$77 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_done1 + connect \B $eq$ls180.v:3111$76_Y + connect \Y $and$ls180.v:3111$77_Y + end + attribute \src "ls180.v:3165.50-3165.119" + cell $and $and$ls180.v:3165$85 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3165$85_Y + end + attribute \src "ls180.v:3165.49-3165.167" + cell $and $and$ls180.v:3165$86 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3165$85_Y + connect \B \main_sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:3165$86_Y + end + attribute \src "ls180.v:3166.49-3166.118" + cell $and $and$ls180.v:3166$87 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3166$87_Y + end + attribute \src "ls180.v:3166.48-3166.154" + cell $and $and$ls180.v:3166$88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3166$87_Y + connect \B \main_sdram_bankmachine0_row_open + connect \Y $and$ls180.v:3166$88_Y + end + attribute \src "ls180.v:3167.50-3167.119" + cell $and $and$ls180.v:3167$89 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3167$89_Y + end + attribute \src "ls180.v:3167.49-3167.155" + cell $and $and$ls180.v:3167$90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3167$89_Y + connect \B \main_sdram_bankmachine0_row_open + connect \Y $and$ls180.v:3167$90_Y + end + attribute \src "ls180.v:3170.7-3170.114" + cell $and $and$ls180.v:3170$92 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $and$ls180.v:3170$92_Y + end + attribute \src "ls180.v:3199.66-3199.246" + cell $and $and$ls180.v:3199$98 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B $or$ls180.v:3199$97_Y + connect \Y $and$ls180.v:3199$98_Y + end + attribute \src "ls180.v:3200.64-3200.187" + cell $and $and$ls180.v:3200$99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + connect \Y $and$ls180.v:3200$99_Y + end + attribute \src "ls180.v:3224.9-3224.86" + cell $and $and$ls180.v:3224$105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \B \main_sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:3224$105_Y + end + attribute \src "ls180.v:3236.9-3236.86" + cell $and $and$ls180.v:3236$106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \B \main_sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:3236$106_Y + end + attribute \src "ls180.v:3286.13-3286.87" + cell $and $and$ls180.v:3286$108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_ready + connect \B \main_sdram_bankmachine0_auto_precharge + connect \Y $and$ls180.v:3286$108_Y + end + attribute \src "ls180.v:3322.50-3322.119" + cell $and $and$ls180.v:3322$115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3322$115_Y + end + attribute \src "ls180.v:3322.49-3322.167" + cell $and $and$ls180.v:3322$116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3322$115_Y + connect \B \main_sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:3322$116_Y + end + attribute \src "ls180.v:3323.49-3323.118" + cell $and $and$ls180.v:3323$117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3323$117_Y + end + attribute \src "ls180.v:3323.48-3323.154" + cell $and $and$ls180.v:3323$118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3323$117_Y + connect \B \main_sdram_bankmachine1_row_open + connect \Y $and$ls180.v:3323$118_Y + end + attribute \src "ls180.v:3324.50-3324.119" + cell $and $and$ls180.v:3324$119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3324$119_Y + end + attribute \src "ls180.v:3324.49-3324.155" + cell $and $and$ls180.v:3324$120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3324$119_Y + connect \B \main_sdram_bankmachine1_row_open + connect \Y $and$ls180.v:3324$120_Y + end + attribute \src "ls180.v:3327.7-3327.114" + cell $and $and$ls180.v:3327$122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $and$ls180.v:3327$122_Y + end + attribute \src "ls180.v:3356.66-3356.246" + cell $and $and$ls180.v:3356$128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B $or$ls180.v:3356$127_Y + connect \Y $and$ls180.v:3356$128_Y + end + attribute \src "ls180.v:3357.64-3357.187" + cell $and $and$ls180.v:3357$129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + connect \Y $and$ls180.v:3357$129_Y + end + attribute \src "ls180.v:3381.9-3381.86" + cell $and $and$ls180.v:3381$135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \B \main_sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:3381$135_Y + end + attribute \src "ls180.v:3393.9-3393.86" + cell $and $and$ls180.v:3393$136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \B \main_sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:3393$136_Y + end + attribute \src "ls180.v:3443.13-3443.87" + cell $and $and$ls180.v:3443$138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_ready + connect \B \main_sdram_bankmachine1_auto_precharge + connect \Y $and$ls180.v:3443$138_Y + end + attribute \src "ls180.v:3479.50-3479.119" + cell $and $and$ls180.v:3479$145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3479$145_Y + end + attribute \src "ls180.v:3479.49-3479.167" + cell $and $and$ls180.v:3479$146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3479$145_Y + connect \B \main_sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:3479$146_Y + end + attribute \src "ls180.v:3480.49-3480.118" + cell $and $and$ls180.v:3480$147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3480$147_Y + end + attribute \src "ls180.v:3480.48-3480.154" + cell $and $and$ls180.v:3480$148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3480$147_Y + connect \B \main_sdram_bankmachine2_row_open + connect \Y $and$ls180.v:3480$148_Y + end + attribute \src "ls180.v:3481.50-3481.119" + cell $and $and$ls180.v:3481$149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3481$149_Y + end + attribute \src "ls180.v:3481.49-3481.155" + cell $and $and$ls180.v:3481$150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3481$149_Y + connect \B \main_sdram_bankmachine2_row_open + connect \Y $and$ls180.v:3481$150_Y + end + attribute \src "ls180.v:3484.7-3484.114" + cell $and $and$ls180.v:3484$152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $and$ls180.v:3484$152_Y + end + attribute \src "ls180.v:3513.66-3513.246" + cell $and $and$ls180.v:3513$158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B $or$ls180.v:3513$157_Y + connect \Y $and$ls180.v:3513$158_Y + end + attribute \src "ls180.v:3514.64-3514.187" + cell $and $and$ls180.v:3514$159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + connect \Y $and$ls180.v:3514$159_Y + end + attribute \src "ls180.v:3538.9-3538.86" + cell $and $and$ls180.v:3538$165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \B \main_sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:3538$165_Y + end + attribute \src "ls180.v:3550.9-3550.86" + cell $and $and$ls180.v:3550$166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \B \main_sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:3550$166_Y + end + attribute \src "ls180.v:3600.13-3600.87" + cell $and $and$ls180.v:3600$168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_ready + connect \B \main_sdram_bankmachine2_auto_precharge + connect \Y $and$ls180.v:3600$168_Y + end + attribute \src "ls180.v:3636.50-3636.119" + cell $and $and$ls180.v:3636$175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3636$175_Y + end + attribute \src "ls180.v:3636.49-3636.167" + cell $and $and$ls180.v:3636$176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3636$175_Y + connect \B \main_sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:3636$176_Y + end + attribute \src "ls180.v:3637.49-3637.118" + cell $and $and$ls180.v:3637$177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3637$177_Y + end + attribute \src "ls180.v:3637.48-3637.154" + cell $and $and$ls180.v:3637$178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3637$177_Y + connect \B \main_sdram_bankmachine3_row_open + connect \Y $and$ls180.v:3637$178_Y + end + attribute \src "ls180.v:3638.50-3638.119" + cell $and $and$ls180.v:3638$179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3638$179_Y + end + attribute \src "ls180.v:3638.49-3638.155" + cell $and $and$ls180.v:3638$180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3638$179_Y + connect \B \main_sdram_bankmachine3_row_open + connect \Y $and$ls180.v:3638$180_Y + end + attribute \src "ls180.v:3641.7-3641.114" + cell $and $and$ls180.v:3641$182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $and$ls180.v:3641$182_Y + end + attribute \src "ls180.v:3670.66-3670.246" + cell $and $and$ls180.v:3670$188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B $or$ls180.v:3670$187_Y + connect \Y $and$ls180.v:3670$188_Y + end + attribute \src "ls180.v:3671.64-3671.187" + cell $and $and$ls180.v:3671$189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + connect \Y $and$ls180.v:3671$189_Y + end + attribute \src "ls180.v:3695.9-3695.86" + cell $and $and$ls180.v:3695$195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \B \main_sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:3695$195_Y + end + attribute \src "ls180.v:3707.9-3707.86" + cell $and $and$ls180.v:3707$196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \B \main_sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:3707$196_Y + end + attribute \src "ls180.v:3757.13-3757.87" + cell $and $and$ls180.v:3757$198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_ready + connect \B \main_sdram_bankmachine3_auto_precharge + connect \Y $and$ls180.v:3757$198_Y + end + attribute \src "ls180.v:3772.37-3772.102" + cell $and $and$ls180.v:3772$199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3772$199_Y + end + attribute \src "ls180.v:3772.108-3772.188" + cell $and $and$ls180.v:3772$201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3772$200_Y + connect \Y $and$ls180.v:3772$201_Y + end + attribute \src "ls180.v:3772.107-3772.231" + cell $and $and$ls180.v:3772$203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3772$201_Y + connect \B $not$ls180.v:3772$202_Y + connect \Y $and$ls180.v:3772$203_Y + end + attribute \src "ls180.v:3772.36-3772.232" + cell $and $and$ls180.v:3772$204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3772$199_Y + connect \B $and$ls180.v:3772$203_Y + connect \Y $and$ls180.v:3772$204_Y + end + attribute \src "ls180.v:3773.37-3773.102" + cell $and $and$ls180.v:3773$205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3773$205_Y + end + attribute \src "ls180.v:3773.108-3773.188" + cell $and $and$ls180.v:3773$207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3773$206_Y + connect \Y $and$ls180.v:3773$207_Y + end + attribute \src "ls180.v:3773.107-3773.231" + cell $and $and$ls180.v:3773$209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3773$207_Y + connect \B $not$ls180.v:3773$208_Y + connect \Y $and$ls180.v:3773$209_Y + end + attribute \src "ls180.v:3773.36-3773.232" + cell $and $and$ls180.v:3773$210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3773$205_Y + connect \B $and$ls180.v:3773$209_Y + connect \Y $and$ls180.v:3773$210_Y + end + attribute \src "ls180.v:3774.34-3774.85" + cell $and $and$ls180.v:3774$211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_trrdcon_ready + connect \B \main_sdram_tfawcon_ready + connect \Y $and$ls180.v:3774$211_Y + end + attribute \src "ls180.v:3775.37-3775.102" + cell $and $and$ls180.v:3775$212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3775$212_Y + end + attribute \src "ls180.v:3775.36-3775.194" + cell $and $and$ls180.v:3775$214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3775$212_Y + connect \B $or$ls180.v:3775$213_Y + connect \Y $and$ls180.v:3775$214_Y + end + attribute \src "ls180.v:3777.37-3777.102" + cell $and $and$ls180.v:3777$215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3777$215_Y + end + attribute \src "ls180.v:3777.36-3777.148" + cell $and $and$ls180.v:3777$216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3777$215_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:3777$216_Y + end + attribute \src "ls180.v:3778.40-3778.119" + cell $and $and$ls180.v:3778$217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_payload_is_read + connect \Y $and$ls180.v:3778$217_Y + end + attribute \src "ls180.v:3778.124-3778.203" + cell $and $and$ls180.v:3778$218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_payload_is_read + connect \Y $and$ls180.v:3778$218_Y + end + attribute \src "ls180.v:3778.209-3778.288" + cell $and $and$ls180.v:3778$220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_payload_is_read + connect \Y $and$ls180.v:3778$220_Y + end + attribute \src "ls180.v:3778.294-3778.373" + cell $and $and$ls180.v:3778$222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_payload_is_read + connect \Y $and$ls180.v:3778$222_Y + end + attribute \src "ls180.v:3779.41-3779.121" + cell $and $and$ls180.v:3779$224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:3779$224_Y + end + attribute \src "ls180.v:3779.126-3779.206" + cell $and $and$ls180.v:3779$225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:3779$225_Y + end + attribute \src "ls180.v:3779.212-3779.292" + cell $and $and$ls180.v:3779$227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:3779$227_Y + end + attribute \src "ls180.v:3779.298-3779.378" + cell $and $and$ls180.v:3779$229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:3779$229_Y + end + attribute \src "ls180.v:3786.38-3786.111" + cell $and $and$ls180.v:3786$233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_refresh_gnt + connect \B \main_sdram_bankmachine1_refresh_gnt + connect \Y $and$ls180.v:3786$233_Y + end + attribute \src "ls180.v:3786.37-3786.150" + cell $and $and$ls180.v:3786$234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3786$233_Y + connect \B \main_sdram_bankmachine2_refresh_gnt + connect \Y $and$ls180.v:3786$234_Y + end + attribute \src "ls180.v:3786.36-3786.189" + cell $and $and$ls180.v:3786$235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3786$234_Y + connect \B \main_sdram_bankmachine3_refresh_gnt + connect \Y $and$ls180.v:3786$235_Y + end + attribute \src "ls180.v:3792.77-3792.153" + cell $and $and$ls180.v:3792$238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3792$238_Y + end + attribute \src "ls180.v:3792.162-3792.246" + cell $and $and$ls180.v:3792$240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_ras + connect \B $not$ls180.v:3792$239_Y + connect \Y $and$ls180.v:3792$240_Y + end + attribute \src "ls180.v:3792.161-3792.291" + cell $and $and$ls180.v:3792$242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3792$240_Y + connect \B $not$ls180.v:3792$241_Y + connect \Y $and$ls180.v:3792$242_Y + end + attribute \src "ls180.v:3792.76-3792.333" + cell $and $and$ls180.v:3792$245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3792$238_Y + connect \B $or$ls180.v:3792$244_Y + connect \Y $and$ls180.v:3792$245_Y + end + attribute \src "ls180.v:3792.338-3792.505" + cell $and $and$ls180.v:3792$248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3792$246_Y + connect \B $eq$ls180.v:3792$247_Y + connect \Y $and$ls180.v:3792$248_Y + end + attribute \src "ls180.v:3792.38-3792.507" + cell $and $and$ls180.v:3792$250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B $or$ls180.v:3792$249_Y + connect \Y $and$ls180.v:3792$250_Y + end + attribute \src "ls180.v:3793.77-3793.153" + cell $and $and$ls180.v:3793$251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3793$251_Y + end + attribute \src "ls180.v:3793.162-3793.246" + cell $and $and$ls180.v:3793$253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_ras + connect \B $not$ls180.v:3793$252_Y + connect \Y $and$ls180.v:3793$253_Y + end + attribute \src "ls180.v:3793.161-3793.291" + cell $and $and$ls180.v:3793$255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3793$253_Y + connect \B $not$ls180.v:3793$254_Y + connect \Y $and$ls180.v:3793$255_Y + end + attribute \src "ls180.v:3793.76-3793.333" + cell $and $and$ls180.v:3793$258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3793$251_Y + connect \B $or$ls180.v:3793$257_Y + connect \Y $and$ls180.v:3793$258_Y + end + attribute \src "ls180.v:3793.338-3793.505" + cell $and $and$ls180.v:3793$261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3793$259_Y + connect \B $eq$ls180.v:3793$260_Y + connect \Y $and$ls180.v:3793$261_Y + end + attribute \src "ls180.v:3793.38-3793.507" + cell $and $and$ls180.v:3793$263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B $or$ls180.v:3793$262_Y + connect \Y $and$ls180.v:3793$263_Y + end + attribute \src "ls180.v:3794.77-3794.153" + cell $and $and$ls180.v:3794$264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3794$264_Y + end + attribute \src "ls180.v:3794.162-3794.246" + cell $and $and$ls180.v:3794$266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_ras + connect \B $not$ls180.v:3794$265_Y + connect \Y $and$ls180.v:3794$266_Y + end + attribute \src "ls180.v:3794.161-3794.291" + cell $and $and$ls180.v:3794$268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3794$266_Y + connect \B $not$ls180.v:3794$267_Y + connect \Y $and$ls180.v:3794$268_Y + end + attribute \src "ls180.v:3794.76-3794.333" + cell $and $and$ls180.v:3794$271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3794$264_Y + connect \B $or$ls180.v:3794$270_Y + connect \Y $and$ls180.v:3794$271_Y + end + attribute \src "ls180.v:3794.338-3794.505" + cell $and $and$ls180.v:3794$274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3794$272_Y + connect \B $eq$ls180.v:3794$273_Y + connect \Y $and$ls180.v:3794$274_Y + end + attribute \src "ls180.v:3794.38-3794.507" + cell $and $and$ls180.v:3794$276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B $or$ls180.v:3794$275_Y + connect \Y $and$ls180.v:3794$276_Y + end + attribute \src "ls180.v:3795.77-3795.153" + cell $and $and$ls180.v:3795$277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3795$277_Y + end + attribute \src "ls180.v:3795.162-3795.246" + cell $and $and$ls180.v:3795$279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_ras + connect \B $not$ls180.v:3795$278_Y + connect \Y $and$ls180.v:3795$279_Y + end + attribute \src "ls180.v:3795.161-3795.291" + cell $and $and$ls180.v:3795$281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3795$279_Y + connect \B $not$ls180.v:3795$280_Y + connect \Y $and$ls180.v:3795$281_Y + end + attribute \src "ls180.v:3795.76-3795.333" + cell $and $and$ls180.v:3795$284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3795$277_Y + connect \B $or$ls180.v:3795$283_Y + connect \Y $and$ls180.v:3795$284_Y + end + attribute \src "ls180.v:3795.338-3795.505" + cell $and $and$ls180.v:3795$287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3795$285_Y + connect \B $eq$ls180.v:3795$286_Y + connect \Y $and$ls180.v:3795$287_Y + end + attribute \src "ls180.v:3795.38-3795.507" + cell $and $and$ls180.v:3795$289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B $or$ls180.v:3795$288_Y + connect \Y $and$ls180.v:3795$289_Y + end + attribute \src "ls180.v:3825.77-3825.153" + cell $and $and$ls180.v:3825$296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3825$296_Y + end + attribute \src "ls180.v:3825.162-3825.246" + cell $and $and$ls180.v:3825$298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_ras + connect \B $not$ls180.v:3825$297_Y + connect \Y $and$ls180.v:3825$298_Y + end + attribute \src "ls180.v:3825.161-3825.291" + cell $and $and$ls180.v:3825$300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3825$298_Y + connect \B $not$ls180.v:3825$299_Y + connect \Y $and$ls180.v:3825$300_Y + end + attribute \src "ls180.v:3825.76-3825.333" + cell $and $and$ls180.v:3825$303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3825$296_Y + connect \B $or$ls180.v:3825$302_Y + connect \Y $and$ls180.v:3825$303_Y + end + attribute \src "ls180.v:3825.338-3825.505" + cell $and $and$ls180.v:3825$306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3825$304_Y + connect \B $eq$ls180.v:3825$305_Y + connect \Y $and$ls180.v:3825$306_Y + end + attribute \src "ls180.v:3825.38-3825.507" + cell $and $and$ls180.v:3825$308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B $or$ls180.v:3825$307_Y + connect \Y $and$ls180.v:3825$308_Y + end + attribute \src "ls180.v:3826.77-3826.153" + cell $and $and$ls180.v:3826$309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3826$309_Y + end + attribute \src "ls180.v:3826.162-3826.246" + cell $and $and$ls180.v:3826$311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_ras + connect \B $not$ls180.v:3826$310_Y + connect \Y $and$ls180.v:3826$311_Y + end + attribute \src "ls180.v:3826.161-3826.291" + cell $and $and$ls180.v:3826$313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3826$311_Y + connect \B $not$ls180.v:3826$312_Y + connect \Y $and$ls180.v:3826$313_Y + end + attribute \src "ls180.v:3826.76-3826.333" + cell $and $and$ls180.v:3826$316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3826$309_Y + connect \B $or$ls180.v:3826$315_Y + connect \Y $and$ls180.v:3826$316_Y + end + attribute \src "ls180.v:3826.338-3826.505" + cell $and $and$ls180.v:3826$319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3826$317_Y + connect \B $eq$ls180.v:3826$318_Y + connect \Y $and$ls180.v:3826$319_Y + end + attribute \src "ls180.v:3826.38-3826.507" + cell $and $and$ls180.v:3826$321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B $or$ls180.v:3826$320_Y + connect \Y $and$ls180.v:3826$321_Y + end + attribute \src "ls180.v:3827.77-3827.153" + cell $and $and$ls180.v:3827$322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3827$322_Y + end + attribute \src "ls180.v:3827.162-3827.246" + cell $and $and$ls180.v:3827$324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_ras + connect \B $not$ls180.v:3827$323_Y + connect \Y $and$ls180.v:3827$324_Y + end + attribute \src "ls180.v:3827.161-3827.291" + cell $and $and$ls180.v:3827$326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3827$324_Y + connect \B $not$ls180.v:3827$325_Y + connect \Y $and$ls180.v:3827$326_Y + end + attribute \src "ls180.v:3827.76-3827.333" + cell $and $and$ls180.v:3827$329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3827$322_Y + connect \B $or$ls180.v:3827$328_Y + connect \Y $and$ls180.v:3827$329_Y + end + attribute \src "ls180.v:3827.338-3827.505" + cell $and $and$ls180.v:3827$332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3827$330_Y + connect \B $eq$ls180.v:3827$331_Y + connect \Y $and$ls180.v:3827$332_Y + end + attribute \src "ls180.v:3827.38-3827.507" + cell $and $and$ls180.v:3827$334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B $or$ls180.v:3827$333_Y + connect \Y $and$ls180.v:3827$334_Y + end + attribute \src "ls180.v:3828.77-3828.153" + cell $and $and$ls180.v:3828$335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3828$335_Y + end + attribute \src "ls180.v:3828.162-3828.246" + cell $and $and$ls180.v:3828$337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_ras + connect \B $not$ls180.v:3828$336_Y + connect \Y $and$ls180.v:3828$337_Y + end + attribute \src "ls180.v:3828.161-3828.291" + cell $and $and$ls180.v:3828$339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3828$337_Y + connect \B $not$ls180.v:3828$338_Y + connect \Y $and$ls180.v:3828$339_Y + end + attribute \src "ls180.v:3828.76-3828.333" + cell $and $and$ls180.v:3828$342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3828$335_Y + connect \B $or$ls180.v:3828$341_Y + connect \Y $and$ls180.v:3828$342_Y + end + attribute \src "ls180.v:3828.338-3828.505" + cell $and $and$ls180.v:3828$345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3828$343_Y + connect \B $eq$ls180.v:3828$344_Y + connect \Y $and$ls180.v:3828$345_Y + end + attribute \src "ls180.v:3828.38-3828.507" + cell $and $and$ls180.v:3828$347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B $or$ls180.v:3828$346_Y + connect \Y $and$ls180.v:3828$347_Y + end + attribute \src "ls180.v:3857.8-3857.73" + cell $and $and$ls180.v:3857$352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3857$352_Y + end + attribute \src "ls180.v:3857.7-3857.114" + cell $and $and$ls180.v:3857$354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3857$352_Y + connect \B $eq$ls180.v:3857$353_Y + connect \Y $and$ls180.v:3857$354_Y + end + attribute \src "ls180.v:3860.8-3860.73" + cell $and $and$ls180.v:3860$355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3860$355_Y + end + attribute \src "ls180.v:3860.7-3860.114" + cell $and $and$ls180.v:3860$357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3860$355_Y + connect \B $eq$ls180.v:3860$356_Y + connect \Y $and$ls180.v:3860$357_Y + end + attribute \src "ls180.v:3866.8-3866.73" + cell $and $and$ls180.v:3866$359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3866$359_Y + end + attribute \src "ls180.v:3866.7-3866.114" + cell $and $and$ls180.v:3866$361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3866$359_Y + connect \B $eq$ls180.v:3866$360_Y + connect \Y $and$ls180.v:3866$361_Y + end + attribute \src "ls180.v:3869.8-3869.73" + cell $and $and$ls180.v:3869$362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3869$362_Y + end + attribute \src "ls180.v:3869.7-3869.114" + cell $and $and$ls180.v:3869$364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3869$362_Y + connect \B $eq$ls180.v:3869$363_Y + connect \Y $and$ls180.v:3869$364_Y + end + attribute \src "ls180.v:3875.8-3875.73" + cell $and $and$ls180.v:3875$366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3875$366_Y + end + attribute \src "ls180.v:3875.7-3875.114" + cell $and $and$ls180.v:3875$368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3875$366_Y + connect \B $eq$ls180.v:3875$367_Y + connect \Y $and$ls180.v:3875$368_Y + end + attribute \src "ls180.v:3878.8-3878.73" + cell $and $and$ls180.v:3878$369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3878$369_Y + end + attribute \src "ls180.v:3878.7-3878.114" + cell $and $and$ls180.v:3878$371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3878$369_Y + connect \B $eq$ls180.v:3878$370_Y + connect \Y $and$ls180.v:3878$371_Y + end + attribute \src "ls180.v:3884.8-3884.73" + cell $and $and$ls180.v:3884$373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3884$373_Y + end + attribute \src "ls180.v:3884.7-3884.114" + cell $and $and$ls180.v:3884$375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3884$373_Y + connect \B $eq$ls180.v:3884$374_Y + connect \Y $and$ls180.v:3884$375_Y + end + attribute \src "ls180.v:3887.8-3887.73" + cell $and $and$ls180.v:3887$376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3887$376_Y + end + attribute \src "ls180.v:3887.7-3887.114" + cell $and $and$ls180.v:3887$378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3887$376_Y + connect \B $eq$ls180.v:3887$377_Y + connect \Y $and$ls180.v:3887$378_Y + end + attribute \src "ls180.v:3912.71-3912.151" + cell $and $and$ls180.v:3912$383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3912$382_Y + connect \Y $and$ls180.v:3912$383_Y + end + attribute \src "ls180.v:3912.70-3912.194" + cell $and $and$ls180.v:3912$385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3912$383_Y + connect \B $not$ls180.v:3912$384_Y + connect \Y $and$ls180.v:3912$385_Y + end + attribute \src "ls180.v:3912.41-3912.222" + cell $and $and$ls180.v:3912$388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cas_allowed + connect \B $or$ls180.v:3912$387_Y + connect \Y $and$ls180.v:3912$388_Y + end + attribute \src "ls180.v:3950.71-3950.151" + cell $and $and$ls180.v:3950$392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3950$391_Y + connect \Y $and$ls180.v:3950$392_Y + end + attribute \src "ls180.v:3950.70-3950.194" + cell $and $and$ls180.v:3950$394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3950$392_Y + connect \B $not$ls180.v:3950$393_Y + connect \Y $and$ls180.v:3950$394_Y + end + attribute \src "ls180.v:3950.41-3950.222" + cell $and $and$ls180.v:3950$397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cas_allowed + connect \B $or$ls180.v:3950$396_Y + connect \Y $and$ls180.v:3950$397_Y + end + attribute \src "ls180.v:3968.110-3968.179" + cell $and $and$ls180.v:3968$402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3968$401_Y + connect \Y $and$ls180.v:3968$402_Y + end + attribute \src "ls180.v:3968.185-3968.254" + cell $and $and$ls180.v:3968$405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3968$404_Y + connect \Y $and$ls180.v:3968$405_Y + end + attribute \src "ls180.v:3968.260-3968.329" + cell $and $and$ls180.v:3968$408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3968$407_Y + connect \Y $and$ls180.v:3968$408_Y + end + attribute \src "ls180.v:3968.41-3968.332" + cell $and $and$ls180.v:3968$411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3968$400_Y + connect \B $not$ls180.v:3968$410_Y + connect \Y $and$ls180.v:3968$411_Y + end + attribute \src "ls180.v:3968.40-3968.355" + cell $and $and$ls180.v:3968$412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3968$411_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:3968$412_Y + end + attribute \src "ls180.v:3969.34-3969.106" + cell $and $and$ls180.v:3969$415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3969$413_Y + connect \B $not$ls180.v:3969$414_Y + connect \Y $and$ls180.v:3969$415_Y + end + attribute \src "ls180.v:3973.110-3973.179" + cell $and $and$ls180.v:3973$418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3973$417_Y + connect \Y $and$ls180.v:3973$418_Y + end + attribute \src "ls180.v:3973.185-3973.254" + cell $and $and$ls180.v:3973$421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3973$420_Y + connect \Y $and$ls180.v:3973$421_Y + end + attribute \src "ls180.v:3973.260-3973.329" + cell $and $and$ls180.v:3973$424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3973$423_Y + connect \Y $and$ls180.v:3973$424_Y + end + attribute \src "ls180.v:3973.41-3973.332" + cell $and $and$ls180.v:3973$427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3973$416_Y + connect \B $not$ls180.v:3973$426_Y + connect \Y $and$ls180.v:3973$427_Y + end + attribute \src "ls180.v:3973.40-3973.355" + cell $and $and$ls180.v:3973$428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3973$427_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:3973$428_Y + end + attribute \src "ls180.v:3974.34-3974.106" + cell $and $and$ls180.v:3974$431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3974$429_Y + connect \B $not$ls180.v:3974$430_Y + connect \Y $and$ls180.v:3974$431_Y + end + attribute \src "ls180.v:3978.110-3978.179" + cell $and $and$ls180.v:3978$434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3978$433_Y + connect \Y $and$ls180.v:3978$434_Y + end + attribute \src "ls180.v:3978.185-3978.254" + cell $and $and$ls180.v:3978$437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3978$436_Y + connect \Y $and$ls180.v:3978$437_Y + end + attribute \src "ls180.v:3978.260-3978.329" + cell $and $and$ls180.v:3978$440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3978$439_Y + connect \Y $and$ls180.v:3978$440_Y + end + attribute \src "ls180.v:3978.41-3978.332" + cell $and $and$ls180.v:3978$443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3978$432_Y + connect \B $not$ls180.v:3978$442_Y + connect \Y $and$ls180.v:3978$443_Y + end + attribute \src "ls180.v:3978.40-3978.355" + cell $and $and$ls180.v:3978$444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3978$443_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:3978$444_Y + end + attribute \src "ls180.v:3979.34-3979.106" + cell $and $and$ls180.v:3979$447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3979$445_Y + connect \B $not$ls180.v:3979$446_Y + connect \Y $and$ls180.v:3979$447_Y + end + attribute \src "ls180.v:3983.110-3983.179" + cell $and $and$ls180.v:3983$450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3983$449_Y + connect \Y $and$ls180.v:3983$450_Y + end + attribute \src "ls180.v:3983.185-3983.254" + cell $and $and$ls180.v:3983$453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3983$452_Y + connect \Y $and$ls180.v:3983$453_Y + end + attribute \src "ls180.v:3983.260-3983.329" + cell $and $and$ls180.v:3983$456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3983$455_Y + connect \Y $and$ls180.v:3983$456_Y + end + attribute \src "ls180.v:3983.41-3983.332" + cell $and $and$ls180.v:3983$459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3983$448_Y + connect \B $not$ls180.v:3983$458_Y + connect \Y $and$ls180.v:3983$459_Y + end + attribute \src "ls180.v:3983.40-3983.355" + cell $and $and$ls180.v:3983$460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3983$459_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:3983$460_Y + end + attribute \src "ls180.v:3984.34-3984.106" + cell $and $and$ls180.v:3984$463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3984$461_Y + connect \B $not$ls180.v:3984$462_Y + connect \Y $and$ls180.v:3984$463_Y + end + attribute \src "ls180.v:3988.151-3988.220" + cell $and $and$ls180.v:3988$467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3988$466_Y + connect \Y $and$ls180.v:3988$467_Y + end + attribute \src "ls180.v:3988.226-3988.295" + cell $and $and$ls180.v:3988$470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3988$469_Y + connect \Y $and$ls180.v:3988$470_Y + end + attribute \src "ls180.v:3988.301-3988.370" + cell $and $and$ls180.v:3988$473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3988$472_Y + connect \Y $and$ls180.v:3988$473_Y + end + attribute \src "ls180.v:3988.82-3988.373" + cell $and $and$ls180.v:3988$476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3988$465_Y + connect \B $not$ls180.v:3988$475_Y + connect \Y $and$ls180.v:3988$476_Y + end + attribute \src "ls180.v:3988.43-3988.374" + cell $and $and$ls180.v:3988$477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3988$464_Y + connect \B $and$ls180.v:3988$476_Y + connect \Y $and$ls180.v:3988$477_Y + end + attribute \src "ls180.v:3988.42-3988.410" + cell $and $and$ls180.v:3988$478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3988$477_Y + connect \B \main_sdram_interface_bank0_ready + connect \Y $and$ls180.v:3988$478_Y + end + attribute \src "ls180.v:3988.525-3988.594" + cell $and $and$ls180.v:3988$483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3988$482_Y + connect \Y $and$ls180.v:3988$483_Y + end + attribute \src "ls180.v:3988.600-3988.669" + cell $and $and$ls180.v:3988$486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3988$485_Y + connect \Y $and$ls180.v:3988$486_Y + end + attribute \src "ls180.v:3988.675-3988.744" + cell $and $and$ls180.v:3988$489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3988$488_Y + connect \Y $and$ls180.v:3988$489_Y + end + attribute \src "ls180.v:3988.456-3988.747" + cell $and $and$ls180.v:3988$492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3988$481_Y + connect \B $not$ls180.v:3988$491_Y + connect \Y $and$ls180.v:3988$492_Y + end + attribute \src "ls180.v:3988.417-3988.748" + cell $and $and$ls180.v:3988$493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3988$480_Y + connect \B $and$ls180.v:3988$492_Y + connect \Y $and$ls180.v:3988$493_Y + end + attribute \src "ls180.v:3988.416-3988.784" + cell $and $and$ls180.v:3988$494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3988$493_Y + connect \B \main_sdram_interface_bank1_ready + connect \Y $and$ls180.v:3988$494_Y + end + attribute \src "ls180.v:3988.899-3988.968" + cell $and $and$ls180.v:3988$499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3988$498_Y + connect \Y $and$ls180.v:3988$499_Y + end + attribute \src "ls180.v:3988.974-3988.1043" + cell $and $and$ls180.v:3988$502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3988$501_Y + connect \Y $and$ls180.v:3988$502_Y + end + attribute \src "ls180.v:3988.1049-3988.1118" + cell $and $and$ls180.v:3988$505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3988$504_Y + connect \Y $and$ls180.v:3988$505_Y + end + attribute \src "ls180.v:3988.830-3988.1121" + cell $and $and$ls180.v:3988$508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3988$497_Y + connect \B $not$ls180.v:3988$507_Y + connect \Y $and$ls180.v:3988$508_Y + end + attribute \src "ls180.v:3988.791-3988.1122" + cell $and $and$ls180.v:3988$509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3988$496_Y + connect \B $and$ls180.v:3988$508_Y + connect \Y $and$ls180.v:3988$509_Y + end + attribute \src "ls180.v:3988.790-3988.1158" + cell $and $and$ls180.v:3988$510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3988$509_Y + connect \B \main_sdram_interface_bank2_ready + connect \Y $and$ls180.v:3988$510_Y + end + attribute \src "ls180.v:3988.1273-3988.1342" + cell $and $and$ls180.v:3988$515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3988$514_Y + connect \Y $and$ls180.v:3988$515_Y + end + attribute \src "ls180.v:3988.1348-3988.1417" + cell $and $and$ls180.v:3988$518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3988$517_Y + connect \Y $and$ls180.v:3988$518_Y + end + attribute \src "ls180.v:3988.1423-3988.1492" + cell $and $and$ls180.v:3988$521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3988$520_Y + connect \Y $and$ls180.v:3988$521_Y + end + attribute \src "ls180.v:3988.1204-3988.1495" + cell $and $and$ls180.v:3988$524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3988$513_Y + connect \B $not$ls180.v:3988$523_Y + connect \Y $and$ls180.v:3988$524_Y + end + attribute \src "ls180.v:3988.1165-3988.1496" + cell $and $and$ls180.v:3988$525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3988$512_Y + connect \B $and$ls180.v:3988$524_Y + connect \Y $and$ls180.v:3988$525_Y + end + attribute \src "ls180.v:3988.1164-3988.1532" + cell $and $and$ls180.v:3988$526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3988$525_Y + connect \B \main_sdram_interface_bank3_ready + connect \Y $and$ls180.v:3988$526_Y + end + attribute \src "ls180.v:4046.9-4046.46" + cell $and $and$ls180.v:4046$532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_stb + connect \B \main_wb_sdram_cyc + connect \Y $and$ls180.v:4046$532_Y + end + attribute \src "ls180.v:4064.9-4064.46" + cell $and $and$ls180.v:4064$539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_stb + connect \B \main_wb_sdram_cyc + connect \Y $and$ls180.v:4064$539_Y + end + attribute \src "ls180.v:4077.32-4077.75" + cell $and $and$ls180.v:4077$543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_cyc + connect \B \main_litedram_wb_stb + connect \Y $and$ls180.v:4077$543_Y + end + attribute \src "ls180.v:4077.31-4077.99" + cell $and $and$ls180.v:4077$545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4077$543_Y + connect \B $not$ls180.v:4077$544_Y + connect \Y $and$ls180.v:4077$545_Y + end + attribute \src "ls180.v:4078.34-4078.102" + cell $and $and$ls180.v:4078$547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4078$546_Y + connect \B \main_port_cmd_payload_we + connect \Y $and$ls180.v:4078$547_Y + end + attribute \src "ls180.v:4078.33-4078.128" + cell $and $and$ls180.v:4078$549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4078$547_Y + connect \B $not$ls180.v:4078$548_Y + connect \Y $and$ls180.v:4078$549_Y + end + attribute \src "ls180.v:4079.33-4079.104" + cell $and $and$ls180.v:4079$552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4079$550_Y + connect \B $not$ls180.v:4079$551_Y + connect \Y $and$ls180.v:4079$552_Y + end + attribute \src "ls180.v:4080.49-4080.85" + cell $and $and$ls180.v:4080$553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \B \main_ack_wdata + connect \Y $and$ls180.v:4080$553_Y + end + attribute \src "ls180.v:4080.90-4080.129" + cell $and $and$ls180.v:4080$555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4080$554_Y + connect \B \main_ack_rdata + connect \Y $and$ls180.v:4080$555_Y + end + attribute \src "ls180.v:4080.32-4080.131" + cell $and $and$ls180.v:4080$557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_ack_cmd + connect \B $or$ls180.v:4080$556_Y + connect \Y $and$ls180.v:4080$557_Y + end + attribute \src "ls180.v:4081.25-4081.66" + cell $and $and$ls180.v:4081$558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_port_cmd_ready + connect \Y $and$ls180.v:4081$558_Y + end + attribute \src "ls180.v:4082.27-4082.72" + cell $and $and$ls180.v:4082$560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_wdata_valid + connect \B \main_port_wdata_ready + connect \Y $and$ls180.v:4082$560_Y + end + attribute \src "ls180.v:4083.26-4083.71" + cell $and $and$ls180.v:4083$562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_rdata_valid + connect \B \main_port_rdata_ready + connect \Y $and$ls180.v:4083$562_Y + end + attribute \src "ls180.v:4112.64-4112.88" + cell $and $and$ls180.v:4112$568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B \main_uart_rxtx_we + connect \Y $and$ls180.v:4112$568_Y + end + attribute \src "ls180.v:4116.7-4116.78" + cell $and $and$ls180.v:4116$572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_re + connect \B \main_uart_eventmanager_pending_r [0] + connect \Y $and$ls180.v:4116$572_Y + end + attribute \src "ls180.v:4127.7-4127.78" + cell $and $and$ls180.v:4127$575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_re + connect \B \main_uart_eventmanager_pending_r [1] + connect \Y $and$ls180.v:4127$575_Y + end + attribute \src "ls180.v:4136.26-4136.97" + cell $and $and$ls180.v:4136$577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_w [0] + connect \B \main_uart_eventmanager_storage [0] + connect \Y $and$ls180.v:4136$577_Y + end + attribute \src "ls180.v:4136.102-4136.173" + cell $and $and$ls180.v:4136$578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_w [1] + connect \B \main_uart_eventmanager_storage [1] + connect \Y $and$ls180.v:4136$578_Y + end + attribute \src "ls180.v:4151.41-4151.133" + cell $and $and$ls180.v:4151$582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_readable + connect \B $or$ls180.v:4151$581_Y + connect \Y $and$ls180.v:4151$582_Y + end + attribute \src "ls180.v:4162.39-4162.136" + cell $and $and$ls180.v:4162$587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B $or$ls180.v:4162$586_Y + connect \Y $and$ls180.v:4162$587_Y + end + attribute \src "ls180.v:4163.37-4163.104" + cell $and $and$ls180.v:4163$588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_readable + connect \B \main_uart_tx_fifo_syncfifo_re + connect \Y $and$ls180.v:4163$588_Y + end + attribute \src "ls180.v:4181.41-4181.133" + cell $and $and$ls180.v:4181$593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_readable + connect \B $or$ls180.v:4181$592_Y + connect \Y $and$ls180.v:4181$593_Y + end + attribute \src "ls180.v:4192.39-4192.136" + cell $and $and$ls180.v:4192$598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B $or$ls180.v:4192$597_Y + connect \Y $and$ls180.v:4192$598_Y + end + attribute \src "ls180.v:4193.37-4193.104" + cell $and $and$ls180.v:4193$599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_readable + connect \B \main_uart_rx_fifo_syncfifo_re + connect \Y $and$ls180.v:4193$599_Y + end + attribute \src "ls180.v:4322.33-4322.86" + cell $and $and$ls180.v:4322$633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk1 + connect \B $not$ls180.v:4322$632_Y + connect \Y $and$ls180.v:4322$633_Y + end + attribute \src "ls180.v:4426.9-4426.68" + cell $and $and$ls180.v:4426$642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_sink_valid + connect \B \main_sdphy_cmdw_pads_out_ready + connect \Y $and$ls180.v:4426$642_Y + end + attribute \src "ls180.v:4446.53-4446.145" + cell $and $and$ls180.v:4446$645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_pads_in_valid + connect \B $or$ls180.v:4446$644_Y + connect \Y $and$ls180.v:4446$645_Y + end + attribute \src "ls180.v:4465.52-4465.137" + cell $and $and$ls180.v:4465$648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:4465$648_Y + end + attribute \src "ls180.v:4506.9-4506.68" + cell $and $and$ls180.v:4506$656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_valid + connect \B \main_sdphy_cmdr_source_ready + connect \Y $and$ls180.v:4506$656_Y + end + attribute \src "ls180.v:4544.9-4544.68" + cell $and $and$ls180.v:4544$662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_valid + connect \B \main_sdphy_cmdr_source_ready + connect \Y $and$ls180.v:4544$662_Y + end + attribute \src "ls180.v:4553.10-4553.69" + cell $and $and$ls180.v:4553$663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_sink_valid + connect \B \main_sdphy_cmdr_pads_out_ready + connect \Y $and$ls180.v:4553$663_Y + end + attribute \src "ls180.v:4553.9-4553.93" + cell $and $and$ls180.v:4553$664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4553$663_Y + connect \B \main_sdphy_cmdw_done + connect \Y $and$ls180.v:4553$664_Y + end + attribute \src "ls180.v:4573.54-4573.117" + cell $and $and$ls180.v:4573$666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_pads_in_valid + connect \B \main_sdphy_dataw_crcr_run + connect \Y $and$ls180.v:4573$666_Y + end + attribute \src "ls180.v:4592.53-4592.140" + cell $and $and$ls180.v:4592$669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:4592$669_Y + end + attribute \src "ls180.v:4689.9-4689.70" + cell $and $and$ls180.v:4689$679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \B \main_sdphy_dataw_pads_out_ready + connect \Y $and$ls180.v:4689$679_Y + end + attribute \src "ls180.v:4707.55-4707.120" + cell $and $and$ls180.v:4707$681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_pads_in_valid + connect \B \main_sdphy_datar_datar_run + connect \Y $and$ls180.v:4707$681_Y + end + attribute \src "ls180.v:4726.54-4726.143" + cell $and $and$ls180.v:4726$684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:4726$684_Y + end + attribute \src "ls180.v:4808.9-4808.70" + cell $and $and$ls180.v:4808$699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_valid + connect \B \main_sdphy_datar_source_ready + connect \Y $and$ls180.v:4808$699_Y + end + attribute \src "ls180.v:4815.9-4815.70" + cell $and $and$ls180.v:4815$700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_sink_valid + connect \B \main_sdphy_datar_pads_out_ready + connect \Y $and$ls180.v:4815$700_Y + end + attribute \src "ls180.v:4896.48-4896.124" + cell $and $and$ls180.v:4896$823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:4896$823_Y + end + attribute \src "ls180.v:4896.47-4896.165" + cell $and $and$ls180.v:4896$824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4896$823_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4896$824_Y + end + attribute \src "ls180.v:4897.50-4897.127" + cell $and $and$ls180.v:4897$825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4897$825_Y + end + attribute \src "ls180.v:4899.48-4899.124" + cell $and $and$ls180.v:4899$826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:4899$826_Y + end + attribute \src "ls180.v:4899.47-4899.165" + cell $and $and$ls180.v:4899$827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4899$826_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4899$827_Y + end + attribute \src "ls180.v:4900.50-4900.127" + cell $and $and$ls180.v:4900$828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4900$828_Y + end + attribute \src "ls180.v:4902.48-4902.124" + cell $and $and$ls180.v:4902$829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:4902$829_Y + end + attribute \src "ls180.v:4902.47-4902.165" + cell $and $and$ls180.v:4902$830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4902$829_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4902$830_Y + end + attribute \src "ls180.v:4903.50-4903.127" + cell $and $and$ls180.v:4903$831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4903$831_Y + end + attribute \src "ls180.v:4905.48-4905.124" + cell $and $and$ls180.v:4905$832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:4905$832_Y + end + attribute \src "ls180.v:4905.47-4905.165" + cell $and $and$ls180.v:4905$833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4905$832_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4905$833_Y + end + attribute \src "ls180.v:4906.50-4906.127" + cell $and $and$ls180.v:4906$834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4906$834_Y + end + attribute \src "ls180.v:5019.10-5019.86" + cell $and $and$ls180.v:5019$883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_last + connect \Y $and$ls180.v:5019$883_Y + end + attribute \src "ls180.v:5019.9-5019.127" + cell $and $and$ls180.v:5019$884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5019$883_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5019$884_Y + end + attribute \src "ls180.v:5029.9-5029.152" + cell $and $and$ls180.v:5029$888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:5029$886_Y + connect \B $eq$ls180.v:5029$887_Y + connect \Y $and$ls180.v:5029$888_Y + end + attribute \src "ls180.v:5029.8-5029.226" + cell $and $and$ls180.v:5029$890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5029$888_Y + connect \B $eq$ls180.v:5029$889_Y + connect \Y $and$ls180.v:5029$890_Y + end + attribute \src "ls180.v:5029.7-5029.300" + cell $and $and$ls180.v:5029$892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5029$890_Y + connect \B $eq$ls180.v:5029$891_Y + connect \Y $and$ls180.v:5029$892_Y + end + attribute \src "ls180.v:5034.49-5034.124" + cell $and $and$ls180.v:5034$893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5034$893_Y + end + attribute \src "ls180.v:5044.49-5044.124" + cell $and $and$ls180.v:5044$896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5044$896_Y + end + attribute \src "ls180.v:5054.49-5054.124" + cell $and $and$ls180.v:5054$899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5054$899_Y + end + attribute \src "ls180.v:5064.49-5064.124" + cell $and $and$ls180.v:5064$902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5064$902_Y + end + attribute \src "ls180.v:5076.7-5076.84" + cell $and $and$ls180.v:5076$907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B $gt$ls180.v:5076$906_Y + connect \Y $and$ls180.v:5076$907_Y + end + attribute \src "ls180.v:5194.9-5194.64" + cell $and $and$ls180.v:5194$956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_sink_valid + connect \B \main_sdphy_cmdw_sink_ready + connect \Y $and$ls180.v:5194$956_Y + end + attribute \src "ls180.v:5246.10-5246.66" + cell $and $and$ls180.v:5246$965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \B \main_sdphy_dataw_sink_last + connect \Y $and$ls180.v:5246$965_Y + end + attribute \src "ls180.v:5246.9-5246.97" + cell $and $and$ls180.v:5246$966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5246$965_Y + connect \B \main_sdphy_dataw_sink_ready + connect \Y $and$ls180.v:5246$966_Y + end + attribute \src "ls180.v:5272.11-5272.71" + cell $and $and$ls180.v:5272$974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_last + connect \B \main_sdphy_datar_source_ready + connect \Y $and$ls180.v:5272$974_Y + end + attribute \src "ls180.v:5356.43-5356.152" + cell $and $and$ls180.v:5356$982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B $or$ls180.v:5356$981_Y + connect \Y $and$ls180.v:5356$982_Y + end + attribute \src "ls180.v:5357.41-5357.116" + cell $and $and$ls180.v:5357$983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_readable + connect \B \main_sdblock2mem_fifo_syncfifo_re + connect \Y $and$ls180.v:5357$983_Y + end + attribute \src "ls180.v:5369.48-5369.125" + cell $and $and$ls180.v:5369$988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:5369$988_Y + end + attribute \src "ls180.v:5396.9-5396.102" + cell $and $and$ls180.v:5396$992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid + connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready + connect \Y $and$ls180.v:5396$992_Y + end + attribute \src "ls180.v:5469.9-5469.58" + cell $and $and$ls180.v:5469$998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_bus_stb + connect \B \main_interface1_bus_ack + connect \Y $and$ls180.v:5469$998_Y + end + attribute \src "ls180.v:5522.51-5522.123" + cell $and $and$ls180.v:5522$1006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_sink_first + connect \B \main_sdmem2block_converter_first + connect \Y $and$ls180.v:5522$1006_Y + end + attribute \src "ls180.v:5523.50-5523.120" + cell $and $and$ls180.v:5523$1007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_sink_last + connect \B \main_sdmem2block_converter_last + connect \Y $and$ls180.v:5523$1007_Y + end + attribute \src "ls180.v:5524.49-5524.122" + cell $and $and$ls180.v:5524$1008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_last + connect \B \main_sdmem2block_converter_source_ready + connect \Y $and$ls180.v:5524$1008_Y + end + attribute \src "ls180.v:5564.43-5564.152" + cell $and $and$ls180.v:5564$1013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B $or$ls180.v:5564$1012_Y + connect \Y $and$ls180.v:5564$1013_Y + end + attribute \src "ls180.v:5565.41-5565.116" + cell $and $and$ls180.v:5565$1014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_readable + connect \B \main_sdmem2block_fifo_syncfifo_re + connect \Y $and$ls180.v:5565$1014_Y + end + attribute \src "ls180.v:5656.9-5656.76" + cell $and $and$ls180.v:5656$1026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_cyc + connect \B \builder_libresocsim_wishbone_stb + connect \Y $and$ls180.v:5656$1026_Y + end + attribute \src "ls180.v:5659.44-5659.120" + cell $and $and$ls180.v:5659$1028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_we + connect \B $ne$ls180.v:5659$1027_Y + connect \Y $and$ls180.v:5659$1028_Y + end + attribute \src "ls180.v:5679.63-5679.107" + cell $and $and$ls180.v:5679$1030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5679$1029_Y + connect \Y $and$ls180.v:5679$1030_Y + end + attribute \src "ls180.v:5680.63-5680.107" + cell $and $and$ls180.v:5680$1032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5680$1031_Y + connect \Y $and$ls180.v:5680$1032_Y + end + attribute \src "ls180.v:5681.63-5681.107" + cell $and $and$ls180.v:5681$1034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5681$1033_Y + connect \Y $and$ls180.v:5681$1034_Y + end + attribute \src "ls180.v:5682.35-5682.79" + cell $and $and$ls180.v:5682$1036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5682$1035_Y + connect \Y $and$ls180.v:5682$1036_Y + end + attribute \src "ls180.v:5683.35-5683.79" + cell $and $and$ls180.v:5683$1038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5683$1037_Y + connect \Y $and$ls180.v:5683$1038_Y + end + attribute \src "ls180.v:5684.63-5684.107" + cell $and $and$ls180.v:5684$1040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5684$1039_Y + connect \Y $and$ls180.v:5684$1040_Y + end + attribute \src "ls180.v:5685.63-5685.107" + cell $and $and$ls180.v:5685$1042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5685$1041_Y + connect \Y $and$ls180.v:5685$1042_Y + end + attribute \src "ls180.v:5686.63-5686.107" + cell $and $and$ls180.v:5686$1044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5686$1043_Y + connect \Y $and$ls180.v:5686$1044_Y + end + attribute \src "ls180.v:5687.35-5687.79" + cell $and $and$ls180.v:5687$1046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5687$1045_Y + connect \Y $and$ls180.v:5687$1046_Y + end + attribute \src "ls180.v:5688.35-5688.79" + cell $and $and$ls180.v:5688$1048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5688$1047_Y + connect \Y $and$ls180.v:5688$1048_Y + end + attribute \src "ls180.v:5733.40-5733.81" + cell $and $and$ls180.v:5733$1055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [0] + connect \Y $and$ls180.v:5733$1055_Y + end + attribute \src "ls180.v:5734.50-5734.91" + cell $and $and$ls180.v:5734$1056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [1] + connect \Y $and$ls180.v:5734$1056_Y + end + attribute \src "ls180.v:5735.50-5735.91" + cell $and $and$ls180.v:5735$1057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [2] + connect \Y $and$ls180.v:5735$1057_Y + end + attribute \src "ls180.v:5736.29-5736.70" + cell $and $and$ls180.v:5736$1058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [3] + connect \Y $and$ls180.v:5736$1058_Y + end + attribute \src "ls180.v:5737.44-5737.85" + cell $and $and$ls180.v:5737$1059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [4] + connect \Y $and$ls180.v:5737$1059_Y + end + attribute \src "ls180.v:5739.25-5739.64" + cell $and $and$ls180.v:5739$1064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_stb + connect \B \builder_shared_cyc + connect \Y $and$ls180.v:5739$1064_Y + end + attribute \src "ls180.v:5739.24-5739.89" + cell $and $and$ls180.v:5739$1066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5739$1064_Y + connect \B $not$ls180.v:5739$1065_Y + connect \Y $and$ls180.v:5739$1066_Y + end + attribute \src "ls180.v:5745.31-5745.92" + cell $and $and$ls180.v:5745$1072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } + connect \B \main_libresocsim_ram_bus_dat_r + connect \Y $and$ls180.v:5745$1072_Y + end + attribute \src "ls180.v:5745.97-5745.168" + cell $and $and$ls180.v:5745$1073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } + connect \B \main_libresocsim_libresoc_xics_icp_dat_r + connect \Y $and$ls180.v:5745$1073_Y + end + attribute \src "ls180.v:5745.174-5745.245" + cell $and $and$ls180.v:5745$1075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } + connect \B \main_libresocsim_libresoc_xics_ics_dat_r + connect \Y $and$ls180.v:5745$1075_Y + end + attribute \src "ls180.v:5745.251-5745.301" + cell $and $and$ls180.v:5745$1077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } + connect \B \main_wb_sdram_dat_r + connect \Y $and$ls180.v:5745$1077_Y + end + attribute \src "ls180.v:5745.307-5745.372" + cell $and $and$ls180.v:5745$1079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } + connect \B \builder_libresocsim_wishbone_dat_r + connect \Y $and$ls180.v:5745$1079_Y + end + attribute \src "ls180.v:5755.39-5755.92" + cell $and $and$ls180.v:5755$1083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5755$1083_Y + end + attribute \src "ls180.v:5755.38-5755.142" + cell $and $and$ls180.v:5755$1085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5755$1083_Y + connect \B $eq$ls180.v:5755$1084_Y + connect \Y $and$ls180.v:5755$1085_Y + end + attribute \src "ls180.v:5756.39-5756.95" + cell $and $and$ls180.v:5756$1087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5756$1086_Y + connect \Y $and$ls180.v:5756$1087_Y + end + attribute \src "ls180.v:5756.38-5756.145" + cell $and $and$ls180.v:5756$1089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5756$1087_Y + connect \B $eq$ls180.v:5756$1088_Y + connect \Y $and$ls180.v:5756$1089_Y + end + attribute \src "ls180.v:5758.41-5758.94" + cell $and $and$ls180.v:5758$1090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5758$1090_Y + end + attribute \src "ls180.v:5758.40-5758.144" + cell $and $and$ls180.v:5758$1092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5758$1090_Y + connect \B $eq$ls180.v:5758$1091_Y + connect \Y $and$ls180.v:5758$1092_Y + end + attribute \src "ls180.v:5759.41-5759.97" + cell $and $and$ls180.v:5759$1094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5759$1093_Y + connect \Y $and$ls180.v:5759$1094_Y + end + attribute \src "ls180.v:5759.40-5759.147" + cell $and $and$ls180.v:5759$1096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5759$1094_Y + connect \B $eq$ls180.v:5759$1095_Y + connect \Y $and$ls180.v:5759$1096_Y + end + attribute \src "ls180.v:5761.41-5761.94" + cell $and $and$ls180.v:5761$1097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5761$1097_Y + end + attribute \src "ls180.v:5761.40-5761.144" + cell $and $and$ls180.v:5761$1099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5761$1097_Y + connect \B $eq$ls180.v:5761$1098_Y + connect \Y $and$ls180.v:5761$1099_Y + end + attribute \src "ls180.v:5762.41-5762.97" + cell $and $and$ls180.v:5762$1101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5762$1100_Y + connect \Y $and$ls180.v:5762$1101_Y + end + attribute \src "ls180.v:5762.40-5762.147" + cell $and $and$ls180.v:5762$1103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5762$1101_Y + connect \B $eq$ls180.v:5762$1102_Y + connect \Y $and$ls180.v:5762$1103_Y + end + attribute \src "ls180.v:5764.41-5764.94" + cell $and $and$ls180.v:5764$1104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5764$1104_Y + end + attribute \src "ls180.v:5764.40-5764.144" + cell $and $and$ls180.v:5764$1106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5764$1104_Y + connect \B $eq$ls180.v:5764$1105_Y + connect \Y $and$ls180.v:5764$1106_Y + end + attribute \src "ls180.v:5765.41-5765.97" + cell $and $and$ls180.v:5765$1108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5765$1107_Y + connect \Y $and$ls180.v:5765$1108_Y + end + attribute \src "ls180.v:5765.40-5765.147" + cell $and $and$ls180.v:5765$1110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5765$1108_Y + connect \B $eq$ls180.v:5765$1109_Y + connect \Y $and$ls180.v:5765$1110_Y + end + attribute \src "ls180.v:5767.41-5767.94" + cell $and $and$ls180.v:5767$1111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5767$1111_Y + end + attribute \src "ls180.v:5767.40-5767.144" + cell $and $and$ls180.v:5767$1113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5767$1111_Y + connect \B $eq$ls180.v:5767$1112_Y + connect \Y $and$ls180.v:5767$1113_Y + end + attribute \src "ls180.v:5768.41-5768.97" + cell $and $and$ls180.v:5768$1115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5768$1114_Y + connect \Y $and$ls180.v:5768$1115_Y + end + attribute \src "ls180.v:5768.40-5768.147" + cell $and $and$ls180.v:5768$1117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5768$1115_Y + connect \B $eq$ls180.v:5768$1116_Y + connect \Y $and$ls180.v:5768$1117_Y + end + attribute \src "ls180.v:5770.44-5770.97" + cell $and $and$ls180.v:5770$1118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5770$1118_Y + end + attribute \src "ls180.v:5770.43-5770.147" + cell $and $and$ls180.v:5770$1120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5770$1118_Y + connect \B $eq$ls180.v:5770$1119_Y + connect \Y $and$ls180.v:5770$1120_Y + end + attribute \src "ls180.v:5771.44-5771.100" + cell $and $and$ls180.v:5771$1122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5771$1121_Y + connect \Y $and$ls180.v:5771$1122_Y + end + attribute \src "ls180.v:5771.43-5771.150" + cell $and $and$ls180.v:5771$1124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5771$1122_Y + connect \B $eq$ls180.v:5771$1123_Y + connect \Y $and$ls180.v:5771$1124_Y + end + attribute \src "ls180.v:5773.44-5773.97" + cell $and $and$ls180.v:5773$1125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5773$1125_Y + end + attribute \src "ls180.v:5773.43-5773.147" + cell $and $and$ls180.v:5773$1127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5773$1125_Y + connect \B $eq$ls180.v:5773$1126_Y + connect \Y $and$ls180.v:5773$1127_Y + end + attribute \src "ls180.v:5774.44-5774.100" + cell $and $and$ls180.v:5774$1129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5774$1128_Y + connect \Y $and$ls180.v:5774$1129_Y + end + attribute \src "ls180.v:5774.43-5774.150" + cell $and $and$ls180.v:5774$1131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5774$1129_Y + connect \B $eq$ls180.v:5774$1130_Y + connect \Y $and$ls180.v:5774$1131_Y + end + attribute \src "ls180.v:5776.44-5776.97" + cell $and $and$ls180.v:5776$1132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5776$1132_Y + end + attribute \src "ls180.v:5776.43-5776.147" + cell $and $and$ls180.v:5776$1134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5776$1132_Y + connect \B $eq$ls180.v:5776$1133_Y + connect \Y $and$ls180.v:5776$1134_Y + end + attribute \src "ls180.v:5777.44-5777.100" + cell $and $and$ls180.v:5777$1136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5777$1135_Y + connect \Y $and$ls180.v:5777$1136_Y + end + attribute \src "ls180.v:5777.43-5777.150" + cell $and $and$ls180.v:5777$1138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5777$1136_Y + connect \B $eq$ls180.v:5777$1137_Y + connect \Y $and$ls180.v:5777$1138_Y + end + attribute \src "ls180.v:5779.44-5779.97" + cell $and $and$ls180.v:5779$1139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5779$1139_Y + end + attribute \src "ls180.v:5779.43-5779.147" + cell $and $and$ls180.v:5779$1141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5779$1139_Y + connect \B $eq$ls180.v:5779$1140_Y + connect \Y $and$ls180.v:5779$1141_Y + end + attribute \src "ls180.v:5780.44-5780.100" + cell $and $and$ls180.v:5780$1143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5780$1142_Y + connect \Y $and$ls180.v:5780$1143_Y + end + attribute \src "ls180.v:5780.43-5780.150" + cell $and $and$ls180.v:5780$1145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5780$1143_Y + connect \B $eq$ls180.v:5780$1144_Y + connect \Y $and$ls180.v:5780$1145_Y + end + attribute \src "ls180.v:5793.36-5793.89" + cell $and $and$ls180.v:5793$1147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5793$1147_Y + end + attribute \src "ls180.v:5793.35-5793.139" + cell $and $and$ls180.v:5793$1149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5793$1147_Y + connect \B $eq$ls180.v:5793$1148_Y + connect \Y $and$ls180.v:5793$1149_Y + end + attribute \src "ls180.v:5794.36-5794.92" + cell $and $and$ls180.v:5794$1151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5794$1150_Y + connect \Y $and$ls180.v:5794$1151_Y + end + attribute \src "ls180.v:5794.35-5794.142" + cell $and $and$ls180.v:5794$1153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5794$1151_Y + connect \B $eq$ls180.v:5794$1152_Y + connect \Y $and$ls180.v:5794$1153_Y + end + attribute \src "ls180.v:5796.36-5796.89" + cell $and $and$ls180.v:5796$1154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5796$1154_Y + end + attribute \src "ls180.v:5796.35-5796.139" + cell $and $and$ls180.v:5796$1156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5796$1154_Y + connect \B $eq$ls180.v:5796$1155_Y + connect \Y $and$ls180.v:5796$1156_Y + end + attribute \src "ls180.v:5797.36-5797.92" + cell $and $and$ls180.v:5797$1158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5797$1157_Y + connect \Y $and$ls180.v:5797$1158_Y + end + attribute \src "ls180.v:5797.35-5797.142" + cell $and $and$ls180.v:5797$1160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5797$1158_Y + connect \B $eq$ls180.v:5797$1159_Y + connect \Y $and$ls180.v:5797$1160_Y + end + attribute \src "ls180.v:5799.36-5799.89" + cell $and $and$ls180.v:5799$1161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5799$1161_Y + end + attribute \src "ls180.v:5799.35-5799.139" + cell $and $and$ls180.v:5799$1163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5799$1161_Y + connect \B $eq$ls180.v:5799$1162_Y + connect \Y $and$ls180.v:5799$1163_Y + end + attribute \src "ls180.v:5800.36-5800.92" + cell $and $and$ls180.v:5800$1165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5800$1164_Y + connect \Y $and$ls180.v:5800$1165_Y + end + attribute \src "ls180.v:5800.35-5800.142" + cell $and $and$ls180.v:5800$1167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5800$1165_Y + connect \B $eq$ls180.v:5800$1166_Y + connect \Y $and$ls180.v:5800$1167_Y + end + attribute \src "ls180.v:5802.36-5802.89" + cell $and $and$ls180.v:5802$1168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5802$1168_Y + end + attribute \src "ls180.v:5802.35-5802.139" + cell $and $and$ls180.v:5802$1170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5802$1168_Y + connect \B $eq$ls180.v:5802$1169_Y + connect \Y $and$ls180.v:5802$1170_Y + end + attribute \src "ls180.v:5803.36-5803.92" + cell $and $and$ls180.v:5803$1172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5803$1171_Y + connect \Y $and$ls180.v:5803$1172_Y + end + attribute \src "ls180.v:5803.35-5803.142" + cell $and $and$ls180.v:5803$1174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5803$1172_Y + connect \B $eq$ls180.v:5803$1173_Y + connect \Y $and$ls180.v:5803$1174_Y + end + attribute \src "ls180.v:5805.37-5805.90" + cell $and $and$ls180.v:5805$1175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5805$1175_Y + end + attribute \src "ls180.v:5805.36-5805.140" + cell $and $and$ls180.v:5805$1177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5805$1175_Y + connect \B $eq$ls180.v:5805$1176_Y + connect \Y $and$ls180.v:5805$1177_Y + end + attribute \src "ls180.v:5806.37-5806.93" + cell $and $and$ls180.v:5806$1179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5806$1178_Y + connect \Y $and$ls180.v:5806$1179_Y + end + attribute \src "ls180.v:5806.36-5806.143" + cell $and $and$ls180.v:5806$1181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5806$1179_Y + connect \B $eq$ls180.v:5806$1180_Y + connect \Y $and$ls180.v:5806$1181_Y + end + attribute \src "ls180.v:5808.37-5808.90" + cell $and $and$ls180.v:5808$1182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5808$1182_Y + end + attribute \src "ls180.v:5808.36-5808.140" + cell $and $and$ls180.v:5808$1184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5808$1182_Y + connect \B $eq$ls180.v:5808$1183_Y + connect \Y $and$ls180.v:5808$1184_Y + end + attribute \src "ls180.v:5809.37-5809.93" + cell $and $and$ls180.v:5809$1186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5809$1185_Y + connect \Y $and$ls180.v:5809$1186_Y + end + attribute \src "ls180.v:5809.36-5809.143" + cell $and $and$ls180.v:5809$1188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5809$1186_Y + connect \B $eq$ls180.v:5809$1187_Y + connect \Y $and$ls180.v:5809$1188_Y + end + attribute \src "ls180.v:5819.35-5819.88" + cell $and $and$ls180.v:5819$1190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5819$1190_Y + end + attribute \src "ls180.v:5819.34-5819.136" + cell $and $and$ls180.v:5819$1192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5819$1190_Y + connect \B $eq$ls180.v:5819$1191_Y + connect \Y $and$ls180.v:5819$1192_Y + end + attribute \src "ls180.v:5820.35-5820.91" + cell $and $and$ls180.v:5820$1194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5820$1193_Y + connect \Y $and$ls180.v:5820$1194_Y + end + attribute \src "ls180.v:5820.34-5820.139" + cell $and $and$ls180.v:5820$1196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5820$1194_Y + connect \B $eq$ls180.v:5820$1195_Y + connect \Y $and$ls180.v:5820$1196_Y + end + attribute \src "ls180.v:5822.34-5822.87" + cell $and $and$ls180.v:5822$1197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5822$1197_Y + end + attribute \src "ls180.v:5822.33-5822.135" + cell $and $and$ls180.v:5822$1199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5822$1197_Y + connect \B $eq$ls180.v:5822$1198_Y + connect \Y $and$ls180.v:5822$1199_Y + end + attribute \src "ls180.v:5823.34-5823.90" + cell $and $and$ls180.v:5823$1201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5823$1200_Y + connect \Y $and$ls180.v:5823$1201_Y + end + attribute \src "ls180.v:5823.33-5823.138" + cell $and $and$ls180.v:5823$1203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5823$1201_Y + connect \B $eq$ls180.v:5823$1202_Y + connect \Y $and$ls180.v:5823$1203_Y + end + attribute \src "ls180.v:5833.40-5833.93" + cell $and $and$ls180.v:5833$1205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5833$1205_Y + end + attribute \src "ls180.v:5833.39-5833.143" + cell $and $and$ls180.v:5833$1207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5833$1205_Y + connect \B $eq$ls180.v:5833$1206_Y + connect \Y $and$ls180.v:5833$1207_Y + end + attribute \src "ls180.v:5834.40-5834.96" + cell $and $and$ls180.v:5834$1209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5834$1208_Y + connect \Y $and$ls180.v:5834$1209_Y + end + attribute \src "ls180.v:5834.39-5834.146" + cell $and $and$ls180.v:5834$1211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5834$1209_Y + connect \B $eq$ls180.v:5834$1210_Y + connect \Y $and$ls180.v:5834$1211_Y + end + attribute \src "ls180.v:5836.39-5836.92" + cell $and $and$ls180.v:5836$1212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5836$1212_Y + end + attribute \src "ls180.v:5836.38-5836.142" + cell $and $and$ls180.v:5836$1214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5836$1212_Y + connect \B $eq$ls180.v:5836$1213_Y + connect \Y $and$ls180.v:5836$1214_Y + end + attribute \src "ls180.v:5837.39-5837.95" + cell $and $and$ls180.v:5837$1216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5837$1215_Y + connect \Y $and$ls180.v:5837$1216_Y + end + attribute \src "ls180.v:5837.38-5837.145" + cell $and $and$ls180.v:5837$1218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5837$1216_Y + connect \B $eq$ls180.v:5837$1217_Y + connect \Y $and$ls180.v:5837$1218_Y + end + attribute \src "ls180.v:5839.39-5839.92" + cell $and $and$ls180.v:5839$1219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5839$1219_Y + end + attribute \src "ls180.v:5839.38-5839.142" + cell $and $and$ls180.v:5839$1221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5839$1219_Y + connect \B $eq$ls180.v:5839$1220_Y + connect \Y $and$ls180.v:5839$1221_Y + end + attribute \src "ls180.v:5840.39-5840.95" + cell $and $and$ls180.v:5840$1223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5840$1222_Y + connect \Y $and$ls180.v:5840$1223_Y + end + attribute \src "ls180.v:5840.38-5840.145" + cell $and $and$ls180.v:5840$1225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5840$1223_Y + connect \B $eq$ls180.v:5840$1224_Y + connect \Y $and$ls180.v:5840$1225_Y + end + attribute \src "ls180.v:5842.39-5842.92" + cell $and $and$ls180.v:5842$1226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5842$1226_Y + end + attribute \src "ls180.v:5842.38-5842.142" + cell $and $and$ls180.v:5842$1228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5842$1226_Y + connect \B $eq$ls180.v:5842$1227_Y + connect \Y $and$ls180.v:5842$1228_Y + end + attribute \src "ls180.v:5843.39-5843.95" + cell $and $and$ls180.v:5843$1230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5843$1229_Y + connect \Y $and$ls180.v:5843$1230_Y + end + attribute \src "ls180.v:5843.38-5843.145" + cell $and $and$ls180.v:5843$1232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5843$1230_Y + connect \B $eq$ls180.v:5843$1231_Y + connect \Y $and$ls180.v:5843$1232_Y + end + attribute \src "ls180.v:5845.39-5845.92" + cell $and $and$ls180.v:5845$1233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5845$1233_Y + end + attribute \src "ls180.v:5845.38-5845.142" + cell $and $and$ls180.v:5845$1235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5845$1233_Y + connect \B $eq$ls180.v:5845$1234_Y + connect \Y $and$ls180.v:5845$1235_Y + end + attribute \src "ls180.v:5846.39-5846.95" + cell $and $and$ls180.v:5846$1237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5846$1236_Y + connect \Y $and$ls180.v:5846$1237_Y + end + attribute \src "ls180.v:5846.38-5846.145" + cell $and $and$ls180.v:5846$1239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5846$1237_Y + connect \B $eq$ls180.v:5846$1238_Y + connect \Y $and$ls180.v:5846$1239_Y + end + attribute \src "ls180.v:5848.40-5848.93" + cell $and $and$ls180.v:5848$1240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5848$1240_Y + end + attribute \src "ls180.v:5848.39-5848.143" + cell $and $and$ls180.v:5848$1242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5848$1240_Y + connect \B $eq$ls180.v:5848$1241_Y + connect \Y $and$ls180.v:5848$1242_Y + end + attribute \src "ls180.v:5849.40-5849.96" + cell $and $and$ls180.v:5849$1244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5849$1243_Y + connect \Y $and$ls180.v:5849$1244_Y + end + attribute \src "ls180.v:5849.39-5849.146" + cell $and $and$ls180.v:5849$1246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5849$1244_Y + connect \B $eq$ls180.v:5849$1245_Y + connect \Y $and$ls180.v:5849$1246_Y + end + attribute \src "ls180.v:5851.40-5851.93" + cell $and $and$ls180.v:5851$1247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5851$1247_Y + end + attribute \src "ls180.v:5851.39-5851.143" + cell $and $and$ls180.v:5851$1249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5851$1247_Y + connect \B $eq$ls180.v:5851$1248_Y + connect \Y $and$ls180.v:5851$1249_Y + end + attribute \src "ls180.v:5852.40-5852.96" + cell $and $and$ls180.v:5852$1251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5852$1250_Y + connect \Y $and$ls180.v:5852$1251_Y + end + attribute \src "ls180.v:5852.39-5852.146" + cell $and $and$ls180.v:5852$1253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5852$1251_Y + connect \B $eq$ls180.v:5852$1252_Y + connect \Y $and$ls180.v:5852$1253_Y + end + attribute \src "ls180.v:5854.40-5854.93" + cell $and $and$ls180.v:5854$1254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5854$1254_Y + end + attribute \src "ls180.v:5854.39-5854.143" + cell $and $and$ls180.v:5854$1256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5854$1254_Y + connect \B $eq$ls180.v:5854$1255_Y + connect \Y $and$ls180.v:5854$1256_Y + end + attribute \src "ls180.v:5855.40-5855.96" + cell $and $and$ls180.v:5855$1258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5855$1257_Y + connect \Y $and$ls180.v:5855$1258_Y + end + attribute \src "ls180.v:5855.39-5855.146" + cell $and $and$ls180.v:5855$1260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5855$1258_Y + connect \B $eq$ls180.v:5855$1259_Y + connect \Y $and$ls180.v:5855$1260_Y + end + attribute \src "ls180.v:5857.40-5857.93" + cell $and $and$ls180.v:5857$1261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5857$1261_Y + end + attribute \src "ls180.v:5857.39-5857.143" + cell $and $and$ls180.v:5857$1263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5857$1261_Y + connect \B $eq$ls180.v:5857$1262_Y + connect \Y $and$ls180.v:5857$1263_Y + end + attribute \src "ls180.v:5858.40-5858.96" + cell $and $and$ls180.v:5858$1265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5858$1264_Y + connect \Y $and$ls180.v:5858$1265_Y + end + attribute \src "ls180.v:5858.39-5858.146" + cell $and $and$ls180.v:5858$1267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5858$1265_Y + connect \B $eq$ls180.v:5858$1266_Y + connect \Y $and$ls180.v:5858$1267_Y + end + attribute \src "ls180.v:5870.40-5870.93" + cell $and $and$ls180.v:5870$1269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5870$1269_Y + end + attribute \src "ls180.v:5870.39-5870.143" + cell $and $and$ls180.v:5870$1271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5870$1269_Y + connect \B $eq$ls180.v:5870$1270_Y + connect \Y $and$ls180.v:5870$1271_Y + end + attribute \src "ls180.v:5871.40-5871.96" + cell $and $and$ls180.v:5871$1273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5871$1272_Y + connect \Y $and$ls180.v:5871$1273_Y + end + attribute \src "ls180.v:5871.39-5871.146" + cell $and $and$ls180.v:5871$1275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5871$1273_Y + connect \B $eq$ls180.v:5871$1274_Y + connect \Y $and$ls180.v:5871$1275_Y + end + attribute \src "ls180.v:5873.39-5873.92" + cell $and $and$ls180.v:5873$1276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5873$1276_Y + end + attribute \src "ls180.v:5873.38-5873.142" + cell $and $and$ls180.v:5873$1278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5873$1276_Y + connect \B $eq$ls180.v:5873$1277_Y + connect \Y $and$ls180.v:5873$1278_Y + end + attribute \src "ls180.v:5874.39-5874.95" + cell $and $and$ls180.v:5874$1280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5874$1279_Y + connect \Y $and$ls180.v:5874$1280_Y + end + attribute \src "ls180.v:5874.38-5874.145" + cell $and $and$ls180.v:5874$1282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5874$1280_Y + connect \B $eq$ls180.v:5874$1281_Y + connect \Y $and$ls180.v:5874$1282_Y + end + attribute \src "ls180.v:5876.39-5876.92" + cell $and $and$ls180.v:5876$1283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5876$1283_Y + end + attribute \src "ls180.v:5876.38-5876.142" + cell $and $and$ls180.v:5876$1285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5876$1283_Y + connect \B $eq$ls180.v:5876$1284_Y + connect \Y $and$ls180.v:5876$1285_Y + end + attribute \src "ls180.v:5877.39-5877.95" + cell $and $and$ls180.v:5877$1287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5877$1286_Y + connect \Y $and$ls180.v:5877$1287_Y + end + attribute \src "ls180.v:5877.38-5877.145" + cell $and $and$ls180.v:5877$1289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5877$1287_Y + connect \B $eq$ls180.v:5877$1288_Y + connect \Y $and$ls180.v:5877$1289_Y + end + attribute \src "ls180.v:5879.39-5879.92" + cell $and $and$ls180.v:5879$1290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5879$1290_Y + end + attribute \src "ls180.v:5879.38-5879.142" + cell $and $and$ls180.v:5879$1292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5879$1290_Y + connect \B $eq$ls180.v:5879$1291_Y + connect \Y $and$ls180.v:5879$1292_Y + end + attribute \src "ls180.v:5880.39-5880.95" + cell $and $and$ls180.v:5880$1294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5880$1293_Y + connect \Y $and$ls180.v:5880$1294_Y + end + attribute \src "ls180.v:5880.38-5880.145" + cell $and $and$ls180.v:5880$1296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5880$1294_Y + connect \B $eq$ls180.v:5880$1295_Y + connect \Y $and$ls180.v:5880$1296_Y + end + attribute \src "ls180.v:5882.39-5882.92" + cell $and $and$ls180.v:5882$1297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5882$1297_Y + end + attribute \src "ls180.v:5882.38-5882.142" + cell $and $and$ls180.v:5882$1299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5882$1297_Y + connect \B $eq$ls180.v:5882$1298_Y + connect \Y $and$ls180.v:5882$1299_Y + end + attribute \src "ls180.v:5883.39-5883.95" + cell $and $and$ls180.v:5883$1301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5883$1300_Y + connect \Y $and$ls180.v:5883$1301_Y + end + attribute \src "ls180.v:5883.38-5883.145" + cell $and $and$ls180.v:5883$1303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5883$1301_Y + connect \B $eq$ls180.v:5883$1302_Y + connect \Y $and$ls180.v:5883$1303_Y + end + attribute \src "ls180.v:5885.40-5885.93" + cell $and $and$ls180.v:5885$1304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5885$1304_Y + end + attribute \src "ls180.v:5885.39-5885.143" + cell $and $and$ls180.v:5885$1306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5885$1304_Y + connect \B $eq$ls180.v:5885$1305_Y + connect \Y $and$ls180.v:5885$1306_Y + end + attribute \src "ls180.v:5886.40-5886.96" + cell $and $and$ls180.v:5886$1308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5886$1307_Y + connect \Y $and$ls180.v:5886$1308_Y + end + attribute \src "ls180.v:5886.39-5886.146" + cell $and $and$ls180.v:5886$1310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5886$1308_Y + connect \B $eq$ls180.v:5886$1309_Y + connect \Y $and$ls180.v:5886$1310_Y + end + attribute \src "ls180.v:5888.40-5888.93" + cell $and $and$ls180.v:5888$1311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5888$1311_Y + end + attribute \src "ls180.v:5888.39-5888.143" + cell $and $and$ls180.v:5888$1313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5888$1311_Y + connect \B $eq$ls180.v:5888$1312_Y + connect \Y $and$ls180.v:5888$1313_Y + end + attribute \src "ls180.v:5889.40-5889.96" + cell $and $and$ls180.v:5889$1315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5889$1314_Y + connect \Y $and$ls180.v:5889$1315_Y + end + attribute \src "ls180.v:5889.39-5889.146" + cell $and $and$ls180.v:5889$1317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5889$1315_Y + connect \B $eq$ls180.v:5889$1316_Y + connect \Y $and$ls180.v:5889$1317_Y + end + attribute \src "ls180.v:5891.40-5891.93" + cell $and $and$ls180.v:5891$1318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5891$1318_Y + end + attribute \src "ls180.v:5891.39-5891.143" + cell $and $and$ls180.v:5891$1320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5891$1318_Y + connect \B $eq$ls180.v:5891$1319_Y + connect \Y $and$ls180.v:5891$1320_Y + end + attribute \src "ls180.v:5892.40-5892.96" + cell $and $and$ls180.v:5892$1322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5892$1321_Y + connect \Y $and$ls180.v:5892$1322_Y + end + attribute \src "ls180.v:5892.39-5892.146" + cell $and $and$ls180.v:5892$1324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5892$1322_Y + connect \B $eq$ls180.v:5892$1323_Y + connect \Y $and$ls180.v:5892$1324_Y + end + attribute \src "ls180.v:5894.40-5894.93" + cell $and $and$ls180.v:5894$1325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5894$1325_Y + end + attribute \src "ls180.v:5894.39-5894.143" + cell $and $and$ls180.v:5894$1327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5894$1325_Y + connect \B $eq$ls180.v:5894$1326_Y + connect \Y $and$ls180.v:5894$1327_Y + end + attribute \src "ls180.v:5895.40-5895.96" + cell $and $and$ls180.v:5895$1329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5895$1328_Y + connect \Y $and$ls180.v:5895$1329_Y + end + attribute \src "ls180.v:5895.39-5895.146" + cell $and $and$ls180.v:5895$1331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5895$1329_Y + connect \B $eq$ls180.v:5895$1330_Y + connect \Y $and$ls180.v:5895$1331_Y + end + attribute \src "ls180.v:5907.42-5907.95" + cell $and $and$ls180.v:5907$1333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5907$1333_Y + end + attribute \src "ls180.v:5907.41-5907.145" + cell $and $and$ls180.v:5907$1335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5907$1333_Y + connect \B $eq$ls180.v:5907$1334_Y + connect \Y $and$ls180.v:5907$1335_Y + end + attribute \src "ls180.v:5908.42-5908.98" + cell $and $and$ls180.v:5908$1337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5908$1336_Y + connect \Y $and$ls180.v:5908$1337_Y + end + attribute \src "ls180.v:5908.41-5908.148" + cell $and $and$ls180.v:5908$1339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5908$1337_Y + connect \B $eq$ls180.v:5908$1338_Y + connect \Y $and$ls180.v:5908$1339_Y + end + attribute \src "ls180.v:5910.42-5910.95" + cell $and $and$ls180.v:5910$1340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5910$1340_Y + end + attribute \src "ls180.v:5910.41-5910.145" + cell $and $and$ls180.v:5910$1342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5910$1340_Y + connect \B $eq$ls180.v:5910$1341_Y + connect \Y $and$ls180.v:5910$1342_Y + end + attribute \src "ls180.v:5911.42-5911.98" + cell $and $and$ls180.v:5911$1344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5911$1343_Y + connect \Y $and$ls180.v:5911$1344_Y + end + attribute \src "ls180.v:5911.41-5911.148" + cell $and $and$ls180.v:5911$1346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5911$1344_Y + connect \B $eq$ls180.v:5911$1345_Y + connect \Y $and$ls180.v:5911$1346_Y + end + attribute \src "ls180.v:5913.42-5913.95" + cell $and $and$ls180.v:5913$1347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5913$1347_Y + end + attribute \src "ls180.v:5913.41-5913.145" + cell $and $and$ls180.v:5913$1349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5913$1347_Y + connect \B $eq$ls180.v:5913$1348_Y + connect \Y $and$ls180.v:5913$1349_Y + end + attribute \src "ls180.v:5914.42-5914.98" + cell $and $and$ls180.v:5914$1351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5914$1350_Y + connect \Y $and$ls180.v:5914$1351_Y + end + attribute \src "ls180.v:5914.41-5914.148" + cell $and $and$ls180.v:5914$1353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5914$1351_Y + connect \B $eq$ls180.v:5914$1352_Y + connect \Y $and$ls180.v:5914$1353_Y + end + attribute \src "ls180.v:5916.42-5916.95" + cell $and $and$ls180.v:5916$1354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5916$1354_Y + end + attribute \src "ls180.v:5916.41-5916.145" + cell $and $and$ls180.v:5916$1356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5916$1354_Y + connect \B $eq$ls180.v:5916$1355_Y + connect \Y $and$ls180.v:5916$1356_Y + end + attribute \src "ls180.v:5917.42-5917.98" + cell $and $and$ls180.v:5917$1358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5917$1357_Y + connect \Y $and$ls180.v:5917$1358_Y + end + attribute \src "ls180.v:5917.41-5917.148" + cell $and $and$ls180.v:5917$1360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5917$1358_Y + connect \B $eq$ls180.v:5917$1359_Y + connect \Y $and$ls180.v:5917$1360_Y + end + attribute \src "ls180.v:5919.42-5919.95" + cell $and $and$ls180.v:5919$1361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5919$1361_Y + end + attribute \src "ls180.v:5919.41-5919.145" + cell $and $and$ls180.v:5919$1363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5919$1361_Y + connect \B $eq$ls180.v:5919$1362_Y + connect \Y $and$ls180.v:5919$1363_Y + end + attribute \src "ls180.v:5920.42-5920.98" + cell $and $and$ls180.v:5920$1365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5920$1364_Y + connect \Y $and$ls180.v:5920$1365_Y + end + attribute \src "ls180.v:5920.41-5920.148" + cell $and $and$ls180.v:5920$1367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5920$1365_Y + connect \B $eq$ls180.v:5920$1366_Y + connect \Y $and$ls180.v:5920$1367_Y + end + attribute \src "ls180.v:5922.42-5922.95" + cell $and $and$ls180.v:5922$1368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5922$1368_Y + end + attribute \src "ls180.v:5922.41-5922.145" + cell $and $and$ls180.v:5922$1370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5922$1368_Y + connect \B $eq$ls180.v:5922$1369_Y + connect \Y $and$ls180.v:5922$1370_Y + end + attribute \src "ls180.v:5923.42-5923.98" + cell $and $and$ls180.v:5923$1372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5923$1371_Y + connect \Y $and$ls180.v:5923$1372_Y + end + attribute \src "ls180.v:5923.41-5923.148" + cell $and $and$ls180.v:5923$1374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5923$1372_Y + connect \B $eq$ls180.v:5923$1373_Y + connect \Y $and$ls180.v:5923$1374_Y + end + attribute \src "ls180.v:5925.42-5925.95" + cell $and $and$ls180.v:5925$1375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5925$1375_Y + end + attribute \src "ls180.v:5925.41-5925.145" + cell $and $and$ls180.v:5925$1377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5925$1375_Y + connect \B $eq$ls180.v:5925$1376_Y + connect \Y $and$ls180.v:5925$1377_Y + end + attribute \src "ls180.v:5926.42-5926.98" + cell $and $and$ls180.v:5926$1379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5926$1378_Y + connect \Y $and$ls180.v:5926$1379_Y + end + attribute \src "ls180.v:5926.41-5926.148" + cell $and $and$ls180.v:5926$1381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5926$1379_Y + connect \B $eq$ls180.v:5926$1380_Y + connect \Y $and$ls180.v:5926$1381_Y + end + attribute \src "ls180.v:5928.42-5928.95" + cell $and $and$ls180.v:5928$1382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5928$1382_Y + end + attribute \src "ls180.v:5928.41-5928.145" + cell $and $and$ls180.v:5928$1384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5928$1382_Y + connect \B $eq$ls180.v:5928$1383_Y + connect \Y $and$ls180.v:5928$1384_Y + end + attribute \src "ls180.v:5929.42-5929.98" + cell $and $and$ls180.v:5929$1386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5929$1385_Y + connect \Y $and$ls180.v:5929$1386_Y + end + attribute \src "ls180.v:5929.41-5929.148" + cell $and $and$ls180.v:5929$1388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5929$1386_Y + connect \B $eq$ls180.v:5929$1387_Y + connect \Y $and$ls180.v:5929$1388_Y + end + attribute \src "ls180.v:5931.44-5931.97" + cell $and $and$ls180.v:5931$1389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5931$1389_Y + end + attribute \src "ls180.v:5931.43-5931.147" + cell $and $and$ls180.v:5931$1391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5931$1389_Y + connect \B $eq$ls180.v:5931$1390_Y + connect \Y $and$ls180.v:5931$1391_Y + end + attribute \src "ls180.v:5932.44-5932.100" + cell $and $and$ls180.v:5932$1393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5932$1392_Y + connect \Y $and$ls180.v:5932$1393_Y + end + attribute \src "ls180.v:5932.43-5932.150" + cell $and $and$ls180.v:5932$1395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5932$1393_Y + connect \B $eq$ls180.v:5932$1394_Y + connect \Y $and$ls180.v:5932$1395_Y + end + attribute \src "ls180.v:5934.44-5934.97" + cell $and $and$ls180.v:5934$1396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5934$1396_Y + end + attribute \src "ls180.v:5934.43-5934.147" + cell $and $and$ls180.v:5934$1398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5934$1396_Y + connect \B $eq$ls180.v:5934$1397_Y + connect \Y $and$ls180.v:5934$1398_Y + end + attribute \src "ls180.v:5935.44-5935.100" + cell $and $and$ls180.v:5935$1400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5935$1399_Y + connect \Y $and$ls180.v:5935$1400_Y + end + attribute \src "ls180.v:5935.43-5935.150" + cell $and $and$ls180.v:5935$1402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5935$1400_Y + connect \B $eq$ls180.v:5935$1401_Y + connect \Y $and$ls180.v:5935$1402_Y + end + attribute \src "ls180.v:5937.44-5937.97" + cell $and $and$ls180.v:5937$1403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5937$1403_Y + end + attribute \src "ls180.v:5937.43-5937.148" + cell $and $and$ls180.v:5937$1405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5937$1403_Y + connect \B $eq$ls180.v:5937$1404_Y + connect \Y $and$ls180.v:5937$1405_Y + end + attribute \src "ls180.v:5938.44-5938.100" + cell $and $and$ls180.v:5938$1407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5938$1406_Y + connect \Y $and$ls180.v:5938$1407_Y + end + attribute \src "ls180.v:5938.43-5938.151" + cell $and $and$ls180.v:5938$1409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5938$1407_Y + connect \B $eq$ls180.v:5938$1408_Y + connect \Y $and$ls180.v:5938$1409_Y + end + attribute \src "ls180.v:5940.44-5940.97" + cell $and $and$ls180.v:5940$1410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5940$1410_Y + end + attribute \src "ls180.v:5940.43-5940.148" + cell $and $and$ls180.v:5940$1412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5940$1410_Y + connect \B $eq$ls180.v:5940$1411_Y + connect \Y $and$ls180.v:5940$1412_Y + end + attribute \src "ls180.v:5941.44-5941.100" + cell $and $and$ls180.v:5941$1414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5941$1413_Y + connect \Y $and$ls180.v:5941$1414_Y + end + attribute \src "ls180.v:5941.43-5941.151" + cell $and $and$ls180.v:5941$1416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5941$1414_Y + connect \B $eq$ls180.v:5941$1415_Y + connect \Y $and$ls180.v:5941$1416_Y + end + attribute \src "ls180.v:5943.44-5943.97" + cell $and $and$ls180.v:5943$1417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5943$1417_Y + end + attribute \src "ls180.v:5943.43-5943.148" + cell $and $and$ls180.v:5943$1419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5943$1417_Y + connect \B $eq$ls180.v:5943$1418_Y + connect \Y $and$ls180.v:5943$1419_Y + end + attribute \src "ls180.v:5944.44-5944.100" + cell $and $and$ls180.v:5944$1421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5944$1420_Y + connect \Y $and$ls180.v:5944$1421_Y + end + attribute \src "ls180.v:5944.43-5944.151" + cell $and $and$ls180.v:5944$1423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5944$1421_Y + connect \B $eq$ls180.v:5944$1422_Y + connect \Y $and$ls180.v:5944$1423_Y + end + attribute \src "ls180.v:5946.41-5946.94" + cell $and $and$ls180.v:5946$1424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5946$1424_Y + end + attribute \src "ls180.v:5946.40-5946.145" + cell $and $and$ls180.v:5946$1426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5946$1424_Y + connect \B $eq$ls180.v:5946$1425_Y + connect \Y $and$ls180.v:5946$1426_Y + end + attribute \src "ls180.v:5947.41-5947.97" + cell $and $and$ls180.v:5947$1428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5947$1427_Y + connect \Y $and$ls180.v:5947$1428_Y + end + attribute \src "ls180.v:5947.40-5947.148" + cell $and $and$ls180.v:5947$1430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5947$1428_Y + connect \B $eq$ls180.v:5947$1429_Y + connect \Y $and$ls180.v:5947$1430_Y + end + attribute \src "ls180.v:5949.42-5949.95" + cell $and $and$ls180.v:5949$1431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5949$1431_Y + end + attribute \src "ls180.v:5949.41-5949.146" + cell $and $and$ls180.v:5949$1433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5949$1431_Y + connect \B $eq$ls180.v:5949$1432_Y + connect \Y $and$ls180.v:5949$1433_Y + end + attribute \src "ls180.v:5950.42-5950.98" + cell $and $and$ls180.v:5950$1435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5950$1434_Y + connect \Y $and$ls180.v:5950$1435_Y + end + attribute \src "ls180.v:5950.41-5950.149" + cell $and $and$ls180.v:5950$1437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5950$1435_Y + connect \B $eq$ls180.v:5950$1436_Y + connect \Y $and$ls180.v:5950$1437_Y + end + attribute \src "ls180.v:5969.46-5969.99" + cell $and $and$ls180.v:5969$1439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5969$1439_Y + end + attribute \src "ls180.v:5969.45-5969.149" + cell $and $and$ls180.v:5969$1441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5969$1439_Y + connect \B $eq$ls180.v:5969$1440_Y + connect \Y $and$ls180.v:5969$1441_Y + end + attribute \src "ls180.v:5970.46-5970.102" + cell $and $and$ls180.v:5970$1443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5970$1442_Y + connect \Y $and$ls180.v:5970$1443_Y + end + attribute \src "ls180.v:5970.45-5970.152" + cell $and $and$ls180.v:5970$1445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5970$1443_Y + connect \B $eq$ls180.v:5970$1444_Y + connect \Y $and$ls180.v:5970$1445_Y + end + attribute \src "ls180.v:5972.46-5972.99" + cell $and $and$ls180.v:5972$1446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5972$1446_Y + end + attribute \src "ls180.v:5972.45-5972.149" + cell $and $and$ls180.v:5972$1448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5972$1446_Y + connect \B $eq$ls180.v:5972$1447_Y + connect \Y $and$ls180.v:5972$1448_Y + end + attribute \src "ls180.v:5973.46-5973.102" + cell $and $and$ls180.v:5973$1450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5973$1449_Y + connect \Y $and$ls180.v:5973$1450_Y + end + attribute \src "ls180.v:5973.45-5973.152" + cell $and $and$ls180.v:5973$1452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5973$1450_Y + connect \B $eq$ls180.v:5973$1451_Y + connect \Y $and$ls180.v:5973$1452_Y + end + attribute \src "ls180.v:5975.46-5975.99" + cell $and $and$ls180.v:5975$1453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5975$1453_Y + end + attribute \src "ls180.v:5975.45-5975.149" + cell $and $and$ls180.v:5975$1455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5975$1453_Y + connect \B $eq$ls180.v:5975$1454_Y + connect \Y $and$ls180.v:5975$1455_Y + end + attribute \src "ls180.v:5976.46-5976.102" + cell $and $and$ls180.v:5976$1457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5976$1456_Y + connect \Y $and$ls180.v:5976$1457_Y + end + attribute \src "ls180.v:5976.45-5976.152" + cell $and $and$ls180.v:5976$1459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5976$1457_Y + connect \B $eq$ls180.v:5976$1458_Y + connect \Y $and$ls180.v:5976$1459_Y + end + attribute \src "ls180.v:5978.46-5978.99" + cell $and $and$ls180.v:5978$1460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5978$1460_Y + end + attribute \src "ls180.v:5978.45-5978.149" + cell $and $and$ls180.v:5978$1462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5978$1460_Y + connect \B $eq$ls180.v:5978$1461_Y + connect \Y $and$ls180.v:5978$1462_Y + end + attribute \src "ls180.v:5979.46-5979.102" + cell $and $and$ls180.v:5979$1464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5979$1463_Y + connect \Y $and$ls180.v:5979$1464_Y + end + attribute \src "ls180.v:5979.45-5979.152" + cell $and $and$ls180.v:5979$1466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5979$1464_Y + connect \B $eq$ls180.v:5979$1465_Y + connect \Y $and$ls180.v:5979$1466_Y + end + attribute \src "ls180.v:5981.45-5981.98" + cell $and $and$ls180.v:5981$1467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5981$1467_Y + end + attribute \src "ls180.v:5981.44-5981.148" + cell $and $and$ls180.v:5981$1469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5981$1467_Y + connect \B $eq$ls180.v:5981$1468_Y + connect \Y $and$ls180.v:5981$1469_Y + end + attribute \src "ls180.v:5982.45-5982.101" + cell $and $and$ls180.v:5982$1471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5982$1470_Y + connect \Y $and$ls180.v:5982$1471_Y + end + attribute \src "ls180.v:5982.44-5982.151" + cell $and $and$ls180.v:5982$1473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5982$1471_Y + connect \B $eq$ls180.v:5982$1472_Y + connect \Y $and$ls180.v:5982$1473_Y + end + attribute \src "ls180.v:5984.45-5984.98" + cell $and $and$ls180.v:5984$1474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5984$1474_Y + end + attribute \src "ls180.v:5984.44-5984.148" + cell $and $and$ls180.v:5984$1476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5984$1474_Y + connect \B $eq$ls180.v:5984$1475_Y + connect \Y $and$ls180.v:5984$1476_Y + end + attribute \src "ls180.v:5985.45-5985.101" + cell $and $and$ls180.v:5985$1478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5985$1477_Y + connect \Y $and$ls180.v:5985$1478_Y + end + attribute \src "ls180.v:5985.44-5985.151" + cell $and $and$ls180.v:5985$1480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5985$1478_Y + connect \B $eq$ls180.v:5985$1479_Y + connect \Y $and$ls180.v:5985$1480_Y + end + attribute \src "ls180.v:5987.45-5987.98" + cell $and $and$ls180.v:5987$1481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5987$1481_Y + end + attribute \src "ls180.v:5987.44-5987.148" + cell $and $and$ls180.v:5987$1483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5987$1481_Y + connect \B $eq$ls180.v:5987$1482_Y + connect \Y $and$ls180.v:5987$1483_Y + end + attribute \src "ls180.v:5988.45-5988.101" + cell $and $and$ls180.v:5988$1485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5988$1484_Y + connect \Y $and$ls180.v:5988$1485_Y + end + attribute \src "ls180.v:5988.44-5988.151" + cell $and $and$ls180.v:5988$1487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5988$1485_Y + connect \B $eq$ls180.v:5988$1486_Y + connect \Y $and$ls180.v:5988$1487_Y + end + attribute \src "ls180.v:5990.45-5990.98" + cell $and $and$ls180.v:5990$1488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5990$1488_Y + end + attribute \src "ls180.v:5990.44-5990.148" + cell $and $and$ls180.v:5990$1490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5990$1488_Y + connect \B $eq$ls180.v:5990$1489_Y + connect \Y $and$ls180.v:5990$1490_Y + end + attribute \src "ls180.v:5991.45-5991.101" + cell $and $and$ls180.v:5991$1492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5991$1491_Y + connect \Y $and$ls180.v:5991$1492_Y + end + attribute \src "ls180.v:5991.44-5991.151" + cell $and $and$ls180.v:5991$1494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5991$1492_Y + connect \B $eq$ls180.v:5991$1493_Y + connect \Y $and$ls180.v:5991$1494_Y + end + attribute \src "ls180.v:5993.36-5993.89" + cell $and $and$ls180.v:5993$1495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5993$1495_Y + end + attribute \src "ls180.v:5993.35-5993.139" + cell $and $and$ls180.v:5993$1497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5993$1495_Y + connect \B $eq$ls180.v:5993$1496_Y + connect \Y $and$ls180.v:5993$1497_Y + end + attribute \src "ls180.v:5994.36-5994.92" + cell $and $and$ls180.v:5994$1499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5994$1498_Y + connect \Y $and$ls180.v:5994$1499_Y + end + attribute \src "ls180.v:5994.35-5994.142" + cell $and $and$ls180.v:5994$1501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5994$1499_Y + connect \B $eq$ls180.v:5994$1500_Y + connect \Y $and$ls180.v:5994$1501_Y + end + attribute \src "ls180.v:5996.47-5996.100" + cell $and $and$ls180.v:5996$1502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5996$1502_Y + end + attribute \src "ls180.v:5996.46-5996.150" + cell $and $and$ls180.v:5996$1504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5996$1502_Y + connect \B $eq$ls180.v:5996$1503_Y + connect \Y $and$ls180.v:5996$1504_Y + end + attribute \src "ls180.v:5997.47-5997.103" + cell $and $and$ls180.v:5997$1506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5997$1505_Y + connect \Y $and$ls180.v:5997$1506_Y + end + attribute \src "ls180.v:5997.46-5997.153" + cell $and $and$ls180.v:5997$1508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5997$1506_Y + connect \B $eq$ls180.v:5997$1507_Y + connect \Y $and$ls180.v:5997$1508_Y + end + attribute \src "ls180.v:5999.47-5999.100" + cell $and $and$ls180.v:5999$1509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5999$1509_Y + end + attribute \src "ls180.v:5999.46-5999.151" + cell $and $and$ls180.v:5999$1511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5999$1509_Y + connect \B $eq$ls180.v:5999$1510_Y + connect \Y $and$ls180.v:5999$1511_Y + end + attribute \src "ls180.v:6000.47-6000.103" + cell $and $and$ls180.v:6000$1513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6000$1512_Y + connect \Y $and$ls180.v:6000$1513_Y + end + attribute \src "ls180.v:6000.46-6000.154" + cell $and $and$ls180.v:6000$1515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6000$1513_Y + connect \B $eq$ls180.v:6000$1514_Y + connect \Y $and$ls180.v:6000$1515_Y + end + attribute \src "ls180.v:6002.47-6002.100" + cell $and $and$ls180.v:6002$1516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6002$1516_Y + end + attribute \src "ls180.v:6002.46-6002.151" + cell $and $and$ls180.v:6002$1518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6002$1516_Y + connect \B $eq$ls180.v:6002$1517_Y + connect \Y $and$ls180.v:6002$1518_Y + end + attribute \src "ls180.v:6003.47-6003.103" + cell $and $and$ls180.v:6003$1520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6003$1519_Y + connect \Y $and$ls180.v:6003$1520_Y + end + attribute \src "ls180.v:6003.46-6003.154" + cell $and $and$ls180.v:6003$1522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6003$1520_Y + connect \B $eq$ls180.v:6003$1521_Y + connect \Y $and$ls180.v:6003$1522_Y + end + attribute \src "ls180.v:6005.47-6005.100" + cell $and $and$ls180.v:6005$1523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6005$1523_Y + end + attribute \src "ls180.v:6005.46-6005.151" + cell $and $and$ls180.v:6005$1525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6005$1523_Y + connect \B $eq$ls180.v:6005$1524_Y + connect \Y $and$ls180.v:6005$1525_Y + end + attribute \src "ls180.v:6006.47-6006.103" + cell $and $and$ls180.v:6006$1527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6006$1526_Y + connect \Y $and$ls180.v:6006$1527_Y + end + attribute \src "ls180.v:6006.46-6006.154" + cell $and $and$ls180.v:6006$1529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6006$1527_Y + connect \B $eq$ls180.v:6006$1528_Y + connect \Y $and$ls180.v:6006$1529_Y + end + attribute \src "ls180.v:6008.47-6008.100" + cell $and $and$ls180.v:6008$1530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6008$1530_Y + end + attribute \src "ls180.v:6008.46-6008.151" + cell $and $and$ls180.v:6008$1532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6008$1530_Y + connect \B $eq$ls180.v:6008$1531_Y + connect \Y $and$ls180.v:6008$1532_Y + end + attribute \src "ls180.v:6009.47-6009.103" + cell $and $and$ls180.v:6009$1534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6009$1533_Y + connect \Y $and$ls180.v:6009$1534_Y + end + attribute \src "ls180.v:6009.46-6009.154" + cell $and $and$ls180.v:6009$1536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6009$1534_Y + connect \B $eq$ls180.v:6009$1535_Y + connect \Y $and$ls180.v:6009$1536_Y + end + attribute \src "ls180.v:6011.47-6011.100" + cell $and $and$ls180.v:6011$1537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6011$1537_Y + end + attribute \src "ls180.v:6011.46-6011.151" + cell $and $and$ls180.v:6011$1539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6011$1537_Y + connect \B $eq$ls180.v:6011$1538_Y + connect \Y $and$ls180.v:6011$1539_Y + end + attribute \src "ls180.v:6012.47-6012.103" + cell $and $and$ls180.v:6012$1541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6012$1540_Y + connect \Y $and$ls180.v:6012$1541_Y + end + attribute \src "ls180.v:6012.46-6012.154" + cell $and $and$ls180.v:6012$1543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6012$1541_Y + connect \B $eq$ls180.v:6012$1542_Y + connect \Y $and$ls180.v:6012$1543_Y + end + attribute \src "ls180.v:6014.46-6014.99" + cell $and $and$ls180.v:6014$1544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6014$1544_Y + end + attribute \src "ls180.v:6014.45-6014.150" + cell $and $and$ls180.v:6014$1546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6014$1544_Y + connect \B $eq$ls180.v:6014$1545_Y + connect \Y $and$ls180.v:6014$1546_Y + end + attribute \src "ls180.v:6015.46-6015.102" + cell $and $and$ls180.v:6015$1548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6015$1547_Y + connect \Y $and$ls180.v:6015$1548_Y + end + attribute \src "ls180.v:6015.45-6015.153" + cell $and $and$ls180.v:6015$1550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6015$1548_Y + connect \B $eq$ls180.v:6015$1549_Y + connect \Y $and$ls180.v:6015$1550_Y + end + attribute \src "ls180.v:6017.46-6017.99" + cell $and $and$ls180.v:6017$1551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6017$1551_Y + end + attribute \src "ls180.v:6017.45-6017.150" + cell $and $and$ls180.v:6017$1553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6017$1551_Y + connect \B $eq$ls180.v:6017$1552_Y + connect \Y $and$ls180.v:6017$1553_Y + end + attribute \src "ls180.v:6018.46-6018.102" + cell $and $and$ls180.v:6018$1555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6018$1554_Y + connect \Y $and$ls180.v:6018$1555_Y + end + attribute \src "ls180.v:6018.45-6018.153" + cell $and $and$ls180.v:6018$1557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6018$1555_Y + connect \B $eq$ls180.v:6018$1556_Y + connect \Y $and$ls180.v:6018$1557_Y + end + attribute \src "ls180.v:6020.46-6020.99" + cell $and $and$ls180.v:6020$1558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6020$1558_Y + end + attribute \src "ls180.v:6020.45-6020.150" + cell $and $and$ls180.v:6020$1560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6020$1558_Y + connect \B $eq$ls180.v:6020$1559_Y + connect \Y $and$ls180.v:6020$1560_Y + end + attribute \src "ls180.v:6021.46-6021.102" + cell $and $and$ls180.v:6021$1562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6021$1561_Y + connect \Y $and$ls180.v:6021$1562_Y + end + attribute \src "ls180.v:6021.45-6021.153" + cell $and $and$ls180.v:6021$1564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6021$1562_Y + connect \B $eq$ls180.v:6021$1563_Y + connect \Y $and$ls180.v:6021$1564_Y + end + attribute \src "ls180.v:6023.46-6023.99" + cell $and $and$ls180.v:6023$1565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6023$1565_Y + end + attribute \src "ls180.v:6023.45-6023.150" + cell $and $and$ls180.v:6023$1567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6023$1565_Y + connect \B $eq$ls180.v:6023$1566_Y + connect \Y $and$ls180.v:6023$1567_Y + end + attribute \src "ls180.v:6024.46-6024.102" + cell $and $and$ls180.v:6024$1569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6024$1568_Y + connect \Y $and$ls180.v:6024$1569_Y + end + attribute \src "ls180.v:6024.45-6024.153" + cell $and $and$ls180.v:6024$1571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6024$1569_Y + connect \B $eq$ls180.v:6024$1570_Y + connect \Y $and$ls180.v:6024$1571_Y + end + attribute \src "ls180.v:6026.46-6026.99" + cell $and $and$ls180.v:6026$1572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6026$1572_Y + end + attribute \src "ls180.v:6026.45-6026.150" + cell $and $and$ls180.v:6026$1574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6026$1572_Y + connect \B $eq$ls180.v:6026$1573_Y + connect \Y $and$ls180.v:6026$1574_Y + end + attribute \src "ls180.v:6027.46-6027.102" + cell $and $and$ls180.v:6027$1576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6027$1575_Y + connect \Y $and$ls180.v:6027$1576_Y + end + attribute \src "ls180.v:6027.45-6027.153" + cell $and $and$ls180.v:6027$1578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6027$1576_Y + connect \B $eq$ls180.v:6027$1577_Y + connect \Y $and$ls180.v:6027$1578_Y + end + attribute \src "ls180.v:6029.46-6029.99" + cell $and $and$ls180.v:6029$1579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6029$1579_Y + end + attribute \src "ls180.v:6029.45-6029.150" + cell $and $and$ls180.v:6029$1581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6029$1579_Y + connect \B $eq$ls180.v:6029$1580_Y + connect \Y $and$ls180.v:6029$1581_Y + end + attribute \src "ls180.v:6030.46-6030.102" + cell $and $and$ls180.v:6030$1583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6030$1582_Y + connect \Y $and$ls180.v:6030$1583_Y + end + attribute \src "ls180.v:6030.45-6030.153" + cell $and $and$ls180.v:6030$1585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6030$1583_Y + connect \B $eq$ls180.v:6030$1584_Y + connect \Y $and$ls180.v:6030$1585_Y + end + attribute \src "ls180.v:6032.46-6032.99" + cell $and $and$ls180.v:6032$1586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6032$1586_Y + end + attribute \src "ls180.v:6032.45-6032.150" + cell $and $and$ls180.v:6032$1588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6032$1586_Y + connect \B $eq$ls180.v:6032$1587_Y + connect \Y $and$ls180.v:6032$1588_Y + end + attribute \src "ls180.v:6033.46-6033.102" + cell $and $and$ls180.v:6033$1590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6033$1589_Y + connect \Y $and$ls180.v:6033$1590_Y + end + attribute \src "ls180.v:6033.45-6033.153" + cell $and $and$ls180.v:6033$1592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6033$1590_Y + connect \B $eq$ls180.v:6033$1591_Y + connect \Y $and$ls180.v:6033$1592_Y + end + attribute \src "ls180.v:6035.46-6035.99" + cell $and $and$ls180.v:6035$1593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6035$1593_Y + end + attribute \src "ls180.v:6035.45-6035.150" + cell $and $and$ls180.v:6035$1595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6035$1593_Y + connect \B $eq$ls180.v:6035$1594_Y + connect \Y $and$ls180.v:6035$1595_Y + end + attribute \src "ls180.v:6036.46-6036.102" + cell $and $and$ls180.v:6036$1597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6036$1596_Y + connect \Y $and$ls180.v:6036$1597_Y + end + attribute \src "ls180.v:6036.45-6036.153" + cell $and $and$ls180.v:6036$1599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6036$1597_Y + connect \B $eq$ls180.v:6036$1598_Y + connect \Y $and$ls180.v:6036$1599_Y + end + attribute \src "ls180.v:6038.46-6038.99" + cell $and $and$ls180.v:6038$1600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6038$1600_Y + end + attribute \src "ls180.v:6038.45-6038.150" + cell $and $and$ls180.v:6038$1602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6038$1600_Y + connect \B $eq$ls180.v:6038$1601_Y + connect \Y $and$ls180.v:6038$1602_Y + end + attribute \src "ls180.v:6039.46-6039.102" + cell $and $and$ls180.v:6039$1604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6039$1603_Y + connect \Y $and$ls180.v:6039$1604_Y + end + attribute \src "ls180.v:6039.45-6039.153" + cell $and $and$ls180.v:6039$1606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6039$1604_Y + connect \B $eq$ls180.v:6039$1605_Y + connect \Y $and$ls180.v:6039$1606_Y + end + attribute \src "ls180.v:6041.46-6041.99" + cell $and $and$ls180.v:6041$1607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6041$1607_Y + end + attribute \src "ls180.v:6041.45-6041.150" + cell $and $and$ls180.v:6041$1609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6041$1607_Y + connect \B $eq$ls180.v:6041$1608_Y + connect \Y $and$ls180.v:6041$1609_Y + end + attribute \src "ls180.v:6042.46-6042.102" + cell $and $and$ls180.v:6042$1611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6042$1610_Y + connect \Y $and$ls180.v:6042$1611_Y + end + attribute \src "ls180.v:6042.45-6042.153" + cell $and $and$ls180.v:6042$1613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6042$1611_Y + connect \B $eq$ls180.v:6042$1612_Y + connect \Y $and$ls180.v:6042$1613_Y + end + attribute \src "ls180.v:6044.42-6044.95" + cell $and $and$ls180.v:6044$1614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6044$1614_Y + end + attribute \src "ls180.v:6044.41-6044.146" + cell $and $and$ls180.v:6044$1616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6044$1614_Y + connect \B $eq$ls180.v:6044$1615_Y + connect \Y $and$ls180.v:6044$1616_Y + end + attribute \src "ls180.v:6045.42-6045.98" + cell $and $and$ls180.v:6045$1618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6045$1617_Y + connect \Y $and$ls180.v:6045$1618_Y + end + attribute \src "ls180.v:6045.41-6045.149" + cell $and $and$ls180.v:6045$1620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6045$1618_Y + connect \B $eq$ls180.v:6045$1619_Y + connect \Y $and$ls180.v:6045$1620_Y + end + attribute \src "ls180.v:6047.43-6047.96" + cell $and $and$ls180.v:6047$1621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6047$1621_Y + end + attribute \src "ls180.v:6047.42-6047.147" + cell $and $and$ls180.v:6047$1623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6047$1621_Y + connect \B $eq$ls180.v:6047$1622_Y + connect \Y $and$ls180.v:6047$1623_Y + end + attribute \src "ls180.v:6048.43-6048.99" + cell $and $and$ls180.v:6048$1625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6048$1624_Y + connect \Y $and$ls180.v:6048$1625_Y + end + attribute \src "ls180.v:6048.42-6048.150" + cell $and $and$ls180.v:6048$1627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6048$1625_Y + connect \B $eq$ls180.v:6048$1626_Y + connect \Y $and$ls180.v:6048$1627_Y + end + attribute \src "ls180.v:6050.46-6050.99" + cell $and $and$ls180.v:6050$1628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6050$1628_Y + end + attribute \src "ls180.v:6050.45-6050.150" + cell $and $and$ls180.v:6050$1630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6050$1628_Y + connect \B $eq$ls180.v:6050$1629_Y + connect \Y $and$ls180.v:6050$1630_Y + end + attribute \src "ls180.v:6051.46-6051.102" + cell $and $and$ls180.v:6051$1632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6051$1631_Y + connect \Y $and$ls180.v:6051$1632_Y + end + attribute \src "ls180.v:6051.45-6051.153" + cell $and $and$ls180.v:6051$1634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6051$1632_Y + connect \B $eq$ls180.v:6051$1633_Y + connect \Y $and$ls180.v:6051$1634_Y + end + attribute \src "ls180.v:6053.46-6053.99" + cell $and $and$ls180.v:6053$1635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6053$1635_Y + end + attribute \src "ls180.v:6053.45-6053.150" + cell $and $and$ls180.v:6053$1637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6053$1635_Y + connect \B $eq$ls180.v:6053$1636_Y + connect \Y $and$ls180.v:6053$1637_Y + end + attribute \src "ls180.v:6054.46-6054.102" + cell $and $and$ls180.v:6054$1639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6054$1638_Y + connect \Y $and$ls180.v:6054$1639_Y + end + attribute \src "ls180.v:6054.45-6054.153" + cell $and $and$ls180.v:6054$1641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6054$1639_Y + connect \B $eq$ls180.v:6054$1640_Y + connect \Y $and$ls180.v:6054$1641_Y + end + attribute \src "ls180.v:6056.45-6056.98" + cell $and $and$ls180.v:6056$1642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6056$1642_Y + end + attribute \src "ls180.v:6056.44-6056.149" + cell $and $and$ls180.v:6056$1644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6056$1642_Y + connect \B $eq$ls180.v:6056$1643_Y + connect \Y $and$ls180.v:6056$1644_Y + end + attribute \src "ls180.v:6057.45-6057.101" + cell $and $and$ls180.v:6057$1646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6057$1645_Y + connect \Y $and$ls180.v:6057$1646_Y + end + attribute \src "ls180.v:6057.44-6057.152" + cell $and $and$ls180.v:6057$1648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6057$1646_Y + connect \B $eq$ls180.v:6057$1647_Y + connect \Y $and$ls180.v:6057$1648_Y + end + attribute \src "ls180.v:6059.45-6059.98" + cell $and $and$ls180.v:6059$1649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6059$1649_Y + end + attribute \src "ls180.v:6059.44-6059.149" + cell $and $and$ls180.v:6059$1651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6059$1649_Y + connect \B $eq$ls180.v:6059$1650_Y + connect \Y $and$ls180.v:6059$1651_Y + end + attribute \src "ls180.v:6060.45-6060.101" + cell $and $and$ls180.v:6060$1653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6060$1652_Y + connect \Y $and$ls180.v:6060$1653_Y + end + attribute \src "ls180.v:6060.44-6060.152" + cell $and $and$ls180.v:6060$1655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6060$1653_Y + connect \B $eq$ls180.v:6060$1654_Y + connect \Y $and$ls180.v:6060$1655_Y + end + attribute \src "ls180.v:6062.45-6062.98" + cell $and $and$ls180.v:6062$1656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6062$1656_Y + end + attribute \src "ls180.v:6062.44-6062.149" + cell $and $and$ls180.v:6062$1658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6062$1656_Y + connect \B $eq$ls180.v:6062$1657_Y + connect \Y $and$ls180.v:6062$1658_Y + end + attribute \src "ls180.v:6063.45-6063.101" + cell $and $and$ls180.v:6063$1660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6063$1659_Y + connect \Y $and$ls180.v:6063$1660_Y + end + attribute \src "ls180.v:6063.44-6063.152" + cell $and $and$ls180.v:6063$1662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6063$1660_Y + connect \B $eq$ls180.v:6063$1661_Y + connect \Y $and$ls180.v:6063$1662_Y + end + attribute \src "ls180.v:6065.45-6065.98" + cell $and $and$ls180.v:6065$1663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6065$1663_Y + end + attribute \src "ls180.v:6065.44-6065.149" + cell $and $and$ls180.v:6065$1665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6065$1663_Y + connect \B $eq$ls180.v:6065$1664_Y + connect \Y $and$ls180.v:6065$1665_Y + end + attribute \src "ls180.v:6066.45-6066.101" + cell $and $and$ls180.v:6066$1667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6066$1666_Y + connect \Y $and$ls180.v:6066$1667_Y + end + attribute \src "ls180.v:6066.44-6066.152" + cell $and $and$ls180.v:6066$1669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6066$1667_Y + connect \B $eq$ls180.v:6066$1668_Y + connect \Y $and$ls180.v:6066$1669_Y + end + attribute \src "ls180.v:6104.42-6104.95" + cell $and $and$ls180.v:6104$1671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6104$1671_Y + end + attribute \src "ls180.v:6104.41-6104.145" + cell $and $and$ls180.v:6104$1673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6104$1671_Y + connect \B $eq$ls180.v:6104$1672_Y + connect \Y $and$ls180.v:6104$1673_Y + end + attribute \src "ls180.v:6105.42-6105.98" + cell $and $and$ls180.v:6105$1675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6105$1674_Y + connect \Y $and$ls180.v:6105$1675_Y + end + attribute \src "ls180.v:6105.41-6105.148" + cell $and $and$ls180.v:6105$1677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6105$1675_Y + connect \B $eq$ls180.v:6105$1676_Y + connect \Y $and$ls180.v:6105$1677_Y + end + attribute \src "ls180.v:6107.42-6107.95" + cell $and $and$ls180.v:6107$1678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6107$1678_Y + end + attribute \src "ls180.v:6107.41-6107.145" + cell $and $and$ls180.v:6107$1680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6107$1678_Y + connect \B $eq$ls180.v:6107$1679_Y + connect \Y $and$ls180.v:6107$1680_Y + end + attribute \src "ls180.v:6108.42-6108.98" + cell $and $and$ls180.v:6108$1682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6108$1681_Y + connect \Y $and$ls180.v:6108$1682_Y + end + attribute \src "ls180.v:6108.41-6108.148" + cell $and $and$ls180.v:6108$1684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6108$1682_Y + connect \B $eq$ls180.v:6108$1683_Y + connect \Y $and$ls180.v:6108$1684_Y + end + attribute \src "ls180.v:6110.42-6110.95" + cell $and $and$ls180.v:6110$1685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6110$1685_Y + end + attribute \src "ls180.v:6110.41-6110.145" + cell $and $and$ls180.v:6110$1687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6110$1685_Y + connect \B $eq$ls180.v:6110$1686_Y + connect \Y $and$ls180.v:6110$1687_Y + end + attribute \src "ls180.v:6111.42-6111.98" + cell $and $and$ls180.v:6111$1689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6111$1688_Y + connect \Y $and$ls180.v:6111$1689_Y + end + attribute \src "ls180.v:6111.41-6111.148" + cell $and $and$ls180.v:6111$1691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6111$1689_Y + connect \B $eq$ls180.v:6111$1690_Y + connect \Y $and$ls180.v:6111$1691_Y + end + attribute \src "ls180.v:6113.42-6113.95" + cell $and $and$ls180.v:6113$1692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6113$1692_Y + end + attribute \src "ls180.v:6113.41-6113.145" + cell $and $and$ls180.v:6113$1694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6113$1692_Y + connect \B $eq$ls180.v:6113$1693_Y + connect \Y $and$ls180.v:6113$1694_Y + end + attribute \src "ls180.v:6114.42-6114.98" + cell $and $and$ls180.v:6114$1696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6114$1695_Y + connect \Y $and$ls180.v:6114$1696_Y + end + attribute \src "ls180.v:6114.41-6114.148" + cell $and $and$ls180.v:6114$1698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6114$1696_Y + connect \B $eq$ls180.v:6114$1697_Y + connect \Y $and$ls180.v:6114$1698_Y + end + attribute \src "ls180.v:6116.42-6116.95" + cell $and $and$ls180.v:6116$1699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6116$1699_Y + end + attribute \src "ls180.v:6116.41-6116.145" + cell $and $and$ls180.v:6116$1701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6116$1699_Y + connect \B $eq$ls180.v:6116$1700_Y + connect \Y $and$ls180.v:6116$1701_Y + end + attribute \src "ls180.v:6117.42-6117.98" + cell $and $and$ls180.v:6117$1703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6117$1702_Y + connect \Y $and$ls180.v:6117$1703_Y + end + attribute \src "ls180.v:6117.41-6117.148" + cell $and $and$ls180.v:6117$1705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6117$1703_Y + connect \B $eq$ls180.v:6117$1704_Y + connect \Y $and$ls180.v:6117$1705_Y + end + attribute \src "ls180.v:6119.42-6119.95" + cell $and $and$ls180.v:6119$1706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6119$1706_Y + end + attribute \src "ls180.v:6119.41-6119.145" + cell $and $and$ls180.v:6119$1708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6119$1706_Y + connect \B $eq$ls180.v:6119$1707_Y + connect \Y $and$ls180.v:6119$1708_Y + end + attribute \src "ls180.v:6120.42-6120.98" + cell $and $and$ls180.v:6120$1710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6120$1709_Y + connect \Y $and$ls180.v:6120$1710_Y + end + attribute \src "ls180.v:6120.41-6120.148" + cell $and $and$ls180.v:6120$1712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6120$1710_Y + connect \B $eq$ls180.v:6120$1711_Y + connect \Y $and$ls180.v:6120$1712_Y + end + attribute \src "ls180.v:6122.42-6122.95" + cell $and $and$ls180.v:6122$1713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6122$1713_Y + end + attribute \src "ls180.v:6122.41-6122.145" + cell $and $and$ls180.v:6122$1715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6122$1713_Y + connect \B $eq$ls180.v:6122$1714_Y + connect \Y $and$ls180.v:6122$1715_Y + end + attribute \src "ls180.v:6123.42-6123.98" + cell $and $and$ls180.v:6123$1717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6123$1716_Y + connect \Y $and$ls180.v:6123$1717_Y + end + attribute \src "ls180.v:6123.41-6123.148" + cell $and $and$ls180.v:6123$1719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6123$1717_Y + connect \B $eq$ls180.v:6123$1718_Y + connect \Y $and$ls180.v:6123$1719_Y + end + attribute \src "ls180.v:6125.42-6125.95" + cell $and $and$ls180.v:6125$1720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6125$1720_Y + end + attribute \src "ls180.v:6125.41-6125.145" + cell $and $and$ls180.v:6125$1722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6125$1720_Y + connect \B $eq$ls180.v:6125$1721_Y + connect \Y $and$ls180.v:6125$1722_Y + end + attribute \src "ls180.v:6126.42-6126.98" + cell $and $and$ls180.v:6126$1724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6126$1723_Y + connect \Y $and$ls180.v:6126$1724_Y + end + attribute \src "ls180.v:6126.41-6126.148" + cell $and $and$ls180.v:6126$1726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6126$1724_Y + connect \B $eq$ls180.v:6126$1725_Y + connect \Y $and$ls180.v:6126$1726_Y + end + attribute \src "ls180.v:6128.44-6128.97" + cell $and $and$ls180.v:6128$1727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6128$1727_Y + end + attribute \src "ls180.v:6128.43-6128.147" + cell $and $and$ls180.v:6128$1729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6128$1727_Y + connect \B $eq$ls180.v:6128$1728_Y + connect \Y $and$ls180.v:6128$1729_Y + end + attribute \src "ls180.v:6129.44-6129.100" + cell $and $and$ls180.v:6129$1731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6129$1730_Y + connect \Y $and$ls180.v:6129$1731_Y + end + attribute \src "ls180.v:6129.43-6129.150" + cell $and $and$ls180.v:6129$1733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6129$1731_Y + connect \B $eq$ls180.v:6129$1732_Y + connect \Y $and$ls180.v:6129$1733_Y + end + attribute \src "ls180.v:6131.44-6131.97" + cell $and $and$ls180.v:6131$1734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6131$1734_Y + end + attribute \src "ls180.v:6131.43-6131.147" + cell $and $and$ls180.v:6131$1736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6131$1734_Y + connect \B $eq$ls180.v:6131$1735_Y + connect \Y $and$ls180.v:6131$1736_Y + end + attribute \src "ls180.v:6132.44-6132.100" + cell $and $and$ls180.v:6132$1738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6132$1737_Y + connect \Y $and$ls180.v:6132$1738_Y + end + attribute \src "ls180.v:6132.43-6132.150" + cell $and $and$ls180.v:6132$1740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6132$1738_Y + connect \B $eq$ls180.v:6132$1739_Y + connect \Y $and$ls180.v:6132$1740_Y + end + attribute \src "ls180.v:6134.44-6134.97" + cell $and $and$ls180.v:6134$1741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6134$1741_Y + end + attribute \src "ls180.v:6134.43-6134.148" + cell $and $and$ls180.v:6134$1743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6134$1741_Y + connect \B $eq$ls180.v:6134$1742_Y + connect \Y $and$ls180.v:6134$1743_Y + end + attribute \src "ls180.v:6135.44-6135.100" + cell $and $and$ls180.v:6135$1745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6135$1744_Y + connect \Y $and$ls180.v:6135$1745_Y + end + attribute \src "ls180.v:6135.43-6135.151" + cell $and $and$ls180.v:6135$1747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6135$1745_Y + connect \B $eq$ls180.v:6135$1746_Y + connect \Y $and$ls180.v:6135$1747_Y + end + attribute \src "ls180.v:6137.44-6137.97" + cell $and $and$ls180.v:6137$1748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6137$1748_Y + end + attribute \src "ls180.v:6137.43-6137.148" + cell $and $and$ls180.v:6137$1750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6137$1748_Y + connect \B $eq$ls180.v:6137$1749_Y + connect \Y $and$ls180.v:6137$1750_Y + end + attribute \src "ls180.v:6138.44-6138.100" + cell $and $and$ls180.v:6138$1752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6138$1751_Y + connect \Y $and$ls180.v:6138$1752_Y + end + attribute \src "ls180.v:6138.43-6138.151" + cell $and $and$ls180.v:6138$1754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6138$1752_Y + connect \B $eq$ls180.v:6138$1753_Y + connect \Y $and$ls180.v:6138$1754_Y + end + attribute \src "ls180.v:6140.44-6140.97" + cell $and $and$ls180.v:6140$1755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6140$1755_Y + end + attribute \src "ls180.v:6140.43-6140.148" + cell $and $and$ls180.v:6140$1757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6140$1755_Y + connect \B $eq$ls180.v:6140$1756_Y + connect \Y $and$ls180.v:6140$1757_Y + end + attribute \src "ls180.v:6141.44-6141.100" + cell $and $and$ls180.v:6141$1759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6141$1758_Y + connect \Y $and$ls180.v:6141$1759_Y + end + attribute \src "ls180.v:6141.43-6141.151" + cell $and $and$ls180.v:6141$1761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6141$1759_Y + connect \B $eq$ls180.v:6141$1760_Y + connect \Y $and$ls180.v:6141$1761_Y + end + attribute \src "ls180.v:6143.41-6143.94" + cell $and $and$ls180.v:6143$1762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6143$1762_Y + end + attribute \src "ls180.v:6143.40-6143.145" + cell $and $and$ls180.v:6143$1764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6143$1762_Y + connect \B $eq$ls180.v:6143$1763_Y + connect \Y $and$ls180.v:6143$1764_Y + end + attribute \src "ls180.v:6144.41-6144.97" + cell $and $and$ls180.v:6144$1766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6144$1765_Y + connect \Y $and$ls180.v:6144$1766_Y + end + attribute \src "ls180.v:6144.40-6144.148" + cell $and $and$ls180.v:6144$1768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6144$1766_Y + connect \B $eq$ls180.v:6144$1767_Y + connect \Y $and$ls180.v:6144$1768_Y + end + attribute \src "ls180.v:6146.42-6146.95" + cell $and $and$ls180.v:6146$1769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6146$1769_Y + end + attribute \src "ls180.v:6146.41-6146.146" + cell $and $and$ls180.v:6146$1771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6146$1769_Y + connect \B $eq$ls180.v:6146$1770_Y + connect \Y $and$ls180.v:6146$1771_Y + end + attribute \src "ls180.v:6147.42-6147.98" + cell $and $and$ls180.v:6147$1773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6147$1772_Y + connect \Y $and$ls180.v:6147$1773_Y + end + attribute \src "ls180.v:6147.41-6147.149" + cell $and $and$ls180.v:6147$1775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6147$1773_Y + connect \B $eq$ls180.v:6147$1774_Y + connect \Y $and$ls180.v:6147$1775_Y + end + attribute \src "ls180.v:6149.44-6149.97" + cell $and $and$ls180.v:6149$1776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6149$1776_Y + end + attribute \src "ls180.v:6149.43-6149.148" + cell $and $and$ls180.v:6149$1778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6149$1776_Y + connect \B $eq$ls180.v:6149$1777_Y + connect \Y $and$ls180.v:6149$1778_Y + end + attribute \src "ls180.v:6150.44-6150.100" + cell $and $and$ls180.v:6150$1780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6150$1779_Y + connect \Y $and$ls180.v:6150$1780_Y + end + attribute \src "ls180.v:6150.43-6150.151" + cell $and $and$ls180.v:6150$1782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6150$1780_Y + connect \B $eq$ls180.v:6150$1781_Y + connect \Y $and$ls180.v:6150$1782_Y + end + attribute \src "ls180.v:6152.44-6152.97" + cell $and $and$ls180.v:6152$1783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6152$1783_Y + end + attribute \src "ls180.v:6152.43-6152.148" + cell $and $and$ls180.v:6152$1785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6152$1783_Y + connect \B $eq$ls180.v:6152$1784_Y + connect \Y $and$ls180.v:6152$1785_Y + end + attribute \src "ls180.v:6153.44-6153.100" + cell $and $and$ls180.v:6153$1787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6153$1786_Y + connect \Y $and$ls180.v:6153$1787_Y + end + attribute \src "ls180.v:6153.43-6153.151" + cell $and $and$ls180.v:6153$1789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6153$1787_Y + connect \B $eq$ls180.v:6153$1788_Y + connect \Y $and$ls180.v:6153$1789_Y + end + attribute \src "ls180.v:6155.44-6155.97" + cell $and $and$ls180.v:6155$1790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6155$1790_Y + end + attribute \src "ls180.v:6155.43-6155.148" + cell $and $and$ls180.v:6155$1792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6155$1790_Y + connect \B $eq$ls180.v:6155$1791_Y + connect \Y $and$ls180.v:6155$1792_Y + end + attribute \src "ls180.v:6156.44-6156.100" + cell $and $and$ls180.v:6156$1794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6156$1793_Y + connect \Y $and$ls180.v:6156$1794_Y + end + attribute \src "ls180.v:6156.43-6156.151" + cell $and $and$ls180.v:6156$1796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6156$1794_Y + connect \B $eq$ls180.v:6156$1795_Y + connect \Y $and$ls180.v:6156$1796_Y + end + attribute \src "ls180.v:6158.44-6158.97" + cell $and $and$ls180.v:6158$1797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6158$1797_Y + end + attribute \src "ls180.v:6158.43-6158.148" + cell $and $and$ls180.v:6158$1799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6158$1797_Y + connect \B $eq$ls180.v:6158$1798_Y + connect \Y $and$ls180.v:6158$1799_Y + end + attribute \src "ls180.v:6159.44-6159.100" + cell $and $and$ls180.v:6159$1801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6159$1800_Y + connect \Y $and$ls180.v:6159$1801_Y + end + attribute \src "ls180.v:6159.43-6159.151" + cell $and $and$ls180.v:6159$1803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6159$1801_Y + connect \B $eq$ls180.v:6159$1802_Y + connect \Y $and$ls180.v:6159$1803_Y + end + attribute \src "ls180.v:6183.44-6183.97" + cell $and $and$ls180.v:6183$1805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6183$1805_Y + end + attribute \src "ls180.v:6183.43-6183.147" + cell $and $and$ls180.v:6183$1807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6183$1805_Y + connect \B $eq$ls180.v:6183$1806_Y + connect \Y $and$ls180.v:6183$1807_Y + end + attribute \src "ls180.v:6184.44-6184.100" + cell $and $and$ls180.v:6184$1809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6184$1808_Y + connect \Y $and$ls180.v:6184$1809_Y + end + attribute \src "ls180.v:6184.43-6184.150" + cell $and $and$ls180.v:6184$1811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6184$1809_Y + connect \B $eq$ls180.v:6184$1810_Y + connect \Y $and$ls180.v:6184$1811_Y + end + attribute \src "ls180.v:6186.49-6186.102" + cell $and $and$ls180.v:6186$1812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6186$1812_Y + end + attribute \src "ls180.v:6186.48-6186.152" + cell $and $and$ls180.v:6186$1814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6186$1812_Y + connect \B $eq$ls180.v:6186$1813_Y + connect \Y $and$ls180.v:6186$1814_Y + end + attribute \src "ls180.v:6187.49-6187.105" + cell $and $and$ls180.v:6187$1816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6187$1815_Y + connect \Y $and$ls180.v:6187$1816_Y + end + attribute \src "ls180.v:6187.48-6187.155" + cell $and $and$ls180.v:6187$1818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6187$1816_Y + connect \B $eq$ls180.v:6187$1817_Y + connect \Y $and$ls180.v:6187$1818_Y + end + attribute \src "ls180.v:6189.49-6189.102" + cell $and $and$ls180.v:6189$1819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6189$1819_Y + end + attribute \src "ls180.v:6189.48-6189.152" + cell $and $and$ls180.v:6189$1821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6189$1819_Y + connect \B $eq$ls180.v:6189$1820_Y + connect \Y $and$ls180.v:6189$1821_Y + end + attribute \src "ls180.v:6190.49-6190.105" + cell $and $and$ls180.v:6190$1823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6190$1822_Y + connect \Y $and$ls180.v:6190$1823_Y + end + attribute \src "ls180.v:6190.48-6190.155" + cell $and $and$ls180.v:6190$1825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6190$1823_Y + connect \B $eq$ls180.v:6190$1824_Y + connect \Y $and$ls180.v:6190$1825_Y + end + attribute \src "ls180.v:6192.42-6192.95" + cell $and $and$ls180.v:6192$1826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6192$1826_Y + end + attribute \src "ls180.v:6192.41-6192.145" + cell $and $and$ls180.v:6192$1828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6192$1826_Y + connect \B $eq$ls180.v:6192$1827_Y + connect \Y $and$ls180.v:6192$1828_Y + end + attribute \src "ls180.v:6193.42-6193.98" + cell $and $and$ls180.v:6193$1830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6193$1829_Y + connect \Y $and$ls180.v:6193$1830_Y + end + attribute \src "ls180.v:6193.41-6193.148" + cell $and $and$ls180.v:6193$1832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6193$1830_Y + connect \B $eq$ls180.v:6193$1831_Y + connect \Y $and$ls180.v:6193$1832_Y + end + attribute \src "ls180.v:6200.46-6200.99" + cell $and $and$ls180.v:6200$1834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6200$1834_Y + end + attribute \src "ls180.v:6200.45-6200.149" + cell $and $and$ls180.v:6200$1836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6200$1834_Y + connect \B $eq$ls180.v:6200$1835_Y + connect \Y $and$ls180.v:6200$1836_Y + end + attribute \src "ls180.v:6201.46-6201.102" + cell $and $and$ls180.v:6201$1838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6201$1837_Y + connect \Y $and$ls180.v:6201$1838_Y + end + attribute \src "ls180.v:6201.45-6201.152" + cell $and $and$ls180.v:6201$1840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6201$1838_Y + connect \B $eq$ls180.v:6201$1839_Y + connect \Y $and$ls180.v:6201$1840_Y + end + attribute \src "ls180.v:6203.50-6203.103" + cell $and $and$ls180.v:6203$1841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6203$1841_Y + end + attribute \src "ls180.v:6203.49-6203.153" + cell $and $and$ls180.v:6203$1843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6203$1841_Y + connect \B $eq$ls180.v:6203$1842_Y + connect \Y $and$ls180.v:6203$1843_Y + end + attribute \src "ls180.v:6204.50-6204.106" + cell $and $and$ls180.v:6204$1845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6204$1844_Y + connect \Y $and$ls180.v:6204$1845_Y + end + attribute \src "ls180.v:6204.49-6204.156" + cell $and $and$ls180.v:6204$1847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6204$1845_Y + connect \B $eq$ls180.v:6204$1846_Y + connect \Y $and$ls180.v:6204$1847_Y + end + attribute \src "ls180.v:6206.40-6206.93" + cell $and $and$ls180.v:6206$1848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6206$1848_Y + end + attribute \src "ls180.v:6206.39-6206.143" + cell $and $and$ls180.v:6206$1850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6206$1848_Y + connect \B $eq$ls180.v:6206$1849_Y + connect \Y $and$ls180.v:6206$1850_Y + end + attribute \src "ls180.v:6207.40-6207.96" + cell $and $and$ls180.v:6207$1852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6207$1851_Y + connect \Y $and$ls180.v:6207$1852_Y + end + attribute \src "ls180.v:6207.39-6207.146" + cell $and $and$ls180.v:6207$1854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6207$1852_Y + connect \B $eq$ls180.v:6207$1853_Y + connect \Y $and$ls180.v:6207$1854_Y + end + attribute \src "ls180.v:6209.50-6209.103" + cell $and $and$ls180.v:6209$1855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6209$1855_Y + end + attribute \src "ls180.v:6209.49-6209.153" + cell $and $and$ls180.v:6209$1857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6209$1855_Y + connect \B $eq$ls180.v:6209$1856_Y + connect \Y $and$ls180.v:6209$1857_Y + end + attribute \src "ls180.v:6210.50-6210.106" + cell $and $and$ls180.v:6210$1859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6210$1858_Y + connect \Y $and$ls180.v:6210$1859_Y + end + attribute \src "ls180.v:6210.49-6210.156" + cell $and $and$ls180.v:6210$1861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6210$1859_Y + connect \B $eq$ls180.v:6210$1860_Y + connect \Y $and$ls180.v:6210$1861_Y + end + attribute \src "ls180.v:6212.50-6212.103" + cell $and $and$ls180.v:6212$1862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6212$1862_Y + end + attribute \src "ls180.v:6212.49-6212.153" + cell $and $and$ls180.v:6212$1864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6212$1862_Y + connect \B $eq$ls180.v:6212$1863_Y + connect \Y $and$ls180.v:6212$1864_Y + end + attribute \src "ls180.v:6213.50-6213.106" + cell $and $and$ls180.v:6213$1866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6213$1865_Y + connect \Y $and$ls180.v:6213$1866_Y + end + attribute \src "ls180.v:6213.49-6213.156" + cell $and $and$ls180.v:6213$1868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6213$1866_Y + connect \B $eq$ls180.v:6213$1867_Y + connect \Y $and$ls180.v:6213$1868_Y + end + attribute \src "ls180.v:6215.51-6215.104" + cell $and $and$ls180.v:6215$1869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6215$1869_Y + end + attribute \src "ls180.v:6215.50-6215.154" + cell $and $and$ls180.v:6215$1871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6215$1869_Y + connect \B $eq$ls180.v:6215$1870_Y + connect \Y $and$ls180.v:6215$1871_Y + end + attribute \src "ls180.v:6216.51-6216.107" + cell $and $and$ls180.v:6216$1873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6216$1872_Y + connect \Y $and$ls180.v:6216$1873_Y + end + attribute \src "ls180.v:6216.50-6216.157" + cell $and $and$ls180.v:6216$1875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6216$1873_Y + connect \B $eq$ls180.v:6216$1874_Y + connect \Y $and$ls180.v:6216$1875_Y + end + attribute \src "ls180.v:6218.49-6218.102" + cell $and $and$ls180.v:6218$1876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6218$1876_Y + end + attribute \src "ls180.v:6218.48-6218.152" + cell $and $and$ls180.v:6218$1878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6218$1876_Y + connect \B $eq$ls180.v:6218$1877_Y + connect \Y $and$ls180.v:6218$1878_Y + end + attribute \src "ls180.v:6219.49-6219.105" + cell $and $and$ls180.v:6219$1880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6219$1879_Y + connect \Y $and$ls180.v:6219$1880_Y + end + attribute \src "ls180.v:6219.48-6219.155" + cell $and $and$ls180.v:6219$1882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6219$1880_Y + connect \B $eq$ls180.v:6219$1881_Y + connect \Y $and$ls180.v:6219$1882_Y + end + attribute \src "ls180.v:6221.49-6221.102" + cell $and $and$ls180.v:6221$1883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6221$1883_Y + end + attribute \src "ls180.v:6221.48-6221.152" + cell $and $and$ls180.v:6221$1885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6221$1883_Y + connect \B $eq$ls180.v:6221$1884_Y + connect \Y $and$ls180.v:6221$1885_Y + end + attribute \src "ls180.v:6222.49-6222.105" + cell $and $and$ls180.v:6222$1887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6222$1886_Y + connect \Y $and$ls180.v:6222$1887_Y + end + attribute \src "ls180.v:6222.48-6222.155" + cell $and $and$ls180.v:6222$1889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6222$1887_Y + connect \B $eq$ls180.v:6222$1888_Y + connect \Y $and$ls180.v:6222$1889_Y + end + attribute \src "ls180.v:6224.49-6224.102" + cell $and $and$ls180.v:6224$1890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6224$1890_Y + end + attribute \src "ls180.v:6224.48-6224.152" + cell $and $and$ls180.v:6224$1892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6224$1890_Y + connect \B $eq$ls180.v:6224$1891_Y + connect \Y $and$ls180.v:6224$1892_Y + end + attribute \src "ls180.v:6225.49-6225.105" + cell $and $and$ls180.v:6225$1894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6225$1893_Y + connect \Y $and$ls180.v:6225$1894_Y + end + attribute \src "ls180.v:6225.48-6225.155" + cell $and $and$ls180.v:6225$1896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6225$1894_Y + connect \B $eq$ls180.v:6225$1895_Y + connect \Y $and$ls180.v:6225$1896_Y + end + attribute \src "ls180.v:6227.49-6227.102" + cell $and $and$ls180.v:6227$1897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6227$1897_Y + end + attribute \src "ls180.v:6227.48-6227.152" + cell $and $and$ls180.v:6227$1899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6227$1897_Y + connect \B $eq$ls180.v:6227$1898_Y + connect \Y $and$ls180.v:6227$1899_Y + end + attribute \src "ls180.v:6228.49-6228.105" + cell $and $and$ls180.v:6228$1901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6228$1900_Y + connect \Y $and$ls180.v:6228$1901_Y + end + attribute \src "ls180.v:6228.48-6228.155" + cell $and $and$ls180.v:6228$1903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6228$1901_Y + connect \B $eq$ls180.v:6228$1902_Y + connect \Y $and$ls180.v:6228$1903_Y + end + attribute \src "ls180.v:6245.42-6245.97" + cell $and $and$ls180.v:6245$1905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6245$1905_Y + end + attribute \src "ls180.v:6245.41-6245.148" + cell $and $and$ls180.v:6245$1907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6245$1905_Y + connect \B $eq$ls180.v:6245$1906_Y + connect \Y $and$ls180.v:6245$1907_Y + end + attribute \src "ls180.v:6246.42-6246.100" + cell $and $and$ls180.v:6246$1909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6246$1908_Y + connect \Y $and$ls180.v:6246$1909_Y + end + attribute \src "ls180.v:6246.41-6246.151" + cell $and $and$ls180.v:6246$1911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6246$1909_Y + connect \B $eq$ls180.v:6246$1910_Y + connect \Y $and$ls180.v:6246$1911_Y + end + attribute \src "ls180.v:6248.42-6248.97" + cell $and $and$ls180.v:6248$1912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6248$1912_Y + end + attribute \src "ls180.v:6248.41-6248.148" + cell $and $and$ls180.v:6248$1914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6248$1912_Y + connect \B $eq$ls180.v:6248$1913_Y + connect \Y $and$ls180.v:6248$1914_Y + end + attribute \src "ls180.v:6249.42-6249.100" + cell $and $and$ls180.v:6249$1916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6249$1915_Y + connect \Y $and$ls180.v:6249$1916_Y + end + attribute \src "ls180.v:6249.41-6249.151" + cell $and $and$ls180.v:6249$1918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6249$1916_Y + connect \B $eq$ls180.v:6249$1917_Y + connect \Y $and$ls180.v:6249$1918_Y + end + attribute \src "ls180.v:6251.40-6251.95" + cell $and $and$ls180.v:6251$1919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6251$1919_Y + end + attribute \src "ls180.v:6251.39-6251.146" + cell $and $and$ls180.v:6251$1921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6251$1919_Y + connect \B $eq$ls180.v:6251$1920_Y + connect \Y $and$ls180.v:6251$1921_Y + end + attribute \src "ls180.v:6252.40-6252.98" + cell $and $and$ls180.v:6252$1923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6252$1922_Y + connect \Y $and$ls180.v:6252$1923_Y + end + attribute \src "ls180.v:6252.39-6252.149" + cell $and $and$ls180.v:6252$1925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6252$1923_Y + connect \B $eq$ls180.v:6252$1924_Y + connect \Y $and$ls180.v:6252$1925_Y + end + attribute \src "ls180.v:6254.39-6254.94" + cell $and $and$ls180.v:6254$1926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6254$1926_Y + end + attribute \src "ls180.v:6254.38-6254.145" + cell $and $and$ls180.v:6254$1928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6254$1926_Y + connect \B $eq$ls180.v:6254$1927_Y + connect \Y $and$ls180.v:6254$1928_Y + end + attribute \src "ls180.v:6255.39-6255.97" + cell $and $and$ls180.v:6255$1930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6255$1929_Y + connect \Y $and$ls180.v:6255$1930_Y + end + attribute \src "ls180.v:6255.38-6255.148" + cell $and $and$ls180.v:6255$1932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6255$1930_Y + connect \B $eq$ls180.v:6255$1931_Y + connect \Y $and$ls180.v:6255$1932_Y + end + attribute \src "ls180.v:6257.38-6257.93" + cell $and $and$ls180.v:6257$1933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6257$1933_Y + end + attribute \src "ls180.v:6257.37-6257.144" + cell $and $and$ls180.v:6257$1935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6257$1933_Y + connect \B $eq$ls180.v:6257$1934_Y + connect \Y $and$ls180.v:6257$1935_Y + end + attribute \src "ls180.v:6258.38-6258.96" + cell $and $and$ls180.v:6258$1937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6258$1936_Y + connect \Y $and$ls180.v:6258$1937_Y + end + attribute \src "ls180.v:6258.37-6258.147" + cell $and $and$ls180.v:6258$1939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6258$1937_Y + connect \B $eq$ls180.v:6258$1938_Y + connect \Y $and$ls180.v:6258$1939_Y + end + attribute \src "ls180.v:6260.37-6260.92" + cell $and $and$ls180.v:6260$1940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6260$1940_Y + end + attribute \src "ls180.v:6260.36-6260.143" + cell $and $and$ls180.v:6260$1942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6260$1940_Y + connect \B $eq$ls180.v:6260$1941_Y + connect \Y $and$ls180.v:6260$1942_Y + end + attribute \src "ls180.v:6261.37-6261.95" + cell $and $and$ls180.v:6261$1944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6261$1943_Y + connect \Y $and$ls180.v:6261$1944_Y + end + attribute \src "ls180.v:6261.36-6261.146" + cell $and $and$ls180.v:6261$1946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6261$1944_Y + connect \B $eq$ls180.v:6261$1945_Y + connect \Y $and$ls180.v:6261$1946_Y + end + attribute \src "ls180.v:6263.43-6263.98" + cell $and $and$ls180.v:6263$1947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6263$1947_Y + end + attribute \src "ls180.v:6263.42-6263.149" + cell $and $and$ls180.v:6263$1949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6263$1947_Y + connect \B $eq$ls180.v:6263$1948_Y + connect \Y $and$ls180.v:6263$1949_Y + end + attribute \src "ls180.v:6264.43-6264.101" + cell $and $and$ls180.v:6264$1951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6264$1950_Y + connect \Y $and$ls180.v:6264$1951_Y + end + attribute \src "ls180.v:6264.42-6264.152" + cell $and $and$ls180.v:6264$1953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6264$1951_Y + connect \B $eq$ls180.v:6264$1952_Y + connect \Y $and$ls180.v:6264$1953_Y + end + attribute \src "ls180.v:6285.42-6285.97" + cell $and $and$ls180.v:6285$1956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6285$1956_Y + end + attribute \src "ls180.v:6285.41-6285.148" + cell $and $and$ls180.v:6285$1958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6285$1956_Y + connect \B $eq$ls180.v:6285$1957_Y + connect \Y $and$ls180.v:6285$1958_Y + end + attribute \src "ls180.v:6286.42-6286.100" + cell $and $and$ls180.v:6286$1960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6286$1959_Y + connect \Y $and$ls180.v:6286$1960_Y + end + attribute \src "ls180.v:6286.41-6286.151" + cell $and $and$ls180.v:6286$1962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6286$1960_Y + connect \B $eq$ls180.v:6286$1961_Y + connect \Y $and$ls180.v:6286$1962_Y + end + attribute \src "ls180.v:6288.42-6288.97" + cell $and $and$ls180.v:6288$1963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6288$1963_Y + end + attribute \src "ls180.v:6288.41-6288.148" + cell $and $and$ls180.v:6288$1965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6288$1963_Y + connect \B $eq$ls180.v:6288$1964_Y + connect \Y $and$ls180.v:6288$1965_Y + end + attribute \src "ls180.v:6289.42-6289.100" + cell $and $and$ls180.v:6289$1967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6289$1966_Y + connect \Y $and$ls180.v:6289$1967_Y + end + attribute \src "ls180.v:6289.41-6289.151" + cell $and $and$ls180.v:6289$1969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6289$1967_Y + connect \B $eq$ls180.v:6289$1968_Y + connect \Y $and$ls180.v:6289$1969_Y + end + attribute \src "ls180.v:6291.40-6291.95" + cell $and $and$ls180.v:6291$1970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6291$1970_Y + end + attribute \src "ls180.v:6291.39-6291.146" + cell $and $and$ls180.v:6291$1972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6291$1970_Y + connect \B $eq$ls180.v:6291$1971_Y + connect \Y $and$ls180.v:6291$1972_Y + end + attribute \src "ls180.v:6292.40-6292.98" + cell $and $and$ls180.v:6292$1974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6292$1973_Y + connect \Y $and$ls180.v:6292$1974_Y + end + attribute \src "ls180.v:6292.39-6292.149" + cell $and $and$ls180.v:6292$1976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6292$1974_Y + connect \B $eq$ls180.v:6292$1975_Y + connect \Y $and$ls180.v:6292$1976_Y + end + attribute \src "ls180.v:6294.39-6294.94" + cell $and $and$ls180.v:6294$1977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6294$1977_Y + end + attribute \src "ls180.v:6294.38-6294.145" + cell $and $and$ls180.v:6294$1979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6294$1977_Y + connect \B $eq$ls180.v:6294$1978_Y + connect \Y $and$ls180.v:6294$1979_Y + end + attribute \src "ls180.v:6295.39-6295.97" + cell $and $and$ls180.v:6295$1981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6295$1980_Y + connect \Y $and$ls180.v:6295$1981_Y + end + attribute \src "ls180.v:6295.38-6295.148" + cell $and $and$ls180.v:6295$1983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6295$1981_Y + connect \B $eq$ls180.v:6295$1982_Y + connect \Y $and$ls180.v:6295$1983_Y + end + attribute \src "ls180.v:6297.38-6297.93" + cell $and $and$ls180.v:6297$1984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6297$1984_Y + end + attribute \src "ls180.v:6297.37-6297.144" + cell $and $and$ls180.v:6297$1986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6297$1984_Y + connect \B $eq$ls180.v:6297$1985_Y + connect \Y $and$ls180.v:6297$1986_Y + end + attribute \src "ls180.v:6298.38-6298.96" + cell $and $and$ls180.v:6298$1988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6298$1987_Y + connect \Y $and$ls180.v:6298$1988_Y + end + attribute \src "ls180.v:6298.37-6298.147" + cell $and $and$ls180.v:6298$1990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6298$1988_Y + connect \B $eq$ls180.v:6298$1989_Y + connect \Y $and$ls180.v:6298$1990_Y + end + attribute \src "ls180.v:6300.37-6300.92" + cell $and $and$ls180.v:6300$1991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6300$1991_Y + end + attribute \src "ls180.v:6300.36-6300.143" + cell $and $and$ls180.v:6300$1993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6300$1991_Y + connect \B $eq$ls180.v:6300$1992_Y + connect \Y $and$ls180.v:6300$1993_Y + end + attribute \src "ls180.v:6301.37-6301.95" + cell $and $and$ls180.v:6301$1995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6301$1994_Y + connect \Y $and$ls180.v:6301$1995_Y + end + attribute \src "ls180.v:6301.36-6301.146" + cell $and $and$ls180.v:6301$1997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6301$1995_Y + connect \B $eq$ls180.v:6301$1996_Y + connect \Y $and$ls180.v:6301$1997_Y + end + attribute \src "ls180.v:6303.43-6303.98" + cell $and $and$ls180.v:6303$1998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6303$1998_Y + end + attribute \src "ls180.v:6303.42-6303.149" + cell $and $and$ls180.v:6303$2000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6303$1998_Y + connect \B $eq$ls180.v:6303$1999_Y + connect \Y $and$ls180.v:6303$2000_Y + end + attribute \src "ls180.v:6304.43-6304.101" + cell $and $and$ls180.v:6304$2002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6304$2001_Y + connect \Y $and$ls180.v:6304$2002_Y + end + attribute \src "ls180.v:6304.42-6304.152" + cell $and $and$ls180.v:6304$2004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6304$2002_Y + connect \B $eq$ls180.v:6304$2003_Y + connect \Y $and$ls180.v:6304$2004_Y + end + attribute \src "ls180.v:6306.46-6306.101" + cell $and $and$ls180.v:6306$2005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6306$2005_Y + end + attribute \src "ls180.v:6306.45-6306.152" + cell $and $and$ls180.v:6306$2007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6306$2005_Y + connect \B $eq$ls180.v:6306$2006_Y + connect \Y $and$ls180.v:6306$2007_Y + end + attribute \src "ls180.v:6307.46-6307.104" + cell $and $and$ls180.v:6307$2009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6307$2008_Y + connect \Y $and$ls180.v:6307$2009_Y + end + attribute \src "ls180.v:6307.45-6307.155" + cell $and $and$ls180.v:6307$2011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6307$2009_Y + connect \B $eq$ls180.v:6307$2010_Y + connect \Y $and$ls180.v:6307$2011_Y + end + attribute \src "ls180.v:6309.46-6309.101" + cell $and $and$ls180.v:6309$2012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6309$2012_Y + end + attribute \src "ls180.v:6309.45-6309.152" + cell $and $and$ls180.v:6309$2014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6309$2012_Y + connect \B $eq$ls180.v:6309$2013_Y + connect \Y $and$ls180.v:6309$2014_Y + end + attribute \src "ls180.v:6310.46-6310.104" + cell $and $and$ls180.v:6310$2016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6310$2015_Y + connect \Y $and$ls180.v:6310$2016_Y + end + attribute \src "ls180.v:6310.45-6310.155" + cell $and $and$ls180.v:6310$2018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6310$2016_Y + connect \B $eq$ls180.v:6310$2017_Y + connect \Y $and$ls180.v:6310$2018_Y + end + attribute \src "ls180.v:6333.39-6333.94" + cell $and $and$ls180.v:6333$2021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6333$2021_Y + end + attribute \src "ls180.v:6333.38-6333.145" + cell $and $and$ls180.v:6333$2023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6333$2021_Y + connect \B $eq$ls180.v:6333$2022_Y + connect \Y $and$ls180.v:6333$2023_Y + end + attribute \src "ls180.v:6334.39-6334.97" + cell $and $and$ls180.v:6334$2025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6334$2024_Y + connect \Y $and$ls180.v:6334$2025_Y + end + attribute \src "ls180.v:6334.38-6334.148" + cell $and $and$ls180.v:6334$2027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6334$2025_Y + connect \B $eq$ls180.v:6334$2026_Y + connect \Y $and$ls180.v:6334$2027_Y + end + attribute \src "ls180.v:6336.39-6336.94" + cell $and $and$ls180.v:6336$2028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6336$2028_Y + end + attribute \src "ls180.v:6336.38-6336.145" + cell $and $and$ls180.v:6336$2030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6336$2028_Y + connect \B $eq$ls180.v:6336$2029_Y + connect \Y $and$ls180.v:6336$2030_Y + end + attribute \src "ls180.v:6337.39-6337.97" + cell $and $and$ls180.v:6337$2032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6337$2031_Y + connect \Y $and$ls180.v:6337$2032_Y + end + attribute \src "ls180.v:6337.38-6337.148" + cell $and $and$ls180.v:6337$2034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6337$2032_Y + connect \B $eq$ls180.v:6337$2033_Y + connect \Y $and$ls180.v:6337$2034_Y + end + attribute \src "ls180.v:6339.39-6339.94" + cell $and $and$ls180.v:6339$2035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6339$2035_Y + end + attribute \src "ls180.v:6339.38-6339.145" + cell $and $and$ls180.v:6339$2037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6339$2035_Y + connect \B $eq$ls180.v:6339$2036_Y + connect \Y $and$ls180.v:6339$2037_Y + end + attribute \src "ls180.v:6340.39-6340.97" + cell $and $and$ls180.v:6340$2039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6340$2038_Y + connect \Y $and$ls180.v:6340$2039_Y + end + attribute \src "ls180.v:6340.38-6340.148" + cell $and $and$ls180.v:6340$2041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6340$2039_Y + connect \B $eq$ls180.v:6340$2040_Y + connect \Y $and$ls180.v:6340$2041_Y + end + attribute \src "ls180.v:6342.39-6342.94" + cell $and $and$ls180.v:6342$2042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6342$2042_Y + end + attribute \src "ls180.v:6342.38-6342.145" + cell $and $and$ls180.v:6342$2044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6342$2042_Y + connect \B $eq$ls180.v:6342$2043_Y + connect \Y $and$ls180.v:6342$2044_Y + end + attribute \src "ls180.v:6343.39-6343.97" + cell $and $and$ls180.v:6343$2046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6343$2045_Y + connect \Y $and$ls180.v:6343$2046_Y + end + attribute \src "ls180.v:6343.38-6343.148" + cell $and $and$ls180.v:6343$2048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6343$2046_Y + connect \B $eq$ls180.v:6343$2047_Y + connect \Y $and$ls180.v:6343$2048_Y + end + attribute \src "ls180.v:6345.41-6345.96" + cell $and $and$ls180.v:6345$2049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6345$2049_Y + end + attribute \src "ls180.v:6345.40-6345.147" + cell $and $and$ls180.v:6345$2051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6345$2049_Y + connect \B $eq$ls180.v:6345$2050_Y + connect \Y $and$ls180.v:6345$2051_Y + end + attribute \src "ls180.v:6346.41-6346.99" + cell $and $and$ls180.v:6346$2053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6346$2052_Y + connect \Y $and$ls180.v:6346$2053_Y + end + attribute \src "ls180.v:6346.40-6346.150" + cell $and $and$ls180.v:6346$2055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6346$2053_Y + connect \B $eq$ls180.v:6346$2054_Y + connect \Y $and$ls180.v:6346$2055_Y + end + attribute \src "ls180.v:6348.41-6348.96" + cell $and $and$ls180.v:6348$2056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6348$2056_Y + end + attribute \src "ls180.v:6348.40-6348.147" + cell $and $and$ls180.v:6348$2058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6348$2056_Y + connect \B $eq$ls180.v:6348$2057_Y + connect \Y $and$ls180.v:6348$2058_Y + end + attribute \src "ls180.v:6349.41-6349.99" + cell $and $and$ls180.v:6349$2060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6349$2059_Y + connect \Y $and$ls180.v:6349$2060_Y + end + attribute \src "ls180.v:6349.40-6349.150" + cell $and $and$ls180.v:6349$2062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6349$2060_Y + connect \B $eq$ls180.v:6349$2061_Y + connect \Y $and$ls180.v:6349$2062_Y + end + attribute \src "ls180.v:6351.41-6351.96" + cell $and $and$ls180.v:6351$2063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6351$2063_Y + end + attribute \src "ls180.v:6351.40-6351.147" + cell $and $and$ls180.v:6351$2065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6351$2063_Y + connect \B $eq$ls180.v:6351$2064_Y + connect \Y $and$ls180.v:6351$2065_Y + end + attribute \src "ls180.v:6352.41-6352.99" + cell $and $and$ls180.v:6352$2067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6352$2066_Y + connect \Y $and$ls180.v:6352$2067_Y + end + attribute \src "ls180.v:6352.40-6352.150" + cell $and $and$ls180.v:6352$2069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6352$2067_Y + connect \B $eq$ls180.v:6352$2068_Y + connect \Y $and$ls180.v:6352$2069_Y + end + attribute \src "ls180.v:6354.41-6354.96" + cell $and $and$ls180.v:6354$2070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6354$2070_Y + end + attribute \src "ls180.v:6354.40-6354.147" + cell $and $and$ls180.v:6354$2072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6354$2070_Y + connect \B $eq$ls180.v:6354$2071_Y + connect \Y $and$ls180.v:6354$2072_Y + end + attribute \src "ls180.v:6355.41-6355.99" + cell $and $and$ls180.v:6355$2074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6355$2073_Y + connect \Y $and$ls180.v:6355$2074_Y + end + attribute \src "ls180.v:6355.40-6355.150" + cell $and $and$ls180.v:6355$2076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6355$2074_Y + connect \B $eq$ls180.v:6355$2075_Y + connect \Y $and$ls180.v:6355$2076_Y + end + attribute \src "ls180.v:6357.37-6357.92" + cell $and $and$ls180.v:6357$2077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6357$2077_Y + end + attribute \src "ls180.v:6357.36-6357.143" + cell $and $and$ls180.v:6357$2079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6357$2077_Y + connect \B $eq$ls180.v:6357$2078_Y + connect \Y $and$ls180.v:6357$2079_Y + end + attribute \src "ls180.v:6358.37-6358.95" + cell $and $and$ls180.v:6358$2081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6358$2080_Y + connect \Y $and$ls180.v:6358$2081_Y + end + attribute \src "ls180.v:6358.36-6358.146" + cell $and $and$ls180.v:6358$2083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6358$2081_Y + connect \B $eq$ls180.v:6358$2082_Y + connect \Y $and$ls180.v:6358$2083_Y + end + attribute \src "ls180.v:6360.47-6360.102" + cell $and $and$ls180.v:6360$2084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6360$2084_Y + end + attribute \src "ls180.v:6360.46-6360.153" + cell $and $and$ls180.v:6360$2086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6360$2084_Y + connect \B $eq$ls180.v:6360$2085_Y + connect \Y $and$ls180.v:6360$2086_Y + end + attribute \src "ls180.v:6361.47-6361.105" + cell $and $and$ls180.v:6361$2088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6361$2087_Y + connect \Y $and$ls180.v:6361$2088_Y + end + attribute \src "ls180.v:6361.46-6361.156" + cell $and $and$ls180.v:6361$2090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6361$2088_Y + connect \B $eq$ls180.v:6361$2089_Y + connect \Y $and$ls180.v:6361$2090_Y + end + attribute \src "ls180.v:6363.40-6363.95" + cell $and $and$ls180.v:6363$2091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6363$2091_Y + end + attribute \src "ls180.v:6363.39-6363.147" + cell $and $and$ls180.v:6363$2093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6363$2091_Y + connect \B $eq$ls180.v:6363$2092_Y + connect \Y $and$ls180.v:6363$2093_Y + end + attribute \src "ls180.v:6364.40-6364.98" + cell $and $and$ls180.v:6364$2095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6364$2094_Y + connect \Y $and$ls180.v:6364$2095_Y + end + attribute \src "ls180.v:6364.39-6364.150" + cell $and $and$ls180.v:6364$2097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6364$2095_Y + connect \B $eq$ls180.v:6364$2096_Y + connect \Y $and$ls180.v:6364$2097_Y + end + attribute \src "ls180.v:6366.40-6366.95" + cell $and $and$ls180.v:6366$2098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6366$2098_Y + end + attribute \src "ls180.v:6366.39-6366.147" + cell $and $and$ls180.v:6366$2100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6366$2098_Y + connect \B $eq$ls180.v:6366$2099_Y + connect \Y $and$ls180.v:6366$2100_Y + end + attribute \src "ls180.v:6367.40-6367.98" + cell $and $and$ls180.v:6367$2102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6367$2101_Y + connect \Y $and$ls180.v:6367$2102_Y + end + attribute \src "ls180.v:6367.39-6367.150" + cell $and $and$ls180.v:6367$2104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6367$2102_Y + connect \B $eq$ls180.v:6367$2103_Y + connect \Y $and$ls180.v:6367$2104_Y + end + attribute \src "ls180.v:6369.40-6369.95" + cell $and $and$ls180.v:6369$2105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6369$2105_Y + end + attribute \src "ls180.v:6369.39-6369.147" + cell $and $and$ls180.v:6369$2107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6369$2105_Y + connect \B $eq$ls180.v:6369$2106_Y + connect \Y $and$ls180.v:6369$2107_Y + end + attribute \src "ls180.v:6370.40-6370.98" + cell $and $and$ls180.v:6370$2109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6370$2108_Y + connect \Y $and$ls180.v:6370$2109_Y + end + attribute \src "ls180.v:6370.39-6370.150" + cell $and $and$ls180.v:6370$2111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6370$2109_Y + connect \B $eq$ls180.v:6370$2110_Y + connect \Y $and$ls180.v:6370$2111_Y + end + attribute \src "ls180.v:6372.40-6372.95" + cell $and $and$ls180.v:6372$2112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6372$2112_Y + end + attribute \src "ls180.v:6372.39-6372.147" + cell $and $and$ls180.v:6372$2114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6372$2112_Y + connect \B $eq$ls180.v:6372$2113_Y + connect \Y $and$ls180.v:6372$2114_Y + end + attribute \src "ls180.v:6373.40-6373.98" + cell $and $and$ls180.v:6373$2116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6373$2115_Y + connect \Y $and$ls180.v:6373$2116_Y + end + attribute \src "ls180.v:6373.39-6373.150" + cell $and $and$ls180.v:6373$2118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6373$2116_Y + connect \B $eq$ls180.v:6373$2117_Y + connect \Y $and$ls180.v:6373$2118_Y + end + attribute \src "ls180.v:6375.52-6375.107" + cell $and $and$ls180.v:6375$2119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6375$2119_Y + end + attribute \src "ls180.v:6375.51-6375.159" + cell $and $and$ls180.v:6375$2121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6375$2119_Y + connect \B $eq$ls180.v:6375$2120_Y + connect \Y $and$ls180.v:6375$2121_Y + end + attribute \src "ls180.v:6376.52-6376.110" + cell $and $and$ls180.v:6376$2123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6376$2122_Y + connect \Y $and$ls180.v:6376$2123_Y + end + attribute \src "ls180.v:6376.51-6376.162" + cell $and $and$ls180.v:6376$2125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6376$2123_Y + connect \B $eq$ls180.v:6376$2124_Y + connect \Y $and$ls180.v:6376$2125_Y + end + attribute \src "ls180.v:6378.53-6378.108" + cell $and $and$ls180.v:6378$2126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6378$2126_Y + end + attribute \src "ls180.v:6378.52-6378.160" + cell $and $and$ls180.v:6378$2128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6378$2126_Y + connect \B $eq$ls180.v:6378$2127_Y + connect \Y $and$ls180.v:6378$2128_Y + end + attribute \src "ls180.v:6379.53-6379.111" + cell $and $and$ls180.v:6379$2130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6379$2129_Y + connect \Y $and$ls180.v:6379$2130_Y + end + attribute \src "ls180.v:6379.52-6379.163" + cell $and $and$ls180.v:6379$2132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6379$2130_Y + connect \B $eq$ls180.v:6379$2131_Y + connect \Y $and$ls180.v:6379$2132_Y + end + attribute \src "ls180.v:6381.44-6381.99" + cell $and $and$ls180.v:6381$2133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6381$2133_Y + end + attribute \src "ls180.v:6381.43-6381.151" + cell $and $and$ls180.v:6381$2135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6381$2133_Y + connect \B $eq$ls180.v:6381$2134_Y + connect \Y $and$ls180.v:6381$2135_Y + end + attribute \src "ls180.v:6382.44-6382.102" + cell $and $and$ls180.v:6382$2137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6382$2136_Y + connect \Y $and$ls180.v:6382$2137_Y + end + attribute \src "ls180.v:6382.43-6382.154" + cell $and $and$ls180.v:6382$2139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6382$2137_Y + connect \B $eq$ls180.v:6382$2138_Y + connect \Y $and$ls180.v:6382$2139_Y + end + attribute \src "ls180.v:6401.30-6401.85" + cell $and $and$ls180.v:6401$2141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6401$2141_Y + end + attribute \src "ls180.v:6401.29-6401.136" + cell $and $and$ls180.v:6401$2143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6401$2141_Y + connect \B $eq$ls180.v:6401$2142_Y + connect \Y $and$ls180.v:6401$2143_Y + end + attribute \src "ls180.v:6402.30-6402.88" + cell $and $and$ls180.v:6402$2145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6402$2144_Y + connect \Y $and$ls180.v:6402$2145_Y + end + attribute \src "ls180.v:6402.29-6402.139" + cell $and $and$ls180.v:6402$2147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6402$2145_Y + connect \B $eq$ls180.v:6402$2146_Y + connect \Y $and$ls180.v:6402$2147_Y + end + attribute \src "ls180.v:6404.40-6404.95" + cell $and $and$ls180.v:6404$2148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6404$2148_Y + end + attribute \src "ls180.v:6404.39-6404.146" + cell $and $and$ls180.v:6404$2150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6404$2148_Y + connect \B $eq$ls180.v:6404$2149_Y + connect \Y $and$ls180.v:6404$2150_Y + end + attribute \src "ls180.v:6405.40-6405.98" + cell $and $and$ls180.v:6405$2152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6405$2151_Y + connect \Y $and$ls180.v:6405$2152_Y + end + attribute \src "ls180.v:6405.39-6405.149" + cell $and $and$ls180.v:6405$2154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6405$2152_Y + connect \B $eq$ls180.v:6405$2153_Y + connect \Y $and$ls180.v:6405$2154_Y + end + attribute \src "ls180.v:6407.41-6407.96" + cell $and $and$ls180.v:6407$2155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6407$2155_Y + end + attribute \src "ls180.v:6407.40-6407.147" + cell $and $and$ls180.v:6407$2157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6407$2155_Y + connect \B $eq$ls180.v:6407$2156_Y + connect \Y $and$ls180.v:6407$2157_Y + end + attribute \src "ls180.v:6408.41-6408.99" + cell $and $and$ls180.v:6408$2159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6408$2158_Y + connect \Y $and$ls180.v:6408$2159_Y + end + attribute \src "ls180.v:6408.40-6408.150" + cell $and $and$ls180.v:6408$2161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6408$2159_Y + connect \B $eq$ls180.v:6408$2160_Y + connect \Y $and$ls180.v:6408$2161_Y + end + attribute \src "ls180.v:6410.45-6410.100" + cell $and $and$ls180.v:6410$2162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6410$2162_Y + end + attribute \src "ls180.v:6410.44-6410.151" + cell $and $and$ls180.v:6410$2164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6410$2162_Y + connect \B $eq$ls180.v:6410$2163_Y + connect \Y $and$ls180.v:6410$2164_Y + end + attribute \src "ls180.v:6411.45-6411.103" + cell $and $and$ls180.v:6411$2166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6411$2165_Y + connect \Y $and$ls180.v:6411$2166_Y + end + attribute \src "ls180.v:6411.44-6411.154" + cell $and $and$ls180.v:6411$2168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6411$2166_Y + connect \B $eq$ls180.v:6411$2167_Y + connect \Y $and$ls180.v:6411$2168_Y + end + attribute \src "ls180.v:6413.46-6413.101" + cell $and $and$ls180.v:6413$2169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6413$2169_Y + end + attribute \src "ls180.v:6413.45-6413.152" + cell $and $and$ls180.v:6413$2171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6413$2169_Y + connect \B $eq$ls180.v:6413$2170_Y + connect \Y $and$ls180.v:6413$2171_Y + end + attribute \src "ls180.v:6414.46-6414.104" + cell $and $and$ls180.v:6414$2173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6414$2172_Y + connect \Y $and$ls180.v:6414$2173_Y + end + attribute \src "ls180.v:6414.45-6414.155" + cell $and $and$ls180.v:6414$2175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6414$2173_Y + connect \B $eq$ls180.v:6414$2174_Y + connect \Y $and$ls180.v:6414$2175_Y + end + attribute \src "ls180.v:6416.44-6416.99" + cell $and $and$ls180.v:6416$2176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6416$2176_Y + end + attribute \src "ls180.v:6416.43-6416.150" + cell $and $and$ls180.v:6416$2178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6416$2176_Y + connect \B $eq$ls180.v:6416$2177_Y + connect \Y $and$ls180.v:6416$2178_Y + end + attribute \src "ls180.v:6417.44-6417.102" + cell $and $and$ls180.v:6417$2180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6417$2179_Y + connect \Y $and$ls180.v:6417$2180_Y + end + attribute \src "ls180.v:6417.43-6417.153" + cell $and $and$ls180.v:6417$2182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6417$2180_Y + connect \B $eq$ls180.v:6417$2181_Y + connect \Y $and$ls180.v:6417$2182_Y + end + attribute \src "ls180.v:6419.41-6419.96" + cell $and $and$ls180.v:6419$2183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6419$2183_Y + end + attribute \src "ls180.v:6419.40-6419.147" + cell $and $and$ls180.v:6419$2185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6419$2183_Y + connect \B $eq$ls180.v:6419$2184_Y + connect \Y $and$ls180.v:6419$2185_Y + end + attribute \src "ls180.v:6420.41-6420.99" + cell $and $and$ls180.v:6420$2187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6420$2186_Y + connect \Y $and$ls180.v:6420$2187_Y + end + attribute \src "ls180.v:6420.40-6420.150" + cell $and $and$ls180.v:6420$2189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6420$2187_Y + connect \B $eq$ls180.v:6420$2188_Y + connect \Y $and$ls180.v:6420$2189_Y + end + attribute \src "ls180.v:6422.40-6422.95" + cell $and $and$ls180.v:6422$2190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6422$2190_Y + end + attribute \src "ls180.v:6422.39-6422.146" + cell $and $and$ls180.v:6422$2192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6422$2190_Y + connect \B $eq$ls180.v:6422$2191_Y + connect \Y $and$ls180.v:6422$2192_Y + end + attribute \src "ls180.v:6423.40-6423.98" + cell $and $and$ls180.v:6423$2194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6423$2193_Y + connect \Y $and$ls180.v:6423$2194_Y + end + attribute \src "ls180.v:6423.39-6423.149" + cell $and $and$ls180.v:6423$2196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6423$2194_Y + connect \B $eq$ls180.v:6423$2195_Y + connect \Y $and$ls180.v:6423$2196_Y + end + attribute \src "ls180.v:6435.46-6435.101" + cell $and $and$ls180.v:6435$2198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6435$2198_Y + end + attribute \src "ls180.v:6435.45-6435.152" + cell $and $and$ls180.v:6435$2200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6435$2198_Y + connect \B $eq$ls180.v:6435$2199_Y + connect \Y $and$ls180.v:6435$2200_Y + end + attribute \src "ls180.v:6436.46-6436.104" + cell $and $and$ls180.v:6436$2202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6436$2201_Y + connect \Y $and$ls180.v:6436$2202_Y + end + attribute \src "ls180.v:6436.45-6436.155" + cell $and $and$ls180.v:6436$2204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6436$2202_Y + connect \B $eq$ls180.v:6436$2203_Y + connect \Y $and$ls180.v:6436$2204_Y + end + attribute \src "ls180.v:6438.46-6438.101" + cell $and $and$ls180.v:6438$2205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6438$2205_Y + end + attribute \src "ls180.v:6438.45-6438.152" + cell $and $and$ls180.v:6438$2207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6438$2205_Y + connect \B $eq$ls180.v:6438$2206_Y + connect \Y $and$ls180.v:6438$2207_Y + end + attribute \src "ls180.v:6439.46-6439.104" + cell $and $and$ls180.v:6439$2209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6439$2208_Y + connect \Y $and$ls180.v:6439$2209_Y + end + attribute \src "ls180.v:6439.45-6439.155" + cell $and $and$ls180.v:6439$2211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6439$2209_Y + connect \B $eq$ls180.v:6439$2210_Y + connect \Y $and$ls180.v:6439$2211_Y + end + attribute \src "ls180.v:6441.46-6441.101" + cell $and $and$ls180.v:6441$2212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6441$2212_Y + end + attribute \src "ls180.v:6441.45-6441.152" + cell $and $and$ls180.v:6441$2214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6441$2212_Y + connect \B $eq$ls180.v:6441$2213_Y + connect \Y $and$ls180.v:6441$2214_Y + end + attribute \src "ls180.v:6442.46-6442.104" + cell $and $and$ls180.v:6442$2216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6442$2215_Y + connect \Y $and$ls180.v:6442$2216_Y + end + attribute \src "ls180.v:6442.45-6442.155" + cell $and $and$ls180.v:6442$2218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6442$2216_Y + connect \B $eq$ls180.v:6442$2217_Y + connect \Y $and$ls180.v:6442$2218_Y + end + attribute \src "ls180.v:6444.46-6444.101" + cell $and $and$ls180.v:6444$2219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6444$2219_Y + end + attribute \src "ls180.v:6444.45-6444.152" + cell $and $and$ls180.v:6444$2221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6444$2219_Y + connect \B $eq$ls180.v:6444$2220_Y + connect \Y $and$ls180.v:6444$2221_Y + end + attribute \src "ls180.v:6445.46-6445.104" + cell $and $and$ls180.v:6445$2223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6445$2222_Y + connect \Y $and$ls180.v:6445$2223_Y + end + attribute \src "ls180.v:6445.45-6445.155" + cell $and $and$ls180.v:6445$2225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6445$2223_Y + connect \B $eq$ls180.v:6445$2224_Y + connect \Y $and$ls180.v:6445$2225_Y + end + attribute \src "ls180.v:6826.109-6826.178" + cell $and $and$ls180.v:6826$2263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:6826$2262_Y + connect \Y $and$ls180.v:6826$2263_Y + end + attribute \src "ls180.v:6826.184-6826.253" + cell $and $and$ls180.v:6826$2266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:6826$2265_Y + connect \Y $and$ls180.v:6826$2266_Y + end + attribute \src "ls180.v:6826.259-6826.328" + cell $and $and$ls180.v:6826$2269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:6826$2268_Y + connect \Y $and$ls180.v:6826$2269_Y + end + attribute \src "ls180.v:6826.40-6826.331" + cell $and $and$ls180.v:6826$2272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:6826$2261_Y + connect \B $not$ls180.v:6826$2271_Y + connect \Y $and$ls180.v:6826$2272_Y + end + attribute \src "ls180.v:6826.39-6826.354" + cell $and $and$ls180.v:6826$2273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6826$2272_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:6826$2273_Y + end + attribute \src "ls180.v:6850.109-6850.178" + cell $and $and$ls180.v:6850$2279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:6850$2278_Y + connect \Y $and$ls180.v:6850$2279_Y + end + attribute \src "ls180.v:6850.184-6850.253" + cell $and $and$ls180.v:6850$2282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:6850$2281_Y + connect \Y $and$ls180.v:6850$2282_Y + end + attribute \src "ls180.v:6850.259-6850.328" + cell $and $and$ls180.v:6850$2285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:6850$2284_Y + connect \Y $and$ls180.v:6850$2285_Y + end + attribute \src "ls180.v:6850.40-6850.331" + cell $and $and$ls180.v:6850$2288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:6850$2277_Y + connect \B $not$ls180.v:6850$2287_Y + connect \Y $and$ls180.v:6850$2288_Y + end + attribute \src "ls180.v:6850.39-6850.354" + cell $and $and$ls180.v:6850$2289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6850$2288_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:6850$2289_Y + end + attribute \src "ls180.v:6874.109-6874.178" + cell $and $and$ls180.v:6874$2295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:6874$2294_Y + connect \Y $and$ls180.v:6874$2295_Y + end + attribute \src "ls180.v:6874.184-6874.253" + cell $and $and$ls180.v:6874$2298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:6874$2297_Y + connect \Y $and$ls180.v:6874$2298_Y + end + attribute \src "ls180.v:6874.259-6874.328" + cell $and $and$ls180.v:6874$2301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:6874$2300_Y + connect \Y $and$ls180.v:6874$2301_Y + end + attribute \src "ls180.v:6874.40-6874.331" + cell $and $and$ls180.v:6874$2304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:6874$2293_Y + connect \B $not$ls180.v:6874$2303_Y + connect \Y $and$ls180.v:6874$2304_Y + end + attribute \src "ls180.v:6874.39-6874.354" + cell $and $and$ls180.v:6874$2305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6874$2304_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:6874$2305_Y + end + attribute \src "ls180.v:6898.109-6898.178" + cell $and $and$ls180.v:6898$2311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:6898$2310_Y + connect \Y $and$ls180.v:6898$2311_Y + end + attribute \src "ls180.v:6898.184-6898.253" + cell $and $and$ls180.v:6898$2314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:6898$2313_Y + connect \Y $and$ls180.v:6898$2314_Y + end + attribute \src "ls180.v:6898.259-6898.328" + cell $and $and$ls180.v:6898$2317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:6898$2316_Y + connect \Y $and$ls180.v:6898$2317_Y + end + attribute \src "ls180.v:6898.40-6898.331" + cell $and $and$ls180.v:6898$2320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:6898$2309_Y + connect \B $not$ls180.v:6898$2319_Y + connect \Y $and$ls180.v:6898$2320_Y + end + attribute \src "ls180.v:6898.39-6898.354" + cell $and $and$ls180.v:6898$2321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6898$2320_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:6898$2321_Y + end + attribute \src "ls180.v:7103.39-7103.104" + cell $and $and$ls180.v:7103$2333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7103$2333_Y + end + attribute \src "ls180.v:7103.38-7103.145" + cell $and $and$ls180.v:7103$2334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7103$2333_Y + connect \B \main_sdram_choose_req_cmd_payload_cas + connect \Y $and$ls180.v:7103$2334_Y + end + attribute \src "ls180.v:7106.39-7106.104" + cell $and $and$ls180.v:7106$2335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7106$2335_Y + end + attribute \src "ls180.v:7106.38-7106.145" + cell $and $and$ls180.v:7106$2336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7106$2335_Y + connect \B \main_sdram_choose_req_cmd_payload_cas + connect \Y $and$ls180.v:7106$2336_Y + end + attribute \src "ls180.v:7109.39-7109.82" + cell $and $and$ls180.v:7109$2337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7109$2337_Y + end + attribute \src "ls180.v:7109.38-7109.112" + cell $and $and$ls180.v:7109$2338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7109$2337_Y + connect \B \main_sdram_cmd_payload_cas + connect \Y $and$ls180.v:7109$2338_Y + end + attribute \src "ls180.v:7120.39-7120.104" + cell $and $and$ls180.v:7120$2340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7120$2340_Y + end + attribute \src "ls180.v:7120.38-7120.145" + cell $and $and$ls180.v:7120$2341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7120$2340_Y + connect \B \main_sdram_choose_req_cmd_payload_ras + connect \Y $and$ls180.v:7120$2341_Y + end + attribute \src "ls180.v:7123.39-7123.104" + cell $and $and$ls180.v:7123$2342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7123$2342_Y + end + attribute \src "ls180.v:7123.38-7123.145" + cell $and $and$ls180.v:7123$2343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7123$2342_Y + connect \B \main_sdram_choose_req_cmd_payload_ras + connect \Y $and$ls180.v:7123$2343_Y + end + attribute \src "ls180.v:7126.39-7126.82" + cell $and $and$ls180.v:7126$2344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7126$2344_Y + end + attribute \src "ls180.v:7126.38-7126.112" + cell $and $and$ls180.v:7126$2345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7126$2344_Y + connect \B \main_sdram_cmd_payload_ras + connect \Y $and$ls180.v:7126$2345_Y + end + attribute \src "ls180.v:7137.39-7137.104" + cell $and $and$ls180.v:7137$2347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7137$2347_Y + end + attribute \src "ls180.v:7137.38-7137.144" + cell $and $and$ls180.v:7137$2348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7137$2347_Y + connect \B \main_sdram_choose_req_cmd_payload_we + connect \Y $and$ls180.v:7137$2348_Y + end + attribute \src "ls180.v:7140.39-7140.104" + cell $and $and$ls180.v:7140$2349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7140$2349_Y + end + attribute \src "ls180.v:7140.38-7140.144" + cell $and $and$ls180.v:7140$2350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7140$2349_Y + connect \B \main_sdram_choose_req_cmd_payload_we + connect \Y $and$ls180.v:7140$2350_Y + end + attribute \src "ls180.v:7143.39-7143.82" + cell $and $and$ls180.v:7143$2351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7143$2351_Y + end + attribute \src "ls180.v:7143.38-7143.111" + cell $and $and$ls180.v:7143$2352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7143$2351_Y + connect \B \main_sdram_cmd_payload_we + connect \Y $and$ls180.v:7143$2352_Y + end + attribute \src "ls180.v:7154.39-7154.104" + cell $and $and$ls180.v:7154$2354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7154$2354_Y + end + attribute \src "ls180.v:7154.38-7154.149" + cell $and $and$ls180.v:7154$2355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7154$2354_Y + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $and$ls180.v:7154$2355_Y + end + attribute \src "ls180.v:7157.39-7157.104" + cell $and $and$ls180.v:7157$2356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7157$2356_Y + end + attribute \src "ls180.v:7157.38-7157.149" + cell $and $and$ls180.v:7157$2357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7157$2356_Y + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $and$ls180.v:7157$2357_Y + end + attribute \src "ls180.v:7160.39-7160.82" + cell $and $and$ls180.v:7160$2358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7160$2358_Y + end + attribute \src "ls180.v:7160.38-7160.116" + cell $and $and$ls180.v:7160$2359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7160$2358_Y + connect \B \main_sdram_cmd_payload_is_read + connect \Y $and$ls180.v:7160$2359_Y + end + attribute \src "ls180.v:7171.39-7171.104" + cell $and $and$ls180.v:7171$2361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7171$2361_Y + end + attribute \src "ls180.v:7171.38-7171.150" + cell $and $and$ls180.v:7171$2362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7171$2361_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:7171$2362_Y + end + attribute \src "ls180.v:7174.39-7174.104" + cell $and $and$ls180.v:7174$2363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7174$2363_Y + end + attribute \src "ls180.v:7174.38-7174.150" + cell $and $and$ls180.v:7174$2364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7174$2363_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:7174$2364_Y + end + attribute \src "ls180.v:7177.39-7177.82" + cell $and $and$ls180.v:7177$2365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7177$2365_Y + end + attribute \src "ls180.v:7177.38-7177.117" + cell $and $and$ls180.v:7177$2366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7177$2365_Y + connect \B \main_sdram_cmd_payload_is_write + connect \Y $and$ls180.v:7177$2366_Y + end + attribute \src "ls180.v:7396.17-7396.67" + cell $and $and$ls180.v:7396$2373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7396$2372_Y + connect \B \main_sdphy_sdpads_clk + connect \Y $and$ls180.v:7396$2373_Y + end + attribute \src "ls180.v:7487.8-7487.67" + cell $and $and$ls180.v:7487$2416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:7487$2416_Y + end + attribute \src "ls180.v:7487.7-7487.102" + cell $and $and$ls180.v:7487$2418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7487$2416_Y + connect \B $not$ls180.v:7487$2417_Y + connect \Y $and$ls180.v:7487$2418_Y + end + attribute \src "ls180.v:7506.7-7506.75" + cell $and $and$ls180.v:7506$2422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7506$2421_Y + connect \B \main_libresocsim_zero_old_trigger + connect \Y $and$ls180.v:7506$2422_Y + end + attribute \src "ls180.v:7514.7-7514.56" + cell $and $and$ls180.v:7514$2424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_wait + connect \B $not$ls180.v:7514$2423_Y + connect \Y $and$ls180.v:7514$2424_Y + end + attribute \src "ls180.v:7542.7-7542.75" + cell $and $and$ls180.v:7542$2431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_start1 + connect \B $eq$ls180.v:7542$2430_Y + connect \Y $and$ls180.v:7542$2431_Y + end + attribute \src "ls180.v:7584.8-7584.131" + cell $and $and$ls180.v:7584$2437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$ls180.v:7584$2437_Y + end + attribute \src "ls180.v:7584.7-7584.190" + cell $and $and$ls180.v:7584$2439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7584$2437_Y + connect \B $not$ls180.v:7584$2438_Y + connect \Y $and$ls180.v:7584$2439_Y + end + attribute \src "ls180.v:7590.8-7590.131" + cell $and $and$ls180.v:7590$2442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$ls180.v:7590$2442_Y + end + attribute \src "ls180.v:7590.7-7590.190" + cell $and $and$ls180.v:7590$2444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7590$2442_Y + connect \B $not$ls180.v:7590$2443_Y + connect \Y $and$ls180.v:7590$2444_Y + end + attribute \src "ls180.v:7630.8-7630.131" + cell $and $and$ls180.v:7630$2453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$ls180.v:7630$2453_Y + end + attribute \src "ls180.v:7630.7-7630.190" + cell $and $and$ls180.v:7630$2455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7630$2453_Y + connect \B $not$ls180.v:7630$2454_Y + connect \Y $and$ls180.v:7630$2455_Y + end + attribute \src "ls180.v:7636.8-7636.131" + cell $and $and$ls180.v:7636$2458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$ls180.v:7636$2458_Y + end + attribute \src "ls180.v:7636.7-7636.190" + cell $and $and$ls180.v:7636$2460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7636$2458_Y + connect \B $not$ls180.v:7636$2459_Y + connect \Y $and$ls180.v:7636$2460_Y + end + attribute \src "ls180.v:7676.8-7676.131" + cell $and $and$ls180.v:7676$2469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$ls180.v:7676$2469_Y + end + attribute \src "ls180.v:7676.7-7676.190" + cell $and $and$ls180.v:7676$2471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7676$2469_Y + connect \B $not$ls180.v:7676$2470_Y + connect \Y $and$ls180.v:7676$2471_Y + end + attribute \src "ls180.v:7682.8-7682.131" + cell $and $and$ls180.v:7682$2474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$ls180.v:7682$2474_Y + end + attribute \src "ls180.v:7682.7-7682.190" + cell $and $and$ls180.v:7682$2476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7682$2474_Y + connect \B $not$ls180.v:7682$2475_Y + connect \Y $and$ls180.v:7682$2476_Y + end + attribute \src "ls180.v:7722.8-7722.131" + cell $and $and$ls180.v:7722$2485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$ls180.v:7722$2485_Y + end + attribute \src "ls180.v:7722.7-7722.190" + cell $and $and$ls180.v:7722$2487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7722$2485_Y + connect \B $not$ls180.v:7722$2486_Y + connect \Y $and$ls180.v:7722$2487_Y + end + attribute \src "ls180.v:7728.8-7728.131" + cell $and $and$ls180.v:7728$2490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$ls180.v:7728$2490_Y + end + attribute \src "ls180.v:7728.7-7728.190" + cell $and $and$ls180.v:7728$2492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7728$2490_Y + connect \B $not$ls180.v:7728$2491_Y + connect \Y $and$ls180.v:7728$2492_Y + end + attribute \src "ls180.v:7925.48-7925.124" + cell $and $and$ls180.v:7925$2517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7925$2516_Y + connect \B \main_sdram_interface_bank0_wdata_ready + connect \Y $and$ls180.v:7925$2517_Y + end + attribute \src "ls180.v:7925.130-7925.206" + cell $and $and$ls180.v:7925$2520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7925$2519_Y + connect \B \main_sdram_interface_bank1_wdata_ready + connect \Y $and$ls180.v:7925$2520_Y + end + attribute \src "ls180.v:7925.212-7925.288" + cell $and $and$ls180.v:7925$2523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7925$2522_Y + connect \B \main_sdram_interface_bank2_wdata_ready + connect \Y $and$ls180.v:7925$2523_Y + end + attribute \src "ls180.v:7925.294-7925.370" + cell $and $and$ls180.v:7925$2526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7925$2525_Y + connect \B \main_sdram_interface_bank3_wdata_ready + connect \Y $and$ls180.v:7925$2526_Y + end + attribute \src "ls180.v:7926.49-7926.125" + cell $and $and$ls180.v:7926$2529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7926$2528_Y + connect \B \main_sdram_interface_bank0_rdata_valid + connect \Y $and$ls180.v:7926$2529_Y + end + attribute \src "ls180.v:7926.131-7926.207" + cell $and $and$ls180.v:7926$2532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7926$2531_Y + connect \B \main_sdram_interface_bank1_rdata_valid + connect \Y $and$ls180.v:7926$2532_Y + end + attribute \src "ls180.v:7926.213-7926.289" + cell $and $and$ls180.v:7926$2535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7926$2534_Y + connect \B \main_sdram_interface_bank2_rdata_valid + connect \Y $and$ls180.v:7926$2535_Y + end + attribute \src "ls180.v:7926.295-7926.371" + cell $and $and$ls180.v:7926$2538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7926$2537_Y + connect \B \main_sdram_interface_bank3_rdata_valid + connect \Y $and$ls180.v:7926$2538_Y + end + attribute \src "ls180.v:7945.8-7945.49" + cell $and $and$ls180.v:7945$2541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_port_cmd_ready + connect \Y $and$ls180.v:7945$2541_Y + end + attribute \src "ls180.v:7948.8-7948.53" + cell $and $and$ls180.v:7948$2542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_wdata_valid + connect \B \main_port_wdata_ready + connect \Y $and$ls180.v:7948$2542_Y + end + attribute \src "ls180.v:7953.8-7953.59" + cell $and $and$ls180.v:7953$2544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_sink_valid + connect \B $not$ls180.v:7953$2543_Y + connect \Y $and$ls180.v:7953$2544_Y + end + attribute \src "ls180.v:7953.7-7953.90" + cell $and $and$ls180.v:7953$2546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7953$2544_Y + connect \B $not$ls180.v:7953$2545_Y + connect \Y $and$ls180.v:7953$2546_Y + end + attribute \src "ls180.v:7959.8-7959.59" + cell $and $and$ls180.v:7959$2547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_uart_clk_txen + connect \B \main_uart_phy_tx_busy + connect \Y $and$ls180.v:7959$2547_Y + end + attribute \src "ls180.v:7983.8-7983.48" + cell $and $and$ls180.v:7983$2554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7983$2553_Y + connect \B \main_uart_phy_rx_r + connect \Y $and$ls180.v:7983$2554_Y + end + attribute \src "ls180.v:8016.7-8016.57" + cell $and $and$ls180.v:8016$2560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8016$2559_Y + connect \B \main_uart_tx_old_trigger + connect \Y $and$ls180.v:8016$2560_Y + end + attribute \src "ls180.v:8023.7-8023.57" + cell $and $and$ls180.v:8023$2562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8023$2561_Y + connect \B \main_uart_rx_old_trigger + connect \Y $and$ls180.v:8023$2562_Y + end + attribute \src "ls180.v:8033.8-8033.75" + cell $and $and$ls180.v:8033$2563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B \main_uart_tx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8033$2563_Y + end + attribute \src "ls180.v:8033.7-8033.107" + cell $and $and$ls180.v:8033$2565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8033$2563_Y + connect \B $not$ls180.v:8033$2564_Y + connect \Y $and$ls180.v:8033$2565_Y + end + attribute \src "ls180.v:8039.8-8039.75" + cell $and $and$ls180.v:8039$2568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B \main_uart_tx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8039$2568_Y + end + attribute \src "ls180.v:8039.7-8039.107" + cell $and $and$ls180.v:8039$2570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8039$2568_Y + connect \B $not$ls180.v:8039$2569_Y + connect \Y $and$ls180.v:8039$2570_Y + end + attribute \src "ls180.v:8055.8-8055.75" + cell $and $and$ls180.v:8055$2574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B \main_uart_rx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8055$2574_Y + end + attribute \src "ls180.v:8055.7-8055.107" + cell $and $and$ls180.v:8055$2576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8055$2574_Y + connect \B $not$ls180.v:8055$2575_Y + connect \Y $and$ls180.v:8055$2576_Y + end + attribute \src "ls180.v:8061.8-8061.75" + cell $and $and$ls180.v:8061$2579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B \main_uart_rx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8061$2579_Y + end + attribute \src "ls180.v:8061.7-8061.107" + cell $and $and$ls180.v:8061$2581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8061$2579_Y + connect \B $not$ls180.v:8061$2580_Y + connect \Y $and$ls180.v:8061$2581_Y + end + attribute \src "ls180.v:8174.7-8174.96" + cell $and $and$ls180.v:8174$2604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_source_valid + connect \B \main_sdphy_cmdr_cmdr_converter_source_ready + connect \Y $and$ls180.v:8174$2604_Y + end + attribute \src "ls180.v:8175.8-8175.93" + cell $and $and$ls180.v:8175$2605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:8175$2605_Y + end + attribute \src "ls180.v:8183.8-8183.93" + cell $and $and$ls180.v:8183$2606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:8183$2606_Y + end + attribute \src "ls180.v:8255.7-8255.98" + cell $and $and$ls180.v:8255$2616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_source_valid + connect \B \main_sdphy_dataw_crcr_converter_source_ready + connect \Y $and$ls180.v:8255$2616_Y + end + attribute \src "ls180.v:8256.8-8256.95" + cell $and $and$ls180.v:8256$2617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:8256$2617_Y + end + attribute \src "ls180.v:8264.8-8264.95" + cell $and $and$ls180.v:8264$2618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:8264$2618_Y + end + attribute \src "ls180.v:8334.7-8334.100" + cell $and $and$ls180.v:8334$2628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_source_valid + connect \B \main_sdphy_datar_datar_converter_source_ready + connect \Y $and$ls180.v:8334$2628_Y + end + attribute \src "ls180.v:8335.8-8335.97" + cell $and $and$ls180.v:8335$2629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:8335$2629_Y + end + attribute \src "ls180.v:8343.8-8343.97" + cell $and $and$ls180.v:8343$2630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:8343$2630_Y + end + attribute \src "ls180.v:8434.7-8434.82" + cell $and $and$ls180.v:8434$2636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8434$2636_Y + end + attribute \src "ls180.v:8437.7-8437.82" + cell $and $and$ls180.v:8437$2637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8437$2637_Y + end + attribute \src "ls180.v:8440.7-8440.82" + cell $and $and$ls180.v:8440$2638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8440$2638_Y + end + attribute \src "ls180.v:8443.7-8443.82" + cell $and $and$ls180.v:8443$2639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8443$2639_Y + end + attribute \src "ls180.v:8446.7-8446.82" + cell $and $and$ls180.v:8446$2640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8446$2640_Y + end + attribute \src "ls180.v:8451.7-8451.82" + cell $and $and$ls180.v:8451$2641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8451$2641_Y + end + attribute \src "ls180.v:8456.7-8456.82" + cell $and $and$ls180.v:8456$2642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8456$2642_Y + end + attribute \src "ls180.v:8461.7-8461.82" + cell $and $and$ls180.v:8461$2643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8461$2643_Y + end + attribute \src "ls180.v:8466.7-8466.82" + cell $and $and$ls180.v:8466$2644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8466$2644_Y + end + attribute \src "ls180.v:8531.8-8531.83" + cell $and $and$ls180.v:8531$2647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B \main_sdblock2mem_fifo_syncfifo_writable + connect \Y $and$ls180.v:8531$2647_Y + end + attribute \src "ls180.v:8531.7-8531.119" + cell $and $and$ls180.v:8531$2649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8531$2647_Y + connect \B $not$ls180.v:8531$2648_Y + connect \Y $and$ls180.v:8531$2649_Y + end + attribute \src "ls180.v:8537.8-8537.83" + cell $and $and$ls180.v:8537$2652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B \main_sdblock2mem_fifo_syncfifo_writable + connect \Y $and$ls180.v:8537$2652_Y + end + attribute \src "ls180.v:8537.7-8537.119" + cell $and $and$ls180.v:8537$2654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8537$2652_Y + connect \B $not$ls180.v:8537$2653_Y + connect \Y $and$ls180.v:8537$2654_Y + end + attribute \src "ls180.v:8557.7-8557.88" + cell $and $and$ls180.v:8557$2661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_source_valid + connect \B \main_sdblock2mem_converter_source_ready + connect \Y $and$ls180.v:8557$2661_Y + end + attribute \src "ls180.v:8558.8-8558.85" + cell $and $and$ls180.v:8558$2662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:8558$2662_Y + end + attribute \src "ls180.v:8566.8-8566.85" + cell $and $and$ls180.v:8566$2663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:8566$2663_Y + end + attribute \src "ls180.v:8610.7-8610.88" + cell $and $and$ls180.v:8610$2667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_source_valid + connect \B \main_sdmem2block_converter_source_ready + connect \Y $and$ls180.v:8610$2667_Y + end + attribute \src "ls180.v:8617.8-8617.83" + cell $and $and$ls180.v:8617$2669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B \main_sdmem2block_fifo_syncfifo_writable + connect \Y $and$ls180.v:8617$2669_Y + end + attribute \src "ls180.v:8617.7-8617.119" + cell $and $and$ls180.v:8617$2671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8617$2669_Y + connect \B $not$ls180.v:8617$2670_Y + connect \Y $and$ls180.v:8617$2671_Y + end + attribute \src "ls180.v:8623.8-8623.83" + cell $and $and$ls180.v:8623$2674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B \main_sdmem2block_fifo_syncfifo_writable + connect \Y $and$ls180.v:8623$2674_Y + end + attribute \src "ls180.v:8623.7-8623.119" + cell $and $and$ls180.v:8623$2676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8623$2674_Y + connect \B $not$ls180.v:8623$2675_Y + connect \Y $and$ls180.v:8623$2676_Y + end + attribute \src "ls180.v:2794.42-2794.101" + cell $eq $eq$ls180.v:2794$18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface0_converted_interface_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2794$18_Y + end + attribute \src "ls180.v:2801.11-2801.54" + cell $eq $eq$ls180.v:2801$23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2801$23_Y + end + attribute \src "ls180.v:2854.42-2854.101" + cell $eq $eq$ls180.v:2854$29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface1_converted_interface_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2854$29_Y + end + attribute \src "ls180.v:2861.11-2861.54" + cell $eq $eq$ls180.v:2861$34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2861$34_Y + end + attribute \src "ls180.v:2914.42-2914.101" + cell $eq $eq$ls180.v:2914$40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface2_converted_interface_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2914$40_Y + end + attribute \src "ls180.v:2921.11-2921.54" + cell $eq $eq$ls180.v:2921$45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter2_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2921$45_Y + end + attribute \src "ls180.v:3107.34-3107.65" + cell $eq $eq$ls180.v:3107$73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_count1 + connect \B 1'0 + connect \Y $eq$ls180.v:3107$73_Y + end + attribute \src "ls180.v:3111.68-3111.102" + cell $eq $eq$ls180.v:3111$76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $eq$ls180.v:3111$76_Y + end + attribute \src "ls180.v:3155.43-3155.134" + cell $eq $eq$ls180.v:3155$81 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_row + connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3155$81_Y + end + attribute \src "ls180.v:3172.47-3172.88" + cell $eq $eq$ls180.v:3172$94 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3172$94_Y + end + attribute \src "ls180.v:3312.43-3312.134" + cell $eq $eq$ls180.v:3312$111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_row + connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3312$111_Y + end + attribute \src "ls180.v:3329.47-3329.88" + cell $eq $eq$ls180.v:3329$124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3329$124_Y + end + attribute \src "ls180.v:3469.43-3469.134" + cell $eq $eq$ls180.v:3469$141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_row + connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3469$141_Y + end + attribute \src "ls180.v:3486.47-3486.88" + cell $eq $eq$ls180.v:3486$154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3486$154_Y + end + attribute \src "ls180.v:3626.43-3626.134" + cell $eq $eq$ls180.v:3626$171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_row + connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3626$171_Y + end + attribute \src "ls180.v:3643.47-3643.88" + cell $eq $eq$ls180.v:3643$184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3643$184_Y + end + attribute \src "ls180.v:3780.32-3780.56" + cell $eq $eq$ls180.v:3780$231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_time0 + connect \B 1'0 + connect \Y $eq$ls180.v:3780$231_Y + end + attribute \src "ls180.v:3781.32-3781.56" + cell $eq $eq$ls180.v:3781$232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_time1 + connect \B 1'0 + connect \Y $eq$ls180.v:3781$232_Y + end + attribute \src "ls180.v:3792.339-3792.418" + cell $eq $eq$ls180.v:3792$246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3792$246_Y + end + attribute \src "ls180.v:3792.423-3792.504" + cell $eq $eq$ls180.v:3792$247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3792$247_Y + end + attribute \src "ls180.v:3793.339-3793.418" + cell $eq $eq$ls180.v:3793$259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3793$259_Y + end + attribute \src "ls180.v:3793.423-3793.504" + cell $eq $eq$ls180.v:3793$260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3793$260_Y + end + attribute \src "ls180.v:3794.339-3794.418" + cell $eq $eq$ls180.v:3794$272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3794$272_Y + end + attribute \src "ls180.v:3794.423-3794.504" + cell $eq $eq$ls180.v:3794$273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3794$273_Y + end + attribute \src "ls180.v:3795.339-3795.418" + cell $eq $eq$ls180.v:3795$285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3795$285_Y + end + attribute \src "ls180.v:3795.423-3795.504" + cell $eq $eq$ls180.v:3795$286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3795$286_Y + end + attribute \src "ls180.v:3825.339-3825.418" + cell $eq $eq$ls180.v:3825$304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3825$304_Y + end + attribute \src "ls180.v:3825.423-3825.504" + cell $eq $eq$ls180.v:3825$305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3825$305_Y + end + attribute \src "ls180.v:3826.339-3826.418" + cell $eq $eq$ls180.v:3826$317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3826$317_Y + end + attribute \src "ls180.v:3826.423-3826.504" + cell $eq $eq$ls180.v:3826$318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3826$318_Y + end + attribute \src "ls180.v:3827.339-3827.418" + cell $eq $eq$ls180.v:3827$330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3827$330_Y + end + attribute \src "ls180.v:3827.423-3827.504" + cell $eq $eq$ls180.v:3827$331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3827$331_Y + end + attribute \src "ls180.v:3828.339-3828.418" + cell $eq $eq$ls180.v:3828$343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3828$343_Y + end + attribute \src "ls180.v:3828.423-3828.504" + cell $eq $eq$ls180.v:3828$344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3828$344_Y + end + attribute \src "ls180.v:3857.78-3857.113" + cell $eq $eq$ls180.v:3857$353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3857$353_Y + end + attribute \src "ls180.v:3860.78-3860.113" + cell $eq $eq$ls180.v:3860$356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3860$356_Y + end + attribute \src "ls180.v:3866.78-3866.113" + cell $eq $eq$ls180.v:3866$360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 1'1 + connect \Y $eq$ls180.v:3866$360_Y + end + attribute \src "ls180.v:3869.78-3869.113" + cell $eq $eq$ls180.v:3869$363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 1'1 + connect \Y $eq$ls180.v:3869$363_Y + end + attribute \src "ls180.v:3875.78-3875.113" + cell $eq $eq$ls180.v:3875$367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 2'10 + connect \Y $eq$ls180.v:3875$367_Y + end + attribute \src "ls180.v:3878.78-3878.113" + cell $eq $eq$ls180.v:3878$370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 2'10 + connect \Y $eq$ls180.v:3878$370_Y + end + attribute \src "ls180.v:3884.78-3884.113" + cell $eq $eq$ls180.v:3884$374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 2'11 + connect \Y $eq$ls180.v:3884$374_Y + end + attribute \src "ls180.v:3887.78-3887.113" + cell $eq $eq$ls180.v:3887$377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 2'11 + connect \Y $eq$ls180.v:3887$377_Y + end + attribute \src "ls180.v:3968.42-3968.82" + cell $eq $eq$ls180.v:3968$400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:3968$400_Y + end + attribute \src "ls180.v:3968.145-3968.178" + cell $eq $eq$ls180.v:3968$401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3968$401_Y + end + attribute \src "ls180.v:3968.220-3968.253" + cell $eq $eq$ls180.v:3968$404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3968$404_Y + end + attribute \src "ls180.v:3968.295-3968.328" + cell $eq $eq$ls180.v:3968$407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3968$407_Y + end + attribute \src "ls180.v:3973.42-3973.82" + cell $eq $eq$ls180.v:3973$416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:3973$416_Y + end + attribute \src "ls180.v:3973.145-3973.178" + cell $eq $eq$ls180.v:3973$417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3973$417_Y + end + attribute \src "ls180.v:3973.220-3973.253" + cell $eq $eq$ls180.v:3973$420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3973$420_Y + end + attribute \src "ls180.v:3973.295-3973.328" + cell $eq $eq$ls180.v:3973$423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3973$423_Y + end + attribute \src "ls180.v:3978.42-3978.82" + cell $eq $eq$ls180.v:3978$432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:3978$432_Y + end + attribute \src "ls180.v:3978.145-3978.178" + cell $eq $eq$ls180.v:3978$433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3978$433_Y + end + attribute \src "ls180.v:3978.220-3978.253" + cell $eq $eq$ls180.v:3978$436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3978$436_Y + end + attribute \src "ls180.v:3978.295-3978.328" + cell $eq $eq$ls180.v:3978$439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3978$439_Y + end + attribute \src "ls180.v:3983.42-3983.82" + cell $eq $eq$ls180.v:3983$448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:3983$448_Y + end + attribute \src "ls180.v:3983.145-3983.178" + cell $eq $eq$ls180.v:3983$449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3983$449_Y + end + attribute \src "ls180.v:3983.220-3983.253" + cell $eq $eq$ls180.v:3983$452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3983$452_Y + end + attribute \src "ls180.v:3983.295-3983.328" + cell $eq $eq$ls180.v:3983$455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3983$455_Y + end + attribute \src "ls180.v:3988.44-3988.77" + cell $eq $eq$ls180.v:3988$464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3988$464_Y + end + attribute \src "ls180.v:3988.83-3988.123" + cell $eq $eq$ls180.v:3988$465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:3988$465_Y + end + attribute \src "ls180.v:3988.186-3988.219" + cell $eq $eq$ls180.v:3988$466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3988$466_Y + end + attribute \src "ls180.v:3988.261-3988.294" + cell $eq $eq$ls180.v:3988$469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3988$469_Y + end + attribute \src "ls180.v:3988.336-3988.369" + cell $eq $eq$ls180.v:3988$472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3988$472_Y + end + attribute \src "ls180.v:3988.418-3988.451" + cell $eq $eq$ls180.v:3988$480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3988$480_Y + end + attribute \src "ls180.v:3988.457-3988.497" + cell $eq $eq$ls180.v:3988$481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:3988$481_Y + end + attribute \src "ls180.v:3988.560-3988.593" + cell $eq $eq$ls180.v:3988$482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3988$482_Y + end + attribute \src "ls180.v:3988.635-3988.668" + cell $eq $eq$ls180.v:3988$485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3988$485_Y + end + attribute \src "ls180.v:3988.710-3988.743" + cell $eq $eq$ls180.v:3988$488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3988$488_Y + end + attribute \src "ls180.v:3988.792-3988.825" + cell $eq $eq$ls180.v:3988$496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3988$496_Y + end + attribute \src "ls180.v:3988.831-3988.871" + cell $eq $eq$ls180.v:3988$497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:3988$497_Y + end + attribute \src "ls180.v:3988.934-3988.967" + cell $eq $eq$ls180.v:3988$498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3988$498_Y + end + attribute \src "ls180.v:3988.1009-3988.1042" + cell $eq $eq$ls180.v:3988$501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3988$501_Y + end + attribute \src "ls180.v:3988.1084-3988.1117" + cell $eq $eq$ls180.v:3988$504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3988$504_Y + end + attribute \src "ls180.v:3988.1166-3988.1199" + cell $eq $eq$ls180.v:3988$512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3988$512_Y + end + attribute \src "ls180.v:3988.1205-3988.1245" + cell $eq $eq$ls180.v:3988$513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:3988$513_Y + end + attribute \src "ls180.v:3988.1308-3988.1341" + cell $eq $eq$ls180.v:3988$514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3988$514_Y + end + attribute \src "ls180.v:3988.1383-3988.1416" + cell $eq $eq$ls180.v:3988$517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3988$517_Y + end + attribute \src "ls180.v:3988.1458-3988.1491" + cell $eq $eq$ls180.v:3988$520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3988$520_Y + end + attribute \src "ls180.v:4047.29-4047.57" + cell $eq $eq$ls180.v:4047$533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_sel + connect \B 1'0 + connect \Y $eq$ls180.v:4047$533_Y + end + attribute \src "ls180.v:4054.11-4054.41" + cell $eq $eq$ls180.v:4054$538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_counter + connect \B 1'1 + connect \Y $eq$ls180.v:4054$538_Y + end + attribute \src "ls180.v:4211.36-4211.111" + cell $eq $eq$ls180.v:4211$603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spi_master_clk_divider1 + connect \B $sub$ls180.v:4211$602_Y + connect \Y $eq$ls180.v:4211$603_Y + end + attribute \src "ls180.v:4212.36-4212.105" + cell $eq $eq$ls180.v:4212$605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spi_master_clk_divider1 + connect \B $sub$ls180.v:4212$604_Y + connect \Y $eq$ls180.v:4212$605_Y + end + attribute \src "ls180.v:4239.10-4239.67" + cell $eq $eq$ls180.v:4239$609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_spi_master_count + connect \B $sub$ls180.v:4239$608_Y + connect \Y $eq$ls180.v:4239$609_Y + end + attribute \src "ls180.v:4343.10-4343.40" + cell $eq $eq$ls180.v:4343$636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_count + connect \B 7'1001111 + connect \Y $eq$ls180.v:4343$636_Y + end + attribute \src "ls180.v:4400.10-4400.39" + cell $eq $eq$ls180.v:4400$639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_count + connect \B 3'111 + connect \Y $eq$ls180.v:4400$639_Y + end + attribute \src "ls180.v:4417.10-4417.39" + cell $eq $eq$ls180.v:4417$641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_count + connect \B 3'111 + connect \Y $eq$ls180.v:4417$641_Y + end + attribute \src "ls180.v:4445.38-4445.88" + cell $eq $eq$ls180.v:4445$643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + connect \B 1'0 + connect \Y $eq$ls180.v:4445$643_Y + end + attribute \src "ls180.v:4495.9-4495.40" + cell $eq $eq$ls180.v:4495$653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4495$653_Y + end + attribute \src "ls180.v:4504.36-4504.105" + cell $eq $eq$ls180.v:4504$655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_count + connect \B $sub$ls180.v:4504$654_Y + connect \Y $eq$ls180.v:4504$655_Y + end + attribute \src "ls180.v:4523.9-4523.40" + cell $eq $eq$ls180.v:4523$659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4523$659_Y + end + attribute \src "ls180.v:4535.10-4535.39" + cell $eq $eq$ls180.v:4535$661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_count + connect \B 3'111 + connect \Y $eq$ls180.v:4535$661_Y + end + attribute \src "ls180.v:4572.39-4572.94" + cell $eq $eq$ls180.v:4572$665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] + connect \B 1'0 + connect \Y $eq$ls180.v:4572$665_Y + end + attribute \src "ls180.v:4609.32-4609.89" + cell $eq $eq$ls180.v:4609$674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 + connect \B 3'101 + connect \Y $eq$ls180.v:4609$674_Y + end + attribute \src "ls180.v:4657.10-4657.40" + cell $eq $eq$ls180.v:4657$678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_count + connect \B 1'1 + connect \Y $eq$ls180.v:4657$678_Y + end + attribute \src "ls180.v:4706.40-4706.98" + cell $eq $eq$ls180.v:4706$680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_pads_in_payload_data_i + connect \B 1'0 + connect \Y $eq$ls180.v:4706$680_Y + end + attribute \src "ls180.v:4757.9-4757.41" + cell $eq $eq$ls180.v:4757$690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4757$690_Y + end + attribute \src "ls180.v:4766.37-4766.123" + cell $eq $eq$ls180.v:4766$693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_count + connect \B $sub$ls180.v:4766$692_Y + connect \Y $eq$ls180.v:4766$693_Y + end + attribute \src "ls180.v:4789.9-4789.41" + cell $eq $eq$ls180.v:4789$696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4789$696_Y + end + attribute \src "ls180.v:4799.10-4799.41" + cell $eq $eq$ls180.v:4799$698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_count + connect \B 6'100111 + connect \Y $eq$ls180.v:4799$698_Y + end + attribute \src "ls180.v:4968.9-4968.47" + cell $eq $eq$ls180.v:4968$880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:4968$880_Y + end + attribute \src "ls180.v:4998.10-4998.48" + cell $eq $eq$ls180.v:4998$881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:4998$881_Y + end + attribute \src "ls180.v:5029.10-5029.78" + cell $eq $eq$ls180.v:5029$886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo0 + connect \B \main_sdcore_crc16_checker_crctmp0 + connect \Y $eq$ls180.v:5029$886_Y + end + attribute \src "ls180.v:5029.83-5029.151" + cell $eq $eq$ls180.v:5029$887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo1 + connect \B \main_sdcore_crc16_checker_crctmp1 + connect \Y $eq$ls180.v:5029$887_Y + end + attribute \src "ls180.v:5029.157-5029.225" + cell $eq $eq$ls180.v:5029$889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo2 + connect \B \main_sdcore_crc16_checker_crctmp2 + connect \Y $eq$ls180.v:5029$889_Y + end + attribute \src "ls180.v:5029.231-5029.299" + cell $eq $eq$ls180.v:5029$891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo3 + connect \B \main_sdcore_crc16_checker_crctmp3 + connect \Y $eq$ls180.v:5029$891_Y + end + attribute \src "ls180.v:5037.7-5037.44" + cell $eq $eq$ls180.v:5037$895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5037$895_Y + end + attribute \src "ls180.v:5047.7-5047.44" + cell $eq $eq$ls180.v:5047$898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5047$898_Y + end + attribute \src "ls180.v:5057.7-5057.44" + cell $eq $eq$ls180.v:5057$901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5057$901_Y + end + attribute \src "ls180.v:5067.7-5067.44" + cell $eq $eq$ls180.v:5067$904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5067$904_Y + end + attribute \src "ls180.v:5191.36-5191.64" + cell $eq $eq$ls180.v:5191$955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 1'0 + connect \Y $eq$ls180.v:5191$955_Y + end + attribute \src "ls180.v:5197.10-5197.39" + cell $eq $eq$ls180.v:5197$958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_count + connect \B 3'101 + connect \Y $eq$ls180.v:5197$958_Y + end + attribute \src "ls180.v:5198.11-5198.39" + cell $eq $eq$ls180.v:5198$959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 1'0 + connect \Y $eq$ls180.v:5198$959_Y + end + attribute \src "ls180.v:5210.34-5210.63" + cell $eq $eq$ls180.v:5210$960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 1'0 + connect \Y $eq$ls180.v:5210$960_Y + end + attribute \src "ls180.v:5211.9-5211.37" + cell $eq $eq$ls180.v:5211$961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 2'10 + connect \Y $eq$ls180.v:5211$961_Y + end + attribute \src "ls180.v:5218.10-5218.55" + cell $eq $eq$ls180.v:5218$962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_payload_status + connect \B 1'1 + connect \Y $eq$ls180.v:5218$962_Y + end + attribute \src "ls180.v:5224.12-5224.41" + cell $eq $eq$ls180.v:5224$963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 2'10 + connect \Y $eq$ls180.v:5224$963_Y + end + attribute \src "ls180.v:5227.13-5227.42" + cell $eq $eq$ls180.v:5227$964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 1'1 + connect \Y $eq$ls180.v:5227$964_Y + end + attribute \src "ls180.v:5249.10-5249.76" + cell $eq $eq$ls180.v:5249$969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5249$968_Y + connect \Y $eq$ls180.v:5249$969_Y + end + attribute \src "ls180.v:5264.35-5264.101" + cell $eq $eq$ls180.v:5264$972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5264$971_Y + connect \Y $eq$ls180.v:5264$972_Y + end + attribute \src "ls180.v:5266.10-5266.56" + cell $eq $eq$ls180.v:5266$973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 1'0 + connect \Y $eq$ls180.v:5266$973_Y + end + attribute \src "ls180.v:5275.12-5275.78" + cell $eq $eq$ls180.v:5275$977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5275$976_Y + connect \Y $eq$ls180.v:5275$977_Y + end + attribute \src "ls180.v:5282.11-5282.57" + cell $eq $eq$ls180.v:5282$978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 1'1 + connect \Y $eq$ls180.v:5282$978_Y + end + attribute \src "ls180.v:5399.10-5399.105" + cell $eq $eq$ls180.v:5399$995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_offset + connect \B $sub$ls180.v:5399$994_Y + connect \Y $eq$ls180.v:5399$995_Y + end + attribute \src "ls180.v:5489.39-5489.106" + cell $eq $eq$ls180.v:5489$1001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_dma_offset + connect \B $sub$ls180.v:5489$1000_Y + connect \Y $eq$ls180.v:5489$1001_Y + end + attribute \src "ls180.v:5519.44-5519.82" + cell $eq $eq$ls180.v:5519$1004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_mux + connect \B 1'0 + connect \Y $eq$ls180.v:5519$1004_Y + end + attribute \src "ls180.v:5520.43-5520.81" + cell $eq $eq$ls180.v:5520$1005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_mux + connect \B 2'11 + connect \Y $eq$ls180.v:5520$1005_Y + end + attribute \src "ls180.v:5577.32-5577.99" + cell $eq $eq$ls180.v:5577$1018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \libresocsim_clk_divider1 + connect \B $sub$ls180.v:5577$1017_Y + connect \Y $eq$ls180.v:5577$1018_Y + end + attribute \src "ls180.v:5578.32-5578.93" + cell $eq $eq$ls180.v:5578$1020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \libresocsim_clk_divider1 + connect \B $sub$ls180.v:5578$1019_Y + connect \Y $eq$ls180.v:5578$1020_Y + end + attribute \src "ls180.v:5606.10-5606.59" + cell $eq $eq$ls180.v:5606$1024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \libresocsim_count + connect \B $sub$ls180.v:5606$1023_Y + connect \Y $eq$ls180.v:5606$1024_Y + end + attribute \src "ls180.v:5679.85-5679.106" + cell $eq $eq$ls180.v:5679$1029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'0 + connect \Y $eq$ls180.v:5679$1029_Y + end + attribute \src "ls180.v:5680.85-5680.106" + cell $eq $eq$ls180.v:5680$1031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'1 + connect \Y $eq$ls180.v:5680$1031_Y + end + attribute \src "ls180.v:5681.85-5681.106" + cell $eq $eq$ls180.v:5681$1033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'10 + connect \Y $eq$ls180.v:5681$1033_Y + end + attribute \src "ls180.v:5682.57-5682.78" + cell $eq $eq$ls180.v:5682$1035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'11 + connect \Y $eq$ls180.v:5682$1035_Y + end + attribute \src "ls180.v:5683.57-5683.78" + cell $eq $eq$ls180.v:5683$1037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 3'100 + connect \Y $eq$ls180.v:5683$1037_Y + end + attribute \src "ls180.v:5684.85-5684.106" + cell $eq $eq$ls180.v:5684$1039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'0 + connect \Y $eq$ls180.v:5684$1039_Y + end + attribute \src "ls180.v:5685.85-5685.106" + cell $eq $eq$ls180.v:5685$1041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'1 + connect \Y $eq$ls180.v:5685$1041_Y + end + attribute \src "ls180.v:5686.85-5686.106" + cell $eq $eq$ls180.v:5686$1043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'10 + connect \Y $eq$ls180.v:5686$1043_Y + end + attribute \src "ls180.v:5687.57-5687.78" + cell $eq $eq$ls180.v:5687$1045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'11 + connect \Y $eq$ls180.v:5687$1045_Y + end + attribute \src "ls180.v:5688.57-5688.78" + cell $eq $eq$ls180.v:5688$1047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 3'100 + connect \Y $eq$ls180.v:5688$1047_Y + end + attribute \src "ls180.v:5692.27-5692.59" + cell $eq $eq$ls180.v:5692$1050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 23 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:7] + connect \B 1'0 + connect \Y $eq$ls180.v:5692$1050_Y + end + attribute \src "ls180.v:5693.27-5693.68" + cell $eq $eq$ls180.v:5693$1051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 27 + parameter \B_SIGNED 0 + parameter \B_WIDTH 27 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:3] + connect \B 27'110000000000000100000000000 + connect \Y $eq$ls180.v:5693$1051_Y + end + attribute \src "ls180.v:5694.27-5694.66" + cell $eq $eq$ls180.v:5694$1052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 20 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:10] + connect \B 20'11000000000000010001 + connect \Y $eq$ls180.v:5694$1052_Y + end + attribute \src "ls180.v:5695.27-5695.61" + cell $eq $eq$ls180.v:5695$1053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:23] + connect \B 7'1001000 + connect \Y $eq$ls180.v:5695$1053_Y + end + attribute \src "ls180.v:5696.27-5696.65" + cell $eq $eq$ls180.v:5696$1054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:14] + connect \B 16'1100000000000000 + connect \Y $eq$ls180.v:5696$1054_Y + end + attribute \src "ls180.v:5752.24-5752.45" + cell $eq $eq$ls180.v:5752$1081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_count + connect \B 1'0 + connect \Y $eq$ls180.v:5752$1081_Y + end + attribute \src "ls180.v:5753.32-5753.77" + cell $eq $eq$ls180.v:5753$1082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [13:9] + connect \B 1'0 + connect \Y $eq$ls180.v:5753$1082_Y + end + attribute \src "ls180.v:5755.97-5755.141" + cell $eq $eq$ls180.v:5755$1084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5755$1084_Y + end + attribute \src "ls180.v:5756.100-5756.144" + cell $eq $eq$ls180.v:5756$1088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5756$1088_Y + end + attribute \src "ls180.v:5758.99-5758.143" + cell $eq $eq$ls180.v:5758$1091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5758$1091_Y + end + attribute \src "ls180.v:5759.102-5759.146" + cell $eq $eq$ls180.v:5759$1095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5759$1095_Y + end + attribute \src "ls180.v:5761.99-5761.143" + cell $eq $eq$ls180.v:5761$1098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5761$1098_Y + end + attribute \src "ls180.v:5762.102-5762.146" + cell $eq $eq$ls180.v:5762$1102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5762$1102_Y + end + attribute \src "ls180.v:5764.99-5764.143" + cell $eq $eq$ls180.v:5764$1105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5764$1105_Y + end + attribute \src "ls180.v:5765.102-5765.146" + cell $eq $eq$ls180.v:5765$1109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5765$1109_Y + end + attribute \src "ls180.v:5767.99-5767.143" + cell $eq $eq$ls180.v:5767$1112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5767$1112_Y + end + attribute \src "ls180.v:5768.102-5768.146" + cell $eq $eq$ls180.v:5768$1116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5768$1116_Y + end + attribute \src "ls180.v:5770.102-5770.146" + cell $eq $eq$ls180.v:5770$1119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5770$1119_Y + end + attribute \src "ls180.v:5771.105-5771.149" + cell $eq $eq$ls180.v:5771$1123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5771$1123_Y + end + attribute \src "ls180.v:5773.102-5773.146" + cell $eq $eq$ls180.v:5773$1126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5773$1126_Y + end + attribute \src "ls180.v:5774.105-5774.149" + cell $eq $eq$ls180.v:5774$1130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5774$1130_Y + end + attribute \src "ls180.v:5776.102-5776.146" + cell $eq $eq$ls180.v:5776$1133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5776$1133_Y + end + attribute \src "ls180.v:5777.105-5777.149" + cell $eq $eq$ls180.v:5777$1137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5777$1137_Y + end + attribute \src "ls180.v:5779.102-5779.146" + cell $eq $eq$ls180.v:5779$1140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5779$1140_Y + end + attribute \src "ls180.v:5780.105-5780.149" + cell $eq $eq$ls180.v:5780$1144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5780$1144_Y + end + attribute \src "ls180.v:5791.32-5791.77" + cell $eq $eq$ls180.v:5791$1146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [13:9] + connect \B 3'110 + connect \Y $eq$ls180.v:5791$1146_Y + end + attribute \src "ls180.v:5793.94-5793.138" + cell $eq $eq$ls180.v:5793$1148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5793$1148_Y + end + attribute \src "ls180.v:5794.97-5794.141" + cell $eq $eq$ls180.v:5794$1152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5794$1152_Y + end + attribute \src "ls180.v:5796.94-5796.138" + cell $eq $eq$ls180.v:5796$1155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5796$1155_Y + end + attribute \src "ls180.v:5797.97-5797.141" + cell $eq $eq$ls180.v:5797$1159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5797$1159_Y + end + attribute \src "ls180.v:5799.94-5799.138" + cell $eq $eq$ls180.v:5799$1162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5799$1162_Y + end + attribute \src "ls180.v:5800.97-5800.141" + cell $eq $eq$ls180.v:5800$1166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5800$1166_Y + end + attribute \src "ls180.v:5802.94-5802.138" + cell $eq $eq$ls180.v:5802$1169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5802$1169_Y + end + attribute \src "ls180.v:5803.97-5803.141" + cell $eq $eq$ls180.v:5803$1173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5803$1173_Y + end + attribute \src "ls180.v:5805.95-5805.139" + cell $eq $eq$ls180.v:5805$1176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5805$1176_Y + end + attribute \src "ls180.v:5806.98-5806.142" + cell $eq $eq$ls180.v:5806$1180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5806$1180_Y + end + attribute \src "ls180.v:5808.95-5808.139" + cell $eq $eq$ls180.v:5808$1183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5808$1183_Y + end + attribute \src "ls180.v:5809.98-5809.142" + cell $eq $eq$ls180.v:5809$1187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5809$1187_Y + end + attribute \src "ls180.v:5817.32-5817.78" + cell $eq $eq$ls180.v:5817$1189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [13:9] + connect \B 4'1010 + connect \Y $eq$ls180.v:5817$1189_Y + end + attribute \src "ls180.v:5819.93-5819.135" + cell $eq $eq$ls180.v:5819$1191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$ls180.v:5819$1191_Y + end + attribute \src "ls180.v:5820.96-5820.138" + cell $eq $eq$ls180.v:5820$1195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$ls180.v:5820$1195_Y + end + attribute \src "ls180.v:5822.92-5822.134" + cell $eq $eq$ls180.v:5822$1198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'1 + connect \Y $eq$ls180.v:5822$1198_Y + end + attribute \src "ls180.v:5823.95-5823.137" + cell $eq $eq$ls180.v:5823$1202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'1 + connect \Y $eq$ls180.v:5823$1202_Y + end + attribute \src "ls180.v:5831.32-5831.77" + cell $eq $eq$ls180.v:5831$1204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [13:9] + connect \B 4'1000 + connect \Y $eq$ls180.v:5831$1204_Y + end + attribute \src "ls180.v:5833.98-5833.142" + cell $eq $eq$ls180.v:5833$1206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5833$1206_Y + end + attribute \src "ls180.v:5834.101-5834.145" + cell $eq $eq$ls180.v:5834$1210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5834$1210_Y + end + attribute \src "ls180.v:5836.97-5836.141" + cell $eq $eq$ls180.v:5836$1213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5836$1213_Y + end + attribute \src "ls180.v:5837.100-5837.144" + cell $eq $eq$ls180.v:5837$1217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5837$1217_Y + end + attribute \src "ls180.v:5839.97-5839.141" + cell $eq $eq$ls180.v:5839$1220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5839$1220_Y + end + attribute \src "ls180.v:5840.100-5840.144" + cell $eq $eq$ls180.v:5840$1224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5840$1224_Y + end + attribute \src "ls180.v:5842.97-5842.141" + cell $eq $eq$ls180.v:5842$1227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5842$1227_Y + end + attribute \src "ls180.v:5843.100-5843.144" + cell $eq $eq$ls180.v:5843$1231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5843$1231_Y + end + attribute \src "ls180.v:5845.97-5845.141" + cell $eq $eq$ls180.v:5845$1234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5845$1234_Y + end + attribute \src "ls180.v:5846.100-5846.144" + cell $eq $eq$ls180.v:5846$1238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5846$1238_Y + end + attribute \src "ls180.v:5848.98-5848.142" + cell $eq $eq$ls180.v:5848$1241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5848$1241_Y + end + attribute \src "ls180.v:5849.101-5849.145" + cell $eq $eq$ls180.v:5849$1245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5849$1245_Y + end + attribute \src "ls180.v:5851.98-5851.142" + cell $eq $eq$ls180.v:5851$1248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5851$1248_Y + end + attribute \src "ls180.v:5852.101-5852.145" + cell $eq $eq$ls180.v:5852$1252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5852$1252_Y + end + attribute \src "ls180.v:5854.98-5854.142" + cell $eq $eq$ls180.v:5854$1255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5854$1255_Y + end + attribute \src "ls180.v:5855.101-5855.145" + cell $eq $eq$ls180.v:5855$1259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5855$1259_Y + end + attribute \src "ls180.v:5857.98-5857.142" + cell $eq $eq$ls180.v:5857$1262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5857$1262_Y + end + attribute \src "ls180.v:5858.101-5858.145" + cell $eq $eq$ls180.v:5858$1266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5858$1266_Y + end + attribute \src "ls180.v:5868.32-5868.77" + cell $eq $eq$ls180.v:5868$1268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [13:9] + connect \B 4'1001 + connect \Y $eq$ls180.v:5868$1268_Y + end + attribute \src "ls180.v:5870.98-5870.142" + cell $eq $eq$ls180.v:5870$1270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5870$1270_Y + end + attribute \src "ls180.v:5871.101-5871.145" + cell $eq $eq$ls180.v:5871$1274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5871$1274_Y + end + attribute \src "ls180.v:5873.97-5873.141" + cell $eq $eq$ls180.v:5873$1277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5873$1277_Y + end + attribute \src "ls180.v:5874.100-5874.144" + cell $eq $eq$ls180.v:5874$1281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5874$1281_Y + end + attribute \src "ls180.v:5876.97-5876.141" + cell $eq $eq$ls180.v:5876$1284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5876$1284_Y + end + attribute \src "ls180.v:5877.100-5877.144" + cell $eq $eq$ls180.v:5877$1288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5877$1288_Y + end + attribute \src "ls180.v:5879.97-5879.141" + cell $eq $eq$ls180.v:5879$1291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5879$1291_Y + end + attribute \src "ls180.v:5880.100-5880.144" + cell $eq $eq$ls180.v:5880$1295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5880$1295_Y + end + attribute \src "ls180.v:5882.97-5882.141" + cell $eq $eq$ls180.v:5882$1298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5882$1298_Y + end + attribute \src "ls180.v:5883.100-5883.144" + cell $eq $eq$ls180.v:5883$1302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5883$1302_Y + end + attribute \src "ls180.v:5885.98-5885.142" + cell $eq $eq$ls180.v:5885$1305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5885$1305_Y + end + attribute \src "ls180.v:5886.101-5886.145" + cell $eq $eq$ls180.v:5886$1309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5886$1309_Y + end + attribute \src "ls180.v:5888.98-5888.142" + cell $eq $eq$ls180.v:5888$1312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5888$1312_Y + end + attribute \src "ls180.v:5889.101-5889.145" + cell $eq $eq$ls180.v:5889$1316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5889$1316_Y + end + attribute \src "ls180.v:5891.98-5891.142" + cell $eq $eq$ls180.v:5891$1319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5891$1319_Y + end + attribute \src "ls180.v:5892.101-5892.145" + cell $eq $eq$ls180.v:5892$1323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5892$1323_Y + end + attribute \src "ls180.v:5894.98-5894.142" + cell $eq $eq$ls180.v:5894$1326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5894$1326_Y + end + attribute \src "ls180.v:5895.101-5895.145" + cell $eq $eq$ls180.v:5895$1330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5895$1330_Y + end + attribute \src "ls180.v:5905.32-5905.78" + cell $eq $eq$ls180.v:5905$1332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [13:9] + connect \B 4'1101 + connect \Y $eq$ls180.v:5905$1332_Y + end + attribute \src "ls180.v:5907.100-5907.144" + cell $eq $eq$ls180.v:5907$1334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5907$1334_Y + end + attribute \src "ls180.v:5908.103-5908.147" + cell $eq $eq$ls180.v:5908$1338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5908$1338_Y + end + attribute \src "ls180.v:5910.100-5910.144" + cell $eq $eq$ls180.v:5910$1341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5910$1341_Y + end + attribute \src "ls180.v:5911.103-5911.147" + cell $eq $eq$ls180.v:5911$1345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5911$1345_Y + end + attribute \src "ls180.v:5913.100-5913.144" + cell $eq $eq$ls180.v:5913$1348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5913$1348_Y + end + attribute \src "ls180.v:5914.103-5914.147" + cell $eq $eq$ls180.v:5914$1352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5914$1352_Y + end + attribute \src "ls180.v:5916.100-5916.144" + cell $eq $eq$ls180.v:5916$1355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5916$1355_Y + end + attribute \src "ls180.v:5917.103-5917.147" + cell $eq $eq$ls180.v:5917$1359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5917$1359_Y + end + attribute \src "ls180.v:5919.100-5919.144" + cell $eq $eq$ls180.v:5919$1362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5919$1362_Y + end + attribute \src "ls180.v:5920.103-5920.147" + cell $eq $eq$ls180.v:5920$1366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5920$1366_Y + end + attribute \src "ls180.v:5922.100-5922.144" + cell $eq $eq$ls180.v:5922$1369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5922$1369_Y + end + attribute \src "ls180.v:5923.103-5923.147" + cell $eq $eq$ls180.v:5923$1373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5923$1373_Y + end + attribute \src "ls180.v:5925.100-5925.144" + cell $eq $eq$ls180.v:5925$1376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5925$1376_Y + end + attribute \src "ls180.v:5926.103-5926.147" + cell $eq $eq$ls180.v:5926$1380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5926$1380_Y + end + attribute \src "ls180.v:5928.100-5928.144" + cell $eq $eq$ls180.v:5928$1383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5928$1383_Y + end + attribute \src "ls180.v:5929.103-5929.147" + cell $eq $eq$ls180.v:5929$1387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5929$1387_Y + end + attribute \src "ls180.v:5931.102-5931.146" + cell $eq $eq$ls180.v:5931$1390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5931$1390_Y + end + attribute \src "ls180.v:5932.105-5932.149" + cell $eq $eq$ls180.v:5932$1394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5932$1394_Y + end + attribute \src "ls180.v:5934.102-5934.146" + cell $eq $eq$ls180.v:5934$1397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:5934$1397_Y + end + attribute \src "ls180.v:5935.105-5935.149" + cell $eq $eq$ls180.v:5935$1401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:5935$1401_Y + end + attribute \src "ls180.v:5937.102-5937.147" + cell $eq $eq$ls180.v:5937$1404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:5937$1404_Y + end + attribute \src "ls180.v:5938.105-5938.150" + cell $eq $eq$ls180.v:5938$1408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:5938$1408_Y + end + attribute \src "ls180.v:5940.102-5940.147" + cell $eq $eq$ls180.v:5940$1411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:5940$1411_Y + end + attribute \src "ls180.v:5941.105-5941.150" + cell $eq $eq$ls180.v:5941$1415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:5941$1415_Y + end + attribute \src "ls180.v:5943.102-5943.147" + cell $eq $eq$ls180.v:5943$1418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:5943$1418_Y + end + attribute \src "ls180.v:5944.105-5944.150" + cell $eq $eq$ls180.v:5944$1422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:5944$1422_Y + end + attribute \src "ls180.v:5946.99-5946.144" + cell $eq $eq$ls180.v:5946$1425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:5946$1425_Y + end + attribute \src "ls180.v:5947.102-5947.147" + cell $eq $eq$ls180.v:5947$1429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:5947$1429_Y + end + attribute \src "ls180.v:5949.100-5949.145" + cell $eq $eq$ls180.v:5949$1432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:5949$1432_Y + end + attribute \src "ls180.v:5950.103-5950.148" + cell $eq $eq$ls180.v:5950$1436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:5950$1436_Y + end + attribute \src "ls180.v:5967.32-5967.78" + cell $eq $eq$ls180.v:5967$1438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [13:9] + connect \B 4'1100 + connect \Y $eq$ls180.v:5967$1438_Y + end + attribute \src "ls180.v:5969.104-5969.148" + cell $eq $eq$ls180.v:5969$1440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5969$1440_Y + end + attribute \src "ls180.v:5970.107-5970.151" + cell $eq $eq$ls180.v:5970$1444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5970$1444_Y + end + attribute \src "ls180.v:5972.104-5972.148" + cell $eq $eq$ls180.v:5972$1447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5972$1447_Y + end + attribute \src "ls180.v:5973.107-5973.151" + cell $eq $eq$ls180.v:5973$1451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5973$1451_Y + end + attribute \src "ls180.v:5975.104-5975.148" + cell $eq $eq$ls180.v:5975$1454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5975$1454_Y + end + attribute \src "ls180.v:5976.107-5976.151" + cell $eq $eq$ls180.v:5976$1458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5976$1458_Y + end + attribute \src "ls180.v:5978.104-5978.148" + cell $eq $eq$ls180.v:5978$1461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5978$1461_Y + end + attribute \src "ls180.v:5979.107-5979.151" + cell $eq $eq$ls180.v:5979$1465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5979$1465_Y + end + attribute \src "ls180.v:5981.103-5981.147" + cell $eq $eq$ls180.v:5981$1468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5981$1468_Y + end + attribute \src "ls180.v:5982.106-5982.150" + cell $eq $eq$ls180.v:5982$1472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5982$1472_Y + end + attribute \src "ls180.v:5984.103-5984.147" + cell $eq $eq$ls180.v:5984$1475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5984$1475_Y + end + attribute \src "ls180.v:5985.106-5985.150" + cell $eq $eq$ls180.v:5985$1479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5985$1479_Y + end + attribute \src "ls180.v:5987.103-5987.147" + cell $eq $eq$ls180.v:5987$1482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5987$1482_Y + end + attribute \src "ls180.v:5988.106-5988.150" + cell $eq $eq$ls180.v:5988$1486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5988$1486_Y + end + attribute \src "ls180.v:5990.103-5990.147" + cell $eq $eq$ls180.v:5990$1489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5990$1489_Y + end + attribute \src "ls180.v:5991.106-5991.150" + cell $eq $eq$ls180.v:5991$1493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5991$1493_Y + end + attribute \src "ls180.v:5993.94-5993.138" + cell $eq $eq$ls180.v:5993$1496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5993$1496_Y + end + attribute \src "ls180.v:5994.97-5994.141" + cell $eq $eq$ls180.v:5994$1500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5994$1500_Y + end + attribute \src "ls180.v:5996.105-5996.149" + cell $eq $eq$ls180.v:5996$1503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:5996$1503_Y + end + attribute \src "ls180.v:5997.108-5997.152" + cell $eq $eq$ls180.v:5997$1507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:5997$1507_Y + end + attribute \src "ls180.v:5999.105-5999.150" + cell $eq $eq$ls180.v:5999$1510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:5999$1510_Y + end + attribute \src "ls180.v:6000.108-6000.153" + cell $eq $eq$ls180.v:6000$1514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6000$1514_Y + end + attribute \src "ls180.v:6002.105-6002.150" + cell $eq $eq$ls180.v:6002$1517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6002$1517_Y + end + attribute \src "ls180.v:6003.108-6003.153" + cell $eq $eq$ls180.v:6003$1521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6003$1521_Y + end + attribute \src "ls180.v:6005.105-6005.150" + cell $eq $eq$ls180.v:6005$1524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6005$1524_Y + end + attribute \src "ls180.v:6006.108-6006.153" + cell $eq $eq$ls180.v:6006$1528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6006$1528_Y + end + attribute \src "ls180.v:6008.105-6008.150" + cell $eq $eq$ls180.v:6008$1531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6008$1531_Y + end + attribute \src "ls180.v:6009.108-6009.153" + cell $eq $eq$ls180.v:6009$1535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6009$1535_Y + end + attribute \src "ls180.v:6011.105-6011.150" + cell $eq $eq$ls180.v:6011$1538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6011$1538_Y + end + attribute \src "ls180.v:6012.108-6012.153" + cell $eq $eq$ls180.v:6012$1542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6012$1542_Y + end + attribute \src "ls180.v:6014.104-6014.149" + cell $eq $eq$ls180.v:6014$1545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6014$1545_Y + end + attribute \src "ls180.v:6015.107-6015.152" + cell $eq $eq$ls180.v:6015$1549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6015$1549_Y + end + attribute \src "ls180.v:6017.104-6017.149" + cell $eq $eq$ls180.v:6017$1552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6017$1552_Y + end + attribute \src "ls180.v:6018.107-6018.152" + cell $eq $eq$ls180.v:6018$1556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6018$1556_Y + end + attribute \src "ls180.v:6020.104-6020.149" + cell $eq $eq$ls180.v:6020$1559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6020$1559_Y + end + attribute \src "ls180.v:6021.107-6021.152" + cell $eq $eq$ls180.v:6021$1563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6021$1563_Y + end + attribute \src "ls180.v:6023.104-6023.149" + cell $eq $eq$ls180.v:6023$1566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6023$1566_Y + end + attribute \src "ls180.v:6024.107-6024.152" + cell $eq $eq$ls180.v:6024$1570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6024$1570_Y + end + attribute \src "ls180.v:6026.104-6026.149" + cell $eq $eq$ls180.v:6026$1573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10011 + connect \Y $eq$ls180.v:6026$1573_Y + end + attribute \src "ls180.v:6027.107-6027.152" + cell $eq $eq$ls180.v:6027$1577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10011 + connect \Y $eq$ls180.v:6027$1577_Y + end + attribute \src "ls180.v:6029.104-6029.149" + cell $eq $eq$ls180.v:6029$1580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10100 + connect \Y $eq$ls180.v:6029$1580_Y + end + attribute \src "ls180.v:6030.107-6030.152" + cell $eq $eq$ls180.v:6030$1584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10100 + connect \Y $eq$ls180.v:6030$1584_Y + end + attribute \src "ls180.v:6032.104-6032.149" + cell $eq $eq$ls180.v:6032$1587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10101 + connect \Y $eq$ls180.v:6032$1587_Y + end + attribute \src "ls180.v:6033.107-6033.152" + cell $eq $eq$ls180.v:6033$1591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10101 + connect \Y $eq$ls180.v:6033$1591_Y + end + attribute \src "ls180.v:6035.104-6035.149" + cell $eq $eq$ls180.v:6035$1594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10110 + connect \Y $eq$ls180.v:6035$1594_Y + end + attribute \src "ls180.v:6036.107-6036.152" + cell $eq $eq$ls180.v:6036$1598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10110 + connect \Y $eq$ls180.v:6036$1598_Y + end + attribute \src "ls180.v:6038.104-6038.149" + cell $eq $eq$ls180.v:6038$1601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10111 + connect \Y $eq$ls180.v:6038$1601_Y + end + attribute \src "ls180.v:6039.107-6039.152" + cell $eq $eq$ls180.v:6039$1605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10111 + connect \Y $eq$ls180.v:6039$1605_Y + end + attribute \src "ls180.v:6041.104-6041.149" + cell $eq $eq$ls180.v:6041$1608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11000 + connect \Y $eq$ls180.v:6041$1608_Y + end + attribute \src "ls180.v:6042.107-6042.152" + cell $eq $eq$ls180.v:6042$1612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11000 + connect \Y $eq$ls180.v:6042$1612_Y + end + attribute \src "ls180.v:6044.100-6044.145" + cell $eq $eq$ls180.v:6044$1615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11001 + connect \Y $eq$ls180.v:6044$1615_Y + end + attribute \src "ls180.v:6045.103-6045.148" + cell $eq $eq$ls180.v:6045$1619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11001 + connect \Y $eq$ls180.v:6045$1619_Y + end + attribute \src "ls180.v:6047.101-6047.146" + cell $eq $eq$ls180.v:6047$1622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11010 + connect \Y $eq$ls180.v:6047$1622_Y + end + attribute \src "ls180.v:6048.104-6048.149" + cell $eq $eq$ls180.v:6048$1626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11010 + connect \Y $eq$ls180.v:6048$1626_Y + end + attribute \src "ls180.v:6050.104-6050.149" + cell $eq $eq$ls180.v:6050$1629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11011 + connect \Y $eq$ls180.v:6050$1629_Y + end + attribute \src "ls180.v:6051.107-6051.152" + cell $eq $eq$ls180.v:6051$1633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11011 + connect \Y $eq$ls180.v:6051$1633_Y + end + attribute \src "ls180.v:6053.104-6053.149" + cell $eq $eq$ls180.v:6053$1636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11100 + connect \Y $eq$ls180.v:6053$1636_Y + end + attribute \src "ls180.v:6054.107-6054.152" + cell $eq $eq$ls180.v:6054$1640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11100 + connect \Y $eq$ls180.v:6054$1640_Y + end + attribute \src "ls180.v:6056.103-6056.148" + cell $eq $eq$ls180.v:6056$1643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11101 + connect \Y $eq$ls180.v:6056$1643_Y + end + attribute \src "ls180.v:6057.106-6057.151" + cell $eq $eq$ls180.v:6057$1647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11101 + connect \Y $eq$ls180.v:6057$1647_Y + end + attribute \src "ls180.v:6059.103-6059.148" + cell $eq $eq$ls180.v:6059$1650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11110 + connect \Y $eq$ls180.v:6059$1650_Y + end + attribute \src "ls180.v:6060.106-6060.151" + cell $eq $eq$ls180.v:6060$1654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11110 + connect \Y $eq$ls180.v:6060$1654_Y + end + attribute \src "ls180.v:6062.103-6062.148" + cell $eq $eq$ls180.v:6062$1657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11111 + connect \Y $eq$ls180.v:6062$1657_Y + end + attribute \src "ls180.v:6063.106-6063.151" + cell $eq $eq$ls180.v:6063$1661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11111 + connect \Y $eq$ls180.v:6063$1661_Y + end + attribute \src "ls180.v:6065.103-6065.148" + cell $eq $eq$ls180.v:6065$1664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 6'100000 + connect \Y $eq$ls180.v:6065$1664_Y + end + attribute \src "ls180.v:6066.106-6066.151" + cell $eq $eq$ls180.v:6066$1668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 6'100000 + connect \Y $eq$ls180.v:6066$1668_Y + end + attribute \src "ls180.v:6102.32-6102.78" + cell $eq $eq$ls180.v:6102$1670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [13:9] + connect \B 4'1110 + connect \Y $eq$ls180.v:6102$1670_Y + end + attribute \src "ls180.v:6104.100-6104.144" + cell $eq $eq$ls180.v:6104$1672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6104$1672_Y + end + attribute \src "ls180.v:6105.103-6105.147" + cell $eq $eq$ls180.v:6105$1676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6105$1676_Y + end + attribute \src "ls180.v:6107.100-6107.144" + cell $eq $eq$ls180.v:6107$1679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6107$1679_Y + end + attribute \src "ls180.v:6108.103-6108.147" + cell $eq $eq$ls180.v:6108$1683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6108$1683_Y + end + attribute \src "ls180.v:6110.100-6110.144" + cell $eq $eq$ls180.v:6110$1686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6110$1686_Y + end + attribute \src "ls180.v:6111.103-6111.147" + cell $eq $eq$ls180.v:6111$1690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6111$1690_Y + end + attribute \src "ls180.v:6113.100-6113.144" + cell $eq $eq$ls180.v:6113$1693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6113$1693_Y + end + attribute \src "ls180.v:6114.103-6114.147" + cell $eq $eq$ls180.v:6114$1697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6114$1697_Y + end + attribute \src "ls180.v:6116.100-6116.144" + cell $eq $eq$ls180.v:6116$1700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6116$1700_Y + end + attribute \src "ls180.v:6117.103-6117.147" + cell $eq $eq$ls180.v:6117$1704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6117$1704_Y + end + attribute \src "ls180.v:6119.100-6119.144" + cell $eq $eq$ls180.v:6119$1707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6119$1707_Y + end + attribute \src "ls180.v:6120.103-6120.147" + cell $eq $eq$ls180.v:6120$1711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6120$1711_Y + end + attribute \src "ls180.v:6122.100-6122.144" + cell $eq $eq$ls180.v:6122$1714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6122$1714_Y + end + attribute \src "ls180.v:6123.103-6123.147" + cell $eq $eq$ls180.v:6123$1718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6123$1718_Y + end + attribute \src "ls180.v:6125.100-6125.144" + cell $eq $eq$ls180.v:6125$1721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6125$1721_Y + end + attribute \src "ls180.v:6126.103-6126.147" + cell $eq $eq$ls180.v:6126$1725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6126$1725_Y + end + attribute \src "ls180.v:6128.102-6128.146" + cell $eq $eq$ls180.v:6128$1728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6128$1728_Y + end + attribute \src "ls180.v:6129.105-6129.149" + cell $eq $eq$ls180.v:6129$1732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6129$1732_Y + end + attribute \src "ls180.v:6131.102-6131.146" + cell $eq $eq$ls180.v:6131$1735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6131$1735_Y + end + attribute \src "ls180.v:6132.105-6132.149" + cell $eq $eq$ls180.v:6132$1739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6132$1739_Y + end + attribute \src "ls180.v:6134.102-6134.147" + cell $eq $eq$ls180.v:6134$1742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6134$1742_Y + end + attribute \src "ls180.v:6135.105-6135.150" + cell $eq $eq$ls180.v:6135$1746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6135$1746_Y + end + attribute \src "ls180.v:6137.102-6137.147" + cell $eq $eq$ls180.v:6137$1749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6137$1749_Y + end + attribute \src "ls180.v:6138.105-6138.150" + cell $eq $eq$ls180.v:6138$1753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6138$1753_Y + end + attribute \src "ls180.v:6140.102-6140.147" + cell $eq $eq$ls180.v:6140$1756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6140$1756_Y + end + attribute \src "ls180.v:6141.105-6141.150" + cell $eq $eq$ls180.v:6141$1760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6141$1760_Y + end + attribute \src "ls180.v:6143.99-6143.144" + cell $eq $eq$ls180.v:6143$1763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6143$1763_Y + end + attribute \src "ls180.v:6144.102-6144.147" + cell $eq $eq$ls180.v:6144$1767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6144$1767_Y + end + attribute \src "ls180.v:6146.100-6146.145" + cell $eq $eq$ls180.v:6146$1770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6146$1770_Y + end + attribute \src "ls180.v:6147.103-6147.148" + cell $eq $eq$ls180.v:6147$1774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6147$1774_Y + end + attribute \src "ls180.v:6149.102-6149.147" + cell $eq $eq$ls180.v:6149$1777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6149$1777_Y + end + attribute \src "ls180.v:6150.105-6150.150" + cell $eq $eq$ls180.v:6150$1781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6150$1781_Y + end + attribute \src "ls180.v:6152.102-6152.147" + cell $eq $eq$ls180.v:6152$1784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6152$1784_Y + end + attribute \src "ls180.v:6153.105-6153.150" + cell $eq $eq$ls180.v:6153$1788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6153$1788_Y + end + attribute \src "ls180.v:6155.102-6155.147" + cell $eq $eq$ls180.v:6155$1791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6155$1791_Y + end + attribute \src "ls180.v:6156.105-6156.150" + cell $eq $eq$ls180.v:6156$1795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6156$1795_Y + end + attribute \src "ls180.v:6158.102-6158.147" + cell $eq $eq$ls180.v:6158$1798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6158$1798_Y + end + attribute \src "ls180.v:6159.105-6159.150" + cell $eq $eq$ls180.v:6159$1802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6159$1802_Y + end + attribute \src "ls180.v:6181.32-6181.78" + cell $eq $eq$ls180.v:6181$1804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [13:9] + connect \B 4'1011 + connect \Y $eq$ls180.v:6181$1804_Y + end + attribute \src "ls180.v:6183.102-6183.146" + cell $eq $eq$ls180.v:6183$1806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6183$1806_Y + end + attribute \src "ls180.v:6184.105-6184.149" + cell $eq $eq$ls180.v:6184$1810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6184$1810_Y + end + attribute \src "ls180.v:6186.107-6186.151" + cell $eq $eq$ls180.v:6186$1813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6186$1813_Y + end + attribute \src "ls180.v:6187.110-6187.154" + cell $eq $eq$ls180.v:6187$1817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6187$1817_Y + end + attribute \src "ls180.v:6189.107-6189.151" + cell $eq $eq$ls180.v:6189$1820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6189$1820_Y + end + attribute \src "ls180.v:6190.110-6190.154" + cell $eq $eq$ls180.v:6190$1824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6190$1824_Y + end + attribute \src "ls180.v:6192.100-6192.144" + cell $eq $eq$ls180.v:6192$1827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6192$1827_Y + end + attribute \src "ls180.v:6193.103-6193.147" + cell $eq $eq$ls180.v:6193$1831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6193$1831_Y + end + attribute \src "ls180.v:6198.32-6198.77" + cell $eq $eq$ls180.v:6198$1833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [13:9] + connect \B 2'11 + connect \Y $eq$ls180.v:6198$1833_Y + end + attribute \src "ls180.v:6200.104-6200.148" + cell $eq $eq$ls180.v:6200$1835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6200$1835_Y + end + attribute \src "ls180.v:6201.107-6201.151" + cell $eq $eq$ls180.v:6201$1839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6201$1839_Y + end + attribute \src "ls180.v:6203.108-6203.152" + cell $eq $eq$ls180.v:6203$1842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6203$1842_Y + end + attribute \src "ls180.v:6204.111-6204.155" + cell $eq $eq$ls180.v:6204$1846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6204$1846_Y + end + attribute \src "ls180.v:6206.98-6206.142" + cell $eq $eq$ls180.v:6206$1849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6206$1849_Y + end + attribute \src "ls180.v:6207.101-6207.145" + cell $eq $eq$ls180.v:6207$1853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6207$1853_Y + end + attribute \src "ls180.v:6209.108-6209.152" + cell $eq $eq$ls180.v:6209$1856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6209$1856_Y + end + attribute \src "ls180.v:6210.111-6210.155" + cell $eq $eq$ls180.v:6210$1860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6210$1860_Y + end + attribute \src "ls180.v:6212.108-6212.152" + cell $eq $eq$ls180.v:6212$1863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6212$1863_Y + end + attribute \src "ls180.v:6213.111-6213.155" + cell $eq $eq$ls180.v:6213$1867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6213$1867_Y + end + attribute \src "ls180.v:6215.109-6215.153" + cell $eq $eq$ls180.v:6215$1870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6215$1870_Y + end + attribute \src "ls180.v:6216.112-6216.156" + cell $eq $eq$ls180.v:6216$1874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6216$1874_Y + end + attribute \src "ls180.v:6218.107-6218.151" + cell $eq $eq$ls180.v:6218$1877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6218$1877_Y + end + attribute \src "ls180.v:6219.110-6219.154" + cell $eq $eq$ls180.v:6219$1881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6219$1881_Y + end + attribute \src "ls180.v:6221.107-6221.151" + cell $eq $eq$ls180.v:6221$1884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6221$1884_Y + end + attribute \src "ls180.v:6222.110-6222.154" + cell $eq $eq$ls180.v:6222$1888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6222$1888_Y + end + attribute \src "ls180.v:6224.107-6224.151" + cell $eq $eq$ls180.v:6224$1891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6224$1891_Y + end + attribute \src "ls180.v:6225.110-6225.154" + cell $eq $eq$ls180.v:6225$1895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6225$1895_Y + end + attribute \src "ls180.v:6227.107-6227.151" + cell $eq $eq$ls180.v:6227$1898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6227$1898_Y + end + attribute \src "ls180.v:6228.110-6228.154" + cell $eq $eq$ls180.v:6228$1902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6228$1902_Y + end + attribute \src "ls180.v:6243.33-6243.79" + cell $eq $eq$ls180.v:6243$1904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [13:9] + connect \B 3'111 + connect \Y $eq$ls180.v:6243$1904_Y + end + attribute \src "ls180.v:6245.102-6245.147" + cell $eq $eq$ls180.v:6245$1906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6245$1906_Y + end + attribute \src "ls180.v:6246.105-6246.150" + cell $eq $eq$ls180.v:6246$1910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6246$1910_Y + end + attribute \src "ls180.v:6248.102-6248.147" + cell $eq $eq$ls180.v:6248$1913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6248$1913_Y + end + attribute \src "ls180.v:6249.105-6249.150" + cell $eq $eq$ls180.v:6249$1917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6249$1917_Y + end + attribute \src "ls180.v:6251.100-6251.145" + cell $eq $eq$ls180.v:6251$1920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6251$1920_Y + end + attribute \src "ls180.v:6252.103-6252.148" + cell $eq $eq$ls180.v:6252$1924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6252$1924_Y + end + attribute \src "ls180.v:6254.99-6254.144" + cell $eq $eq$ls180.v:6254$1927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6254$1927_Y + end + attribute \src "ls180.v:6255.102-6255.147" + cell $eq $eq$ls180.v:6255$1931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6255$1931_Y + end + attribute \src "ls180.v:6257.98-6257.143" + cell $eq $eq$ls180.v:6257$1934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6257$1934_Y + end + attribute \src "ls180.v:6258.101-6258.146" + cell $eq $eq$ls180.v:6258$1938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6258$1938_Y + end + attribute \src "ls180.v:6260.97-6260.142" + cell $eq $eq$ls180.v:6260$1941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6260$1941_Y + end + attribute \src "ls180.v:6261.100-6261.145" + cell $eq $eq$ls180.v:6261$1945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6261$1945_Y + end + attribute \src "ls180.v:6263.103-6263.148" + cell $eq $eq$ls180.v:6263$1948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6263$1948_Y + end + attribute \src "ls180.v:6264.106-6264.151" + cell $eq $eq$ls180.v:6264$1952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6264$1952_Y + end + attribute \src "ls180.v:6283.33-6283.80" + cell $eq $eq$ls180.v:6283$1955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [13:9] + connect \B 4'1111 + connect \Y $eq$ls180.v:6283$1955_Y + end + attribute \src "ls180.v:6285.102-6285.147" + cell $eq $eq$ls180.v:6285$1957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6285$1957_Y + end + attribute \src "ls180.v:6286.105-6286.150" + cell $eq $eq$ls180.v:6286$1961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6286$1961_Y + end + attribute \src "ls180.v:6288.102-6288.147" + cell $eq $eq$ls180.v:6288$1964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6288$1964_Y + end + attribute \src "ls180.v:6289.105-6289.150" + cell $eq $eq$ls180.v:6289$1968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6289$1968_Y + end + attribute \src "ls180.v:6291.100-6291.145" + cell $eq $eq$ls180.v:6291$1971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6291$1971_Y + end + attribute \src "ls180.v:6292.103-6292.148" + cell $eq $eq$ls180.v:6292$1975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6292$1975_Y + end + attribute \src "ls180.v:6294.99-6294.144" + cell $eq $eq$ls180.v:6294$1978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6294$1978_Y + end + attribute \src "ls180.v:6295.102-6295.147" + cell $eq $eq$ls180.v:6295$1982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6295$1982_Y + end + attribute \src "ls180.v:6297.98-6297.143" + cell $eq $eq$ls180.v:6297$1985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6297$1985_Y + end + attribute \src "ls180.v:6298.101-6298.146" + cell $eq $eq$ls180.v:6298$1989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6298$1989_Y + end + attribute \src "ls180.v:6300.97-6300.142" + cell $eq $eq$ls180.v:6300$1992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6300$1992_Y + end + attribute \src "ls180.v:6301.100-6301.145" + cell $eq $eq$ls180.v:6301$1996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6301$1996_Y + end + attribute \src "ls180.v:6303.103-6303.148" + cell $eq $eq$ls180.v:6303$1999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6303$1999_Y + end + attribute \src "ls180.v:6304.106-6304.151" + cell $eq $eq$ls180.v:6304$2003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6304$2003_Y + end + attribute \src "ls180.v:6306.106-6306.151" + cell $eq $eq$ls180.v:6306$2006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6306$2006_Y + end + attribute \src "ls180.v:6307.109-6307.154" + cell $eq $eq$ls180.v:6307$2010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6307$2010_Y + end + attribute \src "ls180.v:6309.106-6309.151" + cell $eq $eq$ls180.v:6309$2013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6309$2013_Y + end + attribute \src "ls180.v:6310.109-6310.154" + cell $eq $eq$ls180.v:6310$2017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6310$2017_Y + end + attribute \src "ls180.v:6331.33-6331.79" + cell $eq $eq$ls180.v:6331$2020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [13:9] + connect \B 2'10 + connect \Y $eq$ls180.v:6331$2020_Y + end + attribute \src "ls180.v:6333.99-6333.144" + cell $eq $eq$ls180.v:6333$2022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6333$2022_Y + end + attribute \src "ls180.v:6334.102-6334.147" + cell $eq $eq$ls180.v:6334$2026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6334$2026_Y + end + attribute \src "ls180.v:6336.99-6336.144" + cell $eq $eq$ls180.v:6336$2029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6336$2029_Y + end + attribute \src "ls180.v:6337.102-6337.147" + cell $eq $eq$ls180.v:6337$2033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6337$2033_Y + end + attribute \src "ls180.v:6339.99-6339.144" + cell $eq $eq$ls180.v:6339$2036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6339$2036_Y + end + attribute \src "ls180.v:6340.102-6340.147" + cell $eq $eq$ls180.v:6340$2040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6340$2040_Y + end + attribute \src "ls180.v:6342.99-6342.144" + cell $eq $eq$ls180.v:6342$2043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6342$2043_Y + end + attribute \src "ls180.v:6343.102-6343.147" + cell $eq $eq$ls180.v:6343$2047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6343$2047_Y + end + attribute \src "ls180.v:6345.101-6345.146" + cell $eq $eq$ls180.v:6345$2050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6345$2050_Y + end + attribute \src "ls180.v:6346.104-6346.149" + cell $eq $eq$ls180.v:6346$2054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6346$2054_Y + end + attribute \src "ls180.v:6348.101-6348.146" + cell $eq $eq$ls180.v:6348$2057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6348$2057_Y + end + attribute \src "ls180.v:6349.104-6349.149" + cell $eq $eq$ls180.v:6349$2061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6349$2061_Y + end + attribute \src "ls180.v:6351.101-6351.146" + cell $eq $eq$ls180.v:6351$2064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6351$2064_Y + end + attribute \src "ls180.v:6352.104-6352.149" + cell $eq $eq$ls180.v:6352$2068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6352$2068_Y + end + attribute \src "ls180.v:6354.101-6354.146" + cell $eq $eq$ls180.v:6354$2071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6354$2071_Y + end + attribute \src "ls180.v:6355.104-6355.149" + cell $eq $eq$ls180.v:6355$2075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6355$2075_Y + end + attribute \src "ls180.v:6357.97-6357.142" + cell $eq $eq$ls180.v:6357$2078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6357$2078_Y + end + attribute \src "ls180.v:6358.100-6358.145" + cell $eq $eq$ls180.v:6358$2082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6358$2082_Y + end + attribute \src "ls180.v:6360.107-6360.152" + cell $eq $eq$ls180.v:6360$2085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6360$2085_Y + end + attribute \src "ls180.v:6361.110-6361.155" + cell $eq $eq$ls180.v:6361$2089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6361$2089_Y + end + attribute \src "ls180.v:6363.100-6363.146" + cell $eq $eq$ls180.v:6363$2092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6363$2092_Y + end + attribute \src "ls180.v:6364.103-6364.149" + cell $eq $eq$ls180.v:6364$2096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6364$2096_Y + end + attribute \src "ls180.v:6366.100-6366.146" + cell $eq $eq$ls180.v:6366$2099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6366$2099_Y + end + attribute \src "ls180.v:6367.103-6367.149" + cell $eq $eq$ls180.v:6367$2103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6367$2103_Y + end + attribute \src "ls180.v:6369.100-6369.146" + cell $eq $eq$ls180.v:6369$2106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6369$2106_Y + end + attribute \src "ls180.v:6370.103-6370.149" + cell $eq $eq$ls180.v:6370$2110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6370$2110_Y + end + attribute \src "ls180.v:6372.100-6372.146" + cell $eq $eq$ls180.v:6372$2113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6372$2113_Y + end + attribute \src "ls180.v:6373.103-6373.149" + cell $eq $eq$ls180.v:6373$2117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6373$2117_Y + end + attribute \src "ls180.v:6375.112-6375.158" + cell $eq $eq$ls180.v:6375$2120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6375$2120_Y + end + attribute \src "ls180.v:6376.115-6376.161" + cell $eq $eq$ls180.v:6376$2124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6376$2124_Y + end + attribute \src "ls180.v:6378.113-6378.159" + cell $eq $eq$ls180.v:6378$2127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6378$2127_Y + end + attribute \src "ls180.v:6379.116-6379.162" + cell $eq $eq$ls180.v:6379$2131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6379$2131_Y + end + attribute \src "ls180.v:6381.104-6381.150" + cell $eq $eq$ls180.v:6381$2134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6381$2134_Y + end + attribute \src "ls180.v:6382.107-6382.153" + cell $eq $eq$ls180.v:6382$2138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6382$2138_Y + end + attribute \src "ls180.v:6399.33-6399.79" + cell $eq $eq$ls180.v:6399$2140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [13:9] + connect \B 3'101 + connect \Y $eq$ls180.v:6399$2140_Y + end + attribute \src "ls180.v:6401.90-6401.135" + cell $eq $eq$ls180.v:6401$2142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6401$2142_Y + end + attribute \src "ls180.v:6402.93-6402.138" + cell $eq $eq$ls180.v:6402$2146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6402$2146_Y + end + attribute \src "ls180.v:6404.100-6404.145" + cell $eq $eq$ls180.v:6404$2149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6404$2149_Y + end + attribute \src "ls180.v:6405.103-6405.148" + cell $eq $eq$ls180.v:6405$2153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6405$2153_Y + end + attribute \src "ls180.v:6407.101-6407.146" + cell $eq $eq$ls180.v:6407$2156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6407$2156_Y + end + attribute \src "ls180.v:6408.104-6408.149" + cell $eq $eq$ls180.v:6408$2160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6408$2160_Y + end + attribute \src "ls180.v:6410.105-6410.150" + cell $eq $eq$ls180.v:6410$2163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6410$2163_Y + end + attribute \src "ls180.v:6411.108-6411.153" + cell $eq $eq$ls180.v:6411$2167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6411$2167_Y + end + attribute \src "ls180.v:6413.106-6413.151" + cell $eq $eq$ls180.v:6413$2170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6413$2170_Y + end + attribute \src "ls180.v:6414.109-6414.154" + cell $eq $eq$ls180.v:6414$2174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6414$2174_Y + end + attribute \src "ls180.v:6416.104-6416.149" + cell $eq $eq$ls180.v:6416$2177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6416$2177_Y + end + attribute \src "ls180.v:6417.107-6417.152" + cell $eq $eq$ls180.v:6417$2181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6417$2181_Y + end + attribute \src "ls180.v:6419.101-6419.146" + cell $eq $eq$ls180.v:6419$2184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6419$2184_Y + end + attribute \src "ls180.v:6420.104-6420.149" + cell $eq $eq$ls180.v:6420$2188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6420$2188_Y + end + attribute \src "ls180.v:6422.100-6422.145" + cell $eq $eq$ls180.v:6422$2191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6422$2191_Y + end + attribute \src "ls180.v:6423.103-6423.148" + cell $eq $eq$ls180.v:6423$2195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6423$2195_Y + end + attribute \src "ls180.v:6433.33-6433.79" + cell $eq $eq$ls180.v:6433$2197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [13:9] + connect \B 3'100 + connect \Y $eq$ls180.v:6433$2197_Y + end + attribute \src "ls180.v:6435.106-6435.151" + cell $eq $eq$ls180.v:6435$2199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6435$2199_Y + end + attribute \src "ls180.v:6436.109-6436.154" + cell $eq $eq$ls180.v:6436$2203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6436$2203_Y + end + attribute \src "ls180.v:6438.106-6438.151" + cell $eq $eq$ls180.v:6438$2206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6438$2206_Y + end + attribute \src "ls180.v:6439.109-6439.154" + cell $eq $eq$ls180.v:6439$2210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6439$2210_Y + end + attribute \src "ls180.v:6441.106-6441.151" + cell $eq $eq$ls180.v:6441$2213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6441$2213_Y + end + attribute \src "ls180.v:6442.109-6442.154" + cell $eq $eq$ls180.v:6442$2217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6442$2217_Y + end + attribute \src "ls180.v:6444.106-6444.151" + cell $eq $eq$ls180.v:6444$2220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6444$2220_Y + end + attribute \src "ls180.v:6445.109-6445.154" + cell $eq $eq$ls180.v:6445$2224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6445$2224_Y + end + attribute \src "ls180.v:6826.41-6826.81" + cell $eq $eq$ls180.v:6826$2261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:6826$2261_Y + end + attribute \src "ls180.v:6826.144-6826.177" + cell $eq $eq$ls180.v:6826$2262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6826$2262_Y + end + attribute \src "ls180.v:6826.219-6826.252" + cell $eq $eq$ls180.v:6826$2265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6826$2265_Y + end + attribute \src "ls180.v:6826.294-6826.327" + cell $eq $eq$ls180.v:6826$2268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6826$2268_Y + end + attribute \src "ls180.v:6850.41-6850.81" + cell $eq $eq$ls180.v:6850$2277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:6850$2277_Y + end + attribute \src "ls180.v:6850.144-6850.177" + cell $eq $eq$ls180.v:6850$2278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6850$2278_Y + end + attribute \src "ls180.v:6850.219-6850.252" + cell $eq $eq$ls180.v:6850$2281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6850$2281_Y + end + attribute \src "ls180.v:6850.294-6850.327" + cell $eq $eq$ls180.v:6850$2284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6850$2284_Y + end + attribute \src "ls180.v:6874.41-6874.81" + cell $eq $eq$ls180.v:6874$2293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:6874$2293_Y + end + attribute \src "ls180.v:6874.144-6874.177" + cell $eq $eq$ls180.v:6874$2294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6874$2294_Y + end + attribute \src "ls180.v:6874.219-6874.252" + cell $eq $eq$ls180.v:6874$2297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6874$2297_Y + end + attribute \src "ls180.v:6874.294-6874.327" + cell $eq $eq$ls180.v:6874$2300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6874$2300_Y + end + attribute \src "ls180.v:6898.41-6898.81" + cell $eq $eq$ls180.v:6898$2309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:6898$2309_Y + end + attribute \src "ls180.v:6898.144-6898.177" + cell $eq $eq$ls180.v:6898$2310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6898$2310_Y + end + attribute \src "ls180.v:6898.219-6898.252" + cell $eq $eq$ls180.v:6898$2313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6898$2313_Y + end + attribute \src "ls180.v:6898.294-6898.327" + cell $eq $eq$ls180.v:6898$2316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6898$2316_Y + end + attribute \src "ls180.v:7491.8-7491.38" + cell $eq $eq$ls180.v:7491$2419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_value + connect \B 1'0 + connect \Y $eq$ls180.v:7491$2419_Y + end + attribute \src "ls180.v:7522.8-7522.42" + cell $eq $eq$ls180.v:7522$2427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_postponer_count + connect \B 1'0 + connect \Y $eq$ls180.v:7522$2427_Y + end + attribute \src "ls180.v:7542.38-7542.74" + cell $eq $eq$ls180.v:7542$2430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 1'0 + connect \Y $eq$ls180.v:7542$2430_Y + end + attribute \src "ls180.v:7549.7-7549.43" + cell $eq $eq$ls180.v:7549$2432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 2'10 + connect \Y $eq$ls180.v:7549$2432_Y + end + attribute \src "ls180.v:7556.7-7556.43" + cell $eq $eq$ls180.v:7556$2433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$ls180.v:7556$2433_Y + end + attribute \src "ls180.v:7564.7-7564.43" + cell $eq $eq$ls180.v:7564$2434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$ls180.v:7564$2434_Y + end + attribute \src "ls180.v:7616.9-7616.54" + cell $eq $eq$ls180.v:7616$2452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7616$2452_Y + end + attribute \src "ls180.v:7662.9-7662.54" + cell $eq $eq$ls180.v:7662$2468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7662$2468_Y + end + attribute \src "ls180.v:7708.9-7708.54" + cell $eq $eq$ls180.v:7708$2484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7708$2484_Y + end + attribute \src "ls180.v:7754.9-7754.54" + cell $eq $eq$ls180.v:7754$2500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7754$2500_Y + end + attribute \src "ls180.v:7904.9-7904.41" + cell $eq $eq$ls180.v:7904$2512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7904$2512_Y + end + attribute \src "ls180.v:7919.9-7919.41" + cell $eq $eq$ls180.v:7919$2515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_twtrcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7919$2515_Y + end + attribute \src "ls180.v:7925.49-7925.82" + cell $eq $eq$ls180.v:7925$2516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7925$2516_Y + end + attribute \src "ls180.v:7925.131-7925.164" + cell $eq $eq$ls180.v:7925$2519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7925$2519_Y + end + attribute \src "ls180.v:7925.213-7925.246" + cell $eq $eq$ls180.v:7925$2522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7925$2522_Y + end + attribute \src "ls180.v:7925.295-7925.328" + cell $eq $eq$ls180.v:7925$2525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7925$2525_Y + end + attribute \src "ls180.v:7926.50-7926.83" + cell $eq $eq$ls180.v:7926$2528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7926$2528_Y + end + attribute \src "ls180.v:7926.132-7926.165" + cell $eq $eq$ls180.v:7926$2531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7926$2531_Y + end + attribute \src "ls180.v:7926.214-7926.247" + cell $eq $eq$ls180.v:7926$2534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7926$2534_Y + end + attribute \src "ls180.v:7926.296-7926.329" + cell $eq $eq$ls180.v:7926$2537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7926$2537_Y + end + attribute \src "ls180.v:7961.9-7961.42" + cell $eq $eq$ls180.v:7961$2549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_tx_bitcount + connect \B 4'1000 + connect \Y $eq$ls180.v:7961$2549_Y + end + attribute \src "ls180.v:7964.10-7964.43" + cell $eq $eq$ls180.v:7964$2550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_tx_bitcount + connect \B 4'1001 + connect \Y $eq$ls180.v:7964$2550_Y + end + attribute \src "ls180.v:7990.9-7990.42" + cell $eq $eq$ls180.v:7990$2556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx_bitcount + connect \B 1'0 + connect \Y $eq$ls180.v:7990$2556_Y + end + attribute \src "ls180.v:7995.10-7995.43" + cell $eq $eq$ls180.v:7995$2557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx_bitcount + connect \B 4'1001 + connect \Y $eq$ls180.v:7995$2557_Y + end + attribute \src "ls180.v:8167.9-8167.53" + cell $eq $eq$ls180.v:8167$2601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 3'111 + connect \Y $eq$ls180.v:8167$2601_Y + end + attribute \src "ls180.v:8248.9-8248.54" + cell $eq $eq$ls180.v:8248$2613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 3'111 + connect \Y $eq$ls180.v:8248$2613_Y + end + attribute \src "ls180.v:8327.9-8327.55" + cell $eq $eq$ls180.v:8327$2625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $eq$ls180.v:8327$2625_Y + end + attribute \src "ls180.v:8550.9-8550.49" + cell $eq $eq$ls180.v:8550$2658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_demux + connect \B 2'11 + connect \Y $eq$ls180.v:8550$2658_Y + end + attribute \src "ls180.v:8126.8-8126.54" + cell $ge $ge$ls180.v:8126$2593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm0_counter + connect \B $sub$ls180.v:8126$2592_Y + connect \Y $ge$ls180.v:8126$2593_Y + end + attribute \src "ls180.v:8140.8-8140.54" + cell $ge $ge$ls180.v:8140$2597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm1_counter + connect \B $sub$ls180.v:8140$2596_Y + connect \Y $ge$ls180.v:8140$2597_Y + end + attribute \src "ls180.v:5076.47-5076.83" + cell $gt $gt$ls180.v:5076$906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $gt$ls180.v:5076$906_Y + end + attribute \src "ls180.v:5082.7-5082.43" + cell $lt $lt$ls180.v:5082$909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 4'1000 + connect \Y $lt$ls180.v:5082$909_Y + end + attribute \src "ls180.v:8121.8-8121.43" + cell $lt $lt$ls180.v:8121$2591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm0_counter + connect \B \main_pwm0_width + connect \Y $lt$ls180.v:8121$2591_Y + end + attribute \src "ls180.v:8135.8-8135.43" + cell $lt $lt$ls180.v:8135$2595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm1_counter + connect \B \main_pwm1_width + connect \Y $lt$ls180.v:8135$2595_Y + end + attribute \src "ls180.v:10052.33-10052.36" + cell $memrd $memrd$\mem$ls180.v:10052$2705 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \TRANSPARENT 0 + parameter \WIDTH 32 + connect \ADDR \memadr + connect \CLK 1'x + connect \DATA $memrd$\mem$ls180.v:10052$2705_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10063.12-10063.19" + cell $memrd $memrd$\storage$ls180.v:10063$2710 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$ls180.v:10063$2710_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10070.68-10070.75" + cell $memrd $memrd$\storage$ls180.v:10070$2712 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$ls180.v:10070$2712_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10077.14-10077.23" + cell $memrd $memrd$\storage_1$ls180.v:10077$2717 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$ls180.v:10077$2717_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10084.68-10084.77" + cell $memrd $memrd$\storage_1$ls180.v:10084$2719 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$ls180.v:10084$2719_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10091.14-10091.23" + cell $memrd $memrd$\storage_2$ls180.v:10091$2724 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$ls180.v:10091$2724_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10098.68-10098.77" + cell $memrd $memrd$\storage_2$ls180.v:10098$2726 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$ls180.v:10098$2726_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10105.14-10105.23" + cell $memrd $memrd$\storage_3$ls180.v:10105$2731 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$ls180.v:10105$2731_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10112.68-10112.77" + cell $memrd $memrd$\storage_3$ls180.v:10112$2733 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$ls180.v:10112$2733_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10120.14-10120.23" + cell $memrd $memrd$\storage_4$ls180.v:10120$2738 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_tx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$ls180.v:10120$2738_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10125.15-10125.24" + cell $memrd $memrd$\storage_4$ls180.v:10125$2740 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_tx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$ls180.v:10125$2740_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10137.14-10137.23" + cell $memrd $memrd$\storage_5$ls180.v:10137$2745 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_rx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$ls180.v:10137$2745_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10142.15-10142.24" + cell $memrd $memrd$\storage_5$ls180.v:10142$2747 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_rx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$ls180.v:10142$2747_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10153.14-10153.23" + cell $memrd $memrd$\storage_6$ls180.v:10153$2752 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdblock2mem_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_6$ls180.v:10153$2752_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10160.45-10160.54" + cell $memrd $memrd$\storage_6$ls180.v:10160$2754 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdblock2mem_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_6$ls180.v:10160$2754_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10167.14-10167.23" + cell $memrd $memrd$\storage_7$ls180.v:10167$2759 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdmem2block_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_7$ls180.v:10167$2759_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10174.45-10174.54" + cell $memrd $memrd$\storage_7$ls180.v:10174$2761 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdmem2block_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_7$ls180.v:10174$2761_DATA + connect \EN 1'x + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2763 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2763 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$ls180.v:10042$1_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10042$1_DATA + connect \EN $memwr$\mem$ls180.v:10042$1_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2764 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2764 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$ls180.v:10044$2_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10044$2_DATA + connect \EN $memwr$\mem$ls180.v:10044$2_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2765 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2765 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$ls180.v:10046$3_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10046$3_DATA + connect \EN $memwr$\mem$ls180.v:10046$3_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2766 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2766 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$ls180.v:10048$4_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10048$4_DATA + connect \EN $memwr$\mem$ls180.v:10048$4_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage$ls180.v:0$2767 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \PRIORITY 2767 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage$ls180.v:10062$5_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage$ls180.v:10062$5_DATA + connect \EN $memwr$\storage$ls180.v:10062$5_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_1$ls180.v:0$2768 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \PRIORITY 2768 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_1$ls180.v:10076$6_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_1$ls180.v:10076$6_DATA + connect \EN $memwr$\storage_1$ls180.v:10076$6_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_2$ls180.v:0$2769 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \PRIORITY 2769 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_2$ls180.v:10090$7_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_2$ls180.v:10090$7_DATA + connect \EN $memwr$\storage_2$ls180.v:10090$7_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_3$ls180.v:0$2770 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \PRIORITY 2770 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_3$ls180.v:10104$8_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_3$ls180.v:10104$8_DATA + connect \EN $memwr$\storage_3$ls180.v:10104$8_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_4$ls180.v:0$2771 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \PRIORITY 2771 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_4$ls180.v:10119$9_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_4$ls180.v:10119$9_DATA + connect \EN $memwr$\storage_4$ls180.v:10119$9_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_5$ls180.v:0$2772 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \PRIORITY 2772 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_5$ls180.v:10136$10_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_5$ls180.v:10136$10_DATA + connect \EN $memwr$\storage_5$ls180.v:10136$10_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_6$ls180.v:0$2773 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \PRIORITY 2773 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_6$ls180.v:10152$11_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_6$ls180.v:10152$11_DATA + connect \EN $memwr$\storage_6$ls180.v:10152$11_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_7$ls180.v:0$2774 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \PRIORITY 2774 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_7$ls180.v:10166$12_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_7$ls180.v:10166$12_DATA + connect \EN $memwr$\storage_7$ls180.v:10166$12_EN + end + attribute \src "ls180.v:2949.41-2949.71" + cell $ne $ne$ls180.v:2949$60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_value + connect \B 1'0 + connect \Y $ne$ls180.v:2949$60_Y + end + attribute \src "ls180.v:3110.70-3110.104" + cell $ne $ne$ls180.v:3110$74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$ls180.v:3110$74_Y + end + attribute \src "ls180.v:3171.8-3171.142" + cell $ne $ne$ls180.v:3171$93 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3171$93_Y + end + attribute \src "ls180.v:3203.75-3203.133" + cell $ne $ne$ls180.v:3203$100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3203$100_Y + end + attribute \src "ls180.v:3204.75-3204.133" + cell $ne $ne$ls180.v:3204$101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3204$101_Y + end + attribute \src "ls180.v:3328.8-3328.142" + cell $ne $ne$ls180.v:3328$123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3328$123_Y + end + attribute \src "ls180.v:3360.75-3360.133" + cell $ne $ne$ls180.v:3360$130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3360$130_Y + end + attribute \src "ls180.v:3361.75-3361.133" + cell $ne $ne$ls180.v:3361$131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3361$131_Y + end + attribute \src "ls180.v:3485.8-3485.142" + cell $ne $ne$ls180.v:3485$153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3485$153_Y + end + attribute \src "ls180.v:3517.75-3517.133" + cell $ne $ne$ls180.v:3517$160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3517$160_Y + end + attribute \src "ls180.v:3518.75-3518.133" + cell $ne $ne$ls180.v:3518$161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3518$161_Y + end + attribute \src "ls180.v:3642.8-3642.142" + cell $ne $ne$ls180.v:3642$183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3642$183_Y + end + attribute \src "ls180.v:3674.75-3674.133" + cell $ne $ne$ls180.v:3674$190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3674$190_Y + end + attribute \src "ls180.v:3675.75-3675.133" + cell $ne $ne$ls180.v:3675$191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3675$191_Y + end + attribute \src "ls180.v:4167.47-4167.80" + cell $ne $ne$ls180.v:4167$589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$ls180.v:4167$589_Y + end + attribute \src "ls180.v:4168.47-4168.79" + cell $ne $ne$ls180.v:4168$590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'0 + connect \Y $ne$ls180.v:4168$590_Y + end + attribute \src "ls180.v:4197.47-4197.80" + cell $ne $ne$ls180.v:4197$600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$ls180.v:4197$600_Y + end + attribute \src "ls180.v:4198.47-4198.79" + cell $ne $ne$ls180.v:4198$601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'0 + connect \Y $ne$ls180.v:4198$601_Y + end + attribute \src "ls180.v:4608.32-4608.89" + cell $ne $ne$ls180.v:4608$673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 + connect \B 3'101 + connect \Y $ne$ls180.v:4608$673_Y + end + attribute \src "ls180.v:5255.10-5255.56" + cell $ne $ne$ls180.v:5255$970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 2'10 + connect \Y $ne$ls180.v:5255$970_Y + end + attribute \src "ls180.v:5360.51-5360.87" + cell $ne $ne$ls180.v:5360$984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_level + connect \B 6'100000 + connect \Y $ne$ls180.v:5360$984_Y + end + attribute \src "ls180.v:5361.51-5361.86" + cell $ne $ne$ls180.v:5361$985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'0 + connect \Y $ne$ls180.v:5361$985_Y + end + attribute \src "ls180.v:5568.51-5568.87" + cell $ne $ne$ls180.v:5568$1015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_level + connect \B 6'100000 + connect \Y $ne$ls180.v:5568$1015_Y + end + attribute \src "ls180.v:5569.51-5569.86" + cell $ne $ne$ls180.v:5569$1016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_level + connect \B 1'0 + connect \Y $ne$ls180.v:5569$1016_Y + end + attribute \src "ls180.v:5659.79-5659.119" + cell $ne $ne$ls180.v:5659$1027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_sel + connect \B 1'0 + connect \Y $ne$ls180.v:5659$1027_Y + end + attribute \src "ls180.v:7481.7-7481.52" + cell $ne $ne$ls180.v:7481$2414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_bus_errors + connect \B 32'11111111111111111111111111111111 + connect \Y $ne$ls180.v:7481$2414_Y + end + attribute \src "ls180.v:7531.9-7531.43" + cell $ne $ne$ls180.v:7531$2428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$ls180.v:7531$2428_Y + end + attribute \src "ls180.v:7567.8-7567.44" + cell $ne $ne$ls180.v:7567$2435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 1'0 + connect \Y $ne$ls180.v:7567$2435_Y + end + attribute \src "ls180.v:8470.9-8470.47" + cell $ne $ne$ls180.v:8470$2645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 4'1010 + connect \Y $ne$ls180.v:8470$2645_Y + end + attribute \src "ls180.v:2757.45-2757.80" + cell $not $not$ls180.v:2757$14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_ibus_cyc + connect \Y $not$ls180.v:2757$14_Y + end + attribute \src "ls180.v:2796.61-2796.94" + cell $not $not$ls180.v:2796$19 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_skip + connect \Y $not$ls180.v:2796$19_Y + end + attribute \src "ls180.v:2797.61-2797.94" + cell $not $not$ls180.v:2797$20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_skip + connect \Y $not$ls180.v:2797$20_Y + end + attribute \src "ls180.v:2817.45-2817.80" + cell $not $not$ls180.v:2817$25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_dbus_cyc + connect \Y $not$ls180.v:2817$25_Y + end + attribute \src "ls180.v:2856.61-2856.94" + cell $not $not$ls180.v:2856$30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_skip + connect \Y $not$ls180.v:2856$30_Y + end + attribute \src "ls180.v:2857.61-2857.94" + cell $not $not$ls180.v:2857$31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_skip + connect \Y $not$ls180.v:2857$31_Y + end + attribute \src "ls180.v:2877.45-2877.83" + cell $not $not$ls180.v:2877$36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_jtag_wb_cyc + connect \Y $not$ls180.v:2877$36_Y + end + attribute \src "ls180.v:2916.61-2916.94" + cell $not $not$ls180.v:2916$41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter2_skip + connect \Y $not$ls180.v:2916$41_Y + end + attribute \src "ls180.v:2917.61-2917.94" + cell $not $not$ls180.v:2917$42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter2_skip + connect \Y $not$ls180.v:2917$42_Y + end + attribute \src "ls180.v:3059.34-3059.64" + cell $not $not$ls180.v:3059$66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [0] + connect \Y $not$ls180.v:3059$66_Y + end + attribute \src "ls180.v:3060.31-3060.61" + cell $not $not$ls180.v:3060$67 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [1] + connect \Y $not$ls180.v:3060$67_Y + end + attribute \src "ls180.v:3061.32-3061.62" + cell $not $not$ls180.v:3061$68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [2] + connect \Y $not$ls180.v:3061$68_Y + end + attribute \src "ls180.v:3062.32-3062.62" + cell $not $not$ls180.v:3062$69 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [3] + connect \Y $not$ls180.v:3062$69_Y + end + attribute \src "ls180.v:3104.33-3104.56" + cell $not $not$ls180.v:3104$72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_done0 + connect \Y $not$ls180.v:3104$72_Y + end + attribute \src "ls180.v:3205.58-3205.106" + cell $not $not$ls180.v:3205$102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$ls180.v:3205$102_Y + end + attribute \src "ls180.v:3259.9-3259.45" + cell $not $not$ls180.v:3259$107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_refresh_req + connect \Y $not$ls180.v:3259$107_Y + end + attribute \src "ls180.v:3362.58-3362.106" + cell $not $not$ls180.v:3362$132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$ls180.v:3362$132_Y + end + attribute \src "ls180.v:3416.9-3416.45" + cell $not $not$ls180.v:3416$137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_refresh_req + connect \Y $not$ls180.v:3416$137_Y + end + attribute \src "ls180.v:3519.58-3519.106" + cell $not $not$ls180.v:3519$162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$ls180.v:3519$162_Y + end + attribute \src "ls180.v:3573.9-3573.45" + cell $not $not$ls180.v:3573$167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_refresh_req + connect \Y $not$ls180.v:3573$167_Y + end + attribute \src "ls180.v:3676.58-3676.106" + cell $not $not$ls180.v:3676$192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$ls180.v:3676$192_Y + end + attribute \src "ls180.v:3730.9-3730.45" + cell $not $not$ls180.v:3730$197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_refresh_req + connect \Y $not$ls180.v:3730$197_Y + end + attribute \src "ls180.v:3772.149-3772.187" + cell $not $not$ls180.v:3772$200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3772$200_Y + end + attribute \src "ls180.v:3772.193-3772.230" + cell $not $not$ls180.v:3772$202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3772$202_Y + end + attribute \src "ls180.v:3773.149-3773.187" + cell $not $not$ls180.v:3773$206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3773$206_Y + end + attribute \src "ls180.v:3773.193-3773.230" + cell $not $not$ls180.v:3773$208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3773$208_Y + end + attribute \src "ls180.v:3789.43-3789.73" + cell $not $not$ls180.v:3789$236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \main_sdram_interface_wdata_we + connect \Y $not$ls180.v:3789$236_Y + end + attribute \src "ls180.v:3792.205-3792.245" + cell $not $not$ls180.v:3792$239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_cas + connect \Y $not$ls180.v:3792$239_Y + end + attribute \src "ls180.v:3792.251-3792.290" + cell $not $not$ls180.v:3792$241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_we + connect \Y $not$ls180.v:3792$241_Y + end + attribute \src "ls180.v:3792.159-3792.292" + cell $not $not$ls180.v:3792$243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3792$242_Y + connect \Y $not$ls180.v:3792$243_Y + end + attribute \src "ls180.v:3793.205-3793.245" + cell $not $not$ls180.v:3793$252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_cas + connect \Y $not$ls180.v:3793$252_Y + end + attribute \src "ls180.v:3793.251-3793.290" + cell $not $not$ls180.v:3793$254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_we + connect \Y $not$ls180.v:3793$254_Y + end + attribute \src "ls180.v:3793.159-3793.292" + cell $not $not$ls180.v:3793$256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3793$255_Y + connect \Y $not$ls180.v:3793$256_Y + end + attribute \src "ls180.v:3794.205-3794.245" + cell $not $not$ls180.v:3794$265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_cas + connect \Y $not$ls180.v:3794$265_Y + end + attribute \src "ls180.v:3794.251-3794.290" + cell $not $not$ls180.v:3794$267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_we + connect \Y $not$ls180.v:3794$267_Y + end + attribute \src "ls180.v:3794.159-3794.292" + cell $not $not$ls180.v:3794$269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3794$268_Y + connect \Y $not$ls180.v:3794$269_Y + end + attribute \src "ls180.v:3795.205-3795.245" + cell $not $not$ls180.v:3795$278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_cas + connect \Y $not$ls180.v:3795$278_Y + end + attribute \src "ls180.v:3795.251-3795.290" + cell $not $not$ls180.v:3795$280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_we + connect \Y $not$ls180.v:3795$280_Y + end + attribute \src "ls180.v:3795.159-3795.292" + cell $not $not$ls180.v:3795$282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3795$281_Y + connect \Y $not$ls180.v:3795$282_Y + end + attribute \src "ls180.v:3822.71-3822.103" + cell $not $not$ls180.v:3822$293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \Y $not$ls180.v:3822$293_Y + end + attribute \src "ls180.v:3825.205-3825.245" + cell $not $not$ls180.v:3825$297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_cas + connect \Y $not$ls180.v:3825$297_Y + end + attribute \src "ls180.v:3825.251-3825.290" + cell $not $not$ls180.v:3825$299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_we + connect \Y $not$ls180.v:3825$299_Y + end + attribute \src "ls180.v:3825.159-3825.292" + cell $not $not$ls180.v:3825$301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3825$300_Y + connect \Y $not$ls180.v:3825$301_Y + end + attribute \src "ls180.v:3826.205-3826.245" + cell $not $not$ls180.v:3826$310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_cas + connect \Y $not$ls180.v:3826$310_Y + end + attribute \src "ls180.v:3826.251-3826.290" + cell $not $not$ls180.v:3826$312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_we + connect \Y $not$ls180.v:3826$312_Y + end + attribute \src "ls180.v:3826.159-3826.292" + cell $not $not$ls180.v:3826$314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3826$313_Y + connect \Y $not$ls180.v:3826$314_Y + end + attribute \src "ls180.v:3827.205-3827.245" + cell $not $not$ls180.v:3827$323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_cas + connect \Y $not$ls180.v:3827$323_Y + end + attribute \src "ls180.v:3827.251-3827.290" + cell $not $not$ls180.v:3827$325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_we + connect \Y $not$ls180.v:3827$325_Y + end + attribute \src "ls180.v:3827.159-3827.292" + cell $not $not$ls180.v:3827$327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3827$326_Y + connect \Y $not$ls180.v:3827$327_Y + end + attribute \src "ls180.v:3828.205-3828.245" + cell $not $not$ls180.v:3828$336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_cas + connect \Y $not$ls180.v:3828$336_Y + end + attribute \src "ls180.v:3828.251-3828.290" + cell $not $not$ls180.v:3828$338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_we + connect \Y $not$ls180.v:3828$338_Y + end + attribute \src "ls180.v:3828.159-3828.292" + cell $not $not$ls180.v:3828$340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3828$339_Y + connect \Y $not$ls180.v:3828$340_Y + end + attribute \src "ls180.v:3891.71-3891.103" + cell $not $not$ls180.v:3891$379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \Y $not$ls180.v:3891$379_Y + end + attribute \src "ls180.v:3912.112-3912.150" + cell $not $not$ls180.v:3912$382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3912$382_Y + end + attribute \src "ls180.v:3912.156-3912.193" + cell $not $not$ls180.v:3912$384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3912$384_Y + end + attribute \src "ls180.v:3912.68-3912.195" + cell $not $not$ls180.v:3912$386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3912$385_Y + connect \Y $not$ls180.v:3912$386_Y + end + attribute \src "ls180.v:3920.11-3920.38" + cell $not $not$ls180.v:3920$389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_write_available + connect \Y $not$ls180.v:3920$389_Y + end + attribute \src "ls180.v:3950.112-3950.150" + cell $not $not$ls180.v:3950$391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3950$391_Y + end + attribute \src "ls180.v:3950.156-3950.193" + cell $not $not$ls180.v:3950$393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3950$393_Y + end + attribute \src "ls180.v:3950.68-3950.195" + cell $not $not$ls180.v:3950$395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3950$394_Y + connect \Y $not$ls180.v:3950$395_Y + end + attribute \src "ls180.v:3958.11-3958.37" + cell $not $not$ls180.v:3958$398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_read_available + connect \Y $not$ls180.v:3958$398_Y + end + attribute \src "ls180.v:3968.87-3968.331" + cell $not $not$ls180.v:3968$410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3968$409_Y + connect \Y $not$ls180.v:3968$410_Y + end + attribute \src "ls180.v:3969.35-3969.68" + cell $not $not$ls180.v:3969$413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_valid + connect \Y $not$ls180.v:3969$413_Y + end + attribute \src "ls180.v:3969.73-3969.105" + cell $not $not$ls180.v:3969$414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \Y $not$ls180.v:3969$414_Y + end + attribute \src "ls180.v:3973.87-3973.331" + cell $not $not$ls180.v:3973$426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3973$425_Y + connect \Y $not$ls180.v:3973$426_Y + end + attribute \src "ls180.v:3974.35-3974.68" + cell $not $not$ls180.v:3974$429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_valid + connect \Y $not$ls180.v:3974$429_Y + end + attribute \src "ls180.v:3974.73-3974.105" + cell $not $not$ls180.v:3974$430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \Y $not$ls180.v:3974$430_Y + end + attribute \src "ls180.v:3978.87-3978.331" + cell $not $not$ls180.v:3978$442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3978$441_Y + connect \Y $not$ls180.v:3978$442_Y + end + attribute \src "ls180.v:3979.35-3979.68" + cell $not $not$ls180.v:3979$445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_valid + connect \Y $not$ls180.v:3979$445_Y + end + attribute \src "ls180.v:3979.73-3979.105" + cell $not $not$ls180.v:3979$446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \Y $not$ls180.v:3979$446_Y + end + attribute \src "ls180.v:3983.87-3983.331" + cell $not $not$ls180.v:3983$458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3983$457_Y + connect \Y $not$ls180.v:3983$458_Y + end + attribute \src "ls180.v:3984.35-3984.68" + cell $not $not$ls180.v:3984$461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_valid + connect \Y $not$ls180.v:3984$461_Y + end + attribute \src "ls180.v:3984.73-3984.105" + cell $not $not$ls180.v:3984$462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \Y $not$ls180.v:3984$462_Y + end + attribute \src "ls180.v:3988.128-3988.372" + cell $not $not$ls180.v:3988$475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3988$474_Y + connect \Y $not$ls180.v:3988$475_Y + end + attribute \src "ls180.v:3988.502-3988.746" + cell $not $not$ls180.v:3988$491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3988$490_Y + connect \Y $not$ls180.v:3988$491_Y + end + attribute \src "ls180.v:3988.876-3988.1120" + cell $not $not$ls180.v:3988$507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3988$506_Y + connect \Y $not$ls180.v:3988$507_Y + end + attribute \src "ls180.v:3988.1250-3988.1494" + cell $not $not$ls180.v:3988$523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3988$522_Y + connect \Y $not$ls180.v:3988$523_Y + end + attribute \src "ls180.v:4010.32-4010.50" + cell $not $not$ls180.v:4010$529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_cyc + connect \Y $not$ls180.v:4010$529_Y + end + attribute \src "ls180.v:4049.30-4049.50" + cell $not $not$ls180.v:4049$534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_skip + connect \Y $not$ls180.v:4049$534_Y + end + attribute \src "ls180.v:4050.30-4050.50" + cell $not $not$ls180.v:4050$535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_skip + connect \Y $not$ls180.v:4050$535_Y + end + attribute \src "ls180.v:4075.27-4075.48" + cell $not $not$ls180.v:4075$541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_cyc + connect \Y $not$ls180.v:4075$541_Y + end + attribute \src "ls180.v:4076.30-4076.50" + cell $not $not$ls180.v:4076$542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \Y $not$ls180.v:4076$542_Y + end + attribute \src "ls180.v:4077.80-4077.98" + cell $not $not$ls180.v:4077$544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_cmd_consumed + connect \Y $not$ls180.v:4077$544_Y + end + attribute \src "ls180.v:4078.107-4078.127" + cell $not $not$ls180.v:4078$548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wdata_consumed + connect \Y $not$ls180.v:4078$548_Y + end + attribute \src "ls180.v:4079.78-4079.103" + cell $not $not$ls180.v:4079$551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_we + connect \Y $not$ls180.v:4079$551_Y + end + attribute \src "ls180.v:4080.91-4080.111" + cell $not $not$ls180.v:4080$554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \Y $not$ls180.v:4080$554_Y + end + attribute \src "ls180.v:4096.35-4096.64" + cell $not $not$ls180.v:4096$563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_sink_ready + connect \Y $not$ls180.v:4096$563_Y + end + attribute \src "ls180.v:4097.36-4097.67" + cell $not $not$ls180.v:4097$564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_source_valid + connect \Y $not$ls180.v:4097$564_Y + end + attribute \src "ls180.v:4103.32-4103.61" + cell $not $not$ls180.v:4103$565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_sink_ready + connect \Y $not$ls180.v:4103$565_Y + end + attribute \src "ls180.v:4109.36-4109.67" + cell $not $not$ls180.v:4109$566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_source_valid + connect \Y $not$ls180.v:4109$566_Y + end + attribute \src "ls180.v:4110.35-4110.64" + cell $not $not$ls180.v:4110$567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_sink_ready + connect \Y $not$ls180.v:4110$567_Y + end + attribute \src "ls180.v:4113.32-4113.63" + cell $not $not$ls180.v:4113$570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_source_valid + connect \Y $not$ls180.v:4113$570_Y + end + attribute \src "ls180.v:4151.81-4151.108" + cell $not $not$ls180.v:4151$580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_readable + connect \Y $not$ls180.v:4151$580_Y + end + attribute \src "ls180.v:4181.81-4181.108" + cell $not $not$ls180.v:4181$591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_readable + connect \Y $not$ls180.v:4181$591_Y + end + attribute \src "ls180.v:4322.60-4322.85" + cell $not $not$ls180.v:4322$632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk_d + connect \Y $not$ls180.v:4322$632_Y + end + attribute \src "ls180.v:4463.54-4463.96" + cell $not $not$ls180.v:4463$646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all + connect \Y $not$ls180.v:4463$646_Y + end + attribute \src "ls180.v:4466.48-4466.86" + cell $not $not$ls180.v:4466$649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_buf_source_valid + connect \Y $not$ls180.v:4466$649_Y + end + attribute \src "ls180.v:4590.55-4590.98" + cell $not $not$ls180.v:4590$667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_strobe_all + connect \Y $not$ls180.v:4590$667_Y + end + attribute \src "ls180.v:4593.49-4593.88" + cell $not $not$ls180.v:4593$670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_buf_source_valid + connect \Y $not$ls180.v:4593$670_Y + end + attribute \src "ls180.v:4643.30-4643.58" + cell $not $not$ls180.v:4643$676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \Y $not$ls180.v:4643$676_Y + end + attribute \src "ls180.v:4724.56-4724.100" + cell $not $not$ls180.v:4724$682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_strobe_all + connect \Y $not$ls180.v:4724$682_Y + end + attribute \src "ls180.v:4727.50-4727.90" + cell $not $not$ls180.v:4727$685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_buf_source_valid + connect \Y $not$ls180.v:4727$685_Y + end + attribute \src "ls180.v:4843.42-4843.74" + cell $not $not$ls180.v:4843$701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_valid + connect \Y $not$ls180.v:4843$701_Y + end + attribute \src "ls180.v:5367.50-5367.88" + cell $not $not$ls180.v:5367$986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_strobe_all + connect \Y $not$ls180.v:5367$986_Y + end + attribute \src "ls180.v:5379.52-5379.102" + cell $not $not$ls180.v:5379$989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage + connect \Y $not$ls180.v:5379$989_Y + end + attribute \src "ls180.v:5438.38-5438.74" + cell $not $not$ls180.v:5438$996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_dma_enable_storage + connect \Y $not$ls180.v:5438$996_Y + end + attribute \src "ls180.v:5739.69-5739.88" + cell $not $not$ls180.v:5739$1065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \Y $not$ls180.v:5739$1065_Y + end + attribute \src "ls180.v:5756.63-5756.94" + cell $not $not$ls180.v:5756$1086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5756$1086_Y + end + attribute \src "ls180.v:5759.65-5759.96" + cell $not $not$ls180.v:5759$1093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5759$1093_Y + end + attribute \src "ls180.v:5762.65-5762.96" + cell $not $not$ls180.v:5762$1100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5762$1100_Y + end + attribute \src "ls180.v:5765.65-5765.96" + cell $not $not$ls180.v:5765$1107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5765$1107_Y + end + attribute \src "ls180.v:5768.65-5768.96" + cell $not $not$ls180.v:5768$1114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5768$1114_Y + end + attribute \src "ls180.v:5771.68-5771.99" + cell $not $not$ls180.v:5771$1121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5771$1121_Y + end + attribute \src "ls180.v:5774.68-5774.99" + cell $not $not$ls180.v:5774$1128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5774$1128_Y + end + attribute \src "ls180.v:5777.68-5777.99" + cell $not $not$ls180.v:5777$1135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5777$1135_Y + end + attribute \src "ls180.v:5780.68-5780.99" + cell $not $not$ls180.v:5780$1142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5780$1142_Y + end + attribute \src "ls180.v:5794.60-5794.91" + cell $not $not$ls180.v:5794$1150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5794$1150_Y + end + attribute \src "ls180.v:5797.60-5797.91" + cell $not $not$ls180.v:5797$1157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5797$1157_Y + end + attribute \src "ls180.v:5800.60-5800.91" + cell $not $not$ls180.v:5800$1164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5800$1164_Y + end + attribute \src "ls180.v:5803.60-5803.91" + cell $not $not$ls180.v:5803$1171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5803$1171_Y + end + attribute \src "ls180.v:5806.61-5806.92" + cell $not $not$ls180.v:5806$1178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5806$1178_Y + end + attribute \src "ls180.v:5809.61-5809.92" + cell $not $not$ls180.v:5809$1185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5809$1185_Y + end + attribute \src "ls180.v:5820.59-5820.90" + cell $not $not$ls180.v:5820$1193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5820$1193_Y + end + attribute \src "ls180.v:5823.58-5823.89" + cell $not $not$ls180.v:5823$1200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5823$1200_Y + end + attribute \src "ls180.v:5834.64-5834.95" + cell $not $not$ls180.v:5834$1208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5834$1208_Y + end + attribute \src "ls180.v:5837.63-5837.94" + cell $not $not$ls180.v:5837$1215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5837$1215_Y + end + attribute \src "ls180.v:5840.63-5840.94" + cell $not $not$ls180.v:5840$1222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5840$1222_Y + end + attribute \src "ls180.v:5843.63-5843.94" + cell $not $not$ls180.v:5843$1229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5843$1229_Y + end + attribute \src "ls180.v:5846.63-5846.94" + cell $not $not$ls180.v:5846$1236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5846$1236_Y + end + attribute \src "ls180.v:5849.64-5849.95" + cell $not $not$ls180.v:5849$1243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5849$1243_Y + end + attribute \src "ls180.v:5852.64-5852.95" + cell $not $not$ls180.v:5852$1250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5852$1250_Y + end + attribute \src "ls180.v:5855.64-5855.95" + cell $not $not$ls180.v:5855$1257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5855$1257_Y + end + attribute \src "ls180.v:5858.64-5858.95" + cell $not $not$ls180.v:5858$1264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5858$1264_Y + end + attribute \src "ls180.v:5871.64-5871.95" + cell $not $not$ls180.v:5871$1272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5871$1272_Y + end + attribute \src "ls180.v:5874.63-5874.94" + cell $not $not$ls180.v:5874$1279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5874$1279_Y + end + attribute \src "ls180.v:5877.63-5877.94" + cell $not $not$ls180.v:5877$1286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5877$1286_Y + end + attribute \src "ls180.v:5880.63-5880.94" + cell $not $not$ls180.v:5880$1293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5880$1293_Y + end + attribute \src "ls180.v:5883.63-5883.94" + cell $not $not$ls180.v:5883$1300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5883$1300_Y + end + attribute \src "ls180.v:5886.64-5886.95" + cell $not $not$ls180.v:5886$1307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5886$1307_Y + end + attribute \src "ls180.v:5889.64-5889.95" + cell $not $not$ls180.v:5889$1314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5889$1314_Y + end + attribute \src "ls180.v:5892.64-5892.95" + cell $not $not$ls180.v:5892$1321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5892$1321_Y + end + attribute \src "ls180.v:5895.64-5895.95" + cell $not $not$ls180.v:5895$1328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5895$1328_Y + end + attribute \src "ls180.v:5908.66-5908.97" + cell $not $not$ls180.v:5908$1336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5908$1336_Y + end + attribute \src "ls180.v:5911.66-5911.97" + cell $not $not$ls180.v:5911$1343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5911$1343_Y + end + attribute \src "ls180.v:5914.66-5914.97" + cell $not $not$ls180.v:5914$1350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5914$1350_Y + end + attribute \src "ls180.v:5917.66-5917.97" + cell $not $not$ls180.v:5917$1357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5917$1357_Y + end + attribute \src "ls180.v:5920.66-5920.97" + cell $not $not$ls180.v:5920$1364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5920$1364_Y + end + attribute \src "ls180.v:5923.66-5923.97" + cell $not $not$ls180.v:5923$1371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5923$1371_Y + end + attribute \src "ls180.v:5926.66-5926.97" + cell $not $not$ls180.v:5926$1378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5926$1378_Y + end + attribute \src "ls180.v:5929.66-5929.97" + cell $not $not$ls180.v:5929$1385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5929$1385_Y + end + attribute \src "ls180.v:5932.68-5932.99" + cell $not $not$ls180.v:5932$1392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5932$1392_Y + end + attribute \src "ls180.v:5935.68-5935.99" + cell $not $not$ls180.v:5935$1399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5935$1399_Y + end + attribute \src "ls180.v:5938.68-5938.99" + cell $not $not$ls180.v:5938$1406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5938$1406_Y + end + attribute \src "ls180.v:5941.68-5941.99" + cell $not $not$ls180.v:5941$1413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5941$1413_Y + end + attribute \src "ls180.v:5944.68-5944.99" + cell $not $not$ls180.v:5944$1420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5944$1420_Y + end + attribute \src "ls180.v:5947.65-5947.96" + cell $not $not$ls180.v:5947$1427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5947$1427_Y + end + attribute \src "ls180.v:5950.66-5950.97" + cell $not $not$ls180.v:5950$1434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5950$1434_Y + end + attribute \src "ls180.v:5970.70-5970.101" + cell $not $not$ls180.v:5970$1442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5970$1442_Y + end + attribute \src "ls180.v:5973.70-5973.101" + cell $not $not$ls180.v:5973$1449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5973$1449_Y + end + attribute \src "ls180.v:5976.70-5976.101" + cell $not $not$ls180.v:5976$1456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5976$1456_Y + end + attribute \src "ls180.v:5979.70-5979.101" + cell $not $not$ls180.v:5979$1463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5979$1463_Y + end + attribute \src "ls180.v:5982.69-5982.100" + cell $not $not$ls180.v:5982$1470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5982$1470_Y + end + attribute \src "ls180.v:5985.69-5985.100" + cell $not $not$ls180.v:5985$1477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5985$1477_Y + end + attribute \src "ls180.v:5988.69-5988.100" + cell $not $not$ls180.v:5988$1484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5988$1484_Y + end + attribute \src "ls180.v:5991.69-5991.100" + cell $not $not$ls180.v:5991$1491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5991$1491_Y + end + attribute \src "ls180.v:5994.60-5994.91" + cell $not $not$ls180.v:5994$1498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5994$1498_Y + end + attribute \src "ls180.v:5997.71-5997.102" + cell $not $not$ls180.v:5997$1505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5997$1505_Y + end + attribute \src "ls180.v:6000.71-6000.102" + cell $not $not$ls180.v:6000$1512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6000$1512_Y + end + attribute \src "ls180.v:6003.71-6003.102" + cell $not $not$ls180.v:6003$1519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6003$1519_Y + end + attribute \src "ls180.v:6006.71-6006.102" + cell $not $not$ls180.v:6006$1526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6006$1526_Y + end + attribute \src "ls180.v:6009.71-6009.102" + cell $not $not$ls180.v:6009$1533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6009$1533_Y + end + attribute \src "ls180.v:6012.71-6012.102" + cell $not $not$ls180.v:6012$1540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6012$1540_Y + end + attribute \src "ls180.v:6015.70-6015.101" + cell $not $not$ls180.v:6015$1547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6015$1547_Y + end + attribute \src "ls180.v:6018.70-6018.101" + cell $not $not$ls180.v:6018$1554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6018$1554_Y + end + attribute \src "ls180.v:6021.70-6021.101" + cell $not $not$ls180.v:6021$1561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6021$1561_Y + end + attribute \src "ls180.v:6024.70-6024.101" + cell $not $not$ls180.v:6024$1568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6024$1568_Y + end + attribute \src "ls180.v:6027.70-6027.101" + cell $not $not$ls180.v:6027$1575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6027$1575_Y + end + attribute \src "ls180.v:6030.70-6030.101" + cell $not $not$ls180.v:6030$1582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6030$1582_Y + end + attribute \src "ls180.v:6033.70-6033.101" + cell $not $not$ls180.v:6033$1589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6033$1589_Y + end + attribute \src "ls180.v:6036.70-6036.101" + cell $not $not$ls180.v:6036$1596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6036$1596_Y + end + attribute \src "ls180.v:6039.70-6039.101" + cell $not $not$ls180.v:6039$1603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6039$1603_Y + end + attribute \src "ls180.v:6042.70-6042.101" + cell $not $not$ls180.v:6042$1610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6042$1610_Y + end + attribute \src "ls180.v:6045.66-6045.97" + cell $not $not$ls180.v:6045$1617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6045$1617_Y + end + attribute \src "ls180.v:6048.67-6048.98" + cell $not $not$ls180.v:6048$1624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6048$1624_Y + end + attribute \src "ls180.v:6051.70-6051.101" + cell $not $not$ls180.v:6051$1631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6051$1631_Y + end + attribute \src "ls180.v:6054.70-6054.101" + cell $not $not$ls180.v:6054$1638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6054$1638_Y + end + attribute \src "ls180.v:6057.69-6057.100" + cell $not $not$ls180.v:6057$1645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6057$1645_Y + end + attribute \src "ls180.v:6060.69-6060.100" + cell $not $not$ls180.v:6060$1652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6060$1652_Y + end + attribute \src "ls180.v:6063.69-6063.100" + cell $not $not$ls180.v:6063$1659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6063$1659_Y + end + attribute \src "ls180.v:6066.69-6066.100" + cell $not $not$ls180.v:6066$1666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6066$1666_Y + end + attribute \src "ls180.v:6105.66-6105.97" + cell $not $not$ls180.v:6105$1674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6105$1674_Y + end + attribute \src "ls180.v:6108.66-6108.97" + cell $not $not$ls180.v:6108$1681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6108$1681_Y + end + attribute \src "ls180.v:6111.66-6111.97" + cell $not $not$ls180.v:6111$1688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6111$1688_Y + end + attribute \src "ls180.v:6114.66-6114.97" + cell $not $not$ls180.v:6114$1695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6114$1695_Y + end + attribute \src "ls180.v:6117.66-6117.97" + cell $not $not$ls180.v:6117$1702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6117$1702_Y + end + attribute \src "ls180.v:6120.66-6120.97" + cell $not $not$ls180.v:6120$1709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6120$1709_Y + end + attribute \src "ls180.v:6123.66-6123.97" + cell $not $not$ls180.v:6123$1716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6123$1716_Y + end + attribute \src "ls180.v:6126.66-6126.97" + cell $not $not$ls180.v:6126$1723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6126$1723_Y + end + attribute \src "ls180.v:6129.68-6129.99" + cell $not $not$ls180.v:6129$1730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6129$1730_Y + end + attribute \src "ls180.v:6132.68-6132.99" + cell $not $not$ls180.v:6132$1737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6132$1737_Y + end + attribute \src "ls180.v:6135.68-6135.99" + cell $not $not$ls180.v:6135$1744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6135$1744_Y + end + attribute \src "ls180.v:6138.68-6138.99" + cell $not $not$ls180.v:6138$1751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6138$1751_Y + end + attribute \src "ls180.v:6141.68-6141.99" + cell $not $not$ls180.v:6141$1758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6141$1758_Y + end + attribute \src "ls180.v:6144.65-6144.96" + cell $not $not$ls180.v:6144$1765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6144$1765_Y + end + attribute \src "ls180.v:6147.66-6147.97" + cell $not $not$ls180.v:6147$1772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6147$1772_Y + end + attribute \src "ls180.v:6150.68-6150.99" + cell $not $not$ls180.v:6150$1779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6150$1779_Y + end + attribute \src "ls180.v:6153.68-6153.99" + cell $not $not$ls180.v:6153$1786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6153$1786_Y + end + attribute \src "ls180.v:6156.68-6156.99" + cell $not $not$ls180.v:6156$1793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6156$1793_Y + end + attribute \src "ls180.v:6159.68-6159.99" + cell $not $not$ls180.v:6159$1800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6159$1800_Y + end + attribute \src "ls180.v:6184.68-6184.99" + cell $not $not$ls180.v:6184$1808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6184$1808_Y + end + attribute \src "ls180.v:6187.73-6187.104" + cell $not $not$ls180.v:6187$1815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6187$1815_Y + end + attribute \src "ls180.v:6190.73-6190.104" + cell $not $not$ls180.v:6190$1822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6190$1822_Y + end + attribute \src "ls180.v:6193.66-6193.97" + cell $not $not$ls180.v:6193$1829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6193$1829_Y + end + attribute \src "ls180.v:6201.70-6201.101" + cell $not $not$ls180.v:6201$1837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6201$1837_Y + end + attribute \src "ls180.v:6204.74-6204.105" + cell $not $not$ls180.v:6204$1844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6204$1844_Y + end + attribute \src "ls180.v:6207.64-6207.95" + cell $not $not$ls180.v:6207$1851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6207$1851_Y + end + attribute \src "ls180.v:6210.74-6210.105" + cell $not $not$ls180.v:6210$1858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6210$1858_Y + end + attribute \src "ls180.v:6213.74-6213.105" + cell $not $not$ls180.v:6213$1865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6213$1865_Y + end + attribute \src "ls180.v:6216.75-6216.106" + cell $not $not$ls180.v:6216$1872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6216$1872_Y + end + attribute \src "ls180.v:6219.73-6219.104" + cell $not $not$ls180.v:6219$1879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6219$1879_Y + end + attribute \src "ls180.v:6222.73-6222.104" + cell $not $not$ls180.v:6222$1886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6222$1886_Y + end + attribute \src "ls180.v:6225.73-6225.104" + cell $not $not$ls180.v:6225$1893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6225$1893_Y + end + attribute \src "ls180.v:6228.73-6228.104" + cell $not $not$ls180.v:6228$1900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6228$1900_Y + end + attribute \src "ls180.v:6246.67-6246.99" + cell $not $not$ls180.v:6246$1908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6246$1908_Y + end + attribute \src "ls180.v:6249.67-6249.99" + cell $not $not$ls180.v:6249$1915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6249$1915_Y + end + attribute \src "ls180.v:6252.65-6252.97" + cell $not $not$ls180.v:6252$1922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6252$1922_Y + end + attribute \src "ls180.v:6255.64-6255.96" + cell $not $not$ls180.v:6255$1929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6255$1929_Y + end + attribute \src "ls180.v:6258.63-6258.95" + cell $not $not$ls180.v:6258$1936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6258$1936_Y + end + attribute \src "ls180.v:6261.62-6261.94" + cell $not $not$ls180.v:6261$1943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6261$1943_Y + end + attribute \src "ls180.v:6264.68-6264.100" + cell $not $not$ls180.v:6264$1950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6264$1950_Y + end + attribute \src "ls180.v:6286.67-6286.99" + cell $not $not$ls180.v:6286$1959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6286$1959_Y + end + attribute \src "ls180.v:6289.67-6289.99" + cell $not $not$ls180.v:6289$1966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6289$1966_Y + end + attribute \src "ls180.v:6292.65-6292.97" + cell $not $not$ls180.v:6292$1973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6292$1973_Y + end + attribute \src "ls180.v:6295.64-6295.96" + cell $not $not$ls180.v:6295$1980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6295$1980_Y + end + attribute \src "ls180.v:6298.63-6298.95" + cell $not $not$ls180.v:6298$1987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6298$1987_Y + end + attribute \src "ls180.v:6301.62-6301.94" + cell $not $not$ls180.v:6301$1994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6301$1994_Y + end + attribute \src "ls180.v:6304.68-6304.100" + cell $not $not$ls180.v:6304$2001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6304$2001_Y + end + attribute \src "ls180.v:6307.71-6307.103" + cell $not $not$ls180.v:6307$2008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6307$2008_Y + end + attribute \src "ls180.v:6310.71-6310.103" + cell $not $not$ls180.v:6310$2015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6310$2015_Y + end + attribute \src "ls180.v:6334.64-6334.96" + cell $not $not$ls180.v:6334$2024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6334$2024_Y + end + attribute \src "ls180.v:6337.64-6337.96" + cell $not $not$ls180.v:6337$2031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6337$2031_Y + end + attribute \src "ls180.v:6340.64-6340.96" + cell $not $not$ls180.v:6340$2038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6340$2038_Y + end + attribute \src "ls180.v:6343.64-6343.96" + cell $not $not$ls180.v:6343$2045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6343$2045_Y + end + attribute \src "ls180.v:6346.66-6346.98" + cell $not $not$ls180.v:6346$2052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6346$2052_Y + end + attribute \src "ls180.v:6349.66-6349.98" + cell $not $not$ls180.v:6349$2059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6349$2059_Y + end + attribute \src "ls180.v:6352.66-6352.98" + cell $not $not$ls180.v:6352$2066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6352$2066_Y + end + attribute \src "ls180.v:6355.66-6355.98" + cell $not $not$ls180.v:6355$2073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6355$2073_Y + end + attribute \src "ls180.v:6358.62-6358.94" + cell $not $not$ls180.v:6358$2080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6358$2080_Y + end + attribute \src "ls180.v:6361.72-6361.104" + cell $not $not$ls180.v:6361$2087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6361$2087_Y + end + attribute \src "ls180.v:6364.65-6364.97" + cell $not $not$ls180.v:6364$2094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6364$2094_Y + end + attribute \src "ls180.v:6367.65-6367.97" + cell $not $not$ls180.v:6367$2101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6367$2101_Y + end + attribute \src "ls180.v:6370.65-6370.97" + cell $not $not$ls180.v:6370$2108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6370$2108_Y + end + attribute \src "ls180.v:6373.65-6373.97" + cell $not $not$ls180.v:6373$2115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6373$2115_Y + end + attribute \src "ls180.v:6376.77-6376.109" + cell $not $not$ls180.v:6376$2122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6376$2122_Y + end + attribute \src "ls180.v:6379.78-6379.110" + cell $not $not$ls180.v:6379$2129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6379$2129_Y + end + attribute \src "ls180.v:6382.69-6382.101" + cell $not $not$ls180.v:6382$2136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6382$2136_Y + end + attribute \src "ls180.v:6402.55-6402.87" + cell $not $not$ls180.v:6402$2144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6402$2144_Y + end + attribute \src "ls180.v:6405.65-6405.97" + cell $not $not$ls180.v:6405$2151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6405$2151_Y + end + attribute \src "ls180.v:6408.66-6408.98" + cell $not $not$ls180.v:6408$2158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6408$2158_Y + end + attribute \src "ls180.v:6411.70-6411.102" + cell $not $not$ls180.v:6411$2165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6411$2165_Y + end + attribute \src "ls180.v:6414.71-6414.103" + cell $not $not$ls180.v:6414$2172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6414$2172_Y + end + attribute \src "ls180.v:6417.69-6417.101" + cell $not $not$ls180.v:6417$2179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6417$2179_Y + end + attribute \src "ls180.v:6420.66-6420.98" + cell $not $not$ls180.v:6420$2186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6420$2186_Y + end + attribute \src "ls180.v:6423.65-6423.97" + cell $not $not$ls180.v:6423$2193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6423$2193_Y + end + attribute \src "ls180.v:6436.71-6436.103" + cell $not $not$ls180.v:6436$2201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6436$2201_Y + end + attribute \src "ls180.v:6439.71-6439.103" + cell $not $not$ls180.v:6439$2208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6439$2208_Y + end + attribute \src "ls180.v:6442.71-6442.103" + cell $not $not$ls180.v:6442$2215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6442$2215_Y + end + attribute \src "ls180.v:6445.71-6445.103" + cell $not $not$ls180.v:6445$2222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6445$2222_Y + end + attribute \src "ls180.v:6826.86-6826.330" + cell $not $not$ls180.v:6826$2271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6826$2270_Y + connect \Y $not$ls180.v:6826$2271_Y + end + attribute \src "ls180.v:6850.86-6850.330" + cell $not $not$ls180.v:6850$2287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6850$2286_Y + connect \Y $not$ls180.v:6850$2287_Y + end + attribute \src "ls180.v:6874.86-6874.330" + cell $not $not$ls180.v:6874$2303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6874$2302_Y + connect \Y $not$ls180.v:6874$2303_Y + end + attribute \src "ls180.v:6898.86-6898.330" + cell $not $not$ls180.v:6898$2319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6898$2318_Y + connect \Y $not$ls180.v:6898$2319_Y + end + attribute \src "ls180.v:7396.18-7396.42" + cell $not $not$ls180.v:7396$2372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk0 + connect \Y $not$ls180.v:7396$2372_Y + end + attribute \src "ls180.v:7487.72-7487.101" + cell $not $not$ls180.v:7487$2417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_ack + connect \Y $not$ls180.v:7487$2417_Y + end + attribute \src "ls180.v:7506.8-7506.38" + cell $not $not$ls180.v:7506$2421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_zero_trigger + connect \Y $not$ls180.v:7506$2421_Y + end + attribute \src "ls180.v:7514.32-7514.55" + cell $not $not$ls180.v:7514$2423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_done0 + connect \Y $not$ls180.v:7514$2423_Y + end + attribute \src "ls180.v:7584.136-7584.189" + cell $not $not$ls180.v:7584$2438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7584$2438_Y + end + attribute \src "ls180.v:7590.136-7590.189" + cell $not $not$ls180.v:7590$2443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7590$2443_Y + end + attribute \src "ls180.v:7591.8-7591.61" + cell $not $not$ls180.v:7591$2445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7591$2445_Y + end + attribute \src "ls180.v:7599.8-7599.56" + cell $not $not$ls180.v:7599$2448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$ls180.v:7599$2448_Y + end + attribute \src "ls180.v:7614.8-7614.46" + cell $not $not$ls180.v:7614$2450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \Y $not$ls180.v:7614$2450_Y + end + attribute \src "ls180.v:7630.136-7630.189" + cell $not $not$ls180.v:7630$2454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7630$2454_Y + end + attribute \src "ls180.v:7636.136-7636.189" + cell $not $not$ls180.v:7636$2459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7636$2459_Y + end + attribute \src "ls180.v:7637.8-7637.61" + cell $not $not$ls180.v:7637$2461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7637$2461_Y + end + attribute \src "ls180.v:7645.8-7645.56" + cell $not $not$ls180.v:7645$2464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$ls180.v:7645$2464_Y + end + attribute \src "ls180.v:7660.8-7660.46" + cell $not $not$ls180.v:7660$2466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \Y $not$ls180.v:7660$2466_Y + end + attribute \src "ls180.v:7676.136-7676.189" + cell $not $not$ls180.v:7676$2470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7676$2470_Y + end + attribute \src "ls180.v:7682.136-7682.189" + cell $not $not$ls180.v:7682$2475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7682$2475_Y + end + attribute \src "ls180.v:7683.8-7683.61" + cell $not $not$ls180.v:7683$2477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7683$2477_Y + end + attribute \src "ls180.v:7691.8-7691.56" + cell $not $not$ls180.v:7691$2480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$ls180.v:7691$2480_Y + end + attribute \src "ls180.v:7706.8-7706.46" + cell $not $not$ls180.v:7706$2482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \Y $not$ls180.v:7706$2482_Y + end + attribute \src "ls180.v:7722.136-7722.189" + cell $not $not$ls180.v:7722$2486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7722$2486_Y + end + attribute \src "ls180.v:7728.136-7728.189" + cell $not $not$ls180.v:7728$2491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7728$2491_Y + end + attribute \src "ls180.v:7729.8-7729.61" + cell $not $not$ls180.v:7729$2493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7729$2493_Y + end + attribute \src "ls180.v:7737.8-7737.56" + cell $not $not$ls180.v:7737$2496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$ls180.v:7737$2496_Y + end + attribute \src "ls180.v:7752.8-7752.46" + cell $not $not$ls180.v:7752$2498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \Y $not$ls180.v:7752$2498_Y + end + attribute \src "ls180.v:7760.7-7760.22" + cell $not $not$ls180.v:7760$2501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_en0 + connect \Y $not$ls180.v:7760$2501_Y + end + attribute \src "ls180.v:7763.8-7763.29" + cell $not $not$ls180.v:7763$2502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_max_time0 + connect \Y $not$ls180.v:7763$2502_Y + end + attribute \src "ls180.v:7767.7-7767.22" + cell $not $not$ls180.v:7767$2504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_en1 + connect \Y $not$ls180.v:7767$2504_Y + end + attribute \src "ls180.v:7770.8-7770.29" + cell $not $not$ls180.v:7770$2505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_max_time1 + connect \Y $not$ls180.v:7770$2505_Y + end + attribute \src "ls180.v:7889.30-7889.60" + cell $not $not$ls180.v:7889$2507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed2 + connect \Y $not$ls180.v:7889$2507_Y + end + attribute \src "ls180.v:7890.30-7890.60" + cell $not $not$ls180.v:7890$2508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed3 + connect \Y $not$ls180.v:7890$2508_Y + end + attribute \src "ls180.v:7891.29-7891.59" + cell $not $not$ls180.v:7891$2509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed4 + connect \Y $not$ls180.v:7891$2509_Y + end + attribute \src "ls180.v:7902.8-7902.33" + cell $not $not$ls180.v:7902$2510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_ready + connect \Y $not$ls180.v:7902$2510_Y + end + attribute \src "ls180.v:7917.8-7917.33" + cell $not $not$ls180.v:7917$2513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_twtrcon_ready + connect \Y $not$ls180.v:7917$2513_Y + end + attribute \src "ls180.v:7953.36-7953.58" + cell $not $not$ls180.v:7953$2543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_tx_busy + connect \Y $not$ls180.v:7953$2543_Y + end + attribute \src "ls180.v:7953.64-7953.89" + cell $not $not$ls180.v:7953$2545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_sink_ready + connect \Y $not$ls180.v:7953$2545_Y + end + attribute \src "ls180.v:7982.7-7982.29" + cell $not $not$ls180.v:7982$2552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx_busy + connect \Y $not$ls180.v:7982$2552_Y + end + attribute \src "ls180.v:7983.9-7983.26" + cell $not $not$ls180.v:7983$2553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx + connect \Y $not$ls180.v:7983$2553_Y + end + attribute \src "ls180.v:8016.8-8016.29" + cell $not $not$ls180.v:8016$2559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_trigger + connect \Y $not$ls180.v:8016$2559_Y + end + attribute \src "ls180.v:8023.8-8023.29" + cell $not $not$ls180.v:8023$2561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_trigger + connect \Y $not$ls180.v:8023$2561_Y + end + attribute \src "ls180.v:8033.80-8033.106" + cell $not $not$ls180.v:8033$2564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_replace + connect \Y $not$ls180.v:8033$2564_Y + end + attribute \src "ls180.v:8039.80-8039.106" + cell $not $not$ls180.v:8039$2569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_replace + connect \Y $not$ls180.v:8039$2569_Y + end + attribute \src "ls180.v:8040.8-8040.34" + cell $not $not$ls180.v:8040$2571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_do_read + connect \Y $not$ls180.v:8040$2571_Y + end + attribute \src "ls180.v:8055.80-8055.106" + cell $not $not$ls180.v:8055$2575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_replace + connect \Y $not$ls180.v:8055$2575_Y + end + attribute \src "ls180.v:8061.80-8061.106" + cell $not $not$ls180.v:8061$2580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_replace + connect \Y $not$ls180.v:8061$2580_Y + end + attribute \src "ls180.v:8062.8-8062.34" + cell $not $not$ls180.v:8062$2582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_do_read + connect \Y $not$ls180.v:8062$2582_Y + end + attribute \src "ls180.v:8093.23-8093.42" + cell $not $not$ls180.v:8093$2586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spi_master_cs + connect \Y $not$ls180.v:8093$2586_Y + end + attribute \src "ls180.v:8093.47-8093.73" + cell $not $not$ls180.v:8093$2587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spi_master_cs_enable + connect \Y $not$ls180.v:8093$2587_Y + end + attribute \src "ls180.v:8147.7-8147.31" + cell $not $not$ls180.v:8147$2598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_stop + connect \Y $not$ls180.v:8147$2598_Y + end + attribute \src "ls180.v:8219.8-8219.46" + cell $not $not$ls180.v:8219$2610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_buf_source_valid + connect \Y $not$ls180.v:8219$2610_Y + end + attribute \src "ls180.v:8300.8-8300.47" + cell $not $not$ls180.v:8300$2622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_buf_source_valid + connect \Y $not$ls180.v:8300$2622_Y + end + attribute \src "ls180.v:8361.8-8361.48" + cell $not $not$ls180.v:8361$2634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_buf_source_valid + connect \Y $not$ls180.v:8361$2634_Y + end + attribute \src "ls180.v:8531.88-8531.118" + cell $not $not$ls180.v:8531$2648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_replace + connect \Y $not$ls180.v:8531$2648_Y + end + attribute \src "ls180.v:8537.88-8537.118" + cell $not $not$ls180.v:8537$2653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_replace + connect \Y $not$ls180.v:8537$2653_Y + end + attribute \src "ls180.v:8538.8-8538.38" + cell $not $not$ls180.v:8538$2655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_do_read + connect \Y $not$ls180.v:8538$2655_Y + end + attribute \src "ls180.v:8617.88-8617.118" + cell $not $not$ls180.v:8617$2670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_replace + connect \Y $not$ls180.v:8617$2670_Y + end + attribute \src "ls180.v:8623.88-8623.118" + cell $not $not$ls180.v:8623$2675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_replace + connect \Y $not$ls180.v:8623$2675_Y + end + attribute \src "ls180.v:8624.8-8624.38" + cell $not $not$ls180.v:8624$2677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_do_read + connect \Y $not$ls180.v:8624$2677_Y + end + attribute \src "ls180.v:8641.22-8641.37" + cell $not $not$ls180.v:8641$2681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cs + connect \Y $not$ls180.v:8641$2681_Y + end + attribute \src "ls180.v:8641.42-8641.64" + cell $not $not$ls180.v:8641$2682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cs_enable + connect \Y $not$ls180.v:8641$2682_Y + end + attribute \src "ls180.v:8679.9-8679.28" + cell $not $not$ls180.v:8679$2685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [0] + connect \Y $not$ls180.v:8679$2685_Y + end + attribute \src "ls180.v:8698.9-8698.28" + cell $not $not$ls180.v:8698$2686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [1] + connect \Y $not$ls180.v:8698$2686_Y + end + attribute \src "ls180.v:8717.9-8717.28" + cell $not $not$ls180.v:8717$2687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [2] + connect \Y $not$ls180.v:8717$2687_Y + end + attribute \src "ls180.v:8736.9-8736.28" + cell $not $not$ls180.v:8736$2688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [3] + connect \Y $not$ls180.v:8736$2688_Y + end + attribute \src "ls180.v:8755.9-8755.28" + cell $not $not$ls180.v:8755$2689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [4] + connect \Y $not$ls180.v:8755$2689_Y + end + attribute \src "ls180.v:8776.8-8776.21" + cell $not $not$ls180.v:8776$2690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_done + connect \Y $not$ls180.v:8776$2690_Y + end + attribute \src "ls180.v:10259.8-10259.51" + cell $or $or$ls180.v:10259$2762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sys_rst_1 + connect \B \main_libresocsim_libresoc_reset + connect \Y $or$ls180.v:10259$2762_Y + end + attribute \src "ls180.v:2798.10-2798.96" + cell $or $or$ls180.v:2798$21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface0_converted_interface_ack + connect \B \main_libresocsim_converter0_skip + connect \Y $or$ls180.v:2798$21_Y + end + attribute \src "ls180.v:2858.10-2858.96" + cell $or $or$ls180.v:2858$32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface1_converted_interface_ack + connect \B \main_libresocsim_converter1_skip + connect \Y $or$ls180.v:2858$32_Y + end + attribute \src "ls180.v:2918.10-2918.96" + cell $or $or$ls180.v:2918$43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface2_converted_interface_ack + connect \B \main_libresocsim_converter2_skip + connect \Y $or$ls180.v:2918$43_Y + end + attribute \src "ls180.v:3110.39-3110.105" + cell $or $or$ls180.v:3110$75 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_start0 + connect \B $ne$ls180.v:3110$74_Y + connect \Y $or$ls180.v:3110$75_Y + end + attribute \src "ls180.v:3153.59-3153.140" + cell $or $or$ls180.v:3153$79 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_req_wdata_ready + connect \B \main_sdram_bankmachine0_req_rdata_valid + connect \Y $or$ls180.v:3153$79_Y + end + attribute \src "ls180.v:3154.44-3154.151" + cell $or $or$ls180.v:3154$80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $or$ls180.v:3154$80_Y + end + attribute \src "ls180.v:3162.45-3162.170" + cell $or $or$ls180.v:3162$84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3162$83_Y + connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3162$84_Y + end + attribute \src "ls180.v:3199.127-3199.245" + cell $or $or$ls180.v:3199$97 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3199$97_Y + end + attribute \src "ls180.v:3205.57-3205.157" + cell $or $or$ls180.v:3205$103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3205$102_Y + connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$ls180.v:3205$103_Y + end + attribute \src "ls180.v:3310.59-3310.140" + cell $or $or$ls180.v:3310$109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_req_wdata_ready + connect \B \main_sdram_bankmachine1_req_rdata_valid + connect \Y $or$ls180.v:3310$109_Y + end + attribute \src "ls180.v:3311.44-3311.151" + cell $or $or$ls180.v:3311$110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $or$ls180.v:3311$110_Y + end + attribute \src "ls180.v:3319.45-3319.170" + cell $or $or$ls180.v:3319$114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3319$113_Y + connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3319$114_Y + end + attribute \src "ls180.v:3356.127-3356.245" + cell $or $or$ls180.v:3356$127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3356$127_Y + end + attribute \src "ls180.v:3362.57-3362.157" + cell $or $or$ls180.v:3362$133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3362$132_Y + connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$ls180.v:3362$133_Y + end + attribute \src "ls180.v:3467.59-3467.140" + cell $or $or$ls180.v:3467$139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_req_wdata_ready + connect \B \main_sdram_bankmachine2_req_rdata_valid + connect \Y $or$ls180.v:3467$139_Y + end + attribute \src "ls180.v:3468.44-3468.151" + cell $or $or$ls180.v:3468$140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $or$ls180.v:3468$140_Y + end + attribute \src "ls180.v:3476.45-3476.170" + cell $or $or$ls180.v:3476$144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3476$143_Y + connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3476$144_Y + end + attribute \src "ls180.v:3513.127-3513.245" + cell $or $or$ls180.v:3513$157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3513$157_Y + end + attribute \src "ls180.v:3519.57-3519.157" + cell $or $or$ls180.v:3519$163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3519$162_Y + connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$ls180.v:3519$163_Y + end + attribute \src "ls180.v:3624.59-3624.140" + cell $or $or$ls180.v:3624$169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_req_wdata_ready + connect \B \main_sdram_bankmachine3_req_rdata_valid + connect \Y $or$ls180.v:3624$169_Y + end + attribute \src "ls180.v:3625.44-3625.151" + cell $or $or$ls180.v:3625$170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $or$ls180.v:3625$170_Y + end + attribute \src "ls180.v:3633.45-3633.170" + cell $or $or$ls180.v:3633$174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3633$173_Y + connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3633$174_Y + end + attribute \src "ls180.v:3670.127-3670.245" + cell $or $or$ls180.v:3670$187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3670$187_Y + end + attribute \src "ls180.v:3676.57-3676.157" + cell $or $or$ls180.v:3676$193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3676$192_Y + connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$ls180.v:3676$193_Y + end + attribute \src "ls180.v:3775.107-3775.193" + cell $or $or$ls180.v:3775$213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_is_write + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $or$ls180.v:3775$213_Y + end + attribute \src "ls180.v:3778.39-3778.204" + cell $or $or$ls180.v:3778$219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3778$217_Y + connect \B $and$ls180.v:3778$218_Y + connect \Y $or$ls180.v:3778$219_Y + end + attribute \src "ls180.v:3778.38-3778.289" + cell $or $or$ls180.v:3778$221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3778$219_Y + connect \B $and$ls180.v:3778$220_Y + connect \Y $or$ls180.v:3778$221_Y + end + attribute \src "ls180.v:3778.37-3778.374" + cell $or $or$ls180.v:3778$223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3778$221_Y + connect \B $and$ls180.v:3778$222_Y + connect \Y $or$ls180.v:3778$223_Y + end + attribute \src "ls180.v:3779.40-3779.207" + cell $or $or$ls180.v:3779$226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3779$224_Y + connect \B $and$ls180.v:3779$225_Y + connect \Y $or$ls180.v:3779$226_Y + end + attribute \src "ls180.v:3779.39-3779.293" + cell $or $or$ls180.v:3779$228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3779$226_Y + connect \B $and$ls180.v:3779$227_Y + connect \Y $or$ls180.v:3779$228_Y + end + attribute \src "ls180.v:3779.38-3779.379" + cell $or $or$ls180.v:3779$230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3779$228_Y + connect \B $and$ls180.v:3779$229_Y + connect \Y $or$ls180.v:3779$230_Y + end + attribute \src "ls180.v:3792.158-3792.332" + cell $or $or$ls180.v:3792$244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3792$243_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3792$244_Y + end + attribute \src "ls180.v:3792.75-3792.506" + cell $or $or$ls180.v:3792$249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3792$245_Y + connect \B $and$ls180.v:3792$248_Y + connect \Y $or$ls180.v:3792$249_Y + end + attribute \src "ls180.v:3793.158-3793.332" + cell $or $or$ls180.v:3793$257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3793$256_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3793$257_Y + end + attribute \src "ls180.v:3793.75-3793.506" + cell $or $or$ls180.v:3793$262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3793$258_Y + connect \B $and$ls180.v:3793$261_Y + connect \Y $or$ls180.v:3793$262_Y + end + attribute \src "ls180.v:3794.158-3794.332" + cell $or $or$ls180.v:3794$270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3794$269_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3794$270_Y + end + attribute \src "ls180.v:3794.75-3794.506" + cell $or $or$ls180.v:3794$275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3794$271_Y + connect \B $and$ls180.v:3794$274_Y + connect \Y $or$ls180.v:3794$275_Y + end + attribute \src "ls180.v:3795.158-3795.332" + cell $or $or$ls180.v:3795$283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3795$282_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3795$283_Y + end + attribute \src "ls180.v:3795.75-3795.506" + cell $or $or$ls180.v:3795$288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3795$284_Y + connect \B $and$ls180.v:3795$287_Y + connect \Y $or$ls180.v:3795$288_Y + end + attribute \src "ls180.v:3822.36-3822.104" + cell $or $or$ls180.v:3822$294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_ready + connect \B $not$ls180.v:3822$293_Y + connect \Y $or$ls180.v:3822$294_Y + end + attribute \src "ls180.v:3825.158-3825.332" + cell $or $or$ls180.v:3825$302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3825$301_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3825$302_Y + end + attribute \src "ls180.v:3825.75-3825.506" + cell $or $or$ls180.v:3825$307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3825$303_Y + connect \B $and$ls180.v:3825$306_Y + connect \Y $or$ls180.v:3825$307_Y + end + attribute \src "ls180.v:3826.158-3826.332" + cell $or $or$ls180.v:3826$315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3826$314_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3826$315_Y + end + attribute \src "ls180.v:3826.75-3826.506" + cell $or $or$ls180.v:3826$320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3826$316_Y + connect \B $and$ls180.v:3826$319_Y + connect \Y $or$ls180.v:3826$320_Y + end + attribute \src "ls180.v:3827.158-3827.332" + cell $or $or$ls180.v:3827$328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3827$327_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3827$328_Y + end + attribute \src "ls180.v:3827.75-3827.506" + cell $or $or$ls180.v:3827$333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3827$329_Y + connect \B $and$ls180.v:3827$332_Y + connect \Y $or$ls180.v:3827$333_Y + end + attribute \src "ls180.v:3828.158-3828.332" + cell $or $or$ls180.v:3828$341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3828$340_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3828$341_Y + end + attribute \src "ls180.v:3828.75-3828.506" + cell $or $or$ls180.v:3828$346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3828$342_Y + connect \B $and$ls180.v:3828$345_Y + connect \Y $or$ls180.v:3828$346_Y + end + attribute \src "ls180.v:3891.36-3891.104" + cell $or $or$ls180.v:3891$380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_ready + connect \B $not$ls180.v:3891$379_Y + connect \Y $or$ls180.v:3891$380_Y + end + attribute \src "ls180.v:3912.67-3912.221" + cell $or $or$ls180.v:3912$387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3912$386_Y + connect \B \main_sdram_ras_allowed + connect \Y $or$ls180.v:3912$387_Y + end + attribute \src "ls180.v:3920.10-3920.62" + cell $or $or$ls180.v:3920$390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3920$389_Y + connect \B \main_sdram_max_time1 + connect \Y $or$ls180.v:3920$390_Y + end + attribute \src "ls180.v:3950.67-3950.221" + cell $or $or$ls180.v:3950$396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3950$395_Y + connect \B \main_sdram_ras_allowed + connect \Y $or$ls180.v:3950$396_Y + end + attribute \src "ls180.v:3958.10-3958.61" + cell $or $or$ls180.v:3958$399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3958$398_Y + connect \B \main_sdram_max_time0 + connect \Y $or$ls180.v:3958$399_Y + end + attribute \src "ls180.v:3968.91-3968.180" + cell $or $or$ls180.v:3968$403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:3968$402_Y + connect \Y $or$ls180.v:3968$403_Y + end + attribute \src "ls180.v:3968.90-3968.255" + cell $or $or$ls180.v:3968$406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3968$403_Y + connect \B $and$ls180.v:3968$405_Y + connect \Y $or$ls180.v:3968$406_Y + end + attribute \src "ls180.v:3968.89-3968.330" + cell $or $or$ls180.v:3968$409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3968$406_Y + connect \B $and$ls180.v:3968$408_Y + connect \Y $or$ls180.v:3968$409_Y + end + attribute \src "ls180.v:3973.91-3973.180" + cell $or $or$ls180.v:3973$419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:3973$418_Y + connect \Y $or$ls180.v:3973$419_Y + end + attribute \src "ls180.v:3973.90-3973.255" + cell $or $or$ls180.v:3973$422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3973$419_Y + connect \B $and$ls180.v:3973$421_Y + connect \Y $or$ls180.v:3973$422_Y + end + attribute \src "ls180.v:3973.89-3973.330" + cell $or $or$ls180.v:3973$425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3973$422_Y + connect \B $and$ls180.v:3973$424_Y + connect \Y $or$ls180.v:3973$425_Y + end + attribute \src "ls180.v:3978.91-3978.180" + cell $or $or$ls180.v:3978$435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:3978$434_Y + connect \Y $or$ls180.v:3978$435_Y + end + attribute \src "ls180.v:3978.90-3978.255" + cell $or $or$ls180.v:3978$438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3978$435_Y + connect \B $and$ls180.v:3978$437_Y + connect \Y $or$ls180.v:3978$438_Y + end + attribute \src "ls180.v:3978.89-3978.330" + cell $or $or$ls180.v:3978$441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3978$438_Y + connect \B $and$ls180.v:3978$440_Y + connect \Y $or$ls180.v:3978$441_Y + end + attribute \src "ls180.v:3983.91-3983.180" + cell $or $or$ls180.v:3983$451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:3983$450_Y + connect \Y $or$ls180.v:3983$451_Y + end + attribute \src "ls180.v:3983.90-3983.255" + cell $or $or$ls180.v:3983$454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3983$451_Y + connect \B $and$ls180.v:3983$453_Y + connect \Y $or$ls180.v:3983$454_Y + end + attribute \src "ls180.v:3983.89-3983.330" + cell $or $or$ls180.v:3983$457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3983$454_Y + connect \B $and$ls180.v:3983$456_Y + connect \Y $or$ls180.v:3983$457_Y + end + attribute \src "ls180.v:3988.132-3988.221" + cell $or $or$ls180.v:3988$468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:3988$467_Y + connect \Y $or$ls180.v:3988$468_Y + end + attribute \src "ls180.v:3988.131-3988.296" + cell $or $or$ls180.v:3988$471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3988$468_Y + connect \B $and$ls180.v:3988$470_Y + connect \Y $or$ls180.v:3988$471_Y + end + attribute \src "ls180.v:3988.130-3988.371" + cell $or $or$ls180.v:3988$474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3988$471_Y + connect \B $and$ls180.v:3988$473_Y + connect \Y $or$ls180.v:3988$474_Y + end + attribute \src "ls180.v:3988.34-3988.411" + cell $or $or$ls180.v:3988$479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:3988$478_Y + connect \Y $or$ls180.v:3988$479_Y + end + attribute \src "ls180.v:3988.506-3988.595" + cell $or $or$ls180.v:3988$484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:3988$483_Y + connect \Y $or$ls180.v:3988$484_Y + end + attribute \src "ls180.v:3988.505-3988.670" + cell $or $or$ls180.v:3988$487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3988$484_Y + connect \B $and$ls180.v:3988$486_Y + connect \Y $or$ls180.v:3988$487_Y + end + attribute \src "ls180.v:3988.504-3988.745" + cell $or $or$ls180.v:3988$490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3988$487_Y + connect \B $and$ls180.v:3988$489_Y + connect \Y $or$ls180.v:3988$490_Y + end + attribute \src "ls180.v:3988.33-3988.785" + cell $or $or$ls180.v:3988$495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3988$479_Y + connect \B $and$ls180.v:3988$494_Y + connect \Y $or$ls180.v:3988$495_Y + end + attribute \src "ls180.v:3988.880-3988.969" + cell $or $or$ls180.v:3988$500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:3988$499_Y + connect \Y $or$ls180.v:3988$500_Y + end + attribute \src "ls180.v:3988.879-3988.1044" + cell $or $or$ls180.v:3988$503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3988$500_Y + connect \B $and$ls180.v:3988$502_Y + connect \Y $or$ls180.v:3988$503_Y + end + attribute \src "ls180.v:3988.878-3988.1119" + cell $or $or$ls180.v:3988$506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3988$503_Y + connect \B $and$ls180.v:3988$505_Y + connect \Y $or$ls180.v:3988$506_Y + end + attribute \src "ls180.v:3988.32-3988.1159" + cell $or $or$ls180.v:3988$511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3988$495_Y + connect \B $and$ls180.v:3988$510_Y + connect \Y $or$ls180.v:3988$511_Y + end + attribute \src "ls180.v:3988.1254-3988.1343" + cell $or $or$ls180.v:3988$516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:3988$515_Y + connect \Y $or$ls180.v:3988$516_Y + end + attribute \src "ls180.v:3988.1253-3988.1418" + cell $or $or$ls180.v:3988$519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3988$516_Y + connect \B $and$ls180.v:3988$518_Y + connect \Y $or$ls180.v:3988$519_Y + end + attribute \src "ls180.v:3988.1252-3988.1493" + cell $or $or$ls180.v:3988$522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3988$519_Y + connect \B $and$ls180.v:3988$521_Y + connect \Y $or$ls180.v:3988$522_Y + end + attribute \src "ls180.v:3988.31-3988.1533" + cell $or $or$ls180.v:3988$527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3988$511_Y + connect \B $and$ls180.v:3988$526_Y + connect \Y $or$ls180.v:3988$527_Y + end + attribute \src "ls180.v:4051.10-4051.52" + cell $or $or$ls180.v:4051$536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_ack + connect \B \main_converter_skip + connect \Y $or$ls180.v:4051$536_Y + end + attribute \src "ls180.v:4078.35-4078.74" + cell $or $or$ls180.v:4078$546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4078$546_Y + end + attribute \src "ls180.v:4079.34-4079.73" + cell $or $or$ls180.v:4079$550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4079$550_Y + end + attribute \src "ls180.v:4080.48-4080.130" + cell $or $or$ls180.v:4080$556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4080$553_Y + connect \B $and$ls180.v:4080$555_Y + connect \Y $or$ls180.v:4080$556_Y + end + attribute \src "ls180.v:4081.24-4081.87" + cell $or $or$ls180.v:4081$559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4081$558_Y + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4081$559_Y + end + attribute \src "ls180.v:4082.26-4082.95" + cell $or $or$ls180.v:4082$561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4082$560_Y + connect \B \main_wdata_consumed + connect \Y $or$ls180.v:4082$561_Y + end + attribute \src "ls180.v:4112.42-4112.89" + cell $or $or$ls180.v:4112$569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_clear + connect \B $and$ls180.v:4112$568_Y + connect \Y $or$ls180.v:4112$569_Y + end + attribute \src "ls180.v:4136.25-4136.174" + cell $or $or$ls180.v:4136$579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4136$577_Y + connect \B $and$ls180.v:4136$578_Y + connect \Y $or$ls180.v:4136$579_Y + end + attribute \src "ls180.v:4151.80-4151.132" + cell $or $or$ls180.v:4151$581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4151$580_Y + connect \B \main_uart_tx_fifo_re + connect \Y $or$ls180.v:4151$581_Y + end + attribute \src "ls180.v:4162.72-4162.135" + cell $or $or$ls180.v:4162$586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_writable + connect \B \main_uart_tx_fifo_replace + connect \Y $or$ls180.v:4162$586_Y + end + attribute \src "ls180.v:4181.80-4181.132" + cell $or $or$ls180.v:4181$592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4181$591_Y + connect \B \main_uart_rx_fifo_re + connect \Y $or$ls180.v:4181$592_Y + end + attribute \src "ls180.v:4192.72-4192.135" + cell $or $or$ls180.v:4192$597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_writable + connect \B \main_uart_rx_fifo_replace + connect \Y $or$ls180.v:4192$597_Y + end + attribute \src "ls180.v:4267.36-4267.111" + cell $or $or$ls180.v:4267$610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_clk + connect \B \main_sdphy_cmdw_pads_out_payload_clk + connect \Y $or$ls180.v:4267$610_Y + end + attribute \src "ls180.v:4267.35-4267.151" + cell $or $or$ls180.v:4267$611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4267$610_Y + connect \B \main_sdphy_cmdr_pads_out_payload_clk + connect \Y $or$ls180.v:4267$611_Y + end + attribute \src "ls180.v:4267.34-4267.192" + cell $or $or$ls180.v:4267$612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4267$611_Y + connect \B \main_sdphy_dataw_pads_out_payload_clk + connect \Y $or$ls180.v:4267$612_Y + end + attribute \src "ls180.v:4267.33-4267.233" + cell $or $or$ls180.v:4267$613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4267$612_Y + connect \B \main_sdphy_datar_pads_out_payload_clk + connect \Y $or$ls180.v:4267$613_Y + end + attribute \src "ls180.v:4268.39-4268.120" + cell $or $or$ls180.v:4268$614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_cmd_oe + connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4268$614_Y + end + attribute \src "ls180.v:4268.38-4268.163" + cell $or $or$ls180.v:4268$615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4268$614_Y + connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4268$615_Y + end + attribute \src "ls180.v:4268.37-4268.207" + cell $or $or$ls180.v:4268$616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4268$615_Y + connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4268$616_Y + end + attribute \src "ls180.v:4268.36-4268.251" + cell $or $or$ls180.v:4268$617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4268$616_Y + connect \B \main_sdphy_datar_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4268$617_Y + end + attribute \src "ls180.v:4269.38-4269.117" + cell $or $or$ls180.v:4269$618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_cmd_o + connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4269$618_Y + end + attribute \src "ls180.v:4269.37-4269.159" + cell $or $or$ls180.v:4269$619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4269$618_Y + connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4269$619_Y + end + attribute \src "ls180.v:4269.36-4269.202" + cell $or $or$ls180.v:4269$620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4269$619_Y + connect \B \main_sdphy_dataw_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4269$620_Y + end + attribute \src "ls180.v:4269.35-4269.245" + cell $or $or$ls180.v:4269$621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4269$620_Y + connect \B \main_sdphy_datar_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4269$621_Y + end + attribute \src "ls180.v:4270.40-4270.123" + cell $or $or$ls180.v:4270$622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_data_oe + connect \B \main_sdphy_cmdw_pads_out_payload_data_oe + connect \Y $or$ls180.v:4270$622_Y + end + attribute \src "ls180.v:4270.39-4270.167" + cell $or $or$ls180.v:4270$623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4270$622_Y + connect \B \main_sdphy_cmdr_pads_out_payload_data_oe + connect \Y $or$ls180.v:4270$623_Y + end + attribute \src "ls180.v:4270.38-4270.212" + cell $or $or$ls180.v:4270$624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4270$623_Y + connect \B \main_sdphy_dataw_pads_out_payload_data_oe + connect \Y $or$ls180.v:4270$624_Y + end + attribute \src "ls180.v:4270.37-4270.257" + cell $or $or$ls180.v:4270$625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4270$624_Y + connect \B \main_sdphy_datar_pads_out_payload_data_oe + connect \Y $or$ls180.v:4270$625_Y + end + attribute \src "ls180.v:4271.39-4271.120" + cell $or $or$ls180.v:4271$626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_init_pads_out_payload_data_o + connect \B \main_sdphy_cmdw_pads_out_payload_data_o + connect \Y $or$ls180.v:4271$626_Y + end + attribute \src "ls180.v:4271.38-4271.163" + cell $or $or$ls180.v:4271$627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4271$626_Y + connect \B \main_sdphy_cmdr_pads_out_payload_data_o + connect \Y $or$ls180.v:4271$627_Y + end + attribute \src "ls180.v:4271.37-4271.207" + cell $or $or$ls180.v:4271$628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4271$627_Y + connect \B \main_sdphy_dataw_pads_out_payload_data_o + connect \Y $or$ls180.v:4271$628_Y + end + attribute \src "ls180.v:4271.36-4271.251" + cell $or $or$ls180.v:4271$629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4271$628_Y + connect \B \main_sdphy_datar_pads_out_payload_data_o + connect \Y $or$ls180.v:4271$629_Y + end + attribute \src "ls180.v:4292.35-4292.80" + cell $or $or$ls180.v:4292$630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_stop + connect \B \main_sdphy_datar_stop + connect \Y $or$ls180.v:4292$630_Y + end + attribute \src "ls180.v:4446.91-4446.144" + cell $or $or$ls180.v:4446$644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_start + connect \B \main_sdphy_cmdr_cmdr_run + connect \Y $or$ls180.v:4446$644_Y + end + attribute \src "ls180.v:4463.53-4463.143" + cell $or $or$ls180.v:4463$647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4463$646_Y + connect \B \main_sdphy_cmdr_cmdr_converter_source_ready + connect \Y $or$ls180.v:4463$647_Y + end + attribute \src "ls180.v:4466.47-4466.127" + cell $or $or$ls180.v:4466$650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4466$649_Y + connect \B \main_sdphy_cmdr_cmdr_buf_source_ready + connect \Y $or$ls180.v:4466$650_Y + end + attribute \src "ls180.v:4590.54-4590.146" + cell $or $or$ls180.v:4590$668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4590$667_Y + connect \B \main_sdphy_dataw_crcr_converter_source_ready + connect \Y $or$ls180.v:4590$668_Y + end + attribute \src "ls180.v:4593.48-4593.130" + cell $or $or$ls180.v:4593$671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4593$670_Y + connect \B \main_sdphy_dataw_crcr_buf_source_ready + connect \Y $or$ls180.v:4593$671_Y + end + attribute \src "ls180.v:4724.55-4724.149" + cell $or $or$ls180.v:4724$683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4724$682_Y + connect \B \main_sdphy_datar_datar_converter_source_ready + connect \Y $or$ls180.v:4724$683_Y + end + attribute \src "ls180.v:4727.49-4727.133" + cell $or $or$ls180.v:4727$686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4727$685_Y + connect \B \main_sdphy_datar_datar_buf_source_ready + connect \Y $or$ls180.v:4727$686_Y + end + attribute \src "ls180.v:5356.80-5356.151" + cell $or $or$ls180.v:5356$981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_writable + connect \B \main_sdblock2mem_fifo_replace + connect \Y $or$ls180.v:5356$981_Y + end + attribute \src "ls180.v:5367.49-5367.131" + cell $or $or$ls180.v:5367$987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:5367$986_Y + connect \B \main_sdblock2mem_converter_source_ready + connect \Y $or$ls180.v:5367$987_Y + end + attribute \src "ls180.v:5564.80-5564.151" + cell $or $or$ls180.v:5564$1012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_writable + connect \B \main_sdmem2block_fifo_replace + connect \Y $or$ls180.v:5564$1012_Y + end + attribute \src "ls180.v:5738.33-5738.102" + cell $or $or$ls180.v:5738$1060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_err + connect \B \main_libresocsim_libresoc_xics_icp_err + connect \Y $or$ls180.v:5738$1060_Y + end + attribute \src "ls180.v:5738.32-5738.144" + cell $or $or$ls180.v:5738$1061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5738$1060_Y + connect \B \main_libresocsim_libresoc_xics_ics_err + connect \Y $or$ls180.v:5738$1061_Y + end + attribute \src "ls180.v:5738.31-5738.165" + cell $or $or$ls180.v:5738$1062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5738$1061_Y + connect \B \main_wb_sdram_err + connect \Y $or$ls180.v:5738$1062_Y + end + attribute \src "ls180.v:5738.30-5738.201" + cell $or $or$ls180.v:5738$1063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5738$1062_Y + connect \B \builder_libresocsim_wishbone_err + connect \Y $or$ls180.v:5738$1063_Y + end + attribute \src "ls180.v:5744.28-5744.97" + cell $or $or$ls180.v:5744$1068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_ack + connect \B \main_libresocsim_libresoc_xics_icp_ack + connect \Y $or$ls180.v:5744$1068_Y + end + attribute \src "ls180.v:5744.27-5744.139" + cell $or $or$ls180.v:5744$1069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5744$1068_Y + connect \B \main_libresocsim_libresoc_xics_ics_ack + connect \Y $or$ls180.v:5744$1069_Y + end + attribute \src "ls180.v:5744.26-5744.160" + cell $or $or$ls180.v:5744$1070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5744$1069_Y + connect \B \main_wb_sdram_ack + connect \Y $or$ls180.v:5744$1070_Y + end + attribute \src "ls180.v:5744.25-5744.196" + cell $or $or$ls180.v:5744$1071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5744$1070_Y + connect \B \builder_libresocsim_wishbone_ack + connect \Y $or$ls180.v:5744$1071_Y + end + attribute \src "ls180.v:5745.30-5745.169" + cell $or $or$ls180.v:5745$1074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $and$ls180.v:5745$1072_Y + connect \B $and$ls180.v:5745$1073_Y + connect \Y $or$ls180.v:5745$1074_Y + end + attribute \src "ls180.v:5745.29-5745.246" + cell $or $or$ls180.v:5745$1076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$ls180.v:5745$1074_Y + connect \B $and$ls180.v:5745$1075_Y + connect \Y $or$ls180.v:5745$1076_Y + end + attribute \src "ls180.v:5745.28-5745.302" + cell $or $or$ls180.v:5745$1078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$ls180.v:5745$1076_Y + connect \B $and$ls180.v:5745$1077_Y + connect \Y $or$ls180.v:5745$1078_Y + end + attribute \src "ls180.v:5745.27-5745.373" + cell $or $or$ls180.v:5745$1080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$ls180.v:5745$1078_Y + connect \B $and$ls180.v:5745$1079_Y + connect \Y $or$ls180.v:5745$1080_Y + end + attribute \src "ls180.v:6499.55-6499.124" + cell $or $or$ls180.v:6499$2226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \builder_interface0_bank_bus_dat_r + connect \B \builder_interface1_bank_bus_dat_r + connect \Y $or$ls180.v:6499$2226_Y + end + attribute \src "ls180.v:6499.54-6499.161" + cell $or $or$ls180.v:6499$2227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6499$2226_Y + connect \B \builder_interface2_bank_bus_dat_r + connect \Y $or$ls180.v:6499$2227_Y + end + attribute \src "ls180.v:6499.53-6499.198" + cell $or $or$ls180.v:6499$2228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6499$2227_Y + connect \B \builder_interface3_bank_bus_dat_r + connect \Y $or$ls180.v:6499$2228_Y + end + attribute \src "ls180.v:6499.52-6499.235" + cell $or $or$ls180.v:6499$2229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6499$2228_Y + connect \B \builder_interface4_bank_bus_dat_r + connect \Y $or$ls180.v:6499$2229_Y + end + attribute \src "ls180.v:6499.51-6499.272" + cell $or $or$ls180.v:6499$2230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6499$2229_Y + connect \B \builder_interface5_bank_bus_dat_r + connect \Y $or$ls180.v:6499$2230_Y + end + attribute \src "ls180.v:6499.50-6499.309" + cell $or $or$ls180.v:6499$2231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6499$2230_Y + connect \B \builder_interface6_bank_bus_dat_r + connect \Y $or$ls180.v:6499$2231_Y + end + attribute \src "ls180.v:6499.49-6499.346" + cell $or $or$ls180.v:6499$2232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6499$2231_Y + connect \B \builder_interface7_bank_bus_dat_r + connect \Y $or$ls180.v:6499$2232_Y + end + attribute \src "ls180.v:6499.48-6499.383" + cell $or $or$ls180.v:6499$2233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6499$2232_Y + connect \B \builder_interface8_bank_bus_dat_r + connect \Y $or$ls180.v:6499$2233_Y + end + attribute \src "ls180.v:6499.47-6499.420" + cell $or $or$ls180.v:6499$2234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6499$2233_Y + connect \B \builder_interface9_bank_bus_dat_r + connect \Y $or$ls180.v:6499$2234_Y + end + attribute \src "ls180.v:6499.46-6499.458" + cell $or $or$ls180.v:6499$2235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6499$2234_Y + connect \B \builder_interface10_bank_bus_dat_r + connect \Y $or$ls180.v:6499$2235_Y + end + attribute \src "ls180.v:6499.45-6499.496" + cell $or $or$ls180.v:6499$2236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6499$2235_Y + connect \B \builder_interface11_bank_bus_dat_r + connect \Y $or$ls180.v:6499$2236_Y + end + attribute \src "ls180.v:6499.44-6499.534" + cell $or $or$ls180.v:6499$2237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6499$2236_Y + connect \B \builder_interface12_bank_bus_dat_r + connect \Y $or$ls180.v:6499$2237_Y + end + attribute \src "ls180.v:6499.43-6499.572" + cell $or $or$ls180.v:6499$2238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6499$2237_Y + connect \B \builder_interface13_bank_bus_dat_r + connect \Y $or$ls180.v:6499$2238_Y + end + attribute \src "ls180.v:6499.42-6499.610" + cell $or $or$ls180.v:6499$2239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6499$2238_Y + connect \B \builder_interface14_bank_bus_dat_r + connect \Y $or$ls180.v:6499$2239_Y + end + attribute \src "ls180.v:6826.90-6826.179" + cell $or $or$ls180.v:6826$2264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:6826$2263_Y + connect \Y $or$ls180.v:6826$2264_Y + end + attribute \src "ls180.v:6826.89-6826.254" + cell $or $or$ls180.v:6826$2267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6826$2264_Y + connect \B $and$ls180.v:6826$2266_Y + connect \Y $or$ls180.v:6826$2267_Y + end + attribute \src "ls180.v:6826.88-6826.329" + cell $or $or$ls180.v:6826$2270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6826$2267_Y + connect \B $and$ls180.v:6826$2269_Y + connect \Y $or$ls180.v:6826$2270_Y + end + attribute \src "ls180.v:6850.90-6850.179" + cell $or $or$ls180.v:6850$2280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:6850$2279_Y + connect \Y $or$ls180.v:6850$2280_Y + end + attribute \src "ls180.v:6850.89-6850.254" + cell $or $or$ls180.v:6850$2283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6850$2280_Y + connect \B $and$ls180.v:6850$2282_Y + connect \Y $or$ls180.v:6850$2283_Y + end + attribute \src "ls180.v:6850.88-6850.329" + cell $or $or$ls180.v:6850$2286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6850$2283_Y + connect \B $and$ls180.v:6850$2285_Y + connect \Y $or$ls180.v:6850$2286_Y + end + attribute \src "ls180.v:6874.90-6874.179" + cell $or $or$ls180.v:6874$2296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:6874$2295_Y + connect \Y $or$ls180.v:6874$2296_Y + end + attribute \src "ls180.v:6874.89-6874.254" + cell $or $or$ls180.v:6874$2299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6874$2296_Y + connect \B $and$ls180.v:6874$2298_Y + connect \Y $or$ls180.v:6874$2299_Y + end + attribute \src "ls180.v:6874.88-6874.329" + cell $or $or$ls180.v:6874$2302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6874$2299_Y + connect \B $and$ls180.v:6874$2301_Y + connect \Y $or$ls180.v:6874$2302_Y + end + attribute \src "ls180.v:6898.90-6898.179" + cell $or $or$ls180.v:6898$2312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:6898$2311_Y + connect \Y $or$ls180.v:6898$2312_Y + end + attribute \src "ls180.v:6898.89-6898.254" + cell $or $or$ls180.v:6898$2315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6898$2312_Y + connect \B $and$ls180.v:6898$2314_Y + connect \Y $or$ls180.v:6898$2315_Y + end + attribute \src "ls180.v:6898.88-6898.329" + cell $or $or$ls180.v:6898$2318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6898$2315_Y + connect \B $and$ls180.v:6898$2317_Y + connect \Y $or$ls180.v:6898$2318_Y + end + attribute \src "ls180.v:7412.20-7412.71" + cell $or $or$ls180.v:7412$2375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [0] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7412$2375_Y + end + attribute \src "ls180.v:7413.20-7413.71" + cell $or $or$ls180.v:7413$2376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [1] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7413$2376_Y + end + attribute \src "ls180.v:7414.20-7414.71" + cell $or $or$ls180.v:7414$2377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [2] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7414$2377_Y + end + attribute \src "ls180.v:7415.20-7415.71" + cell $or $or$ls180.v:7415$2378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [3] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7415$2378_Y + end + attribute \src "ls180.v:7416.20-7416.71" + cell $or $or$ls180.v:7416$2379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [4] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7416$2379_Y + end + attribute \src "ls180.v:7417.20-7417.71" + cell $or $or$ls180.v:7417$2380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [5] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7417$2380_Y + end + attribute \src "ls180.v:7418.20-7418.71" + cell $or $or$ls180.v:7418$2381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [6] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7418$2381_Y + end + attribute \src "ls180.v:7419.20-7419.71" + cell $or $or$ls180.v:7419$2382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [7] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7419$2382_Y + end + attribute \src "ls180.v:7420.20-7420.71" + cell $or $or$ls180.v:7420$2383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [8] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7420$2383_Y + end + attribute \src "ls180.v:7421.20-7421.71" + cell $or $or$ls180.v:7421$2384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [9] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7421$2384_Y + end + attribute \src "ls180.v:7422.21-7422.73" + cell $or $or$ls180.v:7422$2385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [10] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7422$2385_Y + end + attribute \src "ls180.v:7423.21-7423.73" + cell $or $or$ls180.v:7423$2386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [11] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7423$2386_Y + end + attribute \src "ls180.v:7424.21-7424.73" + cell $or $or$ls180.v:7424$2387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [12] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7424$2387_Y + end + attribute \src "ls180.v:7425.21-7425.73" + cell $or $or$ls180.v:7425$2388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [13] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7425$2388_Y + end + attribute \src "ls180.v:7426.21-7426.73" + cell $or $or$ls180.v:7426$2389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [14] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7426$2389_Y + end + attribute \src "ls180.v:7427.21-7427.73" + cell $or $or$ls180.v:7427$2390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [15] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7427$2390_Y + end + attribute \src "ls180.v:7428.21-7428.73" + cell $or $or$ls180.v:7428$2391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [16] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7428$2391_Y + end + attribute \src "ls180.v:7429.21-7429.73" + cell $or $or$ls180.v:7429$2392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [17] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7429$2392_Y + end + attribute \src "ls180.v:7430.21-7430.73" + cell $or $or$ls180.v:7430$2393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [18] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7430$2393_Y + end + attribute \src "ls180.v:7431.21-7431.73" + cell $or $or$ls180.v:7431$2394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [19] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7431$2394_Y + end + attribute \src "ls180.v:7432.21-7432.73" + cell $or $or$ls180.v:7432$2395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [20] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7432$2395_Y + end + attribute \src "ls180.v:7433.21-7433.73" + cell $or $or$ls180.v:7433$2396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [21] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7433$2396_Y + end + attribute \src "ls180.v:7434.21-7434.73" + cell $or $or$ls180.v:7434$2397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [22] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7434$2397_Y + end + attribute \src "ls180.v:7435.21-7435.73" + cell $or $or$ls180.v:7435$2398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [23] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7435$2398_Y + end + attribute \src "ls180.v:7436.21-7436.73" + cell $or $or$ls180.v:7436$2399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [24] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7436$2399_Y + end + attribute \src "ls180.v:7437.21-7437.73" + cell $or $or$ls180.v:7437$2400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [25] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7437$2400_Y + end + attribute \src "ls180.v:7438.21-7438.73" + cell $or $or$ls180.v:7438$2401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [26] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7438$2401_Y + end + attribute \src "ls180.v:7439.21-7439.73" + cell $or $or$ls180.v:7439$2402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [27] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7439$2402_Y + end + attribute \src "ls180.v:7440.21-7440.73" + cell $or $or$ls180.v:7440$2403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [28] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7440$2403_Y + end + attribute \src "ls180.v:7441.21-7441.73" + cell $or $or$ls180.v:7441$2404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [29] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7441$2404_Y + end + attribute \src "ls180.v:7442.21-7442.73" + cell $or $or$ls180.v:7442$2405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [30] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7442$2405_Y + end + attribute \src "ls180.v:7443.21-7443.73" + cell $or $or$ls180.v:7443$2406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [31] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7443$2406_Y + end + attribute \src "ls180.v:7444.21-7444.73" + cell $or $or$ls180.v:7444$2407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [32] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7444$2407_Y + end + attribute \src "ls180.v:7445.21-7445.73" + cell $or $or$ls180.v:7445$2408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [33] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7445$2408_Y + end + attribute \src "ls180.v:7446.21-7446.73" + cell $or $or$ls180.v:7446$2409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [34] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7446$2409_Y + end + attribute \src "ls180.v:7447.21-7447.73" + cell $or $or$ls180.v:7447$2410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [35] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7447$2410_Y + end + attribute \src "ls180.v:7448.7-7448.93" + cell $or $or$ls180.v:7448$2411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface0_converted_interface_ack + connect \B \main_libresocsim_converter0_skip + connect \Y $or$ls180.v:7448$2411_Y + end + attribute \src "ls180.v:7459.7-7459.93" + cell $or $or$ls180.v:7459$2412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface1_converted_interface_ack + connect \B \main_libresocsim_converter1_skip + connect \Y $or$ls180.v:7459$2412_Y + end + attribute \src "ls180.v:7470.7-7470.93" + cell $or $or$ls180.v:7470$2413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface2_converted_interface_ack + connect \B \main_libresocsim_converter2_skip + connect \Y $or$ls180.v:7470$2413_Y + end + attribute \src "ls180.v:7599.7-7599.107" + cell $or $or$ls180.v:7599$2449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7599$2448_Y + connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$ls180.v:7599$2449_Y + end + attribute \src "ls180.v:7645.7-7645.107" + cell $or $or$ls180.v:7645$2465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7645$2464_Y + connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$ls180.v:7645$2465_Y + end + attribute \src "ls180.v:7691.7-7691.107" + cell $or $or$ls180.v:7691$2481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7691$2480_Y + connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$ls180.v:7691$2481_Y + end + attribute \src "ls180.v:7737.7-7737.107" + cell $or $or$ls180.v:7737$2497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7737$2496_Y + connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$ls180.v:7737$2497_Y + end + attribute \src "ls180.v:7925.40-7925.125" + cell $or $or$ls180.v:7925$2518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:7925$2517_Y + connect \Y $or$ls180.v:7925$2518_Y + end + attribute \src "ls180.v:7925.39-7925.207" + cell $or $or$ls180.v:7925$2521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7925$2518_Y + connect \B $and$ls180.v:7925$2520_Y + connect \Y $or$ls180.v:7925$2521_Y + end + attribute \src "ls180.v:7925.38-7925.289" + cell $or $or$ls180.v:7925$2524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7925$2521_Y + connect \B $and$ls180.v:7925$2523_Y + connect \Y $or$ls180.v:7925$2524_Y + end + attribute \src "ls180.v:7925.37-7925.371" + cell $or $or$ls180.v:7925$2527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7925$2524_Y + connect \B $and$ls180.v:7925$2526_Y + connect \Y $or$ls180.v:7925$2527_Y + end + attribute \src "ls180.v:7926.41-7926.126" + cell $or $or$ls180.v:7926$2530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:7926$2529_Y + connect \Y $or$ls180.v:7926$2530_Y + end + attribute \src "ls180.v:7926.40-7926.208" + cell $or $or$ls180.v:7926$2533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7926$2530_Y + connect \B $and$ls180.v:7926$2532_Y + connect \Y $or$ls180.v:7926$2533_Y + end + attribute \src "ls180.v:7926.39-7926.290" + cell $or $or$ls180.v:7926$2536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7926$2533_Y + connect \B $and$ls180.v:7926$2535_Y + connect \Y $or$ls180.v:7926$2536_Y + end + attribute \src "ls180.v:7926.38-7926.372" + cell $or $or$ls180.v:7926$2539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7926$2536_Y + connect \B $and$ls180.v:7926$2538_Y + connect \Y $or$ls180.v:7926$2539_Y + end + attribute \src "ls180.v:7930.7-7930.49" + cell $or $or$ls180.v:7930$2540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_ack + connect \B \main_converter_skip + connect \Y $or$ls180.v:7930$2540_Y + end + attribute \src "ls180.v:8093.22-8093.74" + cell $or $or$ls180.v:8093$2588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8093$2586_Y + connect \B $not$ls180.v:8093$2587_Y + connect \Y $or$ls180.v:8093$2588_Y + end + attribute \src "ls180.v:8161.32-8161.85" + cell $or $or$ls180.v:8161$2600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_start + connect \B \main_sdphy_cmdr_cmdr_run + connect \Y $or$ls180.v:8161$2600_Y + end + attribute \src "ls180.v:8167.8-8167.97" + cell $or $or$ls180.v:8167$2602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8167$2601_Y + connect \B \main_sdphy_cmdr_cmdr_converter_sink_last + connect \Y $or$ls180.v:8167$2602_Y + end + attribute \src "ls180.v:8184.52-8184.139" + cell $or $or$ls180.v:8184$2607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_first + connect \B \main_sdphy_cmdr_cmdr_converter_source_first + connect \Y $or$ls180.v:8184$2607_Y + end + attribute \src "ls180.v:8185.51-8185.136" + cell $or $or$ls180.v:8185$2608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_last + connect \B \main_sdphy_cmdr_cmdr_converter_source_last + connect \Y $or$ls180.v:8185$2608_Y + end + attribute \src "ls180.v:8219.7-8219.87" + cell $or $or$ls180.v:8219$2611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8219$2610_Y + connect \B \main_sdphy_cmdr_cmdr_buf_source_ready + connect \Y $or$ls180.v:8219$2611_Y + end + attribute \src "ls180.v:8242.33-8242.88" + cell $or $or$ls180.v:8242$2612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_start + connect \B \main_sdphy_dataw_crcr_run + connect \Y $or$ls180.v:8242$2612_Y + end + attribute \src "ls180.v:8248.8-8248.99" + cell $or $or$ls180.v:8248$2614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8248$2613_Y + connect \B \main_sdphy_dataw_crcr_converter_sink_last + connect \Y $or$ls180.v:8248$2614_Y + end + attribute \src "ls180.v:8265.53-8265.142" + cell $or $or$ls180.v:8265$2619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_first + connect \B \main_sdphy_dataw_crcr_converter_source_first + connect \Y $or$ls180.v:8265$2619_Y + end + attribute \src "ls180.v:8266.52-8266.139" + cell $or $or$ls180.v:8266$2620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_last + connect \B \main_sdphy_dataw_crcr_converter_source_last + connect \Y $or$ls180.v:8266$2620_Y + end + attribute \src "ls180.v:8300.7-8300.89" + cell $or $or$ls180.v:8300$2623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8300$2622_Y + connect \B \main_sdphy_dataw_crcr_buf_source_ready + connect \Y $or$ls180.v:8300$2623_Y + end + attribute \src "ls180.v:8321.34-8321.91" + cell $or $or$ls180.v:8321$2624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_start + connect \B \main_sdphy_datar_datar_run + connect \Y $or$ls180.v:8321$2624_Y + end + attribute \src "ls180.v:8327.8-8327.101" + cell $or $or$ls180.v:8327$2626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8327$2625_Y + connect \B \main_sdphy_datar_datar_converter_sink_last + connect \Y $or$ls180.v:8327$2626_Y + end + attribute \src "ls180.v:8344.54-8344.145" + cell $or $or$ls180.v:8344$2631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_first + connect \B \main_sdphy_datar_datar_converter_source_first + connect \Y $or$ls180.v:8344$2631_Y + end + attribute \src "ls180.v:8345.53-8345.142" + cell $or $or$ls180.v:8345$2632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_last + connect \B \main_sdphy_datar_datar_converter_source_last + connect \Y $or$ls180.v:8345$2632_Y + end + attribute \src "ls180.v:8361.7-8361.91" + cell $or $or$ls180.v:8361$2635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8361$2634_Y + connect \B \main_sdphy_datar_datar_buf_source_ready + connect \Y $or$ls180.v:8361$2635_Y + end + attribute \src "ls180.v:8550.8-8550.89" + cell $or $or$ls180.v:8550$2659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8550$2658_Y + connect \B \main_sdblock2mem_converter_sink_last + connect \Y $or$ls180.v:8550$2659_Y + end + attribute \src "ls180.v:8567.48-8567.127" + cell $or $or$ls180.v:8567$2664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_first + connect \B \main_sdblock2mem_converter_source_first + connect \Y $or$ls180.v:8567$2664_Y + end + attribute \src "ls180.v:8568.47-8568.124" + cell $or $or$ls180.v:8568$2665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_last + connect \B \main_sdblock2mem_converter_source_last + connect \Y $or$ls180.v:8568$2665_Y + end + attribute \src "ls180.v:8641.21-8641.65" + cell $or $or$ls180.v:8641$2683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8641$2681_Y + connect \B $not$ls180.v:8641$2682_Y + connect \Y $or$ls180.v:8641$2683_Y + end + attribute \src "ls180.v:3162.46-3162.94" + cell $sshl $sshl$ls180.v:3162$83 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine0_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3162$83_Y + end + attribute \src "ls180.v:3319.46-3319.94" + cell $sshl $sshl$ls180.v:3319$113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine1_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3319$113_Y + end + attribute \src "ls180.v:3476.46-3476.94" + cell $sshl $sshl$ls180.v:3476$143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine2_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3476$143_Y + end + attribute \src "ls180.v:3633.46-3633.94" + cell $sshl $sshl$ls180.v:3633$173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine3_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3633$173_Y + end + attribute \src "ls180.v:3193.63-3193.122" + cell $sub $sub$ls180.v:3193$96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3193$96_Y + end + attribute \src "ls180.v:3350.63-3350.122" + cell $sub $sub$ls180.v:3350$126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3350$126_Y + end + attribute \src "ls180.v:3507.63-3507.122" + cell $sub $sub$ls180.v:3507$156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3507$156_Y + end + attribute \src "ls180.v:3664.63-3664.122" + cell $sub $sub$ls180.v:3664$186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3664$186_Y + end + attribute \src "ls180.v:4070.38-4070.75" + cell $sub $sub$ls180.v:4070$540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 30 + parameter \B_SIGNED 0 + parameter \B_WIDTH 31 + parameter \Y_WIDTH 31 + connect \A \main_litedram_wb_adr + connect \B 31'1001000000000000000000000000000 + connect \Y $sub$ls180.v:4070$540_Y + end + attribute \src "ls180.v:4156.36-4156.68" + cell $sub $sub$ls180.v:4156$585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:4156$585_Y + end + attribute \src "ls180.v:4186.36-4186.68" + cell $sub $sub$ls180.v:4186$596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:4186$596_Y + end + attribute \src "ls180.v:4211.69-4211.110" + cell $sub $sub$ls180.v:4211$602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 15 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spi_master_clk_divider0 [15:1] + connect \B 1'1 + connect \Y $sub$ls180.v:4211$602_Y + end + attribute \src "ls180.v:4212.69-4212.104" + cell $sub $sub$ls180.v:4212$604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spi_master_clk_divider0 + connect \B 1'1 + connect \Y $sub$ls180.v:4212$604_Y + end + attribute \src "ls180.v:4239.36-4239.66" + cell $sub $sub$ls180.v:4239$608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_spi_master_length0 + connect \B 1'1 + connect \Y $sub$ls180.v:4239$608_Y + end + attribute \src "ls180.v:4493.60-4493.90" + cell $sub $sub$ls180.v:4493$652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4493$652_Y + end + attribute \src "ls180.v:4504.62-4504.104" + cell $sub $sub$ls180.v:4504$654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_sink_payload_length + connect \B 1'1 + connect \Y $sub$ls180.v:4504$654_Y + end + attribute \src "ls180.v:4521.60-4521.90" + cell $sub $sub$ls180.v:4521$658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4521$658_Y + end + attribute \src "ls180.v:4750.62-4750.93" + cell $sub $sub$ls180.v:4750$688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4750$688_Y + end + attribute \src "ls180.v:4755.62-4755.93" + cell $sub $sub$ls180.v:4755$689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4755$689_Y + end + attribute \src "ls180.v:4766.64-4766.122" + cell $sub $sub$ls180.v:4766$692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A $add$ls180.v:4766$691_Y + connect \B 1'1 + connect \Y $sub$ls180.v:4766$692_Y + end + attribute \src "ls180.v:4787.62-4787.93" + cell $sub $sub$ls180.v:4787$695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4787$695_Y + end + attribute \src "ls180.v:5249.37-5249.75" + cell $sub $sub$ls180.v:5249$968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5249$968_Y + end + attribute \src "ls180.v:5264.62-5264.100" + cell $sub $sub$ls180.v:5264$971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5264$971_Y + end + attribute \src "ls180.v:5275.39-5275.77" + cell $sub $sub$ls180.v:5275$976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5275$976_Y + end + attribute \src "ls180.v:5350.40-5350.76" + cell $sub $sub$ls180.v:5350$980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:5350$980_Y + end + attribute \src "ls180.v:5399.56-5399.104" + cell $sub $sub$ls180.v:5399$994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_length + connect \B 1'1 + connect \Y $sub$ls180.v:5399$994_Y + end + attribute \src "ls180.v:5489.71-5489.105" + cell $sub $sub$ls180.v:5489$1000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_length + connect \B 1'1 + connect \Y $sub$ls180.v:5489$1000_Y + end + attribute \src "ls180.v:5558.40-5558.76" + cell $sub $sub$ls180.v:5558$1011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:5558$1011_Y + end + attribute \src "ls180.v:5577.61-5577.98" + cell $sub $sub$ls180.v:5577$1017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 15 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \libresocsim_clk_divider0 [15:1] + connect \B 1'1 + connect \Y $sub$ls180.v:5577$1017_Y + end + attribute \src "ls180.v:5578.61-5578.92" + cell $sub $sub$ls180.v:5578$1019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \libresocsim_clk_divider0 + connect \B 1'1 + connect \Y $sub$ls180.v:5578$1019_Y + end + attribute \src "ls180.v:5606.32-5606.58" + cell $sub $sub$ls180.v:5606$1023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \libresocsim_length0 + connect \B 1'1 + connect \Y $sub$ls180.v:5606$1023_Y + end + attribute \src "ls180.v:7494.31-7494.60" + cell $sub $sub$ls180.v:7494$2420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_libresocsim_value + connect \B 1'1 + connect \Y $sub$ls180.v:7494$2420_Y + end + attribute \src "ls180.v:7515.31-7515.61" + cell $sub $sub$ls180.v:7515$2425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdram_timer_count1 + connect \B 1'1 + connect \Y $sub$ls180.v:7515$2425_Y + end + attribute \src "ls180.v:7521.34-7521.67" + cell $sub $sub$ls180.v:7521$2426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_postponer_count + connect \B 1'1 + connect \Y $sub$ls180.v:7521$2426_Y + end + attribute \src "ls180.v:7532.36-7532.69" + cell $sub $sub$ls180.v:7532$2429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'1 + connect \Y $sub$ls180.v:7532$2429_Y + end + attribute \src "ls180.v:7596.59-7596.116" + cell $sub $sub$ls180.v:7596$2447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7596$2447_Y + end + attribute \src "ls180.v:7615.46-7615.90" + cell $sub $sub$ls180.v:7615$2451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7615$2451_Y + end + attribute \src "ls180.v:7642.59-7642.116" + cell $sub $sub$ls180.v:7642$2463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7642$2463_Y + end + attribute \src "ls180.v:7661.46-7661.90" + cell $sub $sub$ls180.v:7661$2467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7661$2467_Y + end + attribute \src "ls180.v:7688.59-7688.116" + cell $sub $sub$ls180.v:7688$2479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7688$2479_Y + end + attribute \src "ls180.v:7707.46-7707.90" + cell $sub $sub$ls180.v:7707$2483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7707$2483_Y + end + attribute \src "ls180.v:7734.59-7734.116" + cell $sub $sub$ls180.v:7734$2495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7734$2495_Y + end + attribute \src "ls180.v:7753.46-7753.90" + cell $sub $sub$ls180.v:7753$2499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7753$2499_Y + end + attribute \src "ls180.v:7764.25-7764.48" + cell $sub $sub$ls180.v:7764$2503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdram_time0 + connect \B 1'1 + connect \Y $sub$ls180.v:7764$2503_Y + end + attribute \src "ls180.v:7771.25-7771.48" + cell $sub $sub$ls180.v:7771$2506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_time1 + connect \B 1'1 + connect \Y $sub$ls180.v:7771$2506_Y + end + attribute \src "ls180.v:7903.33-7903.64" + cell $sub $sub$ls180.v:7903$2511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7903$2511_Y + end + attribute \src "ls180.v:7918.33-7918.64" + cell $sub $sub$ls180.v:7918$2514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_twtrcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7918$2514_Y + end + attribute \src "ls180.v:8045.33-8045.64" + cell $sub $sub$ls180.v:8045$2573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'1 + connect \Y $sub$ls180.v:8045$2573_Y + end + attribute \src "ls180.v:8067.33-8067.64" + cell $sub $sub$ls180.v:8067$2584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'1 + connect \Y $sub$ls180.v:8067$2584_Y + end + attribute \src "ls180.v:8102.33-8102.64" + cell $sub $sub$ls180.v:8102$2589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spi_master_mosi_sel + connect \B 1'1 + connect \Y $sub$ls180.v:8102$2589_Y + end + attribute \src "ls180.v:8126.30-8126.53" + cell $sub $sub$ls180.v:8126$2592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm0_period + connect \B 1'1 + connect \Y $sub$ls180.v:8126$2592_Y + end + attribute \src "ls180.v:8140.30-8140.53" + cell $sub $sub$ls180.v:8140$2596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm1_period + connect \B 1'1 + connect \Y $sub$ls180.v:8140$2596_Y + end + attribute \src "ls180.v:8543.36-8543.70" + cell $sub $sub$ls180.v:8543$2657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'1 + connect \Y $sub$ls180.v:8543$2657_Y + end + attribute \src "ls180.v:8629.36-8629.70" + cell $sub $sub$ls180.v:8629$2679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdmem2block_fifo_level + connect \B 1'1 + connect \Y $sub$ls180.v:8629$2679_Y + end + attribute \src "ls180.v:8650.29-8650.56" + cell $sub $sub$ls180.v:8650$2684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \libresocsim_mosi_sel + connect \B 1'1 + connect \Y $sub$ls180.v:8650$2684_Y + end + attribute \src "ls180.v:8777.22-8777.42" + cell $sub $sub$ls180.v:8777$2691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 20 + connect \A \builder_count + connect \B 1'1 + connect \Y $sub$ls180.v:8777$2691_Y + end + attribute \src "ls180.v:4847.353-4847.425" + cell $xor $xor$ls180.v:4847$702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [39] + connect \B \main_sdcore_crc7_inserter_crcreg0 [6] + connect \Y $xor$ls180.v:4847$702_Y + end + attribute \src "ls180.v:4847.200-4847.272" + cell $xor $xor$ls180.v:4847$703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [39] + connect \B \main_sdcore_crc7_inserter_crcreg0 [6] + connect \Y $xor$ls180.v:4847$703_Y + end + attribute \src "ls180.v:4847.160-4847.273" + cell $xor $xor$ls180.v:4847$704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg0 [2] + connect \B $xor$ls180.v:4847$703_Y + connect \Y $xor$ls180.v:4847$704_Y + end + attribute \src "ls180.v:4848.353-4848.425" + cell $xor $xor$ls180.v:4848$705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [38] + connect \B \main_sdcore_crc7_inserter_crcreg1 [6] + connect \Y $xor$ls180.v:4848$705_Y + end + attribute \src "ls180.v:4848.200-4848.272" + cell $xor $xor$ls180.v:4848$706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [38] + connect \B \main_sdcore_crc7_inserter_crcreg1 [6] + connect \Y $xor$ls180.v:4848$706_Y + end + attribute \src "ls180.v:4848.160-4848.273" + cell $xor $xor$ls180.v:4848$707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg1 [2] + connect \B $xor$ls180.v:4848$706_Y + connect \Y $xor$ls180.v:4848$707_Y + end + attribute \src "ls180.v:4849.353-4849.425" + cell $xor $xor$ls180.v:4849$708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [37] + connect \B \main_sdcore_crc7_inserter_crcreg2 [6] + connect \Y $xor$ls180.v:4849$708_Y + end + attribute \src "ls180.v:4849.200-4849.272" + cell $xor $xor$ls180.v:4849$709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [37] + connect \B \main_sdcore_crc7_inserter_crcreg2 [6] + connect \Y $xor$ls180.v:4849$709_Y + end + attribute \src "ls180.v:4849.160-4849.273" + cell $xor $xor$ls180.v:4849$710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg2 [2] + connect \B $xor$ls180.v:4849$709_Y + connect \Y $xor$ls180.v:4849$710_Y + end + attribute \src "ls180.v:4850.353-4850.425" + cell $xor $xor$ls180.v:4850$711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [36] + connect \B \main_sdcore_crc7_inserter_crcreg3 [6] + connect \Y $xor$ls180.v:4850$711_Y + end + attribute \src "ls180.v:4850.200-4850.272" + cell $xor $xor$ls180.v:4850$712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [36] + connect \B \main_sdcore_crc7_inserter_crcreg3 [6] + connect \Y $xor$ls180.v:4850$712_Y + end + attribute \src "ls180.v:4850.160-4850.273" + cell $xor $xor$ls180.v:4850$713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg3 [2] + connect \B $xor$ls180.v:4850$712_Y + connect \Y $xor$ls180.v:4850$713_Y + end + attribute \src "ls180.v:4851.353-4851.425" + cell $xor $xor$ls180.v:4851$714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [35] + connect \B \main_sdcore_crc7_inserter_crcreg4 [6] + connect \Y $xor$ls180.v:4851$714_Y + end + attribute \src "ls180.v:4851.200-4851.272" + cell $xor $xor$ls180.v:4851$715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [35] + connect \B \main_sdcore_crc7_inserter_crcreg4 [6] + connect \Y $xor$ls180.v:4851$715_Y + end + attribute \src "ls180.v:4851.160-4851.273" + cell $xor $xor$ls180.v:4851$716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg4 [2] + connect \B $xor$ls180.v:4851$715_Y + connect \Y $xor$ls180.v:4851$716_Y + end + attribute \src "ls180.v:4852.353-4852.425" + cell $xor $xor$ls180.v:4852$717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [34] + connect \B \main_sdcore_crc7_inserter_crcreg5 [6] + connect \Y $xor$ls180.v:4852$717_Y + end + attribute \src "ls180.v:4852.200-4852.272" + cell $xor $xor$ls180.v:4852$718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [34] + connect \B \main_sdcore_crc7_inserter_crcreg5 [6] + connect \Y $xor$ls180.v:4852$718_Y + end + attribute \src "ls180.v:4852.160-4852.273" + cell $xor $xor$ls180.v:4852$719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg5 [2] + connect \B $xor$ls180.v:4852$718_Y + connect \Y $xor$ls180.v:4852$719_Y + end + attribute \src "ls180.v:4853.353-4853.425" + cell $xor $xor$ls180.v:4853$720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [33] + connect \B \main_sdcore_crc7_inserter_crcreg6 [6] + connect \Y $xor$ls180.v:4853$720_Y + end + attribute \src "ls180.v:4853.200-4853.272" + cell $xor $xor$ls180.v:4853$721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [33] + connect \B \main_sdcore_crc7_inserter_crcreg6 [6] + connect \Y $xor$ls180.v:4853$721_Y + end + attribute \src "ls180.v:4853.160-4853.273" + cell $xor $xor$ls180.v:4853$722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg6 [2] + connect \B $xor$ls180.v:4853$721_Y + connect \Y $xor$ls180.v:4853$722_Y + end + attribute \src "ls180.v:4854.353-4854.425" + cell $xor $xor$ls180.v:4854$723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [32] + connect \B \main_sdcore_crc7_inserter_crcreg7 [6] + connect \Y $xor$ls180.v:4854$723_Y + end + attribute \src "ls180.v:4854.200-4854.272" + cell $xor $xor$ls180.v:4854$724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [32] + connect \B \main_sdcore_crc7_inserter_crcreg7 [6] + connect \Y $xor$ls180.v:4854$724_Y + end + attribute \src "ls180.v:4854.160-4854.273" + cell $xor $xor$ls180.v:4854$725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg7 [2] + connect \B $xor$ls180.v:4854$724_Y + connect \Y $xor$ls180.v:4854$725_Y + end + attribute \src "ls180.v:4855.353-4855.425" + cell $xor $xor$ls180.v:4855$726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [31] + connect \B \main_sdcore_crc7_inserter_crcreg8 [6] + connect \Y $xor$ls180.v:4855$726_Y + end + attribute \src "ls180.v:4855.200-4855.272" + cell $xor $xor$ls180.v:4855$727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [31] + connect \B \main_sdcore_crc7_inserter_crcreg8 [6] + connect \Y $xor$ls180.v:4855$727_Y + end + attribute \src "ls180.v:4855.160-4855.273" + cell $xor $xor$ls180.v:4855$728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg8 [2] + connect \B $xor$ls180.v:4855$727_Y + connect \Y $xor$ls180.v:4855$728_Y + end + attribute \src "ls180.v:4856.354-4856.426" + cell $xor $xor$ls180.v:4856$729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [30] + connect \B \main_sdcore_crc7_inserter_crcreg9 [6] + connect \Y $xor$ls180.v:4856$729_Y + end + attribute \src "ls180.v:4856.201-4856.273" + cell $xor $xor$ls180.v:4856$730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [30] + connect \B \main_sdcore_crc7_inserter_crcreg9 [6] + connect \Y $xor$ls180.v:4856$730_Y + end + attribute \src "ls180.v:4856.161-4856.274" + cell $xor $xor$ls180.v:4856$731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg9 [2] + connect \B $xor$ls180.v:4856$730_Y + connect \Y $xor$ls180.v:4856$731_Y + end + attribute \src "ls180.v:4857.361-4857.434" + cell $xor $xor$ls180.v:4857$732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [29] + connect \B \main_sdcore_crc7_inserter_crcreg10 [6] + connect \Y $xor$ls180.v:4857$732_Y + end + attribute \src "ls180.v:4857.205-4857.278" + cell $xor $xor$ls180.v:4857$733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [29] + connect \B \main_sdcore_crc7_inserter_crcreg10 [6] + connect \Y $xor$ls180.v:4857$733_Y + end + attribute \src "ls180.v:4857.164-4857.279" + cell $xor $xor$ls180.v:4857$734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg10 [2] + connect \B $xor$ls180.v:4857$733_Y + connect \Y $xor$ls180.v:4857$734_Y + end + attribute \src "ls180.v:4858.361-4858.434" + cell $xor $xor$ls180.v:4858$735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [28] + connect \B \main_sdcore_crc7_inserter_crcreg11 [6] + connect \Y $xor$ls180.v:4858$735_Y + end + attribute \src "ls180.v:4858.205-4858.278" + cell $xor $xor$ls180.v:4858$736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [28] + connect \B \main_sdcore_crc7_inserter_crcreg11 [6] + connect \Y $xor$ls180.v:4858$736_Y + end + attribute \src "ls180.v:4858.164-4858.279" + cell $xor $xor$ls180.v:4858$737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg11 [2] + connect \B $xor$ls180.v:4858$736_Y + connect \Y $xor$ls180.v:4858$737_Y + end + attribute \src "ls180.v:4859.361-4859.434" + cell $xor $xor$ls180.v:4859$738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [27] + connect \B \main_sdcore_crc7_inserter_crcreg12 [6] + connect \Y $xor$ls180.v:4859$738_Y + end + attribute \src "ls180.v:4859.205-4859.278" + cell $xor $xor$ls180.v:4859$739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [27] + connect \B \main_sdcore_crc7_inserter_crcreg12 [6] + connect \Y $xor$ls180.v:4859$739_Y + end + attribute \src "ls180.v:4859.164-4859.279" + cell $xor $xor$ls180.v:4859$740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg12 [2] + connect \B $xor$ls180.v:4859$739_Y + connect \Y $xor$ls180.v:4859$740_Y + end + attribute \src "ls180.v:4860.361-4860.434" + cell $xor $xor$ls180.v:4860$741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [26] + connect \B \main_sdcore_crc7_inserter_crcreg13 [6] + connect \Y $xor$ls180.v:4860$741_Y + end + attribute \src "ls180.v:4860.205-4860.278" + cell $xor $xor$ls180.v:4860$742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [26] + connect \B \main_sdcore_crc7_inserter_crcreg13 [6] + connect \Y $xor$ls180.v:4860$742_Y + end + attribute \src "ls180.v:4860.164-4860.279" + cell $xor $xor$ls180.v:4860$743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg13 [2] + connect \B $xor$ls180.v:4860$742_Y + connect \Y $xor$ls180.v:4860$743_Y + end + attribute \src "ls180.v:4861.361-4861.434" + cell $xor $xor$ls180.v:4861$744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [25] + connect \B \main_sdcore_crc7_inserter_crcreg14 [6] + connect \Y $xor$ls180.v:4861$744_Y + end + attribute \src "ls180.v:4861.205-4861.278" + cell $xor $xor$ls180.v:4861$745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [25] + connect \B \main_sdcore_crc7_inserter_crcreg14 [6] + connect \Y $xor$ls180.v:4861$745_Y + end + attribute \src "ls180.v:4861.164-4861.279" + cell $xor $xor$ls180.v:4861$746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg14 [2] + connect \B $xor$ls180.v:4861$745_Y + connect \Y $xor$ls180.v:4861$746_Y + end + attribute \src "ls180.v:4862.361-4862.434" + cell $xor $xor$ls180.v:4862$747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [24] + connect \B \main_sdcore_crc7_inserter_crcreg15 [6] + connect \Y $xor$ls180.v:4862$747_Y + end + attribute \src "ls180.v:4862.205-4862.278" + cell $xor $xor$ls180.v:4862$748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [24] + connect \B \main_sdcore_crc7_inserter_crcreg15 [6] + connect \Y $xor$ls180.v:4862$748_Y + end + attribute \src "ls180.v:4862.164-4862.279" + cell $xor $xor$ls180.v:4862$749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg15 [2] + connect \B $xor$ls180.v:4862$748_Y + connect \Y $xor$ls180.v:4862$749_Y + end + attribute \src "ls180.v:4863.361-4863.434" + cell $xor $xor$ls180.v:4863$750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [23] + connect \B \main_sdcore_crc7_inserter_crcreg16 [6] + connect \Y $xor$ls180.v:4863$750_Y + end + attribute \src "ls180.v:4863.205-4863.278" + cell $xor $xor$ls180.v:4863$751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [23] + connect \B \main_sdcore_crc7_inserter_crcreg16 [6] + connect \Y $xor$ls180.v:4863$751_Y + end + attribute \src "ls180.v:4863.164-4863.279" + cell $xor $xor$ls180.v:4863$752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg16 [2] + connect \B $xor$ls180.v:4863$751_Y + connect \Y $xor$ls180.v:4863$752_Y + end + attribute \src "ls180.v:4864.361-4864.434" + cell $xor $xor$ls180.v:4864$753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [22] + connect \B \main_sdcore_crc7_inserter_crcreg17 [6] + connect \Y $xor$ls180.v:4864$753_Y + end + attribute \src "ls180.v:4864.205-4864.278" + cell $xor $xor$ls180.v:4864$754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [22] + connect \B \main_sdcore_crc7_inserter_crcreg17 [6] + connect \Y $xor$ls180.v:4864$754_Y + end + attribute \src "ls180.v:4864.164-4864.279" + cell $xor $xor$ls180.v:4864$755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg17 [2] + connect \B $xor$ls180.v:4864$754_Y + connect \Y $xor$ls180.v:4864$755_Y + end + attribute \src "ls180.v:4865.361-4865.434" + cell $xor $xor$ls180.v:4865$756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [21] + connect \B \main_sdcore_crc7_inserter_crcreg18 [6] + connect \Y $xor$ls180.v:4865$756_Y + end + attribute \src "ls180.v:4865.205-4865.278" + cell $xor $xor$ls180.v:4865$757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [21] + connect \B \main_sdcore_crc7_inserter_crcreg18 [6] + connect \Y $xor$ls180.v:4865$757_Y + end + attribute \src "ls180.v:4865.164-4865.279" + cell $xor $xor$ls180.v:4865$758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg18 [2] + connect \B $xor$ls180.v:4865$757_Y + connect \Y $xor$ls180.v:4865$758_Y + end + attribute \src "ls180.v:4866.361-4866.434" + cell $xor $xor$ls180.v:4866$759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [20] + connect \B \main_sdcore_crc7_inserter_crcreg19 [6] + connect \Y $xor$ls180.v:4866$759_Y + end + attribute \src "ls180.v:4866.205-4866.278" + cell $xor $xor$ls180.v:4866$760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [20] + connect \B \main_sdcore_crc7_inserter_crcreg19 [6] + connect \Y $xor$ls180.v:4866$760_Y + end + attribute \src "ls180.v:4866.164-4866.279" + cell $xor $xor$ls180.v:4866$761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg19 [2] + connect \B $xor$ls180.v:4866$760_Y + connect \Y $xor$ls180.v:4866$761_Y + end + attribute \src "ls180.v:4867.361-4867.434" + cell $xor $xor$ls180.v:4867$762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [19] + connect \B \main_sdcore_crc7_inserter_crcreg20 [6] + connect \Y $xor$ls180.v:4867$762_Y + end + attribute \src "ls180.v:4867.205-4867.278" + cell $xor $xor$ls180.v:4867$763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [19] + connect \B \main_sdcore_crc7_inserter_crcreg20 [6] + connect \Y $xor$ls180.v:4867$763_Y + end + attribute \src "ls180.v:4867.164-4867.279" + cell $xor $xor$ls180.v:4867$764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg20 [2] + connect \B $xor$ls180.v:4867$763_Y + connect \Y $xor$ls180.v:4867$764_Y + end + attribute \src "ls180.v:4868.361-4868.434" + cell $xor $xor$ls180.v:4868$765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [18] + connect \B \main_sdcore_crc7_inserter_crcreg21 [6] + connect \Y $xor$ls180.v:4868$765_Y + end + attribute \src "ls180.v:4868.205-4868.278" + cell $xor $xor$ls180.v:4868$766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [18] + connect \B \main_sdcore_crc7_inserter_crcreg21 [6] + connect \Y $xor$ls180.v:4868$766_Y + end + attribute \src "ls180.v:4868.164-4868.279" + cell $xor $xor$ls180.v:4868$767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg21 [2] + connect \B $xor$ls180.v:4868$766_Y + connect \Y $xor$ls180.v:4868$767_Y + end + attribute \src "ls180.v:4869.361-4869.434" + cell $xor $xor$ls180.v:4869$768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [17] + connect \B \main_sdcore_crc7_inserter_crcreg22 [6] + connect \Y $xor$ls180.v:4869$768_Y + end + attribute \src "ls180.v:4869.205-4869.278" + cell $xor $xor$ls180.v:4869$769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [17] + connect \B \main_sdcore_crc7_inserter_crcreg22 [6] + connect \Y $xor$ls180.v:4869$769_Y + end + attribute \src "ls180.v:4869.164-4869.279" + cell $xor $xor$ls180.v:4869$770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg22 [2] + connect \B $xor$ls180.v:4869$769_Y + connect \Y $xor$ls180.v:4869$770_Y + end + attribute \src "ls180.v:4870.361-4870.434" + cell $xor $xor$ls180.v:4870$771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [16] + connect \B \main_sdcore_crc7_inserter_crcreg23 [6] + connect \Y $xor$ls180.v:4870$771_Y + end + attribute \src "ls180.v:4870.205-4870.278" + cell $xor $xor$ls180.v:4870$772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [16] + connect \B \main_sdcore_crc7_inserter_crcreg23 [6] + connect \Y $xor$ls180.v:4870$772_Y + end + attribute \src "ls180.v:4870.164-4870.279" + cell $xor $xor$ls180.v:4870$773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg23 [2] + connect \B $xor$ls180.v:4870$772_Y + connect \Y $xor$ls180.v:4870$773_Y + end + attribute \src "ls180.v:4871.361-4871.434" + cell $xor $xor$ls180.v:4871$774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [15] + connect \B \main_sdcore_crc7_inserter_crcreg24 [6] + connect \Y $xor$ls180.v:4871$774_Y + end + attribute \src "ls180.v:4871.205-4871.278" + cell $xor $xor$ls180.v:4871$775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [15] + connect \B \main_sdcore_crc7_inserter_crcreg24 [6] + connect \Y $xor$ls180.v:4871$775_Y + end + attribute \src "ls180.v:4871.164-4871.279" + cell $xor $xor$ls180.v:4871$776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg24 [2] + connect \B $xor$ls180.v:4871$775_Y + connect \Y $xor$ls180.v:4871$776_Y + end + attribute \src "ls180.v:4872.361-4872.434" + cell $xor $xor$ls180.v:4872$777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [14] + connect \B \main_sdcore_crc7_inserter_crcreg25 [6] + connect \Y $xor$ls180.v:4872$777_Y + end + attribute \src "ls180.v:4872.205-4872.278" + cell $xor $xor$ls180.v:4872$778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [14] + connect \B \main_sdcore_crc7_inserter_crcreg25 [6] + connect \Y $xor$ls180.v:4872$778_Y + end + attribute \src "ls180.v:4872.164-4872.279" + cell $xor $xor$ls180.v:4872$779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg25 [2] + connect \B $xor$ls180.v:4872$778_Y + connect \Y $xor$ls180.v:4872$779_Y + end + attribute \src "ls180.v:4873.361-4873.434" + cell $xor $xor$ls180.v:4873$780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [13] + connect \B \main_sdcore_crc7_inserter_crcreg26 [6] + connect \Y $xor$ls180.v:4873$780_Y + end + attribute \src "ls180.v:4873.205-4873.278" + cell $xor $xor$ls180.v:4873$781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [13] + connect \B \main_sdcore_crc7_inserter_crcreg26 [6] + connect \Y $xor$ls180.v:4873$781_Y + end + attribute \src "ls180.v:4873.164-4873.279" + cell $xor $xor$ls180.v:4873$782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg26 [2] + connect \B $xor$ls180.v:4873$781_Y + connect \Y $xor$ls180.v:4873$782_Y + end + attribute \src "ls180.v:4874.361-4874.434" + cell $xor $xor$ls180.v:4874$783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [12] + connect \B \main_sdcore_crc7_inserter_crcreg27 [6] + connect \Y $xor$ls180.v:4874$783_Y + end + attribute \src "ls180.v:4874.205-4874.278" + cell $xor $xor$ls180.v:4874$784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [12] + connect \B \main_sdcore_crc7_inserter_crcreg27 [6] + connect \Y $xor$ls180.v:4874$784_Y + end + attribute \src "ls180.v:4874.164-4874.279" + cell $xor $xor$ls180.v:4874$785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg27 [2] + connect \B $xor$ls180.v:4874$784_Y + connect \Y $xor$ls180.v:4874$785_Y + end + attribute \src "ls180.v:4875.361-4875.434" + cell $xor $xor$ls180.v:4875$786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [11] + connect \B \main_sdcore_crc7_inserter_crcreg28 [6] + connect \Y $xor$ls180.v:4875$786_Y + end + attribute \src "ls180.v:4875.205-4875.278" + cell $xor $xor$ls180.v:4875$787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [11] + connect \B \main_sdcore_crc7_inserter_crcreg28 [6] + connect \Y $xor$ls180.v:4875$787_Y + end + attribute \src "ls180.v:4875.164-4875.279" + cell $xor $xor$ls180.v:4875$788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg28 [2] + connect \B $xor$ls180.v:4875$787_Y + connect \Y $xor$ls180.v:4875$788_Y + end + attribute \src "ls180.v:4876.361-4876.434" + cell $xor $xor$ls180.v:4876$789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [10] + connect \B \main_sdcore_crc7_inserter_crcreg29 [6] + connect \Y $xor$ls180.v:4876$789_Y + end + attribute \src "ls180.v:4876.205-4876.278" + cell $xor $xor$ls180.v:4876$790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [10] + connect \B \main_sdcore_crc7_inserter_crcreg29 [6] + connect \Y $xor$ls180.v:4876$790_Y + end + attribute \src "ls180.v:4876.164-4876.279" + cell $xor $xor$ls180.v:4876$791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg29 [2] + connect \B $xor$ls180.v:4876$790_Y + connect \Y $xor$ls180.v:4876$791_Y + end + attribute \src "ls180.v:4877.360-4877.432" + cell $xor $xor$ls180.v:4877$792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [9] + connect \B \main_sdcore_crc7_inserter_crcreg30 [6] + connect \Y $xor$ls180.v:4877$792_Y + end + attribute \src "ls180.v:4877.205-4877.277" + cell $xor $xor$ls180.v:4877$793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [9] + connect \B \main_sdcore_crc7_inserter_crcreg30 [6] + connect \Y $xor$ls180.v:4877$793_Y + end + attribute \src "ls180.v:4877.164-4877.278" + cell $xor $xor$ls180.v:4877$794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg30 [2] + connect \B $xor$ls180.v:4877$793_Y + connect \Y $xor$ls180.v:4877$794_Y + end + attribute \src "ls180.v:4878.360-4878.432" + cell $xor $xor$ls180.v:4878$795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [8] + connect \B \main_sdcore_crc7_inserter_crcreg31 [6] + connect \Y $xor$ls180.v:4878$795_Y + end + attribute \src "ls180.v:4878.205-4878.277" + cell $xor $xor$ls180.v:4878$796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [8] + connect \B \main_sdcore_crc7_inserter_crcreg31 [6] + connect \Y $xor$ls180.v:4878$796_Y + end + attribute \src "ls180.v:4878.164-4878.278" + cell $xor $xor$ls180.v:4878$797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg31 [2] + connect \B $xor$ls180.v:4878$796_Y + connect \Y $xor$ls180.v:4878$797_Y + end + attribute \src "ls180.v:4879.360-4879.432" + cell $xor $xor$ls180.v:4879$798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [7] + connect \B \main_sdcore_crc7_inserter_crcreg32 [6] + connect \Y $xor$ls180.v:4879$798_Y + end + attribute \src "ls180.v:4879.205-4879.277" + cell $xor $xor$ls180.v:4879$799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [7] + connect \B \main_sdcore_crc7_inserter_crcreg32 [6] + connect \Y $xor$ls180.v:4879$799_Y + end + attribute \src "ls180.v:4879.164-4879.278" + cell $xor $xor$ls180.v:4879$800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg32 [2] + connect \B $xor$ls180.v:4879$799_Y + connect \Y $xor$ls180.v:4879$800_Y + end + attribute \src "ls180.v:4880.360-4880.432" + cell $xor $xor$ls180.v:4880$801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [6] + connect \B \main_sdcore_crc7_inserter_crcreg33 [6] + connect \Y $xor$ls180.v:4880$801_Y + end + attribute \src "ls180.v:4880.205-4880.277" + cell $xor $xor$ls180.v:4880$802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [6] + connect \B \main_sdcore_crc7_inserter_crcreg33 [6] + connect \Y $xor$ls180.v:4880$802_Y + end + attribute \src "ls180.v:4880.164-4880.278" + cell $xor $xor$ls180.v:4880$803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg33 [2] + connect \B $xor$ls180.v:4880$802_Y + connect \Y $xor$ls180.v:4880$803_Y + end + attribute \src "ls180.v:4881.360-4881.432" + cell $xor $xor$ls180.v:4881$804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [5] + connect \B \main_sdcore_crc7_inserter_crcreg34 [6] + connect \Y $xor$ls180.v:4881$804_Y + end + attribute \src "ls180.v:4881.205-4881.277" + cell $xor $xor$ls180.v:4881$805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [5] + connect \B \main_sdcore_crc7_inserter_crcreg34 [6] + connect \Y $xor$ls180.v:4881$805_Y + end + attribute \src "ls180.v:4881.164-4881.278" + cell $xor $xor$ls180.v:4881$806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg34 [2] + connect \B $xor$ls180.v:4881$805_Y + connect \Y $xor$ls180.v:4881$806_Y + end + attribute \src "ls180.v:4882.360-4882.432" + cell $xor $xor$ls180.v:4882$807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [4] + connect \B \main_sdcore_crc7_inserter_crcreg35 [6] + connect \Y $xor$ls180.v:4882$807_Y + end + attribute \src "ls180.v:4882.205-4882.277" + cell $xor $xor$ls180.v:4882$808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [4] + connect \B \main_sdcore_crc7_inserter_crcreg35 [6] + connect \Y $xor$ls180.v:4882$808_Y + end + attribute \src "ls180.v:4882.164-4882.278" + cell $xor $xor$ls180.v:4882$809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg35 [2] + connect \B $xor$ls180.v:4882$808_Y + connect \Y $xor$ls180.v:4882$809_Y + end + attribute \src "ls180.v:4883.360-4883.432" + cell $xor $xor$ls180.v:4883$810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [3] + connect \B \main_sdcore_crc7_inserter_crcreg36 [6] + connect \Y $xor$ls180.v:4883$810_Y + end + attribute \src "ls180.v:4883.205-4883.277" + cell $xor $xor$ls180.v:4883$811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [3] + connect \B \main_sdcore_crc7_inserter_crcreg36 [6] + connect \Y $xor$ls180.v:4883$811_Y + end + attribute \src "ls180.v:4883.164-4883.278" + cell $xor $xor$ls180.v:4883$812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg36 [2] + connect \B $xor$ls180.v:4883$811_Y + connect \Y $xor$ls180.v:4883$812_Y + end + attribute \src "ls180.v:4884.360-4884.432" + cell $xor $xor$ls180.v:4884$813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [2] + connect \B \main_sdcore_crc7_inserter_crcreg37 [6] + connect \Y $xor$ls180.v:4884$813_Y + end + attribute \src "ls180.v:4884.205-4884.277" + cell $xor $xor$ls180.v:4884$814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [2] + connect \B \main_sdcore_crc7_inserter_crcreg37 [6] + connect \Y $xor$ls180.v:4884$814_Y + end + attribute \src "ls180.v:4884.164-4884.278" + cell $xor $xor$ls180.v:4884$815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg37 [2] + connect \B $xor$ls180.v:4884$814_Y + connect \Y $xor$ls180.v:4884$815_Y + end + attribute \src "ls180.v:4885.360-4885.432" + cell $xor $xor$ls180.v:4885$816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [1] + connect \B \main_sdcore_crc7_inserter_crcreg38 [6] + connect \Y $xor$ls180.v:4885$816_Y + end + attribute \src "ls180.v:4885.205-4885.277" + cell $xor $xor$ls180.v:4885$817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [1] + connect \B \main_sdcore_crc7_inserter_crcreg38 [6] + connect \Y $xor$ls180.v:4885$817_Y + end + attribute \src "ls180.v:4885.164-4885.278" + cell $xor $xor$ls180.v:4885$818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg38 [2] + connect \B $xor$ls180.v:4885$817_Y + connect \Y $xor$ls180.v:4885$818_Y + end + attribute \src "ls180.v:4886.360-4886.432" + cell $xor $xor$ls180.v:4886$819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [0] + connect \B \main_sdcore_crc7_inserter_crcreg39 [6] + connect \Y $xor$ls180.v:4886$819_Y + end + attribute \src "ls180.v:4886.205-4886.277" + cell $xor $xor$ls180.v:4886$820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [0] + connect \B \main_sdcore_crc7_inserter_crcreg39 [6] + connect \Y $xor$ls180.v:4886$820_Y + end + attribute \src "ls180.v:4886.164-4886.278" + cell $xor $xor$ls180.v:4886$821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg39 [2] + connect \B $xor$ls180.v:4886$820_Y + connect \Y $xor$ls180.v:4886$821_Y + end + attribute \src "ls180.v:4907.899-4907.983" + cell $xor $xor$ls180.v:4907$835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:4907$835_Y + end + attribute \src "ls180.v:4907.634-4907.718" + cell $xor $xor$ls180.v:4907$836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:4907$836_Y + end + attribute \src "ls180.v:4907.588-4907.719" + cell $xor $xor$ls180.v:4907$837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4] + connect \B $xor$ls180.v:4907$836_Y + connect \Y $xor$ls180.v:4907$837_Y + end + attribute \src "ls180.v:4907.234-4907.318" + cell $xor $xor$ls180.v:4907$838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:4907$838_Y + end + attribute \src "ls180.v:4907.187-4907.319" + cell $xor $xor$ls180.v:4907$839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11] + connect \B $xor$ls180.v:4907$838_Y + connect \Y $xor$ls180.v:4907$839_Y + end + attribute \src "ls180.v:4908.899-4908.983" + cell $xor $xor$ls180.v:4908$840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:4908$840_Y + end + attribute \src "ls180.v:4908.634-4908.718" + cell $xor $xor$ls180.v:4908$841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:4908$841_Y + end + attribute \src "ls180.v:4908.588-4908.719" + cell $xor $xor$ls180.v:4908$842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] + connect \B $xor$ls180.v:4908$841_Y + connect \Y $xor$ls180.v:4908$842_Y + end + attribute \src "ls180.v:4908.234-4908.318" + cell $xor $xor$ls180.v:4908$843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:4908$843_Y + end + attribute \src "ls180.v:4908.187-4908.319" + cell $xor $xor$ls180.v:4908$844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] + connect \B $xor$ls180.v:4908$843_Y + connect \Y $xor$ls180.v:4908$844_Y + end + attribute \src "ls180.v:4917.899-4917.983" + cell $xor $xor$ls180.v:4917$846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:4917$846_Y + end + attribute \src "ls180.v:4917.634-4917.718" + cell $xor $xor$ls180.v:4917$847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:4917$847_Y + end + attribute \src "ls180.v:4917.588-4917.719" + cell $xor $xor$ls180.v:4917$848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4] + connect \B $xor$ls180.v:4917$847_Y + connect \Y $xor$ls180.v:4917$848_Y + end + attribute \src "ls180.v:4917.234-4917.318" + cell $xor $xor$ls180.v:4917$849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:4917$849_Y + end + attribute \src "ls180.v:4917.187-4917.319" + cell $xor $xor$ls180.v:4917$850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11] + connect \B $xor$ls180.v:4917$849_Y + connect \Y $xor$ls180.v:4917$850_Y + end + attribute \src "ls180.v:4918.899-4918.983" + cell $xor $xor$ls180.v:4918$851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:4918$851_Y + end + attribute \src "ls180.v:4918.634-4918.718" + cell $xor $xor$ls180.v:4918$852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:4918$852_Y + end + attribute \src "ls180.v:4918.588-4918.719" + cell $xor $xor$ls180.v:4918$853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4] + connect \B $xor$ls180.v:4918$852_Y + connect \Y $xor$ls180.v:4918$853_Y + end + attribute \src "ls180.v:4918.234-4918.318" + cell $xor $xor$ls180.v:4918$854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:4918$854_Y + end + attribute \src "ls180.v:4918.187-4918.319" + cell $xor $xor$ls180.v:4918$855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11] + connect \B $xor$ls180.v:4918$854_Y + connect \Y $xor$ls180.v:4918$855_Y + end + attribute \src "ls180.v:4927.899-4927.983" + cell $xor $xor$ls180.v:4927$857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:4927$857_Y + end + attribute \src "ls180.v:4927.634-4927.718" + cell $xor $xor$ls180.v:4927$858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:4927$858_Y + end + attribute \src "ls180.v:4927.588-4927.719" + cell $xor $xor$ls180.v:4927$859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4] + connect \B $xor$ls180.v:4927$858_Y + connect \Y $xor$ls180.v:4927$859_Y + end + attribute \src "ls180.v:4927.234-4927.318" + cell $xor $xor$ls180.v:4927$860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:4927$860_Y + end + attribute \src "ls180.v:4927.187-4927.319" + cell $xor $xor$ls180.v:4927$861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11] + connect \B $xor$ls180.v:4927$860_Y + connect \Y $xor$ls180.v:4927$861_Y + end + attribute \src "ls180.v:4928.899-4928.983" + cell $xor $xor$ls180.v:4928$862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:4928$862_Y + end + attribute \src "ls180.v:4928.634-4928.718" + cell $xor $xor$ls180.v:4928$863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:4928$863_Y + end + attribute \src "ls180.v:4928.588-4928.719" + cell $xor $xor$ls180.v:4928$864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4] + connect \B $xor$ls180.v:4928$863_Y + connect \Y $xor$ls180.v:4928$864_Y + end + attribute \src "ls180.v:4928.234-4928.318" + cell $xor $xor$ls180.v:4928$865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:4928$865_Y + end + attribute \src "ls180.v:4928.187-4928.319" + cell $xor $xor$ls180.v:4928$866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11] + connect \B $xor$ls180.v:4928$865_Y + connect \Y $xor$ls180.v:4928$866_Y + end + attribute \src "ls180.v:4937.899-4937.983" + cell $xor $xor$ls180.v:4937$868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:4937$868_Y + end + attribute \src "ls180.v:4937.634-4937.718" + cell $xor $xor$ls180.v:4937$869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:4937$869_Y + end + attribute \src "ls180.v:4937.588-4937.719" + cell $xor $xor$ls180.v:4937$870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4] + connect \B $xor$ls180.v:4937$869_Y + connect \Y $xor$ls180.v:4937$870_Y + end + attribute \src "ls180.v:4937.234-4937.318" + cell $xor $xor$ls180.v:4937$871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:4937$871_Y + end + attribute \src "ls180.v:4937.187-4937.319" + cell $xor $xor$ls180.v:4937$872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11] + connect \B $xor$ls180.v:4937$871_Y + connect \Y $xor$ls180.v:4937$872_Y + end + attribute \src "ls180.v:4938.899-4938.983" + cell $xor $xor$ls180.v:4938$873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:4938$873_Y + end + attribute \src "ls180.v:4938.634-4938.718" + cell $xor $xor$ls180.v:4938$874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:4938$874_Y + end + attribute \src "ls180.v:4938.588-4938.719" + cell $xor $xor$ls180.v:4938$875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4] + connect \B $xor$ls180.v:4938$874_Y + connect \Y $xor$ls180.v:4938$875_Y + end + attribute \src "ls180.v:4938.234-4938.318" + cell $xor $xor$ls180.v:4938$876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:4938$876_Y + end + attribute \src "ls180.v:4938.187-4938.319" + cell $xor $xor$ls180.v:4938$877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] + connect \B $xor$ls180.v:4938$876_Y + connect \Y $xor$ls180.v:4938$877_Y + end + attribute \src "ls180.v:5089.879-5089.961" + cell $xor $xor$ls180.v:5089$910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5089$910_Y + end + attribute \src "ls180.v:5089.620-5089.702" + cell $xor $xor$ls180.v:5089$911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5089$911_Y + end + attribute \src "ls180.v:5089.575-5089.703" + cell $xor $xor$ls180.v:5089$912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4] + connect \B $xor$ls180.v:5089$911_Y + connect \Y $xor$ls180.v:5089$912_Y + end + attribute \src "ls180.v:5089.229-5089.311" + cell $xor $xor$ls180.v:5089$913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5089$913_Y + end + attribute \src "ls180.v:5089.183-5089.312" + cell $xor $xor$ls180.v:5089$914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11] + connect \B $xor$ls180.v:5089$913_Y + connect \Y $xor$ls180.v:5089$914_Y + end + attribute \src "ls180.v:5090.879-5090.961" + cell $xor $xor$ls180.v:5090$915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5090$915_Y + end + attribute \src "ls180.v:5090.620-5090.702" + cell $xor $xor$ls180.v:5090$916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5090$916_Y + end + attribute \src "ls180.v:5090.575-5090.703" + cell $xor $xor$ls180.v:5090$917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4] + connect \B $xor$ls180.v:5090$916_Y + connect \Y $xor$ls180.v:5090$917_Y + end + attribute \src "ls180.v:5090.229-5090.311" + cell $xor $xor$ls180.v:5090$918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5090$918_Y + end + attribute \src "ls180.v:5090.183-5090.312" + cell $xor $xor$ls180.v:5090$919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11] + connect \B $xor$ls180.v:5090$918_Y + connect \Y $xor$ls180.v:5090$919_Y + end + attribute \src "ls180.v:5099.879-5099.961" + cell $xor $xor$ls180.v:5099$921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5099$921_Y + end + attribute \src "ls180.v:5099.620-5099.702" + cell $xor $xor$ls180.v:5099$922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5099$922_Y + end + attribute \src "ls180.v:5099.575-5099.703" + cell $xor $xor$ls180.v:5099$923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4] + connect \B $xor$ls180.v:5099$922_Y + connect \Y $xor$ls180.v:5099$923_Y + end + attribute \src "ls180.v:5099.229-5099.311" + cell $xor $xor$ls180.v:5099$924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5099$924_Y + end + attribute \src "ls180.v:5099.183-5099.312" + cell $xor $xor$ls180.v:5099$925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11] + connect \B $xor$ls180.v:5099$924_Y + connect \Y $xor$ls180.v:5099$925_Y + end + attribute \src "ls180.v:5100.879-5100.961" + cell $xor $xor$ls180.v:5100$926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5100$926_Y + end + attribute \src "ls180.v:5100.620-5100.702" + cell $xor $xor$ls180.v:5100$927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5100$927_Y + end + attribute \src "ls180.v:5100.575-5100.703" + cell $xor $xor$ls180.v:5100$928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4] + connect \B $xor$ls180.v:5100$927_Y + connect \Y $xor$ls180.v:5100$928_Y + end + attribute \src "ls180.v:5100.229-5100.311" + cell $xor $xor$ls180.v:5100$929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5100$929_Y + end + attribute \src "ls180.v:5100.183-5100.312" + cell $xor $xor$ls180.v:5100$930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11] + connect \B $xor$ls180.v:5100$929_Y + connect \Y $xor$ls180.v:5100$930_Y + end + attribute \src "ls180.v:5109.879-5109.961" + cell $xor $xor$ls180.v:5109$932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5109$932_Y + end + attribute \src "ls180.v:5109.620-5109.702" + cell $xor $xor$ls180.v:5109$933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5109$933_Y + end + attribute \src "ls180.v:5109.575-5109.703" + cell $xor $xor$ls180.v:5109$934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4] + connect \B $xor$ls180.v:5109$933_Y + connect \Y $xor$ls180.v:5109$934_Y + end + attribute \src "ls180.v:5109.229-5109.311" + cell $xor $xor$ls180.v:5109$935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5109$935_Y + end + attribute \src "ls180.v:5109.183-5109.312" + cell $xor $xor$ls180.v:5109$936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11] + connect \B $xor$ls180.v:5109$935_Y + connect \Y $xor$ls180.v:5109$936_Y + end + attribute \src "ls180.v:5110.879-5110.961" + cell $xor $xor$ls180.v:5110$937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5110$937_Y + end + attribute \src "ls180.v:5110.620-5110.702" + cell $xor $xor$ls180.v:5110$938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5110$938_Y + end + attribute \src "ls180.v:5110.575-5110.703" + cell $xor $xor$ls180.v:5110$939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] + connect \B $xor$ls180.v:5110$938_Y + connect \Y $xor$ls180.v:5110$939_Y + end + attribute \src "ls180.v:5110.229-5110.311" + cell $xor $xor$ls180.v:5110$940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5110$940_Y + end + attribute \src "ls180.v:5110.183-5110.312" + cell $xor $xor$ls180.v:5110$941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] + connect \B $xor$ls180.v:5110$940_Y + connect \Y $xor$ls180.v:5110$941_Y + end + attribute \src "ls180.v:5119.879-5119.961" + cell $xor $xor$ls180.v:5119$943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5119$943_Y + end + attribute \src "ls180.v:5119.620-5119.702" + cell $xor $xor$ls180.v:5119$944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5119$944_Y + end + attribute \src "ls180.v:5119.575-5119.703" + cell $xor $xor$ls180.v:5119$945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4] + connect \B $xor$ls180.v:5119$944_Y + connect \Y $xor$ls180.v:5119$945_Y + end + attribute \src "ls180.v:5119.229-5119.311" + cell $xor $xor$ls180.v:5119$946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5119$946_Y + end + attribute \src "ls180.v:5119.183-5119.312" + cell $xor $xor$ls180.v:5119$947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11] + connect \B $xor$ls180.v:5119$946_Y + connect \Y $xor$ls180.v:5119$947_Y + end + attribute \src "ls180.v:5120.879-5120.961" + cell $xor $xor$ls180.v:5120$948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5120$948_Y + end + attribute \src "ls180.v:5120.620-5120.702" + cell $xor $xor$ls180.v:5120$949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5120$949_Y + end + attribute \src "ls180.v:5120.575-5120.703" + cell $xor $xor$ls180.v:5120$950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4] + connect \B $xor$ls180.v:5120$949_Y + connect \Y $xor$ls180.v:5120$950_Y + end + attribute \src "ls180.v:5120.229-5120.311" + cell $xor $xor$ls180.v:5120$951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5120$951_Y + end + attribute \src "ls180.v:5120.183-5120.312" + cell $xor $xor$ls180.v:5120$952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11] + connect \B $xor$ls180.v:5120$951_Y + connect \Y $xor$ls180.v:5120$952_Y + end + attribute \module_not_derived 1 + attribute \src "ls180.v:10176.13-10345.2" + cell \test_issuer \test_issuer + connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck + connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi + connect \TAP_bus__tdo \main_libresocsim_libresoc_jtag_tdo + connect \TAP_bus__tms \main_libresocsim_libresoc_jtag_tms + connect \busy_o \main_libresocsim_libresoc0 + connect \clk \sys_clk_1 + connect \clk_sel_i \main_libresocsim_libresoc_clk_sel + connect \core_bigendian_i 1'0 + connect \dbus__ack \main_libresocsim_libresoc_dbus_ack + connect \dbus__adr \main_libresocsim_libresoc_dbus_adr + connect \dbus__bte \main_libresocsim_libresoc_dbus_bte + connect \dbus__cti \main_libresocsim_libresoc_dbus_cti + connect \dbus__cyc \main_libresocsim_libresoc_dbus_cyc + connect \dbus__dat_r \main_libresocsim_libresoc_dbus_dat_r + connect \dbus__dat_w \main_libresocsim_libresoc_dbus_dat_w + connect \dbus__err \main_libresocsim_libresoc_dbus_err + connect \dbus__sel \main_libresocsim_libresoc_dbus_sel + connect \dbus__stb \main_libresocsim_libresoc_dbus_stb + connect \dbus__we \main_libresocsim_libresoc_dbus_we + connect \gpio_gpio0__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [0] + connect \gpio_gpio0__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [0] + connect \gpio_gpio0__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [0] + connect \gpio_gpio0__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [0] + connect \gpio_gpio0__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [0] + connect \gpio_gpio0__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [0] + connect \gpio_gpio10__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [10] + connect \gpio_gpio10__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [10] + connect \gpio_gpio10__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [10] + connect \gpio_gpio10__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [10] + connect \gpio_gpio10__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [10] + connect \gpio_gpio10__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [10] + connect \gpio_gpio11__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [11] + connect \gpio_gpio11__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [11] + connect \gpio_gpio11__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [11] + connect \gpio_gpio11__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [11] + connect \gpio_gpio11__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [11] + connect \gpio_gpio11__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [11] + connect \gpio_gpio12__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [12] + connect \gpio_gpio12__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [12] + connect \gpio_gpio12__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [12] + connect \gpio_gpio12__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [12] + connect \gpio_gpio12__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [12] + connect \gpio_gpio12__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [12] + connect \gpio_gpio13__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [13] + connect \gpio_gpio13__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [13] + connect \gpio_gpio13__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [13] + connect \gpio_gpio13__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [13] + connect \gpio_gpio13__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [13] + connect \gpio_gpio13__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [13] + connect \gpio_gpio14__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [14] + connect \gpio_gpio14__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [14] + connect \gpio_gpio14__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [14] + connect \gpio_gpio14__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [14] + connect \gpio_gpio14__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [14] + connect \gpio_gpio14__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [14] + connect \gpio_gpio15__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [15] + connect \gpio_gpio15__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [15] + connect \gpio_gpio15__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [15] + connect \gpio_gpio15__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [15] + connect \gpio_gpio15__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [15] + connect \gpio_gpio15__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [15] + connect \gpio_gpio1__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [1] + connect \gpio_gpio1__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [1] + connect \gpio_gpio1__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [1] + connect \gpio_gpio1__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [1] + connect \gpio_gpio1__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [1] + connect \gpio_gpio1__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [1] + connect \gpio_gpio2__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [2] + connect \gpio_gpio2__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [2] + connect \gpio_gpio2__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [2] + connect \gpio_gpio2__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [2] + connect \gpio_gpio2__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [2] + connect \gpio_gpio2__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [2] + connect \gpio_gpio3__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [3] + connect \gpio_gpio3__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [3] + connect \gpio_gpio3__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [3] + connect \gpio_gpio3__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [3] + connect \gpio_gpio3__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [3] + connect \gpio_gpio3__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [3] + connect \gpio_gpio4__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [4] + connect \gpio_gpio4__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [4] + connect \gpio_gpio4__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [4] + connect \gpio_gpio4__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [4] + connect \gpio_gpio4__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [4] + connect \gpio_gpio4__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [4] + connect \gpio_gpio5__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [5] + connect \gpio_gpio5__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [5] + connect \gpio_gpio5__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [5] + connect \gpio_gpio5__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [5] + connect \gpio_gpio5__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [5] + connect \gpio_gpio5__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [5] + connect \gpio_gpio6__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [6] + connect \gpio_gpio6__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [6] + connect \gpio_gpio6__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [6] + connect \gpio_gpio6__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [6] + connect \gpio_gpio6__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [6] + connect \gpio_gpio6__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [6] + connect \gpio_gpio7__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [7] + connect \gpio_gpio7__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [7] + connect \gpio_gpio7__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [7] + connect \gpio_gpio7__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [7] + connect \gpio_gpio7__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [7] + connect \gpio_gpio7__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [7] + connect \gpio_gpio8__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [8] + connect \gpio_gpio8__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [8] + connect \gpio_gpio8__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [8] + connect \gpio_gpio8__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [8] + connect \gpio_gpio8__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [8] + connect \gpio_gpio8__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [8] + connect \gpio_gpio9__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [9] + connect \gpio_gpio9__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [9] + connect \gpio_gpio9__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [9] + connect \gpio_gpio9__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [9] + connect \gpio_gpio9__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [9] + connect \gpio_gpio9__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [9] + connect \ibus__ack \main_libresocsim_libresoc_ibus_ack + connect \ibus__adr \main_libresocsim_libresoc_ibus_adr + connect \ibus__bte \main_libresocsim_libresoc_ibus_bte + connect \ibus__cti \main_libresocsim_libresoc_ibus_cti + connect \ibus__cyc \main_libresocsim_libresoc_ibus_cyc + connect \ibus__dat_r \main_libresocsim_libresoc_ibus_dat_r + connect \ibus__dat_w \main_libresocsim_libresoc_ibus_dat_w + connect \ibus__err \main_libresocsim_libresoc_ibus_err + connect \ibus__sel \main_libresocsim_libresoc_ibus_sel + connect \ibus__stb \main_libresocsim_libresoc_ibus_stb + connect \ibus__we \main_libresocsim_libresoc_ibus_we + connect \icp_wb__ack \main_libresocsim_libresoc_xics_icp_ack + connect \icp_wb__adr \main_libresocsim_libresoc_xics_icp_adr + connect \icp_wb__bte \main_libresocsim_libresoc_xics_icp_bte + connect \icp_wb__cti \main_libresocsim_libresoc_xics_icp_cti + connect \icp_wb__cyc \main_libresocsim_libresoc_xics_icp_cyc + connect \icp_wb__dat_r \main_libresocsim_libresoc_xics_icp_dat_r + connect \icp_wb__dat_w \main_libresocsim_libresoc_xics_icp_dat_w + connect \icp_wb__err \main_libresocsim_libresoc_xics_icp_err + connect \icp_wb__sel \main_libresocsim_libresoc_xics_icp_sel + connect \icp_wb__stb \main_libresocsim_libresoc_xics_icp_stb + connect \icp_wb__we \main_libresocsim_libresoc_xics_icp_we + connect \ics_wb__ack \main_libresocsim_libresoc_xics_ics_ack + connect \ics_wb__adr \main_libresocsim_libresoc_xics_ics_adr + connect \ics_wb__bte \main_libresocsim_libresoc_xics_ics_bte + connect \ics_wb__cti \main_libresocsim_libresoc_xics_ics_cti + connect \ics_wb__cyc \main_libresocsim_libresoc_xics_ics_cyc + connect \ics_wb__dat_r \main_libresocsim_libresoc_xics_ics_dat_r + connect \ics_wb__dat_w \main_libresocsim_libresoc_xics_ics_dat_w + connect \ics_wb__err \main_libresocsim_libresoc_xics_ics_err + connect \ics_wb__sel \main_libresocsim_libresoc_xics_ics_sel + connect \ics_wb__stb \main_libresocsim_libresoc_xics_ics_stb + connect \ics_wb__we \main_libresocsim_libresoc_xics_ics_we + connect \int_level_i \main_libresocsim_libresoc_interrupt + connect \jtag_wb__ack \main_libresocsim_libresoc_jtag_wb_ack + connect \jtag_wb__adr \main_libresocsim_libresoc_jtag_wb_adr + connect \jtag_wb__cyc \main_libresocsim_libresoc_jtag_wb_cyc + connect \jtag_wb__dat_r \main_libresocsim_libresoc_jtag_wb_dat_r + connect \jtag_wb__dat_w \main_libresocsim_libresoc_jtag_wb_dat_w + connect \jtag_wb__err \main_libresocsim_libresoc_jtag_wb_err + connect \jtag_wb__sel \main_libresocsim_libresoc_jtag_wb_sel + connect \jtag_wb__stb \main_libresocsim_libresoc_jtag_wb_stb + connect \jtag_wb__we \main_libresocsim_libresoc_jtag_wb_we + connect \memerr_o \main_libresocsim_libresoc1 + connect \pc_i 1'0 + connect \pc_i_ok 1'0 + connect \pc_o \main_libresocsim_libresoc2 + connect \pll_48_o \main_libresocsim_libresoc_pll_48_o + connect \rst $or$ls180.v:10259$2762_Y + connect \uart_rx__core__i \main_libresocsim_libresoc_constraintmanager0_uart0_rx + connect \uart_rx__pad__i \main_libresocsim_libresoc_constraintmanager1_uart0_rx + connect \uart_tx__core__o \main_libresocsim_libresoc_constraintmanager0_uart0_tx + connect \uart_tx__pad__o \main_libresocsim_libresoc_constraintmanager1_uart0_tx + end + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$3714 + sync always + sync init + end + attribute \src "ls180.v:1001.11-1001.43" + process $proc$ls180.v:1001$3156 + assign { } { } + assign $1\main_spi_master_mosi_data[7:0] 8'00000000 + sync always + sync init + update \main_spi_master_mosi_data $1\main_spi_master_mosi_data[7:0] + end + attribute \src "ls180.v:1002.11-1002.42" + process $proc$ls180.v:1002$3157 + assign { } { } + assign $1\main_spi_master_mosi_sel[2:0] 3'000 + sync always + sync init + update \main_spi_master_mosi_sel $1\main_spi_master_mosi_sel[2:0] + end + attribute \src "ls180.v:1003.11-1003.43" + process $proc$ls180.v:1003$3158 + assign { } { } + assign $1\main_spi_master_miso_data[7:0] 8'00000000 + sync always + sync init + update \main_spi_master_miso_data $1\main_spi_master_miso_data[7:0] + end + attribute \src "ls180.v:10040.1-10050.4" + process $proc$ls180.v:10040$2692 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem$ls180.v:10048$4_ADDR[6:0]$2702 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:10048$4_DATA[31:0]$2703 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10048$4_EN[31:0]$2704 0 + assign $0$memwr$\mem$ls180.v:10046$3_ADDR[6:0]$2699 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:10046$3_DATA[31:0]$2700 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10046$3_EN[31:0]$2701 0 + assign $0$memwr$\mem$ls180.v:10044$2_ADDR[6:0]$2696 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:10044$2_DATA[31:0]$2697 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10044$2_EN[31:0]$2698 0 + assign $0$memwr$\mem$ls180.v:10042$1_ADDR[6:0]$2693 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:10042$1_DATA[31:0]$2694 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10042$1_EN[31:0]$2695 0 + assign $0\memadr[6:0] \main_libresocsim_adr + attribute \src "ls180.v:10041.2-10042.65" + switch \main_libresocsim_we [0] + attribute \src "ls180.v:10041.6-10041.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10042$1_ADDR[6:0]$2693 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10042$1_DATA[31:0]$2694 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] } + assign $0$memwr$\mem$ls180.v:10042$1_EN[31:0]$2695 255 + case + end + attribute \src "ls180.v:10043.2-10044.67" + switch \main_libresocsim_we [1] + attribute \src "ls180.v:10043.6-10043.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10044$2_ADDR[6:0]$2696 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10044$2_DATA[31:0]$2697 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem$ls180.v:10044$2_EN[31:0]$2698 65280 + case + end + attribute \src "ls180.v:10045.2-10046.69" + switch \main_libresocsim_we [2] + attribute \src "ls180.v:10045.6-10045.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10046$3_ADDR[6:0]$2699 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10046$3_DATA[31:0]$2700 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10046$3_EN[31:0]$2701 16711680 + case + end + attribute \src "ls180.v:10047.2-10048.69" + switch \main_libresocsim_we [3] + attribute \src "ls180.v:10047.6-10047.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10048$4_ADDR[6:0]$2702 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10048$4_DATA[31:0]$2703 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10048$4_EN[31:0]$2704 32'11111111000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr $0\memadr[6:0] + update $memwr$\mem$ls180.v:10042$1_ADDR $0$memwr$\mem$ls180.v:10042$1_ADDR[6:0]$2693 + update $memwr$\mem$ls180.v:10042$1_DATA $0$memwr$\mem$ls180.v:10042$1_DATA[31:0]$2694 + update $memwr$\mem$ls180.v:10042$1_EN $0$memwr$\mem$ls180.v:10042$1_EN[31:0]$2695 + update $memwr$\mem$ls180.v:10044$2_ADDR $0$memwr$\mem$ls180.v:10044$2_ADDR[6:0]$2696 + update $memwr$\mem$ls180.v:10044$2_DATA $0$memwr$\mem$ls180.v:10044$2_DATA[31:0]$2697 + update $memwr$\mem$ls180.v:10044$2_EN $0$memwr$\mem$ls180.v:10044$2_EN[31:0]$2698 + update $memwr$\mem$ls180.v:10046$3_ADDR $0$memwr$\mem$ls180.v:10046$3_ADDR[6:0]$2699 + update $memwr$\mem$ls180.v:10046$3_DATA $0$memwr$\mem$ls180.v:10046$3_DATA[31:0]$2700 + update $memwr$\mem$ls180.v:10046$3_EN $0$memwr$\mem$ls180.v:10046$3_EN[31:0]$2701 + update $memwr$\mem$ls180.v:10048$4_ADDR $0$memwr$\mem$ls180.v:10048$4_ADDR[6:0]$2702 + update $memwr$\mem$ls180.v:10048$4_DATA $0$memwr$\mem$ls180.v:10048$4_DATA[31:0]$2703 + update $memwr$\mem$ls180.v:10048$4_EN $0$memwr$\mem$ls180.v:10048$4_EN[31:0]$2704 + end + attribute \src "ls180.v:1005.12-1005.30" + process $proc$ls180.v:1005$3159 + assign { } { } + assign $1\main_dummy[35:0] 36'000000000000000000000000000000000000 + sync always + sync init + update \main_dummy $1\main_dummy[35:0] + end + attribute \src "ls180.v:10060.1-10064.4" + process $proc$ls180.v:10060$2706 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage$ls180.v:10062$5_ADDR[2:0]$2707 3'xxx + assign $0$memwr$\storage$ls180.v:10062$5_DATA[24:0]$2708 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage$ls180.v:10062$5_EN[24:0]$2709 25'0000000000000000000000000 + assign $0\memdat[24:0] $memrd$\storage$ls180.v:10063$2710_DATA + attribute \src "ls180.v:10061.2-10062.129" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10061.6-10061.60" + case 1'1 + assign $0$memwr$\storage$ls180.v:10062$5_ADDR[2:0]$2707 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage$ls180.v:10062$5_DATA[24:0]$2708 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage$ls180.v:10062$5_EN[24:0]$2709 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat $0\memdat[24:0] + update $memwr$\storage$ls180.v:10062$5_ADDR $0$memwr$\storage$ls180.v:10062$5_ADDR[2:0]$2707 + update $memwr$\storage$ls180.v:10062$5_DATA $0$memwr$\storage$ls180.v:10062$5_DATA[24:0]$2708 + update $memwr$\storage$ls180.v:10062$5_EN $0$memwr$\storage$ls180.v:10062$5_EN[24:0]$2709 + end + attribute \src "ls180.v:10066.1-10067.4" + process $proc$ls180.v:10066$2711 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10074.1-10078.4" + process $proc$ls180.v:10074$2713 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_1$ls180.v:10076$6_ADDR[2:0]$2714 3'xxx + assign $0$memwr$\storage_1$ls180.v:10076$6_DATA[24:0]$2715 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_1$ls180.v:10076$6_EN[24:0]$2716 25'0000000000000000000000000 + assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10077$2717_DATA + attribute \src "ls180.v:10075.2-10076.131" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10075.6-10075.60" + case 1'1 + assign $0$memwr$\storage_1$ls180.v:10076$6_ADDR[2:0]$2714 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_1$ls180.v:10076$6_DATA[24:0]$2715 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_1$ls180.v:10076$6_EN[24:0]$2716 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_1 $0\memdat_1[24:0] + update $memwr$\storage_1$ls180.v:10076$6_ADDR $0$memwr$\storage_1$ls180.v:10076$6_ADDR[2:0]$2714 + update $memwr$\storage_1$ls180.v:10076$6_DATA $0$memwr$\storage_1$ls180.v:10076$6_DATA[24:0]$2715 + update $memwr$\storage_1$ls180.v:10076$6_EN $0$memwr$\storage_1$ls180.v:10076$6_EN[24:0]$2716 + end + attribute \src "ls180.v:10080.1-10081.4" + process $proc$ls180.v:10080$2718 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10088.1-10092.4" + process $proc$ls180.v:10088$2720 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_2$ls180.v:10090$7_ADDR[2:0]$2721 3'xxx + assign $0$memwr$\storage_2$ls180.v:10090$7_DATA[24:0]$2722 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_2$ls180.v:10090$7_EN[24:0]$2723 25'0000000000000000000000000 + assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10091$2724_DATA + attribute \src "ls180.v:10089.2-10090.131" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10089.6-10089.60" + case 1'1 + assign $0$memwr$\storage_2$ls180.v:10090$7_ADDR[2:0]$2721 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_2$ls180.v:10090$7_DATA[24:0]$2722 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_2$ls180.v:10090$7_EN[24:0]$2723 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_2 $0\memdat_2[24:0] + update $memwr$\storage_2$ls180.v:10090$7_ADDR $0$memwr$\storage_2$ls180.v:10090$7_ADDR[2:0]$2721 + update $memwr$\storage_2$ls180.v:10090$7_DATA $0$memwr$\storage_2$ls180.v:10090$7_DATA[24:0]$2722 + update $memwr$\storage_2$ls180.v:10090$7_EN $0$memwr$\storage_2$ls180.v:10090$7_EN[24:0]$2723 + end + attribute \src "ls180.v:1009.12-1009.37" + process $proc$ls180.v:1009$3160 + assign { } { } + assign $1\main_pwm0_counter[31:0] 0 + sync always + sync init + update \main_pwm0_counter $1\main_pwm0_counter[31:0] + end + attribute \src "ls180.v:10094.1-10095.4" + process $proc$ls180.v:10094$2725 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1010.5-1010.36" + process $proc$ls180.v:1010$3161 + assign { } { } + assign $1\main_pwm0_enable_storage[0:0] 1'0 + sync always + sync init + update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] + end + attribute \src "ls180.v:10102.1-10106.4" + process $proc$ls180.v:10102$2727 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_3$ls180.v:10104$8_ADDR[2:0]$2728 3'xxx + assign $0$memwr$\storage_3$ls180.v:10104$8_DATA[24:0]$2729 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_3$ls180.v:10104$8_EN[24:0]$2730 25'0000000000000000000000000 + assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10105$2731_DATA + attribute \src "ls180.v:10103.2-10104.131" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10103.6-10103.60" + case 1'1 + assign $0$memwr$\storage_3$ls180.v:10104$8_ADDR[2:0]$2728 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_3$ls180.v:10104$8_DATA[24:0]$2729 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_3$ls180.v:10104$8_EN[24:0]$2730 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_3 $0\memdat_3[24:0] + update $memwr$\storage_3$ls180.v:10104$8_ADDR $0$memwr$\storage_3$ls180.v:10104$8_ADDR[2:0]$2728 + update $memwr$\storage_3$ls180.v:10104$8_DATA $0$memwr$\storage_3$ls180.v:10104$8_DATA[24:0]$2729 + update $memwr$\storage_3$ls180.v:10104$8_EN $0$memwr$\storage_3$ls180.v:10104$8_EN[24:0]$2730 + end + attribute \src "ls180.v:10108.1-10109.4" + process $proc$ls180.v:10108$2732 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1011.5-1011.31" + process $proc$ls180.v:1011$3162 + assign { } { } + assign $1\main_pwm0_enable_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] + end + attribute \src "ls180.v:10117.1-10121.4" + process $proc$ls180.v:10117$2734 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_4$ls180.v:10119$9_ADDR[3:0]$2735 4'xxxx + assign $0$memwr$\storage_4$ls180.v:10119$9_DATA[9:0]$2736 10'xxxxxxxxxx + assign $0$memwr$\storage_4$ls180.v:10119$9_EN[9:0]$2737 10'0000000000 + assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10120$2738_DATA + attribute \src "ls180.v:10118.2-10119.77" + switch \main_uart_tx_fifo_wrport_we + attribute \src "ls180.v:10118.6-10118.33" + case 1'1 + assign $0$memwr$\storage_4$ls180.v:10119$9_ADDR[3:0]$2735 \main_uart_tx_fifo_wrport_adr + assign $0$memwr$\storage_4$ls180.v:10119$9_DATA[9:0]$2736 \main_uart_tx_fifo_wrport_dat_w + assign $0$memwr$\storage_4$ls180.v:10119$9_EN[9:0]$2737 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_4 $0\memdat_4[9:0] + update $memwr$\storage_4$ls180.v:10119$9_ADDR $0$memwr$\storage_4$ls180.v:10119$9_ADDR[3:0]$2735 + update $memwr$\storage_4$ls180.v:10119$9_DATA $0$memwr$\storage_4$ls180.v:10119$9_DATA[9:0]$2736 + update $memwr$\storage_4$ls180.v:10119$9_EN $0$memwr$\storage_4$ls180.v:10119$9_EN[9:0]$2737 + end + attribute \src "ls180.v:1012.12-1012.43" + process $proc$ls180.v:1012$3163 + assign { } { } + assign $1\main_pwm0_width_storage[31:0] 0 + sync always + sync init + update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] + end + attribute \src "ls180.v:10123.1-10126.4" + process $proc$ls180.v:10123$2739 + assign $0\memdat_5[9:0] \memdat_5 + attribute \src "ls180.v:10124.2-10125.55" + switch \main_uart_tx_fifo_rdport_re + attribute \src "ls180.v:10124.6-10124.33" + case 1'1 + assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10125$2740_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_5 $0\memdat_5[9:0] + end + attribute \src "ls180.v:1013.5-1013.30" + process $proc$ls180.v:1013$3164 + assign { } { } + assign $1\main_pwm0_width_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] + end + attribute \src "ls180.v:10134.1-10138.4" + process $proc$ls180.v:10134$2741 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_5$ls180.v:10136$10_ADDR[3:0]$2742 4'xxxx + assign $0$memwr$\storage_5$ls180.v:10136$10_DATA[9:0]$2743 10'xxxxxxxxxx + assign $0$memwr$\storage_5$ls180.v:10136$10_EN[9:0]$2744 10'0000000000 + assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10137$2745_DATA + attribute \src "ls180.v:10135.2-10136.77" + switch \main_uart_rx_fifo_wrport_we + attribute \src "ls180.v:10135.6-10135.33" + case 1'1 + assign $0$memwr$\storage_5$ls180.v:10136$10_ADDR[3:0]$2742 \main_uart_rx_fifo_wrport_adr + assign $0$memwr$\storage_5$ls180.v:10136$10_DATA[9:0]$2743 \main_uart_rx_fifo_wrport_dat_w + assign $0$memwr$\storage_5$ls180.v:10136$10_EN[9:0]$2744 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_6 $0\memdat_6[9:0] + update $memwr$\storage_5$ls180.v:10136$10_ADDR $0$memwr$\storage_5$ls180.v:10136$10_ADDR[3:0]$2742 + update $memwr$\storage_5$ls180.v:10136$10_DATA $0$memwr$\storage_5$ls180.v:10136$10_DATA[9:0]$2743 + update $memwr$\storage_5$ls180.v:10136$10_EN $0$memwr$\storage_5$ls180.v:10136$10_EN[9:0]$2744 + end + attribute \src "ls180.v:1014.12-1014.44" + process $proc$ls180.v:1014$3165 + assign { } { } + assign $1\main_pwm0_period_storage[31:0] 0 + sync always + sync init + update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] + end + attribute \src "ls180.v:10140.1-10143.4" + process $proc$ls180.v:10140$2746 + assign $0\memdat_7[9:0] \memdat_7 + attribute \src "ls180.v:10141.2-10142.55" + switch \main_uart_rx_fifo_rdport_re + attribute \src "ls180.v:10141.6-10141.33" + case 1'1 + assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10142$2747_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_7 $0\memdat_7[9:0] + end + attribute \src "ls180.v:1015.5-1015.31" + process $proc$ls180.v:1015$3166 + assign { } { } + assign $1\main_pwm0_period_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] + end + attribute \src "ls180.v:10150.1-10154.4" + process $proc$ls180.v:10150$2748 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_6$ls180.v:10152$11_ADDR[4:0]$2749 5'xxxxx + assign $0$memwr$\storage_6$ls180.v:10152$11_DATA[9:0]$2750 10'xxxxxxxxxx + assign $0$memwr$\storage_6$ls180.v:10152$11_EN[9:0]$2751 10'0000000000 + assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10153$2752_DATA + attribute \src "ls180.v:10151.2-10152.85" + switch \main_sdblock2mem_fifo_wrport_we + attribute \src "ls180.v:10151.6-10151.37" + case 1'1 + assign $0$memwr$\storage_6$ls180.v:10152$11_ADDR[4:0]$2749 \main_sdblock2mem_fifo_wrport_adr + assign $0$memwr$\storage_6$ls180.v:10152$11_DATA[9:0]$2750 \main_sdblock2mem_fifo_wrport_dat_w + assign $0$memwr$\storage_6$ls180.v:10152$11_EN[9:0]$2751 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_8 $0\memdat_8[9:0] + update $memwr$\storage_6$ls180.v:10152$11_ADDR $0$memwr$\storage_6$ls180.v:10152$11_ADDR[4:0]$2749 + update $memwr$\storage_6$ls180.v:10152$11_DATA $0$memwr$\storage_6$ls180.v:10152$11_DATA[9:0]$2750 + update $memwr$\storage_6$ls180.v:10152$11_EN $0$memwr$\storage_6$ls180.v:10152$11_EN[9:0]$2751 + end + attribute \src "ls180.v:10156.1-10157.4" + process $proc$ls180.v:10156$2753 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10164.1-10168.4" + process $proc$ls180.v:10164$2755 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_7$ls180.v:10166$12_ADDR[4:0]$2756 5'xxxxx + assign $0$memwr$\storage_7$ls180.v:10166$12_DATA[9:0]$2757 10'xxxxxxxxxx + assign $0$memwr$\storage_7$ls180.v:10166$12_EN[9:0]$2758 10'0000000000 + assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10167$2759_DATA + attribute \src "ls180.v:10165.2-10166.85" + switch \main_sdmem2block_fifo_wrport_we + attribute \src "ls180.v:10165.6-10165.37" + case 1'1 + assign $0$memwr$\storage_7$ls180.v:10166$12_ADDR[4:0]$2756 \main_sdmem2block_fifo_wrport_adr + assign $0$memwr$\storage_7$ls180.v:10166$12_DATA[9:0]$2757 \main_sdmem2block_fifo_wrport_dat_w + assign $0$memwr$\storage_7$ls180.v:10166$12_EN[9:0]$2758 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_9 $0\memdat_9[9:0] + update $memwr$\storage_7$ls180.v:10166$12_ADDR $0$memwr$\storage_7$ls180.v:10166$12_ADDR[4:0]$2756 + update $memwr$\storage_7$ls180.v:10166$12_DATA $0$memwr$\storage_7$ls180.v:10166$12_DATA[9:0]$2757 + update $memwr$\storage_7$ls180.v:10166$12_EN $0$memwr$\storage_7$ls180.v:10166$12_EN[9:0]$2758 + end + attribute \src "ls180.v:10170.1-10171.4" + process $proc$ls180.v:10170$2760 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1019.12-1019.37" + process $proc$ls180.v:1019$3167 + assign { } { } + assign $1\main_pwm1_counter[31:0] 0 + sync always + sync init + update \main_pwm1_counter $1\main_pwm1_counter[31:0] + end + attribute \src "ls180.v:1020.5-1020.36" + process $proc$ls180.v:1020$3168 + assign { } { } + assign $1\main_pwm1_enable_storage[0:0] 1'0 + sync always + sync init + update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] + end + attribute \src "ls180.v:1021.5-1021.31" + process $proc$ls180.v:1021$3169 + assign { } { } + assign $1\main_pwm1_enable_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] + end + attribute \src "ls180.v:1022.12-1022.43" + process $proc$ls180.v:1022$3170 + assign { } { } + assign $1\main_pwm1_width_storage[31:0] 0 + sync always + sync init + update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] + end + attribute \src "ls180.v:1023.5-1023.30" + process $proc$ls180.v:1023$3171 + assign { } { } + assign $1\main_pwm1_width_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] + end + attribute \src "ls180.v:1024.12-1024.44" + process $proc$ls180.v:1024$3172 + assign { } { } + assign $1\main_pwm1_period_storage[31:0] 0 + sync always + sync init + update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] + end + attribute \src "ls180.v:1025.5-1025.31" + process $proc$ls180.v:1025$3173 + assign { } { } + assign $1\main_pwm1_period_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] + end + attribute \src "ls180.v:1029.11-1029.34" + process $proc$ls180.v:1029$3174 + assign { } { } + assign $1\main_i2c_storage[2:0] 3'000 + sync always + sync init + update \main_i2c_storage $1\main_i2c_storage[2:0] + end + attribute \src "ls180.v:1030.5-1030.23" + process $proc$ls180.v:1030$3175 + assign { } { } + assign $1\main_i2c_re[0:0] 1'0 + sync always + sync init + update \main_i2c_re $1\main_i2c_re[0:0] + end + attribute \src "ls180.v:1036.11-1036.46" + process $proc$ls180.v:1036$3176 + assign { } { } + assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 + sync always + sync init + update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] + end + attribute \src "ls180.v:1037.5-1037.33" + process $proc$ls180.v:1037$3177 + assign { } { } + assign $1\main_sdphy_clocker_re[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] + end + attribute \src "ls180.v:1039.5-1039.35" + process $proc$ls180.v:1039$3178 + assign { } { } + assign $1\main_sdphy_clocker_clk0[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] + end + attribute \src "ls180.v:1041.11-1041.41" + process $proc$ls180.v:1041$3179 + assign { } { } + assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 + sync always + sync init + update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] + end + attribute \src "ls180.v:1042.5-1042.35" + process $proc$ls180.v:1042$3180 + assign { } { } + assign $1\main_sdphy_clocker_clk1[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] + end + attribute \src "ls180.v:1043.5-1043.36" + process $proc$ls180.v:1043$3181 + assign { } { } + assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] + end + attribute \src "ls180.v:1047.5-1047.40" + process $proc$ls180.v:1047$3182 + assign { } { } + assign $0\main_sdphy_init_initialize_w[0:0] 1'0 + sync always + update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0] + sync init + end + attribute \src "ls180.v:1052.5-1052.48" + process $proc$ls180.v:1052$3183 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1053.5-1053.50" + process $proc$ls180.v:1053$3184 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1054.5-1054.51" + process $proc$ls180.v:1054$3185 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1055.11-1055.57" + process $proc$ls180.v:1055$3186 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 + sync always + sync init + update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] + end + attribute \src "ls180.v:1056.5-1056.52" + process $proc$ls180.v:1056$3187 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] + end + attribute \src "ls180.v:1057.11-1057.39" + process $proc$ls180.v:1057$3188 + assign { } { } + assign $1\main_sdphy_init_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] + end + attribute \src "ls180.v:1062.5-1062.48" + process $proc$ls180.v:1062$3189 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1063.5-1063.50" + process $proc$ls180.v:1063$3190 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1064.5-1064.51" + process $proc$ls180.v:1064$3191 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1065.11-1065.57" + process $proc$ls180.v:1065$3192 + assign { } { } + assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1066.5-1066.52" + process $proc$ls180.v:1066$3193 + assign { } { } + assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1067.5-1067.38" + process $proc$ls180.v:1067$3194 + assign { } { } + assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] + end + attribute \src "ls180.v:1068.5-1068.38" + process $proc$ls180.v:1068$3195 + assign { } { } + assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] + end + attribute \src "ls180.v:1069.5-1069.37" + process $proc$ls180.v:1069$3196 + assign { } { } + assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] + end + attribute \src "ls180.v:1070.11-1070.51" + process $proc$ls180.v:1070$3197 + assign { } { } + assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] + end + attribute \src "ls180.v:1071.5-1071.32" + process $proc$ls180.v:1071$3198 + assign { } { } + assign $1\main_sdphy_cmdw_done[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] + end + attribute \src "ls180.v:1072.11-1072.39" + process $proc$ls180.v:1072$3199 + assign { } { } + assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] + end + attribute \src "ls180.v:1075.5-1075.49" + process $proc$ls180.v:1075$3200 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1076.5-1076.48" + process $proc$ls180.v:1076$3201 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1077.5-1077.55" + process $proc$ls180.v:1077$3202 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1079.5-1079.57" + process $proc$ls180.v:1079$3203 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1080.5-1080.58" + process $proc$ls180.v:1080$3204 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1082.11-1082.64" + process $proc$ls180.v:1082$3205 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1083.5-1083.59" + process $proc$ls180.v:1083$3206 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1085.5-1085.48" + process $proc$ls180.v:1085$3207 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1086.5-1086.50" + process $proc$ls180.v:1086$3208 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1087.5-1087.51" + process $proc$ls180.v:1087$3209 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1088.11-1088.57" + process $proc$ls180.v:1088$3210 + assign { } { } + assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1089.5-1089.52" + process $proc$ls180.v:1089$3211 + assign { } { } + assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1090.5-1090.38" + process $proc$ls180.v:1090$3212 + assign { } { } + assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] + end + attribute \src "ls180.v:1091.5-1091.38" + process $proc$ls180.v:1091$3213 + assign { } { } + assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] + end + attribute \src "ls180.v:1092.5-1092.37" + process $proc$ls180.v:1092$3214 + assign { } { } + assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] + end + attribute \src "ls180.v:1093.11-1093.53" + process $proc$ls180.v:1093$3215 + assign { } { } + assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] + end + attribute \src "ls180.v:1094.5-1094.40" + process $proc$ls180.v:1094$3216 + assign { } { } + assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] + end + attribute \src "ls180.v:1095.5-1095.40" + process $proc$ls180.v:1095$3217 + assign { } { } + assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] + end + attribute \src "ls180.v:1096.5-1096.39" + process $proc$ls180.v:1096$3218 + assign { } { } + assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] + end + attribute \src "ls180.v:1097.11-1097.53" + process $proc$ls180.v:1097$3219 + assign { } { } + assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] + end + attribute \src "ls180.v:1098.11-1098.55" + process $proc$ls180.v:1098$3220 + assign { } { } + assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + sync always + sync init + update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] + end + attribute \src "ls180.v:1099.12-1099.48" + process $proc$ls180.v:1099$3221 + assign { } { } + assign $1\main_sdphy_cmdr_timeout[31:0] 500000 + sync always + sync init + update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] + end + attribute \src "ls180.v:1100.11-1100.39" + process $proc$ls180.v:1100$3222 + assign { } { } + assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] + end + attribute \src "ls180.v:1102.5-1102.46" + process $proc$ls180.v:1102$3223 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1113.5-1113.53" + process $proc$ls180.v:1113$3224 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + end + attribute \src "ls180.v:1118.5-1118.36" + process $proc$ls180.v:1118$3225 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] + end + attribute \src "ls180.v:1121.5-1121.53" + process $proc$ls180.v:1121$3226 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1122.5-1122.52" + process $proc$ls180.v:1122$3227 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1126.5-1126.55" + process $proc$ls180.v:1126$3228 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + end + attribute \src "ls180.v:1127.5-1127.54" + process $proc$ls180.v:1127$3229 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + end + attribute \src "ls180.v:1128.11-1128.68" + process $proc$ls180.v:1128$3230 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1129.11-1129.81" + process $proc$ls180.v:1129$3231 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + end + attribute \src "ls180.v:1130.11-1130.54" + process $proc$ls180.v:1130$3232 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] + end + attribute \src "ls180.v:1132.5-1132.53" + process $proc$ls180.v:1132$3233 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1143.5-1143.49" + process $proc$ls180.v:1143$3234 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + end + attribute \src "ls180.v:1145.5-1145.49" + process $proc$ls180.v:1145$3235 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + end + attribute \src "ls180.v:1146.5-1146.48" + process $proc$ls180.v:1146$3236 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + end + attribute \src "ls180.v:1147.11-1147.62" + process $proc$ls180.v:1147$3237 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1148.5-1148.38" + process $proc$ls180.v:1148$3238 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] + end + attribute \src "ls180.v:1153.5-1153.49" + process $proc$ls180.v:1153$3239 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1154.5-1154.51" + process $proc$ls180.v:1154$3240 + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1155.5-1155.52" + process $proc$ls180.v:1155$3241 + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1156.11-1156.58" + process $proc$ls180.v:1156$3242 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] + end + attribute \src "ls180.v:1157.5-1157.53" + process $proc$ls180.v:1157$3243 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + end + attribute \src "ls180.v:1158.5-1158.39" + process $proc$ls180.v:1158$3244 + assign { } { } + assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] + end + attribute \src "ls180.v:1159.5-1159.39" + process $proc$ls180.v:1159$3245 + assign { } { } + assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] + end + attribute \src "ls180.v:116.5-116.49" + process $proc$ls180.v:116$2785 + assign { } { } + assign $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] + end + attribute \src "ls180.v:1160.5-1160.39" + process $proc$ls180.v:1160$3246 + assign { } { } + assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] + end + attribute \src "ls180.v:1161.5-1161.38" + process $proc$ls180.v:1161$3247 + assign { } { } + assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] + end + attribute \src "ls180.v:1162.11-1162.52" + process $proc$ls180.v:1162$3248 + assign { } { } + assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] + end + attribute \src "ls180.v:1163.5-1163.33" + process $proc$ls180.v:1163$3249 + assign { } { } + assign $1\main_sdphy_dataw_stop[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] + end + attribute \src "ls180.v:1164.11-1164.40" + process $proc$ls180.v:1164$3250 + assign { } { } + assign $1\main_sdphy_dataw_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] + end + attribute \src "ls180.v:1165.5-1165.50" + process $proc$ls180.v:1165$3251 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] + sync init + end + attribute \src "ls180.v:1167.5-1167.50" + process $proc$ls180.v:1167$3252 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1168.5-1168.49" + process $proc$ls180.v:1168$3253 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1169.5-1169.56" + process $proc$ls180.v:1169$3254 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1170.5-1170.58" + process $proc$ls180.v:1170$3255 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] + sync init + end + attribute \src "ls180.v:1171.5-1171.58" + process $proc$ls180.v:1171$3256 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1172.5-1172.59" + process $proc$ls180.v:1172$3257 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1173.11-1173.65" + process $proc$ls180.v:1173$3258 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] + sync init + end + attribute \src "ls180.v:1174.11-1174.65" + process $proc$ls180.v:1174$3259 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1175.5-1175.60" + process $proc$ls180.v:1175$3260 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1176.5-1176.34" + process $proc$ls180.v:1176$3261 + assign { } { } + assign $1\main_sdphy_dataw_start[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] + end + attribute \src "ls180.v:1177.5-1177.34" + process $proc$ls180.v:1177$3262 + assign { } { } + assign $1\main_sdphy_dataw_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] + end + attribute \src "ls180.v:1178.5-1178.34" + process $proc$ls180.v:1178$3263 + assign { } { } + assign $1\main_sdphy_dataw_error[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] + end + attribute \src "ls180.v:118.5-118.49" + process $proc$ls180.v:118$2786 + assign { } { } + assign $0\main_libresocsim_libresoc_jtag_wb_err[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_jtag_wb_err $0\main_libresocsim_libresoc_jtag_wb_err[0:0] + sync init + end + attribute \src "ls180.v:1180.5-1180.47" + process $proc$ls180.v:1180$3264 + assign { } { } + assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1191.5-1191.54" + process $proc$ls180.v:1191$3265 + assign { } { } + assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] + end + attribute \src "ls180.v:1196.5-1196.37" + process $proc$ls180.v:1196$3266 + assign { } { } + assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] + end + attribute \src "ls180.v:1199.5-1199.54" + process $proc$ls180.v:1199$3267 + assign { } { } + assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1200.5-1200.53" + process $proc$ls180.v:1200$3268 + assign { } { } + assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1204.5-1204.56" + process $proc$ls180.v:1204$3269 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] + end + attribute \src "ls180.v:1205.5-1205.55" + process $proc$ls180.v:1205$3270 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] + end + attribute \src "ls180.v:1206.11-1206.69" + process $proc$ls180.v:1206$3271 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1207.11-1207.82" + process $proc$ls180.v:1207$3272 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + end + attribute \src "ls180.v:1208.11-1208.55" + process $proc$ls180.v:1208$3273 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] + end + attribute \src "ls180.v:1210.5-1210.54" + process $proc$ls180.v:1210$3274 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1221.5-1221.50" + process $proc$ls180.v:1221$3275 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] + end + attribute \src "ls180.v:1223.5-1223.50" + process $proc$ls180.v:1223$3276 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] + end + attribute \src "ls180.v:1224.5-1224.49" + process $proc$ls180.v:1224$3277 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] + end + attribute \src "ls180.v:1225.11-1225.63" + process $proc$ls180.v:1225$3278 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1226.5-1226.39" + process $proc$ls180.v:1226$3279 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] + end + attribute \src "ls180.v:1229.5-1229.50" + process $proc$ls180.v:1229$3280 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1230.5-1230.49" + process $proc$ls180.v:1230$3281 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1231.5-1231.56" + process $proc$ls180.v:1231$3282 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1233.5-1233.58" + process $proc$ls180.v:1233$3283 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1234.5-1234.59" + process $proc$ls180.v:1234$3284 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1236.11-1236.65" + process $proc$ls180.v:1236$3285 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1237.5-1237.60" + process $proc$ls180.v:1237$3286 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1239.5-1239.49" + process $proc$ls180.v:1239$3287 + assign { } { } + assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1240.5-1240.51" + process $proc$ls180.v:1240$3288 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1241.5-1241.52" + process $proc$ls180.v:1241$3289 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1242.11-1242.58" + process $proc$ls180.v:1242$3290 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1243.5-1243.53" + process $proc$ls180.v:1243$3291 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1244.5-1244.39" + process $proc$ls180.v:1244$3292 + assign { } { } + assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] + end + attribute \src "ls180.v:1245.5-1245.39" + process $proc$ls180.v:1245$3293 + assign { } { } + assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] + end + attribute \src "ls180.v:1246.5-1246.38" + process $proc$ls180.v:1246$3294 + assign { } { } + assign $1\main_sdphy_datar_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] + end + attribute \src "ls180.v:1247.11-1247.61" + process $proc$ls180.v:1247$3295 + assign { } { } + assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] + end + attribute \src "ls180.v:1248.5-1248.41" + process $proc$ls180.v:1248$3296 + assign { } { } + assign $1\main_sdphy_datar_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] + end + attribute \src "ls180.v:1249.5-1249.41" + process $proc$ls180.v:1249$3297 + assign { } { } + assign $1\main_sdphy_datar_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] + end + attribute \src "ls180.v:1250.5-1250.41" + process $proc$ls180.v:1250$3298 + assign { } { } + assign $0\main_sdphy_datar_source_first[0:0] 1'0 + sync always + update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0] + sync init + end + attribute \src "ls180.v:1251.5-1251.40" + process $proc$ls180.v:1251$3299 + assign { } { } + assign $1\main_sdphy_datar_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] + end + attribute \src "ls180.v:1252.11-1252.54" + process $proc$ls180.v:1252$3300 + assign { } { } + assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] + end + attribute \src "ls180.v:1253.11-1253.56" + process $proc$ls180.v:1253$3301 + assign { } { } + assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 + sync always + sync init + update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] + end + attribute \src "ls180.v:1254.5-1254.33" + process $proc$ls180.v:1254$3302 + assign { } { } + assign $1\main_sdphy_datar_stop[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] + end + attribute \src "ls180.v:1255.12-1255.49" + process $proc$ls180.v:1255$3303 + assign { } { } + assign $1\main_sdphy_datar_timeout[31:0] 500000 + sync always + sync init + update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] + end + attribute \src "ls180.v:1256.11-1256.41" + process $proc$ls180.v:1256$3304 + assign { } { } + assign $1\main_sdphy_datar_count[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] + end + attribute \src "ls180.v:1258.5-1258.48" + process $proc$ls180.v:1258$3305 + assign { } { } + assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1269.5-1269.55" + process $proc$ls180.v:1269$3306 + assign { } { } + assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] + end + attribute \src "ls180.v:1274.5-1274.38" + process $proc$ls180.v:1274$3307 + assign { } { } + assign $1\main_sdphy_datar_datar_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] + end + attribute \src "ls180.v:1277.5-1277.55" + process $proc$ls180.v:1277$3308 + assign { } { } + assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1278.5-1278.54" + process $proc$ls180.v:1278$3309 + assign { } { } + assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:128.5-128.65" + process $proc$ls180.v:128$2787 + assign { } { } + assign $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 + sync always + sync init + update \main_libresocsim_libresoc_constraintmanager0_uart0_tx $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] + end + attribute \src "ls180.v:1282.5-1282.57" + process $proc$ls180.v:1282$3310 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] + end + attribute \src "ls180.v:1283.5-1283.56" + process $proc$ls180.v:1283$3311 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] + end + attribute \src "ls180.v:1284.11-1284.70" + process $proc$ls180.v:1284$3312 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1285.11-1285.83" + process $proc$ls180.v:1285$3313 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + end + attribute \src "ls180.v:1286.5-1286.50" + process $proc$ls180.v:1286$3314 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] + end + attribute \src "ls180.v:1288.5-1288.55" + process $proc$ls180.v:1288$3315 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1299.5-1299.51" + process $proc$ls180.v:1299$3316 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] + end + attribute \src "ls180.v:1301.5-1301.51" + process $proc$ls180.v:1301$3317 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] + end + attribute \src "ls180.v:1302.5-1302.50" + process $proc$ls180.v:1302$3318 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] + end + attribute \src "ls180.v:1303.11-1303.64" + process $proc$ls180.v:1303$3319 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1304.5-1304.40" + process $proc$ls180.v:1304$3320 + assign { } { } + assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] + end + attribute \src "ls180.v:1306.5-1306.35" + process $proc$ls180.v:1306$3321 + assign { } { } + assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 + sync always + sync init + update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] + end + attribute \src "ls180.v:1309.11-1309.42" + process $proc$ls180.v:1309$3322 + assign { } { } + assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 + sync always + sync init + update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] + end + attribute \src "ls180.v:1322.12-1322.52" + process $proc$ls180.v:1322$3323 + assign { } { } + assign $1\main_sdcore_cmd_argument_storage[31:0] 0 + sync always + sync init + update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] + end + attribute \src "ls180.v:1323.5-1323.39" + process $proc$ls180.v:1323$3324 + assign { } { } + assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] + end + attribute \src "ls180.v:1324.12-1324.51" + process $proc$ls180.v:1324$3325 + assign { } { } + assign $1\main_sdcore_cmd_command_storage[31:0] 0 + sync always + sync init + update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] + end + attribute \src "ls180.v:1325.5-1325.38" + process $proc$ls180.v:1325$3326 + assign { } { } + assign $1\main_sdcore_cmd_command_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] + end + attribute \src "ls180.v:1329.5-1329.34" + process $proc$ls180.v:1329$3327 + assign { } { } + assign $0\main_sdcore_cmd_send_w[0:0] 1'0 + sync always + update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0] + sync init + end + attribute \src "ls180.v:1330.13-1330.53" + process $proc$ls180.v:1330$3328 + assign { } { } + assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] + end + attribute \src "ls180.v:1336.11-1336.51" + process $proc$ls180.v:1336$3329 + assign { } { } + assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 + sync always + sync init + update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] + end + attribute \src "ls180.v:1337.5-1337.39" + process $proc$ls180.v:1337$3330 + assign { } { } + assign $1\main_sdcore_block_length_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] + end + attribute \src "ls180.v:1338.12-1338.51" + process $proc$ls180.v:1338$3331 + assign { } { } + assign $1\main_sdcore_block_count_storage[31:0] 0 + sync always + sync init + update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] + end + attribute \src "ls180.v:1339.5-1339.38" + process $proc$ls180.v:1339$3332 + assign { } { } + assign $1\main_sdcore_block_count_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] + end + attribute \src "ls180.v:1340.11-1340.51" + process $proc$ls180.v:1340$3333 + assign { } { } + assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + sync always + sync init + update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] + end + attribute \src "ls180.v:138.12-138.71" + process $proc$ls180.v:138$2788 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0] + end + attribute \src "ls180.v:1382.11-1382.47" + process $proc$ls180.v:1382$3334 + assign { } { } + assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 + sync always + sync init + update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] + end + attribute \src "ls180.v:1386.5-1386.49" + process $proc$ls180.v:1386$3335 + assign { } { } + assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] + end + attribute \src "ls180.v:139.12-139.73" + process $proc$ls180.v:139$2789 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:1390.5-1390.51" + process $proc$ls180.v:1390$3336 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] + end + attribute \src "ls180.v:1391.5-1391.51" + process $proc$ls180.v:1391$3337 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] + end + attribute \src "ls180.v:1392.5-1392.51" + process $proc$ls180.v:1392$3338 + assign { } { } + assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 + sync always + update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0] + sync init + end + attribute \src "ls180.v:1393.5-1393.50" + process $proc$ls180.v:1393$3339 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] + end + attribute \src "ls180.v:1394.11-1394.64" + process $proc$ls180.v:1394$3340 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] + end + attribute \src "ls180.v:1395.11-1395.48" + process $proc$ls180.v:1395$3341 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] + end + attribute \src "ls180.v:1396.12-1396.59" + process $proc$ls180.v:1396$3342 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + end + attribute \src "ls180.v:1400.12-1400.55" + process $proc$ls180.v:1400$3343 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] + end + attribute \src "ls180.v:1403.12-1403.59" + process $proc$ls180.v:1403$3344 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + end + attribute \src "ls180.v:1407.12-1407.55" + process $proc$ls180.v:1407$3345 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] + end + attribute \src "ls180.v:141.11-141.69" + process $proc$ls180.v:141$2790 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0] + end + attribute \src "ls180.v:1410.12-1410.59" + process $proc$ls180.v:1410$3346 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + end + attribute \src "ls180.v:1414.12-1414.55" + process $proc$ls180.v:1414$3347 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] + end + attribute \src "ls180.v:1417.12-1417.59" + process $proc$ls180.v:1417$3348 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + end + attribute \src "ls180.v:142.5-142.63" + process $proc$ls180.v:142$2791 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0] + end + attribute \src "ls180.v:1421.12-1421.55" + process $proc$ls180.v:1421$3349 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] + end + attribute \src "ls180.v:1424.12-1424.54" + process $proc$ls180.v:1424$3350 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] + end + attribute \src "ls180.v:1425.12-1425.54" + process $proc$ls180.v:1425$3351 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] + end + attribute \src "ls180.v:1426.12-1426.54" + process $proc$ls180.v:1426$3352 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] + end + attribute \src "ls180.v:1427.12-1427.54" + process $proc$ls180.v:1427$3353 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] + end + attribute \src "ls180.v:1428.5-1428.48" + process $proc$ls180.v:1428$3354 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] + end + attribute \src "ls180.v:1429.5-1429.48" + process $proc$ls180.v:1429$3355 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] + end + attribute \src "ls180.v:143.5-143.63" + process $proc$ls180.v:143$2792 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0] + end + attribute \src "ls180.v:1430.5-1430.48" + process $proc$ls180.v:1430$3356 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] + end + attribute \src "ls180.v:1431.5-1431.47" + process $proc$ls180.v:1431$3357 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] + end + attribute \src "ls180.v:1432.11-1432.61" + process $proc$ls180.v:1432$3358 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] + end + attribute \src "ls180.v:1433.5-1433.50" + process $proc$ls180.v:1433$3359 + assign { } { } + assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] + end + attribute \src "ls180.v:1435.5-1435.50" + process $proc$ls180.v:1435$3360 + assign { } { } + assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 + sync always + update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0] + sync init + end + attribute \src "ls180.v:1438.11-1438.47" + process $proc$ls180.v:1438$3361 + assign { } { } + assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] + end + attribute \src "ls180.v:1439.11-1439.47" + process $proc$ls180.v:1439$3362 + assign { } { } + assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + sync always + sync init + update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] + end + attribute \src "ls180.v:1440.12-1440.58" + process $proc$ls180.v:1440$3363 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + end + attribute \src "ls180.v:1444.12-1444.54" + process $proc$ls180.v:1444$3364 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] + end + attribute \src "ls180.v:1445.5-1445.46" + process $proc$ls180.v:1445$3365 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] + end + attribute \src "ls180.v:1447.12-1447.58" + process $proc$ls180.v:1447$3366 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + end + attribute \src "ls180.v:145.5-145.62" + process $proc$ls180.v:145$2793 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0] + end + attribute \src "ls180.v:1451.12-1451.54" + process $proc$ls180.v:1451$3367 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] + end + attribute \src "ls180.v:1452.5-1452.46" + process $proc$ls180.v:1452$3368 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] + end + attribute \src "ls180.v:1454.12-1454.58" + process $proc$ls180.v:1454$3369 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + end + attribute \src "ls180.v:1458.12-1458.54" + process $proc$ls180.v:1458$3370 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] + end + attribute \src "ls180.v:1459.5-1459.46" + process $proc$ls180.v:1459$3371 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] + end + attribute \src "ls180.v:146.11-146.69" + process $proc$ls180.v:146$2794 + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000 + sync always + update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0] + sync init + end + attribute \src "ls180.v:1461.12-1461.58" + process $proc$ls180.v:1461$3372 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + end + attribute \src "ls180.v:1465.12-1465.54" + process $proc$ls180.v:1465$3373 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] + end + attribute \src "ls180.v:1466.5-1466.46" + process $proc$ls180.v:1466$3374 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] + end + attribute \src "ls180.v:1468.12-1468.53" + process $proc$ls180.v:1468$3375 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] + end + attribute \src "ls180.v:1469.12-1469.53" + process $proc$ls180.v:1469$3376 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] + end + attribute \src "ls180.v:147.11-147.69" + process $proc$ls180.v:147$2795 + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00 + sync always + update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0] + sync init + end + attribute \src "ls180.v:1470.12-1470.53" + process $proc$ls180.v:1470$3377 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] + end + attribute \src "ls180.v:1471.12-1471.53" + process $proc$ls180.v:1471$3378 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] + end + attribute \src "ls180.v:1472.5-1472.43" + process $proc$ls180.v:1472$3379 + assign { } { } + assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] + end + attribute \src "ls180.v:1473.12-1473.51" + process $proc$ls180.v:1473$3380 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] + end + attribute \src "ls180.v:1474.12-1474.51" + process $proc$ls180.v:1474$3381 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] + end + attribute \src "ls180.v:1475.12-1475.51" + process $proc$ls180.v:1475$3382 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] + end + attribute \src "ls180.v:1476.12-1476.51" + process $proc$ls180.v:1476$3383 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] + end + attribute \src "ls180.v:1478.11-1478.39" + process $proc$ls180.v:1478$3384 + assign { } { } + assign $1\main_sdcore_cmd_count[2:0] 3'000 + sync always + sync init + update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] + end + attribute \src "ls180.v:1479.5-1479.32" + process $proc$ls180.v:1479$3385 + assign { } { } + assign $1\main_sdcore_cmd_done[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] + end + attribute \src "ls180.v:1480.5-1480.33" + process $proc$ls180.v:1480$3386 + assign { } { } + assign $1\main_sdcore_cmd_error[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] + end + attribute \src "ls180.v:1481.5-1481.35" + process $proc$ls180.v:1481$3387 + assign { } { } + assign $1\main_sdcore_cmd_timeout[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] + end + attribute \src "ls180.v:1483.12-1483.42" + process $proc$ls180.v:1483$3388 + assign { } { } + assign $1\main_sdcore_data_count[31:0] 0 + sync always + sync init + update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] + end + attribute \src "ls180.v:1484.5-1484.33" + process $proc$ls180.v:1484$3389 + assign { } { } + assign $1\main_sdcore_data_done[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] + end + attribute \src "ls180.v:1485.5-1485.34" + process $proc$ls180.v:1485$3390 + assign { } { } + assign $1\main_sdcore_data_error[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] + end + attribute \src "ls180.v:1486.5-1486.36" + process $proc$ls180.v:1486$3391 + assign { } { } + assign $1\main_sdcore_data_timeout[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] + end + attribute \src "ls180.v:149.5-149.44" + process $proc$ls180.v:149$2796 + assign { } { } + assign $1\main_libresocsim_converter0_skip[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0] + end + attribute \src "ls180.v:1495.11-1495.41" + process $proc$ls180.v:1495$3392 + assign { } { } + assign $0\main_interface0_bus_cti[2:0] 3'000 + sync always + update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0] + sync init + end + attribute \src "ls180.v:1496.11-1496.41" + process $proc$ls180.v:1496$3393 + assign { } { } + assign $0\main_interface0_bus_bte[1:0] 2'00 + sync always + update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0] + sync init + end + attribute \src "ls180.v:150.5-150.47" + process $proc$ls180.v:150$2797 + assign { } { } + assign $1\main_libresocsim_converter0_counter[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0] + end + attribute \src "ls180.v:1519.11-1519.45" + process $proc$ls180.v:1519$3394 + assign { } { } + assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 + sync always + sync init + update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] + end + attribute \src "ls180.v:152.12-152.53" + process $proc$ls180.v:152$2798 + assign { } { } + assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0] + end + attribute \src "ls180.v:1520.5-1520.41" + process $proc$ls180.v:1520$3395 + assign { } { } + assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 + sync always + update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1521.11-1521.47" + process $proc$ls180.v:1521$3396 + assign { } { } + assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] + end + attribute \src "ls180.v:1522.11-1522.47" + process $proc$ls180.v:1522$3397 + assign { } { } + assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] + end + attribute \src "ls180.v:1523.11-1523.50" + process $proc$ls180.v:1523$3398 + assign { } { } + assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:153.12-153.71" + process $proc$ls180.v:153$2799 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0] + end + attribute \src "ls180.v:154.12-154.73" + process $proc$ls180.v:154$2800 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:1543.5-1543.51" + process $proc$ls180.v:1543$3399 + assign { } { } + assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] + end + attribute \src "ls180.v:1544.5-1544.50" + process $proc$ls180.v:1544$3400 + assign { } { } + assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] + end + attribute \src "ls180.v:1545.12-1545.66" + process $proc$ls180.v:1545$3401 + assign { } { } + assign $1\main_sdblock2mem_converter_source_payload_data[31:0] 0 + sync always + sync init + update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[31:0] + end + attribute \src "ls180.v:1546.11-1546.77" + process $proc$ls180.v:1546$3402 + assign { } { } + assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] 3'000 + sync always + sync init + update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + end + attribute \src "ls180.v:1547.11-1547.50" + process $proc$ls180.v:1547$3403 + assign { } { } + assign $1\main_sdblock2mem_converter_demux[1:0] 2'00 + sync always + sync init + update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[1:0] + end + attribute \src "ls180.v:1549.5-1549.49" + process $proc$ls180.v:1549$3404 + assign { } { } + assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1555.5-1555.45" + process $proc$ls180.v:1555$3405 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] + end + attribute \src "ls180.v:1557.12-1557.62" + process $proc$ls180.v:1557$3406 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 + sync always + sync init + update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] + end + attribute \src "ls180.v:1558.12-1558.60" + process $proc$ls180.v:1558$3407 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 + sync always + sync init + update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] + end + attribute \src "ls180.v:156.11-156.69" + process $proc$ls180.v:156$2801 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0] + end + attribute \src "ls180.v:1560.5-1560.57" + process $proc$ls180.v:1560$3408 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + end + attribute \src "ls180.v:1564.12-1564.67" + process $proc$ls180.v:1564$3409 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + end + attribute \src "ls180.v:1565.5-1565.54" + process $proc$ls180.v:1565$3410 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + end + attribute \src "ls180.v:1566.12-1566.69" + process $proc$ls180.v:1566$3411 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + end + attribute \src "ls180.v:1567.5-1567.56" + process $proc$ls180.v:1567$3412 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + end + attribute \src "ls180.v:1568.5-1568.61" + process $proc$ls180.v:1568$3413 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + end + attribute \src "ls180.v:1569.5-1569.56" + process $proc$ls180.v:1569$3414 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + end + attribute \src "ls180.v:157.5-157.63" + process $proc$ls180.v:157$2802 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0] + end + attribute \src "ls180.v:1570.5-1570.53" + process $proc$ls180.v:1570$3415 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] + end + attribute \src "ls180.v:1572.5-1572.59" + process $proc$ls180.v:1572$3416 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + end + attribute \src "ls180.v:1573.5-1573.54" + process $proc$ls180.v:1573$3417 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + end + attribute \src "ls180.v:1575.12-1575.61" + process $proc$ls180.v:1575$3418 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] + end + attribute \src "ls180.v:1578.12-1578.43" + process $proc$ls180.v:1578$3419 + assign { } { } + assign $1\main_interface1_bus_adr[31:0] 0 + sync always + sync init + update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] + end + attribute \src "ls180.v:1579.12-1579.45" + process $proc$ls180.v:1579$3420 + assign { } { } + assign $0\main_interface1_bus_dat_w[31:0] 0 + sync always + update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[31:0] + sync init + end + attribute \src "ls180.v:158.5-158.63" + process $proc$ls180.v:158$2803 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0] + end + attribute \src "ls180.v:1581.11-1581.41" + process $proc$ls180.v:1581$3421 + assign { } { } + assign $1\main_interface1_bus_sel[3:0] 4'0000 + sync always + sync init + update \main_interface1_bus_sel $1\main_interface1_bus_sel[3:0] + end + attribute \src "ls180.v:1582.5-1582.35" + process $proc$ls180.v:1582$3422 + assign { } { } + assign $1\main_interface1_bus_cyc[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] + end + attribute \src "ls180.v:1583.5-1583.35" + process $proc$ls180.v:1583$3423 + assign { } { } + assign $1\main_interface1_bus_stb[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] + end + attribute \src "ls180.v:1585.5-1585.34" + process $proc$ls180.v:1585$3424 + assign { } { } + assign $1\main_interface1_bus_we[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] + end + attribute \src "ls180.v:1586.11-1586.41" + process $proc$ls180.v:1586$3425 + assign { } { } + assign $0\main_interface1_bus_cti[2:0] 3'000 + sync always + update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0] + sync init + end + attribute \src "ls180.v:1587.11-1587.41" + process $proc$ls180.v:1587$3426 + assign { } { } + assign $0\main_interface1_bus_bte[1:0] 2'00 + sync always + update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] + sync init + end + attribute \src "ls180.v:1594.5-1594.43" + process $proc$ls180.v:1594$3427 + assign { } { } + assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] + end + attribute \src "ls180.v:1595.5-1595.43" + process $proc$ls180.v:1595$3428 + assign { } { } + assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] + end + attribute \src "ls180.v:1596.5-1596.42" + process $proc$ls180.v:1596$3429 + assign { } { } + assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] + end + attribute \src "ls180.v:1597.12-1597.61" + process $proc$ls180.v:1597$3430 + assign { } { } + assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] + end + attribute \src "ls180.v:1598.5-1598.45" + process $proc$ls180.v:1598$3431 + assign { } { } + assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] + end + attribute \src "ls180.v:160.5-160.62" + process $proc$ls180.v:160$2804 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0] + end + attribute \src "ls180.v:1600.5-1600.45" + process $proc$ls180.v:1600$3432 + assign { } { } + assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 + sync always + update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0] + sync init + end + attribute \src "ls180.v:1601.5-1601.44" + process $proc$ls180.v:1601$3433 + assign { } { } + assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] + end + attribute \src "ls180.v:1602.12-1602.60" + process $proc$ls180.v:1602$3434 + assign { } { } + assign $1\main_sdmem2block_dma_source_payload_data[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[31:0] + end + attribute \src "ls180.v:1603.12-1603.45" + process $proc$ls180.v:1603$3435 + assign { } { } + assign $1\main_sdmem2block_dma_data[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[31:0] + end + attribute \src "ls180.v:1604.12-1604.53" + process $proc$ls180.v:1604$3436 + assign { } { } + assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] + end + attribute \src "ls180.v:1605.5-1605.40" + process $proc$ls180.v:1605$3437 + assign { } { } + assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] + end + attribute \src "ls180.v:1606.12-1606.55" + process $proc$ls180.v:1606$3438 + assign { } { } + assign $1\main_sdmem2block_dma_length_storage[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] + end + attribute \src "ls180.v:1607.5-1607.42" + process $proc$ls180.v:1607$3439 + assign { } { } + assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] + end + attribute \src "ls180.v:1608.5-1608.47" + process $proc$ls180.v:1608$3440 + assign { } { } + assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] + end + attribute \src "ls180.v:1609.5-1609.42" + process $proc$ls180.v:1609$3441 + assign { } { } + assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] + end + attribute \src "ls180.v:161.11-161.69" + process $proc$ls180.v:161$2805 + assign { } { } + assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000 + sync always + update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0] + sync init + end + attribute \src "ls180.v:1610.5-1610.44" + process $proc$ls180.v:1610$3442 + assign { } { } + assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] + end + attribute \src "ls180.v:1612.5-1612.45" + process $proc$ls180.v:1612$3443 + assign { } { } + assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] + end + attribute \src "ls180.v:1613.5-1613.40" + process $proc$ls180.v:1613$3444 + assign { } { } + assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] + end + attribute \src "ls180.v:1617.12-1617.47" + process $proc$ls180.v:1617$3445 + assign { } { } + assign $1\main_sdmem2block_dma_offset[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] + end + attribute \src "ls180.v:162.11-162.69" + process $proc$ls180.v:162$2806 + assign { } { } + assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00 + sync always + update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0] + sync init + end + attribute \src "ls180.v:1629.11-1629.64" + process $proc$ls180.v:1629$3446 + assign { } { } + assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1631.11-1631.48" + process $proc$ls180.v:1631$3447 + assign { } { } + assign $1\main_sdmem2block_converter_mux[1:0] 2'00 + sync always + sync init + update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[1:0] + end + attribute \src "ls180.v:164.5-164.44" + process $proc$ls180.v:164$2807 + assign { } { } + assign $1\main_libresocsim_converter1_skip[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0] + end + attribute \src "ls180.v:165.5-165.47" + process $proc$ls180.v:165$2808 + assign { } { } + assign $1\main_libresocsim_converter1_counter[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0] + end + attribute \src "ls180.v:1655.11-1655.45" + process $proc$ls180.v:1655$3448 + assign { } { } + assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 + sync always + sync init + update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] + end + attribute \src "ls180.v:1656.5-1656.41" + process $proc$ls180.v:1656$3449 + assign { } { } + assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 + sync always + update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1657.11-1657.47" + process $proc$ls180.v:1657$3450 + assign { } { } + assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] + end + attribute \src "ls180.v:1658.11-1658.47" + process $proc$ls180.v:1658$3451 + assign { } { } + assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] + end + attribute \src "ls180.v:1659.11-1659.50" + process $proc$ls180.v:1659$3452 + assign { } { } + assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:167.12-167.53" + process $proc$ls180.v:167$2809 + assign { } { } + assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0] + end + attribute \src "ls180.v:1674.5-1674.29" + process $proc$ls180.v:1674$3453 + assign { } { } + assign $1\libresocsim_done0[0:0] 1'0 + sync always + sync init + update \libresocsim_done0 $1\libresocsim_done0[0:0] + end + attribute \src "ls180.v:1675.5-1675.27" + process $proc$ls180.v:1675$3454 + assign { } { } + assign $1\libresocsim_irq[0:0] 1'0 + sync always + sync init + update \libresocsim_irq $1\libresocsim_irq[0:0] + end + attribute \src "ls180.v:1677.11-1677.34" + process $proc$ls180.v:1677$3455 + assign { } { } + assign $1\libresocsim_miso[7:0] 8'00000000 + sync always + sync init + update \libresocsim_miso $1\libresocsim_miso[7:0] + end + attribute \src "ls180.v:168.12-168.71" + process $proc$ls180.v:168$2810 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0] + end + attribute \src "ls180.v:1681.5-1681.30" + process $proc$ls180.v:1681$3456 + assign { } { } + assign $1\libresocsim_start1[0:0] 1'0 + sync always + sync init + update \libresocsim_start1 $1\libresocsim_start1[0:0] + end + attribute \src "ls180.v:1683.12-1683.47" + process $proc$ls180.v:1683$3457 + assign { } { } + assign $1\libresocsim_control_storage[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_control_storage $1\libresocsim_control_storage[15:0] + end + attribute \src "ls180.v:1684.5-1684.34" + process $proc$ls180.v:1684$3458 + assign { } { } + assign $1\libresocsim_control_re[0:0] 1'0 + sync always + sync init + update \libresocsim_control_re $1\libresocsim_control_re[0:0] + end + attribute \src "ls180.v:1688.11-1688.42" + process $proc$ls180.v:1688$3459 + assign { } { } + assign $1\libresocsim_mosi_storage[7:0] 8'00000000 + sync always + sync init + update \libresocsim_mosi_storage $1\libresocsim_mosi_storage[7:0] + end + attribute \src "ls180.v:1689.5-1689.31" + process $proc$ls180.v:1689$3460 + assign { } { } + assign $1\libresocsim_mosi_re[0:0] 1'0 + sync always + sync init + update \libresocsim_mosi_re $1\libresocsim_mosi_re[0:0] + end + attribute \src "ls180.v:169.12-169.73" + process $proc$ls180.v:169$2811 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:1693.5-1693.34" + process $proc$ls180.v:1693$3461 + assign { } { } + assign $1\libresocsim_cs_storage[0:0] 1'1 + sync always + sync init + update \libresocsim_cs_storage $1\libresocsim_cs_storage[0:0] + end + attribute \src "ls180.v:1694.5-1694.29" + process $proc$ls180.v:1694$3462 + assign { } { } + assign $1\libresocsim_cs_re[0:0] 1'0 + sync always + sync init + update \libresocsim_cs_re $1\libresocsim_cs_re[0:0] + end + attribute \src "ls180.v:1695.5-1695.40" + process $proc$ls180.v:1695$3463 + assign { } { } + assign $1\libresocsim_loopback_storage[0:0] 1'0 + sync always + sync init + update \libresocsim_loopback_storage $1\libresocsim_loopback_storage[0:0] + end + attribute \src "ls180.v:1696.5-1696.35" + process $proc$ls180.v:1696$3464 + assign { } { } + assign $1\libresocsim_loopback_re[0:0] 1'0 + sync always + sync init + update \libresocsim_loopback_re $1\libresocsim_loopback_re[0:0] + end + attribute \src "ls180.v:1697.5-1697.34" + process $proc$ls180.v:1697$3465 + assign { } { } + assign $1\libresocsim_clk_enable[0:0] 1'0 + sync always + sync init + update \libresocsim_clk_enable $1\libresocsim_clk_enable[0:0] + end + attribute \src "ls180.v:1698.5-1698.33" + process $proc$ls180.v:1698$3466 + assign { } { } + assign $1\libresocsim_cs_enable[0:0] 1'0 + sync always + sync init + update \libresocsim_cs_enable $1\libresocsim_cs_enable[0:0] + end + attribute \src "ls180.v:1699.11-1699.35" + process $proc$ls180.v:1699$3467 + assign { } { } + assign $1\libresocsim_count[2:0] 3'000 + sync always + sync init + update \libresocsim_count $1\libresocsim_count[2:0] + end + attribute \src "ls180.v:1700.5-1700.34" + process $proc$ls180.v:1700$3468 + assign { } { } + assign $1\libresocsim_mosi_latch[0:0] 1'0 + sync always + sync init + update \libresocsim_mosi_latch $1\libresocsim_mosi_latch[0:0] + end + attribute \src "ls180.v:1701.5-1701.34" + process $proc$ls180.v:1701$3469 + assign { } { } + assign $1\libresocsim_miso_latch[0:0] 1'0 + sync always + sync init + update \libresocsim_miso_latch $1\libresocsim_miso_latch[0:0] + end + attribute \src "ls180.v:1702.12-1702.44" + process $proc$ls180.v:1702$3470 + assign { } { } + assign $1\libresocsim_clk_divider1[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_clk_divider1 $1\libresocsim_clk_divider1[15:0] + end + attribute \src "ls180.v:1705.11-1705.39" + process $proc$ls180.v:1705$3471 + assign { } { } + assign $1\libresocsim_mosi_data[7:0] 8'00000000 + sync always + sync init + update \libresocsim_mosi_data $1\libresocsim_mosi_data[7:0] + end + attribute \src "ls180.v:1706.11-1706.38" + process $proc$ls180.v:1706$3472 + assign { } { } + assign $1\libresocsim_mosi_sel[2:0] 3'000 + sync always + sync init + update \libresocsim_mosi_sel $1\libresocsim_mosi_sel[2:0] + end + attribute \src "ls180.v:1707.11-1707.39" + process $proc$ls180.v:1707$3473 + assign { } { } + assign $1\libresocsim_miso_data[7:0] 8'00000000 + sync always + sync init + update \libresocsim_miso_data $1\libresocsim_miso_data[7:0] + end + attribute \src "ls180.v:1708.12-1708.41" + process $proc$ls180.v:1708$3474 + assign { } { } + assign $1\libresocsim_storage[15:0] 16'0000000001111101 + sync always + sync init + update \libresocsim_storage $1\libresocsim_storage[15:0] + end + attribute \src "ls180.v:1709.5-1709.26" + process $proc$ls180.v:1709$3475 + assign { } { } + assign $1\libresocsim_re[0:0] 1'0 + sync always + sync init + update \libresocsim_re $1\libresocsim_re[0:0] + end + attribute \src "ls180.v:171.11-171.69" + process $proc$ls180.v:171$2812 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_sel $1\main_libresocsim_interface2_converted_interface_sel[3:0] + end + attribute \src "ls180.v:1710.5-1710.36" + process $proc$ls180.v:1710$3476 + assign { } { } + assign $1\builder_converter0_state[0:0] 1'0 + sync always + sync init + update \builder_converter0_state $1\builder_converter0_state[0:0] + end + attribute \src "ls180.v:1711.5-1711.41" + process $proc$ls180.v:1711$3477 + assign { } { } + assign $1\builder_converter0_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] + end + attribute \src "ls180.v:1712.5-1712.69" + process $proc$ls180.v:1712$3478 + assign { } { } + assign $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_counter_converter0_next_value $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] + end + attribute \src "ls180.v:1713.5-1713.72" + process $proc$ls180.v:1713$3479 + assign { } { } + assign $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_counter_converter0_next_value_ce $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + end + attribute \src "ls180.v:1714.5-1714.36" + process $proc$ls180.v:1714$3480 + assign { } { } + assign $1\builder_converter1_state[0:0] 1'0 + sync always + sync init + update \builder_converter1_state $1\builder_converter1_state[0:0] + end + attribute \src "ls180.v:1715.5-1715.41" + process $proc$ls180.v:1715$3481 + assign { } { } + assign $1\builder_converter1_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] + end + attribute \src "ls180.v:1716.5-1716.69" + process $proc$ls180.v:1716$3482 + assign { } { } + assign $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_counter_converter1_next_value $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] + end + attribute \src "ls180.v:1717.5-1717.72" + process $proc$ls180.v:1717$3483 + assign { } { } + assign $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_counter_converter1_next_value_ce $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + end + attribute \src "ls180.v:1718.5-1718.36" + process $proc$ls180.v:1718$3484 + assign { } { } + assign $1\builder_converter2_state[0:0] 1'0 + sync always + sync init + update \builder_converter2_state $1\builder_converter2_state[0:0] + end + attribute \src "ls180.v:1719.5-1719.41" + process $proc$ls180.v:1719$3485 + assign { } { } + assign $1\builder_converter2_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] + end + attribute \src "ls180.v:172.5-172.63" + process $proc$ls180.v:172$2813 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0] + end + attribute \src "ls180.v:1720.5-1720.69" + process $proc$ls180.v:1720$3486 + assign { } { } + assign $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter2_counter_converter2_next_value $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] + end + attribute \src "ls180.v:1721.5-1721.72" + process $proc$ls180.v:1721$3487 + assign { } { } + assign $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter2_counter_converter2_next_value_ce $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + end + attribute \src "ls180.v:1722.11-1722.41" + process $proc$ls180.v:1722$3488 + assign { } { } + assign $1\builder_refresher_state[1:0] 2'00 + sync always + sync init + update \builder_refresher_state $1\builder_refresher_state[1:0] + end + attribute \src "ls180.v:1723.11-1723.46" + process $proc$ls180.v:1723$3489 + assign { } { } + assign $1\builder_refresher_next_state[1:0] 2'00 + sync always + sync init + update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] + end + attribute \src "ls180.v:1724.11-1724.44" + process $proc$ls180.v:1724$3490 + assign { } { } + assign $1\builder_bankmachine0_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] + end + attribute \src "ls180.v:1725.11-1725.49" + process $proc$ls180.v:1725$3491 + assign { } { } + assign $1\builder_bankmachine0_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] + end + attribute \src "ls180.v:1726.11-1726.44" + process $proc$ls180.v:1726$3492 + assign { } { } + assign $1\builder_bankmachine1_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] + end + attribute \src "ls180.v:1727.11-1727.49" + process $proc$ls180.v:1727$3493 + assign { } { } + assign $1\builder_bankmachine1_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] + end + attribute \src "ls180.v:1728.11-1728.44" + process $proc$ls180.v:1728$3494 + assign { } { } + assign $1\builder_bankmachine2_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] + end + attribute \src "ls180.v:1729.11-1729.49" + process $proc$ls180.v:1729$3495 + assign { } { } + assign $1\builder_bankmachine2_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] + end + attribute \src "ls180.v:173.5-173.63" + process $proc$ls180.v:173$2814 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_stb $1\main_libresocsim_interface2_converted_interface_stb[0:0] + end + attribute \src "ls180.v:1730.11-1730.44" + process $proc$ls180.v:1730$3496 + assign { } { } + assign $1\builder_bankmachine3_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] + end + attribute \src "ls180.v:1731.11-1731.49" + process $proc$ls180.v:1731$3497 + assign { } { } + assign $1\builder_bankmachine3_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] + end + attribute \src "ls180.v:1732.11-1732.43" + process $proc$ls180.v:1732$3498 + assign { } { } + assign $1\builder_multiplexer_state[2:0] 3'000 + sync always + sync init + update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] + end + attribute \src "ls180.v:1733.11-1733.48" + process $proc$ls180.v:1733$3499 + assign { } { } + assign $1\builder_multiplexer_next_state[2:0] 3'000 + sync always + sync init + update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] + end + attribute \src "ls180.v:1746.5-1746.27" + process $proc$ls180.v:1746$3500 + assign { } { } + assign $0\builder_locked0[0:0] 1'0 + sync always + update \builder_locked0 $0\builder_locked0[0:0] + sync init + end + attribute \src "ls180.v:1747.5-1747.27" + process $proc$ls180.v:1747$3501 + assign { } { } + assign $0\builder_locked1[0:0] 1'0 + sync always + update \builder_locked1 $0\builder_locked1[0:0] + sync init + end + attribute \src "ls180.v:1748.5-1748.27" + process $proc$ls180.v:1748$3502 + assign { } { } + assign $0\builder_locked2[0:0] 1'0 + sync always + update \builder_locked2 $0\builder_locked2[0:0] + sync init + end + attribute \src "ls180.v:1749.5-1749.27" + process $proc$ls180.v:1749$3503 + assign { } { } + assign $0\builder_locked3[0:0] 1'0 + sync always + update \builder_locked3 $0\builder_locked3[0:0] + sync init + end + attribute \src "ls180.v:175.5-175.62" + process $proc$ls180.v:175$2815 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_we $1\main_libresocsim_interface2_converted_interface_we[0:0] + end + attribute \src "ls180.v:1750.5-1750.42" + process $proc$ls180.v:1750$3504 + assign { } { } + assign $1\builder_new_master_wdata_ready[0:0] 1'0 + sync always + sync init + update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] + end + attribute \src "ls180.v:1751.5-1751.43" + process $proc$ls180.v:1751$3505 + assign { } { } + assign $1\builder_new_master_rdata_valid0[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] + end + attribute \src "ls180.v:1752.5-1752.43" + process $proc$ls180.v:1752$3506 + assign { } { } + assign $1\builder_new_master_rdata_valid1[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] + end + attribute \src "ls180.v:1753.5-1753.43" + process $proc$ls180.v:1753$3507 + assign { } { } + assign $1\builder_new_master_rdata_valid2[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] + end + attribute \src "ls180.v:1754.5-1754.43" + process $proc$ls180.v:1754$3508 + assign { } { } + assign $1\builder_new_master_rdata_valid3[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] + end + attribute \src "ls180.v:1755.5-1755.35" + process $proc$ls180.v:1755$3509 + assign { } { } + assign $1\builder_converter_state[0:0] 1'0 + sync always + sync init + update \builder_converter_state $1\builder_converter_state[0:0] + end + attribute \src "ls180.v:1756.5-1756.40" + process $proc$ls180.v:1756$3510 + assign { } { } + assign $1\builder_converter_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter_next_state $1\builder_converter_next_state[0:0] + end + attribute \src "ls180.v:1757.5-1757.55" + process $proc$ls180.v:1757$3511 + assign { } { } + assign $1\main_converter_counter_converter_next_value[0:0] 1'0 + sync always + sync init + update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] + end + attribute \src "ls180.v:1758.5-1758.58" + process $proc$ls180.v:1758$3512 + assign { } { } + assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] + end + attribute \src "ls180.v:1759.11-1759.42" + process $proc$ls180.v:1759$3513 + assign { } { } + assign $1\builder_spimaster0_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] + end + attribute \src "ls180.v:176.11-176.69" + process $proc$ls180.v:176$2816 + assign { } { } + assign $0\main_libresocsim_interface2_converted_interface_cti[2:0] 3'000 + sync always + update \main_libresocsim_interface2_converted_interface_cti $0\main_libresocsim_interface2_converted_interface_cti[2:0] + sync init + end + attribute \src "ls180.v:1760.11-1760.47" + process $proc$ls180.v:1760$3514 + assign { } { } + assign $1\builder_spimaster0_next_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] + end + attribute \src "ls180.v:1761.11-1761.61" + process $proc$ls180.v:1761$3515 + assign { } { } + assign $1\main_spi_master_count_spimaster0_next_value[2:0] 3'000 + sync always + sync init + update \main_spi_master_count_spimaster0_next_value $1\main_spi_master_count_spimaster0_next_value[2:0] + end + attribute \src "ls180.v:1762.5-1762.58" + process $proc$ls180.v:1762$3516 + assign { } { } + assign $1\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_spi_master_count_spimaster0_next_value_ce $1\main_spi_master_count_spimaster0_next_value_ce[0:0] + end + attribute \src "ls180.v:1763.5-1763.41" + process $proc$ls180.v:1763$3517 + assign { } { } + assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] + end + attribute \src "ls180.v:1764.5-1764.46" + process $proc$ls180.v:1764$3518 + assign { } { } + assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] + end + attribute \src "ls180.v:1765.11-1765.66" + process $proc$ls180.v:1765$3519 + assign { } { } + assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + end + attribute \src "ls180.v:1766.5-1766.63" + process $proc$ls180.v:1766$3520 + assign { } { } + assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + end + attribute \src "ls180.v:1767.11-1767.47" + process $proc$ls180.v:1767$3521 + assign { } { } + assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 + sync always + sync init + update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] + end + attribute \src "ls180.v:1768.11-1768.52" + process $proc$ls180.v:1768$3522 + assign { } { } + assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] + end + attribute \src "ls180.v:1769.11-1769.66" + process $proc$ls180.v:1769$3523 + assign { } { } + assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + end + attribute \src "ls180.v:177.11-177.69" + process $proc$ls180.v:177$2817 + assign { } { } + assign $0\main_libresocsim_interface2_converted_interface_bte[1:0] 2'00 + sync always + update \main_libresocsim_interface2_converted_interface_bte $0\main_libresocsim_interface2_converted_interface_bte[1:0] + sync init + end + attribute \src "ls180.v:1770.5-1770.63" + process $proc$ls180.v:1770$3524 + assign { } { } + assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + end + attribute \src "ls180.v:1771.11-1771.47" + process $proc$ls180.v:1771$3525 + assign { } { } + assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] + end + attribute \src "ls180.v:1772.11-1772.52" + process $proc$ls180.v:1772$3526 + assign { } { } + assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] + end + attribute \src "ls180.v:1773.11-1773.67" + process $proc$ls180.v:1773$3527 + assign { } { } + assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + end + attribute \src "ls180.v:1774.5-1774.64" + process $proc$ls180.v:1774$3528 + assign { } { } + assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + end + attribute \src "ls180.v:1775.12-1775.71" + process $proc$ls180.v:1775$3529 + assign { } { } + assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 + sync always + sync init + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + end + attribute \src "ls180.v:1776.5-1776.66" + process $proc$ls180.v:1776$3530 + assign { } { } + assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + end + attribute \src "ls180.v:1777.5-1777.66" + process $proc$ls180.v:1777$3531 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + end + attribute \src "ls180.v:1778.5-1778.69" + process $proc$ls180.v:1778$3532 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + end + attribute \src "ls180.v:1779.5-1779.41" + process $proc$ls180.v:1779$3533 + assign { } { } + assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] + end + attribute \src "ls180.v:1780.5-1780.46" + process $proc$ls180.v:1780$3534 + assign { } { } + assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] + end + attribute \src "ls180.v:1781.5-1781.66" + process $proc$ls180.v:1781$3535 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + end + attribute \src "ls180.v:1782.5-1782.69" + process $proc$ls180.v:1782$3536 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + end + attribute \src "ls180.v:1783.11-1783.41" + process $proc$ls180.v:1783$3537 + assign { } { } + assign $1\builder_sdphy_fsm_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] + end + attribute \src "ls180.v:1784.11-1784.46" + process $proc$ls180.v:1784$3538 + assign { } { } + assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] + end + attribute \src "ls180.v:1785.11-1785.61" + process $proc$ls180.v:1785$3539 + assign { } { } + assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + end + attribute \src "ls180.v:1786.5-1786.58" + process $proc$ls180.v:1786$3540 + assign { } { } + assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:1787.11-1787.48" + process $proc$ls180.v:1787$3541 + assign { } { } + assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] + end + attribute \src "ls180.v:1788.11-1788.53" + process $proc$ls180.v:1788$3542 + assign { } { } + assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] + end + attribute \src "ls180.v:1789.11-1789.70" + process $proc$ls180.v:1789$3543 + assign { } { } + assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + end + attribute \src "ls180.v:179.5-179.44" + process $proc$ls180.v:179$2818 + assign { } { } + assign $1\main_libresocsim_converter2_skip[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter2_skip $1\main_libresocsim_converter2_skip[0:0] + end + attribute \src "ls180.v:1790.5-1790.66" + process $proc$ls180.v:1790$3544 + assign { } { } + assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + end + attribute \src "ls180.v:1791.12-1791.73" + process $proc$ls180.v:1791$3545 + assign { } { } + assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + sync always + sync init + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + end + attribute \src "ls180.v:1792.5-1792.68" + process $proc$ls180.v:1792$3546 + assign { } { } + assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + end + attribute \src "ls180.v:1793.5-1793.69" + process $proc$ls180.v:1793$3547 + assign { } { } + assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + end + attribute \src "ls180.v:1794.5-1794.72" + process $proc$ls180.v:1794$3548 + assign { } { } + assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + end + attribute \src "ls180.v:1795.5-1795.52" + process $proc$ls180.v:1795$3549 + assign { } { } + assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 + sync always + sync init + update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] + end + attribute \src "ls180.v:1796.5-1796.57" + process $proc$ls180.v:1796$3550 + assign { } { } + assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] + end + attribute \src "ls180.v:1797.12-1797.93" + process $proc$ls180.v:1797$3551 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + end + attribute \src "ls180.v:1798.5-1798.88" + process $proc$ls180.v:1798$3552 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + end + attribute \src "ls180.v:1799.12-1799.93" + process $proc$ls180.v:1799$3553 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + end + attribute \src "ls180.v:180.5-180.47" + process $proc$ls180.v:180$2819 + assign { } { } + assign $1\main_libresocsim_converter2_counter[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter2_counter $1\main_libresocsim_converter2_counter[0:0] + end + attribute \src "ls180.v:1800.5-1800.88" + process $proc$ls180.v:1800$3554 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + end + attribute \src "ls180.v:1801.12-1801.93" + process $proc$ls180.v:1801$3555 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + end + attribute \src "ls180.v:1802.5-1802.88" + process $proc$ls180.v:1802$3556 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + end + attribute \src "ls180.v:1803.12-1803.93" + process $proc$ls180.v:1803$3557 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + end + attribute \src "ls180.v:1804.5-1804.88" + process $proc$ls180.v:1804$3558 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + end + attribute \src "ls180.v:1805.11-1805.87" + process $proc$ls180.v:1805$3559 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + end + attribute \src "ls180.v:1806.5-1806.84" + process $proc$ls180.v:1806$3560 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + end + attribute \src "ls180.v:1807.11-1807.42" + process $proc$ls180.v:1807$3561 + assign { } { } + assign $1\builder_sdcore_fsm_state[2:0] 3'000 + sync always + sync init + update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] + end + attribute \src "ls180.v:1808.11-1808.47" + process $proc$ls180.v:1808$3562 + assign { } { } + assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] + end + attribute \src "ls180.v:1809.5-1809.55" + process $proc$ls180.v:1809$3563 + assign { } { } + assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + end + attribute \src "ls180.v:1810.5-1810.58" + process $proc$ls180.v:1810$3564 + assign { } { } + assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + end + attribute \src "ls180.v:1811.5-1811.56" + process $proc$ls180.v:1811$3565 + assign { } { } + assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + end + attribute \src "ls180.v:1812.5-1812.59" + process $proc$ls180.v:1812$3566 + assign { } { } + assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + end + attribute \src "ls180.v:1813.11-1813.62" + process $proc$ls180.v:1813$3567 + assign { } { } + assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + sync always + sync init + update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + end + attribute \src "ls180.v:1814.5-1814.59" + process $proc$ls180.v:1814$3568 + assign { } { } + assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + end + attribute \src "ls180.v:1815.12-1815.65" + process $proc$ls180.v:1815$3569 + assign { } { } + assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + sync always + sync init + update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + end + attribute \src "ls180.v:1816.5-1816.60" + process $proc$ls180.v:1816$3570 + assign { } { } + assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + end + attribute \src "ls180.v:1817.5-1817.56" + process $proc$ls180.v:1817$3571 + assign { } { } + assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + end + attribute \src "ls180.v:1818.5-1818.59" + process $proc$ls180.v:1818$3572 + assign { } { } + assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + end + attribute \src "ls180.v:1819.5-1819.58" + process $proc$ls180.v:1819$3573 + assign { } { } + assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + end + attribute \src "ls180.v:182.12-182.53" + process $proc$ls180.v:182$2820 + assign { } { } + assign $1\main_libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_converter2_dat_r $1\main_libresocsim_converter2_dat_r[63:0] + end + attribute \src "ls180.v:1820.5-1820.61" + process $proc$ls180.v:1820$3574 + assign { } { } + assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + end + attribute \src "ls180.v:1821.5-1821.57" + process $proc$ls180.v:1821$3575 + assign { } { } + assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + end + attribute \src "ls180.v:1822.5-1822.60" + process $proc$ls180.v:1822$3576 + assign { } { } + assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + end + attribute \src "ls180.v:1823.5-1823.59" + process $proc$ls180.v:1823$3577 + assign { } { } + assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + end + attribute \src "ls180.v:1824.5-1824.62" + process $proc$ls180.v:1824$3578 + assign { } { } + assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + end + attribute \src "ls180.v:1825.13-1825.76" + process $proc$ls180.v:1825$3579 + assign { } { } + assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + end + attribute \src "ls180.v:1826.5-1826.69" + process $proc$ls180.v:1826$3580 + assign { } { } + assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + end + attribute \src "ls180.v:1827.11-1827.46" + process $proc$ls180.v:1827$3581 + assign { } { } + assign $1\builder_sdblock2memdma_state[1:0] 2'00 + sync always + sync init + update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] + end + attribute \src "ls180.v:1828.11-1828.51" + process $proc$ls180.v:1828$3582 + assign { } { } + assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] + end + attribute \src "ls180.v:1829.12-1829.87" + process $proc$ls180.v:1829$3583 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + end + attribute \src "ls180.v:1830.5-1830.82" + process $proc$ls180.v:1830$3584 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + end + attribute \src "ls180.v:1831.5-1831.44" + process $proc$ls180.v:1831$3585 + assign { } { } + assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 + sync always + sync init + update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] + end + attribute \src "ls180.v:1832.5-1832.49" + process $proc$ls180.v:1832$3586 + assign { } { } + assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] + end + attribute \src "ls180.v:1833.12-1833.75" + process $proc$ls180.v:1833$3587 + assign { } { } + assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + end + attribute \src "ls180.v:1834.5-1834.70" + process $proc$ls180.v:1834$3588 + assign { } { } + assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:1835.11-1835.60" + process $proc$ls180.v:1835$3589 + assign { } { } + assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + sync always + sync init + update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] + end + attribute \src "ls180.v:1836.11-1836.65" + process $proc$ls180.v:1836$3590 + assign { } { } + assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] + end + attribute \src "ls180.v:1837.12-1837.87" + process $proc$ls180.v:1837$3591 + assign { } { } + assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + end + attribute \src "ls180.v:1838.5-1838.82" + process $proc$ls180.v:1838$3592 + assign { } { } + assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + end + attribute \src "ls180.v:1839.11-1839.42" + process $proc$ls180.v:1839$3593 + assign { } { } + assign $1\builder_spimaster1_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] + end + attribute \src "ls180.v:1840.11-1840.47" + process $proc$ls180.v:1840$3594 + assign { } { } + assign $1\builder_spimaster1_next_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] + end + attribute \src "ls180.v:1841.11-1841.57" + process $proc$ls180.v:1841$3595 + assign { } { } + assign $1\libresocsim_count_spimaster1_next_value[2:0] 3'000 + sync always + sync init + update \libresocsim_count_spimaster1_next_value $1\libresocsim_count_spimaster1_next_value[2:0] + end + attribute \src "ls180.v:1842.5-1842.54" + process $proc$ls180.v:1842$3596 + assign { } { } + assign $1\libresocsim_count_spimaster1_next_value_ce[0:0] 1'0 + sync always + sync init + update \libresocsim_count_spimaster1_next_value_ce $1\libresocsim_count_spimaster1_next_value_ce[0:0] + end + attribute \src "ls180.v:1843.12-1843.43" + process $proc$ls180.v:1843$3597 + assign { } { } + assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 + sync always + sync init + update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] + end + attribute \src "ls180.v:1844.5-1844.34" + process $proc$ls180.v:1844$3598 + assign { } { } + assign $1\builder_libresocsim_we[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] + end + attribute \src "ls180.v:1845.11-1845.43" + process $proc$ls180.v:1845$3599 + assign { } { } + assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 + sync always + sync init + update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] + end + attribute \src "ls180.v:1849.12-1849.54" + process $proc$ls180.v:1849$3600 + assign { } { } + assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 + sync always + sync init + update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] + end + attribute \src "ls180.v:1853.5-1853.44" + process $proc$ls180.v:1853$3601 + assign { } { } + assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] + end + attribute \src "ls180.v:1857.5-1857.44" + process $proc$ls180.v:1857$3602 + assign { } { } + assign $0\builder_libresocsim_wishbone_err[0:0] 1'0 + sync always + update \builder_libresocsim_wishbone_err $0\builder_libresocsim_wishbone_err[0:0] + sync init + end + attribute \src "ls180.v:1860.12-1860.40" + process $proc$ls180.v:1860$3603 + assign { } { } + assign $1\builder_shared_dat_r[31:0] 0 + sync always + sync init + update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] + end + attribute \src "ls180.v:1864.5-1864.30" + process $proc$ls180.v:1864$3604 + assign { } { } + assign $1\builder_shared_ack[0:0] 1'0 + sync always + sync init + update \builder_shared_ack $1\builder_shared_ack[0:0] + end + attribute \src "ls180.v:1870.11-1870.31" + process $proc$ls180.v:1870$3605 + assign { } { } + assign $1\builder_grant[2:0] 3'000 + sync always + sync init + update \builder_grant $1\builder_grant[2:0] + end + attribute \src "ls180.v:1871.11-1871.35" + process $proc$ls180.v:1871$3606 + assign { } { } + assign $1\builder_slave_sel[4:0] 5'00000 + sync always + sync init + update \builder_slave_sel $1\builder_slave_sel[4:0] + end + attribute \src "ls180.v:1872.11-1872.37" + process $proc$ls180.v:1872$3607 + assign { } { } + assign $1\builder_slave_sel_r[4:0] 5'00000 + sync always + sync init + update \builder_slave_sel_r $1\builder_slave_sel_r[4:0] + end + attribute \src "ls180.v:1873.5-1873.25" + process $proc$ls180.v:1873$3608 + assign { } { } + assign $1\builder_error[0:0] 1'0 + sync always + sync init + update \builder_error $1\builder_error[0:0] + end + attribute \src "ls180.v:1876.12-1876.39" + process $proc$ls180.v:1876$3609 + assign { } { } + assign $1\builder_count[19:0] 20'11110100001001000000 + sync always + sync init + update \builder_count $1\builder_count[19:0] + end + attribute \src "ls180.v:1880.11-1880.51" + process $proc$ls180.v:1880$3610 + assign { } { } + assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:189.5-189.40" + process $proc$ls180.v:189$2821 + assign { } { } + assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] + end + attribute \src "ls180.v:1921.11-1921.51" + process $proc$ls180.v:1921$3611 + assign { } { } + assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:193.5-193.40" + process $proc$ls180.v:193$2822 + assign { } { } + assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 + sync always + update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:1950.11-1950.51" + process $proc$ls180.v:1950$3612 + assign { } { } + assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:196.11-196.37" + process $proc$ls180.v:196$2823 + assign { } { } + assign $1\main_libresocsim_we[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_we $1\main_libresocsim_we[3:0] + end + attribute \src "ls180.v:1963.11-1963.51" + process $proc$ls180.v:1963$3613 + assign { } { } + assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:198.12-198.49" + process $proc$ls180.v:198$2824 + assign { } { } + assign $1\main_libresocsim_load_storage[31:0] 0 + sync always + sync init + update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] + end + attribute \src "ls180.v:199.5-199.36" + process $proc$ls180.v:199$2825 + assign { } { } + assign $1\main_libresocsim_load_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] + end + attribute \src "ls180.v:200.12-200.51" + process $proc$ls180.v:200$2826 + assign { } { } + assign $1\main_libresocsim_reload_storage[31:0] 0 + sync always + sync init + update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] + end + attribute \src "ls180.v:2004.11-2004.51" + process $proc$ls180.v:2004$3614 + assign { } { } + assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:201.5-201.38" + process $proc$ls180.v:201$2827 + assign { } { } + assign $1\main_libresocsim_reload_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] + end + attribute \src "ls180.v:202.5-202.39" + process $proc$ls180.v:202$2828 + assign { } { } + assign $1\main_libresocsim_en_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] + end + attribute \src "ls180.v:203.5-203.34" + process $proc$ls180.v:203$2829 + assign { } { } + assign $1\main_libresocsim_en_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] + end + attribute \src "ls180.v:204.5-204.49" + process $proc$ls180.v:204$2830 + assign { } { } + assign $1\main_libresocsim_update_value_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] + end + attribute \src "ls180.v:2045.11-2045.51" + process $proc$ls180.v:2045$3615 + assign { } { } + assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:205.5-205.44" + process $proc$ls180.v:205$2831 + assign { } { } + assign $1\main_libresocsim_update_value_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] + end + attribute \src "ls180.v:206.12-206.49" + process $proc$ls180.v:206$2832 + assign { } { } + assign $1\main_libresocsim_value_status[31:0] 0 + sync always + sync init + update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] + end + attribute \src "ls180.v:210.5-210.41" + process $proc$ls180.v:210$2833 + assign { } { } + assign $1\main_libresocsim_zero_pending[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] + end + attribute \src "ls180.v:2110.11-2110.51" + process $proc$ls180.v:2110$3616 + assign { } { } + assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:212.5-212.39" + process $proc$ls180.v:212$2834 + assign { } { } + assign $1\main_libresocsim_zero_clear[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] + end + attribute \src "ls180.v:213.5-213.45" + process $proc$ls180.v:213$2835 + assign { } { } + assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] + end + attribute \src "ls180.v:222.5-222.49" + process $proc$ls180.v:222$2836 + assign { } { } + assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] + end + attribute \src "ls180.v:223.5-223.44" + process $proc$ls180.v:223$2837 + assign { } { } + assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] + end + attribute \src "ls180.v:224.12-224.42" + process $proc$ls180.v:224$2838 + assign { } { } + assign $1\main_libresocsim_value[31:0] 0 + sync always + sync init + update \main_libresocsim_value $1\main_libresocsim_value[31:0] + end + attribute \src "ls180.v:2243.11-2243.51" + process $proc$ls180.v:2243$3617 + assign { } { } + assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:228.5-228.24" + process $proc$ls180.v:228$2839 + assign { } { } + assign $1\main_int_rst[0:0] 1'1 + sync always + sync init + update \main_int_rst $1\main_int_rst[0:0] + end + attribute \src "ls180.v:2324.11-2324.51" + process $proc$ls180.v:2324$3618 + assign { } { } + assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2341.11-2341.51" + process $proc$ls180.v:2341$3619 + assign { } { } + assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2382.11-2382.52" + process $proc$ls180.v:2382$3620 + assign { } { } + assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2415.11-2415.52" + process $proc$ls180.v:2415$3621 + assign { } { } + assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:243.12-243.38" + process $proc$ls180.v:243$2840 + assign { } { } + assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] + end + attribute \src "ls180.v:244.5-244.36" + process $proc$ls180.v:244$2841 + assign { } { } + assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:245.11-245.32" + process $proc$ls180.v:245$2842 + assign { } { } + assign $1\main_rddata_en[2:0] 3'000 + sync always + sync init + update \main_rddata_en $1\main_rddata_en[2:0] + end + attribute \src "ls180.v:2456.11-2456.52" + process $proc$ls180.v:2456$3622 + assign { } { } + assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:248.5-248.36" + process $proc$ls180.v:248$2843 + assign { } { } + assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] + end + attribute \src "ls180.v:249.5-249.35" + process $proc$ls180.v:249$2844 + assign { } { } + assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] + end + attribute \src "ls180.v:250.5-250.36" + process $proc$ls180.v:250$2845 + assign { } { } + assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] + end + attribute \src "ls180.v:251.5-251.35" + process $proc$ls180.v:251$2846 + assign { } { } + assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] + end + attribute \src "ls180.v:2521.11-2521.52" + process $proc$ls180.v:2521$3623 + assign { } { } + assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2546.11-2546.52" + process $proc$ls180.v:2546$3624 + assign { } { } + assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:255.5-255.36" + process $proc$ls180.v:255$2847 + assign { } { } + assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 + sync always + update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] + sync init + end + attribute \src "ls180.v:2568.11-2568.31" + process $proc$ls180.v:2568$3625 + assign { } { } + assign $1\builder_state[1:0] 2'00 + sync always + sync init + update \builder_state $1\builder_state[1:0] + end + attribute \src "ls180.v:2569.11-2569.36" + process $proc$ls180.v:2569$3626 + assign { } { } + assign $1\builder_next_state[1:0] 2'00 + sync always + sync init + update \builder_next_state $1\builder_next_state[1:0] + end + attribute \src "ls180.v:2570.11-2570.55" + process $proc$ls180.v:2570$3627 + assign { } { } + assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 + sync always + sync init + update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] + end + attribute \src "ls180.v:2571.5-2571.52" + process $proc$ls180.v:2571$3628 + assign { } { } + assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] + end + attribute \src "ls180.v:2572.12-2572.55" + process $proc$ls180.v:2572$3629 + assign { } { } + assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + sync always + sync init + update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] + end + attribute \src "ls180.v:2573.5-2573.50" + process $proc$ls180.v:2573$3630 + assign { } { } + assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] + end + attribute \src "ls180.v:2574.5-2574.46" + process $proc$ls180.v:2574$3631 + assign { } { } + assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] + end + attribute \src "ls180.v:2575.5-2575.49" + process $proc$ls180.v:2575$3632 + assign { } { } + assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] + end + attribute \src "ls180.v:2576.5-2576.41" + process $proc$ls180.v:2576$3633 + assign { } { } + assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] + end + attribute \src "ls180.v:2577.12-2577.49" + process $proc$ls180.v:2577$3634 + assign { } { } + assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:2578.11-2578.47" + process $proc$ls180.v:2578$3635 + assign { } { } + assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] + end + attribute \src "ls180.v:2579.5-2579.41" + process $proc$ls180.v:2579$3636 + assign { } { } + assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:2580.5-2580.41" + process $proc$ls180.v:2580$3637 + assign { } { } + assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:2581.5-2581.41" + process $proc$ls180.v:2581$3638 + assign { } { } + assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:2582.5-2582.39" + process $proc$ls180.v:2582$3639 + assign { } { } + assign $1\builder_comb_t_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] + end + attribute \src "ls180.v:2583.5-2583.39" + process $proc$ls180.v:2583$3640 + assign { } { } + assign $1\builder_comb_t_array_muxed1[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] + end + attribute \src "ls180.v:2584.5-2584.39" + process $proc$ls180.v:2584$3641 + assign { } { } + assign $1\builder_comb_t_array_muxed2[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] + end + attribute \src "ls180.v:2585.5-2585.41" + process $proc$ls180.v:2585$3642 + assign { } { } + assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:2586.12-2586.49" + process $proc$ls180.v:2586$3643 + assign { } { } + assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] + end + attribute \src "ls180.v:2587.11-2587.47" + process $proc$ls180.v:2587$3644 + assign { } { } + assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] + end + attribute \src "ls180.v:2588.5-2588.41" + process $proc$ls180.v:2588$3645 + assign { } { } + assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] + end + attribute \src "ls180.v:2589.5-2589.42" + process $proc$ls180.v:2589$3646 + assign { } { } + assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] + end + attribute \src "ls180.v:2590.5-2590.42" + process $proc$ls180.v:2590$3647 + assign { } { } + assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] + end + attribute \src "ls180.v:2591.5-2591.39" + process $proc$ls180.v:2591$3648 + assign { } { } + assign $1\builder_comb_t_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] + end + attribute \src "ls180.v:2592.5-2592.39" + process $proc$ls180.v:2592$3649 + assign { } { } + assign $1\builder_comb_t_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] + end + attribute \src "ls180.v:2593.5-2593.39" + process $proc$ls180.v:2593$3650 + assign { } { } + assign $1\builder_comb_t_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] + end + attribute \src "ls180.v:2594.12-2594.50" + process $proc$ls180.v:2594$3651 + assign { } { } + assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] + end + attribute \src "ls180.v:2595.5-2595.42" + process $proc$ls180.v:2595$3652 + assign { } { } + assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] + end + attribute \src "ls180.v:2596.5-2596.42" + process $proc$ls180.v:2596$3653 + assign { } { } + assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] + end + attribute \src "ls180.v:2597.12-2597.50" + process $proc$ls180.v:2597$3654 + assign { } { } + assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] + end + attribute \src "ls180.v:2598.5-2598.42" + process $proc$ls180.v:2598$3655 + assign { } { } + assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] + end + attribute \src "ls180.v:2599.5-2599.42" + process $proc$ls180.v:2599$3656 + assign { } { } + assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] + end + attribute \src "ls180.v:260.12-260.45" + process $proc$ls180.v:260$2848 + assign { } { } + assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] + end + attribute \src "ls180.v:2600.12-2600.50" + process $proc$ls180.v:2600$3657 + assign { } { } + assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] + end + attribute \src "ls180.v:2601.5-2601.42" + process $proc$ls180.v:2601$3658 + assign { } { } + assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] + end + attribute \src "ls180.v:2602.5-2602.42" + process $proc$ls180.v:2602$3659 + assign { } { } + assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] + end + attribute \src "ls180.v:2603.12-2603.50" + process $proc$ls180.v:2603$3660 + assign { } { } + assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] + end + attribute \src "ls180.v:2604.5-2604.42" + process $proc$ls180.v:2604$3661 + assign { } { } + assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] + end + attribute \src "ls180.v:2605.5-2605.42" + process $proc$ls180.v:2605$3662 + assign { } { } + assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] + end + attribute \src "ls180.v:2606.12-2606.50" + process $proc$ls180.v:2606$3663 + assign { } { } + assign $1\builder_comb_rhs_array_muxed24[31:0] 0 + sync always + sync init + update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] + end + attribute \src "ls180.v:2607.12-2607.50" + process $proc$ls180.v:2607$3664 + assign { } { } + assign $1\builder_comb_rhs_array_muxed25[31:0] 0 + sync always + sync init + update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[31:0] + end + attribute \src "ls180.v:2608.11-2608.48" + process $proc$ls180.v:2608$3665 + assign { } { } + assign $1\builder_comb_rhs_array_muxed26[3:0] 4'0000 + sync always + sync init + update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[3:0] + end + attribute \src "ls180.v:2609.5-2609.42" + process $proc$ls180.v:2609$3666 + assign { } { } + assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] + end + attribute \src "ls180.v:261.5-261.43" + process $proc$ls180.v:261$2849 + assign { } { } + assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:2610.5-2610.42" + process $proc$ls180.v:2610$3667 + assign { } { } + assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] + end + attribute \src "ls180.v:2611.5-2611.42" + process $proc$ls180.v:2611$3668 + assign { } { } + assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] + end + attribute \src "ls180.v:2612.11-2612.48" + process $proc$ls180.v:2612$3669 + assign { } { } + assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 + sync always + sync init + update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] + end + attribute \src "ls180.v:2613.11-2613.48" + process $proc$ls180.v:2613$3670 + assign { } { } + assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] + end + attribute \src "ls180.v:2614.11-2614.47" + process $proc$ls180.v:2614$3671 + assign { } { } + assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 + sync always + sync init + update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] + end + attribute \src "ls180.v:2615.12-2615.49" + process $proc$ls180.v:2615$3672 + assign { } { } + assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 + sync always + sync init + update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:2616.5-2616.41" + process $proc$ls180.v:2616$3673 + assign { } { } + assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] + end + attribute \src "ls180.v:2617.5-2617.41" + process $proc$ls180.v:2617$3674 + assign { } { } + assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:2618.5-2618.41" + process $proc$ls180.v:2618$3675 + assign { } { } + assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:2619.5-2619.41" + process $proc$ls180.v:2619$3676 + assign { } { } + assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:2620.5-2620.41" + process $proc$ls180.v:2620$3677 + assign { } { } + assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:2621.5-2621.39" + process $proc$ls180.v:2621$3678 + assign { } { } + assign $1\builder_sync_f_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] + end + attribute \src "ls180.v:2622.5-2622.39" + process $proc$ls180.v:2622$3679 + assign { } { } + assign $1\builder_sync_f_array_muxed1[0:0] 1'0 + sync always + sync init + update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] + end + attribute \src "ls180.v:2679.32-2679.66" + process $proc$ls180.v:2679$3680 + assign { } { } + assign $1\builder_multiregimpl0_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] + end + attribute \src "ls180.v:2680.32-2680.66" + process $proc$ls180.v:2680$3681 + assign { } { } + assign $1\builder_multiregimpl0_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] + end + attribute \src "ls180.v:2681.32-2681.66" + process $proc$ls180.v:2681$3682 + assign { } { } + assign $1\builder_multiregimpl1_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] + end + attribute \src "ls180.v:2682.32-2682.66" + process $proc$ls180.v:2682$3683 + assign { } { } + assign $1\builder_multiregimpl1_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] + end + attribute \src "ls180.v:2683.32-2683.66" + process $proc$ls180.v:2683$3684 + assign { } { } + assign $1\builder_multiregimpl2_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] + end + attribute \src "ls180.v:2684.32-2684.66" + process $proc$ls180.v:2684$3685 + assign { } { } + assign $1\builder_multiregimpl2_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] + end + attribute \src "ls180.v:2685.32-2685.66" + process $proc$ls180.v:2685$3686 + assign { } { } + assign $1\builder_multiregimpl3_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] + end + attribute \src "ls180.v:2686.32-2686.66" + process $proc$ls180.v:2686$3687 + assign { } { } + assign $1\builder_multiregimpl3_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] + end + attribute \src "ls180.v:2687.32-2687.66" + process $proc$ls180.v:2687$3688 + assign { } { } + assign $1\builder_multiregimpl4_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] + end + attribute \src "ls180.v:2688.32-2688.66" + process $proc$ls180.v:2688$3689 + assign { } { } + assign $1\builder_multiregimpl4_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] + end + attribute \src "ls180.v:2689.32-2689.66" + process $proc$ls180.v:2689$3690 + assign { } { } + assign $1\builder_multiregimpl5_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] + end + attribute \src "ls180.v:2690.32-2690.66" + process $proc$ls180.v:2690$3691 + assign { } { } + assign $1\builder_multiregimpl5_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] + end + attribute \src "ls180.v:2691.32-2691.66" + process $proc$ls180.v:2691$3692 + assign { } { } + assign $1\builder_multiregimpl6_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] + end + attribute \src "ls180.v:2692.32-2692.66" + process $proc$ls180.v:2692$3693 + assign { } { } + assign $1\builder_multiregimpl6_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] + end + attribute \src "ls180.v:2693.32-2693.66" + process $proc$ls180.v:2693$3694 + assign { } { } + assign $1\builder_multiregimpl7_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] + end + attribute \src "ls180.v:2694.32-2694.66" + process $proc$ls180.v:2694$3695 + assign { } { } + assign $1\builder_multiregimpl7_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] + end + attribute \src "ls180.v:2695.32-2695.66" + process $proc$ls180.v:2695$3696 + assign { } { } + assign $1\builder_multiregimpl8_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] + end + attribute \src "ls180.v:2696.32-2696.66" + process $proc$ls180.v:2696$3697 + assign { } { } + assign $1\builder_multiregimpl8_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] + end + attribute \src "ls180.v:2697.32-2697.66" + process $proc$ls180.v:2697$3698 + assign { } { } + assign $1\builder_multiregimpl9_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] + end + attribute \src "ls180.v:2698.32-2698.66" + process $proc$ls180.v:2698$3699 + assign { } { } + assign $1\builder_multiregimpl9_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] + end + attribute \src "ls180.v:2699.32-2699.67" + process $proc$ls180.v:2699$3700 + assign { } { } + assign $1\builder_multiregimpl10_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] + end + attribute \src "ls180.v:2700.32-2700.67" + process $proc$ls180.v:2700$3701 + assign { } { } + assign $1\builder_multiregimpl10_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] + end + attribute \src "ls180.v:2701.32-2701.67" + process $proc$ls180.v:2701$3702 + assign { } { } + assign $1\builder_multiregimpl11_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] + end + attribute \src "ls180.v:2702.32-2702.67" + process $proc$ls180.v:2702$3703 + assign { } { } + assign $1\builder_multiregimpl11_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] + end + attribute \src "ls180.v:2703.32-2703.67" + process $proc$ls180.v:2703$3704 + assign { } { } + assign $1\builder_multiregimpl12_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] + end + attribute \src "ls180.v:2704.32-2704.67" + process $proc$ls180.v:2704$3705 + assign { } { } + assign $1\builder_multiregimpl12_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] + end + attribute \src "ls180.v:2705.32-2705.67" + process $proc$ls180.v:2705$3706 + assign { } { } + assign $1\builder_multiregimpl13_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] + end + attribute \src "ls180.v:2706.32-2706.67" + process $proc$ls180.v:2706$3707 + assign { } { } + assign $1\builder_multiregimpl13_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] + end + attribute \src "ls180.v:2707.32-2707.67" + process $proc$ls180.v:2707$3708 + assign { } { } + assign $1\builder_multiregimpl14_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] + end + attribute \src "ls180.v:2708.32-2708.67" + process $proc$ls180.v:2708$3709 + assign { } { } + assign $1\builder_multiregimpl14_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] + end + attribute \src "ls180.v:2709.32-2709.67" + process $proc$ls180.v:2709$3710 + assign { } { } + assign $1\builder_multiregimpl15_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] + end + attribute \src "ls180.v:2710.32-2710.67" + process $proc$ls180.v:2710$3711 + assign { } { } + assign $1\builder_multiregimpl15_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] + end + attribute \src "ls180.v:2711.32-2711.67" + process $proc$ls180.v:2711$3712 + assign { } { } + assign $1\builder_multiregimpl16_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] + end + attribute \src "ls180.v:2712.32-2712.67" + process $proc$ls180.v:2712$3713 + assign { } { } + assign $1\builder_multiregimpl16_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0] + end + attribute \src "ls180.v:2751.1-2756.4" + process $proc$ls180.v:2751$13 + assign { } { } + assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 + assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } + assign $0\main_libresocsim_libresoc_interrupt[15:0] [0] \main_libresocsim_irq + assign $0\main_libresocsim_libresoc_interrupt[15:0] [1] \main_uart_irq + sync always + update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] + end + attribute \src "ls180.v:2758.1-2768.4" + process $proc$ls180.v:2758$15 + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 + attribute \src "ls180.v:2760.2-2767.9" + switch \main_libresocsim_converter0_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [63:32] + case + end + sync always + update \main_libresocsim_interface0_converted_interface_dat_w $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:276.12-276.46" + process $proc$ls180.v:276$2850 + assign { } { } + assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] + end + attribute \src "ls180.v:277.5-277.44" + process $proc$ls180.v:277$2851 + assign { } { } + assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:2770.1-2816.4" + process $proc$ls180.v:2770$16 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 + assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 + assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 + assign $0\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 + assign $0\main_libresocsim_converter0_skip[0:0] 1'0 + assign { } { } + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 + assign $0\builder_converter0_next_state[0:0] \builder_converter0_state + attribute \src "ls180.v:2782.2-2815.9" + switch \builder_converter0_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] { \main_libresocsim_libresoc_ibus_adr \main_libresocsim_converter0_counter } + attribute \src "ls180.v:2785.4-2792.11" + switch \main_libresocsim_converter0_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [7:4] + case + end + attribute \src "ls180.v:2793.4-2806.7" + switch $and$ls180.v:2793$17_Y + attribute \src "ls180.v:2793.8-2793.81" + case 1'1 + assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2794$18_Y + assign $0\main_libresocsim_interface0_converted_interface_we[0:0] \main_libresocsim_libresoc_ibus_we + assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2796$19_Y + assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2797$20_Y + attribute \src "ls180.v:2798.5-2805.8" + switch $or$ls180.v:2798$21_Y + attribute \src "ls180.v:2798.9-2798.97" + case 1'1 + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2799$22_Y + assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2801.6-2804.9" + switch $eq$ls180.v:2801$23_Y + attribute \src "ls180.v:2801.10-2801.55" + case 1'1 + assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'1 + assign $0\builder_converter0_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2811.4-2813.7" + switch $and$ls180.v:2811$24_Y + attribute \src "ls180.v:2811.8-2811.81" + case 1'1 + assign $0\builder_converter0_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_ibus_ack $0\main_libresocsim_libresoc_ibus_ack[0:0] + update \main_libresocsim_interface0_converted_interface_adr $0\main_libresocsim_interface0_converted_interface_adr[29:0] + update \main_libresocsim_interface0_converted_interface_sel $0\main_libresocsim_interface0_converted_interface_sel[3:0] + update \main_libresocsim_interface0_converted_interface_cyc $0\main_libresocsim_interface0_converted_interface_cyc[0:0] + update \main_libresocsim_interface0_converted_interface_stb $0\main_libresocsim_interface0_converted_interface_stb[0:0] + update \main_libresocsim_interface0_converted_interface_we $0\main_libresocsim_interface0_converted_interface_we[0:0] + update \main_libresocsim_converter0_skip $0\main_libresocsim_converter0_skip[0:0] + update \builder_converter0_next_state $0\builder_converter0_next_state[0:0] + update \main_libresocsim_converter0_counter_converter0_next_value $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] + update \main_libresocsim_converter0_counter_converter0_next_value_ce $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + end + attribute \src "ls180.v:278.12-278.48" + process $proc$ls180.v:278$2852 + assign { } { } + assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] + end + attribute \src "ls180.v:279.11-279.43" + process $proc$ls180.v:279$2853 + assign { } { } + assign $1\main_sdram_master_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] + end + attribute \src "ls180.v:280.5-280.38" + process $proc$ls180.v:280$2854 + assign { } { } + assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] + end + attribute \src "ls180.v:281.5-281.37" + process $proc$ls180.v:281$2855 + assign { } { } + assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] + end + attribute \src "ls180.v:2818.1-2828.4" + process $proc$ls180.v:2818$26 + assign { } { } + assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 + attribute \src "ls180.v:2820.2-2827.9" + switch \main_libresocsim_converter1_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [63:32] + case + end + sync always + update \main_libresocsim_interface1_converted_interface_dat_w $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:282.5-282.38" + process $proc$ls180.v:282$2856 + assign { } { } + assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] + end + attribute \src "ls180.v:283.5-283.37" + process $proc$ls180.v:283$2857 + assign { } { } + assign $1\main_sdram_master_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] + end + attribute \src "ls180.v:2830.1-2876.4" + process $proc$ls180.v:2830$27 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_libresocsim_converter1_skip[0:0] 1'0 + assign { } { } + assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 + assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 + assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 + assign $0\builder_converter1_next_state[0:0] \builder_converter1_state + attribute \src "ls180.v:2842.2-2875.9" + switch \builder_converter1_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] { \main_libresocsim_libresoc_dbus_adr \main_libresocsim_converter1_counter } + attribute \src "ls180.v:2845.4-2852.11" + switch \main_libresocsim_converter1_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [7:4] + case + end + attribute \src "ls180.v:2853.4-2866.7" + switch $and$ls180.v:2853$28_Y + attribute \src "ls180.v:2853.8-2853.81" + case 1'1 + assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2854$29_Y + assign $0\main_libresocsim_interface1_converted_interface_we[0:0] \main_libresocsim_libresoc_dbus_we + assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2856$30_Y + assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2857$31_Y + attribute \src "ls180.v:2858.5-2865.8" + switch $or$ls180.v:2858$32_Y + attribute \src "ls180.v:2858.9-2858.97" + case 1'1 + assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2859$33_Y + assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2861.6-2864.9" + switch $eq$ls180.v:2861$34_Y + attribute \src "ls180.v:2861.10-2861.55" + case 1'1 + assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'1 + assign $0\builder_converter1_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2871.4-2873.7" + switch $and$ls180.v:2871$35_Y + attribute \src "ls180.v:2871.8-2871.81" + case 1'1 + assign $0\builder_converter1_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_dbus_ack $0\main_libresocsim_libresoc_dbus_ack[0:0] + update \main_libresocsim_interface1_converted_interface_adr $0\main_libresocsim_interface1_converted_interface_adr[29:0] + update \main_libresocsim_interface1_converted_interface_sel $0\main_libresocsim_interface1_converted_interface_sel[3:0] + update \main_libresocsim_interface1_converted_interface_cyc $0\main_libresocsim_interface1_converted_interface_cyc[0:0] + update \main_libresocsim_interface1_converted_interface_stb $0\main_libresocsim_interface1_converted_interface_stb[0:0] + update \main_libresocsim_interface1_converted_interface_we $0\main_libresocsim_interface1_converted_interface_we[0:0] + update \main_libresocsim_converter1_skip $0\main_libresocsim_converter1_skip[0:0] + update \builder_converter1_next_state $0\builder_converter1_next_state[0:0] + update \main_libresocsim_converter1_counter_converter1_next_value $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] + update \main_libresocsim_converter1_counter_converter1_next_value_ce $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + end + attribute \src "ls180.v:284.5-284.36" + process $proc$ls180.v:284$2858 + assign { } { } + assign $1\main_sdram_master_p0_cke[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] + end + attribute \src "ls180.v:285.5-285.36" + process $proc$ls180.v:285$2859 + assign { } { } + assign $1\main_sdram_master_p0_odt[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] + end + attribute \src "ls180.v:286.5-286.40" + process $proc$ls180.v:286$2860 + assign { } { } + assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] + end + attribute \src "ls180.v:287.5-287.38" + process $proc$ls180.v:287$2861 + assign { } { } + assign $1\main_sdram_master_p0_act_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] + end + attribute \src "ls180.v:2878.1-2888.4" + process $proc$ls180.v:2878$37 + assign { } { } + assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 + attribute \src "ls180.v:2880.2-2887.9" + switch \main_libresocsim_converter2_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [63:32] + case + end + sync always + update \main_libresocsim_interface2_converted_interface_dat_w $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:288.12-288.47" + process $proc$ls180.v:288$2862 + assign { } { } + assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] + end + attribute \src "ls180.v:289.5-289.42" + process $proc$ls180.v:289$2863 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] + end + attribute \src "ls180.v:2890.1-2936.4" + process $proc$ls180.v:2890$38 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 + assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign { } { } + assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 + assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 + assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 + assign $0\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 + assign $0\main_libresocsim_converter2_skip[0:0] 1'0 + assign $0\builder_converter2_next_state[0:0] \builder_converter2_state + attribute \src "ls180.v:2902.2-2935.9" + switch \builder_converter2_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] { \main_libresocsim_libresoc_jtag_wb_adr \main_libresocsim_converter2_counter } + attribute \src "ls180.v:2905.4-2912.11" + switch \main_libresocsim_converter2_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [7:4] + case + end + attribute \src "ls180.v:2913.4-2926.7" + switch $and$ls180.v:2913$39_Y + attribute \src "ls180.v:2913.8-2913.87" + case 1'1 + assign $0\main_libresocsim_converter2_skip[0:0] $eq$ls180.v:2914$40_Y + assign $0\main_libresocsim_interface2_converted_interface_we[0:0] \main_libresocsim_libresoc_jtag_wb_we + assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:2916$41_Y + assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:2917$42_Y + attribute \src "ls180.v:2918.5-2925.8" + switch $or$ls180.v:2918$43_Y + attribute \src "ls180.v:2918.9-2918.97" + case 1'1 + assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] $add$ls180.v:2919$44_Y + assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2921.6-2924.9" + switch $eq$ls180.v:2921$45_Y + attribute \src "ls180.v:2921.10-2921.55" + case 1'1 + assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'1 + assign $0\builder_converter2_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2931.4-2933.7" + switch $and$ls180.v:2931$46_Y + attribute \src "ls180.v:2931.8-2931.87" + case 1'1 + assign $0\builder_converter2_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_jtag_wb_ack $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] + update \main_libresocsim_interface2_converted_interface_adr $0\main_libresocsim_interface2_converted_interface_adr[29:0] + update \main_libresocsim_interface2_converted_interface_sel $0\main_libresocsim_interface2_converted_interface_sel[3:0] + update \main_libresocsim_interface2_converted_interface_cyc $0\main_libresocsim_interface2_converted_interface_cyc[0:0] + update \main_libresocsim_interface2_converted_interface_stb $0\main_libresocsim_interface2_converted_interface_stb[0:0] + update \main_libresocsim_interface2_converted_interface_we $0\main_libresocsim_interface2_converted_interface_we[0:0] + update \main_libresocsim_converter2_skip $0\main_libresocsim_converter2_skip[0:0] + update \builder_converter2_next_state $0\builder_converter2_next_state[0:0] + update \main_libresocsim_converter2_counter_converter2_next_value $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] + update \main_libresocsim_converter2_counter_converter2_next_value_ce $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + end + attribute \src "ls180.v:290.11-290.50" + process $proc$ls180.v:290$2864 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] + end + attribute \src "ls180.v:291.5-291.42" + process $proc$ls180.v:291$2865 + assign { } { } + assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:2939.1-2945.4" + process $proc$ls180.v:2939$47 + assign { } { } + assign { } { } + assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:2941$50_Y + assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:2942$53_Y + assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:2943$56_Y + assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:2944$59_Y + sync always + update \main_libresocsim_we $0\main_libresocsim_we[3:0] + end + attribute \src "ls180.v:2951.1-2956.4" + process $proc$ls180.v:2951$61 + assign { } { } + assign $0\main_libresocsim_zero_clear[0:0] 1'0 + attribute \src "ls180.v:2953.2-2955.5" + switch $and$ls180.v:2953$62_Y + attribute \src "ls180.v:2953.6-2953.90" + case 1'1 + assign $0\main_libresocsim_zero_clear[0:0] 1'1 + case + end + sync always + update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] + end + attribute \src "ls180.v:298.11-298.36" + process $proc$ls180.v:298$2866 + assign { } { } + assign $1\main_sdram_storage[3:0] 4'0001 + sync always + sync init + update \main_sdram_storage $1\main_sdram_storage[3:0] + end + attribute \src "ls180.v:299.5-299.25" + process $proc$ls180.v:299$2867 + assign { } { } + assign $1\main_sdram_re[0:0] 1'0 + sync always + sync init + update \main_sdram_re $1\main_sdram_re[0:0] + end + attribute \src "ls180.v:2995.1-3049.4" + process $proc$ls180.v:2995$64 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0 + assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 + assign $0\main_sdram_master_p0_bank[1:0] 2'00 + assign $0\main_sdram_master_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_master_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_master_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_master_p0_we_n[0:0] 1'1 + assign $0\main_sdram_master_p0_cke[0:0] 1'0 + assign $0\main_sdram_master_p0_odt[0:0] 1'0 + assign $0\main_sdram_master_p0_reset_n[0:0] 1'0 + assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + assign $0\main_sdram_master_p0_act_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 + assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 + assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + attribute \src "ls180.v:3014.2-3048.5" + switch \main_sdram_sel + attribute \src "ls180.v:3014.6-3014.20" + case 1'1 + assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address + assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank + assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_slave_p0_cas_n + assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_slave_p0_cs_n + assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_slave_p0_ras_n + assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_slave_p0_we_n + assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_slave_p0_cke + assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_slave_p0_odt + assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_slave_p0_reset_n + assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_slave_p0_act_n + assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_slave_p0_wrdata + assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_slave_p0_wrdata_en + assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_slave_p0_wrdata_mask + assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en + assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata + assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid + attribute \src "ls180.v:3031.6-3031.10" + case + assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address + assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank + assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_inti_p0_cas_n + assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_inti_p0_cs_n + assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_inti_p0_ras_n + assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_inti_p0_we_n + assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_inti_p0_cke + assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_inti_p0_odt + assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_inti_p0_reset_n + assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_inti_p0_act_n + assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_inti_p0_wrdata + assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_inti_p0_wrdata_en + assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_inti_p0_wrdata_mask + assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_inti_p0_rddata_en + assign $0\main_sdram_inti_p0_rddata[15:0] \main_sdram_master_p0_rddata + assign $0\main_sdram_inti_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid + end + sync always + update \main_sdram_inti_p0_rddata $0\main_sdram_inti_p0_rddata[15:0] + update \main_sdram_inti_p0_rddata_valid $0\main_sdram_inti_p0_rddata_valid[0:0] + update \main_sdram_slave_p0_rddata $0\main_sdram_slave_p0_rddata[15:0] + update \main_sdram_slave_p0_rddata_valid $0\main_sdram_slave_p0_rddata_valid[0:0] + update \main_sdram_master_p0_address $0\main_sdram_master_p0_address[12:0] + update \main_sdram_master_p0_bank $0\main_sdram_master_p0_bank[1:0] + update \main_sdram_master_p0_cas_n $0\main_sdram_master_p0_cas_n[0:0] + update \main_sdram_master_p0_cs_n $0\main_sdram_master_p0_cs_n[0:0] + update \main_sdram_master_p0_ras_n $0\main_sdram_master_p0_ras_n[0:0] + update \main_sdram_master_p0_we_n $0\main_sdram_master_p0_we_n[0:0] + update \main_sdram_master_p0_cke $0\main_sdram_master_p0_cke[0:0] + update \main_sdram_master_p0_odt $0\main_sdram_master_p0_odt[0:0] + update \main_sdram_master_p0_reset_n $0\main_sdram_master_p0_reset_n[0:0] + update \main_sdram_master_p0_act_n $0\main_sdram_master_p0_act_n[0:0] + update \main_sdram_master_p0_wrdata $0\main_sdram_master_p0_wrdata[15:0] + update \main_sdram_master_p0_wrdata_en $0\main_sdram_master_p0_wrdata_en[0:0] + update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] + update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:300.11-300.44" + process $proc$ls180.v:300$2868 + assign { } { } + assign $1\main_sdram_command_storage[5:0] 6'000000 + sync always + sync init + update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] + end + attribute \src "ls180.v:301.5-301.33" + process $proc$ls180.v:301$2869 + assign { } { } + assign $1\main_sdram_command_re[0:0] 1'0 + sync always + sync init + update \main_sdram_command_re $1\main_sdram_command_re[0:0] + end + attribute \src "ls180.v:305.5-305.38" + process $proc$ls180.v:305$2870 + assign { } { } + assign $0\main_sdram_command_issue_w[0:0] 1'0 + sync always + update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] + sync init + end + attribute \src "ls180.v:3053.1-3069.4" + process $proc$ls180.v:3053$65 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 + attribute \src "ls180.v:3058.2-3068.5" + switch \main_sdram_command_issue_re + attribute \src "ls180.v:3058.6-3058.33" + case 1'1 + assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3059$66_Y + assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3060$67_Y + assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3061$68_Y + assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3062$69_Y + attribute \src "ls180.v:3063.6-3063.10" + case + assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 + end + sync always + update \main_sdram_inti_p0_cas_n $0\main_sdram_inti_p0_cas_n[0:0] + update \main_sdram_inti_p0_cs_n $0\main_sdram_inti_p0_cs_n[0:0] + update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] + update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] + end + attribute \src "ls180.v:306.12-306.46" + process $proc$ls180.v:306$2871 + assign { } { } + assign $1\main_sdram_address_storage[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] + end + attribute \src "ls180.v:307.5-307.33" + process $proc$ls180.v:307$2872 + assign { } { } + assign $1\main_sdram_address_re[0:0] 1'0 + sync always + sync init + update \main_sdram_address_re $1\main_sdram_address_re[0:0] + end + attribute \src "ls180.v:308.11-308.45" + process $proc$ls180.v:308$2873 + assign { } { } + assign $1\main_sdram_baddress_storage[1:0] 2'00 + sync always + sync init + update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] + end + attribute \src "ls180.v:309.5-309.34" + process $proc$ls180.v:309$2874 + assign { } { } + assign $1\main_sdram_baddress_re[0:0] 1'0 + sync always + sync init + update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] + end + attribute \src "ls180.v:310.12-310.45" + process $proc$ls180.v:310$2875 + assign { } { } + assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] + end + attribute \src "ls180.v:311.5-311.32" + process $proc$ls180.v:311$2876 + assign { } { } + assign $1\main_sdram_wrdata_re[0:0] 1'0 + sync always + sync init + update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] + end + attribute \src "ls180.v:3112.1-3142.4" + process $proc$ls180.v:3112$78 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_sequencer_start0[0:0] 1'0 + assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdram_cmd_last[0:0] 1'0 + assign $0\builder_refresher_next_state[1:0] \builder_refresher_state + attribute \src "ls180.v:3118.2-3141.9" + switch \builder_refresher_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdram_cmd_valid[0:0] 1'1 + attribute \src "ls180.v:3121.4-3124.7" + switch \main_sdram_cmd_ready + attribute \src "ls180.v:3121.8-3121.28" + case 1'1 + assign $0\main_sdram_sequencer_start0[0:0] 1'1 + assign $0\builder_refresher_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdram_cmd_valid[0:0] 1'1 + attribute \src "ls180.v:3128.4-3132.7" + switch \main_sdram_sequencer_done0 + attribute \src "ls180.v:3128.8-3128.34" + case 1'1 + assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign $0\main_sdram_cmd_last[0:0] 1'1 + assign $0\builder_refresher_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3135.4-3139.7" + switch 1'1 + attribute \src "ls180.v:3135.8-3135.12" + case 1'1 + attribute \src "ls180.v:3136.5-3138.8" + switch \main_sdram_wants_refresh + attribute \src "ls180.v:3136.9-3136.33" + case 1'1 + assign $0\builder_refresher_next_state[1:0] 2'01 + case + end + case + end + end + sync always + update \main_sdram_cmd_valid $0\main_sdram_cmd_valid[0:0] + update \main_sdram_cmd_last $0\main_sdram_cmd_last[0:0] + update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] + update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] + end + attribute \src "ls180.v:312.12-312.37" + process $proc$ls180.v:312$2877 + assign { } { } + assign $1\main_sdram_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_status $1\main_sdram_status[15:0] + end + attribute \src "ls180.v:3157.1-3164.4" + process $proc$ls180.v:3157$82 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3159.2-3163.5" + switch \main_sdram_bankmachine0_row_col_n_addr_sel + attribute \src "ls180.v:3159.6-3159.48" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3161.6-3161.10" + case + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3162$84_Y + end + sync always + update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3168.1-3175.4" + process $proc$ls180.v:3168$91 + assign { } { } + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3170.2-3174.5" + switch $and$ls180.v:3170$92_Y + attribute \src "ls180.v:3170.6-3170.115" + case 1'1 + attribute \src "ls180.v:3171.3-3173.6" + switch $ne$ls180.v:3171$93_Y + attribute \src "ls180.v:3171.7-3171.143" + case 1'1 + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3172$94_Y + case + end + case + end + sync always + update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "ls180.v:3190.1-3197.4" + process $proc$ls180.v:3190$95 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3192.2-3196.5" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3192.6-3192.58" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3193$96_Y + attribute \src "ls180.v:3194.6-3194.10" + case + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:3206.1-3299.4" + process $proc$ls180.v:3206$104 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state + attribute \src "ls180.v:3222.2-3298.9" + switch \builder_bankmachine0_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "ls180.v:3224.4-3232.7" + switch $and$ls180.v:3224$105_Y + attribute \src "ls180.v:3224.8-3224.87" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3226.5-3228.8" + switch \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:3226.9-3226.42" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "ls180.v:3236.4-3238.7" + switch $and$ls180.v:3236$106_Y + attribute \src "ls180.v:3236.8-3236.87" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3242.4-3251.7" + switch \main_sdram_bankmachine0_trccon_ready + attribute \src "ls180.v:3242.8-3242.44" + case 1'1 + assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3247.5-3249.8" + switch \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:3247.9-3247.42" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3254.4-3256.7" + switch \main_sdram_bankmachine0_twtpcon_ready + attribute \src "ls180.v:3254.8-3254.45" + case 1'1 + assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3259.4-3261.7" + switch $not$ls180.v:3259$107_Y + attribute \src "ls180.v:3259.8-3259.46" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine0_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine0_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3270.4-3296.7" + switch \main_sdram_bankmachine0_refresh_req + attribute \src "ls180.v:3270.8-3270.43" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'100 + attribute \src "ls180.v:3272.8-3272.12" + case + attribute \src "ls180.v:3273.5-3295.8" + switch \main_sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "ls180.v:3273.9-3273.56" + case 1'1 + attribute \src "ls180.v:3274.6-3294.9" + switch \main_sdram_bankmachine0_row_opened + attribute \src "ls180.v:3274.10-3274.44" + case 1'1 + attribute \src "ls180.v:3275.7-3291.10" + switch \main_sdram_bankmachine0_row_hit + attribute \src "ls180.v:3275.11-3275.42" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3277.8-3284.11" + switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "ls180.v:3277.12-3277.64" + case 1'1 + assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready + assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3281.12-3281.16" + case + assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready + assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3286.8-3288.11" + switch $and$ls180.v:3286$108_Y + attribute \src "ls180.v:3286.12-3286.88" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3289.11-3289.15" + case + assign $0\builder_bankmachine0_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3292.10-3292.14" + case + assign $0\builder_bankmachine0_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine0_req_wdata_ready $0\main_sdram_bankmachine0_req_wdata_ready[0:0] + update \main_sdram_bankmachine0_req_rdata_valid $0\main_sdram_bankmachine0_req_rdata_valid[0:0] + update \main_sdram_bankmachine0_refresh_gnt $0\main_sdram_bankmachine0_refresh_gnt[0:0] + update \main_sdram_bankmachine0_cmd_valid $0\main_sdram_bankmachine0_cmd_valid[0:0] + update \main_sdram_bankmachine0_cmd_payload_cas $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] + update \main_sdram_bankmachine0_cmd_payload_ras $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] + update \main_sdram_bankmachine0_cmd_payload_we $0\main_sdram_bankmachine0_cmd_payload_we[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_cmd $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_read $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_write $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine0_row_open $0\main_sdram_bankmachine0_row_open[0:0] + update \main_sdram_bankmachine0_row_close $0\main_sdram_bankmachine0_row_close[0:0] + update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] + end + attribute \src "ls180.v:3314.1-3321.4" + process $proc$ls180.v:3314$112 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3316.2-3320.5" + switch \main_sdram_bankmachine1_row_col_n_addr_sel + attribute \src "ls180.v:3316.6-3316.48" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3318.6-3318.10" + case + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3319$114_Y + end + sync always + update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3325.1-3332.4" + process $proc$ls180.v:3325$121 + assign { } { } + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3327.2-3331.5" + switch $and$ls180.v:3327$122_Y + attribute \src "ls180.v:3327.6-3327.115" + case 1'1 + attribute \src "ls180.v:3328.3-3330.6" + switch $ne$ls180.v:3328$123_Y + attribute \src "ls180.v:3328.7-3328.143" + case 1'1 + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3329$124_Y + case + end + case + end + sync always + update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "ls180.v:3347.1-3354.4" + process $proc$ls180.v:3347$125 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3349.2-3353.5" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3349.6-3349.58" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3350$126_Y + attribute \src "ls180.v:3351.6-3351.10" + case + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:3363.1-3456.4" + process $proc$ls180.v:3363$134 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state + attribute \src "ls180.v:3379.2-3455.9" + switch \builder_bankmachine1_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "ls180.v:3381.4-3389.7" + switch $and$ls180.v:3381$135_Y + attribute \src "ls180.v:3381.8-3381.87" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3383.5-3385.8" + switch \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:3383.9-3383.42" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "ls180.v:3393.4-3395.7" + switch $and$ls180.v:3393$136_Y + attribute \src "ls180.v:3393.8-3393.87" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3399.4-3408.7" + switch \main_sdram_bankmachine1_trccon_ready + attribute \src "ls180.v:3399.8-3399.44" + case 1'1 + assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3404.5-3406.8" + switch \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:3404.9-3404.42" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3411.4-3413.7" + switch \main_sdram_bankmachine1_twtpcon_ready + attribute \src "ls180.v:3411.8-3411.45" + case 1'1 + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3416.4-3418.7" + switch $not$ls180.v:3416$137_Y + attribute \src "ls180.v:3416.8-3416.46" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine1_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine1_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3427.4-3453.7" + switch \main_sdram_bankmachine1_refresh_req + attribute \src "ls180.v:3427.8-3427.43" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'100 + attribute \src "ls180.v:3429.8-3429.12" + case + attribute \src "ls180.v:3430.5-3452.8" + switch \main_sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "ls180.v:3430.9-3430.56" + case 1'1 + attribute \src "ls180.v:3431.6-3451.9" + switch \main_sdram_bankmachine1_row_opened + attribute \src "ls180.v:3431.10-3431.44" + case 1'1 + attribute \src "ls180.v:3432.7-3448.10" + switch \main_sdram_bankmachine1_row_hit + attribute \src "ls180.v:3432.11-3432.42" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3434.8-3441.11" + switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "ls180.v:3434.12-3434.64" + case 1'1 + assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready + assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3438.12-3438.16" + case + assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready + assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3443.8-3445.11" + switch $and$ls180.v:3443$138_Y + attribute \src "ls180.v:3443.12-3443.88" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3446.11-3446.15" + case + assign $0\builder_bankmachine1_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3449.10-3449.14" + case + assign $0\builder_bankmachine1_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine1_req_wdata_ready $0\main_sdram_bankmachine1_req_wdata_ready[0:0] + update \main_sdram_bankmachine1_req_rdata_valid $0\main_sdram_bankmachine1_req_rdata_valid[0:0] + update \main_sdram_bankmachine1_refresh_gnt $0\main_sdram_bankmachine1_refresh_gnt[0:0] + update \main_sdram_bankmachine1_cmd_valid $0\main_sdram_bankmachine1_cmd_valid[0:0] + update \main_sdram_bankmachine1_cmd_payload_cas $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] + update \main_sdram_bankmachine1_cmd_payload_ras $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] + update \main_sdram_bankmachine1_cmd_payload_we $0\main_sdram_bankmachine1_cmd_payload_we[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_cmd $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_read $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_write $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine1_row_open $0\main_sdram_bankmachine1_row_open[0:0] + update \main_sdram_bankmachine1_row_close $0\main_sdram_bankmachine1_row_close[0:0] + update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] + end + attribute \src "ls180.v:342.12-342.46" + process $proc$ls180.v:342$2878 + assign { } { } + assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] + end + attribute \src "ls180.v:343.11-343.47" + process $proc$ls180.v:343$2879 + assign { } { } + assign $1\main_sdram_interface_wdata_we[1:0] 2'00 + sync always + sync init + update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] + end + attribute \src "ls180.v:345.12-345.45" + process $proc$ls180.v:345$2880 + assign { } { } + assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] + end + attribute \src "ls180.v:346.11-346.40" + process $proc$ls180.v:346$2881 + assign { } { } + assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] + end + attribute \src "ls180.v:347.5-347.35" + process $proc$ls180.v:347$2882 + assign { } { } + assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] + end + attribute \src "ls180.v:3471.1-3478.4" + process $proc$ls180.v:3471$142 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3473.2-3477.5" + switch \main_sdram_bankmachine2_row_col_n_addr_sel + attribute \src "ls180.v:3473.6-3473.48" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3475.6-3475.10" + case + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3476$144_Y + end + sync always + update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] + end + attribute \src "ls180.v:348.5-348.34" + process $proc$ls180.v:348$2883 + assign { } { } + assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] + end + attribute \src "ls180.v:3482.1-3489.4" + process $proc$ls180.v:3482$151 + assign { } { } + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3484.2-3488.5" + switch $and$ls180.v:3484$152_Y + attribute \src "ls180.v:3484.6-3484.115" + case 1'1 + attribute \src "ls180.v:3485.3-3487.6" + switch $ne$ls180.v:3485$153_Y + attribute \src "ls180.v:3485.7-3485.143" + case 1'1 + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3486$154_Y + case + end + case + end + sync always + update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] + end + attribute \src "ls180.v:349.5-349.35" + process $proc$ls180.v:349$2884 + assign { } { } + assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] + end + attribute \src "ls180.v:350.5-350.34" + process $proc$ls180.v:350$2885 + assign { } { } + assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] + end + attribute \src "ls180.v:3504.1-3511.4" + process $proc$ls180.v:3504$155 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3506.2-3510.5" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3506.6-3506.58" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3507$156_Y + attribute \src "ls180.v:3508.6-3508.10" + case + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:3520.1-3613.4" + process $proc$ls180.v:3520$164 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state + attribute \src "ls180.v:3536.2-3612.9" + switch \builder_bankmachine2_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "ls180.v:3538.4-3546.7" + switch $and$ls180.v:3538$165_Y + attribute \src "ls180.v:3538.8-3538.87" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3540.5-3542.8" + switch \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:3540.9-3540.42" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "ls180.v:3550.4-3552.7" + switch $and$ls180.v:3550$166_Y + attribute \src "ls180.v:3550.8-3550.87" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3556.4-3565.7" + switch \main_sdram_bankmachine2_trccon_ready + attribute \src "ls180.v:3556.8-3556.44" + case 1'1 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3561.5-3563.8" + switch \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:3561.9-3561.42" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3568.4-3570.7" + switch \main_sdram_bankmachine2_twtpcon_ready + attribute \src "ls180.v:3568.8-3568.45" + case 1'1 + assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3573.4-3575.7" + switch $not$ls180.v:3573$167_Y + attribute \src "ls180.v:3573.8-3573.46" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine2_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine2_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3584.4-3610.7" + switch \main_sdram_bankmachine2_refresh_req + attribute \src "ls180.v:3584.8-3584.43" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'100 + attribute \src "ls180.v:3586.8-3586.12" + case + attribute \src "ls180.v:3587.5-3609.8" + switch \main_sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "ls180.v:3587.9-3587.56" + case 1'1 + attribute \src "ls180.v:3588.6-3608.9" + switch \main_sdram_bankmachine2_row_opened + attribute \src "ls180.v:3588.10-3588.44" + case 1'1 + attribute \src "ls180.v:3589.7-3605.10" + switch \main_sdram_bankmachine2_row_hit + attribute \src "ls180.v:3589.11-3589.42" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3591.8-3598.11" + switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "ls180.v:3591.12-3591.64" + case 1'1 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3595.12-3595.16" + case + assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3600.8-3602.11" + switch $and$ls180.v:3600$168_Y + attribute \src "ls180.v:3600.12-3600.88" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3603.11-3603.15" + case + assign $0\builder_bankmachine2_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3606.10-3606.14" + case + assign $0\builder_bankmachine2_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine2_req_wdata_ready $0\main_sdram_bankmachine2_req_wdata_ready[0:0] + update \main_sdram_bankmachine2_req_rdata_valid $0\main_sdram_bankmachine2_req_rdata_valid[0:0] + update \main_sdram_bankmachine2_refresh_gnt $0\main_sdram_bankmachine2_refresh_gnt[0:0] + update \main_sdram_bankmachine2_cmd_valid $0\main_sdram_bankmachine2_cmd_valid[0:0] + update \main_sdram_bankmachine2_cmd_payload_cas $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] + update \main_sdram_bankmachine2_cmd_payload_ras $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] + update \main_sdram_bankmachine2_cmd_payload_we $0\main_sdram_bankmachine2_cmd_payload_we[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_cmd $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_read $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_write $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine2_row_open $0\main_sdram_bankmachine2_row_open[0:0] + update \main_sdram_bankmachine2_row_close $0\main_sdram_bankmachine2_row_close[0:0] + update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] + end + attribute \src "ls180.v:354.5-354.35" + process $proc$ls180.v:354$2886 + assign { } { } + assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 + sync always + update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] + sync init + end + attribute \src "ls180.v:356.5-356.39" + process $proc$ls180.v:356$2887 + assign { } { } + assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] + end + attribute \src "ls180.v:358.5-358.39" + process $proc$ls180.v:358$2888 + assign { } { } + assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] + end + attribute \src "ls180.v:361.5-361.32" + process $proc$ls180.v:361$2889 + assign { } { } + assign $1\main_sdram_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] + end + attribute \src "ls180.v:362.5-362.32" + process $proc$ls180.v:362$2890 + assign { } { } + assign $1\main_sdram_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] + end + attribute \src "ls180.v:3628.1-3635.4" + process $proc$ls180.v:3628$172 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3630.2-3634.5" + switch \main_sdram_bankmachine3_row_col_n_addr_sel + attribute \src "ls180.v:3630.6-3630.48" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3632.6-3632.10" + case + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3633$174_Y + end + sync always + update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] + end + attribute \src "ls180.v:363.5-363.31" + process $proc$ls180.v:363$2891 + assign { } { } + assign $1\main_sdram_cmd_last[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] + end + attribute \src "ls180.v:3639.1-3646.4" + process $proc$ls180.v:3639$181 + assign { } { } + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3641.2-3645.5" + switch $and$ls180.v:3641$182_Y + attribute \src "ls180.v:3641.6-3641.115" + case 1'1 + attribute \src "ls180.v:3642.3-3644.6" + switch $ne$ls180.v:3642$183_Y + attribute \src "ls180.v:3642.7-3642.143" + case 1'1 + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3643$184_Y + case + end + case + end + sync always + update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "ls180.v:364.12-364.44" + process $proc$ls180.v:364$2892 + assign { } { } + assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] + end + attribute \src "ls180.v:365.11-365.43" + process $proc$ls180.v:365$2893 + assign { } { } + assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 + sync always + sync init + update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] + end + attribute \src "ls180.v:366.5-366.38" + process $proc$ls180.v:366$2894 + assign { } { } + assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:3661.1-3668.4" + process $proc$ls180.v:3661$185 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3663.2-3667.5" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3663.6-3663.58" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3664$186_Y + attribute \src "ls180.v:3665.6-3665.10" + case + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:367.5-367.38" + process $proc$ls180.v:367$2895 + assign { } { } + assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:3677.1-3770.4" + process $proc$ls180.v:3677$194 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state + attribute \src "ls180.v:3693.2-3769.9" + switch \builder_bankmachine3_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "ls180.v:3695.4-3703.7" + switch $and$ls180.v:3695$195_Y + attribute \src "ls180.v:3695.8-3695.87" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3697.5-3699.8" + switch \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:3697.9-3697.42" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "ls180.v:3707.4-3709.7" + switch $and$ls180.v:3707$196_Y + attribute \src "ls180.v:3707.8-3707.87" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3713.4-3722.7" + switch \main_sdram_bankmachine3_trccon_ready + attribute \src "ls180.v:3713.8-3713.44" + case 1'1 + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3718.5-3720.8" + switch \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:3718.9-3718.42" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3725.4-3727.7" + switch \main_sdram_bankmachine3_twtpcon_ready + attribute \src "ls180.v:3725.8-3725.45" + case 1'1 + assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3730.4-3732.7" + switch $not$ls180.v:3730$197_Y + attribute \src "ls180.v:3730.8-3730.46" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine3_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine3_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3741.4-3767.7" + switch \main_sdram_bankmachine3_refresh_req + attribute \src "ls180.v:3741.8-3741.43" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'100 + attribute \src "ls180.v:3743.8-3743.12" + case + attribute \src "ls180.v:3744.5-3766.8" + switch \main_sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "ls180.v:3744.9-3744.56" + case 1'1 + attribute \src "ls180.v:3745.6-3765.9" + switch \main_sdram_bankmachine3_row_opened + attribute \src "ls180.v:3745.10-3745.44" + case 1'1 + attribute \src "ls180.v:3746.7-3762.10" + switch \main_sdram_bankmachine3_row_hit + attribute \src "ls180.v:3746.11-3746.42" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3748.8-3755.11" + switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "ls180.v:3748.12-3748.64" + case 1'1 + assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready + assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3752.12-3752.16" + case + assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready + assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3757.8-3759.11" + switch $and$ls180.v:3757$198_Y + attribute \src "ls180.v:3757.12-3757.88" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3760.11-3760.15" + case + assign $0\builder_bankmachine3_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3763.10-3763.14" + case + assign $0\builder_bankmachine3_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine3_req_wdata_ready $0\main_sdram_bankmachine3_req_wdata_ready[0:0] + update \main_sdram_bankmachine3_req_rdata_valid $0\main_sdram_bankmachine3_req_rdata_valid[0:0] + update \main_sdram_bankmachine3_refresh_gnt $0\main_sdram_bankmachine3_refresh_gnt[0:0] + update \main_sdram_bankmachine3_cmd_valid $0\main_sdram_bankmachine3_cmd_valid[0:0] + update \main_sdram_bankmachine3_cmd_payload_cas $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] + update \main_sdram_bankmachine3_cmd_payload_ras $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] + update \main_sdram_bankmachine3_cmd_payload_we $0\main_sdram_bankmachine3_cmd_payload_we[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_cmd $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_read $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_write $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine3_row_open $0\main_sdram_bankmachine3_row_open[0:0] + update \main_sdram_bankmachine3_row_close $0\main_sdram_bankmachine3_row_close[0:0] + update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] + end + attribute \src "ls180.v:368.5-368.37" + process $proc$ls180.v:368$2896 + assign { } { } + assign $1\main_sdram_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] + end + attribute \src "ls180.v:369.5-369.42" + process $proc$ls180.v:369$2897 + assign { } { } + assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] + sync init + end + attribute \src "ls180.v:370.5-370.43" + process $proc$ls180.v:370$2898 + assign { } { } + assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] + sync init + end + attribute \src "ls180.v:376.11-376.44" + process $proc$ls180.v:376$2899 + assign { } { } + assign $1\main_sdram_timer_count1[9:0] 10'1100001101 + sync always + sync init + update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] + end + attribute \src "ls180.v:378.5-378.38" + process $proc$ls180.v:378$2900 + assign { } { } + assign $1\main_sdram_postponer_req_o[0:0] 1'0 + sync always + sync init + update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] + end + attribute \src "ls180.v:379.5-379.38" + process $proc$ls180.v:379$2901 + assign { } { } + assign $1\main_sdram_postponer_count[0:0] 1'0 + sync always + sync init + update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] + end + attribute \src "ls180.v:3790.1-3796.4" + process $proc$ls180.v:3790$237 + assign { } { } + assign { } { } + assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3792$250_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3793$263_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3794$276_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3795$289_Y + sync always + update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] + end + attribute \src "ls180.v:380.5-380.39" + process $proc$ls180.v:380$2902 + assign { } { } + assign $1\main_sdram_sequencer_start0[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] + end + attribute \src "ls180.v:3804.1-3809.4" + process $proc$ls180.v:3804$290 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + attribute \src "ls180.v:3806.2-3808.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:3806.6-3806.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:3810.1-3815.4" + process $proc$ls180.v:3810$291 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + attribute \src "ls180.v:3812.2-3814.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:3812.6-3812.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:3816.1-3821.4" + process $proc$ls180.v:3816$292 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + attribute \src "ls180.v:3818.2-3820.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:3818.6-3818.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] + end + attribute \src "ls180.v:3823.1-3829.4" + process $proc$ls180.v:3823$295 + assign { } { } + assign { } { } + assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3825$308_Y + assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3826$321_Y + assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3827$334_Y + assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3828$347_Y + sync always + update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] + end + attribute \src "ls180.v:383.5-383.38" + process $proc$ls180.v:383$2903 + assign { } { } + assign $1\main_sdram_sequencer_done1[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] + end + attribute \src "ls180.v:3837.1-3842.4" + process $proc$ls180.v:3837$348 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + attribute \src "ls180.v:3839.2-3841.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:3839.6-3839.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:384.11-384.46" + process $proc$ls180.v:384$2904 + assign { } { } + assign $1\main_sdram_sequencer_counter[3:0] 4'0000 + sync always + sync init + update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] + end + attribute \src "ls180.v:3843.1-3848.4" + process $proc$ls180.v:3843$349 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 + attribute \src "ls180.v:3845.2-3847.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:3845.6-3845.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:3849.1-3854.4" + process $proc$ls180.v:3849$350 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 + attribute \src "ls180.v:3851.2-3853.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:3851.6-3851.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] + end + attribute \src "ls180.v:385.5-385.38" + process $proc$ls180.v:385$2905 + assign { } { } + assign $1\main_sdram_sequencer_count[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] + end + attribute \src "ls180.v:3855.1-3863.4" + process $proc$ls180.v:3855$351 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3857.2-3859.5" + switch $and$ls180.v:3857$354_Y + attribute \src "ls180.v:3857.6-3857.115" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3860.2-3862.5" + switch $and$ls180.v:3860$357_Y + attribute \src "ls180.v:3860.6-3860.115" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:3864.1-3872.4" + process $proc$ls180.v:3864$358 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3866.2-3868.5" + switch $and$ls180.v:3866$361_Y + attribute \src "ls180.v:3866.6-3866.115" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3869.2-3871.5" + switch $and$ls180.v:3869$364_Y + attribute \src "ls180.v:3869.6-3869.115" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] + end + attribute \src "ls180.v:3873.1-3881.4" + process $proc$ls180.v:3873$365 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3875.2-3877.5" + switch $and$ls180.v:3875$368_Y + attribute \src "ls180.v:3875.6-3875.115" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3878.2-3880.5" + switch $and$ls180.v:3878$371_Y + attribute \src "ls180.v:3878.6-3878.115" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] + end + attribute \src "ls180.v:3882.1-3890.4" + process $proc$ls180.v:3882$372 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3884.2-3886.5" + switch $and$ls180.v:3884$375_Y + attribute \src "ls180.v:3884.6-3884.115" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3887.2-3889.5" + switch $and$ls180.v:3887$378_Y + attribute \src "ls180.v:3887.6-3887.115" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] + end + attribute \src "ls180.v:3895.1-3967.4" + process $proc$ls180.v:3895$381 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 + assign $0\main_sdram_en0[0:0] 1'0 + assign { } { } + assign $0\main_sdram_en1[0:0] 1'0 + assign $0\main_sdram_choose_req_want_reads[0:0] 1'0 + assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 + assign $0\main_sdram_cmd_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdram_steerer_sel[1:0] 2'00 + assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed + assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state + attribute \src "ls180.v:3907.2-3966.9" + switch \builder_multiplexer_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_en1[0:0] 1'1 + assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 + assign $0\main_sdram_steerer_sel[1:0] 2'10 + attribute \src "ls180.v:3911.4-3917.7" + switch 1'1 + attribute \src "ls180.v:3911.8-3911.12" + case 1'1 + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3912$388_Y + case + end + attribute \src "ls180.v:3919.4-3923.7" + switch \main_sdram_read_available + attribute \src "ls180.v:3919.8-3919.33" + case 1'1 + attribute \src "ls180.v:3920.5-3922.8" + switch $or$ls180.v:3920$390_Y + attribute \src "ls180.v:3920.9-3920.63" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'011 + case + end + case + end + attribute \src "ls180.v:3924.4-3926.7" + switch \main_sdram_go_to_refresh + attribute \src "ls180.v:3924.8-3924.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_steerer_sel[1:0] 2'11 + assign $0\main_sdram_cmd_ready[0:0] 1'1 + attribute \src "ls180.v:3931.4-3933.7" + switch \main_sdram_cmd_last + attribute \src "ls180.v:3931.8-3931.27" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3936.4-3938.7" + switch \main_sdram_twtrcon_ready + attribute \src "ls180.v:3936.8-3936.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_multiplexer_next_state[2:0] 3'101 + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_multiplexer_next_state[2:0] 3'001 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdram_en0[0:0] 1'1 + assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 + assign $0\main_sdram_steerer_sel[1:0] 2'10 + attribute \src "ls180.v:3949.4-3955.7" + switch 1'1 + attribute \src "ls180.v:3949.8-3949.12" + case 1'1 + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3950$397_Y + case + end + attribute \src "ls180.v:3957.4-3961.7" + switch \main_sdram_write_available + attribute \src "ls180.v:3957.8-3957.34" + case 1'1 + attribute \src "ls180.v:3958.5-3960.8" + switch $or$ls180.v:3958$399_Y + attribute \src "ls180.v:3958.9-3958.62" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'100 + case + end + case + end + attribute \src "ls180.v:3962.4-3964.7" + switch \main_sdram_go_to_refresh + attribute \src "ls180.v:3962.8-3962.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'010 + case + end + end + sync always + update \main_sdram_cmd_ready $0\main_sdram_cmd_ready[0:0] + update \main_sdram_choose_req_want_reads $0\main_sdram_choose_req_want_reads[0:0] + update \main_sdram_choose_req_want_writes $0\main_sdram_choose_req_want_writes[0:0] + update \main_sdram_choose_req_want_activates $0\main_sdram_choose_req_want_activates[0:0] + update \main_sdram_choose_req_cmd_ready $0\main_sdram_choose_req_cmd_ready[0:0] + update \main_sdram_steerer_sel $0\main_sdram_steerer_sel[1:0] + update \main_sdram_en0 $0\main_sdram_en0[0:0] + update \main_sdram_en1 $0\main_sdram_en1[0:0] + update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] + end + attribute \src "ls180.v:391.5-391.51" + process $proc$ls180.v:391$2906 + assign { } { } + assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + end + attribute \src "ls180.v:392.5-392.51" + process $proc$ls180.v:392$2907 + assign { } { } + assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + end + attribute \src "ls180.v:394.5-394.47" + process $proc$ls180.v:394$2908 + assign { } { } + assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] + end + attribute \src "ls180.v:395.5-395.45" + process $proc$ls180.v:395$2909 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] + end + attribute \src "ls180.v:396.5-396.45" + process $proc$ls180.v:396$2910 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:397.12-397.57" + process $proc$ls180.v:397$2911 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "ls180.v:399.5-399.51" + process $proc$ls180.v:399$2912 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:3991.1-4004.4" + process $proc$ls180.v:3991$528 + assign { } { } + assign { } { } + assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\main_sdram_interface_wdata_we[1:0] 2'00 + attribute \src "ls180.v:3994.2-4003.9" + switch \builder_new_master_wdata_ready + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdram_interface_wdata[15:0] \main_port_wdata_payload_data + assign $0\main_sdram_interface_wdata_we[1:0] \main_port_wdata_payload_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\main_sdram_interface_wdata_we[1:0] 2'00 + end + sync always + update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] + update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] + end + attribute \src "ls180.v:400.5-400.51" + process $proc$ls180.v:400$2913 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:401.5-401.50" + process $proc$ls180.v:401$2914 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + end + attribute \src "ls180.v:4011.1-4021.4" + process $proc$ls180.v:4011$530 + assign { } { } + assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 + attribute \src "ls180.v:4013.2-4020.9" + switch \main_converter_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [15:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [31:16] + case + end + sync always + update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] + end + attribute \src "ls180.v:402.5-402.54" + process $proc$ls180.v:402$2915 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:4023.1-4069.4" + process $proc$ls180.v:4023$531 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_converter_skip[0:0] 1'0 + assign $0\main_wb_sdram_ack[0:0] 1'0 + assign { } { } + assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_converter_counter_converter_next_value[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0 + assign $0\main_litedram_wb_sel[1:0] 2'00 + assign $0\main_litedram_wb_cyc[0:0] 1'0 + assign $0\main_litedram_wb_stb[0:0] 1'0 + assign $0\main_litedram_wb_we[0:0] 1'0 + assign $0\builder_converter_next_state[0:0] \builder_converter_state + attribute \src "ls180.v:4035.2-4068.9" + switch \builder_converter_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } + attribute \src "ls180.v:4038.4-4045.11" + switch \main_converter_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [1:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] + case + end + attribute \src "ls180.v:4046.4-4059.7" + switch $and$ls180.v:4046$532_Y + attribute \src "ls180.v:4046.8-4046.47" + case 1'1 + assign $0\main_converter_skip[0:0] $eq$ls180.v:4047$533_Y + assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we + assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4049$534_Y + assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4050$535_Y + attribute \src "ls180.v:4051.5-4058.8" + switch $or$ls180.v:4051$536_Y + attribute \src "ls180.v:4051.9-4051.53" + case 1'1 + assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4052$537_Y + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4054.6-4057.9" + switch $eq$ls180.v:4054$538_Y + attribute \src "ls180.v:4054.10-4054.42" + case 1'1 + assign $0\main_wb_sdram_ack[0:0] 1'1 + assign $0\builder_converter_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_converter_counter_converter_next_value[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4064.4-4066.7" + switch $and$ls180.v:4064$539_Y + attribute \src "ls180.v:4064.8-4064.47" + case 1'1 + assign $0\builder_converter_next_state[0:0] 1'1 + case + end + end + sync always + update \main_wb_sdram_ack $0\main_wb_sdram_ack[0:0] + update \main_litedram_wb_adr $0\main_litedram_wb_adr[29:0] + update \main_litedram_wb_sel $0\main_litedram_wb_sel[1:0] + update \main_litedram_wb_cyc $0\main_litedram_wb_cyc[0:0] + update \main_litedram_wb_stb $0\main_litedram_wb_stb[0:0] + update \main_litedram_wb_we $0\main_litedram_wb_we[0:0] + update \main_converter_skip $0\main_converter_skip[0:0] + update \builder_converter_next_state $0\builder_converter_next_state[0:0] + update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] + update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] + end + attribute \src "ls180.v:403.5-403.55" + process $proc$ls180.v:403$2916 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:404.5-404.56" + process $proc$ls180.v:404$2917 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:405.5-405.50" + process $proc$ls180.v:405$2918 + assign { } { } + assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "ls180.v:408.5-408.67" + process $proc$ls180.v:408$2919 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:409.5-409.66" + process $proc$ls180.v:409$2920 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:4114.1-4119.4" + process $proc$ls180.v:4114$571 + assign { } { } + assign $0\main_uart_tx_clear[0:0] 1'0 + attribute \src "ls180.v:4116.2-4118.5" + switch $and$ls180.v:4116$572_Y + attribute \src "ls180.v:4116.6-4116.79" + case 1'1 + assign $0\main_uart_tx_clear[0:0] 1'1 + case + end + sync always + update \main_uart_tx_clear $0\main_uart_tx_clear[0:0] + end + attribute \src "ls180.v:4120.1-4124.4" + process $proc$ls180.v:4120$573 + assign { } { } + assign { } { } + assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status + assign $0\main_uart_eventmanager_status_w[1:0] [1] \main_uart_rx_status + sync always + update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0] + end + attribute \src "ls180.v:4125.1-4130.4" + process $proc$ls180.v:4125$574 + assign { } { } + assign $0\main_uart_rx_clear[0:0] 1'0 + attribute \src "ls180.v:4127.2-4129.5" + switch $and$ls180.v:4127$575_Y + attribute \src "ls180.v:4127.6-4127.79" + case 1'1 + assign $0\main_uart_rx_clear[0:0] 1'1 + case + end + sync always + update \main_uart_rx_clear $0\main_uart_rx_clear[0:0] + end + attribute \src "ls180.v:4131.1-4135.4" + process $proc$ls180.v:4131$576 + assign { } { } + assign { } { } + assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending + assign $0\main_uart_eventmanager_pending_w[1:0] [1] \main_uart_rx_pending + sync always + update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0] + end + attribute \src "ls180.v:4153.1-4160.4" + process $proc$ls180.v:4153$584 + assign { } { } + assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "ls180.v:4155.2-4159.5" + switch \main_uart_tx_fifo_replace + attribute \src "ls180.v:4155.6-4155.31" + case 1'1 + assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4156$585_Y + attribute \src "ls180.v:4157.6-4157.10" + case + assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce + end + sync always + update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:4183.1-4190.4" + process $proc$ls180.v:4183$595 + assign { } { } + assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "ls180.v:4185.2-4189.5" + switch \main_uart_rx_fifo_replace + attribute \src "ls180.v:4185.6-4185.31" + case 1'1 + assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4186$596_Y + attribute \src "ls180.v:4187.6-4187.10" + case + assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce + end + sync always + update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:4213.1-4261.4" + process $proc$ls180.v:4213$606 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_spi_master_done0[0:0] 1'0 + assign $0\main_spi_master_miso_latch[0:0] 1'0 + assign $0\main_spi_master_irq[0:0] 1'0 + assign { } { } + assign $0\main_spi_master_count_spimaster0_next_value[2:0] 3'000 + assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'0 + assign $0\main_spi_master_clk_enable[0:0] 1'0 + assign $0\main_spi_master_cs_enable[0:0] 1'0 + assign $0\main_spi_master_mosi_latch[0:0] 1'0 + assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state + attribute \src "ls180.v:4224.2-4260.9" + switch \builder_spimaster0_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_spi_master_count_spimaster0_next_value[2:0] 3'000 + assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4228.4-4231.7" + switch \main_spi_master_clk_fall + attribute \src "ls180.v:4228.8-4228.32" + case 1'1 + assign $0\main_spi_master_cs_enable[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_spi_master_clk_enable[0:0] 1'1 + assign $0\main_spi_master_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4236.4-4242.7" + switch \main_spi_master_clk_fall + attribute \src "ls180.v:4236.8-4236.32" + case 1'1 + assign $0\main_spi_master_count_spimaster0_next_value[2:0] $add$ls180.v:4237$607_Y + assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4239.5-4241.8" + switch $eq$ls180.v:4239$609_Y + attribute \src "ls180.v:4239.9-4239.68" + case 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'11 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\main_spi_master_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4246.4-4250.7" + switch \main_spi_master_clk_rise + attribute \src "ls180.v:4246.8-4246.32" + case 1'1 + assign $0\main_spi_master_miso_latch[0:0] 1'1 + assign $0\main_spi_master_irq[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_spi_master_done0[0:0] 1'1 + attribute \src "ls180.v:4254.4-4258.7" + switch \main_spi_master_start0 + attribute \src "ls180.v:4254.8-4254.30" + case 1'1 + assign $0\main_spi_master_done0[0:0] 1'0 + assign $0\main_spi_master_mosi_latch[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'01 + case + end + end + sync always + update \main_spi_master_done0 $0\main_spi_master_done0[0:0] + update \main_spi_master_irq $0\main_spi_master_irq[0:0] + update \main_spi_master_clk_enable $0\main_spi_master_clk_enable[0:0] + update \main_spi_master_cs_enable $0\main_spi_master_cs_enable[0:0] + update \main_spi_master_mosi_latch $0\main_spi_master_mosi_latch[0:0] + update \main_spi_master_miso_latch $0\main_spi_master_miso_latch[0:0] + update \builder_spimaster0_next_state $0\builder_spimaster0_next_state[1:0] + update \main_spi_master_count_spimaster0_next_value $0\main_spi_master_count_spimaster0_next_value[2:0] + update \main_spi_master_count_spimaster0_next_value_ce $0\main_spi_master_count_spimaster0_next_value_ce[0:0] + end + attribute \src "ls180.v:424.11-424.68" + process $proc$ls180.v:424$2921 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:425.5-425.64" + process $proc$ls180.v:425$2922 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:426.11-426.70" + process $proc$ls180.v:426$2923 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:427.11-427.70" + process $proc$ls180.v:427$2924 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:428.11-428.73" + process $proc$ls180.v:428$2925 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:4293.1-4321.4" + process $proc$ls180.v:4293$631 + assign { } { } + assign $0\main_sdphy_clocker_clk1[0:0] 1'0 + attribute \src "ls180.v:4295.2-4320.9" + switch \main_sdphy_clocker_storage + attribute \src "ls180.v:0.0-0.0" + case 9'000000100 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [1] + attribute \src "ls180.v:0.0-0.0" + case 9'000001000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [2] + attribute \src "ls180.v:0.0-0.0" + case 9'000010000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [3] + attribute \src "ls180.v:0.0-0.0" + case 9'000100000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [4] + attribute \src "ls180.v:0.0-0.0" + case 9'001000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [5] + attribute \src "ls180.v:0.0-0.0" + case 9'010000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [6] + attribute \src "ls180.v:0.0-0.0" + case 9'100000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [7] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [0] + end + sync always + update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] + end + attribute \src "ls180.v:4323.1-4356.4" + process $proc$ls180.v:4323$634 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 + assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:4333.2-4355.9" + switch \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111 + attribute \src "ls180.v:4340.4-4346.7" + switch \main_sdphy_init_pads_out_ready + attribute \src "ls180.v:4340.8-4340.38" + case 1'1 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4341$635_Y + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4343.5-4345.8" + switch $eq$ls180.v:4343$636_Y + attribute \src "ls180.v:4343.9-4343.41" + case 1'1 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4351.4-4353.7" + switch \main_sdphy_init_initialize_re + attribute \src "ls180.v:4351.8-4351.37" + case 1'1 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 + case + end + end + sync always + update \main_sdphy_init_pads_out_payload_clk $0\main_sdphy_init_pads_out_payload_clk[0:0] + update \main_sdphy_init_pads_out_payload_cmd_o $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] + update \main_sdphy_init_pads_out_payload_cmd_oe $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_init_pads_out_payload_data_o $0\main_sdphy_init_pads_out_payload_data_o[3:0] + update \main_sdphy_init_pads_out_payload_data_oe $0\main_sdphy_init_pads_out_payload_data_oe[0:0] + update \builder_sdphy_sdphyinit_next_state $0\builder_sdphy_sdphyinit_next_state[0:0] + update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + end + attribute \src "ls180.v:4357.1-4433.4" + process $proc$ls180.v:4357$637 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_cmdw_done[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:4367.2-4432.9" + switch \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 + attribute \src "ls180.v:4371.4-4396.11" + switch \main_sdphy_cmdw_count + attribute \src "ls180.v:0.0-0.0" + case 8'00000000 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [7] + attribute \src "ls180.v:0.0-0.0" + case 8'00000001 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [6] + attribute \src "ls180.v:0.0-0.0" + case 8'00000010 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [5] + attribute \src "ls180.v:0.0-0.0" + case 8'00000011 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [4] + attribute \src "ls180.v:0.0-0.0" + case 8'00000100 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [3] + attribute \src "ls180.v:0.0-0.0" + case 8'00000101 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [2] + attribute \src "ls180.v:0.0-0.0" + case 8'00000110 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [1] + attribute \src "ls180.v:0.0-0.0" + case 8'00000111 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0] + case + end + attribute \src "ls180.v:4397.4-4408.7" + switch \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:4397.8-4397.38" + case 1'1 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4398$638_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4400.5-4407.8" + switch $eq$ls180.v:4400$639_Y + attribute \src "ls180.v:4400.9-4400.40" + case 1'1 + attribute \src "ls180.v:4401.6-4406.9" + switch \main_sdphy_cmdw_sink_last + attribute \src "ls180.v:4401.10-4401.35" + case 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 + attribute \src "ls180.v:4403.10-4403.14" + case + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1 + attribute \src "ls180.v:4414.4-4421.7" + switch \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:4414.8-4414.38" + case 1'1 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4415$640_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4417.5-4420.8" + switch $eq$ls180.v:4417$641_Y + attribute \src "ls180.v:4417.9-4417.40" + case 1'1 + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4426.4-4430.7" + switch $and$ls180.v:4426$642_Y + attribute \src "ls180.v:4426.8-4426.69" + case 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 + attribute \src "ls180.v:4428.8-4428.12" + case + assign $0\main_sdphy_cmdw_done[0:0] 1'1 + end + end + sync always + update \main_sdphy_cmdw_pads_out_payload_clk $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] + update \main_sdphy_cmdw_pads_out_payload_cmd_o $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + update \main_sdphy_cmdw_pads_out_payload_cmd_oe $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_cmdw_sink_ready $0\main_sdphy_cmdw_sink_ready[0:0] + update \main_sdphy_cmdw_done $0\main_sdphy_cmdw_done[0:0] + update \builder_sdphy_sdphycmdw_next_state $0\builder_sdphy_sdphycmdw_next_state[1:0] + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + end + attribute \src "ls180.v:4467.1-4560.4" + process $proc$ls180.v:4467$651 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 + assign $0\main_sdphy_cmdr_source_last[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:4485.2-4559.9" + switch \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4493$652_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4490.4-4492.7" + switch \main_sdphy_cmdr_cmdr_source_source_valid0 + attribute \src "ls180.v:4490.8-4490.49" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:4495.4-4498.7" + switch $eq$ls180.v:4495$653_Y + attribute \src "ls180.v:4495.8-4495.41" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4504$655_Y + assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4521$658_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4506.4-4520.7" + switch $and$ls180.v:4506$656_Y + attribute \src "ls180.v:4506.8-4506.69" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4508$657_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4510.5-4519.8" + switch \main_sdphy_cmdr_source_last + attribute \src "ls180.v:4510.9-4510.36" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + attribute \src "ls180.v:4512.6-4518.9" + switch \main_sdphy_cmdr_sink_last + attribute \src "ls180.v:4512.10-4512.35" + case 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 + attribute \src "ls180.v:4516.10-4516.14" + case + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + end + case + end + case + end + attribute \src "ls180.v:4523.4-4526.7" + switch $eq$ls180.v:4523$659_Y + attribute \src "ls180.v:4523.8-4523.41" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1 + attribute \src "ls180.v:4532.4-4538.7" + switch \main_sdphy_cmdr_pads_out_ready + attribute \src "ls180.v:4532.8-4532.38" + case 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4533$660_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4535.5-4537.8" + switch $eq$ls180.v:4535$661_Y + attribute \src "ls180.v:4535.9-4535.40" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001 + assign $0\main_sdphy_cmdr_source_last[0:0] 1'1 + attribute \src "ls180.v:4544.4-4546.7" + switch $and$ls180.v:4544$662_Y + attribute \src "ls180.v:4544.8-4544.69" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4553.4-4557.7" + switch $and$ls180.v:4553$664_Y + attribute \src "ls180.v:4553.8-4553.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_cmdr_pads_out_payload_clk $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] + update \main_sdphy_cmdr_pads_out_payload_cmd_o $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + update \main_sdphy_cmdr_pads_out_payload_cmd_oe $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_cmdr_sink_ready $0\main_sdphy_cmdr_sink_ready[0:0] + update \main_sdphy_cmdr_source_valid $0\main_sdphy_cmdr_source_valid[0:0] + update \main_sdphy_cmdr_source_last $0\main_sdphy_cmdr_source_last[0:0] + update \main_sdphy_cmdr_source_payload_data $0\main_sdphy_cmdr_source_payload_data[7:0] + update \main_sdphy_cmdr_source_payload_status $0\main_sdphy_cmdr_source_payload_status[2:0] + update \main_sdphy_cmdr_cmdr_source_source_ready0 $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + update \builder_sdphy_sdphycmdr_next_state $0\builder_sdphy_sdphycmdr_next_state[2:0] + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + end + attribute \src "ls180.v:449.5-449.59" + process $proc$ls180.v:449$2926 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:451.5-451.59" + process $proc$ls180.v:451$2927 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:452.5-452.58" + process $proc$ls180.v:452$2928 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:453.5-453.64" + process $proc$ls180.v:453$2929 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:454.12-454.74" + process $proc$ls180.v:454$2930 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:455.12-455.47" + process $proc$ls180.v:455$2931 + assign { } { } + assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] + end + attribute \src "ls180.v:456.5-456.46" + process $proc$ls180.v:456$2932 + assign { } { } + assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] + end + attribute \src "ls180.v:458.5-458.44" + process $proc$ls180.v:458$2933 + assign { } { } + assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] + end + attribute \src "ls180.v:459.5-459.45" + process $proc$ls180.v:459$2934 + assign { } { } + assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] + end + attribute \src "ls180.v:4594.1-4621.4" + process $proc$ls180.v:4594$672 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_dataw_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\main_sdphy_dataw_error[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:4602.2-4620.9" + switch \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1 + attribute \src "ls180.v:4607.4-4611.7" + switch \main_sdphy_dataw_crcr_source_source_valid0 + attribute \src "ls180.v:4607.8-4607.50" + case 1'1 + assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4608$673_Y + assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4609$674_Y + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 + case + end + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:4614.4-4618.7" + switch \main_sdphy_dataw_start + attribute \src "ls180.v:4614.8-4614.30" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'1 + case + end + end + sync always + update \main_sdphy_dataw_valid $0\main_sdphy_dataw_valid[0:0] + update \main_sdphy_dataw_error $0\main_sdphy_dataw_error[0:0] + update \main_sdphy_dataw_crcr_source_source_ready0 $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] + update \builder_sdphy_sdphycrcr_next_state $0\builder_sdphy_sdphycrcr_next_state[0:0] + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + end + attribute \src "ls180.v:460.5-460.54" + process $proc$ls180.v:460$2935 + assign { } { } + assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:462.32-462.76" + process $proc$ls180.v:462$2936 + assign { } { } + assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + end + attribute \src "ls180.v:4622.1-4694.4" + process $proc$ls180.v:4622$675 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 + assign $0\main_sdphy_dataw_start[0:0] 1'0 + assign $0\main_sdphy_dataw_stop[0:0] 1'0 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 + assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state + attribute \src "ls180.v:4633.2-4693.9" + switch \builder_sdphy_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + attribute \src "ls180.v:4638.4-4640.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4638.8-4638.39" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4643$676_Y + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + attribute \src "ls180.v:4646.4-4653.11" + switch \main_sdphy_dataw_count + attribute \src "ls180.v:0.0-0.0" + case 8'00000000 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [7:4] + attribute \src "ls180.v:0.0-0.0" + case 8'00000001 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0] + case + end + attribute \src "ls180.v:4654.4-4666.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4654.8-4654.39" + case 1'1 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4655$677_Y + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4657.5-4665.8" + switch $eq$ls180.v:4657$678_Y + attribute \src "ls180.v:4657.9-4657.41" + case 1'1 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4660.6-4664.9" + switch \main_sdphy_dataw_sink_last + attribute \src "ls180.v:4660.10-4660.36" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 + attribute \src "ls180.v:4662.10-4662.14" + case + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111 + attribute \src "ls180.v:4672.4-4675.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4672.8-4672.39" + case 1'1 + assign $0\main_sdphy_dataw_start[0:0] 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:4679.4-4684.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4679.8-4679.39" + case 1'1 + attribute \src "ls180.v:4680.5-4683.8" + switch \main_sdphy_dataw_pads_in_payload_data_i [0] + attribute \src "ls180.v:4680.9-4680.51" + case 1'1 + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4689.4-4691.7" + switch $and$ls180.v:4689$679_Y + attribute \src "ls180.v:4689.8-4689.71" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_dataw_pads_out_payload_clk $0\main_sdphy_dataw_pads_out_payload_clk[0:0] + update \main_sdphy_dataw_pads_out_payload_data_o $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] + update \main_sdphy_dataw_pads_out_payload_data_oe $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + update \main_sdphy_dataw_sink_ready $0\main_sdphy_dataw_sink_ready[0:0] + update \main_sdphy_dataw_stop $0\main_sdphy_dataw_stop[0:0] + update \main_sdphy_dataw_start $0\main_sdphy_dataw_start[0:0] + update \builder_sdphy_fsm_next_state $0\builder_sdphy_fsm_next_state[2:0] + update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:463.11-463.55" + process $proc$ls180.v:463$2937 + assign { } { } + assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] + end + attribute \src "ls180.v:465.32-465.75" + process $proc$ls180.v:465$2938 + assign { } { } + assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:467.32-467.76" + process $proc$ls180.v:467$2939 + assign { } { } + assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:4728.1-4829.4" + process $proc$ls180.v:4728$687 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_datar_source_valid[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + assign $0\main_sdphy_datar_source_last[0:0] 1'0 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_datar_stop[0:0] 1'0 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:4745.2-4828.9" + switch \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 + assign { } { } + assign { } { } + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4755$689_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4752.4-4754.7" + switch \main_sdphy_datar_datar_source_source_valid0 + attribute \src "ls180.v:4752.8-4752.51" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:4757.4-4760.7" + switch $eq$ls180.v:4757$690_Y + attribute \src "ls180.v:4757.8-4757.42" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4766$693_Y + assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4787$695_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4768.4-4786.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:4768.8-4768.37" + case 1'1 + attribute \src "ls180.v:4769.5-4785.8" + switch \main_sdphy_datar_source_ready + attribute \src "ls180.v:4769.9-4769.38" + case 1'1 + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4771$694_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4773.6-4782.9" + switch \main_sdphy_datar_source_last + attribute \src "ls180.v:4773.10-4773.38" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + attribute \src "ls180.v:4775.7-4781.10" + switch \main_sdphy_datar_sink_last + attribute \src "ls180.v:4775.11-4775.37" + case 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 + attribute \src "ls180.v:4779.11-4779.15" + case + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + end + case + end + attribute \src "ls180.v:4783.9-4783.13" + case + assign $0\main_sdphy_datar_stop[0:0] 1'1 + end + case + end + attribute \src "ls180.v:4789.4-4792.7" + switch $eq$ls180.v:4789$696_Y + attribute \src "ls180.v:4789.8-4789.42" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:4796.4-4802.7" + switch \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:4796.8-4796.39" + case 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4797$697_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4799.5-4801.8" + switch $eq$ls180.v:4799$698_Y + attribute \src "ls180.v:4799.9-4799.42" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_datar_source_valid[0:0] 1'1 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001 + assign $0\main_sdphy_datar_source_last[0:0] 1'1 + attribute \src "ls180.v:4808.4-4810.7" + switch $and$ls180.v:4808$699_Y + attribute \src "ls180.v:4808.8-4808.71" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4815.4-4826.7" + switch $and$ls180.v:4815$700_Y + attribute \src "ls180.v:4815.8-4815.71" + case 1'1 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:4817.5-4825.8" + switch \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:4817.9-4817.40" + case 1'1 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'001 + case + end + case + end + end + sync always + update \main_sdphy_datar_pads_out_payload_clk $0\main_sdphy_datar_pads_out_payload_clk[0:0] + update \main_sdphy_datar_sink_ready $0\main_sdphy_datar_sink_ready[0:0] + update \main_sdphy_datar_source_valid $0\main_sdphy_datar_source_valid[0:0] + update \main_sdphy_datar_source_last $0\main_sdphy_datar_source_last[0:0] + update \main_sdphy_datar_source_payload_data $0\main_sdphy_datar_source_payload_data[7:0] + update \main_sdphy_datar_source_payload_status $0\main_sdphy_datar_source_payload_status[2:0] + update \main_sdphy_datar_stop $0\main_sdphy_datar_stop[0:0] + update \main_sdphy_datar_datar_source_source_ready0 $0\main_sdphy_datar_datar_source_source_ready0[0:0] + update \builder_sdphy_sdphydatar_next_state $0\builder_sdphy_sdphydatar_next_state[2:0] + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + end + attribute \src "ls180.v:473.5-473.51" + process $proc$ls180.v:473$2940 + assign { } { } + assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + end + attribute \src "ls180.v:474.5-474.51" + process $proc$ls180.v:474$2941 + assign { } { } + assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + end + attribute \src "ls180.v:476.5-476.47" + process $proc$ls180.v:476$2942 + assign { } { } + assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] + end + attribute \src "ls180.v:477.5-477.45" + process $proc$ls180.v:477$2943 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] + end + attribute \src "ls180.v:478.5-478.45" + process $proc$ls180.v:478$2944 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] + end + attribute \src "ls180.v:479.12-479.57" + process $proc$ls180.v:479$2945 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + end + attribute \src "ls180.v:481.5-481.51" + process $proc$ls180.v:481$2946 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:482.5-482.51" + process $proc$ls180.v:482$2947 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:483.5-483.50" + process $proc$ls180.v:483$2948 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + end + attribute \src "ls180.v:484.5-484.54" + process $proc$ls180.v:484$2949 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:485.5-485.55" + process $proc$ls180.v:485$2950 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:486.5-486.56" + process $proc$ls180.v:486$2951 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:487.5-487.50" + process $proc$ls180.v:487$2952 + assign { } { } + assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "ls180.v:4887.1-4894.4" + process $proc$ls180.v:4887$822 + assign { } { } + assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 + attribute \src "ls180.v:4889.2-4893.5" + switch \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:4889.6-4889.38" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40 + attribute \src "ls180.v:4891.6-4891.10" + case + assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0 + end + sync always + update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] + end + attribute \src "ls180.v:490.5-490.67" + process $proc$ls180.v:490$2953 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:4909.1-4916.4" + process $proc$ls180.v:4909$845 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:4911.2-4915.5" + switch \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:4911.6-4911.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 + attribute \src "ls180.v:4913.6-4913.10" + case + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] + end + attribute \src "ls180.v:491.5-491.66" + process $proc$ls180.v:491$2954 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:4919.1-4926.4" + process $proc$ls180.v:4919$856 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:4921.2-4925.5" + switch \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:4921.6-4921.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 + attribute \src "ls180.v:4923.6-4923.10" + case + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] + end + attribute \src "ls180.v:4929.1-4936.4" + process $proc$ls180.v:4929$867 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:4931.2-4935.5" + switch \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:4931.6-4931.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 + attribute \src "ls180.v:4933.6-4933.10" + case + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0] + end + attribute \src "ls180.v:4939.1-4946.4" + process $proc$ls180.v:4939$878 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:4941.2-4945.5" + switch \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:4941.6-4941.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 + attribute \src "ls180.v:4943.6-4943.10" + case + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0] + end + attribute \src "ls180.v:4947.1-5026.4" + process $proc$ls180.v:4947$879 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:4964.2-5025.9" + switch \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1 + attribute \src "ls180.v:4968.4-4970.7" + switch $eq$ls180.v:4968$880_Y + attribute \src "ls180.v:4968.8-4968.48" + case 1'1 + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1 + case + end + attribute \src "ls180.v:4971.4-4996.11" + switch \main_sdcore_crc16_inserter_cnt + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [15] \main_sdcore_crc16_inserter_crctmp2 [15] \main_sdcore_crc16_inserter_crctmp1 [15] \main_sdcore_crc16_inserter_crctmp0 [15] \main_sdcore_crc16_inserter_crctmp3 [14] \main_sdcore_crc16_inserter_crctmp2 [14] \main_sdcore_crc16_inserter_crctmp1 [14] \main_sdcore_crc16_inserter_crctmp0 [14] } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [13] \main_sdcore_crc16_inserter_crctmp2 [13] \main_sdcore_crc16_inserter_crctmp1 [13] \main_sdcore_crc16_inserter_crctmp0 [13] \main_sdcore_crc16_inserter_crctmp3 [12] \main_sdcore_crc16_inserter_crctmp2 [12] \main_sdcore_crc16_inserter_crctmp1 [12] \main_sdcore_crc16_inserter_crctmp0 [12] } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [11] \main_sdcore_crc16_inserter_crctmp2 [11] \main_sdcore_crc16_inserter_crctmp1 [11] \main_sdcore_crc16_inserter_crctmp0 [11] \main_sdcore_crc16_inserter_crctmp3 [10] \main_sdcore_crc16_inserter_crctmp2 [10] \main_sdcore_crc16_inserter_crctmp1 [10] \main_sdcore_crc16_inserter_crctmp0 [10] } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [9] \main_sdcore_crc16_inserter_crctmp2 [9] \main_sdcore_crc16_inserter_crctmp1 [9] \main_sdcore_crc16_inserter_crctmp0 [9] \main_sdcore_crc16_inserter_crctmp3 [8] \main_sdcore_crc16_inserter_crctmp2 [8] \main_sdcore_crc16_inserter_crctmp1 [8] \main_sdcore_crc16_inserter_crctmp0 [8] } + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [7] \main_sdcore_crc16_inserter_crctmp2 [7] \main_sdcore_crc16_inserter_crctmp1 [7] \main_sdcore_crc16_inserter_crctmp0 [7] \main_sdcore_crc16_inserter_crctmp3 [6] \main_sdcore_crc16_inserter_crctmp2 [6] \main_sdcore_crc16_inserter_crctmp1 [6] \main_sdcore_crc16_inserter_crctmp0 [6] } + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [5] \main_sdcore_crc16_inserter_crctmp2 [5] \main_sdcore_crc16_inserter_crctmp1 [5] \main_sdcore_crc16_inserter_crctmp0 [5] \main_sdcore_crc16_inserter_crctmp3 [4] \main_sdcore_crc16_inserter_crctmp2 [4] \main_sdcore_crc16_inserter_crctmp1 [4] \main_sdcore_crc16_inserter_crctmp0 [4] } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [3] \main_sdcore_crc16_inserter_crctmp2 [3] \main_sdcore_crc16_inserter_crctmp1 [3] \main_sdcore_crc16_inserter_crctmp0 [3] \main_sdcore_crc16_inserter_crctmp3 [2] \main_sdcore_crc16_inserter_crctmp2 [2] \main_sdcore_crc16_inserter_crctmp1 [2] \main_sdcore_crc16_inserter_crctmp0 [2] } + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] } + case + end + attribute \src "ls180.v:4997.4-5004.7" + switch \main_sdcore_crc16_inserter_source_ready + attribute \src "ls180.v:4997.8-4997.47" + case 1'1 + attribute \src "ls180.v:4998.5-5003.8" + switch $eq$ls180.v:4998$881_Y + attribute \src "ls180.v:4998.9-4998.49" + case 1'1 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 + attribute \src "ls180.v:5000.9-5000.13" + case + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5001$882_Y + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] \main_sdcore_crc16_inserter_sink_payload_data + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] \main_sdcore_crc16_inserter_sink_valid + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] \main_sdcore_crc16_inserter_source_ready + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] \main_sdcore_crc16_inserter_crc0_crc + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] \main_sdcore_crc16_inserter_crc1_crc + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] \main_sdcore_crc16_inserter_crc2_crc + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5019.4-5023.7" + switch $and$ls180.v:5019$884_Y + attribute \src "ls180.v:5019.8-5019.128" + case 1'1 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 + case + end + end + sync always + update \main_sdcore_crc16_inserter_sink_ready $0\main_sdcore_crc16_inserter_sink_ready[0:0] + update \main_sdcore_crc16_inserter_source_valid $0\main_sdcore_crc16_inserter_source_valid[0:0] + update \main_sdcore_crc16_inserter_source_last $0\main_sdcore_crc16_inserter_source_last[0:0] + update \main_sdcore_crc16_inserter_source_payload_data $0\main_sdcore_crc16_inserter_source_payload_data[7:0] + update \builder_sdcore_crcupstreaminserter_next_state $0\builder_sdcore_crcupstreaminserter_next_state[0:0] + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + end + attribute \src "ls180.v:5027.1-5032.4" + process $proc$ls180.v:5027$885 + assign { } { } + assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0 + attribute \src "ls180.v:5029.2-5031.5" + switch $and$ls180.v:5029$892_Y + attribute \src "ls180.v:5029.6-5029.301" + case 1'1 + assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1 + case + end + sync always + update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0] + end + attribute \src "ls180.v:5035.1-5042.4" + process $proc$ls180.v:5035$894 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + attribute \src "ls180.v:5037.2-5041.5" + switch $eq$ls180.v:5037$895_Y + attribute \src "ls180.v:5037.6-5037.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1 + attribute \src "ls180.v:5039.6-5039.10" + case + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0] + end + attribute \src "ls180.v:5045.1-5052.4" + process $proc$ls180.v:5045$897 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + attribute \src "ls180.v:5047.2-5051.5" + switch $eq$ls180.v:5047$898_Y + attribute \src "ls180.v:5047.6-5047.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1 + attribute \src "ls180.v:5049.6-5049.10" + case + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0] + end + attribute \src "ls180.v:5055.1-5062.4" + process $proc$ls180.v:5055$900 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + attribute \src "ls180.v:5057.2-5061.5" + switch $eq$ls180.v:5057$901_Y + attribute \src "ls180.v:5057.6-5057.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1 + attribute \src "ls180.v:5059.6-5059.10" + case + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0] + end + attribute \src "ls180.v:506.11-506.68" + process $proc$ls180.v:506$2955 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:5065.1-5072.4" + process $proc$ls180.v:5065$903 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + attribute \src "ls180.v:5067.2-5071.5" + switch $eq$ls180.v:5067$904_Y + attribute \src "ls180.v:5067.6-5067.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1 + attribute \src "ls180.v:5069.6-5069.10" + case + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0] + end + attribute \src "ls180.v:507.5-507.64" + process $proc$ls180.v:507$2956 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:5074.1-5079.4" + process $proc$ls180.v:5074$905 + assign { } { } + assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0 + attribute \src "ls180.v:5076.2-5078.5" + switch $and$ls180.v:5076$907_Y + attribute \src "ls180.v:5076.6-5076.85" + case 1'1 + assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1 + case + end + sync always + update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0] + end + attribute \src "ls180.v:508.11-508.70" + process $proc$ls180.v:508$2957 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:5080.1-5087.4" + process $proc$ls180.v:5080$908 + assign { } { } + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 + attribute \src "ls180.v:5082.2-5086.5" + switch $lt$ls180.v:5082$909_Y + attribute \src "ls180.v:5082.6-5082.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1 + attribute \src "ls180.v:5084.6-5084.10" + case + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready + end + sync always + update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0] + end + attribute \src "ls180.v:509.11-509.70" + process $proc$ls180.v:509$2958 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:5091.1-5098.4" + process $proc$ls180.v:5091$920 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5093.2-5097.5" + switch \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:5093.6-5093.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 + attribute \src "ls180.v:5095.6-5095.10" + case + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0] + end + attribute \src "ls180.v:510.11-510.73" + process $proc$ls180.v:510$2959 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:5101.1-5108.4" + process $proc$ls180.v:5101$931 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5103.2-5107.5" + switch \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:5103.6-5103.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 + attribute \src "ls180.v:5105.6-5105.10" + case + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0] + end + attribute \src "ls180.v:5111.1-5118.4" + process $proc$ls180.v:5111$942 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5113.2-5117.5" + switch \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:5113.6-5113.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 + attribute \src "ls180.v:5115.6-5115.10" + case + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] + end + attribute \src "ls180.v:5121.1-5128.4" + process $proc$ls180.v:5121$953 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5123.2-5127.5" + switch \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:5123.6-5123.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 + attribute \src "ls180.v:5125.6-5125.10" + case + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] + end + attribute \src "ls180.v:5129.1-5319.4" + process $proc$ls180.v:5129$954 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 + assign $0\main_sdphy_datar_sink_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_first[0:0] 1'0 + assign $0\main_sdphy_datar_sink_last[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_last[0:0] 1'0 + assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 + assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 + assign $0\main_sdphy_datar_source_ready[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 + assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state + attribute \src "ls180.v:5170.2-5318.9" + switch \builder_sdcore_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1 + attribute \src "ls180.v:5173.4-5193.11" + switch \main_sdcore_cmd_count + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { 2'01 \main_sdcore_cmd_command_storage [13:8] } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [31:24] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [23:16] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [15:8] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [7:0] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 } + assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5191$955_Y + case + end + attribute \src "ls180.v:5194.4-5206.7" + switch $and$ls180.v:5194$956_Y + attribute \src "ls180.v:5194.8-5194.65" + case 1'1 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5195$957_Y + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 + attribute \src "ls180.v:5197.5-5205.8" + switch $eq$ls180.v:5197$958_Y + attribute \src "ls180.v:5197.9-5197.40" + case 1'1 + attribute \src "ls180.v:5198.6-5204.9" + switch $eq$ls180.v:5198$959_Y + attribute \src "ls180.v:5198.10-5198.40" + case 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5202.10-5202.14" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1 + assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5210$960_Y + assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1 + attribute \src "ls180.v:5211.4-5215.7" + switch $eq$ls180.v:5211$961_Y + attribute \src "ls180.v:5211.8-5211.38" + case 1'1 + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001 + attribute \src "ls180.v:5213.8-5213.12" + case + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110 + end + attribute \src "ls180.v:5217.4-5238.7" + switch \main_sdphy_cmdr_source_valid + attribute \src "ls180.v:5217.8-5217.36" + case 1'1 + attribute \src "ls180.v:5218.5-5237.8" + switch $eq$ls180.v:5218$962_Y + attribute \src "ls180.v:5218.9-5218.56" + case 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5222.9-5222.13" + case + attribute \src "ls180.v:5223.6-5236.9" + switch \main_sdphy_cmdr_source_last + attribute \src "ls180.v:5223.10-5223.37" + case 1'1 + attribute \src "ls180.v:5224.7-5232.10" + switch $eq$ls180.v:5224$963_Y + attribute \src "ls180.v:5224.11-5224.42" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 + attribute \src "ls180.v:5226.11-5226.15" + case + attribute \src "ls180.v:5227.8-5231.11" + switch $eq$ls180.v:5227$964_Y + attribute \src "ls180.v:5227.12-5227.43" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 + attribute \src "ls180.v:5229.12-5229.16" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + end + end + attribute \src "ls180.v:5233.10-5233.14" + case + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data } + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_sink_valid[0:0] \main_sdcore_crc16_inserter_source_valid + assign $0\main_sdcore_crc16_inserter_source_ready[0:0] \main_sdphy_dataw_sink_ready + assign $0\main_sdphy_dataw_sink_first[0:0] \main_sdcore_crc16_inserter_source_first + assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last + assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data + assign $0\main_sdphy_datar_source_ready[0:0] 1'1 + attribute \src "ls180.v:5246.4-5252.7" + switch $and$ls180.v:5246$966_Y + attribute \src "ls180.v:5246.8-5246.98" + case 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5247$967_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5249.5-5251.8" + switch $eq$ls180.v:5249$969_Y + attribute \src "ls180.v:5249.9-5249.77" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:5254.4-5259.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:5254.8-5254.37" + case 1'1 + attribute \src "ls180.v:5255.5-5258.8" + switch $ne$ls180.v:5255$970_Y + attribute \src "ls180.v:5255.9-5255.57" + case 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_datar_sink_valid[0:0] 1'1 + assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage + assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5264$972_Y + attribute \src "ls180.v:5265.4-5291.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:5265.8-5265.37" + case 1'1 + attribute \src "ls180.v:5266.5-5290.8" + switch $eq$ls180.v:5266$973_Y + attribute \src "ls180.v:5266.9-5266.57" + case 1'1 + assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid + assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready + assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first + assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last + assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data + attribute \src "ls180.v:5272.6-5280.9" + switch $and$ls180.v:5272$974_Y + attribute \src "ls180.v:5272.10-5272.72" + case 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5273$975_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5275.7-5279.10" + switch $eq$ls180.v:5275$977_Y + attribute \src "ls180.v:5275.11-5275.79" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5277.11-5277.15" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 + end + case + end + attribute \src "ls180.v:5281.9-5281.13" + case + attribute \src "ls180.v:5282.6-5289.9" + switch $eq$ls180.v:5282$978_Y + attribute \src "ls180.v:5282.10-5282.58" + case 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + assign $0\main_sdphy_datar_source_ready[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + case + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5302.4-5316.7" + switch \main_sdcore_cmd_send_re + attribute \src "ls180.v:5302.8-5302.31" + case 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_cmdw_sink_valid $0\main_sdphy_cmdw_sink_valid[0:0] + update \main_sdphy_cmdw_sink_last $0\main_sdphy_cmdw_sink_last[0:0] + update \main_sdphy_cmdw_sink_payload_data $0\main_sdphy_cmdw_sink_payload_data[7:0] + update \main_sdphy_cmdr_sink_valid $0\main_sdphy_cmdr_sink_valid[0:0] + update \main_sdphy_cmdr_sink_last $0\main_sdphy_cmdr_sink_last[0:0] + update \main_sdphy_cmdr_sink_payload_length $0\main_sdphy_cmdr_sink_payload_length[7:0] + update \main_sdphy_cmdr_source_ready $0\main_sdphy_cmdr_source_ready[0:0] + update \main_sdphy_dataw_sink_valid $0\main_sdphy_dataw_sink_valid[0:0] + update \main_sdphy_dataw_sink_first $0\main_sdphy_dataw_sink_first[0:0] + update \main_sdphy_dataw_sink_last $0\main_sdphy_dataw_sink_last[0:0] + update \main_sdphy_dataw_sink_payload_data $0\main_sdphy_dataw_sink_payload_data[7:0] + update \main_sdphy_datar_sink_valid $0\main_sdphy_datar_sink_valid[0:0] + update \main_sdphy_datar_sink_last $0\main_sdphy_datar_sink_last[0:0] + update \main_sdphy_datar_sink_payload_block_length $0\main_sdphy_datar_sink_payload_block_length[9:0] + update \main_sdphy_datar_source_ready $0\main_sdphy_datar_source_ready[0:0] + update \main_sdcore_crc16_inserter_source_ready $0\main_sdcore_crc16_inserter_source_ready[0:0] + update \main_sdcore_crc16_checker_sink_valid $0\main_sdcore_crc16_checker_sink_valid[0:0] + update \main_sdcore_crc16_checker_sink_first $0\main_sdcore_crc16_checker_sink_first[0:0] + update \main_sdcore_crc16_checker_sink_last $0\main_sdcore_crc16_checker_sink_last[0:0] + update \main_sdcore_crc16_checker_sink_payload_data $0\main_sdcore_crc16_checker_sink_payload_data[7:0] + update \builder_sdcore_fsm_next_state $0\builder_sdcore_fsm_next_state[2:0] + update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + update \main_sdcore_data_done_sdcore_fsm_next_value1 $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + update \main_sdcore_data_count_sdcore_fsm_next_value3 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + update \main_sdcore_data_error_sdcore_fsm_next_value6 $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + end + attribute \src "ls180.v:531.5-531.59" + process $proc$ls180.v:531$2960 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:533.5-533.59" + process $proc$ls180.v:533$2961 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:534.5-534.58" + process $proc$ls180.v:534$2962 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:5347.1-5354.4" + process $proc$ls180.v:5347$979 + assign { } { } + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 + attribute \src "ls180.v:5349.2-5353.5" + switch \main_sdblock2mem_fifo_replace + attribute \src "ls180.v:5349.6-5349.35" + case 1'1 + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5350$980_Y + attribute \src "ls180.v:5351.6-5351.10" + case + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce + end + sync always + update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:535.5-535.64" + process $proc$ls180.v:535$2963 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:536.12-536.74" + process $proc$ls180.v:536$2964 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:537.12-537.47" + process $proc$ls180.v:537$2965 + assign { } { } + assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] + end + attribute \src "ls180.v:538.5-538.46" + process $proc$ls180.v:538$2966 + assign { } { } + assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] + end + attribute \src "ls180.v:5380.1-5419.4" + process $proc$ls180.v:5380$990 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0 + assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 + assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state + attribute \src "ls180.v:5390.2-5418.9" + switch \builder_sdblock2memdma_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid + assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5394$991_Y + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1 + attribute \src "ls180.v:5396.4-5407.7" + switch $and$ls180.v:5396$992_Y + attribute \src "ls180.v:5396.8-5396.103" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5397$993_Y + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5399.5-5406.8" + switch $eq$ls180.v:5399$995_Y + attribute \src "ls180.v:5399.9-5399.106" + case 1'1 + attribute \src "ls180.v:5400.6-5405.9" + switch \main_sdblock2mem_wishbonedmawriter_loop_storage + attribute \src "ls180.v:5400.10-5400.57" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5403.10-5403.14" + case + assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'1 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + assign $0\builder_sdblock2memdma_next_state[1:0] 2'01 + end + sync always + update \main_sdblock2mem_sink_sink_valid1 $0\main_sdblock2mem_sink_sink_valid1[0:0] + update \main_sdblock2mem_sink_sink_payload_address $0\main_sdblock2mem_sink_sink_payload_address[31:0] + update \main_sdblock2mem_sink_sink_payload_data1 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] + update \main_sdblock2mem_wishbonedmawriter_sink_ready $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + update \main_sdblock2mem_wishbonedmawriter_status $0\main_sdblock2mem_wishbonedmawriter_status[0:0] + update \builder_sdblock2memdma_next_state $0\builder_sdblock2memdma_next_state[1:0] + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + end + attribute \src "ls180.v:540.5-540.44" + process $proc$ls180.v:540$2967 + assign { } { } + assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] + end + attribute \src "ls180.v:541.5-541.45" + process $proc$ls180.v:541$2968 + assign { } { } + assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] + end + attribute \src "ls180.v:542.5-542.54" + process $proc$ls180.v:542$2969 + assign { } { } + assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:5439.1-5476.4" + process $proc$ls180.v:5439$997 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_interface1_bus_stb[0:0] 1'0 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 + assign $0\main_interface1_bus_we[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_payload_data[31:0] 0 + assign $0\main_interface1_bus_adr[31:0] 0 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0 + assign { } { } + assign $0\main_interface1_bus_sel[3:0] 4'0000 + assign $0\main_interface1_bus_cyc[0:0] 1'0 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:5453.2-5475.9" + switch \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1 + assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last + assign $0\main_sdmem2block_dma_source_payload_data[31:0] \main_sdmem2block_dma_data + attribute \src "ls180.v:5458.4-5461.7" + switch \main_sdmem2block_dma_source_ready + attribute \src "ls180.v:5458.8-5458.41" + case 1'1 + assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_interface1_bus_stb[0:0] \main_sdmem2block_dma_sink_valid + assign $0\main_interface1_bus_cyc[0:0] \main_sdmem2block_dma_sink_valid + assign $0\main_interface1_bus_we[0:0] 1'0 + assign $0\main_interface1_bus_sel[3:0] 4'1111 + assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address + attribute \src "ls180.v:5469.4-5473.7" + switch $and$ls180.v:5469$998_Y + attribute \src "ls180.v:5469.8-5469.59" + case 1'1 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] } + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'1 + case + end + end + sync always + update \main_interface1_bus_adr $0\main_interface1_bus_adr[31:0] + update \main_interface1_bus_sel $0\main_interface1_bus_sel[3:0] + update \main_interface1_bus_cyc $0\main_interface1_bus_cyc[0:0] + update \main_interface1_bus_stb $0\main_interface1_bus_stb[0:0] + update \main_interface1_bus_we $0\main_interface1_bus_we[0:0] + update \main_sdmem2block_dma_sink_ready $0\main_sdmem2block_dma_sink_ready[0:0] + update \main_sdmem2block_dma_source_valid $0\main_sdmem2block_dma_source_valid[0:0] + update \main_sdmem2block_dma_source_last $0\main_sdmem2block_dma_source_last[0:0] + update \main_sdmem2block_dma_source_payload_data $0\main_sdmem2block_dma_source_payload_data[31:0] + update \builder_sdmem2blockdma_fsm_next_state $0\builder_sdmem2blockdma_fsm_next_state[0:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:544.32-544.76" + process $proc$ls180.v:544$2970 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] + end + attribute \src "ls180.v:545.11-545.55" + process $proc$ls180.v:545$2971 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] + end + attribute \src "ls180.v:547.32-547.75" + process $proc$ls180.v:547$2972 + assign { } { } + assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:5477.1-5513.4" + process $proc$ls180.v:5477$999 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 + assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 + assign { } { } + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:5486.2-5512.9" + switch \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1 + assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5489$1001_Y + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5490$1002_Y + attribute \src "ls180.v:5491.4-5502.7" + switch \main_sdmem2block_dma_sink_ready + attribute \src "ls180.v:5491.8-5491.39" + case 1'1 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5492$1003_Y + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5494.5-5501.8" + switch \main_sdmem2block_dma_sink_last + attribute \src "ls180.v:5494.9-5494.39" + case 1'1 + attribute \src "ls180.v:5495.6-5500.9" + switch \main_sdmem2block_dma_loop_storage + attribute \src "ls180.v:5495.10-5495.43" + case 1'1 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5498.10-5498.14" + case + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdmem2block_dma_done_status[0:0] 1'1 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'01 + end + sync always + update \main_sdmem2block_dma_sink_valid $0\main_sdmem2block_dma_sink_valid[0:0] + update \main_sdmem2block_dma_sink_last $0\main_sdmem2block_dma_sink_last[0:0] + update \main_sdmem2block_dma_sink_payload_address $0\main_sdmem2block_dma_sink_payload_address[31:0] + update \main_sdmem2block_dma_done_status $0\main_sdmem2block_dma_done_status[0:0] + update \builder_sdmem2blockdma_resetinserter_next_state $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + end + attribute \src "ls180.v:549.32-549.76" + process $proc$ls180.v:549$2973 + assign { } { } + assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:55.5-55.42" + process $proc$ls180.v:55$2775 + assign { } { } + assign $1\main_libresocsim_reset_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] + end + attribute \src "ls180.v:5525.1-5541.4" + process $proc$ls180.v:5525$1009 + assign { } { } + assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 + attribute \src "ls180.v:5527.2-5540.9" + switch \main_sdmem2block_converter_mux + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [31:24] + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [23:16] + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [15:8] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [7:0] + end + sync always + update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:555.5-555.51" + process $proc$ls180.v:555$2974 + assign { } { } + assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + end + attribute \src "ls180.v:5555.1-5562.4" + process $proc$ls180.v:5555$1010 + assign { } { } + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 + attribute \src "ls180.v:5557.2-5561.5" + switch \main_sdmem2block_fifo_replace + attribute \src "ls180.v:5557.6-5557.35" + case 1'1 + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5558$1011_Y + attribute \src "ls180.v:5559.6-5559.10" + case + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce + end + sync always + update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:556.5-556.51" + process $proc$ls180.v:556$2975 + assign { } { } + assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] + end + attribute \src "ls180.v:558.5-558.47" + process $proc$ls180.v:558$2976 + assign { } { } + assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] + end + attribute \src "ls180.v:5580.1-5628.4" + process $proc$ls180.v:5580$1021 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\libresocsim_clk_enable[0:0] 1'0 + assign $0\libresocsim_count_spimaster1_next_value[2:0] 3'000 + assign $0\libresocsim_cs_enable[0:0] 1'0 + assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'0 + assign $0\libresocsim_mosi_latch[0:0] 1'0 + assign $0\libresocsim_done0[0:0] 1'0 + assign $0\libresocsim_miso_latch[0:0] 1'0 + assign $0\libresocsim_irq[0:0] 1'0 + assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state + attribute \src "ls180.v:5591.2-5627.9" + switch \builder_spimaster1_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\libresocsim_count_spimaster1_next_value[2:0] 3'000 + assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5595.4-5598.7" + switch \libresocsim_clk_fall + attribute \src "ls180.v:5595.8-5595.28" + case 1'1 + assign $0\libresocsim_cs_enable[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\libresocsim_clk_enable[0:0] 1'1 + assign $0\libresocsim_cs_enable[0:0] 1'1 + attribute \src "ls180.v:5603.4-5609.7" + switch \libresocsim_clk_fall + attribute \src "ls180.v:5603.8-5603.28" + case 1'1 + assign $0\libresocsim_count_spimaster1_next_value[2:0] $add$ls180.v:5604$1022_Y + assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5606.5-5608.8" + switch $eq$ls180.v:5606$1024_Y + attribute \src "ls180.v:5606.9-5606.60" + case 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'11 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\libresocsim_cs_enable[0:0] 1'1 + attribute \src "ls180.v:5613.4-5617.7" + switch \libresocsim_clk_rise + attribute \src "ls180.v:5613.8-5613.28" + case 1'1 + assign $0\libresocsim_miso_latch[0:0] 1'1 + assign $0\libresocsim_irq[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\libresocsim_done0[0:0] 1'1 + attribute \src "ls180.v:5621.4-5625.7" + switch \libresocsim_start0 + attribute \src "ls180.v:5621.8-5621.26" + case 1'1 + assign $0\libresocsim_done0[0:0] 1'0 + assign $0\libresocsim_mosi_latch[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'01 + case + end + end + sync always + update \libresocsim_done0 $0\libresocsim_done0[0:0] + update \libresocsim_irq $0\libresocsim_irq[0:0] + update \libresocsim_clk_enable $0\libresocsim_clk_enable[0:0] + update \libresocsim_cs_enable $0\libresocsim_cs_enable[0:0] + update \libresocsim_mosi_latch $0\libresocsim_mosi_latch[0:0] + update \libresocsim_miso_latch $0\libresocsim_miso_latch[0:0] + update \builder_spimaster1_next_state $0\builder_spimaster1_next_state[1:0] + update \libresocsim_count_spimaster1_next_value $0\libresocsim_count_spimaster1_next_value[2:0] + update \libresocsim_count_spimaster1_next_value_ce $0\libresocsim_count_spimaster1_next_value_ce[0:0] + end + attribute \src "ls180.v:559.5-559.45" + process $proc$ls180.v:559$2977 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] + end + attribute \src "ls180.v:56.5-56.37" + process $proc$ls180.v:56$2776 + assign { } { } + assign $1\main_libresocsim_reset_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] + end + attribute \src "ls180.v:560.5-560.45" + process $proc$ls180.v:560$2978 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] + end + attribute \src "ls180.v:561.12-561.57" + process $proc$ls180.v:561$2979 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] + end + attribute \src "ls180.v:5629.1-5665.4" + process $proc$ls180.v:5629$1025 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 + assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 + assign { } { } + assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 + assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 + assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 + assign $0\builder_next_state[1:0] \builder_state + attribute \src "ls180.v:5640.2-5664.9" + switch \builder_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 + assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 + assign $0\builder_next_state[1:0] 2'10 + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'1 + assign $0\builder_libresocsim_wishbone_dat_r[31:0] { 24'000000000000000000000000 \builder_libresocsim_dat_r } + assign $0\builder_next_state[1:0] 2'00 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] + assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:5656.4-5662.7" + switch $and$ls180.v:5656$1026_Y + attribute \src "ls180.v:5656.8-5656.77" + case 1'1 + assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 + assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5659$1028_Y + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 + assign $0\builder_next_state[1:0] 2'01 + case + end + end + sync always + update \builder_libresocsim_wishbone_dat_r $0\builder_libresocsim_wishbone_dat_r[31:0] + update \builder_libresocsim_wishbone_ack $0\builder_libresocsim_wishbone_ack[0:0] + update \builder_next_state $0\builder_next_state[1:0] + update \builder_libresocsim_dat_w_next_value0 $0\builder_libresocsim_dat_w_next_value0[7:0] + update \builder_libresocsim_dat_w_next_value_ce0 $0\builder_libresocsim_dat_w_next_value_ce0[0:0] + update \builder_libresocsim_adr_next_value1 $0\builder_libresocsim_adr_next_value1[13:0] + update \builder_libresocsim_adr_next_value_ce1 $0\builder_libresocsim_adr_next_value_ce1[0:0] + update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] + update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] + end + attribute \src "ls180.v:563.5-563.51" + process $proc$ls180.v:563$2980 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:564.5-564.51" + process $proc$ls180.v:564$2981 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:565.5-565.50" + process $proc$ls180.v:565$2982 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] + end + attribute \src "ls180.v:566.5-566.54" + process $proc$ls180.v:566$2983 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:567.5-567.55" + process $proc$ls180.v:567$2984 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:568.5-568.56" + process $proc$ls180.v:568$2985 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:569.5-569.50" + process $proc$ls180.v:569$2986 + assign { } { } + assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] + end + attribute \src "ls180.v:5690.1-5697.4" + process $proc$ls180.v:5690$1049 + assign { } { } + assign { } { } + assign $0\builder_slave_sel[4:0] [0] $eq$ls180.v:5692$1050_Y + assign $0\builder_slave_sel[4:0] [1] $eq$ls180.v:5693$1051_Y + assign $0\builder_slave_sel[4:0] [2] $eq$ls180.v:5694$1052_Y + assign $0\builder_slave_sel[4:0] [3] $eq$ls180.v:5695$1053_Y + assign $0\builder_slave_sel[4:0] [4] $eq$ls180.v:5696$1054_Y + sync always + update \builder_slave_sel $0\builder_slave_sel[4:0] + end + attribute \src "ls180.v:57.12-57.60" + process $proc$ls180.v:57$2777 + assign { } { } + assign $1\main_libresocsim_scratch_storage[31:0] 305419896 + sync always + sync init + update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] + end + attribute \src "ls180.v:572.5-572.67" + process $proc$ls180.v:572$2987 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:573.5-573.66" + process $proc$ls180.v:573$2988 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:5740.1-5751.4" + process $proc$ls180.v:5740$1067 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_error[0:0] 1'0 + assign $0\builder_shared_ack[0:0] $or$ls180.v:5744$1071_Y + assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5745$1080_Y + attribute \src "ls180.v:5746.2-5750.5" + switch \builder_done + attribute \src "ls180.v:5746.6-5746.18" + case 1'1 + assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 + assign $0\builder_shared_ack[0:0] 1'1 + assign $0\builder_error[0:0] 1'1 + case + end + sync always + update \builder_shared_dat_r $0\builder_shared_dat_r[31:0] + update \builder_shared_ack $0\builder_shared_ack[0:0] + update \builder_error $0\builder_error[0:0] + end + attribute \src "ls180.v:58.5-58.39" + process $proc$ls180.v:58$2778 + assign { } { } + assign $1\main_libresocsim_scratch_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] + end + attribute \src "ls180.v:588.11-588.68" + process $proc$ls180.v:588$2989 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:589.5-589.64" + process $proc$ls180.v:589$2990 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:590.11-590.70" + process $proc$ls180.v:590$2991 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:591.11-591.70" + process $proc$ls180.v:591$2992 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:592.11-592.73" + process $proc$ls180.v:592$2993 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:613.5-613.59" + process $proc$ls180.v:613$2994 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:615.5-615.59" + process $proc$ls180.v:615$2995 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:616.5-616.58" + process $proc$ls180.v:616$2996 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:617.5-617.64" + process $proc$ls180.v:617$2997 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:618.12-618.74" + process $proc$ls180.v:618$2998 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:619.12-619.47" + process $proc$ls180.v:619$2999 + assign { } { } + assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] + end + attribute \src "ls180.v:620.5-620.46" + process $proc$ls180.v:620$3000 + assign { } { } + assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] + end + attribute \src "ls180.v:622.5-622.44" + process $proc$ls180.v:622$3001 + assign { } { } + assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] + end + attribute \src "ls180.v:623.5-623.45" + process $proc$ls180.v:623$3002 + assign { } { } + assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] + end + attribute \src "ls180.v:624.5-624.54" + process $proc$ls180.v:624$3003 + assign { } { } + assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:626.32-626.76" + process $proc$ls180.v:626$3004 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + end + attribute \src "ls180.v:6265.1-6270.4" + process $proc$ls180.v:6265$1954 + assign { } { } + assign $0\main_spi_master_start1[0:0] 1'0 + attribute \src "ls180.v:6267.2-6269.5" + switch \main_spi_master_control_re + attribute \src "ls180.v:6267.6-6267.32" + case 1'1 + assign $0\main_spi_master_start1[0:0] \main_spi_master_control_storage [0] + case + end + sync always + update \main_spi_master_start1 $0\main_spi_master_start1[0:0] + end + attribute \src "ls180.v:627.11-627.55" + process $proc$ls180.v:627$3005 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] + end + attribute \src "ls180.v:629.32-629.75" + process $proc$ls180.v:629$3006 + assign { } { } + assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:63.12-63.47" + process $proc$ls180.v:63$2779 + assign { } { } + assign $1\main_libresocsim_bus_errors[31:0] 0 + sync always + sync init + update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] + end + attribute \src "ls180.v:631.32-631.76" + process $proc$ls180.v:631$3007 + assign { } { } + assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:6311.1-6316.4" + process $proc$ls180.v:6311$2019 + assign { } { } + assign $0\libresocsim_start1[0:0] 1'0 + attribute \src "ls180.v:6313.2-6315.5" + switch \libresocsim_control_re + attribute \src "ls180.v:6313.6-6313.28" + case 1'1 + assign $0\libresocsim_start1[0:0] \libresocsim_control_storage [0] + case + end + sync always + update \libresocsim_start1 $0\libresocsim_start1[0:0] + end + attribute \src "ls180.v:637.5-637.51" + process $proc$ls180.v:637$3008 + assign { } { } + assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] + end + attribute \src "ls180.v:638.5-638.51" + process $proc$ls180.v:638$3009 + assign { } { } + assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + end + attribute \src "ls180.v:640.5-640.47" + process $proc$ls180.v:640$3010 + assign { } { } + assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] + end + attribute \src "ls180.v:641.5-641.45" + process $proc$ls180.v:641$3011 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] + end + attribute \src "ls180.v:642.5-642.45" + process $proc$ls180.v:642$3012 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] + end + attribute \src "ls180.v:643.12-643.57" + process $proc$ls180.v:643$3013 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + end + attribute \src "ls180.v:645.5-645.51" + process $proc$ls180.v:645$3014 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:646.5-646.51" + process $proc$ls180.v:646$3015 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:647.5-647.50" + process $proc$ls180.v:647$3016 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + end + attribute \src "ls180.v:648.5-648.54" + process $proc$ls180.v:648$3017 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:649.5-649.55" + process $proc$ls180.v:649$3018 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:65.12-65.55" + process $proc$ls180.v:65$2780 + assign { } { } + assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] + end + attribute \src "ls180.v:650.5-650.56" + process $proc$ls180.v:650$3019 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:6500.1-6516.4" + process $proc$ls180.v:6500$2240 + assign { } { } + assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:6502.2-6515.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [0] + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [1] + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [2] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [3] + end + sync always + update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] + end + attribute \src "ls180.v:651.5-651.50" + process $proc$ls180.v:651$3020 + assign { } { } + assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "ls180.v:6517.1-6533.4" + process $proc$ls180.v:6517$2241 + assign { } { } + assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 + attribute \src "ls180.v:6519.2-6532.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine3_cmd_payload_a + end + sync always + update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:6534.1-6550.4" + process $proc$ls180.v:6534$2242 + assign { } { } + assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 + attribute \src "ls180.v:6536.2-6549.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine3_cmd_payload_ba + end + sync always + update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] + end + attribute \src "ls180.v:654.5-654.67" + process $proc$ls180.v:654$3021 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:655.5-655.66" + process $proc$ls180.v:655$3022 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:6551.1-6567.4" + process $proc$ls180.v:6551$2243 + assign { } { } + assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:6553.2-6566.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_is_read + end + sync always + update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:6568.1-6584.4" + process $proc$ls180.v:6568$2244 + assign { } { } + assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:6570.2-6583.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_is_write + end + sync always + update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:6585.1-6601.4" + process $proc$ls180.v:6585$2245 + assign { } { } + assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:6587.2-6600.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd + end + sync always + update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:6602.1-6618.4" + process $proc$ls180.v:6602$2246 + assign { } { } + assign $0\builder_comb_t_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:6604.2-6617.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine3_cmd_payload_cas + end + sync always + update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] + end + attribute \src "ls180.v:6619.1-6635.4" + process $proc$ls180.v:6619$2247 + assign { } { } + assign $0\builder_comb_t_array_muxed1[0:0] 1'0 + attribute \src "ls180.v:6621.2-6634.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine3_cmd_payload_ras + end + sync always + update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] + end + attribute \src "ls180.v:6636.1-6652.4" + process $proc$ls180.v:6636$2248 + assign { } { } + assign $0\builder_comb_t_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:6638.2-6651.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine3_cmd_payload_we + end + sync always + update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] + end + attribute \src "ls180.v:6653.1-6669.4" + process $proc$ls180.v:6653$2249 + assign { } { } + assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:6655.2-6668.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [0] + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [1] + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [2] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [3] + end + sync always + update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:6670.1-6686.4" + process $proc$ls180.v:6670$2250 + assign { } { } + assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 + attribute \src "ls180.v:6672.2-6685.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine3_cmd_payload_a + end + sync always + update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] + end + attribute \src "ls180.v:6687.1-6703.4" + process $proc$ls180.v:6687$2251 + assign { } { } + assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 + attribute \src "ls180.v:6689.2-6702.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine3_cmd_payload_ba + end + sync always + update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] + end + attribute \src "ls180.v:670.11-670.68" + process $proc$ls180.v:670$3023 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:6704.1-6720.4" + process $proc$ls180.v:6704$2252 + assign { } { } + assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 + attribute \src "ls180.v:6706.2-6719.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine3_cmd_payload_is_read + end + sync always + update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] + end + attribute \src "ls180.v:671.5-671.64" + process $proc$ls180.v:671$3024 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:672.11-672.70" + process $proc$ls180.v:672$3025 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:6721.1-6737.4" + process $proc$ls180.v:6721$2253 + assign { } { } + assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 + attribute \src "ls180.v:6723.2-6736.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine3_cmd_payload_is_write + end + sync always + update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] + end + attribute \src "ls180.v:673.11-673.70" + process $proc$ls180.v:673$3026 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:6738.1-6754.4" + process $proc$ls180.v:6738$2254 + assign { } { } + assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 + attribute \src "ls180.v:6740.2-6753.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd + end + sync always + update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] + end + attribute \src "ls180.v:674.11-674.73" + process $proc$ls180.v:674$3027 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:6755.1-6771.4" + process $proc$ls180.v:6755$2255 + assign { } { } + assign $0\builder_comb_t_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:6757.2-6770.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_cas + end + sync always + update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] + end + attribute \src "ls180.v:6772.1-6788.4" + process $proc$ls180.v:6772$2256 + assign { } { } + assign $0\builder_comb_t_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:6774.2-6787.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_ras + end + sync always + update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] + end + attribute \src "ls180.v:6789.1-6805.4" + process $proc$ls180.v:6789$2257 + assign { } { } + assign $0\builder_comb_t_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:6791.2-6804.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_we + end + sync always + update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] + end + attribute \src "ls180.v:6806.1-6813.4" + process $proc$ls180.v:6806$2258 + assign { } { } + assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:6808.2-6812.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed12[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] + end + attribute \src "ls180.v:6814.1-6821.4" + process $proc$ls180.v:6814$2259 + assign { } { } + assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 + attribute \src "ls180.v:6816.2-6820.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed13[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] + end + attribute \src "ls180.v:6822.1-6829.4" + process $proc$ls180.v:6822$2260 + assign { } { } + assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 + attribute \src "ls180.v:6824.2-6828.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6826$2273_Y + end + sync always + update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] + end + attribute \src "ls180.v:6830.1-6837.4" + process $proc$ls180.v:6830$2274 + assign { } { } + assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:6832.2-6836.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed15[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] + end + attribute \src "ls180.v:6838.1-6845.4" + process $proc$ls180.v:6838$2275 + assign { } { } + assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 + attribute \src "ls180.v:6840.2-6844.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed16[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] + end + attribute \src "ls180.v:6846.1-6853.4" + process $proc$ls180.v:6846$2276 + assign { } { } + assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 + attribute \src "ls180.v:6848.2-6852.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6850$2289_Y + end + sync always + update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] + end + attribute \src "ls180.v:6854.1-6861.4" + process $proc$ls180.v:6854$2290 + assign { } { } + assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:6856.2-6860.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed18[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] + end + attribute \src "ls180.v:6862.1-6869.4" + process $proc$ls180.v:6862$2291 + assign { } { } + assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 + attribute \src "ls180.v:6864.2-6868.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed19[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] + end + attribute \src "ls180.v:6870.1-6877.4" + process $proc$ls180.v:6870$2292 + assign { } { } + assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 + attribute \src "ls180.v:6872.2-6876.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6874$2305_Y + end + sync always + update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] + end + attribute \src "ls180.v:6878.1-6885.4" + process $proc$ls180.v:6878$2306 + assign { } { } + assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:6880.2-6884.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed21[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] + end + attribute \src "ls180.v:6886.1-6893.4" + process $proc$ls180.v:6886$2307 + assign { } { } + assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 + attribute \src "ls180.v:6888.2-6892.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed22[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] + end + attribute \src "ls180.v:6894.1-6901.4" + process $proc$ls180.v:6894$2308 + assign { } { } + assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 + attribute \src "ls180.v:6896.2-6900.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:6898$2321_Y + end + sync always + update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] + end + attribute \src "ls180.v:6902.1-6921.4" + process $proc$ls180.v:6902$2322 + assign { } { } + assign $0\builder_comb_rhs_array_muxed24[31:0] 0 + attribute \src "ls180.v:6904.2-6920.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface0_converted_interface_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface1_converted_interface_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface2_converted_interface_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface0_bus_adr + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface1_bus_adr + end + sync always + update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] + end + attribute \src "ls180.v:6922.1-6941.4" + process $proc$ls180.v:6922$2323 + assign { } { } + assign $0\builder_comb_rhs_array_muxed25[31:0] 0 + attribute \src "ls180.v:6924.2-6940.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface0_converted_interface_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface1_converted_interface_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface2_converted_interface_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface0_bus_dat_w + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface1_bus_dat_w + end + sync always + update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[31:0] + end + attribute \src "ls180.v:6942.1-6961.4" + process $proc$ls180.v:6942$2324 + assign { } { } + assign $0\builder_comb_rhs_array_muxed26[3:0] 4'0000 + attribute \src "ls180.v:6944.2-6960.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface0_converted_interface_sel + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface1_converted_interface_sel + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface2_converted_interface_sel + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface0_bus_sel + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface1_bus_sel + end + sync always + update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[3:0] + end + attribute \src "ls180.v:695.5-695.59" + process $proc$ls180.v:695$3028 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:6962.1-6981.4" + process $proc$ls180.v:6962$2325 + assign { } { } + assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 + attribute \src "ls180.v:6964.2-6980.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface0_converted_interface_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface1_converted_interface_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface2_converted_interface_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface0_bus_cyc + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface1_bus_cyc + end + sync always + update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] + end + attribute \src "ls180.v:697.5-697.59" + process $proc$ls180.v:697$3029 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:698.5-698.58" + process $proc$ls180.v:698$3030 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:6982.1-7001.4" + process $proc$ls180.v:6982$2326 + assign { } { } + assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 + attribute \src "ls180.v:6984.2-7000.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface0_converted_interface_stb + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface1_converted_interface_stb + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface2_converted_interface_stb + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface0_bus_stb + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface1_bus_stb + end + sync always + update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] + end + attribute \src "ls180.v:699.5-699.64" + process $proc$ls180.v:699$3031 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:700.12-700.74" + process $proc$ls180.v:700$3032 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:7002.1-7021.4" + process $proc$ls180.v:7002$2327 + assign { } { } + assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 + attribute \src "ls180.v:7004.2-7020.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface0_converted_interface_we + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface1_converted_interface_we + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface2_converted_interface_we + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface0_bus_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface1_bus_we + end + sync always + update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] + end + attribute \src "ls180.v:701.12-701.47" + process $proc$ls180.v:701$3033 + assign { } { } + assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] + end + attribute \src "ls180.v:702.5-702.46" + process $proc$ls180.v:702$3034 + assign { } { } + assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] + end + attribute \src "ls180.v:7022.1-7041.4" + process $proc$ls180.v:7022$2328 + assign { } { } + assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 + attribute \src "ls180.v:7024.2-7040.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface0_converted_interface_cti + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface1_converted_interface_cti + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface2_converted_interface_cti + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface0_bus_cti + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface1_bus_cti + end + sync always + update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] + end + attribute \src "ls180.v:704.5-704.44" + process $proc$ls180.v:704$3035 + assign { } { } + assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] + end + attribute \src "ls180.v:7042.1-7061.4" + process $proc$ls180.v:7042$2329 + assign { } { } + assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 + attribute \src "ls180.v:7044.2-7060.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface0_converted_interface_bte + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface1_converted_interface_bte + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface2_converted_interface_bte + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface0_bus_bte + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface1_bus_bte + end + sync always + update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] + end + attribute \src "ls180.v:705.5-705.45" + process $proc$ls180.v:705$3036 + assign { } { } + assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] + end + attribute \src "ls180.v:706.5-706.54" + process $proc$ls180.v:706$3037 + assign { } { } + assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:7062.1-7078.4" + process $proc$ls180.v:7062$2330 + assign { } { } + assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 + attribute \src "ls180.v:7064.2-7077.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_nop_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_cmd_payload_ba + end + sync always + update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] + end + attribute \src "ls180.v:7079.1-7095.4" + process $proc$ls180.v:7079$2331 + assign { } { } + assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 + attribute \src "ls180.v:7081.2-7094.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_nop_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_cmd_payload_a + end + sync always + update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:708.32-708.76" + process $proc$ls180.v:708$3038 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] + end + attribute \src "ls180.v:709.11-709.55" + process $proc$ls180.v:709$3039 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] + end + attribute \src "ls180.v:7096.1-7112.4" + process $proc$ls180.v:7096$2332 + assign { } { } + assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:7098.2-7111.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7103$2334_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7106$2336_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7109$2338_Y + end + sync always + update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] + end + attribute \src "ls180.v:711.32-711.75" + process $proc$ls180.v:711$3040 + assign { } { } + assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:7113.1-7129.4" + process $proc$ls180.v:7113$2339 + assign { } { } + assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:7115.2-7128.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7120$2341_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7123$2343_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7126$2345_Y + end + sync always + update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:713.32-713.76" + process $proc$ls180.v:713$3041 + assign { } { } + assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:7130.1-7146.4" + process $proc$ls180.v:7130$2346 + assign { } { } + assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:7132.2-7145.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7137$2348_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7140$2350_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7143$2352_Y + end + sync always + update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:7147.1-7163.4" + process $proc$ls180.v:7147$2353 + assign { } { } + assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:7149.2-7162.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7154$2355_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7157$2357_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7160$2359_Y + end + sync always + update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:716.5-716.44" + process $proc$ls180.v:716$3042 + assign { } { } + assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] + sync init + end + attribute \src "ls180.v:7164.1-7180.4" + process $proc$ls180.v:7164$2360 + assign { } { } + assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:7166.2-7179.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7171$2362_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7174$2364_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7177$2366_Y + end + sync always + update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:717.5-717.45" + process $proc$ls180.v:717$3043 + assign { } { } + assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] + sync init + end + attribute \src "ls180.v:718.5-718.43" + process $proc$ls180.v:718$3044 + assign { } { } + assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] + sync init + end + attribute \src "ls180.v:7181.1-7209.4" + process $proc$ls180.v:7181$2367 + assign { } { } + assign $0\builder_sync_f_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:7183.2-7208.9" + switch \main_spi_master_mosi_sel + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [0] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [1] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [2] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [3] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [4] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [5] + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [6] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [7] + end + sync always + update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] + end + attribute \src "ls180.v:719.5-719.48" + process $proc$ls180.v:719$3045 + assign { } { } + assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] + sync init + end + attribute \src "ls180.v:72.5-72.46" + process $proc$ls180.v:72$2781 + assign { } { } + assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0] + end + attribute \src "ls180.v:721.5-721.43" + process $proc$ls180.v:721$3046 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] + sync init + end + attribute \src "ls180.v:7210.1-7238.4" + process $proc$ls180.v:7210$2368 + assign { } { } + assign $0\builder_sync_f_array_muxed1[0:0] 1'0 + attribute \src "ls180.v:7212.2-7237.9" + switch \libresocsim_mosi_sel + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [0] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [1] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [2] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [3] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [4] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [5] + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [6] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [7] + end + sync always + update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] + end + attribute \src "ls180.v:724.5-724.49" + process $proc$ls180.v:724$3047 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:725.5-725.49" + process $proc$ls180.v:725$3048 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:726.5-726.48" + process $proc$ls180.v:726$3049 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] + end + attribute \src "ls180.v:7296.1-7314.4" + process $proc$ls180.v:7296$2369 + assign { } { } + assign { } { } + assign $0\main_gpio_status[15:0] [0] \builder_multiregimpl1_regs1 + assign $0\main_gpio_status[15:0] [1] \builder_multiregimpl2_regs1 + assign $0\main_gpio_status[15:0] [2] \builder_multiregimpl3_regs1 + assign $0\main_gpio_status[15:0] [3] \builder_multiregimpl4_regs1 + assign $0\main_gpio_status[15:0] [4] \builder_multiregimpl5_regs1 + assign $0\main_gpio_status[15:0] [5] \builder_multiregimpl6_regs1 + assign $0\main_gpio_status[15:0] [6] \builder_multiregimpl7_regs1 + assign $0\main_gpio_status[15:0] [7] \builder_multiregimpl8_regs1 + assign $0\main_gpio_status[15:0] [8] \builder_multiregimpl9_regs1 + assign $0\main_gpio_status[15:0] [9] \builder_multiregimpl10_regs1 + assign $0\main_gpio_status[15:0] [10] \builder_multiregimpl11_regs1 + assign $0\main_gpio_status[15:0] [11] \builder_multiregimpl12_regs1 + assign $0\main_gpio_status[15:0] [12] \builder_multiregimpl13_regs1 + assign $0\main_gpio_status[15:0] [13] \builder_multiregimpl14_regs1 + assign $0\main_gpio_status[15:0] [14] \builder_multiregimpl15_regs1 + assign $0\main_gpio_status[15:0] [15] \builder_multiregimpl16_regs1 + sync always + update \main_gpio_status $0\main_gpio_status[15:0] + end + attribute \src "ls180.v:730.11-730.46" + process $proc$ls180.v:730$3050 + assign { } { } + assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 + sync always + sync init + update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] + end + attribute \src "ls180.v:732.11-732.45" + process $proc$ls180.v:732$3051 + assign { } { } + assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 + sync always + sync init + update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] + end + attribute \src "ls180.v:7335.1-7337.4" + process $proc$ls180.v:7335$2370 + assign { } { } + assign $0\main_int_rst[0:0] \sys_rst + sync posedge \por_clk + update \main_int_rst $0\main_int_rst[0:0] + end + attribute \src "ls180.v:7339.1-7409.4" + process $proc$ls180.v:7339$2371 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sdram_a[12:0] [0] \main_dfi_p0_address [0] + assign $0\sdram_a[12:0] [1] \main_dfi_p0_address [1] + assign $0\sdram_a[12:0] [2] \main_dfi_p0_address [2] + assign $0\sdram_a[12:0] [3] \main_dfi_p0_address [3] + assign $0\sdram_a[12:0] [4] \main_dfi_p0_address [4] + assign $0\sdram_a[12:0] [5] \main_dfi_p0_address [5] + assign $0\sdram_a[12:0] [6] \main_dfi_p0_address [6] + assign $0\sdram_a[12:0] [7] \main_dfi_p0_address [7] + assign $0\sdram_a[12:0] [8] \main_dfi_p0_address [8] + assign $0\sdram_a[12:0] [9] \main_dfi_p0_address [9] + assign $0\sdram_a[12:0] [10] \main_dfi_p0_address [10] + assign $0\sdram_a[12:0] [11] \main_dfi_p0_address [11] + assign $0\sdram_a[12:0] [12] \main_dfi_p0_address [12] + assign $0\sdram_ba[1:0] [0] \main_dfi_p0_bank [0] + assign $0\sdram_ba[1:0] [1] \main_dfi_p0_bank [1] + assign $0\sdram_cas_n[0:0] \main_dfi_p0_cas_n + assign $0\sdram_ras_n[0:0] \main_dfi_p0_ras_n + assign $0\sdram_we_n[0:0] \main_dfi_p0_we_n + assign $0\sdram_cke[0:0] \main_dfi_p0_cke + assign $0\sdram_cs_n[0:0] \main_dfi_p0_cs_n + assign $0\sdram_dq_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\sdram_dq_o[15:0] [0] \main_dfi_p0_wrdata [0] + assign $0\main_dfi_p0_rddata[15:0] [0] \sdram_dq_i [0] + assign $0\sdram_dq_o[15:0] [1] \main_dfi_p0_wrdata [1] + assign $0\main_dfi_p0_rddata[15:0] [1] \sdram_dq_i [1] + assign $0\sdram_dq_o[15:0] [2] \main_dfi_p0_wrdata [2] + assign $0\main_dfi_p0_rddata[15:0] [2] \sdram_dq_i [2] + assign $0\sdram_dq_o[15:0] [3] \main_dfi_p0_wrdata [3] + assign $0\main_dfi_p0_rddata[15:0] [3] \sdram_dq_i [3] + assign $0\sdram_dq_o[15:0] [4] \main_dfi_p0_wrdata [4] + assign $0\main_dfi_p0_rddata[15:0] [4] \sdram_dq_i [4] + assign $0\sdram_dq_o[15:0] [5] \main_dfi_p0_wrdata [5] + assign $0\main_dfi_p0_rddata[15:0] [5] \sdram_dq_i [5] + assign $0\sdram_dq_o[15:0] [6] \main_dfi_p0_wrdata [6] + assign $0\main_dfi_p0_rddata[15:0] [6] \sdram_dq_i [6] + assign $0\sdram_dq_o[15:0] [7] \main_dfi_p0_wrdata [7] + assign $0\main_dfi_p0_rddata[15:0] [7] \sdram_dq_i [7] + assign $0\sdram_dq_o[15:0] [8] \main_dfi_p0_wrdata [8] + assign $0\main_dfi_p0_rddata[15:0] [8] \sdram_dq_i [8] + assign $0\sdram_dq_o[15:0] [9] \main_dfi_p0_wrdata [9] + assign $0\main_dfi_p0_rddata[15:0] [9] \sdram_dq_i [9] + assign $0\sdram_dq_o[15:0] [10] \main_dfi_p0_wrdata [10] + assign $0\main_dfi_p0_rddata[15:0] [10] \sdram_dq_i [10] + assign $0\sdram_dq_o[15:0] [11] \main_dfi_p0_wrdata [11] + assign $0\main_dfi_p0_rddata[15:0] [11] \sdram_dq_i [11] + assign $0\sdram_dq_o[15:0] [12] \main_dfi_p0_wrdata [12] + assign $0\main_dfi_p0_rddata[15:0] [12] \sdram_dq_i [12] + assign $0\sdram_dq_o[15:0] [13] \main_dfi_p0_wrdata [13] + assign $0\main_dfi_p0_rddata[15:0] [13] \sdram_dq_i [13] + assign $0\sdram_dq_o[15:0] [14] \main_dfi_p0_wrdata [14] + assign $0\main_dfi_p0_rddata[15:0] [14] \sdram_dq_i [14] + assign $0\sdram_dq_o[15:0] [15] \main_dfi_p0_wrdata [15] + assign $0\main_dfi_p0_rddata[15:0] [15] \sdram_dq_i [15] + assign $0\sdram_dm[1:0] [0] \main_dfi_p0_wrdata_mask [0] + assign $0\sdram_dm[1:0] [1] \main_dfi_p0_wrdata_mask [1] + assign $0\sdram_clock[0:0] \sys_clk_1 + assign $0\sdcard_clk[0:0] $and$ls180.v:7396$2373_Y + assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe + assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o + assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i + assign $0\sdcard_data_oe[0:0] \main_sdphy_sdpads_data_oe + assign $0\sdcard_data_o[3:0] [0] \main_sdphy_sdpads_data_o [0] + assign $0\main_sdphy_sdpads_data_i[3:0] [0] \sdcard_data_i [0] + assign $0\sdcard_data_o[3:0] [1] \main_sdphy_sdpads_data_o [1] + assign $0\main_sdphy_sdpads_data_i[3:0] [1] \sdcard_data_i [1] + assign $0\sdcard_data_o[3:0] [2] \main_sdphy_sdpads_data_o [2] + assign $0\main_sdphy_sdpads_data_i[3:0] [2] \sdcard_data_i [2] + assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3] + assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3] + sync posedge \sdrio_clk + update \sdram_a $0\sdram_a[12:0] + update \sdram_dq_o $0\sdram_dq_o[15:0] + update \sdram_dq_oe $0\sdram_dq_oe[0:0] + update \sdram_we_n $0\sdram_we_n[0:0] + update \sdram_ras_n $0\sdram_ras_n[0:0] + update \sdram_cas_n $0\sdram_cas_n[0:0] + update \sdram_cs_n $0\sdram_cs_n[0:0] + update \sdram_cke $0\sdram_cke[0:0] + update \sdram_ba $0\sdram_ba[1:0] + update \sdram_dm $0\sdram_dm[1:0] + update \sdram_clock $0\sdram_clock[0:0] + update \sdcard_clk $0\sdcard_clk[0:0] + update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] + update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] + update \sdcard_data_o $0\sdcard_data_o[3:0] + update \sdcard_data_oe $0\sdcard_data_oe[0:0] + update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] + update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] + update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] + end + attribute \src "ls180.v:734.5-734.44" + process $proc$ls180.v:734$3052 + assign { } { } + assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] + end + attribute \src "ls180.v:735.5-735.45" + process $proc$ls180.v:735$3053 + assign { } { } + assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] + end + attribute \src "ls180.v:737.5-737.48" + process $proc$ls180.v:737$3054 + assign { } { } + assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] + end + attribute \src "ls180.v:739.5-739.43" + process $proc$ls180.v:739$3055 + assign { } { } + assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] + end + attribute \src "ls180.v:7411.1-10036.4" + process $proc$ls180.v:7411$2374 + assign $0\spi_master_clk[0:0] \spi_master_clk + assign $0\spi_master_mosi[0:0] \spi_master_mosi + assign { } { } + assign $0\pwm0[0:0] \pwm0 + assign $0\pwm1[0:0] \pwm1 + assign $0\spisdcard_clk[0:0] \spisdcard_clk + assign $0\spisdcard_mosi[0:0] \spisdcard_mosi + assign { } { } + assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage + assign { } { } + assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage + assign { } { } + assign $0\main_libresocsim_bus_errors[31:0] \main_libresocsim_bus_errors + assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] \main_libresocsim_libresoc_constraintmanager0_uart0_tx + assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter + assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_converter0_dat_r + assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter + assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_converter1_dat_r + assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter + assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_converter2_dat_r + assign { } { } + assign $0\main_libresocsim_load_storage[31:0] \main_libresocsim_load_storage + assign { } { } + assign $0\main_libresocsim_reload_storage[31:0] \main_libresocsim_reload_storage + assign { } { } + assign $0\main_libresocsim_en_storage[0:0] \main_libresocsim_en_storage + assign { } { } + assign $0\main_libresocsim_update_value_storage[0:0] \main_libresocsim_update_value_storage + assign { } { } + assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value_status + assign $0\main_libresocsim_zero_pending[0:0] \main_libresocsim_zero_pending + assign { } { } + assign $0\main_libresocsim_eventmanager_storage[0:0] \main_libresocsim_eventmanager_storage + assign { } { } + assign $0\main_libresocsim_value[31:0] \main_libresocsim_value + assign { } { } + assign { } { } + assign $0\main_sdram_storage[3:0] \main_sdram_storage + assign { } { } + assign $0\main_sdram_command_storage[5:0] \main_sdram_command_storage + assign { } { } + assign $0\main_sdram_address_storage[12:0] \main_sdram_address_storage + assign { } { } + assign $0\main_sdram_baddress_storage[1:0] \main_sdram_baddress_storage + assign { } { } + assign $0\main_sdram_wrdata_storage[15:0] \main_sdram_wrdata_storage + assign { } { } + assign $0\main_sdram_status[15:0] \main_sdram_status + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_timer_count1[9:0] \main_sdram_timer_count1 + assign { } { } + assign $0\main_sdram_postponer_count[0:0] \main_sdram_postponer_count + assign { } { } + assign $0\main_sdram_sequencer_counter[3:0] \main_sdram_sequencer_counter + assign $0\main_sdram_sequencer_count[0:0] \main_sdram_sequencer_count + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_source_first + assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_source_last + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_row + assign $0\main_sdram_bankmachine0_row_opened[0:0] \main_sdram_bankmachine0_row_opened + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] \main_sdram_bankmachine0_twtpcon_ready + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] \main_sdram_bankmachine0_twtpcon_count + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_source_first + assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_source_last + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_row + assign $0\main_sdram_bankmachine1_row_opened[0:0] \main_sdram_bankmachine1_row_opened + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] \main_sdram_bankmachine1_twtpcon_ready + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] \main_sdram_bankmachine1_twtpcon_count + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_source_first + assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_source_last + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_row + assign $0\main_sdram_bankmachine2_row_opened[0:0] \main_sdram_bankmachine2_row_opened + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] \main_sdram_bankmachine2_twtpcon_ready + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] \main_sdram_bankmachine2_twtpcon_count + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_source_first + assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_source_last + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_row + assign $0\main_sdram_bankmachine3_row_opened[0:0] \main_sdram_bankmachine3_row_opened + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] \main_sdram_bankmachine3_twtpcon_ready + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] \main_sdram_bankmachine3_twtpcon_count + assign $0\main_sdram_choose_cmd_grant[1:0] \main_sdram_choose_cmd_grant + assign $0\main_sdram_choose_req_grant[1:0] \main_sdram_choose_req_grant + assign $0\main_sdram_tccdcon_ready[0:0] \main_sdram_tccdcon_ready + assign $0\main_sdram_tccdcon_count[0:0] \main_sdram_tccdcon_count + assign $0\main_sdram_twtrcon_ready[0:0] \main_sdram_twtrcon_ready + assign $0\main_sdram_twtrcon_count[2:0] \main_sdram_twtrcon_count + assign $0\main_sdram_time0[4:0] \main_sdram_time0 + assign $0\main_sdram_time1[3:0] \main_sdram_time1 + assign $0\main_converter_counter[0:0] \main_converter_counter + assign $0\main_converter_dat_r[31:0] \main_converter_dat_r + assign $0\main_cmd_consumed[0:0] \main_cmd_consumed + assign $0\main_wdata_consumed[0:0] \main_wdata_consumed + assign $0\main_uart_phy_storage[31:0] \main_uart_phy_storage + assign { } { } + assign { } { } + assign $0\main_uart_phy_uart_clk_txen[0:0] \main_uart_phy_uart_clk_txen + assign $0\main_uart_phy_phase_accumulator_tx[31:0] \main_uart_phy_phase_accumulator_tx + assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_tx_reg + assign $0\main_uart_phy_tx_bitcount[3:0] \main_uart_phy_tx_bitcount + assign $0\main_uart_phy_tx_busy[0:0] \main_uart_phy_tx_busy + assign { } { } + assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_source_payload_data + assign $0\main_uart_phy_uart_clk_rxen[0:0] \main_uart_phy_uart_clk_rxen + assign $0\main_uart_phy_phase_accumulator_rx[31:0] \main_uart_phy_phase_accumulator_rx + assign { } { } + assign $0\main_uart_phy_rx_reg[7:0] \main_uart_phy_rx_reg + assign $0\main_uart_phy_rx_bitcount[3:0] \main_uart_phy_rx_bitcount + assign $0\main_uart_phy_rx_busy[0:0] \main_uart_phy_rx_busy + assign $0\main_uart_tx_pending[0:0] \main_uart_tx_pending + assign { } { } + assign $0\main_uart_rx_pending[0:0] \main_uart_rx_pending + assign { } { } + assign $0\main_uart_eventmanager_storage[1:0] \main_uart_eventmanager_storage + assign { } { } + assign $0\main_uart_tx_fifo_readable[0:0] \main_uart_tx_fifo_readable + assign $0\main_uart_tx_fifo_level0[4:0] \main_uart_tx_fifo_level0 + assign $0\main_uart_tx_fifo_produce[3:0] \main_uart_tx_fifo_produce + assign $0\main_uart_tx_fifo_consume[3:0] \main_uart_tx_fifo_consume + assign $0\main_uart_rx_fifo_readable[0:0] \main_uart_rx_fifo_readable + assign $0\main_uart_rx_fifo_level0[4:0] \main_uart_rx_fifo_level0 + assign $0\main_uart_rx_fifo_produce[3:0] \main_uart_rx_fifo_produce + assign $0\main_uart_rx_fifo_consume[3:0] \main_uart_rx_fifo_consume + assign $0\main_gpio_oe_storage[15:0] \main_gpio_oe_storage + assign { } { } + assign $0\main_gpio_out_storage[15:0] \main_gpio_out_storage + assign { } { } + assign $0\main_spi_master_miso[7:0] \main_spi_master_miso + assign $0\main_spi_master_control_storage[15:0] \main_spi_master_control_storage + assign { } { } + assign $0\main_spi_master_mosi_storage[7:0] \main_spi_master_mosi_storage + assign { } { } + assign $0\main_spi_master_cs_storage[0:0] \main_spi_master_cs_storage + assign { } { } + assign $0\main_spi_master_loopback_storage[0:0] \main_spi_master_loopback_storage + assign { } { } + assign $0\main_spi_master_count[2:0] \main_spi_master_count + assign { } { } + assign $0\main_spi_master_mosi_data[7:0] \main_spi_master_mosi_data + assign $0\main_spi_master_mosi_sel[2:0] \main_spi_master_mosi_sel + assign $0\main_spi_master_miso_data[7:0] \main_spi_master_miso_data + assign { } { } + assign $0\main_pwm0_counter[31:0] \main_pwm0_counter + assign $0\main_pwm0_enable_storage[0:0] \main_pwm0_enable_storage + assign { } { } + assign $0\main_pwm0_width_storage[31:0] \main_pwm0_width_storage + assign { } { } + assign $0\main_pwm0_period_storage[31:0] \main_pwm0_period_storage + assign { } { } + assign $0\main_pwm1_counter[31:0] \main_pwm1_counter + assign $0\main_pwm1_enable_storage[0:0] \main_pwm1_enable_storage + assign { } { } + assign $0\main_pwm1_width_storage[31:0] \main_pwm1_width_storage + assign { } { } + assign $0\main_pwm1_period_storage[31:0] \main_pwm1_period_storage + assign { } { } + assign $0\main_i2c_storage[2:0] \main_i2c_storage + assign { } { } + assign $0\main_sdphy_clocker_storage[8:0] \main_sdphy_clocker_storage + assign { } { } + assign { } { } + assign $0\main_sdphy_clocker_clks[8:0] \main_sdphy_clocker_clks + assign { } { } + assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count + assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count + assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout + assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count + assign $0\main_sdphy_cmdr_cmdr_run[0:0] \main_sdphy_cmdr_cmdr_run + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_source_first + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_source_last + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_converter_source_payload_data + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] \main_sdphy_cmdr_cmdr_converter_demux + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] \main_sdphy_cmdr_cmdr_converter_strobe_all + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_source_valid + assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_source_first + assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_source_last + assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_source_payload_data + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset + assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count + assign $0\main_sdphy_dataw_crcr_run[0:0] \main_sdphy_dataw_crcr_run + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_source_first + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_source_last + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] \main_sdphy_dataw_crcr_converter_source_payload_data + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] \main_sdphy_dataw_crcr_converter_demux + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] \main_sdphy_dataw_crcr_converter_strobe_all + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_source_valid + assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_source_first + assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_source_last + assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_source_payload_data + assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset + assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout + assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count + assign $0\main_sdphy_datar_datar_run[0:0] \main_sdphy_datar_datar_run + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_source_first + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_source_last + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] \main_sdphy_datar_datar_converter_source_payload_data + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] \main_sdphy_datar_datar_converter_source_payload_valid_token_count + assign $0\main_sdphy_datar_datar_converter_demux[0:0] \main_sdphy_datar_datar_converter_demux + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] \main_sdphy_datar_datar_converter_strobe_all + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_source_valid + assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_source_first + assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_source_last + assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_source_payload_data + assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset + assign $0\main_sdcore_cmd_argument_storage[31:0] \main_sdcore_cmd_argument_storage + assign { } { } + assign $0\main_sdcore_cmd_command_storage[31:0] \main_sdcore_cmd_command_storage + assign { } { } + assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status + assign $0\main_sdcore_block_length_storage[9:0] \main_sdcore_block_length_storage + assign { } { } + assign $0\main_sdcore_block_count_storage[31:0] \main_sdcore_block_count_storage + assign { } { } + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg0 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3 + assign $0\main_sdcore_crc16_checker_val[7:0] \main_sdcore_crc16_checker_val + assign $0\main_sdcore_crc16_checker_cnt[3:0] \main_sdcore_crc16_checker_cnt + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crctmp0 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crctmp1 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crctmp2 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crctmp3 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] \main_sdcore_crc16_checker_fifo0 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] \main_sdcore_crc16_checker_fifo1 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] \main_sdcore_crc16_checker_fifo2 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] \main_sdcore_crc16_checker_fifo3 + assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count + assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done + assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error + assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout + assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count + assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done + assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error + assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout + assign $0\main_sdblock2mem_fifo_level[5:0] \main_sdblock2mem_fifo_level + assign $0\main_sdblock2mem_fifo_produce[4:0] \main_sdblock2mem_fifo_produce + assign $0\main_sdblock2mem_fifo_consume[4:0] \main_sdblock2mem_fifo_consume + assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_source_first + assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_source_last + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] \main_sdblock2mem_converter_source_payload_data + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] \main_sdblock2mem_converter_source_payload_valid_token_count + assign $0\main_sdblock2mem_converter_demux[1:0] \main_sdblock2mem_converter_demux + assign $0\main_sdblock2mem_converter_strobe_all[0:0] \main_sdblock2mem_converter_strobe_all + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] \main_sdblock2mem_wishbonedmawriter_base_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] \main_sdblock2mem_wishbonedmawriter_length_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \main_sdblock2mem_wishbonedmawriter_enable_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \main_sdblock2mem_wishbonedmawriter_loop_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset + assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data + assign $0\main_sdmem2block_dma_base_storage[63:0] \main_sdmem2block_dma_base_storage + assign { } { } + assign $0\main_sdmem2block_dma_length_storage[31:0] \main_sdmem2block_dma_length_storage + assign { } { } + assign $0\main_sdmem2block_dma_enable_storage[0:0] \main_sdmem2block_dma_enable_storage + assign { } { } + assign $0\main_sdmem2block_dma_loop_storage[0:0] \main_sdmem2block_dma_loop_storage + assign { } { } + assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset + assign $0\main_sdmem2block_converter_mux[1:0] \main_sdmem2block_converter_mux + assign $0\main_sdmem2block_fifo_level[5:0] \main_sdmem2block_fifo_level + assign $0\main_sdmem2block_fifo_produce[4:0] \main_sdmem2block_fifo_produce + assign $0\main_sdmem2block_fifo_consume[4:0] \main_sdmem2block_fifo_consume + assign $0\libresocsim_miso[7:0] \libresocsim_miso + assign $0\libresocsim_control_storage[15:0] \libresocsim_control_storage + assign { } { } + assign $0\libresocsim_mosi_storage[7:0] \libresocsim_mosi_storage + assign { } { } + assign $0\libresocsim_cs_storage[0:0] \libresocsim_cs_storage + assign { } { } + assign $0\libresocsim_loopback_storage[0:0] \libresocsim_loopback_storage + assign { } { } + assign $0\libresocsim_count[2:0] \libresocsim_count + assign { } { } + assign $0\libresocsim_mosi_data[7:0] \libresocsim_mosi_data + assign $0\libresocsim_mosi_sel[2:0] \libresocsim_mosi_sel + assign $0\libresocsim_miso_data[7:0] \libresocsim_miso_data + assign $0\libresocsim_storage[15:0] \libresocsim_storage + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr + assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we + assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w + assign $0\builder_grant[2:0] \builder_grant + assign { } { } + assign $0\builder_count[19:0] \builder_count + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_dummy[35:0] [0] $or$ls180.v:7412$2375_Y + assign $0\main_dummy[35:0] [1] $or$ls180.v:7413$2376_Y + assign $0\main_dummy[35:0] [2] $or$ls180.v:7414$2377_Y + assign $0\main_dummy[35:0] [3] $or$ls180.v:7415$2378_Y + assign $0\main_dummy[35:0] [4] $or$ls180.v:7416$2379_Y + assign $0\main_dummy[35:0] [5] $or$ls180.v:7417$2380_Y + assign $0\main_dummy[35:0] [6] $or$ls180.v:7418$2381_Y + assign $0\main_dummy[35:0] [7] $or$ls180.v:7419$2382_Y + assign $0\main_dummy[35:0] [8] $or$ls180.v:7420$2383_Y + assign $0\main_dummy[35:0] [9] $or$ls180.v:7421$2384_Y + assign $0\main_dummy[35:0] [10] $or$ls180.v:7422$2385_Y + assign $0\main_dummy[35:0] [11] $or$ls180.v:7423$2386_Y + assign $0\main_dummy[35:0] [12] $or$ls180.v:7424$2387_Y + assign $0\main_dummy[35:0] [13] $or$ls180.v:7425$2388_Y + assign $0\main_dummy[35:0] [14] $or$ls180.v:7426$2389_Y + assign $0\main_dummy[35:0] [15] $or$ls180.v:7427$2390_Y + assign $0\main_dummy[35:0] [16] $or$ls180.v:7428$2391_Y + assign $0\main_dummy[35:0] [17] $or$ls180.v:7429$2392_Y + assign $0\main_dummy[35:0] [18] $or$ls180.v:7430$2393_Y + assign $0\main_dummy[35:0] [19] $or$ls180.v:7431$2394_Y + assign $0\main_dummy[35:0] [20] $or$ls180.v:7432$2395_Y + assign $0\main_dummy[35:0] [21] $or$ls180.v:7433$2396_Y + assign $0\main_dummy[35:0] [22] $or$ls180.v:7434$2397_Y + assign $0\main_dummy[35:0] [23] $or$ls180.v:7435$2398_Y + assign $0\main_dummy[35:0] [24] $or$ls180.v:7436$2399_Y + assign $0\main_dummy[35:0] [25] $or$ls180.v:7437$2400_Y + assign $0\main_dummy[35:0] [26] $or$ls180.v:7438$2401_Y + assign $0\main_dummy[35:0] [27] $or$ls180.v:7439$2402_Y + assign $0\main_dummy[35:0] [28] $or$ls180.v:7440$2403_Y + assign $0\main_dummy[35:0] [29] $or$ls180.v:7441$2404_Y + assign $0\main_dummy[35:0] [30] $or$ls180.v:7442$2405_Y + assign $0\main_dummy[35:0] [31] $or$ls180.v:7443$2406_Y + assign $0\main_dummy[35:0] [32] $or$ls180.v:7444$2407_Y + assign $0\main_dummy[35:0] [33] $or$ls180.v:7445$2408_Y + assign $0\main_dummy[35:0] [34] $or$ls180.v:7446$2409_Y + assign $0\main_dummy[35:0] [35] $or$ls180.v:7447$2410_Y + assign $0\builder_converter0_state[0:0] \builder_converter0_next_state + assign $0\builder_converter1_state[0:0] \builder_converter1_next_state + assign $0\builder_converter2_state[0:0] \builder_converter2_next_state + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\main_libresocsim_zero_old_trigger[0:0] \main_libresocsim_zero_trigger + assign $0\main_rddata_en[2:0] { \main_rddata_en [1:0] \main_dfi_p0_rddata_en } + assign $0\main_dfi_p0_rddata_valid[0:0] \main_rddata_en [2] + assign $0\main_sdram_postponer_req_o[0:0] 1'0 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'0 + assign $0\builder_refresher_state[1:0] \builder_refresher_next_state + assign $0\builder_bankmachine0_state[2:0] \builder_bankmachine0_next_state + assign $0\builder_bankmachine1_state[2:0] \builder_bankmachine1_next_state + assign $0\builder_bankmachine2_state[2:0] \builder_bankmachine2_next_state + assign $0\builder_bankmachine3_state[2:0] \builder_bankmachine3_next_state + assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 + assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 + assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 + assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7889$2507_Y + assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7890$2508_Y + assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7891$2509_Y + assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 + assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 + assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state + assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:7925$2527_Y + assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:7926$2539_Y + assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 + assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 + assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 + assign $0\builder_converter_state[0:0] \builder_converter_next_state + assign $0\main_uart_phy_sink_ready[0:0] 1'0 + assign $0\main_uart_phy_source_valid[0:0] 1'0 + assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx + assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger + assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger + assign $0\main_spi_master_clk_divider1[15:0] $add$ls180.v:8084$2585_Y + assign $0\spi_master_cs_n[0:0] $or$ls180.v:8093$2588_Y + assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state + assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 + assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 + assign $0\builder_sdphy_sdphyinit_state[0:0] \builder_sdphy_sdphyinit_next_state + assign $0\builder_sdphy_sdphycmdw_state[1:0] \builder_sdphy_sdphycmdw_next_state + assign $0\builder_sdphy_sdphycmdr_state[2:0] \builder_sdphy_sdphycmdr_next_state + assign $0\builder_sdphy_sdphycrcr_state[0:0] \builder_sdphy_sdphycrcr_next_state + assign $0\builder_sdphy_fsm_state[2:0] \builder_sdphy_fsm_next_state + assign $0\builder_sdphy_sdphydatar_state[2:0] \builder_sdphy_sdphydatar_next_state + assign $0\builder_sdcore_crcupstreaminserter_state[0:0] \builder_sdcore_crcupstreaminserter_next_state + assign $0\builder_sdcore_fsm_state[2:0] \builder_sdcore_fsm_next_state + assign $0\builder_sdblock2memdma_state[1:0] \builder_sdblock2memdma_next_state + assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state + assign $0\libresocsim_clk_divider1[15:0] $add$ls180.v:8632$2680_Y + assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8641$2683_Y + assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state + assign $0\builder_state[1:0] \builder_next_state + assign $0\builder_slave_sel_r[4:0] \builder_slave_sel + assign $0\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_libresocsim_reset_re[0:0] \builder_csrbank0_reset0_re + assign $0\main_libresocsim_scratch_re[0:0] \builder_csrbank0_scratch0_re + assign $0\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_gpio_oe_re[0:0] \builder_csrbank1_oe0_re + assign $0\main_gpio_out_re[0:0] \builder_csrbank1_out0_re + assign $0\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_i2c_re[0:0] \builder_csrbank2_w0_re + assign $0\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_pwm0_enable_re[0:0] \builder_csrbank3_enable0_re + assign $0\main_pwm0_width_re[0:0] \builder_csrbank3_width0_re + assign $0\main_pwm0_period_re[0:0] \builder_csrbank3_period0_re + assign $0\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_pwm1_enable_re[0:0] \builder_csrbank4_enable0_re + assign $0\main_pwm1_width_re[0:0] \builder_csrbank4_width0_re + assign $0\main_pwm1_period_re[0:0] \builder_csrbank4_period0_re + assign $0\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] \builder_csrbank5_dma_base0_re + assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] \builder_csrbank5_dma_length0_re + assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] \builder_csrbank5_dma_enable0_re + assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] \builder_csrbank5_dma_loop0_re + assign $0\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdcore_cmd_argument_re[0:0] \builder_csrbank6_cmd_argument0_re + assign $0\main_sdcore_cmd_command_re[0:0] \builder_csrbank6_cmd_command0_re + assign $0\main_sdcore_block_length_re[0:0] \builder_csrbank6_block_length0_re + assign $0\main_sdcore_block_count_re[0:0] \builder_csrbank6_block_count0_re + assign $0\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdmem2block_dma_base_re[0:0] \builder_csrbank7_dma_base0_re + assign $0\main_sdmem2block_dma_length_re[0:0] \builder_csrbank7_dma_length0_re + assign $0\main_sdmem2block_dma_enable_re[0:0] \builder_csrbank7_dma_enable0_re + assign $0\main_sdmem2block_dma_loop_re[0:0] \builder_csrbank7_dma_loop0_re + assign $0\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdphy_clocker_re[0:0] \builder_csrbank8_clocker_divider0_re + assign $0\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdram_re[0:0] \builder_csrbank9_dfii_control0_re + assign $0\main_sdram_command_re[0:0] \builder_csrbank9_dfii_pi0_command0_re + assign $0\main_sdram_address_re[0:0] \builder_csrbank9_dfii_pi0_address0_re + assign $0\main_sdram_baddress_re[0:0] \builder_csrbank9_dfii_pi0_baddress0_re + assign $0\main_sdram_wrdata_re[0:0] \builder_csrbank9_dfii_pi0_wrdata0_re + assign $0\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_spi_master_control_re[0:0] \builder_csrbank10_control0_re + assign $0\main_spi_master_mosi_re[0:0] \builder_csrbank10_mosi0_re + assign $0\main_spi_master_cs_re[0:0] \builder_csrbank10_cs0_re + assign $0\main_spi_master_loopback_re[0:0] \builder_csrbank10_loopback0_re + assign $0\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + assign $0\libresocsim_control_re[0:0] \builder_csrbank11_control0_re + assign $0\libresocsim_mosi_re[0:0] \builder_csrbank11_mosi0_re + assign $0\libresocsim_cs_re[0:0] \builder_csrbank11_cs0_re + assign $0\libresocsim_loopback_re[0:0] \builder_csrbank11_loopback0_re + assign $0\libresocsim_re[0:0] \builder_csrbank11_clk_divider0_re + assign $0\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_libresocsim_load_re[0:0] \builder_csrbank12_load0_re + assign $0\main_libresocsim_reload_re[0:0] \builder_csrbank12_reload0_re + assign $0\main_libresocsim_en_re[0:0] \builder_csrbank12_en0_re + assign $0\main_libresocsim_update_value_re[0:0] \builder_csrbank12_update_value0_re + assign $0\main_libresocsim_eventmanager_re[0:0] \builder_csrbank12_ev_enable0_re + assign $0\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_uart_eventmanager_re[0:0] \builder_csrbank13_ev_enable0_re + assign $0\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_uart_phy_re[0:0] \builder_csrbank14_tuning_word0_re + assign $0\builder_multiregimpl0_regs0[0:0] \main_libresocsim_libresoc_constraintmanager0_uart0_rx + assign $0\builder_multiregimpl0_regs1[0:0] \builder_multiregimpl0_regs0 + assign $0\builder_multiregimpl1_regs0[0:0] \main_gpio_pads_i [0] + assign $0\builder_multiregimpl1_regs1[0:0] \builder_multiregimpl1_regs0 + assign $0\builder_multiregimpl2_regs0[0:0] \main_gpio_pads_i [1] + assign $0\builder_multiregimpl2_regs1[0:0] \builder_multiregimpl2_regs0 + assign $0\builder_multiregimpl3_regs0[0:0] \main_gpio_pads_i [2] + assign $0\builder_multiregimpl3_regs1[0:0] \builder_multiregimpl3_regs0 + assign $0\builder_multiregimpl4_regs0[0:0] \main_gpio_pads_i [3] + assign $0\builder_multiregimpl4_regs1[0:0] \builder_multiregimpl4_regs0 + assign $0\builder_multiregimpl5_regs0[0:0] \main_gpio_pads_i [4] + assign $0\builder_multiregimpl5_regs1[0:0] \builder_multiregimpl5_regs0 + assign $0\builder_multiregimpl6_regs0[0:0] \main_gpio_pads_i [5] + assign $0\builder_multiregimpl6_regs1[0:0] \builder_multiregimpl6_regs0 + assign $0\builder_multiregimpl7_regs0[0:0] \main_gpio_pads_i [6] + assign $0\builder_multiregimpl7_regs1[0:0] \builder_multiregimpl7_regs0 + assign $0\builder_multiregimpl8_regs0[0:0] \main_gpio_pads_i [7] + assign $0\builder_multiregimpl8_regs1[0:0] \builder_multiregimpl8_regs0 + assign $0\builder_multiregimpl9_regs0[0:0] \main_gpio_pads_i [8] + assign $0\builder_multiregimpl9_regs1[0:0] \builder_multiregimpl9_regs0 + assign $0\builder_multiregimpl10_regs0[0:0] \main_gpio_pads_i [9] + assign $0\builder_multiregimpl10_regs1[0:0] \builder_multiregimpl10_regs0 + assign $0\builder_multiregimpl11_regs0[0:0] \main_gpio_pads_i [10] + assign $0\builder_multiregimpl11_regs1[0:0] \builder_multiregimpl11_regs0 + assign $0\builder_multiregimpl12_regs0[0:0] \main_gpio_pads_i [11] + assign $0\builder_multiregimpl12_regs1[0:0] \builder_multiregimpl12_regs0 + assign $0\builder_multiregimpl13_regs0[0:0] \main_gpio_pads_i [12] + assign $0\builder_multiregimpl13_regs1[0:0] \builder_multiregimpl13_regs0 + assign $0\builder_multiregimpl14_regs0[0:0] \main_gpio_pads_i [13] + assign $0\builder_multiregimpl14_regs1[0:0] \builder_multiregimpl14_regs0 + assign $0\builder_multiregimpl15_regs0[0:0] \main_gpio_pads_i [14] + assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0 + assign $0\builder_multiregimpl16_regs0[0:0] \main_gpio_pads_i [15] + assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 + attribute \src "ls180.v:7448.2-7450.5" + switch $or$ls180.v:7448$2411_Y + attribute \src "ls180.v:7448.6-7448.94" + case 1'1 + assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_libresoc_ibus_dat_r + case + end + attribute \src "ls180.v:7452.2-7454.5" + switch \main_libresocsim_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:7452.6-7452.66" + case 1'1 + assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter_converter0_next_value + case + end + attribute \src "ls180.v:7455.2-7458.5" + switch \main_libresocsim_converter0_reset + attribute \src "ls180.v:7455.6-7455.39" + case 1'1 + assign $0\main_libresocsim_converter0_counter[0:0] 1'0 + assign $0\builder_converter0_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7459.2-7461.5" + switch $or$ls180.v:7459$2412_Y + attribute \src "ls180.v:7459.6-7459.94" + case 1'1 + assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_libresoc_dbus_dat_r + case + end + attribute \src "ls180.v:7463.2-7465.5" + switch \main_libresocsim_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:7463.6-7463.66" + case 1'1 + assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter_converter1_next_value + case + end + attribute \src "ls180.v:7466.2-7469.5" + switch \main_libresocsim_converter1_reset + attribute \src "ls180.v:7466.6-7466.39" + case 1'1 + assign $0\main_libresocsim_converter1_counter[0:0] 1'0 + assign $0\builder_converter1_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7470.2-7472.5" + switch $or$ls180.v:7470$2413_Y + attribute \src "ls180.v:7470.6-7470.94" + case 1'1 + assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_libresoc_jtag_wb_dat_r + case + end + attribute \src "ls180.v:7474.2-7476.5" + switch \main_libresocsim_converter2_counter_converter2_next_value_ce + attribute \src "ls180.v:7474.6-7474.66" + case 1'1 + assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter_converter2_next_value + case + end + attribute \src "ls180.v:7477.2-7480.5" + switch \main_libresocsim_converter2_reset + attribute \src "ls180.v:7477.6-7477.39" + case 1'1 + assign $0\main_libresocsim_converter2_counter[0:0] 1'0 + assign $0\builder_converter2_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7481.2-7485.5" + switch $ne$ls180.v:7481$2414_Y + attribute \src "ls180.v:7481.6-7481.53" + case 1'1 + attribute \src "ls180.v:7482.3-7484.6" + switch \main_libresocsim_bus_error + attribute \src "ls180.v:7482.7-7482.33" + case 1'1 + assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7483$2415_Y + case + end + case + end + attribute \src "ls180.v:7487.2-7489.5" + switch $and$ls180.v:7487$2418_Y + attribute \src "ls180.v:7487.6-7487.103" + case 1'1 + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "ls180.v:7490.2-7498.5" + switch \main_libresocsim_en_storage + attribute \src "ls180.v:7490.6-7490.33" + case 1'1 + attribute \src "ls180.v:7491.3-7495.6" + switch $eq$ls180.v:7491$2419_Y + attribute \src "ls180.v:7491.7-7491.39" + case 1'1 + assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage + attribute \src "ls180.v:7493.7-7493.11" + case + assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7494$2420_Y + end + attribute \src "ls180.v:7496.6-7496.10" + case + assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage + end + attribute \src "ls180.v:7499.2-7501.5" + switch \main_libresocsim_update_value_re + attribute \src "ls180.v:7499.6-7499.38" + case 1'1 + assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value + case + end + attribute \src "ls180.v:7502.2-7504.5" + switch \main_libresocsim_zero_clear + attribute \src "ls180.v:7502.6-7502.33" + case 1'1 + assign $0\main_libresocsim_zero_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:7506.2-7508.5" + switch $and$ls180.v:7506$2422_Y + attribute \src "ls180.v:7506.6-7506.76" + case 1'1 + assign $0\main_libresocsim_zero_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:7511.2-7513.5" + switch \main_sdram_inti_p0_rddata_valid + attribute \src "ls180.v:7511.6-7511.37" + case 1'1 + assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata + case + end + attribute \src "ls180.v:7514.2-7518.5" + switch $and$ls180.v:7514$2424_Y + attribute \src "ls180.v:7514.6-7514.57" + case 1'1 + assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7515$2425_Y + attribute \src "ls180.v:7516.6-7516.10" + case + assign $0\main_sdram_timer_count1[9:0] 10'1100001101 + end + attribute \src "ls180.v:7520.2-7526.5" + switch \main_sdram_postponer_req_i + attribute \src "ls180.v:7520.6-7520.32" + case 1'1 + assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7521$2426_Y + attribute \src "ls180.v:7522.3-7525.6" + switch $eq$ls180.v:7522$2427_Y + attribute \src "ls180.v:7522.7-7522.43" + case 1'1 + assign $0\main_sdram_postponer_count[0:0] 1'0 + assign $0\main_sdram_postponer_req_o[0:0] 1'1 + case + end + case + end + attribute \src "ls180.v:7527.2-7535.5" + switch \main_sdram_sequencer_start0 + attribute \src "ls180.v:7527.6-7527.33" + case 1'1 + assign $0\main_sdram_sequencer_count[0:0] 1'0 + attribute \src "ls180.v:7529.6-7529.10" + case + attribute \src "ls180.v:7530.3-7534.6" + switch \main_sdram_sequencer_done1 + attribute \src "ls180.v:7530.7-7530.33" + case 1'1 + attribute \src "ls180.v:7531.4-7533.7" + switch $ne$ls180.v:7531$2428_Y + attribute \src "ls180.v:7531.8-7531.44" + case 1'1 + assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7532$2429_Y + case + end + case + end + end + attribute \src "ls180.v:7542.2-7548.5" + switch $and$ls180.v:7542$2431_Y + attribute \src "ls180.v:7542.6-7542.76" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_cmd_payload_we[0:0] 1'1 + case + end + attribute \src "ls180.v:7549.2-7555.5" + switch $eq$ls180.v:7549$2432_Y + attribute \src "ls180.v:7549.6-7549.44" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'1 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + case + end + attribute \src "ls180.v:7556.2-7563.5" + switch $eq$ls180.v:7556$2433_Y + attribute \src "ls180.v:7556.6-7556.44" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'1 + case + end + attribute \src "ls180.v:7564.2-7574.5" + switch $eq$ls180.v:7564$2434_Y + attribute \src "ls180.v:7564.6-7564.44" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] 4'0000 + attribute \src "ls180.v:7566.6-7566.10" + case + attribute \src "ls180.v:7567.3-7573.6" + switch $ne$ls180.v:7567$2435_Y + attribute \src "ls180.v:7567.7-7567.45" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7568$2436_Y + attribute \src "ls180.v:7569.7-7569.11" + case + attribute \src "ls180.v:7570.4-7572.7" + switch \main_sdram_sequencer_start1 + attribute \src "ls180.v:7570.8-7570.35" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] 4'0001 + case + end + end + end + attribute \src "ls180.v:7576.2-7583.5" + switch \main_sdram_bankmachine0_row_close + attribute \src "ls180.v:7576.6-7576.39" + case 1'1 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 + attribute \src "ls180.v:7578.6-7578.10" + case + attribute \src "ls180.v:7579.3-7582.6" + switch \main_sdram_bankmachine0_row_open + attribute \src "ls180.v:7579.7-7579.39" + case 1'1 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7584.2-7586.5" + switch $and$ls180.v:7584$2439_Y + attribute \src "ls180.v:7584.6-7584.191" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7585$2440_Y + case + end + attribute \src "ls180.v:7587.2-7589.5" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7587.6-7587.58" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7588$2441_Y + case + end + attribute \src "ls180.v:7590.2-7598.5" + switch $and$ls180.v:7590$2444_Y + attribute \src "ls180.v:7590.6-7590.191" + case 1'1 + attribute \src "ls180.v:7591.3-7593.6" + switch $not$ls180.v:7591$2445_Y + attribute \src "ls180.v:7591.7-7591.62" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7592$2446_Y + case + end + attribute \src "ls180.v:7594.6-7594.10" + case + attribute \src "ls180.v:7595.3-7597.6" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7595.7-7595.59" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7596$2447_Y + case + end + end + attribute \src "ls180.v:7599.2-7605.5" + switch $or$ls180.v:7599$2449_Y + attribute \src "ls180.v:7599.6-7599.108" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7606.2-7620.5" + switch \main_sdram_bankmachine0_twtpcon_valid + attribute \src "ls180.v:7606.6-7606.43" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7608.3-7612.6" + switch 1'0 + attribute \src "ls180.v:7610.7-7610.11" + case + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7613.6-7613.10" + case + attribute \src "ls180.v:7614.3-7619.6" + switch $not$ls180.v:7614$2450_Y + attribute \src "ls180.v:7614.7-7614.47" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7615$2451_Y + attribute \src "ls180.v:7616.4-7618.7" + switch $eq$ls180.v:7616$2452_Y + attribute \src "ls180.v:7616.8-7616.55" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7622.2-7629.5" + switch \main_sdram_bankmachine1_row_close + attribute \src "ls180.v:7622.6-7622.39" + case 1'1 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 + attribute \src "ls180.v:7624.6-7624.10" + case + attribute \src "ls180.v:7625.3-7628.6" + switch \main_sdram_bankmachine1_row_open + attribute \src "ls180.v:7625.7-7625.39" + case 1'1 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7630.2-7632.5" + switch $and$ls180.v:7630$2455_Y + attribute \src "ls180.v:7630.6-7630.191" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7631$2456_Y + case + end + attribute \src "ls180.v:7633.2-7635.5" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7633.6-7633.58" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7634$2457_Y + case + end + attribute \src "ls180.v:7636.2-7644.5" + switch $and$ls180.v:7636$2460_Y + attribute \src "ls180.v:7636.6-7636.191" + case 1'1 + attribute \src "ls180.v:7637.3-7639.6" + switch $not$ls180.v:7637$2461_Y + attribute \src "ls180.v:7637.7-7637.62" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7638$2462_Y + case + end + attribute \src "ls180.v:7640.6-7640.10" + case + attribute \src "ls180.v:7641.3-7643.6" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7641.7-7641.59" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7642$2463_Y + case + end + end + attribute \src "ls180.v:7645.2-7651.5" + switch $or$ls180.v:7645$2465_Y + attribute \src "ls180.v:7645.6-7645.108" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7652.2-7666.5" + switch \main_sdram_bankmachine1_twtpcon_valid + attribute \src "ls180.v:7652.6-7652.43" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7654.3-7658.6" + switch 1'0 + attribute \src "ls180.v:7656.7-7656.11" + case + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7659.6-7659.10" + case + attribute \src "ls180.v:7660.3-7665.6" + switch $not$ls180.v:7660$2466_Y + attribute \src "ls180.v:7660.7-7660.47" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7661$2467_Y + attribute \src "ls180.v:7662.4-7664.7" + switch $eq$ls180.v:7662$2468_Y + attribute \src "ls180.v:7662.8-7662.55" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7668.2-7675.5" + switch \main_sdram_bankmachine2_row_close + attribute \src "ls180.v:7668.6-7668.39" + case 1'1 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 + attribute \src "ls180.v:7670.6-7670.10" + case + attribute \src "ls180.v:7671.3-7674.6" + switch \main_sdram_bankmachine2_row_open + attribute \src "ls180.v:7671.7-7671.39" + case 1'1 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7676.2-7678.5" + switch $and$ls180.v:7676$2471_Y + attribute \src "ls180.v:7676.6-7676.191" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7677$2472_Y + case + end + attribute \src "ls180.v:7679.2-7681.5" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7679.6-7679.58" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7680$2473_Y + case + end + attribute \src "ls180.v:7682.2-7690.5" + switch $and$ls180.v:7682$2476_Y + attribute \src "ls180.v:7682.6-7682.191" + case 1'1 + attribute \src "ls180.v:7683.3-7685.6" + switch $not$ls180.v:7683$2477_Y + attribute \src "ls180.v:7683.7-7683.62" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7684$2478_Y + case + end + attribute \src "ls180.v:7686.6-7686.10" + case + attribute \src "ls180.v:7687.3-7689.6" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7687.7-7687.59" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7688$2479_Y + case + end + end + attribute \src "ls180.v:7691.2-7697.5" + switch $or$ls180.v:7691$2481_Y + attribute \src "ls180.v:7691.6-7691.108" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7698.2-7712.5" + switch \main_sdram_bankmachine2_twtpcon_valid + attribute \src "ls180.v:7698.6-7698.43" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7700.3-7704.6" + switch 1'0 + attribute \src "ls180.v:7702.7-7702.11" + case + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7705.6-7705.10" + case + attribute \src "ls180.v:7706.3-7711.6" + switch $not$ls180.v:7706$2482_Y + attribute \src "ls180.v:7706.7-7706.47" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7707$2483_Y + attribute \src "ls180.v:7708.4-7710.7" + switch $eq$ls180.v:7708$2484_Y + attribute \src "ls180.v:7708.8-7708.55" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7714.2-7721.5" + switch \main_sdram_bankmachine3_row_close + attribute \src "ls180.v:7714.6-7714.39" + case 1'1 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 + attribute \src "ls180.v:7716.6-7716.10" + case + attribute \src "ls180.v:7717.3-7720.6" + switch \main_sdram_bankmachine3_row_open + attribute \src "ls180.v:7717.7-7717.39" + case 1'1 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7722.2-7724.5" + switch $and$ls180.v:7722$2487_Y + attribute \src "ls180.v:7722.6-7722.191" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7723$2488_Y + case + end + attribute \src "ls180.v:7725.2-7727.5" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7725.6-7725.58" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7726$2489_Y + case + end + attribute \src "ls180.v:7728.2-7736.5" + switch $and$ls180.v:7728$2492_Y + attribute \src "ls180.v:7728.6-7728.191" + case 1'1 + attribute \src "ls180.v:7729.3-7731.6" + switch $not$ls180.v:7729$2493_Y + attribute \src "ls180.v:7729.7-7729.62" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7730$2494_Y + case + end + attribute \src "ls180.v:7732.6-7732.10" + case + attribute \src "ls180.v:7733.3-7735.6" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7733.7-7733.59" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7734$2495_Y + case + end + end + attribute \src "ls180.v:7737.2-7743.5" + switch $or$ls180.v:7737$2497_Y + attribute \src "ls180.v:7737.6-7737.108" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7744.2-7758.5" + switch \main_sdram_bankmachine3_twtpcon_valid + attribute \src "ls180.v:7744.6-7744.43" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7746.3-7750.6" + switch 1'0 + attribute \src "ls180.v:7748.7-7748.11" + case + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7751.6-7751.10" + case + attribute \src "ls180.v:7752.3-7757.6" + switch $not$ls180.v:7752$2498_Y + attribute \src "ls180.v:7752.7-7752.47" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7753$2499_Y + attribute \src "ls180.v:7754.4-7756.7" + switch $eq$ls180.v:7754$2500_Y + attribute \src "ls180.v:7754.8-7754.55" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7760.2-7766.5" + switch $not$ls180.v:7760$2501_Y + attribute \src "ls180.v:7760.6-7760.23" + case 1'1 + assign $0\main_sdram_time0[4:0] 5'11111 + attribute \src "ls180.v:7762.6-7762.10" + case + attribute \src "ls180.v:7763.3-7765.6" + switch $not$ls180.v:7763$2502_Y + attribute \src "ls180.v:7763.7-7763.30" + case 1'1 + assign $0\main_sdram_time0[4:0] $sub$ls180.v:7764$2503_Y + case + end + end + attribute \src "ls180.v:7767.2-7773.5" + switch $not$ls180.v:7767$2504_Y + attribute \src "ls180.v:7767.6-7767.23" + case 1'1 + assign $0\main_sdram_time1[3:0] 4'1111 + attribute \src "ls180.v:7769.6-7769.10" + case + attribute \src "ls180.v:7770.3-7772.6" + switch $not$ls180.v:7770$2505_Y + attribute \src "ls180.v:7770.7-7770.30" + case 1'1 + assign $0\main_sdram_time1[3:0] $sub$ls180.v:7771$2506_Y + case + end + end + attribute \src "ls180.v:7774.2-7829.5" + switch \main_sdram_choose_cmd_ce + attribute \src "ls180.v:7774.6-7774.30" + case 1'1 + attribute \src "ls180.v:7775.3-7828.10" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + attribute \src "ls180.v:7777.5-7787.8" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:7777.9-7777.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "ls180.v:7779.9-7779.13" + case + attribute \src "ls180.v:7780.6-7786.9" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:7780.10-7780.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "ls180.v:7782.10-7782.14" + case + attribute \src "ls180.v:7783.7-7785.10" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:7783.11-7783.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'01 + attribute \src "ls180.v:7790.5-7800.8" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:7790.9-7790.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "ls180.v:7792.9-7792.13" + case + attribute \src "ls180.v:7793.6-7799.9" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:7793.10-7793.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "ls180.v:7795.10-7795.14" + case + attribute \src "ls180.v:7796.7-7798.10" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:7796.11-7796.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + attribute \src "ls180.v:7803.5-7813.8" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:7803.9-7803.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "ls180.v:7805.9-7805.13" + case + attribute \src "ls180.v:7806.6-7812.9" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:7806.10-7806.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "ls180.v:7808.10-7808.14" + case + attribute \src "ls180.v:7809.7-7811.10" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:7809.11-7809.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + attribute \src "ls180.v:7816.5-7826.8" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:7816.9-7816.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "ls180.v:7818.9-7818.13" + case + attribute \src "ls180.v:7819.6-7825.9" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:7819.10-7819.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "ls180.v:7821.10-7821.14" + case + attribute \src "ls180.v:7822.7-7824.10" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:7822.11-7822.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + case + end + end + end + case + end + case + end + attribute \src "ls180.v:7830.2-7885.5" + switch \main_sdram_choose_req_ce + attribute \src "ls180.v:7830.6-7830.30" + case 1'1 + attribute \src "ls180.v:7831.3-7884.10" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + attribute \src "ls180.v:7833.5-7843.8" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:7833.9-7833.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + attribute \src "ls180.v:7835.9-7835.13" + case + attribute \src "ls180.v:7836.6-7842.9" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:7836.10-7836.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + attribute \src "ls180.v:7838.10-7838.14" + case + attribute \src "ls180.v:7839.7-7841.10" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:7839.11-7839.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'01 + attribute \src "ls180.v:7846.5-7856.8" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:7846.9-7846.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + attribute \src "ls180.v:7848.9-7848.13" + case + attribute \src "ls180.v:7849.6-7855.9" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:7849.10-7849.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + attribute \src "ls180.v:7851.10-7851.14" + case + attribute \src "ls180.v:7852.7-7854.10" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:7852.11-7852.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + attribute \src "ls180.v:7859.5-7869.8" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:7859.9-7859.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + attribute \src "ls180.v:7861.9-7861.13" + case + attribute \src "ls180.v:7862.6-7868.9" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:7862.10-7862.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + attribute \src "ls180.v:7864.10-7864.14" + case + attribute \src "ls180.v:7865.7-7867.10" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:7865.11-7865.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + attribute \src "ls180.v:7872.5-7882.8" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:7872.9-7872.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + attribute \src "ls180.v:7874.9-7874.13" + case + attribute \src "ls180.v:7875.6-7881.9" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:7875.10-7875.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + attribute \src "ls180.v:7877.10-7877.14" + case + attribute \src "ls180.v:7878.7-7880.10" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:7878.11-7878.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + case + end + end + end + case + end + case + end + attribute \src "ls180.v:7894.2-7908.5" + switch \main_sdram_tccdcon_valid + attribute \src "ls180.v:7894.6-7894.30" + case 1'1 + assign $0\main_sdram_tccdcon_count[0:0] 1'0 + attribute \src "ls180.v:7896.3-7900.6" + switch 1'1 + attribute \src "ls180.v:7896.7-7896.11" + case 1'1 + assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:7901.6-7901.10" + case + attribute \src "ls180.v:7902.3-7907.6" + switch $not$ls180.v:7902$2510_Y + attribute \src "ls180.v:7902.7-7902.34" + case 1'1 + assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7903$2511_Y + attribute \src "ls180.v:7904.4-7906.7" + switch $eq$ls180.v:7904$2512_Y + attribute \src "ls180.v:7904.8-7904.42" + case 1'1 + assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7909.2-7923.5" + switch \main_sdram_twtrcon_valid + attribute \src "ls180.v:7909.6-7909.30" + case 1'1 + assign $0\main_sdram_twtrcon_count[2:0] 3'100 + attribute \src "ls180.v:7911.3-7915.6" + switch 1'0 + attribute \src "ls180.v:7913.7-7913.11" + case + assign $0\main_sdram_twtrcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7916.6-7916.10" + case + attribute \src "ls180.v:7917.3-7922.6" + switch $not$ls180.v:7917$2513_Y + attribute \src "ls180.v:7917.7-7917.34" + case 1'1 + assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:7918$2514_Y + attribute \src "ls180.v:7919.4-7921.7" + switch $eq$ls180.v:7919$2515_Y + attribute \src "ls180.v:7919.8-7919.42" + case 1'1 + assign $0\main_sdram_twtrcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7930.2-7932.5" + switch $or$ls180.v:7930$2540_Y + attribute \src "ls180.v:7930.6-7930.50" + case 1'1 + assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r + case + end + attribute \src "ls180.v:7934.2-7936.5" + switch \main_converter_counter_converter_next_value_ce + attribute \src "ls180.v:7934.6-7934.52" + case 1'1 + assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value + case + end + attribute \src "ls180.v:7937.2-7940.5" + switch \main_converter_reset + attribute \src "ls180.v:7937.6-7937.26" + case 1'1 + assign $0\main_converter_counter[0:0] 1'0 + assign $0\builder_converter_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7941.2-7951.5" + switch \main_litedram_wb_ack + attribute \src "ls180.v:7941.6-7941.26" + case 1'1 + assign $0\main_cmd_consumed[0:0] 1'0 + assign $0\main_wdata_consumed[0:0] 1'0 + attribute \src "ls180.v:7944.6-7944.10" + case + attribute \src "ls180.v:7945.3-7947.6" + switch $and$ls180.v:7945$2541_Y + attribute \src "ls180.v:7945.7-7945.50" + case 1'1 + assign $0\main_cmd_consumed[0:0] 1'1 + case + end + attribute \src "ls180.v:7948.3-7950.6" + switch $and$ls180.v:7948$2542_Y + attribute \src "ls180.v:7948.7-7948.54" + case 1'1 + assign $0\main_wdata_consumed[0:0] 1'1 + case + end + end + attribute \src "ls180.v:7953.2-7974.5" + switch $and$ls180.v:7953$2546_Y + attribute \src "ls180.v:7953.6-7953.91" + case 1'1 + assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data + assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000 + assign $0\main_uart_phy_tx_busy[0:0] 1'1 + assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'0 + attribute \src "ls180.v:7958.6-7958.10" + case + attribute \src "ls180.v:7959.3-7973.6" + switch $and$ls180.v:7959$2547_Y + attribute \src "ls180.v:7959.7-7959.60" + case 1'1 + assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:7960$2548_Y + attribute \src "ls180.v:7961.4-7972.7" + switch $eq$ls180.v:7961$2549_Y + attribute \src "ls180.v:7961.8-7961.43" + case 1'1 + assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 + attribute \src "ls180.v:7963.8-7963.12" + case + attribute \src "ls180.v:7964.5-7971.8" + switch $eq$ls180.v:7964$2550_Y + attribute \src "ls180.v:7964.9-7964.44" + case 1'1 + assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 + assign $0\main_uart_phy_tx_busy[0:0] 1'0 + assign $0\main_uart_phy_sink_ready[0:0] 1'1 + attribute \src "ls180.v:7968.9-7968.13" + case + assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] \main_uart_phy_tx_reg [0] + assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] } + end + end + case + end + end + attribute \src "ls180.v:7975.2-7979.5" + switch \main_uart_phy_tx_busy + attribute \src "ls180.v:7975.6-7975.27" + case 1'1 + assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:7976$2551_Y + attribute \src "ls180.v:7977.6-7977.10" + case + assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage } + end + attribute \src "ls180.v:7982.2-8006.5" + switch $not$ls180.v:7982$2552_Y + attribute \src "ls180.v:7982.6-7982.30" + case 1'1 + attribute \src "ls180.v:7983.3-7986.6" + switch $and$ls180.v:7983$2554_Y + attribute \src "ls180.v:7983.7-7983.49" + case 1'1 + assign $0\main_uart_phy_rx_busy[0:0] 1'1 + assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000 + case + end + attribute \src "ls180.v:7987.6-7987.10" + case + attribute \src "ls180.v:7988.3-8005.6" + switch \main_uart_phy_uart_clk_rxen + attribute \src "ls180.v:7988.7-7988.34" + case 1'1 + assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:7989$2555_Y + attribute \src "ls180.v:7990.4-8004.7" + switch $eq$ls180.v:7990$2556_Y + attribute \src "ls180.v:7990.8-7990.43" + case 1'1 + attribute \src "ls180.v:7991.5-7993.8" + switch \main_uart_phy_rx + attribute \src "ls180.v:7991.9-7991.25" + case 1'1 + assign $0\main_uart_phy_rx_busy[0:0] 1'0 + case + end + attribute \src "ls180.v:7994.8-7994.12" + case + attribute \src "ls180.v:7995.5-8003.8" + switch $eq$ls180.v:7995$2557_Y + attribute \src "ls180.v:7995.9-7995.44" + case 1'1 + assign $0\main_uart_phy_rx_busy[0:0] 1'0 + attribute \src "ls180.v:7997.6-8000.9" + switch \main_uart_phy_rx + attribute \src "ls180.v:7997.10-7997.26" + case 1'1 + assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg + assign $0\main_uart_phy_source_valid[0:0] 1'1 + case + end + attribute \src "ls180.v:8001.9-8001.13" + case + assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] } + end + end + case + end + end + attribute \src "ls180.v:8007.2-8011.5" + switch \main_uart_phy_rx_busy + attribute \src "ls180.v:8007.6-8007.27" + case 1'1 + assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8008$2558_Y + attribute \src "ls180.v:8009.6-8009.10" + case + assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 + end + attribute \src "ls180.v:8012.2-8014.5" + switch \main_uart_tx_clear + attribute \src "ls180.v:8012.6-8012.24" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:8016.2-8018.5" + switch $and$ls180.v:8016$2560_Y + attribute \src "ls180.v:8016.6-8016.58" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:8019.2-8021.5" + switch \main_uart_rx_clear + attribute \src "ls180.v:8019.6-8019.24" + case 1'1 + assign $0\main_uart_rx_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:8023.2-8025.5" + switch $and$ls180.v:8023$2562_Y + attribute \src "ls180.v:8023.6-8023.58" + case 1'1 + assign $0\main_uart_rx_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:8026.2-8032.5" + switch \main_uart_tx_fifo_syncfifo_re + attribute \src "ls180.v:8026.6-8026.35" + case 1'1 + assign $0\main_uart_tx_fifo_readable[0:0] 1'1 + attribute \src "ls180.v:8028.6-8028.10" + case + attribute \src "ls180.v:8029.3-8031.6" + switch \main_uart_tx_fifo_re + attribute \src "ls180.v:8029.7-8029.27" + case 1'1 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8033.2-8035.5" + switch $and$ls180.v:8033$2565_Y + attribute \src "ls180.v:8033.6-8033.108" + case 1'1 + assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8034$2566_Y + case + end + attribute \src "ls180.v:8036.2-8038.5" + switch \main_uart_tx_fifo_do_read + attribute \src "ls180.v:8036.6-8036.31" + case 1'1 + assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8037$2567_Y + case + end + attribute \src "ls180.v:8039.2-8047.5" + switch $and$ls180.v:8039$2570_Y + attribute \src "ls180.v:8039.6-8039.108" + case 1'1 + attribute \src "ls180.v:8040.3-8042.6" + switch $not$ls180.v:8040$2571_Y + attribute \src "ls180.v:8040.7-8040.35" + case 1'1 + assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8041$2572_Y + case + end + attribute \src "ls180.v:8043.6-8043.10" + case + attribute \src "ls180.v:8044.3-8046.6" + switch \main_uart_tx_fifo_do_read + attribute \src "ls180.v:8044.7-8044.32" + case 1'1 + assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8045$2573_Y + case + end + end + attribute \src "ls180.v:8048.2-8054.5" + switch \main_uart_rx_fifo_syncfifo_re + attribute \src "ls180.v:8048.6-8048.35" + case 1'1 + assign $0\main_uart_rx_fifo_readable[0:0] 1'1 + attribute \src "ls180.v:8050.6-8050.10" + case + attribute \src "ls180.v:8051.3-8053.6" + switch \main_uart_rx_fifo_re + attribute \src "ls180.v:8051.7-8051.27" + case 1'1 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8055.2-8057.5" + switch $and$ls180.v:8055$2576_Y + attribute \src "ls180.v:8055.6-8055.108" + case 1'1 + assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8056$2577_Y + case + end + attribute \src "ls180.v:8058.2-8060.5" + switch \main_uart_rx_fifo_do_read + attribute \src "ls180.v:8058.6-8058.31" + case 1'1 + assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8059$2578_Y + case + end + attribute \src "ls180.v:8061.2-8069.5" + switch $and$ls180.v:8061$2581_Y + attribute \src "ls180.v:8061.6-8061.108" + case 1'1 + attribute \src "ls180.v:8062.3-8064.6" + switch $not$ls180.v:8062$2582_Y + attribute \src "ls180.v:8062.7-8062.35" + case 1'1 + assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8063$2583_Y + case + end + attribute \src "ls180.v:8065.6-8065.10" + case + attribute \src "ls180.v:8066.3-8068.6" + switch \main_uart_rx_fifo_do_read + attribute \src "ls180.v:8066.7-8066.32" + case 1'1 + assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8067$2584_Y + case + end + end + attribute \src "ls180.v:8070.2-8083.5" + switch \main_uart_reset + attribute \src "ls180.v:8070.6-8070.21" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'0 + assign $0\main_uart_tx_old_trigger[0:0] 1'0 + assign $0\main_uart_rx_pending[0:0] 1'0 + assign $0\main_uart_rx_old_trigger[0:0] 1'0 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 + case + end + attribute \src "ls180.v:8085.2-8092.5" + switch \main_spi_master_clk_rise + attribute \src "ls180.v:8085.6-8085.30" + case 1'1 + assign $0\spi_master_clk[0:0] \main_spi_master_clk_enable + attribute \src "ls180.v:8087.6-8087.10" + case + attribute \src "ls180.v:8088.3-8091.6" + switch \main_spi_master_clk_fall + attribute \src "ls180.v:8088.7-8088.31" + case 1'1 + assign $0\main_spi_master_clk_divider1[15:0] 16'0000000000000000 + assign $0\spi_master_clk[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8094.2-8104.5" + switch \main_spi_master_mosi_latch + attribute \src "ls180.v:8094.6-8094.32" + case 1'1 + assign $0\main_spi_master_mosi_data[7:0] \main_spi_master_mosi + assign $0\main_spi_master_mosi_sel[2:0] 3'111 + attribute \src "ls180.v:8097.6-8097.10" + case + attribute \src "ls180.v:8098.3-8103.6" + switch \main_spi_master_clk_fall + attribute \src "ls180.v:8098.7-8098.31" + case 1'1 + assign $0\main_spi_master_mosi_sel[2:0] $sub$ls180.v:8102$2589_Y + attribute \src "ls180.v:8099.4-8101.7" + switch \main_spi_master_cs_enable + attribute \src "ls180.v:8099.8-8099.33" + case 1'1 + assign $0\spi_master_mosi[0:0] \builder_sync_f_array_muxed0 + case + end + case + end + end + attribute \src "ls180.v:8105.2-8111.5" + switch \main_spi_master_clk_rise + attribute \src "ls180.v:8105.6-8105.30" + case 1'1 + attribute \src "ls180.v:8106.3-8110.6" + switch \main_spi_master_loopback + attribute \src "ls180.v:8106.7-8106.31" + case 1'1 + assign $0\main_spi_master_miso_data[7:0] { \main_spi_master_miso_data [6:0] \spi_master_mosi } + attribute \src "ls180.v:8108.7-8108.11" + case + assign $0\main_spi_master_miso_data[7:0] { \main_spi_master_miso_data [6:0] \spi_master_miso } + end + case + end + attribute \src "ls180.v:8112.2-8114.5" + switch \main_spi_master_miso_latch + attribute \src "ls180.v:8112.6-8112.32" + case 1'1 + assign $0\main_spi_master_miso[7:0] \main_spi_master_miso_data + case + end + attribute \src "ls180.v:8116.2-8118.5" + switch \main_spi_master_count_spimaster0_next_value_ce + attribute \src "ls180.v:8116.6-8116.52" + case 1'1 + assign $0\main_spi_master_count[2:0] \main_spi_master_count_spimaster0_next_value + case + end + attribute \src "ls180.v:8119.2-8132.5" + switch \main_pwm0_enable + attribute \src "ls180.v:8119.6-8119.22" + case 1'1 + assign $0\main_pwm0_counter[31:0] $add$ls180.v:8120$2590_Y + attribute \src "ls180.v:8121.3-8125.6" + switch $lt$ls180.v:8121$2591_Y + attribute \src "ls180.v:8121.7-8121.44" + case 1'1 + assign $0\pwm0[0:0] 1'1 + attribute \src "ls180.v:8123.7-8123.11" + case + assign $0\pwm0[0:0] 1'0 + end + attribute \src "ls180.v:8126.3-8128.6" + switch $ge$ls180.v:8126$2593_Y + attribute \src "ls180.v:8126.7-8126.55" + case 1'1 + assign $0\main_pwm0_counter[31:0] 0 + case + end + attribute \src "ls180.v:8129.6-8129.10" + case + assign $0\main_pwm0_counter[31:0] 0 + assign $0\pwm0[0:0] 1'0 + end + attribute \src "ls180.v:8133.2-8146.5" + switch \main_pwm1_enable + attribute \src "ls180.v:8133.6-8133.22" + case 1'1 + assign $0\main_pwm1_counter[31:0] $add$ls180.v:8134$2594_Y + attribute \src "ls180.v:8135.3-8139.6" + switch $lt$ls180.v:8135$2595_Y + attribute \src "ls180.v:8135.7-8135.44" + case 1'1 + assign $0\pwm1[0:0] 1'1 + attribute \src "ls180.v:8137.7-8137.11" + case + assign $0\pwm1[0:0] 1'0 + end + attribute \src "ls180.v:8140.3-8142.6" + switch $ge$ls180.v:8140$2597_Y + attribute \src "ls180.v:8140.7-8140.55" + case 1'1 + assign $0\main_pwm1_counter[31:0] 0 + case + end + attribute \src "ls180.v:8143.6-8143.10" + case + assign $0\main_pwm1_counter[31:0] 0 + assign $0\pwm1[0:0] 1'0 + end + attribute \src "ls180.v:8147.2-8149.5" + switch $not$ls180.v:8147$2598_Y + attribute \src "ls180.v:8147.6-8147.32" + case 1'1 + assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8148$2599_Y + case + end + attribute \src "ls180.v:8153.2-8155.5" + switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce + attribute \src "ls180.v:8153.6-8153.57" + case 1'1 + assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value + case + end + attribute \src "ls180.v:8157.2-8159.5" + switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce + attribute \src "ls180.v:8157.6-8157.57" + case 1'1 + assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value + case + end + attribute \src "ls180.v:8160.2-8162.5" + switch \main_sdphy_cmdr_cmdr_pads_in_valid + attribute \src "ls180.v:8160.6-8160.40" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8161$2600_Y + case + end + attribute \src "ls180.v:8163.2-8165.5" + switch \main_sdphy_cmdr_cmdr_converter_source_ready + attribute \src "ls180.v:8163.6-8163.49" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8166.2-8173.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8166.6-8166.46" + case 1'1 + attribute \src "ls180.v:8167.3-8172.6" + switch $or$ls180.v:8167$2602_Y + attribute \src "ls180.v:8167.7-8167.98" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8170.7-8170.11" + case + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8171$2603_Y + end + case + end + attribute \src "ls180.v:8174.2-8187.5" + switch $and$ls180.v:8174$2604_Y + attribute \src "ls180.v:8174.6-8174.97" + case 1'1 + attribute \src "ls180.v:8175.3-8181.6" + switch $and$ls180.v:8175$2605_Y + attribute \src "ls180.v:8175.7-8175.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last + attribute \src "ls180.v:8178.7-8178.11" + case + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8182.6-8182.10" + case + attribute \src "ls180.v:8183.3-8186.6" + switch $and$ls180.v:8183$2606_Y + attribute \src "ls180.v:8183.7-8183.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8184$2607_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8185$2608_Y + case + end + end + attribute \src "ls180.v:8188.2-8215.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8188.6-8188.46" + case 1'1 + attribute \src "ls180.v:8189.3-8214.10" + switch \main_sdphy_cmdr_cmdr_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [7] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [6] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [5] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [4] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [3] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [2] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [1] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [0] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8216.2-8218.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8216.6-8216.46" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8217$2609_Y + case + end + attribute \src "ls180.v:8219.2-8224.5" + switch $or$ls180.v:8219$2611_Y + attribute \src "ls180.v:8219.6-8219.88" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid + assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first + assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_sink_last + assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data + case + end + attribute \src "ls180.v:8225.2-8230.5" + switch \main_sdphy_cmdr_cmdr_reset + attribute \src "ls180.v:8225.6-8225.32" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8232.2-8234.5" + switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 + attribute \src "ls180.v:8232.6-8232.58" + case 1'1 + assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 + case + end + attribute \src "ls180.v:8235.2-8237.5" + switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 + attribute \src "ls180.v:8235.6-8235.60" + case 1'1 + assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 + case + end + attribute \src "ls180.v:8238.2-8240.5" + switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 + attribute \src "ls180.v:8238.6-8238.63" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 + case + end + attribute \src "ls180.v:8241.2-8243.5" + switch \main_sdphy_dataw_crcr_pads_in_valid + attribute \src "ls180.v:8241.6-8241.41" + case 1'1 + assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8242$2612_Y + case + end + attribute \src "ls180.v:8244.2-8246.5" + switch \main_sdphy_dataw_crcr_converter_source_ready + attribute \src "ls180.v:8244.6-8244.50" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8247.2-8254.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8247.6-8247.47" + case 1'1 + attribute \src "ls180.v:8248.3-8253.6" + switch $or$ls180.v:8248$2614_Y + attribute \src "ls180.v:8248.7-8248.100" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8251.7-8251.11" + case + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8252$2615_Y + end + case + end + attribute \src "ls180.v:8255.2-8268.5" + switch $and$ls180.v:8255$2616_Y + attribute \src "ls180.v:8255.6-8255.99" + case 1'1 + attribute \src "ls180.v:8256.3-8262.6" + switch $and$ls180.v:8256$2617_Y + attribute \src "ls180.v:8256.7-8256.96" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last + attribute \src "ls180.v:8259.7-8259.11" + case + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8263.6-8263.10" + case + attribute \src "ls180.v:8264.3-8267.6" + switch $and$ls180.v:8264$2618_Y + attribute \src "ls180.v:8264.7-8264.96" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8265$2619_Y + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8266$2620_Y + case + end + end + attribute \src "ls180.v:8269.2-8296.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8269.6-8269.47" + case 1'1 + attribute \src "ls180.v:8270.3-8295.10" + switch \main_sdphy_dataw_crcr_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [7] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [6] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [5] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [4] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [3] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [2] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [1] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [0] \main_sdphy_dataw_crcr_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8297.2-8299.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8297.6-8297.47" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8298$2621_Y + case + end + attribute \src "ls180.v:8300.2-8305.5" + switch $or$ls180.v:8300$2623_Y + attribute \src "ls180.v:8300.6-8300.90" + case 1'1 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid + assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first + assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_sink_last + assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data + case + end + attribute \src "ls180.v:8306.2-8311.5" + switch \main_sdphy_dataw_crcr_reset + attribute \src "ls180.v:8306.6-8306.33" + case 1'1 + assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8313.2-8315.5" + switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce + attribute \src "ls180.v:8313.6-8313.63" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value + case + end + attribute \src "ls180.v:8317.2-8319.5" + switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce + attribute \src "ls180.v:8317.6-8317.52" + case 1'1 + assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value + case + end + attribute \src "ls180.v:8320.2-8322.5" + switch \main_sdphy_datar_datar_pads_in_valid + attribute \src "ls180.v:8320.6-8320.42" + case 1'1 + assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8321$2624_Y + case + end + attribute \src "ls180.v:8323.2-8325.5" + switch \main_sdphy_datar_datar_converter_source_ready + attribute \src "ls180.v:8323.6-8323.51" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8326.2-8333.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8326.6-8326.48" + case 1'1 + attribute \src "ls180.v:8327.3-8332.6" + switch $or$ls180.v:8327$2626_Y + attribute \src "ls180.v:8327.7-8327.102" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8330.7-8330.11" + case + assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8331$2627_Y + end + case + end + attribute \src "ls180.v:8334.2-8347.5" + switch $and$ls180.v:8334$2628_Y + attribute \src "ls180.v:8334.6-8334.101" + case 1'1 + attribute \src "ls180.v:8335.3-8341.6" + switch $and$ls180.v:8335$2629_Y + attribute \src "ls180.v:8335.7-8335.98" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last + attribute \src "ls180.v:8338.7-8338.11" + case + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8342.6-8342.10" + case + attribute \src "ls180.v:8343.3-8346.6" + switch $and$ls180.v:8343$2630_Y + attribute \src "ls180.v:8343.7-8343.98" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8344$2631_Y + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8345$2632_Y + case + end + end + attribute \src "ls180.v:8348.2-8357.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8348.6-8348.48" + case 1'1 + attribute \src "ls180.v:8349.3-8356.10" + switch \main_sdphy_datar_datar_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [7:4] \main_sdphy_datar_datar_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [3:0] \main_sdphy_datar_datar_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8358.2-8360.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8358.6-8358.48" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8359$2633_Y + case + end + attribute \src "ls180.v:8361.2-8366.5" + switch $or$ls180.v:8361$2635_Y + attribute \src "ls180.v:8361.6-8361.92" + case 1'1 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid + assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first + assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_sink_last + assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data + case + end + attribute \src "ls180.v:8367.2-8372.5" + switch \main_sdphy_datar_datar_reset + attribute \src "ls180.v:8367.6-8367.34" + case 1'1 + assign $0\main_sdphy_datar_datar_run[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8374.2-8376.5" + switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 + attribute \src "ls180.v:8374.6-8374.60" + case 1'1 + assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 + case + end + attribute \src "ls180.v:8377.2-8379.5" + switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 + attribute \src "ls180.v:8377.6-8377.62" + case 1'1 + assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 + case + end + attribute \src "ls180.v:8380.2-8382.5" + switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 + attribute \src "ls180.v:8380.6-8380.66" + case 1'1 + assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 + case + end + attribute \src "ls180.v:8383.2-8389.5" + switch \main_sdcore_crc7_inserter_clr + attribute \src "ls180.v:8383.6-8383.35" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + attribute \src "ls180.v:8385.6-8385.10" + case + attribute \src "ls180.v:8386.3-8388.6" + switch \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:8386.7-8386.39" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40 + case + end + end + attribute \src "ls180.v:8390.2-8396.5" + switch \main_sdcore_crc16_inserter_crc0_clr + attribute \src "ls180.v:8390.6-8390.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8392.6-8392.10" + case + attribute \src "ls180.v:8393.3-8395.6" + switch \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:8393.7-8393.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 + case + end + end + attribute \src "ls180.v:8397.2-8403.5" + switch \main_sdcore_crc16_inserter_crc1_clr + attribute \src "ls180.v:8397.6-8397.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8399.6-8399.10" + case + attribute \src "ls180.v:8400.3-8402.6" + switch \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:8400.7-8400.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 + case + end + end + attribute \src "ls180.v:8404.2-8410.5" + switch \main_sdcore_crc16_inserter_crc2_clr + attribute \src "ls180.v:8404.6-8404.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8406.6-8406.10" + case + attribute \src "ls180.v:8407.3-8409.6" + switch \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:8407.7-8407.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 + case + end + end + attribute \src "ls180.v:8411.2-8417.5" + switch \main_sdcore_crc16_inserter_crc3_clr + attribute \src "ls180.v:8411.6-8411.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8413.6-8413.10" + case + attribute \src "ls180.v:8414.3-8416.6" + switch \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:8414.7-8414.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 + case + end + end + attribute \src "ls180.v:8419.2-8421.5" + switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 + attribute \src "ls180.v:8419.6-8419.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 + case + end + attribute \src "ls180.v:8422.2-8424.5" + switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 + attribute \src "ls180.v:8422.6-8422.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 + case + end + attribute \src "ls180.v:8425.2-8427.5" + switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 + attribute \src "ls180.v:8425.6-8425.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 + case + end + attribute \src "ls180.v:8428.2-8430.5" + switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 + attribute \src "ls180.v:8428.6-8428.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 + case + end + attribute \src "ls180.v:8431.2-8433.5" + switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 + attribute \src "ls180.v:8431.6-8431.78" + case 1'1 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 + case + end + attribute \src "ls180.v:8434.2-8436.5" + switch $and$ls180.v:8434$2636_Y + attribute \src "ls180.v:8434.6-8434.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc + case + end + attribute \src "ls180.v:8437.2-8439.5" + switch $and$ls180.v:8437$2637_Y + attribute \src "ls180.v:8437.6-8437.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc + case + end + attribute \src "ls180.v:8440.2-8442.5" + switch $and$ls180.v:8440$2638_Y + attribute \src "ls180.v:8440.6-8440.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc + case + end + attribute \src "ls180.v:8443.2-8445.5" + switch $and$ls180.v:8443$2639_Y + attribute \src "ls180.v:8443.6-8443.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc + case + end + attribute \src "ls180.v:8446.2-8450.5" + switch $and$ls180.v:8446$2640_Y + attribute \src "ls180.v:8446.6-8446.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } + assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12] + case + end + attribute \src "ls180.v:8451.2-8455.5" + switch $and$ls180.v:8451$2641_Y + attribute \src "ls180.v:8451.6-8451.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } + assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12] + case + end + attribute \src "ls180.v:8456.2-8460.5" + switch $and$ls180.v:8456$2642_Y + attribute \src "ls180.v:8456.6-8456.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } + assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12] + case + end + attribute \src "ls180.v:8461.2-8465.5" + switch $and$ls180.v:8461$2643_Y + attribute \src "ls180.v:8461.6-8461.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } + assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12] + case + end + attribute \src "ls180.v:8466.2-8474.5" + switch $and$ls180.v:8466$2644_Y + attribute \src "ls180.v:8466.6-8466.83" + case 1'1 + attribute \src "ls180.v:8467.3-8473.6" + switch \main_sdcore_crc16_checker_sink_last + attribute \src "ls180.v:8467.7-8467.42" + case 1'1 + assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + attribute \src "ls180.v:8469.7-8469.11" + case + attribute \src "ls180.v:8470.4-8472.7" + switch $ne$ls180.v:8470$2645_Y + attribute \src "ls180.v:8470.8-8470.48" + case 1'1 + assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8471$2646_Y + case + end + end + case + end + attribute \src "ls180.v:8475.2-8481.5" + switch \main_sdcore_crc16_checker_crc0_clr + attribute \src "ls180.v:8475.6-8475.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8477.6-8477.10" + case + attribute \src "ls180.v:8478.3-8480.6" + switch \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:8478.7-8478.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 + case + end + end + attribute \src "ls180.v:8482.2-8488.5" + switch \main_sdcore_crc16_checker_crc1_clr + attribute \src "ls180.v:8482.6-8482.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8484.6-8484.10" + case + attribute \src "ls180.v:8485.3-8487.6" + switch \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:8485.7-8485.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 + case + end + end + attribute \src "ls180.v:8489.2-8495.5" + switch \main_sdcore_crc16_checker_crc2_clr + attribute \src "ls180.v:8489.6-8489.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8491.6-8491.10" + case + attribute \src "ls180.v:8492.3-8494.6" + switch \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:8492.7-8492.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 + case + end + end + attribute \src "ls180.v:8496.2-8502.5" + switch \main_sdcore_crc16_checker_crc3_clr + attribute \src "ls180.v:8496.6-8496.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8498.6-8498.10" + case + attribute \src "ls180.v:8499.3-8501.6" + switch \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:8499.7-8499.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 + case + end + end + attribute \src "ls180.v:8504.2-8506.5" + switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 + attribute \src "ls180.v:8504.6-8504.52" + case 1'1 + assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0 + case + end + attribute \src "ls180.v:8507.2-8509.5" + switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1 + attribute \src "ls180.v:8507.6-8507.53" + case 1'1 + assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1 + case + end + attribute \src "ls180.v:8510.2-8512.5" + switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 + attribute \src "ls180.v:8510.6-8510.53" + case 1'1 + assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2 + case + end + attribute \src "ls180.v:8513.2-8515.5" + switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3 + attribute \src "ls180.v:8513.6-8513.54" + case 1'1 + assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3 + case + end + attribute \src "ls180.v:8516.2-8518.5" + switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 + attribute \src "ls180.v:8516.6-8516.53" + case 1'1 + assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4 + case + end + attribute \src "ls180.v:8519.2-8521.5" + switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 + attribute \src "ls180.v:8519.6-8519.55" + case 1'1 + assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 + case + end + attribute \src "ls180.v:8522.2-8524.5" + switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6 + attribute \src "ls180.v:8522.6-8522.54" + case 1'1 + assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6 + case + end + attribute \src "ls180.v:8525.2-8527.5" + switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 + attribute \src "ls180.v:8525.6-8525.56" + case 1'1 + assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7 + case + end + attribute \src "ls180.v:8528.2-8530.5" + switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 + attribute \src "ls180.v:8528.6-8528.63" + case 1'1 + assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 + case + end + attribute \src "ls180.v:8531.2-8533.5" + switch $and$ls180.v:8531$2649_Y + attribute \src "ls180.v:8531.6-8531.120" + case 1'1 + assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8532$2650_Y + case + end + attribute \src "ls180.v:8534.2-8536.5" + switch \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:8534.6-8534.35" + case 1'1 + assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8535$2651_Y + case + end + attribute \src "ls180.v:8537.2-8545.5" + switch $and$ls180.v:8537$2654_Y + attribute \src "ls180.v:8537.6-8537.120" + case 1'1 + attribute \src "ls180.v:8538.3-8540.6" + switch $not$ls180.v:8538$2655_Y + attribute \src "ls180.v:8538.7-8538.39" + case 1'1 + assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8539$2656_Y + case + end + attribute \src "ls180.v:8541.6-8541.10" + case + attribute \src "ls180.v:8542.3-8544.6" + switch \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:8542.7-8542.36" + case 1'1 + assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8543$2657_Y + case + end + end + attribute \src "ls180.v:8546.2-8548.5" + switch \main_sdblock2mem_converter_source_ready + attribute \src "ls180.v:8546.6-8546.45" + case 1'1 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8549.2-8556.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8549.6-8549.42" + case 1'1 + attribute \src "ls180.v:8550.3-8555.6" + switch $or$ls180.v:8550$2659_Y + attribute \src "ls180.v:8550.7-8550.90" + case 1'1 + assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8553.7-8553.11" + case + assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8554$2660_Y + end + case + end + attribute \src "ls180.v:8557.2-8570.5" + switch $and$ls180.v:8557$2661_Y + attribute \src "ls180.v:8557.6-8557.89" + case 1'1 + attribute \src "ls180.v:8558.3-8564.6" + switch $and$ls180.v:8558$2662_Y + attribute \src "ls180.v:8558.7-8558.86" + case 1'1 + assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first + assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last + attribute \src "ls180.v:8561.7-8561.11" + case + assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0 + assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8565.6-8565.10" + case + attribute \src "ls180.v:8566.3-8569.6" + switch $and$ls180.v:8566$2663_Y + attribute \src "ls180.v:8566.7-8566.86" + case 1'1 + assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8567$2664_Y + assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8568$2665_Y + case + end + end + attribute \src "ls180.v:8571.2-8586.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8571.6-8571.42" + case 1'1 + attribute \src "ls180.v:8572.3-8585.10" + switch \main_sdblock2mem_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [31:24] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [23:16] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [15:8] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [7:0] \main_sdblock2mem_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8587.2-8589.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8587.6-8587.42" + case 1'1 + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8588$2666_Y + case + end + attribute \src "ls180.v:8591.2-8593.5" + switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce + attribute \src "ls180.v:8591.6-8591.76" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value + case + end + attribute \src "ls180.v:8594.2-8597.5" + switch \main_sdblock2mem_wishbonedmawriter_reset + attribute \src "ls180.v:8594.6-8594.46" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + assign $0\builder_sdblock2memdma_state[1:0] 2'00 + case + end + attribute \src "ls180.v:8599.2-8601.5" + switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce + attribute \src "ls180.v:8599.6-8599.64" + case 1'1 + assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + case + end + attribute \src "ls180.v:8603.2-8605.5" + switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce + attribute \src "ls180.v:8603.6-8603.76" + case 1'1 + assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value + case + end + attribute \src "ls180.v:8606.2-8609.5" + switch \main_sdmem2block_dma_reset + attribute \src "ls180.v:8606.6-8606.32" + case 1'1 + assign $0\main_sdmem2block_dma_offset[31:0] 0 + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + case + end + attribute \src "ls180.v:8610.2-8616.5" + switch $and$ls180.v:8610$2667_Y + attribute \src "ls180.v:8610.6-8610.89" + case 1'1 + attribute \src "ls180.v:8611.3-8615.6" + switch \main_sdmem2block_converter_last + attribute \src "ls180.v:8611.7-8611.38" + case 1'1 + assign $0\main_sdmem2block_converter_mux[1:0] 2'00 + attribute \src "ls180.v:8613.7-8613.11" + case + assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8614$2668_Y + end + case + end + attribute \src "ls180.v:8617.2-8619.5" + switch $and$ls180.v:8617$2671_Y + attribute \src "ls180.v:8617.6-8617.120" + case 1'1 + assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8618$2672_Y + case + end + attribute \src "ls180.v:8620.2-8622.5" + switch \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:8620.6-8620.35" + case 1'1 + assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8621$2673_Y + case + end + attribute \src "ls180.v:8623.2-8631.5" + switch $and$ls180.v:8623$2676_Y + attribute \src "ls180.v:8623.6-8623.120" + case 1'1 + attribute \src "ls180.v:8624.3-8626.6" + switch $not$ls180.v:8624$2677_Y + attribute \src "ls180.v:8624.7-8624.39" + case 1'1 + assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8625$2678_Y + case + end + attribute \src "ls180.v:8627.6-8627.10" + case + attribute \src "ls180.v:8628.3-8630.6" + switch \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:8628.7-8628.36" + case 1'1 + assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8629$2679_Y + case + end + end + attribute \src "ls180.v:8633.2-8640.5" + switch \libresocsim_clk_rise + attribute \src "ls180.v:8633.6-8633.26" + case 1'1 + assign $0\spisdcard_clk[0:0] \libresocsim_clk_enable + attribute \src "ls180.v:8635.6-8635.10" + case + attribute \src "ls180.v:8636.3-8639.6" + switch \libresocsim_clk_fall + attribute \src "ls180.v:8636.7-8636.27" + case 1'1 + assign $0\libresocsim_clk_divider1[15:0] 16'0000000000000000 + assign $0\spisdcard_clk[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8642.2-8652.5" + switch \libresocsim_mosi_latch + attribute \src "ls180.v:8642.6-8642.28" + case 1'1 + assign $0\libresocsim_mosi_data[7:0] \libresocsim_mosi + assign $0\libresocsim_mosi_sel[2:0] 3'111 + attribute \src "ls180.v:8645.6-8645.10" + case + attribute \src "ls180.v:8646.3-8651.6" + switch \libresocsim_clk_fall + attribute \src "ls180.v:8646.7-8646.27" + case 1'1 + assign $0\libresocsim_mosi_sel[2:0] $sub$ls180.v:8650$2684_Y + attribute \src "ls180.v:8647.4-8649.7" + switch \libresocsim_cs_enable + attribute \src "ls180.v:8647.8-8647.29" + case 1'1 + assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed1 + case + end + case + end + end + attribute \src "ls180.v:8653.2-8659.5" + switch \libresocsim_clk_rise + attribute \src "ls180.v:8653.6-8653.26" + case 1'1 + attribute \src "ls180.v:8654.3-8658.6" + switch \libresocsim_loopback + attribute \src "ls180.v:8654.7-8654.27" + case 1'1 + assign $0\libresocsim_miso_data[7:0] { \libresocsim_miso_data [6:0] \spisdcard_mosi } + attribute \src "ls180.v:8656.7-8656.11" + case + assign $0\libresocsim_miso_data[7:0] { \libresocsim_miso_data [6:0] \spisdcard_miso } + end + case + end + attribute \src "ls180.v:8660.2-8662.5" + switch \libresocsim_miso_latch + attribute \src "ls180.v:8660.6-8660.28" + case 1'1 + assign $0\libresocsim_miso[7:0] \libresocsim_miso_data + case + end + attribute \src "ls180.v:8664.2-8666.5" + switch \libresocsim_count_spimaster1_next_value_ce + attribute \src "ls180.v:8664.6-8664.48" + case 1'1 + assign $0\libresocsim_count[2:0] \libresocsim_count_spimaster1_next_value + case + end + attribute \src "ls180.v:8668.2-8670.5" + switch \builder_libresocsim_dat_w_next_value_ce0 + attribute \src "ls180.v:8668.6-8668.46" + case 1'1 + assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 + case + end + attribute \src "ls180.v:8671.2-8673.5" + switch \builder_libresocsim_adr_next_value_ce1 + attribute \src "ls180.v:8671.6-8671.44" + case 1'1 + assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 + case + end + attribute \src "ls180.v:8674.2-8676.5" + switch \builder_libresocsim_we_next_value_ce2 + attribute \src "ls180.v:8674.6-8674.43" + case 1'1 + assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 + case + end + attribute \src "ls180.v:8677.2-8773.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + attribute \src "ls180.v:8679.4-8695.7" + switch $not$ls180.v:8679$2685_Y + attribute \src "ls180.v:8679.8-8679.29" + case 1'1 + attribute \src "ls180.v:8680.5-8694.8" + switch \builder_request [1] + attribute \src "ls180.v:8680.9-8680.27" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:8682.9-8682.13" + case + attribute \src "ls180.v:8683.6-8693.9" + switch \builder_request [2] + attribute \src "ls180.v:8683.10-8683.28" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:8685.10-8685.14" + case + attribute \src "ls180.v:8686.7-8692.10" + switch \builder_request [3] + attribute \src "ls180.v:8686.11-8686.29" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:8688.11-8688.15" + case + attribute \src "ls180.v:8689.8-8691.11" + switch \builder_request [4] + attribute \src "ls180.v:8689.12-8689.30" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'001 + attribute \src "ls180.v:8698.4-8714.7" + switch $not$ls180.v:8698$2686_Y + attribute \src "ls180.v:8698.8-8698.29" + case 1'1 + attribute \src "ls180.v:8699.5-8713.8" + switch \builder_request [2] + attribute \src "ls180.v:8699.9-8699.27" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:8701.9-8701.13" + case + attribute \src "ls180.v:8702.6-8712.9" + switch \builder_request [3] + attribute \src "ls180.v:8702.10-8702.28" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:8704.10-8704.14" + case + attribute \src "ls180.v:8705.7-8711.10" + switch \builder_request [4] + attribute \src "ls180.v:8705.11-8705.29" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:8707.11-8707.15" + case + attribute \src "ls180.v:8708.8-8710.11" + switch \builder_request [0] + attribute \src "ls180.v:8708.12-8708.30" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + attribute \src "ls180.v:8717.4-8733.7" + switch $not$ls180.v:8717$2687_Y + attribute \src "ls180.v:8717.8-8717.29" + case 1'1 + attribute \src "ls180.v:8718.5-8732.8" + switch \builder_request [3] + attribute \src "ls180.v:8718.9-8718.27" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:8720.9-8720.13" + case + attribute \src "ls180.v:8721.6-8731.9" + switch \builder_request [4] + attribute \src "ls180.v:8721.10-8721.28" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:8723.10-8723.14" + case + attribute \src "ls180.v:8724.7-8730.10" + switch \builder_request [0] + attribute \src "ls180.v:8724.11-8724.29" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:8726.11-8726.15" + case + attribute \src "ls180.v:8727.8-8729.11" + switch \builder_request [1] + attribute \src "ls180.v:8727.12-8727.30" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:8736.4-8752.7" + switch $not$ls180.v:8736$2688_Y + attribute \src "ls180.v:8736.8-8736.29" + case 1'1 + attribute \src "ls180.v:8737.5-8751.8" + switch \builder_request [4] + attribute \src "ls180.v:8737.9-8737.27" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:8739.9-8739.13" + case + attribute \src "ls180.v:8740.6-8750.9" + switch \builder_request [0] + attribute \src "ls180.v:8740.10-8740.28" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:8742.10-8742.14" + case + attribute \src "ls180.v:8743.7-8749.10" + switch \builder_request [1] + attribute \src "ls180.v:8743.11-8743.29" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:8745.11-8745.15" + case + attribute \src "ls180.v:8746.8-8748.11" + switch \builder_request [2] + attribute \src "ls180.v:8746.12-8746.30" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + attribute \src "ls180.v:8755.4-8771.7" + switch $not$ls180.v:8755$2689_Y + attribute \src "ls180.v:8755.8-8755.29" + case 1'1 + attribute \src "ls180.v:8756.5-8770.8" + switch \builder_request [0] + attribute \src "ls180.v:8756.9-8756.27" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:8758.9-8758.13" + case + attribute \src "ls180.v:8759.6-8769.9" + switch \builder_request [1] + attribute \src "ls180.v:8759.10-8759.28" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:8761.10-8761.14" + case + attribute \src "ls180.v:8762.7-8768.10" + switch \builder_request [2] + attribute \src "ls180.v:8762.11-8762.29" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:8764.11-8764.15" + case + attribute \src "ls180.v:8765.8-8767.11" + switch \builder_request [3] + attribute \src "ls180.v:8765.12-8765.30" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + case + end + end + end + end + case + end + case + end + attribute \src "ls180.v:8775.2-8781.5" + switch \builder_wait + attribute \src "ls180.v:8775.6-8775.18" + case 1'1 + attribute \src "ls180.v:8776.3-8778.6" + switch $not$ls180.v:8776$2690_Y + attribute \src "ls180.v:8776.7-8776.22" + case 1'1 + assign $0\builder_count[19:0] $sub$ls180.v:8777$2691_Y + case + end + attribute \src "ls180.v:8779.6-8779.10" + case + assign $0\builder_count[19:0] 20'11110100001001000000 + end + attribute \src "ls180.v:8783.2-8813.5" + switch \builder_csrbank0_sel + attribute \src "ls180.v:8783.6-8783.26" + case 1'1 + attribute \src "ls180.v:8784.3-8812.10" + switch \builder_interface0_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface0_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank0_reset0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors0_w + case + end + case + end + attribute \src "ls180.v:8814.2-8816.5" + switch \builder_csrbank0_reset0_re + attribute \src "ls180.v:8814.6-8814.32" + case 1'1 + assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r + case + end + attribute \src "ls180.v:8818.2-8820.5" + switch \builder_csrbank0_scratch3_re + attribute \src "ls180.v:8818.6-8818.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r + case + end + attribute \src "ls180.v:8821.2-8823.5" + switch \builder_csrbank0_scratch2_re + attribute \src "ls180.v:8821.6-8821.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r + case + end + attribute \src "ls180.v:8824.2-8826.5" + switch \builder_csrbank0_scratch1_re + attribute \src "ls180.v:8824.6-8824.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r + case + end + attribute \src "ls180.v:8827.2-8829.5" + switch \builder_csrbank0_scratch0_re + attribute \src "ls180.v:8827.6-8827.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r + case + end + attribute \src "ls180.v:8832.2-8853.5" + switch \builder_csrbank1_sel + attribute \src "ls180.v:8832.6-8832.26" + case 1'1 + attribute \src "ls180.v:8833.3-8852.10" + switch \builder_interface1_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe1_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe0_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in1_w + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in0_w + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out1_w + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out0_w + case + end + case + end + attribute \src "ls180.v:8854.2-8856.5" + switch \builder_csrbank1_oe1_re + attribute \src "ls180.v:8854.6-8854.29" + case 1'1 + assign $0\main_gpio_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r + case + end + attribute \src "ls180.v:8857.2-8859.5" + switch \builder_csrbank1_oe0_re + attribute \src "ls180.v:8857.6-8857.29" + case 1'1 + assign $0\main_gpio_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r + case + end + attribute \src "ls180.v:8861.2-8863.5" + switch \builder_csrbank1_out1_re + attribute \src "ls180.v:8861.6-8861.30" + case 1'1 + assign $0\main_gpio_out_storage[15:0] [15:8] \builder_csrbank1_out1_r + case + end + attribute \src "ls180.v:8864.2-8866.5" + switch \builder_csrbank1_out0_re + attribute \src "ls180.v:8864.6-8864.30" + case 1'1 + assign $0\main_gpio_out_storage[15:0] [7:0] \builder_csrbank1_out0_r + case + end + attribute \src "ls180.v:8869.2-8878.5" + switch \builder_csrbank2_sel + attribute \src "ls180.v:8869.6-8869.26" + case 1'1 + attribute \src "ls180.v:8870.3-8877.10" + switch \builder_interface2_bank_bus_adr [0] + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\builder_interface2_bank_bus_dat_r[7:0] { 5'00000 \builder_csrbank2_w0_w } + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\builder_interface2_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank2_r_w } + case + end + case + end + attribute \src "ls180.v:8879.2-8881.5" + switch \builder_csrbank2_w0_re + attribute \src "ls180.v:8879.6-8879.28" + case 1'1 + assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r + case + end + attribute \src "ls180.v:8884.2-8914.5" + switch \builder_csrbank3_sel + attribute \src "ls180.v:8884.6-8884.26" + case 1'1 + attribute \src "ls180.v:8885.3-8913.10" + switch \builder_interface3_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period0_w + case + end + case + end + attribute \src "ls180.v:8915.2-8917.5" + switch \builder_csrbank3_enable0_re + attribute \src "ls180.v:8915.6-8915.33" + case 1'1 + assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r + case + end + attribute \src "ls180.v:8919.2-8921.5" + switch \builder_csrbank3_width3_re + attribute \src "ls180.v:8919.6-8919.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r + case + end + attribute \src "ls180.v:8922.2-8924.5" + switch \builder_csrbank3_width2_re + attribute \src "ls180.v:8922.6-8922.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r + case + end + attribute \src "ls180.v:8925.2-8927.5" + switch \builder_csrbank3_width1_re + attribute \src "ls180.v:8925.6-8925.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r + case + end + attribute \src "ls180.v:8928.2-8930.5" + switch \builder_csrbank3_width0_re + attribute \src "ls180.v:8928.6-8928.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r + case + end + attribute \src "ls180.v:8932.2-8934.5" + switch \builder_csrbank3_period3_re + attribute \src "ls180.v:8932.6-8932.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r + case + end + attribute \src "ls180.v:8935.2-8937.5" + switch \builder_csrbank3_period2_re + attribute \src "ls180.v:8935.6-8935.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r + case + end + attribute \src "ls180.v:8938.2-8940.5" + switch \builder_csrbank3_period1_re + attribute \src "ls180.v:8938.6-8938.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r + case + end + attribute \src "ls180.v:8941.2-8943.5" + switch \builder_csrbank3_period0_re + attribute \src "ls180.v:8941.6-8941.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r + case + end + attribute \src "ls180.v:8946.2-8976.5" + switch \builder_csrbank4_sel + attribute \src "ls180.v:8946.6-8946.26" + case 1'1 + attribute \src "ls180.v:8947.3-8975.10" + switch \builder_interface4_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period0_w + case + end + case + end + attribute \src "ls180.v:8977.2-8979.5" + switch \builder_csrbank4_enable0_re + attribute \src "ls180.v:8977.6-8977.33" + case 1'1 + assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r + case + end + attribute \src "ls180.v:8981.2-8983.5" + switch \builder_csrbank4_width3_re + attribute \src "ls180.v:8981.6-8981.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r + case + end + attribute \src "ls180.v:8984.2-8986.5" + switch \builder_csrbank4_width2_re + attribute \src "ls180.v:8984.6-8984.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r + case + end + attribute \src "ls180.v:8987.2-8989.5" + switch \builder_csrbank4_width1_re + attribute \src "ls180.v:8987.6-8987.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r + case + end + attribute \src "ls180.v:8990.2-8992.5" + switch \builder_csrbank4_width0_re + attribute \src "ls180.v:8990.6-8990.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r + case + end + attribute \src "ls180.v:8994.2-8996.5" + switch \builder_csrbank4_period3_re + attribute \src "ls180.v:8994.6-8994.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r + case + end + attribute \src "ls180.v:8997.2-8999.5" + switch \builder_csrbank4_period2_re + attribute \src "ls180.v:8997.6-8997.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r + case + end + attribute \src "ls180.v:9000.2-9002.5" + switch \builder_csrbank4_period1_re + attribute \src "ls180.v:9000.6-9000.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r + case + end + attribute \src "ls180.v:9003.2-9005.5" + switch \builder_csrbank4_period0_re + attribute \src "ls180.v:9003.6-9003.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r + case + end + attribute \src "ls180.v:9008.2-9056.5" + switch \builder_csrbank5_sel + attribute \src "ls180.v:9008.6-9008.26" + case 1'1 + attribute \src "ls180.v:9009.3-9055.10" + switch \builder_interface5_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base7_w + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base6_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base5_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base4_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length3_w + attribute \src "ls180.v:0.0-0.0" + case 4'1001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length2_w + attribute \src "ls180.v:0.0-0.0" + case 4'1010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'1101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_done_w } + attribute \src "ls180.v:0.0-0.0" + case 4'1110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_loop0_w } + case + end + case + end + attribute \src "ls180.v:9057.2-9059.5" + switch \builder_csrbank5_dma_base7_re + attribute \src "ls180.v:9057.6-9057.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r + case + end + attribute \src "ls180.v:9060.2-9062.5" + switch \builder_csrbank5_dma_base6_re + attribute \src "ls180.v:9060.6-9060.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r + case + end + attribute \src "ls180.v:9063.2-9065.5" + switch \builder_csrbank5_dma_base5_re + attribute \src "ls180.v:9063.6-9063.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r + case + end + attribute \src "ls180.v:9066.2-9068.5" + switch \builder_csrbank5_dma_base4_re + attribute \src "ls180.v:9066.6-9066.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r + case + end + attribute \src "ls180.v:9069.2-9071.5" + switch \builder_csrbank5_dma_base3_re + attribute \src "ls180.v:9069.6-9069.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r + case + end + attribute \src "ls180.v:9072.2-9074.5" + switch \builder_csrbank5_dma_base2_re + attribute \src "ls180.v:9072.6-9072.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r + case + end + attribute \src "ls180.v:9075.2-9077.5" + switch \builder_csrbank5_dma_base1_re + attribute \src "ls180.v:9075.6-9075.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r + case + end + attribute \src "ls180.v:9078.2-9080.5" + switch \builder_csrbank5_dma_base0_re + attribute \src "ls180.v:9078.6-9078.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r + case + end + attribute \src "ls180.v:9082.2-9084.5" + switch \builder_csrbank5_dma_length3_re + attribute \src "ls180.v:9082.6-9082.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r + case + end + attribute \src "ls180.v:9085.2-9087.5" + switch \builder_csrbank5_dma_length2_re + attribute \src "ls180.v:9085.6-9085.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r + case + end + attribute \src "ls180.v:9088.2-9090.5" + switch \builder_csrbank5_dma_length1_re + attribute \src "ls180.v:9088.6-9088.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r + case + end + attribute \src "ls180.v:9091.2-9093.5" + switch \builder_csrbank5_dma_length0_re + attribute \src "ls180.v:9091.6-9091.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r + case + end + attribute \src "ls180.v:9095.2-9097.5" + switch \builder_csrbank5_dma_enable0_re + attribute \src "ls180.v:9095.6-9095.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r + case + end + attribute \src "ls180.v:9099.2-9101.5" + switch \builder_csrbank5_dma_loop0_re + attribute \src "ls180.v:9099.6-9099.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r + case + end + attribute \src "ls180.v:9104.2-9206.5" + switch \builder_csrbank6_sel + attribute \src "ls180.v:9104.6-9104.26" + case 1'1 + attribute \src "ls180.v:9105.3-9205.10" + switch \builder_interface6_bank_bus_adr [5:0] + attribute \src "ls180.v:0.0-0.0" + case 6'000000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument3_w + attribute \src "ls180.v:0.0-0.0" + case 6'000001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument2_w + attribute \src "ls180.v:0.0-0.0" + case 6'000010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument1_w + attribute \src "ls180.v:0.0-0.0" + case 6'000011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument0_w + attribute \src "ls180.v:0.0-0.0" + case 6'000100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command3_w + attribute \src "ls180.v:0.0-0.0" + case 6'000101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command2_w + attribute \src "ls180.v:0.0-0.0" + case 6'000110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command1_w + attribute \src "ls180.v:0.0-0.0" + case 6'000111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command0_w + attribute \src "ls180.v:0.0-0.0" + case 6'001000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \main_sdcore_cmd_send_w } + attribute \src "ls180.v:0.0-0.0" + case 6'001001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response15_w + attribute \src "ls180.v:0.0-0.0" + case 6'001010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response14_w + attribute \src "ls180.v:0.0-0.0" + case 6'001011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response13_w + attribute \src "ls180.v:0.0-0.0" + case 6'001100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response12_w + attribute \src "ls180.v:0.0-0.0" + case 6'001101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response11_w + attribute \src "ls180.v:0.0-0.0" + case 6'001110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response10_w + attribute \src "ls180.v:0.0-0.0" + case 6'001111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response9_w + attribute \src "ls180.v:0.0-0.0" + case 6'010000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response8_w + attribute \src "ls180.v:0.0-0.0" + case 6'010001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response7_w + attribute \src "ls180.v:0.0-0.0" + case 6'010010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response6_w + attribute \src "ls180.v:0.0-0.0" + case 6'010011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response5_w + attribute \src "ls180.v:0.0-0.0" + case 6'010100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response4_w + attribute \src "ls180.v:0.0-0.0" + case 6'010101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response3_w + attribute \src "ls180.v:0.0-0.0" + case 6'010110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response2_w + attribute \src "ls180.v:0.0-0.0" + case 6'010111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response1_w + attribute \src "ls180.v:0.0-0.0" + case 6'011000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response0_w + attribute \src "ls180.v:0.0-0.0" + case 6'011001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_cmd_event_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_data_event_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank6_block_length1_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_length0_w + attribute \src "ls180.v:0.0-0.0" + case 6'011101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count3_w + attribute \src "ls180.v:0.0-0.0" + case 6'011110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count2_w + attribute \src "ls180.v:0.0-0.0" + case 6'011111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count1_w + attribute \src "ls180.v:0.0-0.0" + case 6'100000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count0_w + case + end + case + end + attribute \src "ls180.v:9207.2-9209.5" + switch \builder_csrbank6_cmd_argument3_re + attribute \src "ls180.v:9207.6-9207.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r + case + end + attribute \src "ls180.v:9210.2-9212.5" + switch \builder_csrbank6_cmd_argument2_re + attribute \src "ls180.v:9210.6-9210.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r + case + end + attribute \src "ls180.v:9213.2-9215.5" + switch \builder_csrbank6_cmd_argument1_re + attribute \src "ls180.v:9213.6-9213.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r + case + end + attribute \src "ls180.v:9216.2-9218.5" + switch \builder_csrbank6_cmd_argument0_re + attribute \src "ls180.v:9216.6-9216.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r + case + end + attribute \src "ls180.v:9220.2-9222.5" + switch \builder_csrbank6_cmd_command3_re + attribute \src "ls180.v:9220.6-9220.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r + case + end + attribute \src "ls180.v:9223.2-9225.5" + switch \builder_csrbank6_cmd_command2_re + attribute \src "ls180.v:9223.6-9223.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r + case + end + attribute \src "ls180.v:9226.2-9228.5" + switch \builder_csrbank6_cmd_command1_re + attribute \src "ls180.v:9226.6-9226.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r + case + end + attribute \src "ls180.v:9229.2-9231.5" + switch \builder_csrbank6_cmd_command0_re + attribute \src "ls180.v:9229.6-9229.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r + case + end + attribute \src "ls180.v:9233.2-9235.5" + switch \builder_csrbank6_block_length1_re + attribute \src "ls180.v:9233.6-9233.39" + case 1'1 + assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r + case + end + attribute \src "ls180.v:9236.2-9238.5" + switch \builder_csrbank6_block_length0_re + attribute \src "ls180.v:9236.6-9236.39" + case 1'1 + assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r + case + end + attribute \src "ls180.v:9240.2-9242.5" + switch \builder_csrbank6_block_count3_re + attribute \src "ls180.v:9240.6-9240.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r + case + end + attribute \src "ls180.v:9243.2-9245.5" + switch \builder_csrbank6_block_count2_re + attribute \src "ls180.v:9243.6-9243.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r + case + end + attribute \src "ls180.v:9246.2-9248.5" + switch \builder_csrbank6_block_count1_re + attribute \src "ls180.v:9246.6-9246.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r + case + end + attribute \src "ls180.v:9249.2-9251.5" + switch \builder_csrbank6_block_count0_re + attribute \src "ls180.v:9249.6-9249.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r + case + end + attribute \src "ls180.v:9254.2-9314.5" + switch \builder_csrbank7_sel + attribute \src "ls180.v:9254.6-9254.26" + case 1'1 + attribute \src "ls180.v:9255.3-9313.10" + switch \builder_interface7_bank_bus_adr [4:0] + attribute \src "ls180.v:0.0-0.0" + case 5'00000 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base7_w + attribute \src "ls180.v:0.0-0.0" + case 5'00001 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base6_w + attribute \src "ls180.v:0.0-0.0" + case 5'00010 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base5_w + attribute \src "ls180.v:0.0-0.0" + case 5'00011 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base4_w + attribute \src "ls180.v:0.0-0.0" + case 5'00100 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00101 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00110 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00111 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01000 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length3_w + attribute \src "ls180.v:0.0-0.0" + case 5'01001 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length2_w + attribute \src "ls180.v:0.0-0.0" + case 5'01010 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length1_w + attribute \src "ls180.v:0.0-0.0" + case 5'01011 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01100 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01101 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_done_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01110 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_loop0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01111 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset3_w + attribute \src "ls180.v:0.0-0.0" + case 5'10000 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset2_w + attribute \src "ls180.v:0.0-0.0" + case 5'10001 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset1_w + attribute \src "ls180.v:0.0-0.0" + case 5'10010 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset0_w + case + end + case + end + attribute \src "ls180.v:9315.2-9317.5" + switch \builder_csrbank7_dma_base7_re + attribute \src "ls180.v:9315.6-9315.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r + case + end + attribute \src "ls180.v:9318.2-9320.5" + switch \builder_csrbank7_dma_base6_re + attribute \src "ls180.v:9318.6-9318.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r + case + end + attribute \src "ls180.v:9321.2-9323.5" + switch \builder_csrbank7_dma_base5_re + attribute \src "ls180.v:9321.6-9321.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r + case + end + attribute \src "ls180.v:9324.2-9326.5" + switch \builder_csrbank7_dma_base4_re + attribute \src "ls180.v:9324.6-9324.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r + case + end + attribute \src "ls180.v:9327.2-9329.5" + switch \builder_csrbank7_dma_base3_re + attribute \src "ls180.v:9327.6-9327.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r + case + end + attribute \src "ls180.v:9330.2-9332.5" + switch \builder_csrbank7_dma_base2_re + attribute \src "ls180.v:9330.6-9330.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r + case + end + attribute \src "ls180.v:9333.2-9335.5" + switch \builder_csrbank7_dma_base1_re + attribute \src "ls180.v:9333.6-9333.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r + case + end + attribute \src "ls180.v:9336.2-9338.5" + switch \builder_csrbank7_dma_base0_re + attribute \src "ls180.v:9336.6-9336.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r + case + end + attribute \src "ls180.v:9340.2-9342.5" + switch \builder_csrbank7_dma_length3_re + attribute \src "ls180.v:9340.6-9340.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r + case + end + attribute \src "ls180.v:9343.2-9345.5" + switch \builder_csrbank7_dma_length2_re + attribute \src "ls180.v:9343.6-9343.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r + case + end + attribute \src "ls180.v:9346.2-9348.5" + switch \builder_csrbank7_dma_length1_re + attribute \src "ls180.v:9346.6-9346.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r + case + end + attribute \src "ls180.v:9349.2-9351.5" + switch \builder_csrbank7_dma_length0_re + attribute \src "ls180.v:9349.6-9349.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r + case + end + attribute \src "ls180.v:9353.2-9355.5" + switch \builder_csrbank7_dma_enable0_re + attribute \src "ls180.v:9353.6-9353.37" + case 1'1 + assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r + case + end + attribute \src "ls180.v:9357.2-9359.5" + switch \builder_csrbank7_dma_loop0_re + attribute \src "ls180.v:9357.6-9357.35" + case 1'1 + assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r + case + end + attribute \src "ls180.v:9362.2-9377.5" + switch \builder_csrbank8_sel + attribute \src "ls180.v:9362.6-9362.26" + case 1'1 + attribute \src "ls180.v:9363.3-9376.10" + switch \builder_interface8_bank_bus_adr [1:0] + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_card_detect_w } + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_clocker_divider1_w } + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_clocker_divider0_w + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \main_sdphy_init_initialize_w } + case + end + case + end + attribute \src "ls180.v:9378.2-9380.5" + switch \builder_csrbank8_clocker_divider1_re + attribute \src "ls180.v:9378.6-9378.42" + case 1'1 + assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r + case + end + attribute \src "ls180.v:9381.2-9383.5" + switch \builder_csrbank8_clocker_divider0_re + attribute \src "ls180.v:9381.6-9381.42" + case 1'1 + assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r + case + end + attribute \src "ls180.v:9386.2-9419.5" + switch \builder_csrbank9_sel + attribute \src "ls180.v:9386.6-9386.26" + case 1'1 + attribute \src "ls180.v:9387.3-9418.10" + switch \builder_interface9_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank9_dfii_control0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 2'00 \builder_csrbank9_dfii_pi0_command0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \main_sdram_command_issue_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 3'000 \builder_csrbank9_dfii_pi0_address1_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_address0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank9_dfii_pi0_baddress0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1001 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata0_w + case + end + case + end + attribute \src "ls180.v:9420.2-9422.5" + switch \builder_csrbank9_dfii_control0_re + attribute \src "ls180.v:9420.6-9420.39" + case 1'1 + assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r + case + end + attribute \src "ls180.v:9424.2-9426.5" + switch \builder_csrbank9_dfii_pi0_command0_re + attribute \src "ls180.v:9424.6-9424.43" + case 1'1 + assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r + case + end + attribute \src "ls180.v:9428.2-9430.5" + switch \builder_csrbank9_dfii_pi0_address1_re + attribute \src "ls180.v:9428.6-9428.43" + case 1'1 + assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r + case + end + attribute \src "ls180.v:9431.2-9433.5" + switch \builder_csrbank9_dfii_pi0_address0_re + attribute \src "ls180.v:9431.6-9431.43" + case 1'1 + assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r + case + end + attribute \src "ls180.v:9435.2-9437.5" + switch \builder_csrbank9_dfii_pi0_baddress0_re + attribute \src "ls180.v:9435.6-9435.44" + case 1'1 + assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r + case + end + attribute \src "ls180.v:9439.2-9441.5" + switch \builder_csrbank9_dfii_pi0_wrdata1_re + attribute \src "ls180.v:9439.6-9439.42" + case 1'1 + assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r + case + end + attribute \src "ls180.v:9442.2-9444.5" + switch \builder_csrbank9_dfii_pi0_wrdata0_re + attribute \src "ls180.v:9442.6-9442.42" + case 1'1 + assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r + case + end + attribute \src "ls180.v:9447.2-9471.5" + switch \builder_csrbank10_sel + attribute \src "ls180.v:9447.6-9447.27" + case 1'1 + attribute \src "ls180.v:9448.3-9470.10" + switch \builder_interface10_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control1_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control0_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_status_w } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_mosi0_w + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_miso_w + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_cs0_w } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_loopback0_w } + case + end + case + end + attribute \src "ls180.v:9472.2-9474.5" + switch \builder_csrbank10_control1_re + attribute \src "ls180.v:9472.6-9472.35" + case 1'1 + assign $0\main_spi_master_control_storage[15:0] [15:8] \builder_csrbank10_control1_r + case + end + attribute \src "ls180.v:9475.2-9477.5" + switch \builder_csrbank10_control0_re + attribute \src "ls180.v:9475.6-9475.35" + case 1'1 + assign $0\main_spi_master_control_storage[15:0] [7:0] \builder_csrbank10_control0_r + case + end + attribute \src "ls180.v:9479.2-9481.5" + switch \builder_csrbank10_mosi0_re + attribute \src "ls180.v:9479.6-9479.32" + case 1'1 + assign $0\main_spi_master_mosi_storage[7:0] \builder_csrbank10_mosi0_r + case + end + attribute \src "ls180.v:9483.2-9485.5" + switch \builder_csrbank10_cs0_re + attribute \src "ls180.v:9483.6-9483.30" + case 1'1 + assign $0\main_spi_master_cs_storage[0:0] \builder_csrbank10_cs0_r + case + end + attribute \src "ls180.v:9487.2-9489.5" + switch \builder_csrbank10_loopback0_re + attribute \src "ls180.v:9487.6-9487.36" + case 1'1 + assign $0\main_spi_master_loopback_storage[0:0] \builder_csrbank10_loopback0_r + case + end + attribute \src "ls180.v:9492.2-9522.5" + switch \builder_csrbank11_sel + attribute \src "ls180.v:9492.6-9492.27" + case 1'1 + attribute \src "ls180.v:9493.3-9521.10" + switch \builder_interface11_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_status_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_mosi0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_miso_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_cs0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_loopback0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider0_w + case + end + case + end + attribute \src "ls180.v:9523.2-9525.5" + switch \builder_csrbank11_control1_re + attribute \src "ls180.v:9523.6-9523.35" + case 1'1 + assign $0\libresocsim_control_storage[15:0] [15:8] \builder_csrbank11_control1_r + case + end + attribute \src "ls180.v:9526.2-9528.5" + switch \builder_csrbank11_control0_re + attribute \src "ls180.v:9526.6-9526.35" + case 1'1 + assign $0\libresocsim_control_storage[15:0] [7:0] \builder_csrbank11_control0_r + case + end + attribute \src "ls180.v:9530.2-9532.5" + switch \builder_csrbank11_mosi0_re + attribute \src "ls180.v:9530.6-9530.32" + case 1'1 + assign $0\libresocsim_mosi_storage[7:0] \builder_csrbank11_mosi0_r + case + end + attribute \src "ls180.v:9534.2-9536.5" + switch \builder_csrbank11_cs0_re + attribute \src "ls180.v:9534.6-9534.30" + case 1'1 + assign $0\libresocsim_cs_storage[0:0] \builder_csrbank11_cs0_r + case + end + attribute \src "ls180.v:9538.2-9540.5" + switch \builder_csrbank11_loopback0_re + attribute \src "ls180.v:9538.6-9538.36" + case 1'1 + assign $0\libresocsim_loopback_storage[0:0] \builder_csrbank11_loopback0_r + case + end + attribute \src "ls180.v:9542.2-9544.5" + switch \builder_csrbank11_clk_divider1_re + attribute \src "ls180.v:9542.6-9542.39" + case 1'1 + assign $0\libresocsim_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r + case + end + attribute \src "ls180.v:9545.2-9547.5" + switch \builder_csrbank11_clk_divider0_re + attribute \src "ls180.v:9545.6-9545.39" + case 1'1 + assign $0\libresocsim_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r + case + end + attribute \src "ls180.v:9550.2-9604.5" + switch \builder_csrbank12_sel + attribute \src "ls180.v:9550.6-9550.27" + case 1'1 + attribute \src "ls180.v:9551.3-9603.10" + switch \builder_interface12_bank_bus_adr [4:0] + attribute \src "ls180.v:0.0-0.0" + case 5'00000 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00001 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00010 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00011 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load0_w + attribute \src "ls180.v:0.0-0.0" + case 5'00100 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00101 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00110 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00111 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01000 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_en0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01001 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_update_value0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01010 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value3_w + attribute \src "ls180.v:0.0-0.0" + case 5'01011 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value2_w + attribute \src "ls180.v:0.0-0.0" + case 5'01100 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value1_w + attribute \src "ls180.v:0.0-0.0" + case 5'01101 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01110 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_status_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01111 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_pending_w } + attribute \src "ls180.v:0.0-0.0" + case 5'10000 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_ev_enable0_w } + case + end + case + end + attribute \src "ls180.v:9605.2-9607.5" + switch \builder_csrbank12_load3_re + attribute \src "ls180.v:9605.6-9605.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r + case + end + attribute \src "ls180.v:9608.2-9610.5" + switch \builder_csrbank12_load2_re + attribute \src "ls180.v:9608.6-9608.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r + case + end + attribute \src "ls180.v:9611.2-9613.5" + switch \builder_csrbank12_load1_re + attribute \src "ls180.v:9611.6-9611.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r + case + end + attribute \src "ls180.v:9614.2-9616.5" + switch \builder_csrbank12_load0_re + attribute \src "ls180.v:9614.6-9614.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r + case + end + attribute \src "ls180.v:9618.2-9620.5" + switch \builder_csrbank12_reload3_re + attribute \src "ls180.v:9618.6-9618.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r + case + end + attribute \src "ls180.v:9621.2-9623.5" + switch \builder_csrbank12_reload2_re + attribute \src "ls180.v:9621.6-9621.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r + case + end + attribute \src "ls180.v:9624.2-9626.5" + switch \builder_csrbank12_reload1_re + attribute \src "ls180.v:9624.6-9624.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r + case + end + attribute \src "ls180.v:9627.2-9629.5" + switch \builder_csrbank12_reload0_re + attribute \src "ls180.v:9627.6-9627.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r + case + end + attribute \src "ls180.v:9631.2-9633.5" + switch \builder_csrbank12_en0_re + attribute \src "ls180.v:9631.6-9631.30" + case 1'1 + assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r + case + end + attribute \src "ls180.v:9635.2-9637.5" + switch \builder_csrbank12_update_value0_re + attribute \src "ls180.v:9635.6-9635.40" + case 1'1 + assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r + case + end + attribute \src "ls180.v:9639.2-9641.5" + switch \builder_csrbank12_ev_enable0_re + attribute \src "ls180.v:9639.6-9639.37" + case 1'1 + assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r + case + end + attribute \src "ls180.v:9644.2-9671.5" + switch \builder_csrbank13_sel + attribute \src "ls180.v:9644.6-9644.27" + case 1'1 + attribute \src "ls180.v:9645.3-9670.10" + switch \builder_interface13_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface13_bank_bus_dat_r[7:0] \main_uart_rxtx_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txfull_w } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxempty_w } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_status_w } + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_pending_w } + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank13_ev_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txempty_w } + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxfull_w } + case + end + case + end + attribute \src "ls180.v:9672.2-9674.5" + switch \builder_csrbank13_ev_enable0_re + attribute \src "ls180.v:9672.6-9672.37" + case 1'1 + assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r + case + end + attribute \src "ls180.v:9677.2-9692.5" + switch \builder_csrbank14_sel + attribute \src "ls180.v:9677.6-9677.27" + case 1'1 + attribute \src "ls180.v:9678.3-9691.10" + switch \builder_interface14_bank_bus_adr [1:0] + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word3_w + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word2_w + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word1_w + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word0_w + case + end + case + end + attribute \src "ls180.v:9693.2-9695.5" + switch \builder_csrbank14_tuning_word3_re + attribute \src "ls180.v:9693.6-9693.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r + case + end + attribute \src "ls180.v:9696.2-9698.5" + switch \builder_csrbank14_tuning_word2_re + attribute \src "ls180.v:9696.6-9696.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r + case + end + attribute \src "ls180.v:9699.2-9701.5" + switch \builder_csrbank14_tuning_word1_re + attribute \src "ls180.v:9699.6-9699.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r + case + end + attribute \src "ls180.v:9702.2-9704.5" + switch \builder_csrbank14_tuning_word0_re + attribute \src "ls180.v:9702.6-9702.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r + case + end + attribute \src "ls180.v:9706.2-10001.5" + switch \sys_rst_1 + attribute \src "ls180.v:9706.6-9706.15" + case 1'1 + assign $0\main_libresocsim_reset_storage[0:0] 1'0 + assign $0\main_libresocsim_reset_re[0:0] 1'0 + assign $0\main_libresocsim_scratch_storage[31:0] 305419896 + assign $0\main_libresocsim_scratch_re[0:0] 1'0 + assign $0\main_libresocsim_bus_errors[31:0] 0 + assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 + assign $0\main_libresocsim_converter0_counter[0:0] 1'0 + assign $0\main_libresocsim_converter1_counter[0:0] 1'0 + assign $0\main_libresocsim_converter2_counter[0:0] 1'0 + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\main_libresocsim_load_storage[31:0] 0 + assign $0\main_libresocsim_load_re[0:0] 1'0 + assign $0\main_libresocsim_reload_storage[31:0] 0 + assign $0\main_libresocsim_reload_re[0:0] 1'0 + assign $0\main_libresocsim_en_storage[0:0] 1'0 + assign $0\main_libresocsim_en_re[0:0] 1'0 + assign $0\main_libresocsim_update_value_storage[0:0] 1'0 + assign $0\main_libresocsim_update_value_re[0:0] 1'0 + assign $0\main_libresocsim_value_status[31:0] 0 + assign $0\main_libresocsim_zero_pending[0:0] 1'0 + assign $0\main_libresocsim_zero_old_trigger[0:0] 1'0 + assign $0\main_libresocsim_eventmanager_storage[0:0] 1'0 + assign $0\main_libresocsim_eventmanager_re[0:0] 1'0 + assign $0\main_libresocsim_value[31:0] 0 + assign $0\main_dfi_p0_rddata_valid[0:0] 1'0 + assign $0\main_rddata_en[2:0] 3'000 + assign $0\main_sdram_storage[3:0] 4'0001 + assign $0\main_sdram_re[0:0] 1'0 + assign $0\main_sdram_command_storage[5:0] 6'000000 + assign $0\main_sdram_command_re[0:0] 1'0 + assign $0\main_sdram_address_re[0:0] 1'0 + assign $0\main_sdram_baddress_re[0:0] 1'0 + assign $0\main_sdram_wrdata_re[0:0] 1'0 + assign $0\main_sdram_status[15:0] 16'0000000000000000 + assign $0\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + assign $0\main_sdram_dfi_p0_bank[1:0] 2'00 + assign $0\main_sdram_dfi_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_we_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + assign $0\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + assign $0\main_sdram_timer_count1[9:0] 10'1100001101 + assign $0\main_sdram_postponer_req_o[0:0] 1'0 + assign $0\main_sdram_postponer_count[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'0 + assign $0\main_sdram_sequencer_counter[3:0] 4'0000 + assign $0\main_sdram_sequencer_count[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + assign $0\main_sdram_tccdcon_ready[0:0] 1'0 + assign $0\main_sdram_tccdcon_count[0:0] 1'0 + assign $0\main_sdram_twtrcon_ready[0:0] 1'0 + assign $0\main_sdram_twtrcon_count[2:0] 3'000 + assign $0\main_sdram_time0[4:0] 5'00000 + assign $0\main_sdram_time1[3:0] 4'0000 + assign $0\main_converter_counter[0:0] 1'0 + assign $0\main_cmd_consumed[0:0] 1'0 + assign $0\main_wdata_consumed[0:0] 1'0 + assign $0\main_uart_phy_storage[31:0] 9895604 + assign $0\main_uart_phy_re[0:0] 1'0 + assign $0\main_uart_phy_sink_ready[0:0] 1'0 + assign $0\main_uart_phy_uart_clk_txen[0:0] 1'0 + assign $0\main_uart_phy_tx_busy[0:0] 1'0 + assign $0\main_uart_phy_source_valid[0:0] 1'0 + assign $0\main_uart_phy_uart_clk_rxen[0:0] 1'0 + assign $0\main_uart_phy_rx_r[0:0] 1'0 + assign $0\main_uart_phy_rx_busy[0:0] 1'0 + assign $0\main_uart_tx_pending[0:0] 1'0 + assign $0\main_uart_tx_old_trigger[0:0] 1'0 + assign $0\main_uart_rx_pending[0:0] 1'0 + assign $0\main_uart_rx_old_trigger[0:0] 1'0 + assign $0\main_uart_eventmanager_storage[1:0] 2'00 + assign $0\main_uart_eventmanager_re[0:0] 1'0 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 + assign $0\main_gpio_oe_storage[15:0] 16'0000000000000000 + assign $0\main_gpio_oe_re[0:0] 1'0 + assign $0\main_gpio_out_storage[15:0] 16'0000000000000000 + assign $0\main_gpio_out_re[0:0] 1'0 + assign $0\spi_master_clk[0:0] 1'0 + assign $0\spi_master_mosi[0:0] 1'0 + assign $0\spi_master_cs_n[0:0] 1'0 + assign $0\main_spi_master_miso[7:0] 8'00000000 + assign $0\main_spi_master_control_storage[15:0] 16'0000000000000000 + assign $0\main_spi_master_control_re[0:0] 1'0 + assign $0\main_spi_master_mosi_re[0:0] 1'0 + assign $0\main_spi_master_cs_storage[0:0] 1'1 + assign $0\main_spi_master_cs_re[0:0] 1'0 + assign $0\main_spi_master_loopback_storage[0:0] 1'0 + assign $0\main_spi_master_loopback_re[0:0] 1'0 + assign $0\main_spi_master_count[2:0] 3'000 + assign $0\main_spi_master_clk_divider1[15:0] 16'0000000000000000 + assign $0\main_spi_master_mosi_data[7:0] 8'00000000 + assign $0\main_spi_master_mosi_sel[2:0] 3'000 + assign $0\main_spi_master_miso_data[7:0] 8'00000000 + assign $0\main_dummy[35:0] 36'000000000000000000000000000000000000 + assign $0\pwm0[0:0] 1'0 + assign $0\main_pwm0_enable_storage[0:0] 1'0 + assign $0\main_pwm0_enable_re[0:0] 1'0 + assign $0\main_pwm0_width_re[0:0] 1'0 + assign $0\main_pwm0_period_re[0:0] 1'0 + assign $0\pwm1[0:0] 1'0 + assign $0\main_pwm1_enable_storage[0:0] 1'0 + assign $0\main_pwm1_enable_re[0:0] 1'0 + assign $0\main_pwm1_width_re[0:0] 1'0 + assign $0\main_pwm1_period_re[0:0] 1'0 + assign $0\main_i2c_storage[2:0] 3'000 + assign $0\main_i2c_re[0:0] 1'0 + assign $0\main_sdphy_clocker_storage[8:0] 9'100000000 + assign $0\main_sdphy_clocker_re[0:0] 1'0 + assign $0\main_sdphy_clocker_clk0[0:0] 1'0 + assign $0\main_sdphy_clocker_clks[8:0] 9'000000000 + assign $0\main_sdphy_clocker_clk_d[0:0] 1'0 + assign $0\main_sdphy_init_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_timeout[31:0] 500000 + assign $0\main_sdphy_cmdr_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 + assign $0\main_sdphy_dataw_count[7:0] 8'00000000 + assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset[0:0] 1'0 + assign $0\main_sdphy_datar_timeout[31:0] 500000 + assign $0\main_sdphy_datar_count[9:0] 10'0000000000 + assign $0\main_sdphy_datar_datar_run[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset[0:0] 1'0 + assign $0\main_sdcore_cmd_argument_storage[31:0] 0 + assign $0\main_sdcore_cmd_argument_re[0:0] 1'0 + assign $0\main_sdcore_cmd_command_storage[31:0] 0 + assign $0\main_sdcore_cmd_command_re[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdcore_block_length_storage[9:0] 10'0000000000 + assign $0\main_sdcore_block_length_re[0:0] 1'0 + assign $0\main_sdcore_block_count_storage[31:0] 0 + assign $0\main_sdcore_block_count_re[0:0] 1'0 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_val[7:0] 8'00000000 + assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 + assign $0\main_sdcore_cmd_count[2:0] 3'000 + assign $0\main_sdcore_cmd_done[0:0] 1'0 + assign $0\main_sdcore_cmd_error[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout[0:0] 1'0 + assign $0\main_sdcore_data_count[31:0] 0 + assign $0\main_sdcore_data_done[0:0] 1'0 + assign $0\main_sdcore_data_error[0:0] 1'0 + assign $0\main_sdcore_data_timeout[0:0] 1'0 + assign $0\main_sdblock2mem_fifo_level[5:0] 6'000000 + assign $0\main_sdblock2mem_fifo_produce[4:0] 5'00000 + assign $0\main_sdblock2mem_fifo_consume[4:0] 5'00000 + assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + assign $0\main_sdmem2block_dma_data[31:0] 0 + assign $0\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdmem2block_dma_base_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_length_storage[31:0] 0 + assign $0\main_sdmem2block_dma_length_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_enable_storage[0:0] 1'0 + assign $0\main_sdmem2block_dma_enable_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_loop_storage[0:0] 1'0 + assign $0\main_sdmem2block_dma_loop_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_offset[31:0] 0 + assign $0\main_sdmem2block_converter_mux[1:0] 2'00 + assign $0\main_sdmem2block_fifo_level[5:0] 6'000000 + assign $0\main_sdmem2block_fifo_produce[4:0] 5'00000 + assign $0\main_sdmem2block_fifo_consume[4:0] 5'00000 + assign $0\spisdcard_clk[0:0] 1'0 + assign $0\spisdcard_mosi[0:0] 1'0 + assign $0\spisdcard_cs_n[0:0] 1'0 + assign $0\libresocsim_miso[7:0] 8'00000000 + assign $0\libresocsim_control_storage[15:0] 16'0000000000000000 + assign $0\libresocsim_control_re[0:0] 1'0 + assign $0\libresocsim_mosi_re[0:0] 1'0 + assign $0\libresocsim_cs_storage[0:0] 1'1 + assign $0\libresocsim_cs_re[0:0] 1'0 + assign $0\libresocsim_loopback_storage[0:0] 1'0 + assign $0\libresocsim_loopback_re[0:0] 1'0 + assign $0\libresocsim_count[2:0] 3'000 + assign $0\libresocsim_clk_divider1[15:0] 16'0000000000000000 + assign $0\libresocsim_mosi_data[7:0] 8'00000000 + assign $0\libresocsim_mosi_sel[2:0] 3'000 + assign $0\libresocsim_miso_data[7:0] 8'00000000 + assign $0\libresocsim_storage[15:0] 16'0000000001111101 + assign $0\libresocsim_re[0:0] 1'0 + assign $0\builder_converter0_state[0:0] 1'0 + assign $0\builder_converter1_state[0:0] 1'0 + assign $0\builder_converter2_state[0:0] 1'0 + assign $0\builder_refresher_state[1:0] 2'00 + assign $0\builder_bankmachine0_state[2:0] 3'000 + assign $0\builder_bankmachine1_state[2:0] 3'000 + assign $0\builder_bankmachine2_state[2:0] 3'000 + assign $0\builder_bankmachine3_state[2:0] 3'000 + assign $0\builder_multiplexer_state[2:0] 3'000 + assign $0\builder_new_master_wdata_ready[0:0] 1'0 + assign $0\builder_new_master_rdata_valid0[0:0] 1'0 + assign $0\builder_new_master_rdata_valid1[0:0] 1'0 + assign $0\builder_new_master_rdata_valid2[0:0] 1'0 + assign $0\builder_new_master_rdata_valid3[0:0] 1'0 + assign $0\builder_converter_state[0:0] 1'0 + assign $0\builder_spimaster0_state[1:0] 2'00 + assign $0\builder_sdphy_sdphyinit_state[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdw_state[1:0] 2'00 + assign $0\builder_sdphy_sdphycmdr_state[2:0] 3'000 + assign $0\builder_sdphy_sdphycrcr_state[0:0] 1'0 + assign $0\builder_sdphy_fsm_state[2:0] 3'000 + assign $0\builder_sdphy_sdphydatar_state[2:0] 3'000 + assign $0\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 + assign $0\builder_sdcore_fsm_state[2:0] 3'000 + assign $0\builder_sdblock2memdma_state[1:0] 2'00 + assign $0\builder_sdmem2blockdma_fsm_state[0:0] 1'0 + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + assign $0\builder_spimaster1_state[1:0] 2'00 + assign $0\builder_libresocsim_we[0:0] 1'0 + assign $0\builder_grant[2:0] 3'000 + assign $0\builder_slave_sel_r[4:0] 5'00000 + assign $0\builder_count[19:0] 20'11110100001001000000 + assign $0\builder_state[1:0] 2'00 + case + end + sync posedge \sys_clk_1 + update \spi_master_clk $0\spi_master_clk[0:0] + update \spi_master_mosi $0\spi_master_mosi[0:0] + update \spi_master_cs_n $0\spi_master_cs_n[0:0] + update \pwm0 $0\pwm0[0:0] + update \pwm1 $0\pwm1[0:0] + update \spisdcard_clk $0\spisdcard_clk[0:0] + update \spisdcard_mosi $0\spisdcard_mosi[0:0] + update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] + update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] + update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] + update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] + update \main_libresocsim_scratch_re $0\main_libresocsim_scratch_re[0:0] + update \main_libresocsim_bus_errors $0\main_libresocsim_bus_errors[31:0] + update \main_libresocsim_libresoc_constraintmanager0_uart0_tx $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] + update \main_libresocsim_converter0_counter $0\main_libresocsim_converter0_counter[0:0] + update \main_libresocsim_converter0_dat_r $0\main_libresocsim_converter0_dat_r[63:0] + update \main_libresocsim_converter1_counter $0\main_libresocsim_converter1_counter[0:0] + update \main_libresocsim_converter1_dat_r $0\main_libresocsim_converter1_dat_r[63:0] + update \main_libresocsim_converter2_counter $0\main_libresocsim_converter2_counter[0:0] + update \main_libresocsim_converter2_dat_r $0\main_libresocsim_converter2_dat_r[63:0] + update \main_libresocsim_ram_bus_ack $0\main_libresocsim_ram_bus_ack[0:0] + update \main_libresocsim_load_storage $0\main_libresocsim_load_storage[31:0] + update \main_libresocsim_load_re $0\main_libresocsim_load_re[0:0] + update \main_libresocsim_reload_storage $0\main_libresocsim_reload_storage[31:0] + update \main_libresocsim_reload_re $0\main_libresocsim_reload_re[0:0] + update \main_libresocsim_en_storage $0\main_libresocsim_en_storage[0:0] + update \main_libresocsim_en_re $0\main_libresocsim_en_re[0:0] + update \main_libresocsim_update_value_storage $0\main_libresocsim_update_value_storage[0:0] + update \main_libresocsim_update_value_re $0\main_libresocsim_update_value_re[0:0] + update \main_libresocsim_value_status $0\main_libresocsim_value_status[31:0] + update \main_libresocsim_zero_pending $0\main_libresocsim_zero_pending[0:0] + update \main_libresocsim_zero_old_trigger $0\main_libresocsim_zero_old_trigger[0:0] + update \main_libresocsim_eventmanager_storage $0\main_libresocsim_eventmanager_storage[0:0] + update \main_libresocsim_eventmanager_re $0\main_libresocsim_eventmanager_re[0:0] + update \main_libresocsim_value $0\main_libresocsim_value[31:0] + update \main_dfi_p0_rddata_valid $0\main_dfi_p0_rddata_valid[0:0] + update \main_rddata_en $0\main_rddata_en[2:0] + update \main_sdram_storage $0\main_sdram_storage[3:0] + update \main_sdram_re $0\main_sdram_re[0:0] + update \main_sdram_command_storage $0\main_sdram_command_storage[5:0] + update \main_sdram_command_re $0\main_sdram_command_re[0:0] + update \main_sdram_address_storage $0\main_sdram_address_storage[12:0] + update \main_sdram_address_re $0\main_sdram_address_re[0:0] + update \main_sdram_baddress_storage $0\main_sdram_baddress_storage[1:0] + update \main_sdram_baddress_re $0\main_sdram_baddress_re[0:0] + update \main_sdram_wrdata_storage $0\main_sdram_wrdata_storage[15:0] + update \main_sdram_wrdata_re $0\main_sdram_wrdata_re[0:0] + update \main_sdram_status $0\main_sdram_status[15:0] + update \main_sdram_dfi_p0_address $0\main_sdram_dfi_p0_address[12:0] + update \main_sdram_dfi_p0_bank $0\main_sdram_dfi_p0_bank[1:0] + update \main_sdram_dfi_p0_cas_n $0\main_sdram_dfi_p0_cas_n[0:0] + update \main_sdram_dfi_p0_cs_n $0\main_sdram_dfi_p0_cs_n[0:0] + update \main_sdram_dfi_p0_ras_n $0\main_sdram_dfi_p0_ras_n[0:0] + update \main_sdram_dfi_p0_we_n $0\main_sdram_dfi_p0_we_n[0:0] + update \main_sdram_dfi_p0_wrdata_en $0\main_sdram_dfi_p0_wrdata_en[0:0] + update \main_sdram_dfi_p0_rddata_en $0\main_sdram_dfi_p0_rddata_en[0:0] + update \main_sdram_cmd_payload_a $0\main_sdram_cmd_payload_a[12:0] + update \main_sdram_cmd_payload_ba $0\main_sdram_cmd_payload_ba[1:0] + update \main_sdram_cmd_payload_cas $0\main_sdram_cmd_payload_cas[0:0] + update \main_sdram_cmd_payload_ras $0\main_sdram_cmd_payload_ras[0:0] + update \main_sdram_cmd_payload_we $0\main_sdram_cmd_payload_we[0:0] + update \main_sdram_timer_count1 $0\main_sdram_timer_count1[9:0] + update \main_sdram_postponer_req_o $0\main_sdram_postponer_req_o[0:0] + update \main_sdram_postponer_count $0\main_sdram_postponer_count[0:0] + update \main_sdram_sequencer_done1 $0\main_sdram_sequencer_done1[0:0] + update \main_sdram_sequencer_counter $0\main_sdram_sequencer_counter[3:0] + update \main_sdram_sequencer_count $0\main_sdram_sequencer_count[0:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine0_cmd_buffer_source_valid $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_first $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_last $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine0_row $0\main_sdram_bankmachine0_row[12:0] + update \main_sdram_bankmachine0_row_opened $0\main_sdram_bankmachine0_row_opened[0:0] + update \main_sdram_bankmachine0_twtpcon_ready $0\main_sdram_bankmachine0_twtpcon_ready[0:0] + update \main_sdram_bankmachine0_twtpcon_count $0\main_sdram_bankmachine0_twtpcon_count[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine1_cmd_buffer_source_valid $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_first $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_last $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine1_row $0\main_sdram_bankmachine1_row[12:0] + update \main_sdram_bankmachine1_row_opened $0\main_sdram_bankmachine1_row_opened[0:0] + update \main_sdram_bankmachine1_twtpcon_ready $0\main_sdram_bankmachine1_twtpcon_ready[0:0] + update \main_sdram_bankmachine1_twtpcon_count $0\main_sdram_bankmachine1_twtpcon_count[2:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine2_cmd_buffer_source_valid $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_first $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_last $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine2_row $0\main_sdram_bankmachine2_row[12:0] + update \main_sdram_bankmachine2_row_opened $0\main_sdram_bankmachine2_row_opened[0:0] + update \main_sdram_bankmachine2_twtpcon_ready $0\main_sdram_bankmachine2_twtpcon_ready[0:0] + update \main_sdram_bankmachine2_twtpcon_count $0\main_sdram_bankmachine2_twtpcon_count[2:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine3_cmd_buffer_source_valid $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_first $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_last $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine3_row $0\main_sdram_bankmachine3_row[12:0] + update \main_sdram_bankmachine3_row_opened $0\main_sdram_bankmachine3_row_opened[0:0] + update \main_sdram_bankmachine3_twtpcon_ready $0\main_sdram_bankmachine3_twtpcon_ready[0:0] + update \main_sdram_bankmachine3_twtpcon_count $0\main_sdram_bankmachine3_twtpcon_count[2:0] + update \main_sdram_choose_cmd_grant $0\main_sdram_choose_cmd_grant[1:0] + update \main_sdram_choose_req_grant $0\main_sdram_choose_req_grant[1:0] + update \main_sdram_tccdcon_ready $0\main_sdram_tccdcon_ready[0:0] + update \main_sdram_tccdcon_count $0\main_sdram_tccdcon_count[0:0] + update \main_sdram_twtrcon_ready $0\main_sdram_twtrcon_ready[0:0] + update \main_sdram_twtrcon_count $0\main_sdram_twtrcon_count[2:0] + update \main_sdram_time0 $0\main_sdram_time0[4:0] + update \main_sdram_time1 $0\main_sdram_time1[3:0] + update \main_converter_counter $0\main_converter_counter[0:0] + update \main_converter_dat_r $0\main_converter_dat_r[31:0] + update \main_cmd_consumed $0\main_cmd_consumed[0:0] + update \main_wdata_consumed $0\main_wdata_consumed[0:0] + update \main_uart_phy_storage $0\main_uart_phy_storage[31:0] + update \main_uart_phy_re $0\main_uart_phy_re[0:0] + update \main_uart_phy_sink_ready $0\main_uart_phy_sink_ready[0:0] + update \main_uart_phy_uart_clk_txen $0\main_uart_phy_uart_clk_txen[0:0] + update \main_uart_phy_phase_accumulator_tx $0\main_uart_phy_phase_accumulator_tx[31:0] + update \main_uart_phy_tx_reg $0\main_uart_phy_tx_reg[7:0] + update \main_uart_phy_tx_bitcount $0\main_uart_phy_tx_bitcount[3:0] + update \main_uart_phy_tx_busy $0\main_uart_phy_tx_busy[0:0] + update \main_uart_phy_source_valid $0\main_uart_phy_source_valid[0:0] + update \main_uart_phy_source_payload_data $0\main_uart_phy_source_payload_data[7:0] + update \main_uart_phy_uart_clk_rxen $0\main_uart_phy_uart_clk_rxen[0:0] + update \main_uart_phy_phase_accumulator_rx $0\main_uart_phy_phase_accumulator_rx[31:0] + update \main_uart_phy_rx_r $0\main_uart_phy_rx_r[0:0] + update \main_uart_phy_rx_reg $0\main_uart_phy_rx_reg[7:0] + update \main_uart_phy_rx_bitcount $0\main_uart_phy_rx_bitcount[3:0] + update \main_uart_phy_rx_busy $0\main_uart_phy_rx_busy[0:0] + update \main_uart_tx_pending $0\main_uart_tx_pending[0:0] + update \main_uart_tx_old_trigger $0\main_uart_tx_old_trigger[0:0] + update \main_uart_rx_pending $0\main_uart_rx_pending[0:0] + update \main_uart_rx_old_trigger $0\main_uart_rx_old_trigger[0:0] + update \main_uart_eventmanager_storage $0\main_uart_eventmanager_storage[1:0] + update \main_uart_eventmanager_re $0\main_uart_eventmanager_re[0:0] + update \main_uart_tx_fifo_readable $0\main_uart_tx_fifo_readable[0:0] + update \main_uart_tx_fifo_level0 $0\main_uart_tx_fifo_level0[4:0] + update \main_uart_tx_fifo_produce $0\main_uart_tx_fifo_produce[3:0] + update \main_uart_tx_fifo_consume $0\main_uart_tx_fifo_consume[3:0] + update \main_uart_rx_fifo_readable $0\main_uart_rx_fifo_readable[0:0] + update \main_uart_rx_fifo_level0 $0\main_uart_rx_fifo_level0[4:0] + update \main_uart_rx_fifo_produce $0\main_uart_rx_fifo_produce[3:0] + update \main_uart_rx_fifo_consume $0\main_uart_rx_fifo_consume[3:0] + update \main_gpio_oe_storage $0\main_gpio_oe_storage[15:0] + update \main_gpio_oe_re $0\main_gpio_oe_re[0:0] + update \main_gpio_out_storage $0\main_gpio_out_storage[15:0] + update \main_gpio_out_re $0\main_gpio_out_re[0:0] + update \main_spi_master_miso $0\main_spi_master_miso[7:0] + update \main_spi_master_control_storage $0\main_spi_master_control_storage[15:0] + update \main_spi_master_control_re $0\main_spi_master_control_re[0:0] + update \main_spi_master_mosi_storage $0\main_spi_master_mosi_storage[7:0] + update \main_spi_master_mosi_re $0\main_spi_master_mosi_re[0:0] + update \main_spi_master_cs_storage $0\main_spi_master_cs_storage[0:0] + update \main_spi_master_cs_re $0\main_spi_master_cs_re[0:0] + update \main_spi_master_loopback_storage $0\main_spi_master_loopback_storage[0:0] + update \main_spi_master_loopback_re $0\main_spi_master_loopback_re[0:0] + update \main_spi_master_count $0\main_spi_master_count[2:0] + update \main_spi_master_clk_divider1 $0\main_spi_master_clk_divider1[15:0] + update \main_spi_master_mosi_data $0\main_spi_master_mosi_data[7:0] + update \main_spi_master_mosi_sel $0\main_spi_master_mosi_sel[2:0] + update \main_spi_master_miso_data $0\main_spi_master_miso_data[7:0] + update \main_dummy $0\main_dummy[35:0] + update \main_pwm0_counter $0\main_pwm0_counter[31:0] + update \main_pwm0_enable_storage $0\main_pwm0_enable_storage[0:0] + update \main_pwm0_enable_re $0\main_pwm0_enable_re[0:0] + update \main_pwm0_width_storage $0\main_pwm0_width_storage[31:0] + update \main_pwm0_width_re $0\main_pwm0_width_re[0:0] + update \main_pwm0_period_storage $0\main_pwm0_period_storage[31:0] + update \main_pwm0_period_re $0\main_pwm0_period_re[0:0] + update \main_pwm1_counter $0\main_pwm1_counter[31:0] + update \main_pwm1_enable_storage $0\main_pwm1_enable_storage[0:0] + update \main_pwm1_enable_re $0\main_pwm1_enable_re[0:0] + update \main_pwm1_width_storage $0\main_pwm1_width_storage[31:0] + update \main_pwm1_width_re $0\main_pwm1_width_re[0:0] + update \main_pwm1_period_storage $0\main_pwm1_period_storage[31:0] + update \main_pwm1_period_re $0\main_pwm1_period_re[0:0] + update \main_i2c_storage $0\main_i2c_storage[2:0] + update \main_i2c_re $0\main_i2c_re[0:0] + update \main_sdphy_clocker_storage $0\main_sdphy_clocker_storage[8:0] + update \main_sdphy_clocker_re $0\main_sdphy_clocker_re[0:0] + update \main_sdphy_clocker_clk0 $0\main_sdphy_clocker_clk0[0:0] + update \main_sdphy_clocker_clks $0\main_sdphy_clocker_clks[8:0] + update \main_sdphy_clocker_clk_d $0\main_sdphy_clocker_clk_d[0:0] + update \main_sdphy_init_count $0\main_sdphy_init_count[7:0] + update \main_sdphy_cmdw_count $0\main_sdphy_cmdw_count[7:0] + update \main_sdphy_cmdr_timeout $0\main_sdphy_cmdr_timeout[31:0] + update \main_sdphy_cmdr_count $0\main_sdphy_cmdr_count[7:0] + update \main_sdphy_cmdr_cmdr_run $0\main_sdphy_cmdr_cmdr_run[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_first $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_last $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_payload_data $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + update \main_sdphy_cmdr_cmdr_converter_demux $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] + update \main_sdphy_cmdr_cmdr_converter_strobe_all $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_valid $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_first $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_last $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_payload_data $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + update \main_sdphy_cmdr_cmdr_reset $0\main_sdphy_cmdr_cmdr_reset[0:0] + update \main_sdphy_dataw_count $0\main_sdphy_dataw_count[7:0] + update \main_sdphy_dataw_crcr_run $0\main_sdphy_dataw_crcr_run[0:0] + update \main_sdphy_dataw_crcr_converter_source_first $0\main_sdphy_dataw_crcr_converter_source_first[0:0] + update \main_sdphy_dataw_crcr_converter_source_last $0\main_sdphy_dataw_crcr_converter_source_last[0:0] + update \main_sdphy_dataw_crcr_converter_source_payload_data $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + update \main_sdphy_dataw_crcr_converter_demux $0\main_sdphy_dataw_crcr_converter_demux[2:0] + update \main_sdphy_dataw_crcr_converter_strobe_all $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + update \main_sdphy_dataw_crcr_buf_source_valid $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] + update \main_sdphy_dataw_crcr_buf_source_first $0\main_sdphy_dataw_crcr_buf_source_first[0:0] + update \main_sdphy_dataw_crcr_buf_source_last $0\main_sdphy_dataw_crcr_buf_source_last[0:0] + update \main_sdphy_dataw_crcr_buf_source_payload_data $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + update \main_sdphy_dataw_crcr_reset $0\main_sdphy_dataw_crcr_reset[0:0] + update \main_sdphy_datar_timeout $0\main_sdphy_datar_timeout[31:0] + update \main_sdphy_datar_count $0\main_sdphy_datar_count[9:0] + update \main_sdphy_datar_datar_run $0\main_sdphy_datar_datar_run[0:0] + update \main_sdphy_datar_datar_converter_source_first $0\main_sdphy_datar_datar_converter_source_first[0:0] + update \main_sdphy_datar_datar_converter_source_last $0\main_sdphy_datar_datar_converter_source_last[0:0] + update \main_sdphy_datar_datar_converter_source_payload_data $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] + update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + update \main_sdphy_datar_datar_converter_demux $0\main_sdphy_datar_datar_converter_demux[0:0] + update \main_sdphy_datar_datar_converter_strobe_all $0\main_sdphy_datar_datar_converter_strobe_all[0:0] + update \main_sdphy_datar_datar_buf_source_valid $0\main_sdphy_datar_datar_buf_source_valid[0:0] + update \main_sdphy_datar_datar_buf_source_first $0\main_sdphy_datar_datar_buf_source_first[0:0] + update \main_sdphy_datar_datar_buf_source_last $0\main_sdphy_datar_datar_buf_source_last[0:0] + update \main_sdphy_datar_datar_buf_source_payload_data $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] + update \main_sdphy_datar_datar_reset $0\main_sdphy_datar_datar_reset[0:0] + update \main_sdcore_cmd_argument_storage $0\main_sdcore_cmd_argument_storage[31:0] + update \main_sdcore_cmd_argument_re $0\main_sdcore_cmd_argument_re[0:0] + update \main_sdcore_cmd_command_storage $0\main_sdcore_cmd_command_storage[31:0] + update \main_sdcore_cmd_command_re $0\main_sdcore_cmd_command_re[0:0] + update \main_sdcore_cmd_response_status $0\main_sdcore_cmd_response_status[127:0] + update \main_sdcore_block_length_storage $0\main_sdcore_block_length_storage[9:0] + update \main_sdcore_block_length_re $0\main_sdcore_block_length_re[0:0] + update \main_sdcore_block_count_storage $0\main_sdcore_block_count_storage[31:0] + update \main_sdcore_block_count_re $0\main_sdcore_block_count_re[0:0] + update \main_sdcore_crc7_inserter_crcreg0 $0\main_sdcore_crc7_inserter_crcreg0[6:0] + update \main_sdcore_crc16_inserter_cnt $0\main_sdcore_crc16_inserter_cnt[2:0] + update \main_sdcore_crc16_inserter_crc0_crcreg0 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc1_crcreg0 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc2_crcreg0 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc3_crcreg0 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crctmp0 $0\main_sdcore_crc16_inserter_crctmp0[15:0] + update \main_sdcore_crc16_inserter_crctmp1 $0\main_sdcore_crc16_inserter_crctmp1[15:0] + update \main_sdcore_crc16_inserter_crctmp2 $0\main_sdcore_crc16_inserter_crctmp2[15:0] + update \main_sdcore_crc16_inserter_crctmp3 $0\main_sdcore_crc16_inserter_crctmp3[15:0] + update \main_sdcore_crc16_checker_val $0\main_sdcore_crc16_checker_val[7:0] + update \main_sdcore_crc16_checker_cnt $0\main_sdcore_crc16_checker_cnt[3:0] + update \main_sdcore_crc16_checker_crc0_crcreg0 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc1_crcreg0 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc2_crcreg0 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc3_crcreg0 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + update \main_sdcore_crc16_checker_crctmp0 $0\main_sdcore_crc16_checker_crctmp0[15:0] + update \main_sdcore_crc16_checker_crctmp1 $0\main_sdcore_crc16_checker_crctmp1[15:0] + update \main_sdcore_crc16_checker_crctmp2 $0\main_sdcore_crc16_checker_crctmp2[15:0] + update \main_sdcore_crc16_checker_crctmp3 $0\main_sdcore_crc16_checker_crctmp3[15:0] + update \main_sdcore_crc16_checker_fifo0 $0\main_sdcore_crc16_checker_fifo0[15:0] + update \main_sdcore_crc16_checker_fifo1 $0\main_sdcore_crc16_checker_fifo1[15:0] + update \main_sdcore_crc16_checker_fifo2 $0\main_sdcore_crc16_checker_fifo2[15:0] + update \main_sdcore_crc16_checker_fifo3 $0\main_sdcore_crc16_checker_fifo3[15:0] + update \main_sdcore_cmd_count $0\main_sdcore_cmd_count[2:0] + update \main_sdcore_cmd_done $0\main_sdcore_cmd_done[0:0] + update \main_sdcore_cmd_error $0\main_sdcore_cmd_error[0:0] + update \main_sdcore_cmd_timeout $0\main_sdcore_cmd_timeout[0:0] + update \main_sdcore_data_count $0\main_sdcore_data_count[31:0] + update \main_sdcore_data_done $0\main_sdcore_data_done[0:0] + update \main_sdcore_data_error $0\main_sdcore_data_error[0:0] + update \main_sdcore_data_timeout $0\main_sdcore_data_timeout[0:0] + update \main_sdblock2mem_fifo_level $0\main_sdblock2mem_fifo_level[5:0] + update \main_sdblock2mem_fifo_produce $0\main_sdblock2mem_fifo_produce[4:0] + update \main_sdblock2mem_fifo_consume $0\main_sdblock2mem_fifo_consume[4:0] + update \main_sdblock2mem_converter_source_first $0\main_sdblock2mem_converter_source_first[0:0] + update \main_sdblock2mem_converter_source_last $0\main_sdblock2mem_converter_source_last[0:0] + update \main_sdblock2mem_converter_source_payload_data $0\main_sdblock2mem_converter_source_payload_data[31:0] + update \main_sdblock2mem_converter_source_payload_valid_token_count $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + update \main_sdblock2mem_converter_demux $0\main_sdblock2mem_converter_demux[1:0] + update \main_sdblock2mem_converter_strobe_all $0\main_sdblock2mem_converter_strobe_all[0:0] + update \main_sdblock2mem_wishbonedmawriter_base_storage $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + update \main_sdblock2mem_wishbonedmawriter_base_re $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_length_storage $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + update \main_sdblock2mem_wishbonedmawriter_length_re $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_enable_storage $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + update \main_sdblock2mem_wishbonedmawriter_enable_re $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_loop_storage $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + update \main_sdblock2mem_wishbonedmawriter_loop_re $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_offset $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] + update \main_sdmem2block_dma_data $0\main_sdmem2block_dma_data[31:0] + update \main_sdmem2block_dma_base_storage $0\main_sdmem2block_dma_base_storage[63:0] + update \main_sdmem2block_dma_base_re $0\main_sdmem2block_dma_base_re[0:0] + update \main_sdmem2block_dma_length_storage $0\main_sdmem2block_dma_length_storage[31:0] + update \main_sdmem2block_dma_length_re $0\main_sdmem2block_dma_length_re[0:0] + update \main_sdmem2block_dma_enable_storage $0\main_sdmem2block_dma_enable_storage[0:0] + update \main_sdmem2block_dma_enable_re $0\main_sdmem2block_dma_enable_re[0:0] + update \main_sdmem2block_dma_loop_storage $0\main_sdmem2block_dma_loop_storage[0:0] + update \main_sdmem2block_dma_loop_re $0\main_sdmem2block_dma_loop_re[0:0] + update \main_sdmem2block_dma_offset $0\main_sdmem2block_dma_offset[31:0] + update \main_sdmem2block_converter_mux $0\main_sdmem2block_converter_mux[1:0] + update \main_sdmem2block_fifo_level $0\main_sdmem2block_fifo_level[5:0] + update \main_sdmem2block_fifo_produce $0\main_sdmem2block_fifo_produce[4:0] + update \main_sdmem2block_fifo_consume $0\main_sdmem2block_fifo_consume[4:0] + update \libresocsim_miso $0\libresocsim_miso[7:0] + update \libresocsim_control_storage $0\libresocsim_control_storage[15:0] + update \libresocsim_control_re $0\libresocsim_control_re[0:0] + update \libresocsim_mosi_storage $0\libresocsim_mosi_storage[7:0] + update \libresocsim_mosi_re $0\libresocsim_mosi_re[0:0] + update \libresocsim_cs_storage $0\libresocsim_cs_storage[0:0] + update \libresocsim_cs_re $0\libresocsim_cs_re[0:0] + update \libresocsim_loopback_storage $0\libresocsim_loopback_storage[0:0] + update \libresocsim_loopback_re $0\libresocsim_loopback_re[0:0] + update \libresocsim_count $0\libresocsim_count[2:0] + update \libresocsim_clk_divider1 $0\libresocsim_clk_divider1[15:0] + update \libresocsim_mosi_data $0\libresocsim_mosi_data[7:0] + update \libresocsim_mosi_sel $0\libresocsim_mosi_sel[2:0] + update \libresocsim_miso_data $0\libresocsim_miso_data[7:0] + update \libresocsim_storage $0\libresocsim_storage[15:0] + update \libresocsim_re $0\libresocsim_re[0:0] + update \builder_converter0_state $0\builder_converter0_state[0:0] + update \builder_converter1_state $0\builder_converter1_state[0:0] + update \builder_converter2_state $0\builder_converter2_state[0:0] + update \builder_refresher_state $0\builder_refresher_state[1:0] + update \builder_bankmachine0_state $0\builder_bankmachine0_state[2:0] + update \builder_bankmachine1_state $0\builder_bankmachine1_state[2:0] + update \builder_bankmachine2_state $0\builder_bankmachine2_state[2:0] + update \builder_bankmachine3_state $0\builder_bankmachine3_state[2:0] + update \builder_multiplexer_state $0\builder_multiplexer_state[2:0] + update \builder_new_master_wdata_ready $0\builder_new_master_wdata_ready[0:0] + update \builder_new_master_rdata_valid0 $0\builder_new_master_rdata_valid0[0:0] + update \builder_new_master_rdata_valid1 $0\builder_new_master_rdata_valid1[0:0] + update \builder_new_master_rdata_valid2 $0\builder_new_master_rdata_valid2[0:0] + update \builder_new_master_rdata_valid3 $0\builder_new_master_rdata_valid3[0:0] + update \builder_converter_state $0\builder_converter_state[0:0] + update \builder_spimaster0_state $0\builder_spimaster0_state[1:0] + update \builder_sdphy_sdphyinit_state $0\builder_sdphy_sdphyinit_state[0:0] + update \builder_sdphy_sdphycmdw_state $0\builder_sdphy_sdphycmdw_state[1:0] + update \builder_sdphy_sdphycmdr_state $0\builder_sdphy_sdphycmdr_state[2:0] + update \builder_sdphy_sdphycrcr_state $0\builder_sdphy_sdphycrcr_state[0:0] + update \builder_sdphy_fsm_state $0\builder_sdphy_fsm_state[2:0] + update \builder_sdphy_sdphydatar_state $0\builder_sdphy_sdphydatar_state[2:0] + update \builder_sdcore_crcupstreaminserter_state $0\builder_sdcore_crcupstreaminserter_state[0:0] + update \builder_sdcore_fsm_state $0\builder_sdcore_fsm_state[2:0] + update \builder_sdblock2memdma_state $0\builder_sdblock2memdma_state[1:0] + update \builder_sdmem2blockdma_fsm_state $0\builder_sdmem2blockdma_fsm_state[0:0] + update \builder_sdmem2blockdma_resetinserter_state $0\builder_sdmem2blockdma_resetinserter_state[1:0] + update \builder_spimaster1_state $0\builder_spimaster1_state[1:0] + update \builder_libresocsim_adr $0\builder_libresocsim_adr[13:0] + update \builder_libresocsim_we $0\builder_libresocsim_we[0:0] + update \builder_libresocsim_dat_w $0\builder_libresocsim_dat_w[7:0] + update \builder_grant $0\builder_grant[2:0] + update \builder_slave_sel_r $0\builder_slave_sel_r[4:0] + update \builder_count $0\builder_count[19:0] + update \builder_interface0_bank_bus_dat_r $0\builder_interface0_bank_bus_dat_r[7:0] + update \builder_interface1_bank_bus_dat_r $0\builder_interface1_bank_bus_dat_r[7:0] + update \builder_interface2_bank_bus_dat_r $0\builder_interface2_bank_bus_dat_r[7:0] + update \builder_interface3_bank_bus_dat_r $0\builder_interface3_bank_bus_dat_r[7:0] + update \builder_interface4_bank_bus_dat_r $0\builder_interface4_bank_bus_dat_r[7:0] + update \builder_interface5_bank_bus_dat_r $0\builder_interface5_bank_bus_dat_r[7:0] + update \builder_interface6_bank_bus_dat_r $0\builder_interface6_bank_bus_dat_r[7:0] + update \builder_interface7_bank_bus_dat_r $0\builder_interface7_bank_bus_dat_r[7:0] + update \builder_interface8_bank_bus_dat_r $0\builder_interface8_bank_bus_dat_r[7:0] + update \builder_interface9_bank_bus_dat_r $0\builder_interface9_bank_bus_dat_r[7:0] + update \builder_interface10_bank_bus_dat_r $0\builder_interface10_bank_bus_dat_r[7:0] + update \builder_interface11_bank_bus_dat_r $0\builder_interface11_bank_bus_dat_r[7:0] + update \builder_interface12_bank_bus_dat_r $0\builder_interface12_bank_bus_dat_r[7:0] + update \builder_interface13_bank_bus_dat_r $0\builder_interface13_bank_bus_dat_r[7:0] + update \builder_interface14_bank_bus_dat_r $0\builder_interface14_bank_bus_dat_r[7:0] + update \builder_state $0\builder_state[1:0] + update \builder_multiregimpl0_regs0 $0\builder_multiregimpl0_regs0[0:0] + update \builder_multiregimpl0_regs1 $0\builder_multiregimpl0_regs1[0:0] + update \builder_multiregimpl1_regs0 $0\builder_multiregimpl1_regs0[0:0] + update \builder_multiregimpl1_regs1 $0\builder_multiregimpl1_regs1[0:0] + update \builder_multiregimpl2_regs0 $0\builder_multiregimpl2_regs0[0:0] + update \builder_multiregimpl2_regs1 $0\builder_multiregimpl2_regs1[0:0] + update \builder_multiregimpl3_regs0 $0\builder_multiregimpl3_regs0[0:0] + update \builder_multiregimpl3_regs1 $0\builder_multiregimpl3_regs1[0:0] + update \builder_multiregimpl4_regs0 $0\builder_multiregimpl4_regs0[0:0] + update \builder_multiregimpl4_regs1 $0\builder_multiregimpl4_regs1[0:0] + update \builder_multiregimpl5_regs0 $0\builder_multiregimpl5_regs0[0:0] + update \builder_multiregimpl5_regs1 $0\builder_multiregimpl5_regs1[0:0] + update \builder_multiregimpl6_regs0 $0\builder_multiregimpl6_regs0[0:0] + update \builder_multiregimpl6_regs1 $0\builder_multiregimpl6_regs1[0:0] + update \builder_multiregimpl7_regs0 $0\builder_multiregimpl7_regs0[0:0] + update \builder_multiregimpl7_regs1 $0\builder_multiregimpl7_regs1[0:0] + update \builder_multiregimpl8_regs0 $0\builder_multiregimpl8_regs0[0:0] + update \builder_multiregimpl8_regs1 $0\builder_multiregimpl8_regs1[0:0] + update \builder_multiregimpl9_regs0 $0\builder_multiregimpl9_regs0[0:0] + update \builder_multiregimpl9_regs1 $0\builder_multiregimpl9_regs1[0:0] + update \builder_multiregimpl10_regs0 $0\builder_multiregimpl10_regs0[0:0] + update \builder_multiregimpl10_regs1 $0\builder_multiregimpl10_regs1[0:0] + update \builder_multiregimpl11_regs0 $0\builder_multiregimpl11_regs0[0:0] + update \builder_multiregimpl11_regs1 $0\builder_multiregimpl11_regs1[0:0] + update \builder_multiregimpl12_regs0 $0\builder_multiregimpl12_regs0[0:0] + update \builder_multiregimpl12_regs1 $0\builder_multiregimpl12_regs1[0:0] + update \builder_multiregimpl13_regs0 $0\builder_multiregimpl13_regs0[0:0] + update \builder_multiregimpl13_regs1 $0\builder_multiregimpl13_regs1[0:0] + update \builder_multiregimpl14_regs0 $0\builder_multiregimpl14_regs0[0:0] + update \builder_multiregimpl14_regs1 $0\builder_multiregimpl14_regs1[0:0] + update \builder_multiregimpl15_regs0 $0\builder_multiregimpl15_regs0[0:0] + update \builder_multiregimpl15_regs1 $0\builder_multiregimpl15_regs1[0:0] + update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0] + update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] + end + attribute \src "ls180.v:742.5-742.49" + process $proc$ls180.v:742$3056 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:743.5-743.49" + process $proc$ls180.v:743$3057 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:744.5-744.48" + process $proc$ls180.v:744$3058 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] + end + attribute \src "ls180.v:748.11-748.46" + process $proc$ls180.v:748$3059 + assign { } { } + assign $1\main_sdram_choose_req_valids[3:0] 4'0000 + sync always + sync init + update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] + end + attribute \src "ls180.v:750.11-750.45" + process $proc$ls180.v:750$3060 + assign { } { } + assign $1\main_sdram_choose_req_grant[1:0] 2'00 + sync always + sync init + update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] + end + attribute \src "ls180.v:752.12-752.36" + process $proc$ls180.v:752$3061 + assign { } { } + assign $0\main_sdram_nop_a[12:0] 13'0000000000000 + sync always + update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] + sync init + end + attribute \src "ls180.v:753.11-753.35" + process $proc$ls180.v:753$3062 + assign { } { } + assign $0\main_sdram_nop_ba[1:0] 2'00 + sync always + update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] + sync init + end + attribute \src "ls180.v:754.11-754.40" + process $proc$ls180.v:754$3063 + assign { } { } + assign $1\main_sdram_steerer_sel[1:0] 2'00 + sync always + sync init + update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] + end + attribute \src "ls180.v:755.5-755.31" + process $proc$ls180.v:755$3064 + assign { } { } + assign $0\main_sdram_steerer0[0:0] 1'1 + sync always + update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] + sync init + end + attribute \src "ls180.v:756.5-756.31" + process $proc$ls180.v:756$3065 + assign { } { } + assign $0\main_sdram_steerer1[0:0] 1'1 + sync always + update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0] + sync init + end + attribute \src "ls180.v:758.32-758.63" + process $proc$ls180.v:758$3066 + assign { } { } + assign $0\main_sdram_trrdcon_ready[0:0] 1'1 + sync always + update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0] + sync init + end + attribute \src "ls180.v:76.5-76.46" + process $proc$ls180.v:76$2782 + assign { } { } + assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0] + sync init + end + attribute \src "ls180.v:760.32-760.63" + process $proc$ls180.v:760$3067 + assign { } { } + assign $0\main_sdram_tfawcon_ready[0:0] 1'1 + sync always + update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0] + sync init + end + attribute \src "ls180.v:762.32-762.63" + process $proc$ls180.v:762$3068 + assign { } { } + assign $1\main_sdram_tccdcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] + end + attribute \src "ls180.v:763.5-763.36" + process $proc$ls180.v:763$3069 + assign { } { } + assign $1\main_sdram_tccdcon_count[0:0] 1'0 + sync always + sync init + update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] + end + attribute \src "ls180.v:765.32-765.63" + process $proc$ls180.v:765$3070 + assign { } { } + assign $1\main_sdram_twtrcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] + end + attribute \src "ls180.v:766.11-766.42" + process $proc$ls180.v:766$3071 + assign { } { } + assign $1\main_sdram_twtrcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] + end + attribute \src "ls180.v:769.5-769.26" + process $proc$ls180.v:769$3072 + assign { } { } + assign $1\main_sdram_en0[0:0] 1'0 + sync always + sync init + update \main_sdram_en0 $1\main_sdram_en0[0:0] + end + attribute \src "ls180.v:771.11-771.34" + process $proc$ls180.v:771$3073 + assign { } { } + assign $1\main_sdram_time0[4:0] 5'00000 + sync always + sync init + update \main_sdram_time0 $1\main_sdram_time0[4:0] + end + attribute \src "ls180.v:772.5-772.26" + process $proc$ls180.v:772$3074 + assign { } { } + assign $1\main_sdram_en1[0:0] 1'0 + sync always + sync init + update \main_sdram_en1 $1\main_sdram_en1[0:0] + end + attribute \src "ls180.v:774.11-774.34" + process $proc$ls180.v:774$3075 + assign { } { } + assign $1\main_sdram_time1[3:0] 4'0000 + sync always + sync init + update \main_sdram_time1 $1\main_sdram_time1[3:0] + end + attribute \src "ls180.v:795.5-795.29" + process $proc$ls180.v:795$3076 + assign { } { } + assign $1\main_wb_sdram_ack[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] + end + attribute \src "ls180.v:799.5-799.29" + process $proc$ls180.v:799$3077 + assign { } { } + assign $0\main_wb_sdram_err[0:0] 1'0 + sync always + update \main_wb_sdram_err $0\main_wb_sdram_err[0:0] + sync init + end + attribute \src "ls180.v:800.12-800.40" + process $proc$ls180.v:800$3078 + assign { } { } + assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] + end + attribute \src "ls180.v:801.12-801.42" + process $proc$ls180.v:801$3079 + assign { } { } + assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 + sync always + sync init + update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] + end + attribute \src "ls180.v:803.11-803.38" + process $proc$ls180.v:803$3080 + assign { } { } + assign $1\main_litedram_wb_sel[1:0] 2'00 + sync always + sync init + update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] + end + attribute \src "ls180.v:804.5-804.32" + process $proc$ls180.v:804$3081 + assign { } { } + assign $1\main_litedram_wb_cyc[0:0] 1'0 + sync always + sync init + update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] + end + attribute \src "ls180.v:805.5-805.32" + process $proc$ls180.v:805$3082 + assign { } { } + assign $1\main_litedram_wb_stb[0:0] 1'0 + sync always + sync init + update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] + end + attribute \src "ls180.v:807.5-807.31" + process $proc$ls180.v:807$3083 + assign { } { } + assign $1\main_litedram_wb_we[0:0] 1'0 + sync always + sync init + update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] + end + attribute \src "ls180.v:808.5-808.31" + process $proc$ls180.v:808$3084 + assign { } { } + assign $1\main_converter_skip[0:0] 1'0 + sync always + sync init + update \main_converter_skip $1\main_converter_skip[0:0] + end + attribute \src "ls180.v:809.5-809.34" + process $proc$ls180.v:809$3085 + assign { } { } + assign $1\main_converter_counter[0:0] 1'0 + sync always + sync init + update \main_converter_counter $1\main_converter_counter[0:0] + end + attribute \src "ls180.v:811.12-811.40" + process $proc$ls180.v:811$3086 + assign { } { } + assign $1\main_converter_dat_r[31:0] 0 + sync always + sync init + update \main_converter_dat_r $1\main_converter_dat_r[31:0] + end + attribute \src "ls180.v:812.5-812.29" + process $proc$ls180.v:812$3087 + assign { } { } + assign $1\main_cmd_consumed[0:0] 1'0 + sync always + sync init + update \main_cmd_consumed $1\main_cmd_consumed[0:0] + end + attribute \src "ls180.v:813.5-813.31" + process $proc$ls180.v:813$3088 + assign { } { } + assign $1\main_wdata_consumed[0:0] 1'0 + sync always + sync init + update \main_wdata_consumed $1\main_wdata_consumed[0:0] + end + attribute \src "ls180.v:817.12-817.47" + process $proc$ls180.v:817$3089 + assign { } { } + assign $1\main_uart_phy_storage[31:0] 9895604 + sync always + sync init + update \main_uart_phy_storage $1\main_uart_phy_storage[31:0] + end + attribute \src "ls180.v:818.5-818.28" + process $proc$ls180.v:818$3090 + assign { } { } + assign $1\main_uart_phy_re[0:0] 1'0 + sync always + sync init + update \main_uart_phy_re $1\main_uart_phy_re[0:0] + end + attribute \src "ls180.v:820.5-820.36" + process $proc$ls180.v:820$3091 + assign { } { } + assign $1\main_uart_phy_sink_ready[0:0] 1'0 + sync always + sync init + update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0] + end + attribute \src "ls180.v:824.5-824.39" + process $proc$ls180.v:824$3092 + assign { } { } + assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0 + sync always + sync init + update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0] + end + attribute \src "ls180.v:825.12-825.54" + process $proc$ls180.v:825$3093 + assign { } { } + assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0 + sync always + sync init + update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0] + end + attribute \src "ls180.v:826.11-826.38" + process $proc$ls180.v:826$3094 + assign { } { } + assign $1\main_uart_phy_tx_reg[7:0] 8'00000000 + sync always + sync init + update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0] + end + attribute \src "ls180.v:827.11-827.43" + process $proc$ls180.v:827$3095 + assign { } { } + assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000 + sync always + sync init + update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0] + end + attribute \src "ls180.v:828.5-828.33" + process $proc$ls180.v:828$3096 + assign { } { } + assign $1\main_uart_phy_tx_busy[0:0] 1'0 + sync always + sync init + update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0] + end + attribute \src "ls180.v:829.5-829.38" + process $proc$ls180.v:829$3097 + assign { } { } + assign $1\main_uart_phy_source_valid[0:0] 1'0 + sync always + sync init + update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0] + end + attribute \src "ls180.v:83.5-83.46" + process $proc$ls180.v:83$2783 + assign { } { } + assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0] + end + attribute \src "ls180.v:831.5-831.38" + process $proc$ls180.v:831$3098 + assign { } { } + assign $0\main_uart_phy_source_first[0:0] 1'0 + sync always + update \main_uart_phy_source_first $0\main_uart_phy_source_first[0:0] + sync init + end + attribute \src "ls180.v:832.5-832.37" + process $proc$ls180.v:832$3099 + assign { } { } + assign $0\main_uart_phy_source_last[0:0] 1'0 + sync always + update \main_uart_phy_source_last $0\main_uart_phy_source_last[0:0] + sync init + end + attribute \src "ls180.v:833.11-833.51" + process $proc$ls180.v:833$3100 + assign { } { } + assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0] + end + attribute \src "ls180.v:834.5-834.39" + process $proc$ls180.v:834$3101 + assign { } { } + assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0 + sync always + sync init + update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0] + end + attribute \src "ls180.v:835.12-835.54" + process $proc$ls180.v:835$3102 + assign { } { } + assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0 + sync always + sync init + update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0] + end + attribute \src "ls180.v:837.5-837.30" + process $proc$ls180.v:837$3103 + assign { } { } + assign $1\main_uart_phy_rx_r[0:0] 1'0 + sync always + sync init + update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0] + end + attribute \src "ls180.v:838.11-838.38" + process $proc$ls180.v:838$3104 + assign { } { } + assign $1\main_uart_phy_rx_reg[7:0] 8'00000000 + sync always + sync init + update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0] + end + attribute \src "ls180.v:839.11-839.43" + process $proc$ls180.v:839$3105 + assign { } { } + assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000 + sync always + sync init + update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0] + end + attribute \src "ls180.v:840.5-840.33" + process $proc$ls180.v:840$3106 + assign { } { } + assign $1\main_uart_phy_rx_busy[0:0] 1'0 + sync always + sync init + update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0] + end + attribute \src "ls180.v:851.5-851.32" + process $proc$ls180.v:851$3107 + assign { } { } + assign $1\main_uart_tx_pending[0:0] 1'0 + sync always + sync init + update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] + end + attribute \src "ls180.v:853.5-853.30" + process $proc$ls180.v:853$3108 + assign { } { } + assign $1\main_uart_tx_clear[0:0] 1'0 + sync always + sync init + update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] + end + attribute \src "ls180.v:854.5-854.36" + process $proc$ls180.v:854$3109 + assign { } { } + assign $1\main_uart_tx_old_trigger[0:0] 1'0 + sync always + sync init + update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] + end + attribute \src "ls180.v:856.5-856.32" + process $proc$ls180.v:856$3110 + assign { } { } + assign $1\main_uart_rx_pending[0:0] 1'0 + sync always + sync init + update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] + end + attribute \src "ls180.v:858.5-858.30" + process $proc$ls180.v:858$3111 + assign { } { } + assign $1\main_uart_rx_clear[0:0] 1'0 + sync always + sync init + update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] + end + attribute \src "ls180.v:859.5-859.36" + process $proc$ls180.v:859$3112 + assign { } { } + assign $1\main_uart_rx_old_trigger[0:0] 1'0 + sync always + sync init + update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] + end + attribute \src "ls180.v:863.11-863.49" + process $proc$ls180.v:863$3113 + assign { } { } + assign $1\main_uart_eventmanager_status_w[1:0] 2'00 + sync always + sync init + update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] + end + attribute \src "ls180.v:867.11-867.50" + process $proc$ls180.v:867$3114 + assign { } { } + assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 + sync always + sync init + update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] + end + attribute \src "ls180.v:868.11-868.48" + process $proc$ls180.v:868$3115 + assign { } { } + assign $1\main_uart_eventmanager_storage[1:0] 2'00 + sync always + sync init + update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] + end + attribute \src "ls180.v:869.5-869.37" + process $proc$ls180.v:869$3116 + assign { } { } + assign $1\main_uart_eventmanager_re[0:0] 1'0 + sync always + sync init + update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0] + end + attribute \src "ls180.v:87.5-87.46" + process $proc$ls180.v:87$2784 + assign { } { } + assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0] + sync init + end + attribute \src "ls180.v:886.5-886.40" + process $proc$ls180.v:886$3117 + assign { } { } + assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 + sync always + update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] + sync init + end + attribute \src "ls180.v:887.5-887.39" + process $proc$ls180.v:887$3118 + assign { } { } + assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 + sync always + update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] + sync init + end + attribute \src "ls180.v:895.5-895.38" + process $proc$ls180.v:895$3119 + assign { } { } + assign $1\main_uart_tx_fifo_readable[0:0] 1'0 + sync always + sync init + update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] + end + attribute \src "ls180.v:902.11-902.42" + process $proc$ls180.v:902$3120 + assign { } { } + assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 + sync always + sync init + update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] + end + attribute \src "ls180.v:903.5-903.37" + process $proc$ls180.v:903$3121 + assign { } { } + assign $0\main_uart_tx_fifo_replace[0:0] 1'0 + sync always + update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:904.11-904.43" + process $proc$ls180.v:904$3122 + assign { } { } + assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] + end + attribute \src "ls180.v:905.11-905.43" + process $proc$ls180.v:905$3123 + assign { } { } + assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] + end + attribute \src "ls180.v:906.11-906.46" + process $proc$ls180.v:906$3124 + assign { } { } + assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:932.5-932.38" + process $proc$ls180.v:932$3125 + assign { } { } + assign $1\main_uart_rx_fifo_readable[0:0] 1'0 + sync always + sync init + update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] + end + attribute \src "ls180.v:939.11-939.42" + process $proc$ls180.v:939$3126 + assign { } { } + assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 + sync always + sync init + update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] + end + attribute \src "ls180.v:940.5-940.37" + process $proc$ls180.v:940$3127 + assign { } { } + assign $0\main_uart_rx_fifo_replace[0:0] 1'0 + sync always + update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:941.11-941.43" + process $proc$ls180.v:941$3128 + assign { } { } + assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] + end + attribute \src "ls180.v:942.11-942.43" + process $proc$ls180.v:942$3129 + assign { } { } + assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] + end + attribute \src "ls180.v:943.11-943.46" + process $proc$ls180.v:943$3130 + assign { } { } + assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:958.5-958.27" + process $proc$ls180.v:958$3131 + assign { } { } + assign $0\main_uart_reset[0:0] 1'0 + sync always + update \main_uart_reset $0\main_uart_reset[0:0] + sync init + end + attribute \src "ls180.v:959.12-959.40" + process $proc$ls180.v:959$3132 + assign { } { } + assign $1\main_gpio_oe_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpio_oe_storage $1\main_gpio_oe_storage[15:0] + end + attribute \src "ls180.v:960.5-960.27" + process $proc$ls180.v:960$3133 + assign { } { } + assign $1\main_gpio_oe_re[0:0] 1'0 + sync always + sync init + update \main_gpio_oe_re $1\main_gpio_oe_re[0:0] + end + attribute \src "ls180.v:961.12-961.36" + process $proc$ls180.v:961$3134 + assign { } { } + assign $1\main_gpio_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpio_status $1\main_gpio_status[15:0] + end + attribute \src "ls180.v:963.12-963.41" + process $proc$ls180.v:963$3135 + assign { } { } + assign $1\main_gpio_out_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpio_out_storage $1\main_gpio_out_storage[15:0] + end + attribute \src "ls180.v:964.5-964.28" + process $proc$ls180.v:964$3136 + assign { } { } + assign $1\main_gpio_out_re[0:0] 1'0 + sync always + sync init + update \main_gpio_out_re $1\main_gpio_out_re[0:0] + end + attribute \src "ls180.v:970.5-970.33" + process $proc$ls180.v:970$3137 + assign { } { } + assign $1\main_spi_master_done0[0:0] 1'0 + sync always + sync init + update \main_spi_master_done0 $1\main_spi_master_done0[0:0] + end + attribute \src "ls180.v:971.5-971.31" + process $proc$ls180.v:971$3138 + assign { } { } + assign $1\main_spi_master_irq[0:0] 1'0 + sync always + sync init + update \main_spi_master_irq $1\main_spi_master_irq[0:0] + end + attribute \src "ls180.v:973.11-973.38" + process $proc$ls180.v:973$3139 + assign { } { } + assign $1\main_spi_master_miso[7:0] 8'00000000 + sync always + sync init + update \main_spi_master_miso $1\main_spi_master_miso[7:0] + end + attribute \src "ls180.v:976.12-976.48" + process $proc$ls180.v:976$3140 + assign { } { } + assign $0\main_spi_master_clk_divider0[15:0] 16'0000000000000111 + sync always + update \main_spi_master_clk_divider0 $0\main_spi_master_clk_divider0[15:0] + sync init + end + attribute \src "ls180.v:977.5-977.34" + process $proc$ls180.v:977$3141 + assign { } { } + assign $1\main_spi_master_start1[0:0] 1'0 + sync always + sync init + update \main_spi_master_start1 $1\main_spi_master_start1[0:0] + end + attribute \src "ls180.v:979.12-979.51" + process $proc$ls180.v:979$3142 + assign { } { } + assign $1\main_spi_master_control_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_spi_master_control_storage $1\main_spi_master_control_storage[15:0] + end + attribute \src "ls180.v:980.5-980.38" + process $proc$ls180.v:980$3143 + assign { } { } + assign $1\main_spi_master_control_re[0:0] 1'0 + sync always + sync init + update \main_spi_master_control_re $1\main_spi_master_control_re[0:0] + end + attribute \src "ls180.v:984.11-984.46" + process $proc$ls180.v:984$3144 + assign { } { } + assign $1\main_spi_master_mosi_storage[7:0] 8'00000000 + sync always + sync init + update \main_spi_master_mosi_storage $1\main_spi_master_mosi_storage[7:0] + end + attribute \src "ls180.v:985.5-985.35" + process $proc$ls180.v:985$3145 + assign { } { } + assign $1\main_spi_master_mosi_re[0:0] 1'0 + sync always + sync init + update \main_spi_master_mosi_re $1\main_spi_master_mosi_re[0:0] + end + attribute \src "ls180.v:989.5-989.38" + process $proc$ls180.v:989$3146 + assign { } { } + assign $1\main_spi_master_cs_storage[0:0] 1'1 + sync always + sync init + update \main_spi_master_cs_storage $1\main_spi_master_cs_storage[0:0] + end + attribute \src "ls180.v:990.5-990.33" + process $proc$ls180.v:990$3147 + assign { } { } + assign $1\main_spi_master_cs_re[0:0] 1'0 + sync always + sync init + update \main_spi_master_cs_re $1\main_spi_master_cs_re[0:0] + end + attribute \src "ls180.v:991.5-991.44" + process $proc$ls180.v:991$3148 + assign { } { } + assign $1\main_spi_master_loopback_storage[0:0] 1'0 + sync always + sync init + update \main_spi_master_loopback_storage $1\main_spi_master_loopback_storage[0:0] + end + attribute \src "ls180.v:992.5-992.39" + process $proc$ls180.v:992$3149 + assign { } { } + assign $1\main_spi_master_loopback_re[0:0] 1'0 + sync always + sync init + update \main_spi_master_loopback_re $1\main_spi_master_loopback_re[0:0] + end + attribute \src "ls180.v:993.5-993.38" + process $proc$ls180.v:993$3150 + assign { } { } + assign $1\main_spi_master_clk_enable[0:0] 1'0 + sync always + sync init + update \main_spi_master_clk_enable $1\main_spi_master_clk_enable[0:0] + end + attribute \src "ls180.v:994.5-994.37" + process $proc$ls180.v:994$3151 + assign { } { } + assign $1\main_spi_master_cs_enable[0:0] 1'0 + sync always + sync init + update \main_spi_master_cs_enable $1\main_spi_master_cs_enable[0:0] + end + attribute \src "ls180.v:995.11-995.39" + process $proc$ls180.v:995$3152 + assign { } { } + assign $1\main_spi_master_count[2:0] 3'000 + sync always + sync init + update \main_spi_master_count $1\main_spi_master_count[2:0] + end + attribute \src "ls180.v:996.5-996.38" + process $proc$ls180.v:996$3153 + assign { } { } + assign $1\main_spi_master_mosi_latch[0:0] 1'0 + sync always + sync init + update \main_spi_master_mosi_latch $1\main_spi_master_mosi_latch[0:0] + end + attribute \src "ls180.v:997.5-997.38" + process $proc$ls180.v:997$3154 + assign { } { } + assign $1\main_spi_master_miso_latch[0:0] 1'0 + sync always + sync init + update \main_spi_master_miso_latch $1\main_spi_master_miso_latch[0:0] + end + attribute \src "ls180.v:998.12-998.48" + process $proc$ls180.v:998$3155 + assign { } { } + assign $1\main_spi_master_clk_divider1[15:0] 16'0000000000000000 + sync always + sync init + update \main_spi_master_clk_divider1 $1\main_spi_master_clk_divider1[15:0] + end + connect \main_libresocsim_libresoc_reset \main_libresocsim_reset + connect \main_libresocsim_libresoc_clk_sel \sys_clksel_i + connect \sys_pll_48_o \main_libresocsim_libresoc_pll_48_o + connect \uart_tx \main_libresocsim_libresoc_constraintmanager1_uart0_tx + connect \main_libresocsim_libresoc_constraintmanager1_uart0_rx \uart_rx + connect \main_libresocsim_libresoc_constraintmanager1_gpio0_i \gpio_i + connect \gpio_o \main_libresocsim_libresoc_constraintmanager1_gpio0_o + connect \gpio_oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe + connect \main_libresocsim_libresoc_jtag_tck \jtag_tck + connect \main_libresocsim_libresoc_jtag_tms \jtag_tms + connect \main_libresocsim_libresoc_jtag_tdi \jtag_tdi + connect \jtag_tdo \main_libresocsim_libresoc_jtag_tdo + connect \main_nc \nc + connect \main_sdblock2mem_sink_sink_valid0 \main_sdcore_source_source_valid + connect \main_sdcore_source_source_ready \main_sdblock2mem_sink_sink_ready0 + connect \main_sdblock2mem_sink_sink_first \main_sdcore_source_source_first + connect \main_sdblock2mem_sink_sink_last \main_sdcore_source_source_last + connect \main_sdblock2mem_sink_sink_payload_data0 \main_sdcore_source_source_payload_data + connect \main_sdcore_sink_sink_valid \main_sdmem2block_source_source_valid0 + connect \main_sdmem2block_source_source_ready0 \main_sdcore_sink_sink_ready + connect \main_sdcore_sink_sink_first \main_sdmem2block_source_source_first0 + connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0 + connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0 + connect \main_libresocsim_bus_error \builder_error + connect \main_libresocsim_converter0_reset $not$ls180.v:2757$14_Y + connect \main_libresocsim_libresoc_ibus_dat_r { \main_libresocsim_interface0_converted_interface_dat_r \main_libresocsim_converter0_dat_r [63:32] } + connect \main_libresocsim_converter1_reset $not$ls180.v:2817$25_Y + connect \main_libresocsim_libresoc_dbus_dat_r { \main_libresocsim_interface1_converted_interface_dat_r \main_libresocsim_converter1_dat_r [63:32] } + connect \main_libresocsim_converter2_reset $not$ls180.v:2877$36_Y + connect \main_libresocsim_libresoc_jtag_wb_dat_r { \main_libresocsim_interface2_converted_interface_dat_r \main_libresocsim_converter2_dat_r [63:32] } + connect \main_libresocsim_reset \main_libresocsim_reset_re + connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors + connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [6:0] + connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r + connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w + connect \main_libresocsim_zero_trigger $ne$ls180.v:2949$60_Y + connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status + connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending + connect \main_libresocsim_irq $and$ls180.v:2958$63_Y + connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger + connect \sys_clk_1 \sys_clk + connect \por_clk \sys_clk + connect \sys_rst_1 \main_int_rst + connect \main_dfi_p0_address \main_sdram_master_p0_address + connect \main_dfi_p0_bank \main_sdram_master_p0_bank + connect \main_dfi_p0_cas_n \main_sdram_master_p0_cas_n + connect \main_dfi_p0_cs_n \main_sdram_master_p0_cs_n + connect \main_dfi_p0_ras_n \main_sdram_master_p0_ras_n + connect \main_dfi_p0_we_n \main_sdram_master_p0_we_n + connect \main_dfi_p0_cke \main_sdram_master_p0_cke + connect \main_dfi_p0_odt \main_sdram_master_p0_odt + connect \main_dfi_p0_reset_n \main_sdram_master_p0_reset_n + connect \main_dfi_p0_act_n \main_sdram_master_p0_act_n + connect \main_dfi_p0_wrdata \main_sdram_master_p0_wrdata + connect \main_dfi_p0_wrdata_en \main_sdram_master_p0_wrdata_en + connect \main_dfi_p0_wrdata_mask \main_sdram_master_p0_wrdata_mask + connect \main_dfi_p0_rddata_en \main_sdram_master_p0_rddata_en + connect \main_sdram_master_p0_rddata \main_dfi_p0_rddata + connect \main_sdram_master_p0_rddata_valid \main_dfi_p0_rddata_valid + connect \main_sdram_slave_p0_address \main_sdram_dfi_p0_address + connect \main_sdram_slave_p0_bank \main_sdram_dfi_p0_bank + connect \main_sdram_slave_p0_cas_n \main_sdram_dfi_p0_cas_n + connect \main_sdram_slave_p0_cs_n \main_sdram_dfi_p0_cs_n + connect \main_sdram_slave_p0_ras_n \main_sdram_dfi_p0_ras_n + connect \main_sdram_slave_p0_we_n \main_sdram_dfi_p0_we_n + connect \main_sdram_slave_p0_cke \main_sdram_dfi_p0_cke + connect \main_sdram_slave_p0_odt \main_sdram_dfi_p0_odt + connect \main_sdram_slave_p0_reset_n \main_sdram_dfi_p0_reset_n + connect \main_sdram_slave_p0_act_n \main_sdram_dfi_p0_act_n + connect \main_sdram_slave_p0_wrdata \main_sdram_dfi_p0_wrdata + connect \main_sdram_slave_p0_wrdata_en \main_sdram_dfi_p0_wrdata_en + connect \main_sdram_slave_p0_wrdata_mask \main_sdram_dfi_p0_wrdata_mask + connect \main_sdram_slave_p0_rddata_en \main_sdram_dfi_p0_rddata_en + connect \main_sdram_dfi_p0_rddata \main_sdram_slave_p0_rddata + connect \main_sdram_dfi_p0_rddata_valid \main_sdram_slave_p0_rddata_valid + connect \main_sdram_inti_p0_cke \main_sdram_cke + connect \main_sdram_inti_p0_odt \main_sdram_odt + connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n + connect \main_sdram_inti_p0_address \main_sdram_address_storage + connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage + connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3072$70_Y + connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3073$71_Y + connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage + connect \main_sdram_inti_p0_wrdata_mask 2'00 + connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid + connect \main_sdram_interface_bank0_ready \main_sdram_bankmachine0_req_ready + connect \main_sdram_bankmachine0_req_we \main_sdram_interface_bank0_we + connect \main_sdram_bankmachine0_req_addr \main_sdram_interface_bank0_addr + connect \main_sdram_interface_bank0_lock \main_sdram_bankmachine0_req_lock + connect \main_sdram_interface_bank0_wdata_ready \main_sdram_bankmachine0_req_wdata_ready + connect \main_sdram_interface_bank0_rdata_valid \main_sdram_bankmachine0_req_rdata_valid + connect \main_sdram_bankmachine1_req_valid \main_sdram_interface_bank1_valid + connect \main_sdram_interface_bank1_ready \main_sdram_bankmachine1_req_ready + connect \main_sdram_bankmachine1_req_we \main_sdram_interface_bank1_we + connect \main_sdram_bankmachine1_req_addr \main_sdram_interface_bank1_addr + connect \main_sdram_interface_bank1_lock \main_sdram_bankmachine1_req_lock + connect \main_sdram_interface_bank1_wdata_ready \main_sdram_bankmachine1_req_wdata_ready + connect \main_sdram_interface_bank1_rdata_valid \main_sdram_bankmachine1_req_rdata_valid + connect \main_sdram_bankmachine2_req_valid \main_sdram_interface_bank2_valid + connect \main_sdram_interface_bank2_ready \main_sdram_bankmachine2_req_ready + connect \main_sdram_bankmachine2_req_we \main_sdram_interface_bank2_we + connect \main_sdram_bankmachine2_req_addr \main_sdram_interface_bank2_addr + connect \main_sdram_interface_bank2_lock \main_sdram_bankmachine2_req_lock + connect \main_sdram_interface_bank2_wdata_ready \main_sdram_bankmachine2_req_wdata_ready + connect \main_sdram_interface_bank2_rdata_valid \main_sdram_bankmachine2_req_rdata_valid + connect \main_sdram_bankmachine3_req_valid \main_sdram_interface_bank3_valid + connect \main_sdram_interface_bank3_ready \main_sdram_bankmachine3_req_ready + connect \main_sdram_bankmachine3_req_we \main_sdram_interface_bank3_we + connect \main_sdram_bankmachine3_req_addr \main_sdram_interface_bank3_addr + connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock + connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready + connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid + connect \main_sdram_timer_wait $not$ls180.v:3104$72_Y + connect \main_sdram_postponer_req_i \main_sdram_timer_done0 + connect \main_sdram_wants_refresh \main_sdram_postponer_req_o + connect \main_sdram_timer_done1 $eq$ls180.v:3107$73_Y + connect \main_sdram_timer_done0 \main_sdram_timer_done1 + connect \main_sdram_timer_count0 \main_sdram_timer_count1 + connect \main_sdram_sequencer_start1 $or$ls180.v:3110$75_Y + connect \main_sdram_sequencer_done0 $and$ls180.v:3111$77_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid + connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine0_req_addr + connect \main_sdram_bankmachine0_cmd_buffer_sink_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine0_cmd_buffer_sink_ready + connect \main_sdram_bankmachine0_cmd_buffer_sink_first \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3153$79_Y + connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3154$80_Y + connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3155$81_Y + connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 + connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3165$86_Y + connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3166$88_Y + connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3167$90_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3199$98_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3200$99_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3203$100_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3204$101_Y + connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3205$103_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid + connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine1_req_addr + connect \main_sdram_bankmachine1_cmd_buffer_sink_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine1_cmd_buffer_sink_ready + connect \main_sdram_bankmachine1_cmd_buffer_sink_first \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3310$109_Y + connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3311$110_Y + connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3312$111_Y + connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 + connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3322$116_Y + connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3323$118_Y + connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3324$120_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3356$128_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3357$129_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3360$130_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3361$131_Y + connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3362$133_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid + connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine2_req_addr + connect \main_sdram_bankmachine2_cmd_buffer_sink_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine2_cmd_buffer_sink_ready + connect \main_sdram_bankmachine2_cmd_buffer_sink_first \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3467$139_Y + connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3468$140_Y + connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3469$141_Y + connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 + connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3479$146_Y + connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3480$148_Y + connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3481$150_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3513$158_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3514$159_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3517$160_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3518$161_Y + connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3519$163_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid + connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine3_req_addr + connect \main_sdram_bankmachine3_cmd_buffer_sink_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine3_cmd_buffer_sink_ready + connect \main_sdram_bankmachine3_cmd_buffer_sink_first \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3624$169_Y + connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3625$170_Y + connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3626$171_Y + connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 + connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3636$176_Y + connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3637$178_Y + connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3638$180_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3670$188_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3671$189_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3674$190_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3675$191_Y + connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3676$193_Y + connect \main_sdram_choose_req_want_cmds 1'1 + connect \main_sdram_trrdcon_valid $and$ls180.v:3772$204_Y + connect \main_sdram_tfawcon_valid $and$ls180.v:3773$210_Y + connect \main_sdram_ras_allowed $and$ls180.v:3774$211_Y + connect \main_sdram_tccdcon_valid $and$ls180.v:3775$214_Y + connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready + connect \main_sdram_twtrcon_valid $and$ls180.v:3777$216_Y + connect \main_sdram_read_available $or$ls180.v:3778$223_Y + connect \main_sdram_write_available $or$ls180.v:3779$230_Y + connect \main_sdram_max_time0 $eq$ls180.v:3780$231_Y + connect \main_sdram_max_time1 $eq$ls180.v:3781$232_Y + connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid + connect \main_sdram_go_to_refresh $and$ls180.v:3786$235_Y + connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata + connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata + connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3789$236_Y + connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids + connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 + connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 + connect \main_sdram_choose_cmd_cmd_payload_ba \builder_comb_rhs_array_muxed2 + connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 + connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 + connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 + connect \main_sdram_choose_cmd_ce $or$ls180.v:3822$294_Y + connect \main_sdram_choose_req_request \main_sdram_choose_req_valids + connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 + connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 + connect \main_sdram_choose_req_cmd_payload_ba \builder_comb_rhs_array_muxed8 + connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 + connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 + connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 + connect \main_sdram_choose_req_ce $or$ls180.v:3891$380_Y + connect \main_sdram_dfi_p0_reset_n 1'1 + connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 + connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 + connect \builder_roundrobin0_request $and$ls180.v:3968$412_Y + connect \builder_roundrobin0_ce $and$ls180.v:3969$415_Y + connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 + connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 + connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 + connect \builder_roundrobin1_request $and$ls180.v:3973$428_Y + connect \builder_roundrobin1_ce $and$ls180.v:3974$431_Y + connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 + connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 + connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 + connect \builder_roundrobin2_request $and$ls180.v:3978$444_Y + connect \builder_roundrobin2_ce $and$ls180.v:3979$447_Y + connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 + connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 + connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 + connect \builder_roundrobin3_request $and$ls180.v:3983$460_Y + connect \builder_roundrobin3_ce $and$ls180.v:3984$463_Y + connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 + connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 + connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 + connect \main_port_cmd_ready $or$ls180.v:3988$527_Y + connect \main_port_wdata_ready \builder_new_master_wdata_ready + connect \main_port_rdata_valid \builder_new_master_rdata_valid3 + connect \main_port_rdata_payload_data \main_sdram_interface_rdata + connect \builder_roundrobin0_grant 1'0 + connect \builder_roundrobin1_grant 1'0 + connect \builder_roundrobin2_grant 1'0 + connect \builder_roundrobin3_grant 1'0 + connect \main_converter_reset $not$ls180.v:4010$529_Y + connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } + connect \main_port_cmd_payload_addr $sub$ls180.v:4070$540_Y [23:0] + connect \main_port_cmd_payload_we \main_litedram_wb_we + connect \main_port_wdata_payload_data \main_litedram_wb_dat_w + connect \main_port_wdata_payload_we \main_litedram_wb_sel + connect \main_litedram_wb_dat_r \main_port_rdata_payload_data + connect \main_port_flush $not$ls180.v:4075$541_Y + connect \main_port_cmd_last $not$ls180.v:4076$542_Y + connect \main_port_cmd_valid $and$ls180.v:4077$545_Y + connect \main_port_wdata_valid $and$ls180.v:4078$549_Y + connect \main_port_rdata_ready $and$ls180.v:4079$552_Y + connect \main_litedram_wb_ack $and$ls180.v:4080$557_Y + connect \main_ack_cmd $or$ls180.v:4081$559_Y + connect \main_ack_wdata $or$ls180.v:4082$561_Y + connect \main_ack_rdata $and$ls180.v:4083$562_Y + connect \main_uart_uart_sink_valid \main_uart_phy_source_valid + connect \main_uart_phy_source_ready \main_uart_uart_sink_ready + connect \main_uart_uart_sink_first \main_uart_phy_source_first + connect \main_uart_uart_sink_last \main_uart_phy_source_last + connect \main_uart_uart_sink_payload_data \main_uart_phy_source_payload_data + connect \main_uart_phy_sink_valid \main_uart_uart_source_valid + connect \main_uart_uart_source_ready \main_uart_phy_sink_ready + connect \main_uart_phy_sink_first \main_uart_uart_source_first + connect \main_uart_phy_sink_last \main_uart_uart_source_last + connect \main_uart_phy_sink_payload_data \main_uart_uart_source_payload_data + connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re + connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r + connect \main_uart_txfull_status $not$ls180.v:4096$563_Y + connect \main_uart_txempty_status $not$ls180.v:4097$564_Y + connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid + connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready + connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first + connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last + connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data + connect \main_uart_tx_trigger $not$ls180.v:4103$565_Y + connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid + connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready + connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first + connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last + connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data + connect \main_uart_rxempty_status $not$ls180.v:4109$566_Y + connect \main_uart_rxfull_status $not$ls180.v:4110$567_Y + connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data + connect \main_uart_rx_fifo_source_ready $or$ls180.v:4112$569_Y + connect \main_uart_rx_trigger $not$ls180.v:4113$570_Y + connect \main_uart_irq $or$ls180.v:4136$579_Y + connect \main_uart_tx_status \main_uart_tx_trigger + connect \main_uart_rx_status \main_uart_rx_trigger + connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data } + connect { \main_uart_tx_fifo_fifo_out_last \main_uart_tx_fifo_fifo_out_first \main_uart_tx_fifo_fifo_out_payload_data } \main_uart_tx_fifo_syncfifo_dout + connect \main_uart_tx_fifo_sink_ready \main_uart_tx_fifo_syncfifo_writable + connect \main_uart_tx_fifo_syncfifo_we \main_uart_tx_fifo_sink_valid + connect \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_sink_first + connect \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_sink_last + connect \main_uart_tx_fifo_fifo_in_payload_data \main_uart_tx_fifo_sink_payload_data + connect \main_uart_tx_fifo_source_valid \main_uart_tx_fifo_readable + connect \main_uart_tx_fifo_source_first \main_uart_tx_fifo_fifo_out_first + connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last + connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data + connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready + connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4151$582_Y + connect \main_uart_tx_fifo_level1 $add$ls180.v:4152$583_Y + connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din + connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4162$587_Y + connect \main_uart_tx_fifo_do_read $and$ls180.v:4163$588_Y + connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume + connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r + connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read + connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4167$589_Y + connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4168$590_Y + connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data } + connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout + connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable + connect \main_uart_rx_fifo_syncfifo_we \main_uart_rx_fifo_sink_valid + connect \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_sink_first + connect \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_sink_last + connect \main_uart_rx_fifo_fifo_in_payload_data \main_uart_rx_fifo_sink_payload_data + connect \main_uart_rx_fifo_source_valid \main_uart_rx_fifo_readable + connect \main_uart_rx_fifo_source_first \main_uart_rx_fifo_fifo_out_first + connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last + connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data + connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready + connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4181$593_Y + connect \main_uart_rx_fifo_level1 $add$ls180.v:4182$594_Y + connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din + connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4192$598_Y + connect \main_uart_rx_fifo_do_read $and$ls180.v:4193$599_Y + connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume + connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r + connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read + connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4197$600_Y + connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4198$601_Y + connect \main_gpio_pads_i \main_libresocsim_libresoc_constraintmanager0_gpio0_i + connect \main_libresocsim_libresoc_constraintmanager0_gpio0_o \main_gpio_pads_o + connect \main_libresocsim_libresoc_constraintmanager0_gpio0_oe \main_gpio_pads_oe + connect \main_gpio_pads_oe \main_gpio_oe_storage + connect \main_gpio_pads_o \main_gpio_out_storage + connect \main_spi_master_start0 \main_spi_master_start1 + connect \main_spi_master_length0 \main_spi_master_length1 + connect \main_spi_master_mosi \main_spi_master_mosi_storage + connect \main_spi_master_done1 \main_spi_master_done0 + connect \main_spi_master_miso_status \main_spi_master_miso + connect \main_spi_master_cs \main_spi_master_cs_storage + connect \main_spi_master_loopback \main_spi_master_loopback_storage + connect \main_spi_master_clk_rise $eq$ls180.v:4211$603_Y + connect \main_spi_master_clk_fall $eq$ls180.v:4212$605_Y + connect \i2c_scl \main_i2c_scl + connect \i2c_sda_oe \main_i2c_oe + connect \i2c_sda_o \main_i2c_sda0 + connect \main_i2c_sda1 \i2c_sda_i + connect \main_sdphy_status 1'0 + connect \main_sdphy_sdpads_clk $or$ls180.v:4267$613_Y + connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4268$617_Y + connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4269$621_Y + connect \main_sdphy_sdpads_data_oe $or$ls180.v:4270$625_Y + connect \main_sdphy_sdpads_data_o $or$ls180.v:4271$629_Y + connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_dataw_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_datar_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_init_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_init_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_init_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_cmdw_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_cmdw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_cmdw_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_cmdr_pads_in_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_cmdr_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_dataw_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_dataw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_dataw_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_clocker_stop $or$ls180.v:4292$630_Y + connect \main_sdphy_clocker_ce $and$ls180.v:4322$633_Y + connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid + connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready + connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first + connect \main_sdphy_cmdr_cmdr_pads_in_last \main_sdphy_cmdr_pads_in_pads_in_last + connect \main_sdphy_cmdr_cmdr_pads_in_payload_clk \main_sdphy_cmdr_pads_in_pads_in_payload_clk + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe + connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4445$643_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4446$645_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1 + connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready + connect \main_sdphy_cmdr_cmdr_buf_sink_first \main_sdphy_cmdr_cmdr_source_source_first1 + connect \main_sdphy_cmdr_cmdr_buf_sink_last \main_sdphy_cmdr_cmdr_source_source_last1 + connect \main_sdphy_cmdr_cmdr_buf_sink_payload_data \main_sdphy_cmdr_cmdr_source_source_payload_data1 + connect \main_sdphy_cmdr_cmdr_source_source_valid0 \main_sdphy_cmdr_cmdr_buf_source_valid + connect \main_sdphy_cmdr_cmdr_buf_source_ready \main_sdphy_cmdr_cmdr_source_source_ready0 + connect \main_sdphy_cmdr_cmdr_source_source_first0 \main_sdphy_cmdr_cmdr_buf_source_first + connect \main_sdphy_cmdr_cmdr_source_source_last0 \main_sdphy_cmdr_cmdr_buf_source_last + connect \main_sdphy_cmdr_cmdr_source_source_payload_data0 \main_sdphy_cmdr_cmdr_buf_source_payload_data + connect \main_sdphy_cmdr_cmdr_source_source_valid1 \main_sdphy_cmdr_cmdr_converter_source_valid + connect \main_sdphy_cmdr_cmdr_converter_source_ready \main_sdphy_cmdr_cmdr_source_source_ready1 + connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first + connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last + connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data + connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4463$647_Y + connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all + connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4465$648_Y + connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4466$650_Y + connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid + connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready + connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first + connect \main_sdphy_dataw_crcr_pads_in_last \main_sdphy_dataw_pads_in_pads_in_last + connect \main_sdphy_dataw_crcr_pads_in_payload_clk \main_sdphy_dataw_pads_in_pads_in_payload_clk + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_i \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_o \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i + connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o + connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe + connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4572$665_Y + connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4573$666_Y + connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] + connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1 + connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready + connect \main_sdphy_dataw_crcr_buf_sink_first \main_sdphy_dataw_crcr_source_source_first1 + connect \main_sdphy_dataw_crcr_buf_sink_last \main_sdphy_dataw_crcr_source_source_last1 + connect \main_sdphy_dataw_crcr_buf_sink_payload_data \main_sdphy_dataw_crcr_source_source_payload_data1 + connect \main_sdphy_dataw_crcr_source_source_valid0 \main_sdphy_dataw_crcr_buf_source_valid + connect \main_sdphy_dataw_crcr_buf_source_ready \main_sdphy_dataw_crcr_source_source_ready0 + connect \main_sdphy_dataw_crcr_source_source_first0 \main_sdphy_dataw_crcr_buf_source_first + connect \main_sdphy_dataw_crcr_source_source_last0 \main_sdphy_dataw_crcr_buf_source_last + connect \main_sdphy_dataw_crcr_source_source_payload_data0 \main_sdphy_dataw_crcr_buf_source_payload_data + connect \main_sdphy_dataw_crcr_source_source_valid1 \main_sdphy_dataw_crcr_converter_source_valid + connect \main_sdphy_dataw_crcr_converter_source_ready \main_sdphy_dataw_crcr_source_source_ready1 + connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first + connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last + connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data + connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4590$668_Y + connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all + connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4592$669_Y + connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4593$671_Y + connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid + connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready + connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first + connect \main_sdphy_datar_datar_pads_in_last \main_sdphy_datar_pads_in_pads_in_last + connect \main_sdphy_datar_datar_pads_in_payload_clk \main_sdphy_datar_pads_in_pads_in_payload_clk + connect \main_sdphy_datar_datar_pads_in_payload_cmd_i \main_sdphy_datar_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_datar_datar_pads_in_payload_cmd_o \main_sdphy_datar_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_datar_datar_pads_in_payload_cmd_oe \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i + connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o + connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe + connect \main_sdphy_datar_datar_start $eq$ls180.v:4706$680_Y + connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4707$681_Y + connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i + connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1 + connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready + connect \main_sdphy_datar_datar_buf_sink_first \main_sdphy_datar_datar_source_source_first1 + connect \main_sdphy_datar_datar_buf_sink_last \main_sdphy_datar_datar_source_source_last1 + connect \main_sdphy_datar_datar_buf_sink_payload_data \main_sdphy_datar_datar_source_source_payload_data1 + connect \main_sdphy_datar_datar_source_source_valid0 \main_sdphy_datar_datar_buf_source_valid + connect \main_sdphy_datar_datar_buf_source_ready \main_sdphy_datar_datar_source_source_ready0 + connect \main_sdphy_datar_datar_source_source_first0 \main_sdphy_datar_datar_buf_source_first + connect \main_sdphy_datar_datar_source_source_last0 \main_sdphy_datar_datar_buf_source_last + connect \main_sdphy_datar_datar_source_source_payload_data0 \main_sdphy_datar_datar_buf_source_payload_data + connect \main_sdphy_datar_datar_source_source_valid1 \main_sdphy_datar_datar_converter_source_valid + connect \main_sdphy_datar_datar_converter_source_ready \main_sdphy_datar_datar_source_source_ready1 + connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first + connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last + connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data + connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4724$683_Y + connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all + connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4726$684_Y + connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4727$686_Y + connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid + connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready + connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first + connect \main_sdcore_crc16_inserter_sink_last \main_sdcore_sink_sink_last + connect \main_sdcore_crc16_inserter_sink_payload_data \main_sdcore_sink_sink_payload_data + connect \main_sdcore_source_source_valid \main_sdcore_crc16_checker_source_valid + connect \main_sdcore_crc16_checker_source_ready \main_sdcore_source_source_ready + connect \main_sdcore_source_source_first \main_sdcore_crc16_checker_source_first + connect \main_sdcore_source_source_last \main_sdcore_crc16_checker_source_last + connect \main_sdcore_source_source_payload_data \main_sdcore_crc16_checker_source_payload_data + connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0] + connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5] + connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done } + connect \main_sdcore_data_event_status { $not$ls180.v:4843$701_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } + connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage } + connect \main_sdcore_crc7_inserter_clr 1'1 + connect \main_sdcore_crc7_inserter_enable 1'1 + connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4847$704_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4847$702_Y } + connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4848$707_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4848$705_Y } + connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4849$710_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4849$708_Y } + connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:4850$713_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:4850$711_Y } + connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:4851$716_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:4851$714_Y } + connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:4852$719_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:4852$717_Y } + connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:4853$722_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:4853$720_Y } + connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:4854$725_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:4854$723_Y } + connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:4855$728_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:4855$726_Y } + connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:4856$731_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:4856$729_Y } + connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:4857$734_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:4857$732_Y } + connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:4858$737_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:4858$735_Y } + connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:4859$740_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:4859$738_Y } + connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:4860$743_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:4860$741_Y } + connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:4861$746_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:4861$744_Y } + connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:4862$749_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:4862$747_Y } + connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:4863$752_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:4863$750_Y } + connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:4864$755_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:4864$753_Y } + connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:4865$758_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:4865$756_Y } + connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:4866$761_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:4866$759_Y } + connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:4867$764_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:4867$762_Y } + connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:4868$767_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:4868$765_Y } + connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:4869$770_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:4869$768_Y } + connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:4870$773_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:4870$771_Y } + connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:4871$776_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:4871$774_Y } + connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:4872$779_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:4872$777_Y } + connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:4873$782_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:4873$780_Y } + connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:4874$785_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:4874$783_Y } + connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:4875$788_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:4875$786_Y } + connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:4876$791_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:4876$789_Y } + connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:4877$794_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:4877$792_Y } + connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:4878$797_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:4878$795_Y } + connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:4879$800_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:4879$798_Y } + connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:4880$803_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:4880$801_Y } + connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:4881$806_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:4881$804_Y } + connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:4882$809_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:4882$807_Y } + connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:4883$812_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:4883$810_Y } + connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:4884$815_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:4884$813_Y } + connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:4885$818_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:4885$816_Y } + connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:4886$821_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:4886$819_Y } + connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] } + connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:4896$824_Y + connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:4897$825_Y + connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] } + connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:4899$827_Y + connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:4900$828_Y + connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] } + connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:4902$830_Y + connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:4903$831_Y + connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] } + connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:4905$833_Y + connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:4906$834_Y + connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:4907$839_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:4907$837_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:4907$835_Y } + connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:4908$844_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:4908$842_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:4908$840_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:4917$850_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:4917$848_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:4917$846_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:4918$855_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:4918$853_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:4918$851_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:4927$861_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:4927$859_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:4927$857_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:4928$866_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:4928$864_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:4928$862_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:4937$872_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:4937$870_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:4937$868_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:4938$877_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:4938$875_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:4938$873_Y } + connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] } + connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5034$893_Y + connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] } + connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5044$896_Y + connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] } + connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5054$899_Y + connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] } + connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5064$902_Y + connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val + connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last + connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5089$914_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5089$912_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5089$910_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5090$919_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5090$917_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5090$915_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5099$925_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5099$923_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5099$921_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5100$930_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5100$928_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5100$926_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5109$936_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5109$934_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5109$932_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5110$941_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5110$939_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5110$937_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5119$947_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5119$945_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5119$943_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5120$952_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5120$950_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5120$948_Y } + connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0 + connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready + connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first + connect \main_sdblock2mem_fifo_sink_last \main_sdblock2mem_sink_sink_last + connect \main_sdblock2mem_fifo_sink_payload_data \main_sdblock2mem_sink_sink_payload_data0 + connect \main_sdblock2mem_converter_sink_valid \main_sdblock2mem_fifo_source_valid + connect \main_sdblock2mem_fifo_source_ready \main_sdblock2mem_converter_sink_ready + connect \main_sdblock2mem_converter_sink_first \main_sdblock2mem_fifo_source_first + connect \main_sdblock2mem_converter_sink_last \main_sdblock2mem_fifo_source_last + connect \main_sdblock2mem_converter_sink_payload_data \main_sdblock2mem_fifo_source_payload_data + connect \main_sdblock2mem_wishbonedmawriter_sink_valid \main_sdblock2mem_source_source_valid + connect \main_sdblock2mem_source_source_ready \main_sdblock2mem_wishbonedmawriter_sink_ready + connect \main_sdblock2mem_wishbonedmawriter_sink_first \main_sdblock2mem_source_source_first + connect \main_sdblock2mem_wishbonedmawriter_sink_last \main_sdblock2mem_source_source_last + connect \main_sdblock2mem_wishbonedmawriter_sink_payload_data \main_sdblock2mem_source_source_payload_data + connect \main_sdblock2mem_fifo_syncfifo_din { \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_fifo_in_payload_data } + connect { \main_sdblock2mem_fifo_fifo_out_last \main_sdblock2mem_fifo_fifo_out_first \main_sdblock2mem_fifo_fifo_out_payload_data } \main_sdblock2mem_fifo_syncfifo_dout + connect \main_sdblock2mem_fifo_sink_ready \main_sdblock2mem_fifo_syncfifo_writable + connect \main_sdblock2mem_fifo_syncfifo_we \main_sdblock2mem_fifo_sink_valid + connect \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_sink_first + connect \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_sink_last + connect \main_sdblock2mem_fifo_fifo_in_payload_data \main_sdblock2mem_fifo_sink_payload_data + connect \main_sdblock2mem_fifo_source_valid \main_sdblock2mem_fifo_syncfifo_readable + connect \main_sdblock2mem_fifo_source_first \main_sdblock2mem_fifo_fifo_out_first + connect \main_sdblock2mem_fifo_source_last \main_sdblock2mem_fifo_fifo_out_last + connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data + connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready + connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din + connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5356$982_Y + connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5357$983_Y + connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume + connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r + connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5360$984_Y + connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5361$985_Y + connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid + connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready + connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first + connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last + connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data + connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5367$987_Y + connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all + connect \main_sdblock2mem_converter_load_part $and$ls180.v:5369$988_Y + connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1 + connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1 + connect \main_interface0_bus_we 1'1 + connect \main_interface0_bus_sel 4'1111 + connect \main_interface0_bus_adr \main_sdblock2mem_sink_sink_payload_address + connect \main_interface0_bus_dat_w { \main_sdblock2mem_sink_sink_payload_data1 [7:0] \main_sdblock2mem_sink_sink_payload_data1 [15:8] \main_sdblock2mem_sink_sink_payload_data1 [23:16] \main_sdblock2mem_sink_sink_payload_data1 [31:24] } + connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack + connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [33:2] + connect \main_sdblock2mem_wishbonedmawriter_length { 2'00 \main_sdblock2mem_wishbonedmawriter_length_storage [31:2] } + connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5379$989_Y + connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid + connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready + connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first + connect \main_sdmem2block_converter_sink_last \main_sdmem2block_dma_source_last + connect \main_sdmem2block_converter_sink_payload_data \main_sdmem2block_dma_source_payload_data + connect \main_sdmem2block_fifo_sink_valid \main_sdmem2block_source_source_valid1 + connect \main_sdmem2block_source_source_ready1 \main_sdmem2block_fifo_sink_ready + connect \main_sdmem2block_fifo_sink_first \main_sdmem2block_source_source_first1 + connect \main_sdmem2block_fifo_sink_last \main_sdmem2block_source_source_last1 + connect \main_sdmem2block_fifo_sink_payload_data \main_sdmem2block_source_source_payload_data1 + connect \main_sdmem2block_source_source_valid0 \main_sdmem2block_fifo_source_valid + connect \main_sdmem2block_fifo_source_ready \main_sdmem2block_source_source_ready0 + connect \main_sdmem2block_source_source_first0 \main_sdmem2block_fifo_source_first + connect \main_sdmem2block_source_source_last0 \main_sdmem2block_fifo_source_last + connect \main_sdmem2block_source_source_payload_data0 \main_sdmem2block_fifo_source_payload_data + connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [33:2] + connect \main_sdmem2block_dma_length { 2'00 \main_sdmem2block_dma_length_storage [31:2] } + connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset + connect \main_sdmem2block_dma_reset $not$ls180.v:5438$996_Y + connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid + connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1 + connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first + connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last + connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data + connect \main_sdmem2block_converter_first $eq$ls180.v:5519$1004_Y + connect \main_sdmem2block_converter_last $eq$ls180.v:5520$1005_Y + connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid + connect \main_sdmem2block_converter_source_first $and$ls180.v:5522$1006_Y + connect \main_sdmem2block_converter_source_last $and$ls180.v:5523$1007_Y + connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5524$1008_Y + connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last + connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data } + connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout + connect \main_sdmem2block_fifo_sink_ready \main_sdmem2block_fifo_syncfifo_writable + connect \main_sdmem2block_fifo_syncfifo_we \main_sdmem2block_fifo_sink_valid + connect \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_sink_first + connect \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_sink_last + connect \main_sdmem2block_fifo_fifo_in_payload_data \main_sdmem2block_fifo_sink_payload_data + connect \main_sdmem2block_fifo_source_valid \main_sdmem2block_fifo_syncfifo_readable + connect \main_sdmem2block_fifo_source_first \main_sdmem2block_fifo_fifo_out_first + connect \main_sdmem2block_fifo_source_last \main_sdmem2block_fifo_fifo_out_last + connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data + connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready + connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din + connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5564$1013_Y + connect \main_sdmem2block_fifo_do_read $and$ls180.v:5565$1014_Y + connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume + connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r + connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5568$1015_Y + connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5569$1016_Y + connect \libresocsim_start0 \libresocsim_start1 + connect \libresocsim_length0 \libresocsim_length1 + connect \libresocsim_mosi \libresocsim_mosi_storage + connect \libresocsim_done1 \libresocsim_done0 + connect \libresocsim_miso_status \libresocsim_miso + connect \libresocsim_cs \libresocsim_cs_storage + connect \libresocsim_loopback \libresocsim_loopback_storage + connect \libresocsim_clk_rise $eq$ls180.v:5577$1018_Y + connect \libresocsim_clk_fall $eq$ls180.v:5578$1020_Y + connect \libresocsim_clk_divider0 \libresocsim_storage + connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] + connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 + connect \builder_shared_sel \builder_comb_rhs_array_muxed26 + connect \builder_shared_cyc \builder_comb_rhs_array_muxed27 + connect \builder_shared_stb \builder_comb_rhs_array_muxed28 + connect \builder_shared_we \builder_comb_rhs_array_muxed29 + connect \builder_shared_cti \builder_comb_rhs_array_muxed30 + connect \builder_shared_bte \builder_comb_rhs_array_muxed31 + connect \main_libresocsim_interface0_converted_interface_dat_r \builder_shared_dat_r + connect \main_libresocsim_interface1_converted_interface_dat_r \builder_shared_dat_r + connect \main_libresocsim_interface2_converted_interface_dat_r \builder_shared_dat_r + connect \main_interface0_bus_dat_r \builder_shared_dat_r + connect \main_interface1_bus_dat_r \builder_shared_dat_r + connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5679$1030_Y + connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5680$1032_Y + connect \main_libresocsim_interface2_converted_interface_ack $and$ls180.v:5681$1034_Y + connect \main_interface0_bus_ack $and$ls180.v:5682$1036_Y + connect \main_interface1_bus_ack $and$ls180.v:5683$1038_Y + connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5684$1040_Y + connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5685$1042_Y + connect \main_libresocsim_interface2_converted_interface_err $and$ls180.v:5686$1044_Y + connect \main_interface0_bus_err $and$ls180.v:5687$1046_Y + connect \main_interface1_bus_err $and$ls180.v:5688$1048_Y + connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_interface2_converted_interface_cyc \main_libresocsim_interface1_converted_interface_cyc \main_libresocsim_interface0_converted_interface_cyc } + connect \main_libresocsim_ram_bus_adr \builder_shared_adr + connect \main_libresocsim_ram_bus_dat_w \builder_shared_dat_w + connect \main_libresocsim_ram_bus_sel \builder_shared_sel + connect \main_libresocsim_ram_bus_stb \builder_shared_stb + connect \main_libresocsim_ram_bus_we \builder_shared_we + connect \main_libresocsim_ram_bus_cti \builder_shared_cti + connect \main_libresocsim_ram_bus_bte \builder_shared_bte + connect \main_libresocsim_libresoc_xics_icp_adr \builder_shared_adr + connect \main_libresocsim_libresoc_xics_icp_dat_w \builder_shared_dat_w + connect \main_libresocsim_libresoc_xics_icp_sel \builder_shared_sel + connect \main_libresocsim_libresoc_xics_icp_stb \builder_shared_stb + connect \main_libresocsim_libresoc_xics_icp_we \builder_shared_we + connect \main_libresocsim_libresoc_xics_icp_cti \builder_shared_cti + connect \main_libresocsim_libresoc_xics_icp_bte \builder_shared_bte + connect \main_libresocsim_libresoc_xics_ics_adr \builder_shared_adr + connect \main_libresocsim_libresoc_xics_ics_dat_w \builder_shared_dat_w + connect \main_libresocsim_libresoc_xics_ics_sel \builder_shared_sel + connect \main_libresocsim_libresoc_xics_ics_stb \builder_shared_stb + connect \main_libresocsim_libresoc_xics_ics_we \builder_shared_we + connect \main_libresocsim_libresoc_xics_ics_cti \builder_shared_cti + connect \main_libresocsim_libresoc_xics_ics_bte \builder_shared_bte + connect \main_wb_sdram_adr \builder_shared_adr + connect \main_wb_sdram_dat_w \builder_shared_dat_w + connect \main_wb_sdram_sel \builder_shared_sel + connect \main_wb_sdram_stb \builder_shared_stb + connect \main_wb_sdram_we \builder_shared_we + connect \main_wb_sdram_cti \builder_shared_cti + connect \main_wb_sdram_bte \builder_shared_bte + connect \builder_libresocsim_wishbone_adr \builder_shared_adr + connect \builder_libresocsim_wishbone_dat_w \builder_shared_dat_w + connect \builder_libresocsim_wishbone_sel \builder_shared_sel + connect \builder_libresocsim_wishbone_stb \builder_shared_stb + connect \builder_libresocsim_wishbone_we \builder_shared_we + connect \builder_libresocsim_wishbone_cti \builder_shared_cti + connect \builder_libresocsim_wishbone_bte \builder_shared_bte + connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5733$1055_Y + connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5734$1056_Y + connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5735$1057_Y + connect \main_wb_sdram_cyc $and$ls180.v:5736$1058_Y + connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5737$1059_Y + connect \builder_shared_err $or$ls180.v:5738$1063_Y + connect \builder_wait $and$ls180.v:5739$1066_Y + connect \builder_done $eq$ls180.v:5752$1081_Y + connect \builder_csrbank0_sel $eq$ls180.v:5753$1082_Y + connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] + connect \builder_csrbank0_reset0_re $and$ls180.v:5755$1085_Y + connect \builder_csrbank0_reset0_we $and$ls180.v:5756$1089_Y + connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch3_re $and$ls180.v:5758$1092_Y + connect \builder_csrbank0_scratch3_we $and$ls180.v:5759$1096_Y + connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch2_re $and$ls180.v:5761$1099_Y + connect \builder_csrbank0_scratch2_we $and$ls180.v:5762$1103_Y + connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch1_re $and$ls180.v:5764$1106_Y + connect \builder_csrbank0_scratch1_we $and$ls180.v:5765$1110_Y + connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch0_re $and$ls180.v:5767$1113_Y + connect \builder_csrbank0_scratch0_we $and$ls180.v:5768$1117_Y + connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5770$1120_Y + connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5771$1124_Y + connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5773$1127_Y + connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5774$1131_Y + connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5776$1134_Y + connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5777$1138_Y + connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5779$1141_Y + connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5780$1145_Y + connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage + connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24] + connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16] + connect \builder_csrbank0_scratch1_w \main_libresocsim_scratch_storage [15:8] + connect \builder_csrbank0_scratch0_w \main_libresocsim_scratch_storage [7:0] + connect \builder_csrbank0_bus_errors3_w \main_libresocsim_bus_errors_status [31:24] + connect \builder_csrbank0_bus_errors2_w \main_libresocsim_bus_errors_status [23:16] + connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8] + connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0] + connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we + connect \builder_csrbank1_sel $eq$ls180.v:5791$1146_Y + connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_oe1_re $and$ls180.v:5793$1149_Y + connect \builder_csrbank1_oe1_we $and$ls180.v:5794$1153_Y + connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_oe0_re $and$ls180.v:5796$1156_Y + connect \builder_csrbank1_oe0_we $and$ls180.v:5797$1160_Y + connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_in1_re $and$ls180.v:5799$1163_Y + connect \builder_csrbank1_in1_we $and$ls180.v:5800$1167_Y + connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_in0_re $and$ls180.v:5802$1170_Y + connect \builder_csrbank1_in0_we $and$ls180.v:5803$1174_Y + connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_out1_re $and$ls180.v:5805$1177_Y + connect \builder_csrbank1_out1_we $and$ls180.v:5806$1181_Y + connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_out0_re $and$ls180.v:5808$1184_Y + connect \builder_csrbank1_out0_we $and$ls180.v:5809$1188_Y + connect \builder_csrbank1_oe1_w \main_gpio_oe_storage [15:8] + connect \builder_csrbank1_oe0_w \main_gpio_oe_storage [7:0] + connect \builder_csrbank1_in1_w \main_gpio_status [15:8] + connect \builder_csrbank1_in0_w \main_gpio_status [7:0] + connect \main_gpio_we \builder_csrbank1_in0_we + connect \builder_csrbank1_out1_w \main_gpio_out_storage [15:8] + connect \builder_csrbank1_out0_w \main_gpio_out_storage [7:0] + connect \builder_csrbank2_sel $eq$ls180.v:5817$1189_Y + connect \builder_csrbank2_w0_r \builder_interface2_bank_bus_dat_w [2:0] + connect \builder_csrbank2_w0_re $and$ls180.v:5819$1192_Y + connect \builder_csrbank2_w0_we $and$ls180.v:5820$1196_Y + connect \builder_csrbank2_r_r \builder_interface2_bank_bus_dat_w [0] + connect \builder_csrbank2_r_re $and$ls180.v:5822$1199_Y + connect \builder_csrbank2_r_we $and$ls180.v:5823$1203_Y + connect \main_i2c_scl \main_i2c_storage [0] + connect \main_i2c_oe \main_i2c_storage [1] + connect \main_i2c_sda0 \main_i2c_storage [2] + connect \builder_csrbank2_w0_w \main_i2c_storage + connect \main_i2c_status \main_i2c_sda1 + connect \builder_csrbank2_r_w \main_i2c_status + connect \main_i2c_we \builder_csrbank2_r_we + connect \builder_csrbank3_sel $eq$ls180.v:5831$1204_Y + connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0] + connect \builder_csrbank3_enable0_re $and$ls180.v:5833$1207_Y + connect \builder_csrbank3_enable0_we $and$ls180.v:5834$1211_Y + connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width3_re $and$ls180.v:5836$1214_Y + connect \builder_csrbank3_width3_we $and$ls180.v:5837$1218_Y + connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width2_re $and$ls180.v:5839$1221_Y + connect \builder_csrbank3_width2_we $and$ls180.v:5840$1225_Y + connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width1_re $and$ls180.v:5842$1228_Y + connect \builder_csrbank3_width1_we $and$ls180.v:5843$1232_Y + connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width0_re $and$ls180.v:5845$1235_Y + connect \builder_csrbank3_width0_we $and$ls180.v:5846$1239_Y + connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period3_re $and$ls180.v:5848$1242_Y + connect \builder_csrbank3_period3_we $and$ls180.v:5849$1246_Y + connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period2_re $and$ls180.v:5851$1249_Y + connect \builder_csrbank3_period2_we $and$ls180.v:5852$1253_Y + connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period1_re $and$ls180.v:5854$1256_Y + connect \builder_csrbank3_period1_we $and$ls180.v:5855$1260_Y + connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period0_re $and$ls180.v:5857$1263_Y + connect \builder_csrbank3_period0_we $and$ls180.v:5858$1267_Y + connect \builder_csrbank3_enable0_w \main_pwm0_enable_storage + connect \builder_csrbank3_width3_w \main_pwm0_width_storage [31:24] + connect \builder_csrbank3_width2_w \main_pwm0_width_storage [23:16] + connect \builder_csrbank3_width1_w \main_pwm0_width_storage [15:8] + connect \builder_csrbank3_width0_w \main_pwm0_width_storage [7:0] + connect \builder_csrbank3_period3_w \main_pwm0_period_storage [31:24] + connect \builder_csrbank3_period2_w \main_pwm0_period_storage [23:16] + connect \builder_csrbank3_period1_w \main_pwm0_period_storage [15:8] + connect \builder_csrbank3_period0_w \main_pwm0_period_storage [7:0] + connect \builder_csrbank4_sel $eq$ls180.v:5868$1268_Y + connect \builder_csrbank4_enable0_r \builder_interface4_bank_bus_dat_w [0] + connect \builder_csrbank4_enable0_re $and$ls180.v:5870$1271_Y + connect \builder_csrbank4_enable0_we $and$ls180.v:5871$1275_Y + connect \builder_csrbank4_width3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width3_re $and$ls180.v:5873$1278_Y + connect \builder_csrbank4_width3_we $and$ls180.v:5874$1282_Y + connect \builder_csrbank4_width2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width2_re $and$ls180.v:5876$1285_Y + connect \builder_csrbank4_width2_we $and$ls180.v:5877$1289_Y + connect \builder_csrbank4_width1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width1_re $and$ls180.v:5879$1292_Y + connect \builder_csrbank4_width1_we $and$ls180.v:5880$1296_Y + connect \builder_csrbank4_width0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width0_re $and$ls180.v:5882$1299_Y + connect \builder_csrbank4_width0_we $and$ls180.v:5883$1303_Y + connect \builder_csrbank4_period3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period3_re $and$ls180.v:5885$1306_Y + connect \builder_csrbank4_period3_we $and$ls180.v:5886$1310_Y + connect \builder_csrbank4_period2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period2_re $and$ls180.v:5888$1313_Y + connect \builder_csrbank4_period2_we $and$ls180.v:5889$1317_Y + connect \builder_csrbank4_period1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period1_re $and$ls180.v:5891$1320_Y + connect \builder_csrbank4_period1_we $and$ls180.v:5892$1324_Y + connect \builder_csrbank4_period0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period0_re $and$ls180.v:5894$1327_Y + connect \builder_csrbank4_period0_we $and$ls180.v:5895$1331_Y + connect \builder_csrbank4_enable0_w \main_pwm1_enable_storage + connect \builder_csrbank4_width3_w \main_pwm1_width_storage [31:24] + connect \builder_csrbank4_width2_w \main_pwm1_width_storage [23:16] + connect \builder_csrbank4_width1_w \main_pwm1_width_storage [15:8] + connect \builder_csrbank4_width0_w \main_pwm1_width_storage [7:0] + connect \builder_csrbank4_period3_w \main_pwm1_period_storage [31:24] + connect \builder_csrbank4_period2_w \main_pwm1_period_storage [23:16] + connect \builder_csrbank4_period1_w \main_pwm1_period_storage [15:8] + connect \builder_csrbank4_period0_w \main_pwm1_period_storage [7:0] + connect \builder_csrbank5_sel $eq$ls180.v:5905$1332_Y + connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base7_re $and$ls180.v:5907$1335_Y + connect \builder_csrbank5_dma_base7_we $and$ls180.v:5908$1339_Y + connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base6_re $and$ls180.v:5910$1342_Y + connect \builder_csrbank5_dma_base6_we $and$ls180.v:5911$1346_Y + connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base5_re $and$ls180.v:5913$1349_Y + connect \builder_csrbank5_dma_base5_we $and$ls180.v:5914$1353_Y + connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base4_re $and$ls180.v:5916$1356_Y + connect \builder_csrbank5_dma_base4_we $and$ls180.v:5917$1360_Y + connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base3_re $and$ls180.v:5919$1363_Y + connect \builder_csrbank5_dma_base3_we $and$ls180.v:5920$1367_Y + connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base2_re $and$ls180.v:5922$1370_Y + connect \builder_csrbank5_dma_base2_we $and$ls180.v:5923$1374_Y + connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base1_re $and$ls180.v:5925$1377_Y + connect \builder_csrbank5_dma_base1_we $and$ls180.v:5926$1381_Y + connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base0_re $and$ls180.v:5928$1384_Y + connect \builder_csrbank5_dma_base0_we $and$ls180.v:5929$1388_Y + connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length3_re $and$ls180.v:5931$1391_Y + connect \builder_csrbank5_dma_length3_we $and$ls180.v:5932$1395_Y + connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length2_re $and$ls180.v:5934$1398_Y + connect \builder_csrbank5_dma_length2_we $and$ls180.v:5935$1402_Y + connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length1_re $and$ls180.v:5937$1405_Y + connect \builder_csrbank5_dma_length1_we $and$ls180.v:5938$1409_Y + connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length0_re $and$ls180.v:5940$1412_Y + connect \builder_csrbank5_dma_length0_we $and$ls180.v:5941$1416_Y + connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_enable0_re $and$ls180.v:5943$1419_Y + connect \builder_csrbank5_dma_enable0_we $and$ls180.v:5944$1423_Y + connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_done_re $and$ls180.v:5946$1426_Y + connect \builder_csrbank5_dma_done_we $and$ls180.v:5947$1430_Y + connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_loop0_re $and$ls180.v:5949$1433_Y + connect \builder_csrbank5_dma_loop0_we $and$ls180.v:5950$1437_Y + connect \builder_csrbank5_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56] + connect \builder_csrbank5_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48] + connect \builder_csrbank5_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40] + connect \builder_csrbank5_dma_base4_w \main_sdblock2mem_wishbonedmawriter_base_storage [39:32] + connect \builder_csrbank5_dma_base3_w \main_sdblock2mem_wishbonedmawriter_base_storage [31:24] + connect \builder_csrbank5_dma_base2_w \main_sdblock2mem_wishbonedmawriter_base_storage [23:16] + connect \builder_csrbank5_dma_base1_w \main_sdblock2mem_wishbonedmawriter_base_storage [15:8] + connect \builder_csrbank5_dma_base0_w \main_sdblock2mem_wishbonedmawriter_base_storage [7:0] + connect \builder_csrbank5_dma_length3_w \main_sdblock2mem_wishbonedmawriter_length_storage [31:24] + connect \builder_csrbank5_dma_length2_w \main_sdblock2mem_wishbonedmawriter_length_storage [23:16] + connect \builder_csrbank5_dma_length1_w \main_sdblock2mem_wishbonedmawriter_length_storage [15:8] + connect \builder_csrbank5_dma_length0_w \main_sdblock2mem_wishbonedmawriter_length_storage [7:0] + connect \builder_csrbank5_dma_enable0_w \main_sdblock2mem_wishbonedmawriter_enable_storage + connect \builder_csrbank5_dma_done_w \main_sdblock2mem_wishbonedmawriter_status + connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank5_dma_done_we + connect \builder_csrbank5_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage + connect \builder_csrbank6_sel $eq$ls180.v:5967$1438_Y + connect \builder_csrbank6_cmd_argument3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:5969$1441_Y + connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:5970$1445_Y + connect \builder_csrbank6_cmd_argument2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:5972$1448_Y + connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:5973$1452_Y + connect \builder_csrbank6_cmd_argument1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:5975$1455_Y + connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:5976$1459_Y + connect \builder_csrbank6_cmd_argument0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:5978$1462_Y + connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:5979$1466_Y + connect \builder_csrbank6_cmd_command3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command3_re $and$ls180.v:5981$1469_Y + connect \builder_csrbank6_cmd_command3_we $and$ls180.v:5982$1473_Y + connect \builder_csrbank6_cmd_command2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command2_re $and$ls180.v:5984$1476_Y + connect \builder_csrbank6_cmd_command2_we $and$ls180.v:5985$1480_Y + connect \builder_csrbank6_cmd_command1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command1_re $and$ls180.v:5987$1483_Y + connect \builder_csrbank6_cmd_command1_we $and$ls180.v:5988$1487_Y + connect \builder_csrbank6_cmd_command0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command0_re $and$ls180.v:5990$1490_Y + connect \builder_csrbank6_cmd_command0_we $and$ls180.v:5991$1494_Y + connect \main_sdcore_cmd_send_r \builder_interface6_bank_bus_dat_w [0] + connect \main_sdcore_cmd_send_re $and$ls180.v:5993$1497_Y + connect \main_sdcore_cmd_send_we $and$ls180.v:5994$1501_Y + connect \builder_csrbank6_cmd_response15_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response15_re $and$ls180.v:5996$1504_Y + connect \builder_csrbank6_cmd_response15_we $and$ls180.v:5997$1508_Y + connect \builder_csrbank6_cmd_response14_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response14_re $and$ls180.v:5999$1511_Y + connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6000$1515_Y + connect \builder_csrbank6_cmd_response13_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6002$1518_Y + connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6003$1522_Y + connect \builder_csrbank6_cmd_response12_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6005$1525_Y + connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6006$1529_Y + connect \builder_csrbank6_cmd_response11_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6008$1532_Y + connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6009$1536_Y + connect \builder_csrbank6_cmd_response10_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6011$1539_Y + connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6012$1543_Y + connect \builder_csrbank6_cmd_response9_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6014$1546_Y + connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6015$1550_Y + connect \builder_csrbank6_cmd_response8_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6017$1553_Y + connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6018$1557_Y + connect \builder_csrbank6_cmd_response7_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6020$1560_Y + connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6021$1564_Y + connect \builder_csrbank6_cmd_response6_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6023$1567_Y + connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6024$1571_Y + connect \builder_csrbank6_cmd_response5_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6026$1574_Y + connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6027$1578_Y + connect \builder_csrbank6_cmd_response4_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6029$1581_Y + connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6030$1585_Y + connect \builder_csrbank6_cmd_response3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6032$1588_Y + connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6033$1592_Y + connect \builder_csrbank6_cmd_response2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6035$1595_Y + connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6036$1599_Y + connect \builder_csrbank6_cmd_response1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6038$1602_Y + connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6039$1606_Y + connect \builder_csrbank6_cmd_response0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6041$1609_Y + connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6042$1613_Y + connect \builder_csrbank6_cmd_event_r \builder_interface6_bank_bus_dat_w [3:0] + connect \builder_csrbank6_cmd_event_re $and$ls180.v:6044$1616_Y + connect \builder_csrbank6_cmd_event_we $and$ls180.v:6045$1620_Y + connect \builder_csrbank6_data_event_r \builder_interface6_bank_bus_dat_w [3:0] + connect \builder_csrbank6_data_event_re $and$ls180.v:6047$1623_Y + connect \builder_csrbank6_data_event_we $and$ls180.v:6048$1627_Y + connect \builder_csrbank6_block_length1_r \builder_interface6_bank_bus_dat_w [1:0] + connect \builder_csrbank6_block_length1_re $and$ls180.v:6050$1630_Y + connect \builder_csrbank6_block_length1_we $and$ls180.v:6051$1634_Y + connect \builder_csrbank6_block_length0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_length0_re $and$ls180.v:6053$1637_Y + connect \builder_csrbank6_block_length0_we $and$ls180.v:6054$1641_Y + connect \builder_csrbank6_block_count3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count3_re $and$ls180.v:6056$1644_Y + connect \builder_csrbank6_block_count3_we $and$ls180.v:6057$1648_Y + connect \builder_csrbank6_block_count2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count2_re $and$ls180.v:6059$1651_Y + connect \builder_csrbank6_block_count2_we $and$ls180.v:6060$1655_Y + connect \builder_csrbank6_block_count1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count1_re $and$ls180.v:6062$1658_Y + connect \builder_csrbank6_block_count1_we $and$ls180.v:6063$1662_Y + connect \builder_csrbank6_block_count0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count0_re $and$ls180.v:6065$1665_Y + connect \builder_csrbank6_block_count0_we $and$ls180.v:6066$1669_Y + connect \builder_csrbank6_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24] + connect \builder_csrbank6_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16] + connect \builder_csrbank6_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8] + connect \builder_csrbank6_cmd_argument0_w \main_sdcore_cmd_argument_storage [7:0] + connect \builder_csrbank6_cmd_command3_w \main_sdcore_cmd_command_storage [31:24] + connect \builder_csrbank6_cmd_command2_w \main_sdcore_cmd_command_storage [23:16] + connect \builder_csrbank6_cmd_command1_w \main_sdcore_cmd_command_storage [15:8] + connect \builder_csrbank6_cmd_command0_w \main_sdcore_cmd_command_storage [7:0] + connect \builder_csrbank6_cmd_response15_w \main_sdcore_cmd_response_status [127:120] + connect \builder_csrbank6_cmd_response14_w \main_sdcore_cmd_response_status [119:112] + connect \builder_csrbank6_cmd_response13_w \main_sdcore_cmd_response_status [111:104] + connect \builder_csrbank6_cmd_response12_w \main_sdcore_cmd_response_status [103:96] + connect \builder_csrbank6_cmd_response11_w \main_sdcore_cmd_response_status [95:88] + connect \builder_csrbank6_cmd_response10_w \main_sdcore_cmd_response_status [87:80] + connect \builder_csrbank6_cmd_response9_w \main_sdcore_cmd_response_status [79:72] + connect \builder_csrbank6_cmd_response8_w \main_sdcore_cmd_response_status [71:64] + connect \builder_csrbank6_cmd_response7_w \main_sdcore_cmd_response_status [63:56] + connect \builder_csrbank6_cmd_response6_w \main_sdcore_cmd_response_status [55:48] + connect \builder_csrbank6_cmd_response5_w \main_sdcore_cmd_response_status [47:40] + connect \builder_csrbank6_cmd_response4_w \main_sdcore_cmd_response_status [39:32] + connect \builder_csrbank6_cmd_response3_w \main_sdcore_cmd_response_status [31:24] + connect \builder_csrbank6_cmd_response2_w \main_sdcore_cmd_response_status [23:16] + connect \builder_csrbank6_cmd_response1_w \main_sdcore_cmd_response_status [15:8] + connect \builder_csrbank6_cmd_response0_w \main_sdcore_cmd_response_status [7:0] + connect \main_sdcore_cmd_response_we \builder_csrbank6_cmd_response0_we + connect \builder_csrbank6_cmd_event_w \main_sdcore_cmd_event_status + connect \main_sdcore_cmd_event_we \builder_csrbank6_cmd_event_we + connect \builder_csrbank6_data_event_w \main_sdcore_data_event_status + connect \main_sdcore_data_event_we \builder_csrbank6_data_event_we + connect \builder_csrbank6_block_length1_w \main_sdcore_block_length_storage [9:8] + connect \builder_csrbank6_block_length0_w \main_sdcore_block_length_storage [7:0] + connect \builder_csrbank6_block_count3_w \main_sdcore_block_count_storage [31:24] + connect \builder_csrbank6_block_count2_w \main_sdcore_block_count_storage [23:16] + connect \builder_csrbank6_block_count1_w \main_sdcore_block_count_storage [15:8] + connect \builder_csrbank6_block_count0_w \main_sdcore_block_count_storage [7:0] + connect \builder_csrbank7_sel $eq$ls180.v:6102$1670_Y + connect \builder_csrbank7_dma_base7_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base7_re $and$ls180.v:6104$1673_Y + connect \builder_csrbank7_dma_base7_we $and$ls180.v:6105$1677_Y + connect \builder_csrbank7_dma_base6_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base6_re $and$ls180.v:6107$1680_Y + connect \builder_csrbank7_dma_base6_we $and$ls180.v:6108$1684_Y + connect \builder_csrbank7_dma_base5_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base5_re $and$ls180.v:6110$1687_Y + connect \builder_csrbank7_dma_base5_we $and$ls180.v:6111$1691_Y + connect \builder_csrbank7_dma_base4_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base4_re $and$ls180.v:6113$1694_Y + connect \builder_csrbank7_dma_base4_we $and$ls180.v:6114$1698_Y + connect \builder_csrbank7_dma_base3_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base3_re $and$ls180.v:6116$1701_Y + connect \builder_csrbank7_dma_base3_we $and$ls180.v:6117$1705_Y + connect \builder_csrbank7_dma_base2_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base2_re $and$ls180.v:6119$1708_Y + connect \builder_csrbank7_dma_base2_we $and$ls180.v:6120$1712_Y + connect \builder_csrbank7_dma_base1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base1_re $and$ls180.v:6122$1715_Y + connect \builder_csrbank7_dma_base1_we $and$ls180.v:6123$1719_Y + connect \builder_csrbank7_dma_base0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base0_re $and$ls180.v:6125$1722_Y + connect \builder_csrbank7_dma_base0_we $and$ls180.v:6126$1726_Y + connect \builder_csrbank7_dma_length3_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length3_re $and$ls180.v:6128$1729_Y + connect \builder_csrbank7_dma_length3_we $and$ls180.v:6129$1733_Y + connect \builder_csrbank7_dma_length2_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length2_re $and$ls180.v:6131$1736_Y + connect \builder_csrbank7_dma_length2_we $and$ls180.v:6132$1740_Y + connect \builder_csrbank7_dma_length1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length1_re $and$ls180.v:6134$1743_Y + connect \builder_csrbank7_dma_length1_we $and$ls180.v:6135$1747_Y + connect \builder_csrbank7_dma_length0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length0_re $and$ls180.v:6137$1750_Y + connect \builder_csrbank7_dma_length0_we $and$ls180.v:6138$1754_Y + connect \builder_csrbank7_dma_enable0_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6140$1757_Y + connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6141$1761_Y + connect \builder_csrbank7_dma_done_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_dma_done_re $and$ls180.v:6143$1764_Y + connect \builder_csrbank7_dma_done_we $and$ls180.v:6144$1768_Y + connect \builder_csrbank7_dma_loop0_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6146$1771_Y + connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6147$1775_Y + connect \builder_csrbank7_dma_offset3_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6149$1778_Y + connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6150$1782_Y + connect \builder_csrbank7_dma_offset2_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6152$1785_Y + connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6153$1789_Y + connect \builder_csrbank7_dma_offset1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6155$1792_Y + connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6156$1796_Y + connect \builder_csrbank7_dma_offset0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6158$1799_Y + connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6159$1803_Y + connect \builder_csrbank7_dma_base7_w \main_sdmem2block_dma_base_storage [63:56] + connect \builder_csrbank7_dma_base6_w \main_sdmem2block_dma_base_storage [55:48] + connect \builder_csrbank7_dma_base5_w \main_sdmem2block_dma_base_storage [47:40] + connect \builder_csrbank7_dma_base4_w \main_sdmem2block_dma_base_storage [39:32] + connect \builder_csrbank7_dma_base3_w \main_sdmem2block_dma_base_storage [31:24] + connect \builder_csrbank7_dma_base2_w \main_sdmem2block_dma_base_storage [23:16] + connect \builder_csrbank7_dma_base1_w \main_sdmem2block_dma_base_storage [15:8] + connect \builder_csrbank7_dma_base0_w \main_sdmem2block_dma_base_storage [7:0] + connect \builder_csrbank7_dma_length3_w \main_sdmem2block_dma_length_storage [31:24] + connect \builder_csrbank7_dma_length2_w \main_sdmem2block_dma_length_storage [23:16] + connect \builder_csrbank7_dma_length1_w \main_sdmem2block_dma_length_storage [15:8] + connect \builder_csrbank7_dma_length0_w \main_sdmem2block_dma_length_storage [7:0] + connect \builder_csrbank7_dma_enable0_w \main_sdmem2block_dma_enable_storage + connect \builder_csrbank7_dma_done_w \main_sdmem2block_dma_done_status + connect \main_sdmem2block_dma_done_we \builder_csrbank7_dma_done_we + connect \builder_csrbank7_dma_loop0_w \main_sdmem2block_dma_loop_storage + connect \builder_csrbank7_dma_offset3_w \main_sdmem2block_dma_offset_status [31:24] + connect \builder_csrbank7_dma_offset2_w \main_sdmem2block_dma_offset_status [23:16] + connect \builder_csrbank7_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8] + connect \builder_csrbank7_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0] + connect \main_sdmem2block_dma_offset_we \builder_csrbank7_dma_offset0_we + connect \builder_csrbank8_sel $eq$ls180.v:6181$1804_Y + connect \builder_csrbank8_card_detect_r \builder_interface8_bank_bus_dat_w [0] + connect \builder_csrbank8_card_detect_re $and$ls180.v:6183$1807_Y + connect \builder_csrbank8_card_detect_we $and$ls180.v:6184$1811_Y + connect \builder_csrbank8_clocker_divider1_r \builder_interface8_bank_bus_dat_w [0] + connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6186$1814_Y + connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6187$1818_Y + connect \builder_csrbank8_clocker_divider0_r \builder_interface8_bank_bus_dat_w + connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6189$1821_Y + connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6190$1825_Y + connect \main_sdphy_init_initialize_r \builder_interface8_bank_bus_dat_w [0] + connect \main_sdphy_init_initialize_re $and$ls180.v:6192$1828_Y + connect \main_sdphy_init_initialize_we $and$ls180.v:6193$1832_Y + connect \builder_csrbank8_card_detect_w \main_sdphy_status + connect \main_sdphy_we \builder_csrbank8_card_detect_we + connect \builder_csrbank8_clocker_divider1_w \main_sdphy_clocker_storage [8] + connect \builder_csrbank8_clocker_divider0_w \main_sdphy_clocker_storage [7:0] + connect \builder_csrbank9_sel $eq$ls180.v:6198$1833_Y + connect \builder_csrbank9_dfii_control0_r \builder_interface9_bank_bus_dat_w [3:0] + connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6200$1836_Y + connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6201$1840_Y + connect \builder_csrbank9_dfii_pi0_command0_r \builder_interface9_bank_bus_dat_w [5:0] + connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6203$1843_Y + connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6204$1847_Y + connect \main_sdram_command_issue_r \builder_interface9_bank_bus_dat_w [0] + connect \main_sdram_command_issue_re $and$ls180.v:6206$1850_Y + connect \main_sdram_command_issue_we $and$ls180.v:6207$1854_Y + connect \builder_csrbank9_dfii_pi0_address1_r \builder_interface9_bank_bus_dat_w [4:0] + connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6209$1857_Y + connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6210$1861_Y + connect \builder_csrbank9_dfii_pi0_address0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6212$1864_Y + connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6213$1868_Y + connect \builder_csrbank9_dfii_pi0_baddress0_r \builder_interface9_bank_bus_dat_w [1:0] + connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6215$1871_Y + connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6216$1875_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6218$1878_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6219$1882_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6221$1885_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6222$1889_Y + connect \builder_csrbank9_dfii_pi0_rddata1_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6224$1892_Y + connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6225$1896_Y + connect \builder_csrbank9_dfii_pi0_rddata0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6227$1899_Y + connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6228$1903_Y + connect \main_sdram_sel \main_sdram_storage [0] + connect \main_sdram_cke \main_sdram_storage [1] + connect \main_sdram_odt \main_sdram_storage [2] + connect \main_sdram_reset_n \main_sdram_storage [3] + connect \builder_csrbank9_dfii_control0_w \main_sdram_storage + connect \builder_csrbank9_dfii_pi0_command0_w \main_sdram_command_storage + connect \builder_csrbank9_dfii_pi0_address1_w \main_sdram_address_storage [12:8] + connect \builder_csrbank9_dfii_pi0_address0_w \main_sdram_address_storage [7:0] + connect \builder_csrbank9_dfii_pi0_baddress0_w \main_sdram_baddress_storage + connect \builder_csrbank9_dfii_pi0_wrdata1_w \main_sdram_wrdata_storage [15:8] + connect \builder_csrbank9_dfii_pi0_wrdata0_w \main_sdram_wrdata_storage [7:0] + connect \builder_csrbank9_dfii_pi0_rddata1_w \main_sdram_status [15:8] + connect \builder_csrbank9_dfii_pi0_rddata0_w \main_sdram_status [7:0] + connect \main_sdram_we \builder_csrbank9_dfii_pi0_rddata0_we + connect \builder_csrbank10_sel $eq$ls180.v:6243$1904_Y + connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_control1_re $and$ls180.v:6245$1907_Y + connect \builder_csrbank10_control1_we $and$ls180.v:6246$1911_Y + connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_control0_re $and$ls180.v:6248$1914_Y + connect \builder_csrbank10_control0_we $and$ls180.v:6249$1918_Y + connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_status_re $and$ls180.v:6251$1921_Y + connect \builder_csrbank10_status_we $and$ls180.v:6252$1925_Y + connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_mosi0_re $and$ls180.v:6254$1928_Y + connect \builder_csrbank10_mosi0_we $and$ls180.v:6255$1932_Y + connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_miso_re $and$ls180.v:6257$1935_Y + connect \builder_csrbank10_miso_we $and$ls180.v:6258$1939_Y + connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_cs0_re $and$ls180.v:6260$1942_Y + connect \builder_csrbank10_cs0_we $and$ls180.v:6261$1946_Y + connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_loopback0_re $and$ls180.v:6263$1949_Y + connect \builder_csrbank10_loopback0_we $and$ls180.v:6264$1953_Y + connect \main_spi_master_length1 \main_spi_master_control_storage [15:8] + connect \builder_csrbank10_control1_w \main_spi_master_control_storage [15:8] + connect \builder_csrbank10_control0_w \main_spi_master_control_storage [7:0] + connect \main_spi_master_status_status \main_spi_master_done1 + connect \builder_csrbank10_status_w \main_spi_master_status_status + connect \main_spi_master_status_we \builder_csrbank10_status_we + connect \builder_csrbank10_mosi0_w \main_spi_master_mosi_storage + connect \builder_csrbank10_miso_w \main_spi_master_miso_status + connect \main_spi_master_miso_we \builder_csrbank10_miso_we + connect \main_spi_master_sel \main_spi_master_cs_storage + connect \builder_csrbank10_cs0_w \main_spi_master_cs_storage + connect \builder_csrbank10_loopback0_w \main_spi_master_loopback_storage + connect \builder_csrbank11_sel $eq$ls180.v:6283$1955_Y + connect \builder_csrbank11_control1_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_control1_re $and$ls180.v:6285$1958_Y + connect \builder_csrbank11_control1_we $and$ls180.v:6286$1962_Y + connect \builder_csrbank11_control0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_control0_re $and$ls180.v:6288$1965_Y + connect \builder_csrbank11_control0_we $and$ls180.v:6289$1969_Y + connect \builder_csrbank11_status_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_status_re $and$ls180.v:6291$1972_Y + connect \builder_csrbank11_status_we $and$ls180.v:6292$1976_Y + connect \builder_csrbank11_mosi0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_mosi0_re $and$ls180.v:6294$1979_Y + connect \builder_csrbank11_mosi0_we $and$ls180.v:6295$1983_Y + connect \builder_csrbank11_miso_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_miso_re $and$ls180.v:6297$1986_Y + connect \builder_csrbank11_miso_we $and$ls180.v:6298$1990_Y + connect \builder_csrbank11_cs0_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_cs0_re $and$ls180.v:6300$1993_Y + connect \builder_csrbank11_cs0_we $and$ls180.v:6301$1997_Y + connect \builder_csrbank11_loopback0_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_loopback0_re $and$ls180.v:6303$2000_Y + connect \builder_csrbank11_loopback0_we $and$ls180.v:6304$2004_Y + connect \builder_csrbank11_clk_divider1_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6306$2007_Y + connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6307$2011_Y + connect \builder_csrbank11_clk_divider0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6309$2014_Y + connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6310$2018_Y + connect \libresocsim_length1 \libresocsim_control_storage [15:8] + connect \builder_csrbank11_control1_w \libresocsim_control_storage [15:8] + connect \builder_csrbank11_control0_w \libresocsim_control_storage [7:0] + connect \libresocsim_status_status \libresocsim_done1 + connect \builder_csrbank11_status_w \libresocsim_status_status + connect \libresocsim_status_we \builder_csrbank11_status_we + connect \builder_csrbank11_mosi0_w \libresocsim_mosi_storage + connect \builder_csrbank11_miso_w \libresocsim_miso_status + connect \libresocsim_miso_we \builder_csrbank11_miso_we + connect \libresocsim_sel \libresocsim_cs_storage + connect \builder_csrbank11_cs0_w \libresocsim_cs_storage + connect \builder_csrbank11_loopback0_w \libresocsim_loopback_storage + connect \builder_csrbank11_clk_divider1_w \libresocsim_storage [15:8] + connect \builder_csrbank11_clk_divider0_w \libresocsim_storage [7:0] + connect \builder_csrbank12_sel $eq$ls180.v:6331$2020_Y + connect \builder_csrbank12_load3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load3_re $and$ls180.v:6333$2023_Y + connect \builder_csrbank12_load3_we $and$ls180.v:6334$2027_Y + connect \builder_csrbank12_load2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load2_re $and$ls180.v:6336$2030_Y + connect \builder_csrbank12_load2_we $and$ls180.v:6337$2034_Y + connect \builder_csrbank12_load1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load1_re $and$ls180.v:6339$2037_Y + connect \builder_csrbank12_load1_we $and$ls180.v:6340$2041_Y + connect \builder_csrbank12_load0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load0_re $and$ls180.v:6342$2044_Y + connect \builder_csrbank12_load0_we $and$ls180.v:6343$2048_Y + connect \builder_csrbank12_reload3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload3_re $and$ls180.v:6345$2051_Y + connect \builder_csrbank12_reload3_we $and$ls180.v:6346$2055_Y + connect \builder_csrbank12_reload2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload2_re $and$ls180.v:6348$2058_Y + connect \builder_csrbank12_reload2_we $and$ls180.v:6349$2062_Y + connect \builder_csrbank12_reload1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload1_re $and$ls180.v:6351$2065_Y + connect \builder_csrbank12_reload1_we $and$ls180.v:6352$2069_Y + connect \builder_csrbank12_reload0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload0_re $and$ls180.v:6354$2072_Y + connect \builder_csrbank12_reload0_we $and$ls180.v:6355$2076_Y + connect \builder_csrbank12_en0_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_en0_re $and$ls180.v:6357$2079_Y + connect \builder_csrbank12_en0_we $and$ls180.v:6358$2083_Y + connect \builder_csrbank12_update_value0_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_update_value0_re $and$ls180.v:6360$2086_Y + connect \builder_csrbank12_update_value0_we $and$ls180.v:6361$2090_Y + connect \builder_csrbank12_value3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value3_re $and$ls180.v:6363$2093_Y + connect \builder_csrbank12_value3_we $and$ls180.v:6364$2097_Y + connect \builder_csrbank12_value2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value2_re $and$ls180.v:6366$2100_Y + connect \builder_csrbank12_value2_we $and$ls180.v:6367$2104_Y + connect \builder_csrbank12_value1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value1_re $and$ls180.v:6369$2107_Y + connect \builder_csrbank12_value1_we $and$ls180.v:6370$2111_Y + connect \builder_csrbank12_value0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value0_re $and$ls180.v:6372$2114_Y + connect \builder_csrbank12_value0_we $and$ls180.v:6373$2118_Y + connect \main_libresocsim_eventmanager_status_r \builder_interface12_bank_bus_dat_w [0] + connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6375$2121_Y + connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6376$2125_Y + connect \main_libresocsim_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [0] + connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6378$2128_Y + connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6379$2132_Y + connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6381$2135_Y + connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6382$2139_Y + connect \builder_csrbank12_load3_w \main_libresocsim_load_storage [31:24] + connect \builder_csrbank12_load2_w \main_libresocsim_load_storage [23:16] + connect \builder_csrbank12_load1_w \main_libresocsim_load_storage [15:8] + connect \builder_csrbank12_load0_w \main_libresocsim_load_storage [7:0] + connect \builder_csrbank12_reload3_w \main_libresocsim_reload_storage [31:24] + connect \builder_csrbank12_reload2_w \main_libresocsim_reload_storage [23:16] + connect \builder_csrbank12_reload1_w \main_libresocsim_reload_storage [15:8] + connect \builder_csrbank12_reload0_w \main_libresocsim_reload_storage [7:0] + connect \builder_csrbank12_en0_w \main_libresocsim_en_storage + connect \builder_csrbank12_update_value0_w \main_libresocsim_update_value_storage + connect \builder_csrbank12_value3_w \main_libresocsim_value_status [31:24] + connect \builder_csrbank12_value2_w \main_libresocsim_value_status [23:16] + connect \builder_csrbank12_value1_w \main_libresocsim_value_status [15:8] + connect \builder_csrbank12_value0_w \main_libresocsim_value_status [7:0] + connect \main_libresocsim_value_we \builder_csrbank12_value0_we + connect \builder_csrbank12_ev_enable0_w \main_libresocsim_eventmanager_storage + connect \builder_csrbank13_sel $eq$ls180.v:6399$2140_Y + connect \main_uart_rxtx_r \builder_interface13_bank_bus_dat_w + connect \main_uart_rxtx_re $and$ls180.v:6401$2143_Y + connect \main_uart_rxtx_we $and$ls180.v:6402$2147_Y + connect \builder_csrbank13_txfull_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_txfull_re $and$ls180.v:6404$2150_Y + connect \builder_csrbank13_txfull_we $and$ls180.v:6405$2154_Y + connect \builder_csrbank13_rxempty_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_rxempty_re $and$ls180.v:6407$2157_Y + connect \builder_csrbank13_rxempty_we $and$ls180.v:6408$2161_Y + connect \main_uart_eventmanager_status_r \builder_interface13_bank_bus_dat_w [1:0] + connect \main_uart_eventmanager_status_re $and$ls180.v:6410$2164_Y + connect \main_uart_eventmanager_status_we $and$ls180.v:6411$2168_Y + connect \main_uart_eventmanager_pending_r \builder_interface13_bank_bus_dat_w [1:0] + connect \main_uart_eventmanager_pending_re $and$ls180.v:6413$2171_Y + connect \main_uart_eventmanager_pending_we $and$ls180.v:6414$2175_Y + connect \builder_csrbank13_ev_enable0_r \builder_interface13_bank_bus_dat_w [1:0] + connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6416$2178_Y + connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6417$2182_Y + connect \builder_csrbank13_txempty_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_txempty_re $and$ls180.v:6419$2185_Y + connect \builder_csrbank13_txempty_we $and$ls180.v:6420$2189_Y + connect \builder_csrbank13_rxfull_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_rxfull_re $and$ls180.v:6422$2192_Y + connect \builder_csrbank13_rxfull_we $and$ls180.v:6423$2196_Y + connect \builder_csrbank13_txfull_w \main_uart_txfull_status + connect \main_uart_txfull_we \builder_csrbank13_txfull_we + connect \builder_csrbank13_rxempty_w \main_uart_rxempty_status + connect \main_uart_rxempty_we \builder_csrbank13_rxempty_we + connect \builder_csrbank13_ev_enable0_w \main_uart_eventmanager_storage + connect \builder_csrbank13_txempty_w \main_uart_txempty_status + connect \main_uart_txempty_we \builder_csrbank13_txempty_we + connect \builder_csrbank13_rxfull_w \main_uart_rxfull_status + connect \main_uart_rxfull_we \builder_csrbank13_rxfull_we + connect \builder_csrbank14_sel $eq$ls180.v:6433$2197_Y + connect \builder_csrbank14_tuning_word3_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6435$2200_Y + connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6436$2204_Y + connect \builder_csrbank14_tuning_word2_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6438$2207_Y + connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6439$2211_Y + connect \builder_csrbank14_tuning_word1_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6441$2214_Y + connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6442$2218_Y + connect \builder_csrbank14_tuning_word0_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6444$2221_Y + connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6445$2225_Y + connect \builder_csrbank14_tuning_word3_w \main_uart_phy_storage [31:24] + connect \builder_csrbank14_tuning_word2_w \main_uart_phy_storage [23:16] + connect \builder_csrbank14_tuning_word1_w \main_uart_phy_storage [15:8] + connect \builder_csrbank14_tuning_word0_w \main_uart_phy_storage [7:0] + connect \builder_csr_interconnect_adr \builder_libresocsim_adr + connect \builder_csr_interconnect_we \builder_libresocsim_we + connect \builder_csr_interconnect_dat_w \builder_libresocsim_dat_w + connect \builder_libresocsim_dat_r \builder_csr_interconnect_dat_r + connect \builder_interface0_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface1_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface2_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface3_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface4_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface5_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface6_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface7_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface8_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface9_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface10_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface11_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface12_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface13_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface14_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface0_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface1_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface2_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface3_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface4_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface5_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface6_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface7_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface8_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface9_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface10_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface11_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface12_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface13_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface14_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface0_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface1_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface2_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface3_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface4_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface5_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface6_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface7_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface8_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface9_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface10_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface11_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface14_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_csr_interconnect_dat_r $or$ls180.v:6499$2239_Y + connect \sdrio_clk \sys_clk_1 + connect \sdrio_clk_1 \sys_clk_1 + connect \sdrio_clk_2 \sys_clk_1 + connect \sdrio_clk_3 \sys_clk_1 + connect \sdrio_clk_4 \sys_clk_1 + connect \sdrio_clk_5 \sys_clk_1 + connect \sdrio_clk_6 \sys_clk_1 + connect \sdrio_clk_7 \sys_clk_1 + connect \sdrio_clk_8 \sys_clk_1 + connect \sdrio_clk_9 \sys_clk_1 + connect \sdrio_clk_10 \sys_clk_1 + connect \sdrio_clk_11 \sys_clk_1 + connect \sdrio_clk_12 \sys_clk_1 + connect \sdrio_clk_13 \sys_clk_1 + connect \sdrio_clk_14 \sys_clk_1 + connect \sdrio_clk_15 \sys_clk_1 + connect \sdrio_clk_16 \sys_clk_1 + connect \sdrio_clk_17 \sys_clk_1 + connect \sdrio_clk_18 \sys_clk_1 + connect \sdrio_clk_19 \sys_clk_1 + connect \sdrio_clk_20 \sys_clk_1 + connect \sdrio_clk_21 \sys_clk_1 + connect \sdrio_clk_22 \sys_clk_1 + connect \sdrio_clk_23 \sys_clk_1 + connect \sdrio_clk_24 \sys_clk_1 + connect \sdrio_clk_25 \sys_clk_1 + connect \sdrio_clk_26 \sys_clk_1 + connect \sdrio_clk_27 \sys_clk_1 + connect \sdrio_clk_28 \sys_clk_1 + connect \sdrio_clk_29 \sys_clk_1 + connect \sdrio_clk_30 \sys_clk_1 + connect \sdrio_clk_31 \sys_clk_1 + connect \sdrio_clk_32 \sys_clk_1 + connect \sdrio_clk_33 \sys_clk_1 + connect \sdrio_clk_34 \sys_clk_1 + connect \sdrio_clk_35 \sys_clk_1 + connect \sdrio_clk_36 \sys_clk_1 + connect \sdrio_clk_37 \sys_clk_1 + connect \sdrio_clk_38 \sys_clk_1 + connect \sdrio_clk_39 \sys_clk_1 + connect \sdrio_clk_40 \sys_clk_1 + connect \sdrio_clk_41 \sys_clk_1 + connect \sdrio_clk_42 \sys_clk_1 + connect \sdrio_clk_43 \sys_clk_1 + connect \sdrio_clk_44 \sys_clk_1 + connect \sdrio_clk_45 \sys_clk_1 + connect \sdrio_clk_46 \sys_clk_1 + connect \sdrio_clk_47 \sys_clk_1 + connect \sdrio_clk_48 \sys_clk_1 + connect \sdrio_clk_49 \sys_clk_1 + connect \sdrio_clk_50 \sys_clk_1 + connect \sdrio_clk_51 \sys_clk_1 + connect \sdrio_clk_52 \sys_clk_1 + connect \sdrio_clk_53 \sys_clk_1 + connect \sdrio_clk_54 \sys_clk_1 + connect \sdrio_clk_55 \sys_clk_1 + connect \main_uart_phy_rx \builder_multiregimpl0_regs1 + connect \main_pwm0_enable \main_pwm0_enable_storage + connect \main_pwm0_width \main_pwm0_width_storage + connect \main_pwm0_period \main_pwm0_period_storage + connect \main_pwm1_enable \main_pwm1_enable_storage + connect \main_pwm1_width \main_pwm1_width_storage + connect \main_pwm1_period \main_pwm1_period_storage + connect \sdrio_clk_56 \sys_clk_1 + connect \sdrio_clk_57 \sys_clk_1 + connect \sdrio_clk_58 \sys_clk_1 + connect \sdrio_clk_59 \sys_clk_1 + connect \sdrio_clk_60 \sys_clk_1 + connect \sdrio_clk_61 \sys_clk_1 + connect \sdrio_clk_62 \sys_clk_1 + connect \sdrio_clk_63 \sys_clk_1 + connect \sdrio_clk_64 \sys_clk_1 + connect \sdrio_clk_65 \sys_clk_1 + connect \sdrio_clk_66 \sys_clk_1 + connect \sdrio_clk_67 \sys_clk_1 + connect \sdrio_clk_68 \sys_clk_1 + connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10052$2705_DATA + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10070$2712_DATA + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10084$2719_DATA + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10098$2726_DATA + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10112$2733_DATA + connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 + connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 + connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 + connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 + connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 + connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10160$2754_DATA + connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 + connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10174$2761_DATA +end +attribute \src "libresoc.v:44776.1-44787.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.pll" +attribute \generator "nMigen" +module \pll + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:80" + wire input 1 \clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:81" + wire output 4 \clk_pll_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:82" + wire input 2 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:527" + wire output 3 \rst$1 + connect \rst$1 \rst + connect \clk_pll_o \clk_24_i +end +attribute \src "libresoc.v:44791.1-44875.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick + attribute \src "libresoc.v:44848.17-44848.91" + wire $not$libresoc.v:44848$1401_Y + attribute \src "libresoc.v:44850.18-44850.93" + wire $not$libresoc.v:44850$1403_Y + attribute \src "libresoc.v:44852.18-44852.93" + wire $not$libresoc.v:44852$1405_Y + attribute \src "libresoc.v:44853.17-44853.138" + wire width 8 $not$libresoc.v:44853$1406_Y + attribute \src "libresoc.v:44855.18-44855.93" + wire $not$libresoc.v:44855$1408_Y + attribute \src "libresoc.v:44857.18-44857.93" + wire $not$libresoc.v:44857$1410_Y + attribute \src "libresoc.v:44859.18-44859.93" + wire $not$libresoc.v:44859$1412_Y + attribute \src "libresoc.v:44862.17-44862.91" + wire $not$libresoc.v:44862$1415_Y + attribute \src "libresoc.v:44849.18-44849.116" + wire $reduce_or$libresoc.v:44849$1402_Y + attribute \src "libresoc.v:44851.18-44851.122" + wire $reduce_or$libresoc.v:44851$1404_Y + attribute \src "libresoc.v:44854.18-44854.128" + wire $reduce_or$libresoc.v:44854$1407_Y + attribute \src "libresoc.v:44856.18-44856.134" + wire $reduce_or$libresoc.v:44856$1409_Y + attribute \src "libresoc.v:44858.18-44858.140" + wire $reduce_or$libresoc.v:44858$1411_Y + attribute \src "libresoc.v:44860.18-44860.90" + wire $reduce_or$libresoc.v:44860$1413_Y + attribute \src "libresoc.v:44861.17-44861.103" + wire $reduce_or$libresoc.v:44861$1414_Y + attribute \src "libresoc.v:44863.17-44863.109" + wire $reduce_or$libresoc.v:44863$1416_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44848$1401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:44848$1401_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44850$1403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:44850$1403_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44852$1405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:44852$1405_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:44853$1406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:44853$1406_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44855$1408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:44855$1408_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44857$1410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:44857$1410_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44859$1412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:44859$1412_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44862$1415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:44862$1415_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44849$1402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:44849$1402_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44851$1404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:44851$1404_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44854$1407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:44854$1407_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44856$1409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:44856$1409_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44858$1411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:44858$1411_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:44860$1413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:44860$1413_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44861$1414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:44861$1414_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44863$1416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:44863$1416_Y + end + connect \$7 $not$libresoc.v:44848$1401_Y + connect \$12 $reduce_or$libresoc.v:44849$1402_Y + connect \$11 $not$libresoc.v:44850$1403_Y + connect \$16 $reduce_or$libresoc.v:44851$1404_Y + connect \$15 $not$libresoc.v:44852$1405_Y + connect \$1 $not$libresoc.v:44853$1406_Y + connect \$20 $reduce_or$libresoc.v:44854$1407_Y + connect \$19 $not$libresoc.v:44855$1408_Y + connect \$24 $reduce_or$libresoc.v:44856$1409_Y + connect \$23 $not$libresoc.v:44857$1410_Y + connect \$28 $reduce_or$libresoc.v:44858$1411_Y + connect \$27 $not$libresoc.v:44859$1412_Y + connect \$31 $reduce_or$libresoc.v:44860$1413_Y + connect \$4 $reduce_or$libresoc.v:44861$1414_Y + connect \$3 $not$libresoc.v:44862$1415_Y + connect \$8 $reduce_or$libresoc.v:44863$1416_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:44879.1-44963.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$1 + attribute \src "libresoc.v:44936.17-44936.91" + wire $not$libresoc.v:44936$1417_Y + attribute \src "libresoc.v:44938.18-44938.93" + wire $not$libresoc.v:44938$1419_Y + attribute \src "libresoc.v:44940.18-44940.93" + wire $not$libresoc.v:44940$1421_Y + attribute \src "libresoc.v:44941.17-44941.138" + wire width 8 $not$libresoc.v:44941$1422_Y + attribute \src "libresoc.v:44943.18-44943.93" + wire $not$libresoc.v:44943$1424_Y + attribute \src "libresoc.v:44945.18-44945.93" + wire $not$libresoc.v:44945$1426_Y + attribute \src "libresoc.v:44947.18-44947.93" + wire $not$libresoc.v:44947$1428_Y + attribute \src "libresoc.v:44950.17-44950.91" + wire $not$libresoc.v:44950$1431_Y + attribute \src "libresoc.v:44937.18-44937.116" + wire $reduce_or$libresoc.v:44937$1418_Y + attribute \src "libresoc.v:44939.18-44939.122" + wire $reduce_or$libresoc.v:44939$1420_Y + attribute \src "libresoc.v:44942.18-44942.128" + wire $reduce_or$libresoc.v:44942$1423_Y + attribute \src "libresoc.v:44944.18-44944.134" + wire $reduce_or$libresoc.v:44944$1425_Y + attribute \src "libresoc.v:44946.18-44946.140" + wire $reduce_or$libresoc.v:44946$1427_Y + attribute \src "libresoc.v:44948.18-44948.90" + wire $reduce_or$libresoc.v:44948$1429_Y + attribute \src "libresoc.v:44949.17-44949.103" + wire $reduce_or$libresoc.v:44949$1430_Y + attribute \src "libresoc.v:44951.17-44951.109" + wire $reduce_or$libresoc.v:44951$1432_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44936$1417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:44936$1417_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44938$1419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:44938$1419_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44940$1421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:44940$1421_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:44941$1422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:44941$1422_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44943$1424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:44943$1424_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44945$1426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:44945$1426_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44947$1428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:44947$1428_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44950$1431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:44950$1431_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44937$1418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:44937$1418_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44939$1420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:44939$1420_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44942$1423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:44942$1423_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44944$1425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:44944$1425_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44946$1427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:44946$1427_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:44948$1429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:44948$1429_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44949$1430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:44949$1430_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44951$1432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:44951$1432_Y + end + connect \$7 $not$libresoc.v:44936$1417_Y + connect \$12 $reduce_or$libresoc.v:44937$1418_Y + connect \$11 $not$libresoc.v:44938$1419_Y + connect \$16 $reduce_or$libresoc.v:44939$1420_Y + connect \$15 $not$libresoc.v:44940$1421_Y + connect \$1 $not$libresoc.v:44941$1422_Y + connect \$20 $reduce_or$libresoc.v:44942$1423_Y + connect \$19 $not$libresoc.v:44943$1424_Y + connect \$24 $reduce_or$libresoc.v:44944$1425_Y + connect \$23 $not$libresoc.v:44945$1426_Y + connect \$28 $reduce_or$libresoc.v:44946$1427_Y + connect \$27 $not$libresoc.v:44947$1428_Y + connect \$31 $reduce_or$libresoc.v:44948$1429_Y + connect \$4 $reduce_or$libresoc.v:44949$1430_Y + connect \$3 $not$libresoc.v:44950$1431_Y + connect \$8 $reduce_or$libresoc.v:44951$1432_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:44967.1-45782.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap" +attribute \generator "nMigen" +module \sprmap + attribute \src "libresoc.v:45094.3-45124.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:45125.3-45155.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:44968.7-44968.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:45156.3-45468.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:45469.3-45781.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:45094.3-45124.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:45125.3-45155.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:45156.3-45468.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:45469.3-45781.6" + wire $1\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 3 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \fast_o_ok + attribute \src "libresoc.v:44968.7-44968.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + wire width 10 input 5 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 1 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \spr_o_ok + attribute \src "libresoc.v:44968.7-44968.20" + process $proc$libresoc.v:44968$1437 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:45094.3-45124.6" + process $proc$libresoc.v:45094$1433 + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:45095.5-45095.29" + switch \initial + attribute \src "libresoc.v:45095.9-45095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o[2:0] 3'111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o[2:0] 3'010 + case + assign $1\fast_o[2:0] 3'000 + end + sync always + update \fast_o $0\fast_o[2:0] + end + attribute \src "libresoc.v:45125.3-45155.6" + process $proc$libresoc.v:45125$1434 + assign { } { } + assign { } { } + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:45126.5-45126.29" + switch \initial + attribute \src "libresoc.v:45126.9-45126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + case + assign $1\fast_o_ok[0:0] 1'0 + end + sync always + update \fast_o_ok $0\fast_o_ok[0:0] + end + attribute \src "libresoc.v:45156.3-45468.6" + process $proc$libresoc.v:45156$1435 + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + attribute \src "libresoc.v:45157.5-45157.29" + switch \initial + attribute \src "libresoc.v:45157.9-45157.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o[9:0] 10'0000010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0000101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000101101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o[9:0] 10'0000101110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o[9:0] 10'0000101111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000110001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o[9:0] 10'0000110010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o[9:0] 10'0000110100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000110101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o[9:0] 10'0000111000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000111010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000111011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000111100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000111101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000111110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o[9:0] 10'0001000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0001000011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o[9:0] 10'0001000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o[9:0] 10'0001000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o[9:0] 10'0001000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o[9:0] 10'0001000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o[9:0] 10'0001001001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o[9:0] 10'0001001010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0001001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o[9:0] 10'0001001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0001001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o[9:0] 10'0001010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o[9:0] 10'0001010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o[9:0] 10'0001010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0001011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o[9:0] 10'0001011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o[9:0] 10'0001011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o[9:0] 10'0001011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o[9:0] 10'0001011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o[9:0] 10'0001011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o[9:0] 10'0001100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o[9:0] 10'0001100010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o[9:0] 10'0001100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o[9:0] 10'0001100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o[9:0] 10'0001100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101101 + case + assign $1\spr_o[9:0] 10'0000000000 + end + sync always + update \spr_o $0\spr_o[9:0] + end + attribute \src "libresoc.v:45469.3-45781.6" + process $proc$libresoc.v:45469$1436 + assign { } { } + assign { } { } + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:45470.5-45470.29" + switch \initial + attribute \src "libresoc.v:45470.9-45470.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + case + assign $1\spr_o_ok[0:0] 1'0 + end + sync always + update \spr_o_ok $0\spr_o_ok[0:0] + end +end +attribute \src "libresoc.v:45786.1-46601.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap" +attribute \generator "nMigen" +module \sprmap$2 + attribute \src "libresoc.v:45913.3-45943.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:45944.3-45974.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:45787.7-45787.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:45975.3-46287.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:46288.3-46600.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:45913.3-45943.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:45944.3-45974.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:45975.3-46287.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:46288.3-46600.6" + wire $1\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 3 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \fast_o_ok + attribute \src "libresoc.v:45787.7-45787.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + wire width 10 input 5 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 1 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \spr_o_ok + attribute \src "libresoc.v:45787.7-45787.20" + process $proc$libresoc.v:45787$1442 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:45913.3-45943.6" + process $proc$libresoc.v:45913$1438 + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:45914.5-45914.29" + switch \initial + attribute \src "libresoc.v:45914.9-45914.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o[2:0] 3'111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o[2:0] 3'010 + case + assign $1\fast_o[2:0] 3'000 + end + sync always + update \fast_o $0\fast_o[2:0] + end + attribute \src "libresoc.v:45944.3-45974.6" + process $proc$libresoc.v:45944$1439 + assign { } { } + assign { } { } + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:45945.5-45945.29" + switch \initial + attribute \src "libresoc.v:45945.9-45945.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + case + assign $1\fast_o_ok[0:0] 1'0 + end + sync always + update \fast_o_ok $0\fast_o_ok[0:0] + end + attribute \src "libresoc.v:45975.3-46287.6" + process $proc$libresoc.v:45975$1440 + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + attribute \src "libresoc.v:45976.5-45976.29" + switch \initial + attribute \src "libresoc.v:45976.9-45976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o[9:0] 10'0000010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0000101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000101101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o[9:0] 10'0000101110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o[9:0] 10'0000101111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000110001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o[9:0] 10'0000110010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o[9:0] 10'0000110100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000110101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o[9:0] 10'0000111000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000111010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000111011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000111100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000111101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000111110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o[9:0] 10'0001000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0001000011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o[9:0] 10'0001000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o[9:0] 10'0001000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o[9:0] 10'0001000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o[9:0] 10'0001000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o[9:0] 10'0001001001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o[9:0] 10'0001001010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0001001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o[9:0] 10'0001001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0001001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o[9:0] 10'0001010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o[9:0] 10'0001010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o[9:0] 10'0001010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0001011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o[9:0] 10'0001011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o[9:0] 10'0001011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o[9:0] 10'0001011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o[9:0] 10'0001011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o[9:0] 10'0001011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o[9:0] 10'0001100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o[9:0] 10'0001100010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o[9:0] 10'0001100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o[9:0] 10'0001100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o[9:0] 10'0001100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101101 + case + assign $1\spr_o[9:0] 10'0000000000 + end + sync always + update \spr_o $0\spr_o[9:0] + end + attribute \src "libresoc.v:46288.3-46600.6" + process $proc$libresoc.v:46288$1441 + assign { } { } + assign { } { } + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:46289.5-46289.29" + switch \initial + attribute \src "libresoc.v:46289.9-46289.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + case + assign $1\spr_o_ok[0:0] 1'0 + end + sync always + update \spr_o_ok $0\spr_o_ok[0:0] + end +end +attribute \src "libresoc.v:46606.1-47121.10" +attribute \cells_not_processed 1 +attribute \top 1 +attribute \nmigen.hierarchy "test_issuer" +attribute \generator "nMigen" +module \test_issuer + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 9 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 7 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire output 6 \TAP_bus__tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 8 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:92" + wire output 5 \busy_o + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:527" + wire input 166 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:36" + wire width 3 input 164 \clk_sel_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:34" + wire \clksel_clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:37" + wire \clksel_core_clk_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + wire \clksel_pllclk_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:38" + wire \clksel_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:91" + wire input 4 \core_bigendian_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 136 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 input 130 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 2 input 139 \dbus__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 3 input 138 \dbus__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 134 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 132 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 131 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 140 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 input 133 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 135 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 137 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 23 \gpio_gpio0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 24 \gpio_gpio0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 25 \gpio_gpio0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 26 \gpio_gpio0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 27 \gpio_gpio0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 28 \gpio_gpio0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 83 \gpio_gpio10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 84 \gpio_gpio10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 85 \gpio_gpio10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 86 \gpio_gpio10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 87 \gpio_gpio10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 88 \gpio_gpio10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 89 \gpio_gpio11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 90 \gpio_gpio11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 91 \gpio_gpio11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 92 \gpio_gpio11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 93 \gpio_gpio11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 94 \gpio_gpio11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 95 \gpio_gpio12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 96 \gpio_gpio12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 97 \gpio_gpio12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 98 \gpio_gpio12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 99 \gpio_gpio12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 100 \gpio_gpio12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 101 \gpio_gpio13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 102 \gpio_gpio13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 103 \gpio_gpio13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 104 \gpio_gpio13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 105 \gpio_gpio13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 106 \gpio_gpio13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 107 \gpio_gpio14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 108 \gpio_gpio14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 109 \gpio_gpio14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 110 \gpio_gpio14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 111 \gpio_gpio14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 112 \gpio_gpio14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 113 \gpio_gpio15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 114 \gpio_gpio15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 115 \gpio_gpio15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 116 \gpio_gpio15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 117 \gpio_gpio15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 118 \gpio_gpio15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 29 \gpio_gpio1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 30 \gpio_gpio1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 31 \gpio_gpio1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 32 \gpio_gpio1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 33 \gpio_gpio1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 34 \gpio_gpio1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 35 \gpio_gpio2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 36 \gpio_gpio2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 37 \gpio_gpio2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 38 \gpio_gpio2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 39 \gpio_gpio2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 40 \gpio_gpio2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 41 \gpio_gpio3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 42 \gpio_gpio3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 43 \gpio_gpio3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 44 \gpio_gpio3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 45 \gpio_gpio3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 46 \gpio_gpio3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 47 \gpio_gpio4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 48 \gpio_gpio4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 49 \gpio_gpio4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 50 \gpio_gpio4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 51 \gpio_gpio4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 52 \gpio_gpio4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 53 \gpio_gpio5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 54 \gpio_gpio5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 55 \gpio_gpio5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 56 \gpio_gpio5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 57 \gpio_gpio5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 58 \gpio_gpio5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 59 \gpio_gpio6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 60 \gpio_gpio6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 61 \gpio_gpio6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 62 \gpio_gpio6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 63 \gpio_gpio6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 64 \gpio_gpio6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 65 \gpio_gpio7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 66 \gpio_gpio7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 67 \gpio_gpio7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 68 \gpio_gpio7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 69 \gpio_gpio7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 70 \gpio_gpio7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 71 \gpio_gpio8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 72 \gpio_gpio8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 73 \gpio_gpio8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 74 \gpio_gpio8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 75 \gpio_gpio8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 76 \gpio_gpio8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 77 \gpio_gpio9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 78 \gpio_gpio9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 79 \gpio_gpio9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 80 \gpio_gpio9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 81 \gpio_gpio9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 82 \gpio_gpio9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 125 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 119 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 2 input 128 \ibus__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 3 input 127 \ibus__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 123 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 121 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 120 \ibus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 129 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 122 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 124 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 126 \ibus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 147 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 141 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 2 input 150 \icp_wb__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 3 input 149 \icp_wb__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 145 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 143 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 142 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 151 \icp_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 144 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 146 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 148 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire output 158 \ics_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 28 input 152 \ics_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 2 input 161 \ics_wb__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 3 input 160 \ics_wb__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 156 \ics_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 output 154 \ics_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 input 153 \ics_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 162 \ics_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 4 input 155 \ics_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 157 \ics_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 159 \ics_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" + wire width 16 input 163 \int_level_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:457" + wire \intclk_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire input 17 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 29 output 10 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 14 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 64 input 12 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 64 output 11 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire input 18 \jtag_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 13 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 15 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 16 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:93" + wire input 3 \memerr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 168 \pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 1 \pc_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:89" + wire width 64 output 2 \pc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:35" + wire output 165 \pll_48_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:80" + wire \pll_clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:81" + wire \pll_clk_pll_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:82" + wire \pll_rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:527" + wire output 167 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 21 \uart_rx__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 22 \uart_rx__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 19 \uart_tx__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 20 \uart_tx__pad__o + attribute \module_not_derived 1 + attribute \src "libresoc.v:46959.10-46966.4" + cell \clksel \clksel + connect \clk_24_i \clksel_clk_24_i + connect \clk_sel_i \clk_sel_i + connect \core_clk_o \clksel_core_clk_o + connect \pll_48_o \pll_48_o + connect \pllclk_clk \clksel_pllclk_clk + connect \rst \clksel_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:46967.7-46972.4" + cell \pll \pll + connect \clk_24_i \pll_clk_24_i + connect \clk_pll_o \pll_clk_pll_o + connect \rst \pll_rst + connect \rst$1 \rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:46973.6-47114.4" + cell \ti \ti + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_bus__tdo \TAP_bus__tdo + connect \TAP_bus__tms \TAP_bus__tms + connect \busy_o \busy_o + connect \core_bigendian_i \core_bigendian_i + connect \gpio_gpio0__core__i \gpio_gpio0__core__i + connect \gpio_gpio0__core__o \gpio_gpio0__core__o + connect \gpio_gpio0__core__oe \gpio_gpio0__core__oe + connect \gpio_gpio0__pad__i \gpio_gpio0__pad__i + connect \gpio_gpio0__pad__o \gpio_gpio0__pad__o + connect \gpio_gpio0__pad__oe \gpio_gpio0__pad__oe + connect \gpio_gpio10__core__i \gpio_gpio10__core__i + connect \gpio_gpio10__core__o \gpio_gpio10__core__o + connect \gpio_gpio10__core__oe \gpio_gpio10__core__oe + connect \gpio_gpio10__pad__i \gpio_gpio10__pad__i + connect \gpio_gpio10__pad__o \gpio_gpio10__pad__o + connect \gpio_gpio10__pad__oe \gpio_gpio10__pad__oe + connect \gpio_gpio11__core__i \gpio_gpio11__core__i + connect \gpio_gpio11__core__o \gpio_gpio11__core__o + connect \gpio_gpio11__core__oe \gpio_gpio11__core__oe + connect \gpio_gpio11__pad__i \gpio_gpio11__pad__i + connect \gpio_gpio11__pad__o \gpio_gpio11__pad__o + connect \gpio_gpio11__pad__oe \gpio_gpio11__pad__oe + connect \gpio_gpio12__core__i \gpio_gpio12__core__i + connect \gpio_gpio12__core__o \gpio_gpio12__core__o + connect \gpio_gpio12__core__oe \gpio_gpio12__core__oe + connect \gpio_gpio12__pad__i \gpio_gpio12__pad__i + connect \gpio_gpio12__pad__o \gpio_gpio12__pad__o + connect \gpio_gpio12__pad__oe \gpio_gpio12__pad__oe + connect \gpio_gpio13__core__i \gpio_gpio13__core__i + connect \gpio_gpio13__core__o \gpio_gpio13__core__o + connect \gpio_gpio13__core__oe \gpio_gpio13__core__oe + connect \gpio_gpio13__pad__i \gpio_gpio13__pad__i + connect \gpio_gpio13__pad__o \gpio_gpio13__pad__o + connect \gpio_gpio13__pad__oe \gpio_gpio13__pad__oe + connect \gpio_gpio14__core__i \gpio_gpio14__core__i + connect \gpio_gpio14__core__o \gpio_gpio14__core__o + connect \gpio_gpio14__core__oe \gpio_gpio14__core__oe + connect \gpio_gpio14__pad__i \gpio_gpio14__pad__i + connect \gpio_gpio14__pad__o \gpio_gpio14__pad__o + connect \gpio_gpio14__pad__oe \gpio_gpio14__pad__oe + connect \gpio_gpio15__core__i \gpio_gpio15__core__i + connect \gpio_gpio15__core__o \gpio_gpio15__core__o + connect \gpio_gpio15__core__oe \gpio_gpio15__core__oe + connect \gpio_gpio15__pad__i \gpio_gpio15__pad__i + connect \gpio_gpio15__pad__o \gpio_gpio15__pad__o + connect \gpio_gpio15__pad__oe \gpio_gpio15__pad__oe + connect \gpio_gpio1__core__i \gpio_gpio1__core__i + connect \gpio_gpio1__core__o \gpio_gpio1__core__o + connect \gpio_gpio1__core__oe \gpio_gpio1__core__oe + connect \gpio_gpio1__pad__i \gpio_gpio1__pad__i + connect \gpio_gpio1__pad__o \gpio_gpio1__pad__o + connect \gpio_gpio1__pad__oe \gpio_gpio1__pad__oe + connect \gpio_gpio2__core__i \gpio_gpio2__core__i + connect \gpio_gpio2__core__o \gpio_gpio2__core__o + connect \gpio_gpio2__core__oe \gpio_gpio2__core__oe + connect \gpio_gpio2__pad__i \gpio_gpio2__pad__i + connect \gpio_gpio2__pad__o \gpio_gpio2__pad__o + connect \gpio_gpio2__pad__oe \gpio_gpio2__pad__oe + connect \gpio_gpio3__core__i \gpio_gpio3__core__i + connect \gpio_gpio3__core__o \gpio_gpio3__core__o + connect \gpio_gpio3__core__oe \gpio_gpio3__core__oe + connect \gpio_gpio3__pad__i \gpio_gpio3__pad__i + connect \gpio_gpio3__pad__o \gpio_gpio3__pad__o + connect \gpio_gpio3__pad__oe \gpio_gpio3__pad__oe + connect \gpio_gpio4__core__i \gpio_gpio4__core__i + connect \gpio_gpio4__core__o \gpio_gpio4__core__o + connect \gpio_gpio4__core__oe \gpio_gpio4__core__oe + connect \gpio_gpio4__pad__i \gpio_gpio4__pad__i + connect \gpio_gpio4__pad__o \gpio_gpio4__pad__o + connect \gpio_gpio4__pad__oe \gpio_gpio4__pad__oe + connect \gpio_gpio5__core__i \gpio_gpio5__core__i + connect \gpio_gpio5__core__o \gpio_gpio5__core__o + connect \gpio_gpio5__core__oe \gpio_gpio5__core__oe + connect \gpio_gpio5__pad__i \gpio_gpio5__pad__i + connect \gpio_gpio5__pad__o \gpio_gpio5__pad__o + connect \gpio_gpio5__pad__oe \gpio_gpio5__pad__oe + connect \gpio_gpio6__core__i \gpio_gpio6__core__i + connect \gpio_gpio6__core__o \gpio_gpio6__core__o + connect \gpio_gpio6__core__oe \gpio_gpio6__core__oe + connect \gpio_gpio6__pad__i \gpio_gpio6__pad__i + connect \gpio_gpio6__pad__o \gpio_gpio6__pad__o + connect \gpio_gpio6__pad__oe \gpio_gpio6__pad__oe + connect \gpio_gpio7__core__i \gpio_gpio7__core__i + connect \gpio_gpio7__core__o \gpio_gpio7__core__o + connect \gpio_gpio7__core__oe \gpio_gpio7__core__oe + connect \gpio_gpio7__pad__i \gpio_gpio7__pad__i + connect \gpio_gpio7__pad__o \gpio_gpio7__pad__o + connect \gpio_gpio7__pad__oe \gpio_gpio7__pad__oe + connect \gpio_gpio8__core__i \gpio_gpio8__core__i + connect \gpio_gpio8__core__o \gpio_gpio8__core__o + connect \gpio_gpio8__core__oe \gpio_gpio8__core__oe + connect \gpio_gpio8__pad__i \gpio_gpio8__pad__i + connect \gpio_gpio8__pad__o \gpio_gpio8__pad__o + connect \gpio_gpio8__pad__oe \gpio_gpio8__pad__oe + connect \gpio_gpio9__core__i \gpio_gpio9__core__i + connect \gpio_gpio9__core__o \gpio_gpio9__core__o + connect \gpio_gpio9__core__oe \gpio_gpio9__core__oe + connect \gpio_gpio9__pad__i \gpio_gpio9__pad__i + connect \gpio_gpio9__pad__o \gpio_gpio9__pad__o + connect \gpio_gpio9__pad__oe \gpio_gpio9__pad__oe + connect \ibus__ack \ibus__ack + connect \ibus__adr \ibus__adr + connect \ibus__cyc \ibus__cyc + connect \ibus__dat_r \ibus__dat_r + connect \ibus__err \ibus__err + connect \ibus__sel \ibus__sel + connect \ibus__stb \ibus__stb + connect \icp_wb__ack \icp_wb__ack + connect \icp_wb__adr \icp_wb__adr + connect \icp_wb__cyc \icp_wb__cyc + connect \icp_wb__dat_r \icp_wb__dat_r + connect \icp_wb__dat_w \icp_wb__dat_w + connect \icp_wb__sel \icp_wb__sel + connect \icp_wb__stb \icp_wb__stb + connect \icp_wb__we \icp_wb__we + connect \ics_wb__ack \ics_wb__ack + connect \ics_wb__adr \ics_wb__adr + connect \ics_wb__cyc \ics_wb__cyc + connect \ics_wb__dat_r \ics_wb__dat_r + connect \ics_wb__dat_w \ics_wb__dat_w + connect \ics_wb__stb \ics_wb__stb + connect \ics_wb__we \ics_wb__we + connect \int_level_i \int_level_i + connect \jtag_wb__ack \jtag_wb__ack + connect \jtag_wb__adr \jtag_wb__adr + connect \jtag_wb__cyc \jtag_wb__cyc + connect \jtag_wb__dat_r \jtag_wb__dat_r + connect \jtag_wb__dat_w \jtag_wb__dat_w + connect \jtag_wb__sel \jtag_wb__sel + connect \jtag_wb__stb \jtag_wb__stb + connect \jtag_wb__we \jtag_wb__we + connect \pc_i \pc_i + connect \pc_i_ok \pc_i_ok + connect \pc_o \pc_o + connect \uart_rx__core__i \uart_rx__core__i + connect \uart_rx__pad__i \uart_rx__pad__i + connect \uart_tx__core__o \uart_tx__core__o + connect \uart_tx__pad__o \uart_tx__pad__o + end + connect \clksel_rst \rst + connect \pll_rst \rst + connect \pll_clk_24_i \clksel_clk_24_i + connect \clksel_clk_24_i \clk + connect \clksel_pllclk_clk \pll_clk_pll_o + connect \intclk_clk \clksel_core_clk_o +end +attribute \src "libresoc.v:47125.1-50180.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti" +attribute \generator "nMigen" +module \ti + attribute \src "libresoc.v:49784.3-49820.6" + wire $0\bigendian_i$next[0:0]$1884 + attribute \src "libresoc.v:48789.3-48790.39" + wire $0\bigendian_i[0:0] + attribute \src "libresoc.v:49508.3-49520.6" + wire width 4 $0\cia__ren[3:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 8 $0\core_asmcode$next[7:0]$1645 + attribute \src "libresoc.v:48793.3-48794.41" + wire width 8 $0\core_asmcode[7:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 64 $0\core_core_cia$next[63:0]$1646 + attribute \src "libresoc.v:48861.3-48862.43" + wire width 64 $0\core_core_cia[63:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 8 $0\core_core_cr_rd$next[7:0]$1647 + attribute \src "libresoc.v:48887.3-48888.47" + wire width 8 $0\core_core_cr_rd[7:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_core_cr_rd_ok$next[0:0]$1648 + attribute \src "libresoc.v:48889.3-48890.53" + wire $0\core_core_cr_rd_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 8 $0\core_core_cr_wr$next[7:0]$1649 + attribute \src "libresoc.v:48893.3-48894.47" + wire width 8 $0\core_core_cr_wr[7:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_core_cr_wr_ok$next[0:0]$1650 + attribute \src "libresoc.v:48895.3-48896.53" + wire $0\core_core_cr_wr_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 12 $0\core_core_fn_unit$next[11:0]$1651 + attribute \src "libresoc.v:48867.3-48868.51" + wire width 12 $0\core_core_fn_unit[11:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 2 $0\core_core_input_carry$next[1:0]$1652 + attribute \src "libresoc.v:48881.3-48882.59" + wire width 2 $0\core_core_input_carry[1:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 32 $0\core_core_insn$next[31:0]$1653 + attribute \src "libresoc.v:48863.3-48864.45" + wire width 32 $0\core_core_insn[31:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 7 $0\core_core_insn_type$next[6:0]$1654 + attribute \src "libresoc.v:48865.3-48866.55" + wire width 7 $0\core_core_insn_type[6:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_core_is_32bit$next[0:0]$1655 + attribute \src "libresoc.v:48897.3-48898.53" + wire $0\core_core_is_32bit[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_core_lk$next[0:0]$1656 + attribute \src "libresoc.v:48871.3-48872.41" + wire $0\core_core_lk[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 64 $0\core_core_msr$next[63:0]$1657 + attribute \src "libresoc.v:48859.3-48860.43" + wire width 64 $0\core_core_msr[63:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_core_oe$next[0:0]$1658 + attribute \src "libresoc.v:48877.3-48878.41" + wire $0\core_core_oe[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_core_oe_ok$next[0:0]$1659 + attribute \src "libresoc.v:48879.3-48880.47" + wire $0\core_core_oe_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_core_rc$next[0:0]$1660 + attribute \src "libresoc.v:48873.3-48874.41" + wire $0\core_core_rc[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_core_rc_ok$next[0:0]$1661 + attribute \src "libresoc.v:48875.3-48876.47" + wire $0\core_core_rc_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 13 $0\core_core_trapaddr$next[12:0]$1662 + attribute \src "libresoc.v:48885.3-48886.53" + wire width 13 $0\core_core_trapaddr[12:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 7 $0\core_core_traptype$next[6:0]$1663 + attribute \src "libresoc.v:48883.3-48884.53" + wire width 7 $0\core_core_traptype[6:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $0\core_cr_in1$next[2:0]$1664 + attribute \src "libresoc.v:48843.3-48844.39" + wire width 3 $0\core_cr_in1[2:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_cr_in1_ok$next[0:0]$1665 + attribute \src "libresoc.v:48845.3-48846.45" + wire $0\core_cr_in1_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $0\core_cr_in2$39$next[2:0]$1666 + attribute \src "libresoc.v:48851.3-48852.47" + wire width 3 $0\core_cr_in2$39[2:0]$1543 + attribute \src "libresoc.v:47445.13-47445.36" + wire width 3 $0\core_cr_in2$39[2:0]$1969 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $0\core_cr_in2$next[2:0]$1667 + attribute \src "libresoc.v:48847.3-48848.39" + wire width 3 $0\core_cr_in2[2:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_cr_in2_ok$40$next[0:0]$1668 + attribute \src "libresoc.v:48853.3-48854.53" + wire $0\core_cr_in2_ok$40[0:0]$1545 + attribute \src "libresoc.v:47453.7-47453.33" + wire $0\core_cr_in2_ok$40[0:0]$1972 + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_cr_in2_ok$next[0:0]$1669 + attribute \src "libresoc.v:48849.3-48850.45" + wire $0\core_cr_in2_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $0\core_cr_out$next[2:0]$1670 + attribute \src "libresoc.v:48855.3-48856.39" + wire width 3 $0\core_cr_out[2:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_cr_out_ok$next[0:0]$1671 + attribute \src "libresoc.v:48857.3-48858.45" + wire $0\core_cr_out_ok[0:0] + attribute \src "libresoc.v:50072.3-50103.6" + wire width 64 $0\core_dec$next[63:0]$1922 + attribute \src "libresoc.v:48779.3-48780.33" + wire width 64 $0\core_dec[63:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 5 $0\core_ea$next[4:0]$1672 + attribute \src "libresoc.v:48799.3-48800.31" + wire width 5 $0\core_ea[4:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_ea_ok$next[0:0]$1673 + attribute \src "libresoc.v:48801.3-48802.37" + wire $0\core_ea_ok[0:0] + attribute \src "libresoc.v:50072.3-50103.6" + wire $0\core_eint$next[0:0]$1923 + attribute \src "libresoc.v:48777.3-48778.35" + wire $0\core_eint[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $0\core_fast1$next[2:0]$1674 + attribute \src "libresoc.v:48827.3-48828.37" + wire width 3 $0\core_fast1[2:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_fast1_ok$next[0:0]$1675 + attribute \src "libresoc.v:48829.3-48830.43" + wire $0\core_fast1_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $0\core_fast2$next[2:0]$1676 + attribute \src "libresoc.v:48831.3-48832.37" + wire width 3 $0\core_fast2[2:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_fast2_ok$next[0:0]$1677 + attribute \src "libresoc.v:48833.3-48834.43" + wire $0\core_fast2_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $0\core_fasto1$next[2:0]$1678 + attribute \src "libresoc.v:48835.3-48836.39" + wire width 3 $0\core_fasto1[2:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_fasto1_ok$next[0:0]$1679 + attribute \src "libresoc.v:48837.3-48838.45" + wire $0\core_fasto1_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $0\core_fasto2$next[2:0]$1680 + attribute \src "libresoc.v:48839.3-48840.39" + wire width 3 $0\core_fasto2[2:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_fasto2_ok$next[0:0]$1681 + attribute \src "libresoc.v:48841.3-48842.45" + wire $0\core_fasto2_ok[0:0] + attribute \src "libresoc.v:50072.3-50103.6" + wire width 64 $0\core_msr$next[63:0]$1924 + attribute \src "libresoc.v:48775.3-48776.33" + wire width 64 $0\core_msr[63:0] + attribute \src "libresoc.v:50072.3-50103.6" + wire width 64 $0\core_pc$next[63:0]$1925 + attribute \src "libresoc.v:48773.3-48774.31" + wire width 64 $0\core_pc[63:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 5 $0\core_reg1$next[4:0]$1682 + attribute \src "libresoc.v:48803.3-48804.35" + wire width 5 $0\core_reg1[4:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_reg1_ok$next[0:0]$1683 + attribute \src "libresoc.v:48805.3-48806.41" + wire $0\core_reg1_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 5 $0\core_reg2$next[4:0]$1684 + attribute \src "libresoc.v:48807.3-48808.35" + wire width 5 $0\core_reg2[4:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_reg2_ok$next[0:0]$1685 + attribute \src "libresoc.v:48809.3-48810.41" + wire $0\core_reg2_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 5 $0\core_reg3$next[4:0]$1686 + attribute \src "libresoc.v:48811.3-48812.35" + wire width 5 $0\core_reg3[4:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_reg3_ok$next[0:0]$1687 + attribute \src "libresoc.v:48813.3-48814.41" + wire $0\core_reg3_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 5 $0\core_rego$next[4:0]$1688 + attribute \src "libresoc.v:48795.3-48796.35" + wire width 5 $0\core_rego[4:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_rego_ok$next[0:0]$1689 + attribute \src "libresoc.v:48797.3-48798.41" + wire $0\core_rego_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 10 $0\core_spr1$next[9:0]$1690 + attribute \src "libresoc.v:48819.3-48820.35" + wire width 10 $0\core_spr1[9:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_spr1_ok$next[0:0]$1691 + attribute \src "libresoc.v:48821.3-48822.41" + wire $0\core_spr1_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 10 $0\core_spro$next[9:0]$1692 + attribute \src "libresoc.v:48815.3-48816.35" + wire width 10 $0\core_spro[9:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_spro_ok$next[0:0]$1693 + attribute \src "libresoc.v:48817.3-48818.41" + wire $0\core_spro_ok[0:0] + attribute \src "libresoc.v:49994.3-50012.6" + wire $0\core_stopped_i[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $0\core_xer_in$next[2:0]$1694 + attribute \src "libresoc.v:48823.3-48824.39" + wire width 3 $0\core_xer_in[2:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $0\core_xer_out$next[0:0]$1695 + attribute \src "libresoc.v:48825.3-48826.41" + wire $0\core_xer_out[0:0] + attribute \src "libresoc.v:48903.3-48904.30" + wire $0\cu_st__rel_o_dly[0:0] + attribute \src "libresoc.v:49265.3-49273.6" + wire $0\d_cr_delay$next[0:0]$1598 + attribute \src "libresoc.v:48923.3-48924.37" + wire $0\d_cr_delay[0:0] + attribute \src "libresoc.v:49226.3-49234.6" + wire $0\d_reg_delay$next[0:0]$1592 + attribute \src "libresoc.v:48769.3-48770.39" + wire $0\d_reg_delay[0:0] + attribute \src "libresoc.v:49304.3-49312.6" + wire $0\d_xer_delay$next[0:0]$1604 + attribute \src "libresoc.v:48913.3-48914.39" + wire $0\d_xer_delay[0:0] + attribute \src "libresoc.v:49542.3-49562.6" + wire width 64 $0\data_i[63:0] + attribute \src "libresoc.v:50013.3-50031.6" + wire $0\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:49284.3-49293.6" + wire $0\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:49274.3-49283.6" + wire width 64 $0\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:49245.3-49254.6" + wire $0\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:49235.3-49244.6" + wire width 64 $0\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:49323.3-49332.6" + wire $0\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:49313.3-49322.6" + wire width 64 $0\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:49177.3-49185.6" + wire width 4 $0\dbg_dmi_addr_i$next[3:0]$1583 + attribute \src "libresoc.v:48921.3-48922.45" + wire width 4 $0\dbg_dmi_addr_i[3:0] + attribute \src "libresoc.v:49579.3-49587.6" + wire width 64 $0\dbg_dmi_din$next[63:0]$1637 + attribute \src "libresoc.v:48915.3-48916.39" + wire width 64 $0\dbg_dmi_din[63:0] + attribute \src "libresoc.v:49186.3-49194.6" + wire $0\dbg_dmi_req_i$next[0:0]$1586 + attribute \src "libresoc.v:48919.3-48920.43" + wire $0\dbg_dmi_req_i[0:0] + attribute \src "libresoc.v:49474.3-49482.6" + wire $0\dbg_dmi_we_i$next[0:0]$1626 + attribute \src "libresoc.v:48917.3-48918.41" + wire $0\dbg_dmi_we_i[0:0] + attribute \src "libresoc.v:49447.3-49462.6" + wire width 64 $0\dec2_cur_dec$next[63:0]$1621 + attribute \src "libresoc.v:48869.3-48870.41" + wire width 64 $0\dec2_cur_dec[63:0] + attribute \src "libresoc.v:49738.3-49746.6" + wire $0\dec2_cur_eint$next[0:0]$1875 + attribute \src "libresoc.v:48907.3-48908.43" + wire $0\dec2_cur_eint[0:0] + attribute \src "libresoc.v:50032.3-50052.6" + wire width 64 $0\dec2_cur_msr$next[63:0]$1916 + attribute \src "libresoc.v:48781.3-48782.41" + wire width 64 $0\dec2_cur_msr[63:0] + attribute \src "libresoc.v:49887.3-49907.6" + wire width 64 $0\dec2_cur_pc$next[63:0]$1893 + attribute \src "libresoc.v:48787.3-48788.39" + wire width 64 $0\dec2_cur_pc[63:0] + attribute \src "libresoc.v:50053.3-50071.6" + wire width 32 $0\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:49984.3-49993.6" + wire width 2 $0\delay$next[1:0]$1911 + attribute \src "libresoc.v:48905.3-48906.27" + wire width 2 $0\delay[1:0] + attribute \src "libresoc.v:49206.3-49215.6" + wire width 5 $0\dmi__addr[4:0] + attribute \src "libresoc.v:49216.3-49225.6" + wire $0\dmi__ren[0:0] + attribute \src "libresoc.v:49363.3-49390.6" + wire width 2 $0\fsm_state$115$next[1:0]$1611 + attribute \src "libresoc.v:48891.3-48892.45" + wire width 2 $0\fsm_state$115[1:0]$1565 + attribute \src "libresoc.v:48338.13-48338.35" + wire width 2 $0\fsm_state$115[1:0]$2018 + attribute \src "libresoc.v:49938.3-49983.6" + wire width 2 $0\fsm_state$next[1:0]$1904 + attribute \src "libresoc.v:48783.3-48784.35" + wire width 2 $0\fsm_state[1:0] + attribute \src "libresoc.v:49255.3-49264.6" + wire width 8 $0\full_rd2__ren[7:0] + attribute \src "libresoc.v:49294.3-49303.6" + wire width 3 $0\full_rd__ren[2:0] + attribute \src "libresoc.v:50104.3-50127.6" + wire width 32 $0\ilatch$next[31:0]$1939 + attribute \src "libresoc.v:48771.3-48772.29" + wire width 32 $0\ilatch[31:0] + attribute \src "libresoc.v:49821.3-49836.6" + wire width 48 $0\imem_a_pc_i[47:0] + attribute \src "libresoc.v:49837.3-49861.6" + wire $0\imem_a_valid_i[0:0] + attribute \src "libresoc.v:49862.3-49886.6" + wire $0\imem_f_valid_i[0:0] + attribute \src "libresoc.v:47126.7-47126.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:49402.3-49416.6" + wire width 3 $0\issue__addr$119[2:0]$1616 + attribute \src "libresoc.v:49333.3-49347.6" + wire width 3 $0\issue__addr[2:0] + attribute \src "libresoc.v:49432.3-49446.6" + wire width 64 $0\issue__data_i[63:0] + attribute \src "libresoc.v:49348.3-49362.6" + wire $0\issue__ren[0:0] + attribute \src "libresoc.v:49417.3-49431.6" + wire $0\issue__wen[0:0] + attribute \src "libresoc.v:49195.3-49205.6" + wire $0\issue_i[0:0] + attribute \src "libresoc.v:50128.3-50147.6" + wire $0\ivalid_i[0:0] + attribute \src "libresoc.v:49720.3-49728.6" + wire $0\jtag_dmi0_ack_o$next[0:0]$1869 + attribute \src "libresoc.v:48911.3-48912.47" + wire $0\jtag_dmi0_ack_o[0:0] + attribute \src "libresoc.v:49729.3-49737.6" + wire width 64 $0\jtag_dmi0_dout$next[63:0]$1872 + attribute \src "libresoc.v:48909.3-48910.45" + wire width 64 $0\jtag_dmi0_dout[63:0] + attribute \src "libresoc.v:49563.3-49578.6" + wire width 4 $0\msr__ren[3:0] + attribute \src "libresoc.v:49908.3-49937.6" + wire $0\msr_read$next[0:0]$1898 + attribute \src "libresoc.v:48785.3-48786.33" + wire $0\msr_read[0:0] + attribute \src "libresoc.v:49391.3-49401.6" + wire width 64 $0\new_dec[63:0] + attribute \src "libresoc.v:49463.3-49473.6" + wire width 64 $0\new_tb[63:0] + attribute \src "libresoc.v:49492.3-49507.6" + wire width 64 $0\pc[63:0] + attribute \src "libresoc.v:49588.3-49612.6" + wire $0\pc_changed$next[0:0]$1640 + attribute \src "libresoc.v:48899.3-48900.37" + wire $0\pc_changed[0:0] + attribute \src "libresoc.v:49483.3-49491.6" + wire $0\pc_ok_delay$next[0:0]$1629 + attribute \src "libresoc.v:48901.3-48902.39" + wire $0\pc_ok_delay[0:0] + attribute \src "libresoc.v:49747.3-49783.6" + wire width 32 $0\raw_insn_i$next[31:0]$1878 + attribute \src "libresoc.v:48791.3-48792.37" + wire width 32 $0\raw_insn_i[31:0] + attribute \src "libresoc.v:49521.3-49541.6" + wire width 4 $0\wen[3:0] + attribute \src "libresoc.v:49784.3-49820.6" + wire $1\bigendian_i$next[0:0]$1885 + attribute \src "libresoc.v:47256.7-47256.25" + wire $1\bigendian_i[0:0] + attribute \src "libresoc.v:49508.3-49520.6" + wire width 4 $1\cia__ren[3:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 8 $1\core_asmcode$next[7:0]$1696 + attribute \src "libresoc.v:47266.13-47266.33" + wire width 8 $1\core_asmcode[7:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 64 $1\core_core_cia$next[63:0]$1697 + attribute \src "libresoc.v:47272.14-47272.50" + wire width 64 $1\core_core_cia[63:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 8 $1\core_core_cr_rd$next[7:0]$1698 + attribute \src "libresoc.v:47276.13-47276.36" + wire width 8 $1\core_core_cr_rd[7:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_core_cr_rd_ok$next[0:0]$1699 + attribute \src "libresoc.v:47280.7-47280.32" + wire $1\core_core_cr_rd_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 8 $1\core_core_cr_wr$next[7:0]$1700 + attribute \src "libresoc.v:47284.13-47284.36" + wire width 8 $1\core_core_cr_wr[7:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_core_cr_wr_ok$next[0:0]$1701 + attribute \src "libresoc.v:47288.7-47288.32" + wire $1\core_core_cr_wr_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 12 $1\core_core_fn_unit$next[11:0]$1702 + attribute \src "libresoc.v:47305.14-47305.41" + wire width 12 $1\core_core_fn_unit[11:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 2 $1\core_core_input_carry$next[1:0]$1703 + attribute \src "libresoc.v:47313.13-47313.41" + wire width 2 $1\core_core_input_carry[1:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 32 $1\core_core_insn$next[31:0]$1704 + attribute \src "libresoc.v:47317.14-47317.36" + wire width 32 $1\core_core_insn[31:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 7 $1\core_core_insn_type$next[6:0]$1705 + attribute \src "libresoc.v:47395.13-47395.40" + wire width 7 $1\core_core_insn_type[6:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_core_is_32bit$next[0:0]$1706 + attribute \src "libresoc.v:47399.7-47399.32" + wire $1\core_core_is_32bit[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_core_lk$next[0:0]$1707 + attribute \src "libresoc.v:47403.7-47403.26" + wire $1\core_core_lk[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 64 $1\core_core_msr$next[63:0]$1708 + attribute \src "libresoc.v:47407.14-47407.50" + wire width 64 $1\core_core_msr[63:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_core_oe$next[0:0]$1709 + attribute \src "libresoc.v:47411.7-47411.26" + wire $1\core_core_oe[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_core_oe_ok$next[0:0]$1710 + attribute \src "libresoc.v:47415.7-47415.29" + wire $1\core_core_oe_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_core_rc$next[0:0]$1711 + attribute \src "libresoc.v:47419.7-47419.26" + wire $1\core_core_rc[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_core_rc_ok$next[0:0]$1712 + attribute \src "libresoc.v:47423.7-47423.29" + wire $1\core_core_rc_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 13 $1\core_core_trapaddr$next[12:0]$1713 + attribute \src "libresoc.v:47427.14-47427.43" + wire width 13 $1\core_core_trapaddr[12:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 7 $1\core_core_traptype$next[6:0]$1714 + attribute \src "libresoc.v:47431.13-47431.39" + wire width 7 $1\core_core_traptype[6:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $1\core_cr_in1$next[2:0]$1715 + attribute \src "libresoc.v:47435.13-47435.31" + wire width 3 $1\core_cr_in1[2:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_cr_in1_ok$next[0:0]$1716 + attribute \src "libresoc.v:47439.7-47439.28" + wire $1\core_cr_in1_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $1\core_cr_in2$39$next[2:0]$1717 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $1\core_cr_in2$next[2:0]$1718 + attribute \src "libresoc.v:47443.13-47443.31" + wire width 3 $1\core_cr_in2[2:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_cr_in2_ok$40$next[0:0]$1719 + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_cr_in2_ok$next[0:0]$1720 + attribute \src "libresoc.v:47451.7-47451.28" + wire $1\core_cr_in2_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $1\core_cr_out$next[2:0]$1721 + attribute \src "libresoc.v:47459.13-47459.31" + wire width 3 $1\core_cr_out[2:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_cr_out_ok$next[0:0]$1722 + attribute \src "libresoc.v:47463.7-47463.28" + wire $1\core_cr_out_ok[0:0] + attribute \src "libresoc.v:50072.3-50103.6" + wire width 64 $1\core_dec$next[63:0]$1926 + attribute \src "libresoc.v:47467.14-47467.45" + wire width 64 $1\core_dec[63:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 5 $1\core_ea$next[4:0]$1723 + attribute \src "libresoc.v:47471.13-47471.28" + wire width 5 $1\core_ea[4:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_ea_ok$next[0:0]$1724 + attribute \src "libresoc.v:47475.7-47475.24" + wire $1\core_ea_ok[0:0] + attribute \src "libresoc.v:50072.3-50103.6" + wire $1\core_eint$next[0:0]$1927 + attribute \src "libresoc.v:47479.7-47479.23" + wire $1\core_eint[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $1\core_fast1$next[2:0]$1725 + attribute \src "libresoc.v:47483.13-47483.30" + wire width 3 $1\core_fast1[2:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_fast1_ok$next[0:0]$1726 + attribute \src "libresoc.v:47487.7-47487.27" + wire $1\core_fast1_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $1\core_fast2$next[2:0]$1727 + attribute \src "libresoc.v:47491.13-47491.30" + wire width 3 $1\core_fast2[2:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_fast2_ok$next[0:0]$1728 + attribute \src "libresoc.v:47495.7-47495.27" + wire $1\core_fast2_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $1\core_fasto1$next[2:0]$1729 + attribute \src "libresoc.v:47499.13-47499.31" + wire width 3 $1\core_fasto1[2:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_fasto1_ok$next[0:0]$1730 + attribute \src "libresoc.v:47503.7-47503.28" + wire $1\core_fasto1_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $1\core_fasto2$next[2:0]$1731 + attribute \src "libresoc.v:47507.13-47507.31" + wire width 3 $1\core_fasto2[2:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_fasto2_ok$next[0:0]$1732 + attribute \src "libresoc.v:47511.7-47511.28" + wire $1\core_fasto2_ok[0:0] + attribute \src "libresoc.v:50072.3-50103.6" + wire width 64 $1\core_msr$next[63:0]$1928 + attribute \src "libresoc.v:47515.14-47515.45" + wire width 64 $1\core_msr[63:0] + attribute \src "libresoc.v:50072.3-50103.6" + wire width 64 $1\core_pc$next[63:0]$1929 + attribute \src "libresoc.v:47519.14-47519.44" + wire width 64 $1\core_pc[63:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 5 $1\core_reg1$next[4:0]$1733 + attribute \src "libresoc.v:47523.13-47523.30" + wire width 5 $1\core_reg1[4:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_reg1_ok$next[0:0]$1734 + attribute \src "libresoc.v:47527.7-47527.26" + wire $1\core_reg1_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 5 $1\core_reg2$next[4:0]$1735 + attribute \src "libresoc.v:47531.13-47531.30" + wire width 5 $1\core_reg2[4:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_reg2_ok$next[0:0]$1736 + attribute \src "libresoc.v:47535.7-47535.26" + wire $1\core_reg2_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 5 $1\core_reg3$next[4:0]$1737 + attribute \src "libresoc.v:47539.13-47539.30" + wire width 5 $1\core_reg3[4:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_reg3_ok$next[0:0]$1738 + attribute \src "libresoc.v:47543.7-47543.26" + wire $1\core_reg3_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 5 $1\core_rego$next[4:0]$1739 + attribute \src "libresoc.v:47547.13-47547.30" + wire width 5 $1\core_rego[4:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_rego_ok$next[0:0]$1740 + attribute \src "libresoc.v:47551.7-47551.26" + wire $1\core_rego_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 10 $1\core_spr1$next[9:0]$1741 + attribute \src "libresoc.v:47668.13-47668.32" + wire width 10 $1\core_spr1[9:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_spr1_ok$next[0:0]$1742 + attribute \src "libresoc.v:47672.7-47672.26" + wire $1\core_spr1_ok[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 10 $1\core_spro$next[9:0]$1743 + attribute \src "libresoc.v:47787.13-47787.32" + wire width 10 $1\core_spro[9:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_spro_ok$next[0:0]$1744 + attribute \src "libresoc.v:47791.7-47791.26" + wire $1\core_spro_ok[0:0] + attribute \src "libresoc.v:49994.3-50012.6" + wire $1\core_stopped_i[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $1\core_xer_in$next[2:0]$1745 + attribute \src "libresoc.v:47799.13-47799.31" + wire width 3 $1\core_xer_in[2:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire $1\core_xer_out$next[0:0]$1746 + attribute \src "libresoc.v:47803.7-47803.26" + wire $1\core_xer_out[0:0] + attribute \src "libresoc.v:47819.7-47819.30" + wire $1\cu_st__rel_o_dly[0:0] + attribute \src "libresoc.v:49265.3-49273.6" + wire $1\d_cr_delay$next[0:0]$1599 + attribute \src "libresoc.v:47825.7-47825.24" + wire $1\d_cr_delay[0:0] + attribute \src "libresoc.v:49226.3-49234.6" + wire $1\d_reg_delay$next[0:0]$1593 + attribute \src "libresoc.v:47829.7-47829.25" + wire $1\d_reg_delay[0:0] + attribute \src "libresoc.v:49304.3-49312.6" + wire $1\d_xer_delay$next[0:0]$1605 + attribute \src "libresoc.v:47833.7-47833.25" + wire $1\d_xer_delay[0:0] + attribute \src "libresoc.v:49542.3-49562.6" + wire width 64 $1\data_i[63:0] + attribute \src "libresoc.v:50013.3-50031.6" + wire $1\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:49284.3-49293.6" + wire $1\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:49274.3-49283.6" + wire width 64 $1\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:49245.3-49254.6" + wire $1\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:49235.3-49244.6" + wire width 64 $1\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:49323.3-49332.6" + wire $1\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:49313.3-49322.6" + wire width 64 $1\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:49177.3-49185.6" + wire width 4 $1\dbg_dmi_addr_i$next[3:0]$1584 + attribute \src "libresoc.v:47871.13-47871.34" + wire width 4 $1\dbg_dmi_addr_i[3:0] + attribute \src "libresoc.v:49579.3-49587.6" + wire width 64 $1\dbg_dmi_din$next[63:0]$1638 + attribute \src "libresoc.v:47875.14-47875.48" + wire width 64 $1\dbg_dmi_din[63:0] + attribute \src "libresoc.v:49186.3-49194.6" + wire $1\dbg_dmi_req_i$next[0:0]$1587 + attribute \src "libresoc.v:47881.7-47881.27" + wire $1\dbg_dmi_req_i[0:0] + attribute \src "libresoc.v:49474.3-49482.6" + wire $1\dbg_dmi_we_i$next[0:0]$1627 + attribute \src "libresoc.v:47885.7-47885.26" + wire $1\dbg_dmi_we_i[0:0] + attribute \src "libresoc.v:49447.3-49462.6" + wire width 64 $1\dec2_cur_dec$next[63:0]$1622 + attribute \src "libresoc.v:47921.14-47921.49" + wire width 64 $1\dec2_cur_dec[63:0] + attribute \src "libresoc.v:49738.3-49746.6" + wire $1\dec2_cur_eint$next[0:0]$1876 + attribute \src "libresoc.v:47925.7-47925.27" + wire $1\dec2_cur_eint[0:0] + attribute \src "libresoc.v:50032.3-50052.6" + wire width 64 $1\dec2_cur_msr$next[63:0]$1917 + attribute \src "libresoc.v:47929.14-47929.49" + wire width 64 $1\dec2_cur_msr[63:0] + attribute \src "libresoc.v:49887.3-49907.6" + wire width 64 $1\dec2_cur_pc$next[63:0]$1894 + attribute \src "libresoc.v:47933.14-47933.48" + wire width 64 $1\dec2_cur_pc[63:0] + attribute \src "libresoc.v:50053.3-50071.6" + wire width 32 $1\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:49984.3-49993.6" + wire width 2 $1\delay$next[1:0]$1912 + attribute \src "libresoc.v:48326.13-48326.25" + wire width 2 $1\delay[1:0] + attribute \src "libresoc.v:49206.3-49215.6" + wire width 5 $1\dmi__addr[4:0] + attribute \src "libresoc.v:49216.3-49225.6" + wire $1\dmi__ren[0:0] + attribute \src "libresoc.v:49363.3-49390.6" + wire width 2 $1\fsm_state$115$next[1:0]$1612 + attribute \src "libresoc.v:49938.3-49983.6" + wire width 2 $1\fsm_state$next[1:0]$1905 + attribute \src "libresoc.v:48336.13-48336.29" + wire width 2 $1\fsm_state[1:0] + attribute \src "libresoc.v:49255.3-49264.6" + wire width 8 $1\full_rd2__ren[7:0] + attribute \src "libresoc.v:49294.3-49303.6" + wire width 3 $1\full_rd__ren[2:0] + attribute \src "libresoc.v:50104.3-50127.6" + wire width 32 $1\ilatch$next[31:0]$1940 + attribute \src "libresoc.v:48588.14-48588.28" + wire width 32 $1\ilatch[31:0] + attribute \src "libresoc.v:49821.3-49836.6" + wire width 48 $1\imem_a_pc_i[47:0] + attribute \src "libresoc.v:49837.3-49861.6" + wire $1\imem_a_valid_i[0:0] + attribute \src "libresoc.v:49862.3-49886.6" + wire $1\imem_f_valid_i[0:0] + attribute \src "libresoc.v:49402.3-49416.6" + wire width 3 $1\issue__addr$119[2:0]$1617 + attribute \src "libresoc.v:49333.3-49347.6" + wire width 3 $1\issue__addr[2:0] + attribute \src "libresoc.v:49432.3-49446.6" + wire width 64 $1\issue__data_i[63:0] + attribute \src "libresoc.v:49348.3-49362.6" + wire $1\issue__ren[0:0] + attribute \src "libresoc.v:49417.3-49431.6" + wire $1\issue__wen[0:0] + attribute \src "libresoc.v:49195.3-49205.6" + wire $1\issue_i[0:0] + attribute \src "libresoc.v:50128.3-50147.6" + wire $1\ivalid_i[0:0] + attribute \src "libresoc.v:49720.3-49728.6" + wire $1\jtag_dmi0_ack_o$next[0:0]$1870 + attribute \src "libresoc.v:48624.7-48624.29" + wire $1\jtag_dmi0_ack_o[0:0] + attribute \src "libresoc.v:49729.3-49737.6" + wire width 64 $1\jtag_dmi0_dout$next[63:0]$1873 + attribute \src "libresoc.v:48632.14-48632.51" + wire width 64 $1\jtag_dmi0_dout[63:0] + attribute \src "libresoc.v:49563.3-49578.6" + wire width 4 $1\msr__ren[3:0] + attribute \src "libresoc.v:49908.3-49937.6" + wire $1\msr_read$next[0:0]$1899 + attribute \src "libresoc.v:48660.7-48660.22" + wire $1\msr_read[0:0] + attribute \src "libresoc.v:49391.3-49401.6" + wire width 64 $1\new_dec[63:0] + attribute \src "libresoc.v:49463.3-49473.6" + wire width 64 $1\new_tb[63:0] + attribute \src "libresoc.v:49492.3-49507.6" + wire width 64 $1\pc[63:0] + attribute \src "libresoc.v:49588.3-49612.6" + wire $1\pc_changed$next[0:0]$1641 + attribute \src "libresoc.v:48672.7-48672.24" + wire $1\pc_changed[0:0] + attribute \src "libresoc.v:49483.3-49491.6" + wire $1\pc_ok_delay$next[0:0]$1630 + attribute \src "libresoc.v:48682.7-48682.25" + wire $1\pc_ok_delay[0:0] + attribute \src "libresoc.v:49747.3-49783.6" + wire width 32 $1\raw_insn_i$next[31:0]$1879 + attribute \src "libresoc.v:48688.14-48688.32" + wire width 32 $1\raw_insn_i[31:0] + attribute \src "libresoc.v:49521.3-49541.6" + wire width 4 $1\wen[3:0] + attribute \src "libresoc.v:49784.3-49820.6" + wire $2\bigendian_i$next[0:0]$1886 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 8 $2\core_asmcode$next[7:0]$1747 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 64 $2\core_core_cia$next[63:0]$1748 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 8 $2\core_core_cr_rd$next[7:0]$1749 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_core_cr_rd_ok$next[0:0]$1750 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 8 $2\core_core_cr_wr$next[7:0]$1751 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_core_cr_wr_ok$next[0:0]$1752 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 12 $2\core_core_fn_unit$next[11:0]$1753 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 2 $2\core_core_input_carry$next[1:0]$1754 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 32 $2\core_core_insn$next[31:0]$1755 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 7 $2\core_core_insn_type$next[6:0]$1756 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_core_is_32bit$next[0:0]$1757 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_core_lk$next[0:0]$1758 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 64 $2\core_core_msr$next[63:0]$1759 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_core_oe$next[0:0]$1760 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_core_oe_ok$next[0:0]$1761 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_core_rc$next[0:0]$1762 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_core_rc_ok$next[0:0]$1763 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 13 $2\core_core_trapaddr$next[12:0]$1764 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 7 $2\core_core_traptype$next[6:0]$1765 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $2\core_cr_in1$next[2:0]$1766 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_cr_in1_ok$next[0:0]$1767 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $2\core_cr_in2$39$next[2:0]$1768 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $2\core_cr_in2$next[2:0]$1769 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_cr_in2_ok$40$next[0:0]$1770 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_cr_in2_ok$next[0:0]$1771 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $2\core_cr_out$next[2:0]$1772 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_cr_out_ok$next[0:0]$1773 + attribute \src "libresoc.v:50072.3-50103.6" + wire width 64 $2\core_dec$next[63:0]$1930 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 5 $2\core_ea$next[4:0]$1774 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_ea_ok$next[0:0]$1775 + attribute \src "libresoc.v:50072.3-50103.6" + wire $2\core_eint$next[0:0]$1931 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $2\core_fast1$next[2:0]$1776 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_fast1_ok$next[0:0]$1777 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $2\core_fast2$next[2:0]$1778 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_fast2_ok$next[0:0]$1779 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $2\core_fasto1$next[2:0]$1780 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_fasto1_ok$next[0:0]$1781 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $2\core_fasto2$next[2:0]$1782 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_fasto2_ok$next[0:0]$1783 + attribute \src "libresoc.v:50072.3-50103.6" + wire width 64 $2\core_msr$next[63:0]$1932 + attribute \src "libresoc.v:50072.3-50103.6" + wire width 64 $2\core_pc$next[63:0]$1933 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 5 $2\core_reg1$next[4:0]$1784 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_reg1_ok$next[0:0]$1785 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 5 $2\core_reg2$next[4:0]$1786 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_reg2_ok$next[0:0]$1787 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 5 $2\core_reg3$next[4:0]$1788 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_reg3_ok$next[0:0]$1789 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 5 $2\core_rego$next[4:0]$1790 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_rego_ok$next[0:0]$1791 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 10 $2\core_spr1$next[9:0]$1792 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_spr1_ok$next[0:0]$1793 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 10 $2\core_spro$next[9:0]$1794 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_spro_ok$next[0:0]$1795 + attribute \src "libresoc.v:49994.3-50012.6" + wire $2\core_stopped_i[0:0] + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $2\core_xer_in$next[2:0]$1796 + attribute \src "libresoc.v:49613.3-49719.6" + wire $2\core_xer_out$next[0:0]$1797 + attribute \src "libresoc.v:49542.3-49562.6" + wire width 64 $2\data_i[63:0] + attribute \src "libresoc.v:50013.3-50031.6" + wire $2\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:49447.3-49462.6" + wire width 64 $2\dec2_cur_dec$next[63:0]$1623 + attribute \src "libresoc.v:50032.3-50052.6" + wire width 64 $2\dec2_cur_msr$next[63:0]$1918 + attribute \src "libresoc.v:49887.3-49907.6" + wire width 64 $2\dec2_cur_pc$next[63:0]$1895 + attribute \src "libresoc.v:50053.3-50071.6" + wire width 32 $2\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:49363.3-49390.6" + wire width 2 $2\fsm_state$115$next[1:0]$1613 + attribute \src "libresoc.v:49938.3-49983.6" + wire width 2 $2\fsm_state$next[1:0]$1906 + attribute \src "libresoc.v:50104.3-50127.6" + wire width 32 $2\ilatch$next[31:0]$1941 + attribute \src "libresoc.v:49821.3-49836.6" + wire width 48 $2\imem_a_pc_i[47:0] + attribute \src "libresoc.v:49837.3-49861.6" + wire $2\imem_a_valid_i[0:0] + attribute \src "libresoc.v:49862.3-49886.6" + wire $2\imem_f_valid_i[0:0] + attribute \src "libresoc.v:50128.3-50147.6" + wire $2\ivalid_i[0:0] + attribute \src "libresoc.v:49563.3-49578.6" + wire width 4 $2\msr__ren[3:0] + attribute \src "libresoc.v:49908.3-49937.6" + wire $2\msr_read$next[0:0]$1900 + attribute \src "libresoc.v:49492.3-49507.6" + wire width 64 $2\pc[63:0] + attribute \src "libresoc.v:49588.3-49612.6" + wire $2\pc_changed$next[0:0]$1642 + attribute \src "libresoc.v:49747.3-49783.6" + wire width 32 $2\raw_insn_i$next[31:0]$1880 + attribute \src "libresoc.v:49521.3-49541.6" + wire width 4 $2\wen[3:0] + attribute \src "libresoc.v:49784.3-49820.6" + wire $3\bigendian_i$next[0:0]$1887 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 8 $3\core_asmcode$next[7:0]$1798 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 64 $3\core_core_cia$next[63:0]$1799 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 8 $3\core_core_cr_rd$next[7:0]$1800 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_core_cr_rd_ok$next[0:0]$1801 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 8 $3\core_core_cr_wr$next[7:0]$1802 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_core_cr_wr_ok$next[0:0]$1803 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 12 $3\core_core_fn_unit$next[11:0]$1804 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 2 $3\core_core_input_carry$next[1:0]$1805 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 32 $3\core_core_insn$next[31:0]$1806 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 7 $3\core_core_insn_type$next[6:0]$1807 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_core_is_32bit$next[0:0]$1808 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_core_lk$next[0:0]$1809 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 64 $3\core_core_msr$next[63:0]$1810 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_core_oe$next[0:0]$1811 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_core_oe_ok$next[0:0]$1812 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_core_rc$next[0:0]$1813 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_core_rc_ok$next[0:0]$1814 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 13 $3\core_core_trapaddr$next[12:0]$1815 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 7 $3\core_core_traptype$next[6:0]$1816 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $3\core_cr_in1$next[2:0]$1817 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_cr_in1_ok$next[0:0]$1818 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $3\core_cr_in2$39$next[2:0]$1819 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $3\core_cr_in2$next[2:0]$1820 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_cr_in2_ok$40$next[0:0]$1821 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_cr_in2_ok$next[0:0]$1822 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $3\core_cr_out$next[2:0]$1823 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_cr_out_ok$next[0:0]$1824 + attribute \src "libresoc.v:50072.3-50103.6" + wire width 64 $3\core_dec$next[63:0]$1934 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 5 $3\core_ea$next[4:0]$1825 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_ea_ok$next[0:0]$1826 + attribute \src "libresoc.v:50072.3-50103.6" + wire $3\core_eint$next[0:0]$1935 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $3\core_fast1$next[2:0]$1827 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_fast1_ok$next[0:0]$1828 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $3\core_fast2$next[2:0]$1829 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_fast2_ok$next[0:0]$1830 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $3\core_fasto1$next[2:0]$1831 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_fasto1_ok$next[0:0]$1832 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $3\core_fasto2$next[2:0]$1833 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_fasto2_ok$next[0:0]$1834 + attribute \src "libresoc.v:50072.3-50103.6" + wire width 64 $3\core_msr$next[63:0]$1936 + attribute \src "libresoc.v:50072.3-50103.6" + wire width 64 $3\core_pc$next[63:0]$1937 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 5 $3\core_reg1$next[4:0]$1835 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_reg1_ok$next[0:0]$1836 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 5 $3\core_reg2$next[4:0]$1837 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_reg2_ok$next[0:0]$1838 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 5 $3\core_reg3$next[4:0]$1839 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_reg3_ok$next[0:0]$1840 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 5 $3\core_rego$next[4:0]$1841 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_rego_ok$next[0:0]$1842 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 10 $3\core_spr1$next[9:0]$1843 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_spr1_ok$next[0:0]$1844 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 10 $3\core_spro$next[9:0]$1845 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_spro_ok$next[0:0]$1846 + attribute \src "libresoc.v:49613.3-49719.6" + wire width 3 $3\core_xer_in$next[2:0]$1847 + attribute \src "libresoc.v:49613.3-49719.6" + wire $3\core_xer_out$next[0:0]$1848 + attribute \src "libresoc.v:49542.3-49562.6" + wire width 64 $3\data_i[63:0] + attribute \src "libresoc.v:50032.3-50052.6" + wire width 64 $3\dec2_cur_msr$next[63:0]$1919 + attribute \src "libresoc.v:49887.3-49907.6" + wire width 64 $3\dec2_cur_pc$next[63:0]$1896 + attribute \src "libresoc.v:49938.3-49983.6" + wire width 2 $3\fsm_state$next[1:0]$1907 + attribute \src "libresoc.v:50104.3-50127.6" + wire width 32 $3\ilatch$next[31:0]$1942 + attribute \src "libresoc.v:49837.3-49861.6" + wire $3\imem_a_valid_i[0:0] + attribute \src "libresoc.v:49862.3-49886.6" + wire $3\imem_f_valid_i[0:0] + attribute \src "libresoc.v:49908.3-49937.6" + wire $3\msr_read$next[0:0]$1901 + attribute \src "libresoc.v:49588.3-49612.6" + wire $3\pc_changed$next[0:0]$1643 + attribute \src "libresoc.v:49747.3-49783.6" + wire width 32 $3\raw_insn_i$next[31:0]$1881 + attribute \src "libresoc.v:49521.3-49541.6" + wire width 4 $3\wen[3:0] + attribute \src "libresoc.v:49784.3-49820.6" + wire $4\bigendian_i$next[0:0]$1888 + attribute \src "libresoc.v:49613.3-49719.6" + wire $4\core_core_cr_rd_ok$next[0:0]$1849 + attribute \src "libresoc.v:49613.3-49719.6" + wire $4\core_core_cr_wr_ok$next[0:0]$1850 + attribute \src "libresoc.v:49613.3-49719.6" + wire $4\core_core_oe_ok$next[0:0]$1851 + attribute \src "libresoc.v:49613.3-49719.6" + wire $4\core_core_rc_ok$next[0:0]$1852 + attribute \src "libresoc.v:49613.3-49719.6" + wire $4\core_cr_in1_ok$next[0:0]$1853 + attribute \src "libresoc.v:49613.3-49719.6" + wire $4\core_cr_in2_ok$40$next[0:0]$1854 + attribute \src "libresoc.v:49613.3-49719.6" + wire $4\core_cr_in2_ok$next[0:0]$1855 + attribute \src "libresoc.v:49613.3-49719.6" + wire $4\core_cr_out_ok$next[0:0]$1856 + attribute \src "libresoc.v:49613.3-49719.6" + wire $4\core_ea_ok$next[0:0]$1857 + attribute \src "libresoc.v:49613.3-49719.6" + wire $4\core_fast1_ok$next[0:0]$1858 + attribute \src "libresoc.v:49613.3-49719.6" + wire $4\core_fast2_ok$next[0:0]$1859 + attribute \src "libresoc.v:49613.3-49719.6" + wire $4\core_fasto1_ok$next[0:0]$1860 + attribute \src "libresoc.v:49613.3-49719.6" + wire $4\core_fasto2_ok$next[0:0]$1861 + attribute \src "libresoc.v:49613.3-49719.6" + wire $4\core_reg1_ok$next[0:0]$1862 + attribute \src "libresoc.v:49613.3-49719.6" + wire $4\core_reg2_ok$next[0:0]$1863 + attribute \src "libresoc.v:49613.3-49719.6" + wire $4\core_reg3_ok$next[0:0]$1864 + attribute \src "libresoc.v:49613.3-49719.6" + wire $4\core_rego_ok$next[0:0]$1865 + attribute \src "libresoc.v:49613.3-49719.6" + wire $4\core_spr1_ok$next[0:0]$1866 + attribute \src "libresoc.v:49613.3-49719.6" + wire $4\core_spro_ok$next[0:0]$1867 + attribute \src "libresoc.v:49938.3-49983.6" + wire width 2 $4\fsm_state$next[1:0]$1908 + attribute \src "libresoc.v:49908.3-49937.6" + wire $4\msr_read$next[0:0]$1902 + attribute \src "libresoc.v:49747.3-49783.6" + wire width 32 $4\raw_insn_i$next[31:0]$1882 + attribute \src "libresoc.v:49938.3-49983.6" + wire width 2 $5\fsm_state$next[1:0]$1909 + attribute \src "libresoc.v:48723.19-48723.110" + wire width 65 $add$libresoc.v:48723$1455_Y + attribute \src "libresoc.v:48726.18-48726.107" + wire width 65 $add$libresoc.v:48726$1458_Y + attribute \src "libresoc.v:48725.18-48725.104" + wire $and$libresoc.v:48725$1457_Y + attribute \src "libresoc.v:48734.18-48734.101" + wire $and$libresoc.v:48734$1466_Y + attribute \src "libresoc.v:48735.18-48735.109" + wire width 4 $and$libresoc.v:48735$1467_Y + attribute \src "libresoc.v:48743.18-48743.101" + wire $and$libresoc.v:48743$1475_Y + attribute \src "libresoc.v:48746.18-48746.101" + wire $and$libresoc.v:48746$1478_Y + attribute \src "libresoc.v:48749.18-48749.101" + wire $and$libresoc.v:48749$1481_Y + attribute \src "libresoc.v:48753.18-48753.101" + wire $and$libresoc.v:48753$1485_Y + attribute \src "libresoc.v:48756.18-48756.101" + wire $and$libresoc.v:48756$1488_Y + attribute \src "libresoc.v:48760.18-48760.101" + wire $and$libresoc.v:48760$1492_Y + attribute \src "libresoc.v:48765.18-48765.101" + wire $and$libresoc.v:48765$1497_Y + attribute \src "libresoc.v:48768.18-48768.101" + wire $and$libresoc.v:48768$1500_Y + attribute \src "libresoc.v:48720.19-48720.109" + wire width 64 $extend$libresoc.v:48720$1450_Y + attribute \src "libresoc.v:48721.19-48721.108" + wire width 64 $extend$libresoc.v:48721$1452_Y + attribute \src "libresoc.v:48714.19-48714.111" + wire width 7 $mul$libresoc.v:48714$1444_Y + attribute \src "libresoc.v:48716.19-48716.111" + wire width 7 $mul$libresoc.v:48716$1446_Y + attribute \src "libresoc.v:48718.18-48718.101" + wire $ne$libresoc.v:48718$1448_Y + attribute \src "libresoc.v:48719.19-48719.118" + wire $ne$libresoc.v:48719$1449_Y + attribute \src "libresoc.v:48737.17-48737.101" + wire $ne$libresoc.v:48737$1469_Y + attribute \src "libresoc.v:48713.18-48713.99" + wire $not$libresoc.v:48713$1443_Y + attribute \src "libresoc.v:48724.18-48724.103" + wire $not$libresoc.v:48724$1456_Y + attribute \src "libresoc.v:48727.18-48727.98" + wire $not$libresoc.v:48727$1459_Y + attribute \src "libresoc.v:48728.18-48728.101" + wire $not$libresoc.v:48728$1460_Y + attribute \src "libresoc.v:48729.18-48729.101" + wire $not$libresoc.v:48729$1461_Y + attribute \src "libresoc.v:48730.18-48730.101" + wire $not$libresoc.v:48730$1462_Y + attribute \src "libresoc.v:48731.18-48731.101" + wire $not$libresoc.v:48731$1463_Y + attribute \src "libresoc.v:48732.18-48732.106" + wire $not$libresoc.v:48732$1464_Y + attribute \src "libresoc.v:48733.18-48733.103" + wire $not$libresoc.v:48733$1465_Y + attribute \src "libresoc.v:48738.18-48738.101" + wire $not$libresoc.v:48738$1470_Y + attribute \src "libresoc.v:48739.18-48739.101" + wire $not$libresoc.v:48739$1471_Y + attribute \src "libresoc.v:48740.18-48740.101" + wire $not$libresoc.v:48740$1472_Y + attribute \src "libresoc.v:48741.18-48741.106" + wire $not$libresoc.v:48741$1473_Y + attribute \src "libresoc.v:48742.18-48742.103" + wire $not$libresoc.v:48742$1474_Y + attribute \src "libresoc.v:48744.18-48744.106" + wire $not$libresoc.v:48744$1476_Y + attribute \src "libresoc.v:48745.18-48745.103" + wire $not$libresoc.v:48745$1477_Y + attribute \src "libresoc.v:48747.18-48747.106" + wire $not$libresoc.v:48747$1479_Y + attribute \src "libresoc.v:48748.18-48748.103" + wire $not$libresoc.v:48748$1480_Y + attribute \src "libresoc.v:48750.18-48750.106" + wire $not$libresoc.v:48750$1482_Y + attribute \src "libresoc.v:48751.18-48751.103" + wire $not$libresoc.v:48751$1483_Y + attribute \src "libresoc.v:48754.18-48754.106" + wire $not$libresoc.v:48754$1486_Y + attribute \src "libresoc.v:48755.18-48755.103" + wire $not$libresoc.v:48755$1487_Y + attribute \src "libresoc.v:48757.18-48757.99" + wire $not$libresoc.v:48757$1489_Y + attribute \src "libresoc.v:48758.18-48758.106" + wire $not$libresoc.v:48758$1490_Y + attribute \src "libresoc.v:48759.18-48759.103" + wire $not$libresoc.v:48759$1491_Y + attribute \src "libresoc.v:48761.18-48761.101" + wire $not$libresoc.v:48761$1493_Y + attribute \src "libresoc.v:48762.18-48762.106" + wire $not$libresoc.v:48762$1494_Y + attribute \src "libresoc.v:48764.18-48764.103" + wire $not$libresoc.v:48764$1496_Y + attribute \src "libresoc.v:48766.18-48766.106" + wire $not$libresoc.v:48766$1498_Y + attribute \src "libresoc.v:48767.18-48767.103" + wire $not$libresoc.v:48767$1499_Y + attribute \src "libresoc.v:48763.17-48763.109" + wire $or$libresoc.v:48763$1495_Y + attribute \src "libresoc.v:48720.19-48720.109" + wire width 64 $pos$libresoc.v:48720$1451_Y + attribute \src "libresoc.v:48721.19-48721.108" + wire width 64 $pos$libresoc.v:48721$1453_Y + attribute \src "libresoc.v:48736.18-48736.91" + wire $reduce_or$libresoc.v:48736$1468_Y + attribute \src "libresoc.v:48715.19-48715.42" + wire width 64 $shr$libresoc.v:48715$1445_Y + attribute \src "libresoc.v:48717.19-48717.42" + wire width 64 $shr$libresoc.v:48717$1447_Y + attribute \src "libresoc.v:48722.19-48722.110" + wire width 65 $sub$libresoc.v:48722$1454_Y + attribute \src "libresoc.v:48752.17-48752.100" + wire width 3 $sub$libresoc.v:48752$1484_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:163" + wire \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:270" + wire width 32 \$101 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + wire width 7 \$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:270" + wire width 32 \$105 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + wire width 7 \$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \$111 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" + wire width 65 \$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" + wire width 65 \$117 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:391" + wire width 65 \$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:391" + wire width 65 \$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:183" + wire width 65 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:183" + wire width 65 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:188" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:158" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + wire width 4 \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:159" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:159" + wire width 3 \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:257" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:163" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:257" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 122 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 62 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire output 113 \TAP_bus__tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 123 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" + wire \bigendian_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" + wire \bigendian_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:92" + wire output 140 \busy_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \cia__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cia__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + wire width 8 \core_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + wire width 8 \core_asmcode$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:91" + wire input 1 \core_bigendian_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \core_core_cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \core_core_cia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \core_core_cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \core_core_cr_rd$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_cr_rd_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_cr_rd_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \core_core_cr_wr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \core_core_cr_wr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_cr_wr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_cr_wr_ok$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 12 \core_core_fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 12 \core_core_fn_unit$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 2 \core_core_input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 2 \core_core_input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 \core_core_insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 \core_core_insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 \core_core_insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire \core_core_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire \core_core_is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire \core_core_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire \core_core_lk$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 \core_core_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 \core_core_msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_oe_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_rc_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 13 \core_core_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 13 \core_core_trapaddr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 7 \core_core_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 7 \core_core_traptype$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_cr_in1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_cr_in1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_cr_in1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_cr_in2$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_cr_in2$39$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_cr_in2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_cr_in2_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_cr_in2_ok$40$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_cr_in2_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_cr_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_cr_out_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_cr_out_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 \core_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 \core_dec$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_ea$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_ea_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + wire \core_eint + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + wire \core_eint$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_fast1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_fast1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_fast2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_fast2_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_fasto1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_fasto1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_fasto2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_fasto2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_fasto2_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \core_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \core_msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 \core_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 \core_pc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_reg1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_reg1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_reg2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_reg2_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_reg3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_reg3_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_rego$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_rego_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_rego_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" + wire \core_reset_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \core_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \core_spr1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_spr1_ok$next + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \core_spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \core_spro$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_spro_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" + wire \core_stopped_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:104" + wire \core_terminate_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 \core_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 \core_xer_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + wire \core_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + wire \core_xer_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" + wire \corebusy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:154" + wire \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire \cu_ad__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire \cu_ad__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire \cu_st__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire \cu_st__rel_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \cu_st__rel_o_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \cu_st__rel_o_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \cu_st__rel_o_rise + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" + wire \d_cr_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" + wire \d_cr_delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + wire \d_reg_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + wire \d_reg_delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335" + wire \d_xer_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335" + wire \d_xer_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \dbg_core_dbg_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 \dbg_core_dbg_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" + wire \dbg_core_rst_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:97" + wire \dbg_core_stop_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" + wire \dbg_core_stopped_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire \dbg_d_cr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 \dbg_d_cr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire \dbg_d_cr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire \dbg_d_gpr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" + wire width 7 \dbg_d_gpr_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 \dbg_d_gpr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire \dbg_d_gpr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire \dbg_d_xer_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 \dbg_d_xer_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire \dbg_d_xer_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire \dbg_dmi_ack_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 \dbg_dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 \dbg_dmi_addr_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 \dbg_dmi_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 \dbg_dmi_din$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 \dbg_dmi_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire \dbg_dmi_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire \dbg_dmi_req_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire \dbg_dmi_we_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire \dbg_dmi_we_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102" + wire \dbg_terminate_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + wire width 8 \dec2_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec2_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \dec2_cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_cr_in1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_cr_in2$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_cr_in2_ok$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_cr_out_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \dec2_cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_cr_rd_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \dec2_cr_wr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_cr_wr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 \dec2_cur_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 \dec2_cur_dec$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + wire \dec2_cur_eint + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + wire \dec2_cur_eint$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \dec2_cur_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \dec2_cur_msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 \dec2_cur_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 \dec2_cur_pc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec2_ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_fasto2_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 12 \dec2_fn_unit + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 2 \dec2_input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 \dec2_insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 \dec2_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire \dec2_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire \dec2_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 \dec2_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 \dec2_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec2_reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec2_reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec2_reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec2_rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_rego_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \dec2_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \dec2_spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 13 \dec2_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 7 \dec2_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 \dec2_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + wire \dec2_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:157" + wire width 2 \delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:157" + wire width 2 \delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 \dmi__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \dmi__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \dmi__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + wire width 2 \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" + wire width 2 \fsm_state$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" + wire width 2 \fsm_state$115$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + wire width 2 \fsm_state$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 \full_rd2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \full_rd2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 6 \full_rd__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \full_rd__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 65 \gpio_gpio0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 15 \gpio_gpio0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 16 \gpio_gpio0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 14 \gpio_gpio0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 66 \gpio_gpio0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 67 \gpio_gpio0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 95 \gpio_gpio10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 45 \gpio_gpio10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 46 \gpio_gpio10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 44 \gpio_gpio10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 96 \gpio_gpio10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 97 \gpio_gpio10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 98 \gpio_gpio11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 48 \gpio_gpio11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 49 \gpio_gpio11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 47 \gpio_gpio11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 99 \gpio_gpio11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 100 \gpio_gpio11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 101 \gpio_gpio12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 51 \gpio_gpio12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 52 \gpio_gpio12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 50 \gpio_gpio12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 102 \gpio_gpio12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 103 \gpio_gpio12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 104 \gpio_gpio13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 54 \gpio_gpio13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 55 \gpio_gpio13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 53 \gpio_gpio13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 105 \gpio_gpio13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 106 \gpio_gpio13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 107 \gpio_gpio14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 57 \gpio_gpio14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 58 \gpio_gpio14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 56 \gpio_gpio14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 108 \gpio_gpio14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 109 \gpio_gpio14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 110 \gpio_gpio15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 60 \gpio_gpio15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 61 \gpio_gpio15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 59 \gpio_gpio15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 111 \gpio_gpio15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 112 \gpio_gpio15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 68 \gpio_gpio1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 18 \gpio_gpio1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 19 \gpio_gpio1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 17 \gpio_gpio1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 69 \gpio_gpio1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 70 \gpio_gpio1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 71 \gpio_gpio2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 21 \gpio_gpio2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 22 \gpio_gpio2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 20 \gpio_gpio2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 72 \gpio_gpio2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 73 \gpio_gpio2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 74 \gpio_gpio3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 24 \gpio_gpio3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 25 \gpio_gpio3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 23 \gpio_gpio3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 75 \gpio_gpio3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 76 \gpio_gpio3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 77 \gpio_gpio4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 27 \gpio_gpio4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 28 \gpio_gpio4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 26 \gpio_gpio4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 78 \gpio_gpio4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 79 \gpio_gpio4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 80 \gpio_gpio5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 30 \gpio_gpio5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 31 \gpio_gpio5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 29 \gpio_gpio5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 81 \gpio_gpio5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 82 \gpio_gpio5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 83 \gpio_gpio6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 33 \gpio_gpio6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 34 \gpio_gpio6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 32 \gpio_gpio6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 84 \gpio_gpio6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 85 \gpio_gpio6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 86 \gpio_gpio7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 36 \gpio_gpio7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 37 \gpio_gpio7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 35 \gpio_gpio7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 87 \gpio_gpio7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 88 \gpio_gpio7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 89 \gpio_gpio8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 39 \gpio_gpio8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 40 \gpio_gpio8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 38 \gpio_gpio8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 90 \gpio_gpio8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 91 \gpio_gpio8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 92 \gpio_gpio9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 42 \gpio_gpio9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 43 \gpio_gpio9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 41 \gpio_gpio9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 93 \gpio_gpio9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 94 \gpio_gpio9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 6 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 11 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 5 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 10 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 7 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 9 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 8 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 124 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 130 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 125 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 126 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 127 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 131 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 128 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 129 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire output 137 \ics_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 28 input 132 \ics_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 134 \ics_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 output 136 \ics_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 input 138 \ics_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 135 \ics_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 139 \ics_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:179" + wire width 32 \ilatch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:179" + wire width 32 \ilatch$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" + wire width 48 \imem_a_pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" + wire \imem_a_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" + wire \imem_f_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" + wire width 64 \imem_f_instr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" + wire \imem_f_valid_i + attribute \src "libresoc.v:47126.7-47126.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" + wire width 16 input 133 \int_level_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" + wire \intclk_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" + wire \intclk_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \issue__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \issue__addr$119 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \issue__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \issue__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \issue__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \issue__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" + wire \issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" + wire \ivalid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire \jtag_dmi0_ack_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire \jtag_dmi0_ack_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 \jtag_dmi0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 \jtag_dmi0_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 \jtag_dmi0_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 \jtag_dmi0_dout$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire \jtag_dmi0_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire \jtag_dmi0_we_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire input 120 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 29 output 114 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 116 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 64 input 121 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 64 output 119 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 115 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 117 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 118 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \msr__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \msr__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205" + wire \msr_read + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205" + wire \msr_read$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:373" + wire width 64 \new_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:390" + wire width 64 \new_tb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:182" + wire width 64 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:186" + wire width 64 \pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177" + wire \pc_changed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177" + wire \pc_changed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 4 \pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 3 \pc_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:89" + wire width 64 output 2 \pc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:187" + wire \pc_ok_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:187" + wire \pc_ok_delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire \por_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" + wire width 32 \raw_insn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" + wire width 32 \raw_insn_i$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \state_nia_wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 64 \uart_rx__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 13 \uart_rx__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 12 \uart_tx__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 63 \uart_tx__pad__o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" + wire \xics_icp_core_irq_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 \xics_icp_ics_i_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 \xics_icp_ics_i_src + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 \xics_ics_icp_o_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 \xics_ics_icp_o_src + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:391" + cell $add $add$libresoc.v:48723$1455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \issue__data_o + connect \B 1'1 + connect \Y $add$libresoc.v:48723$1455_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:183" + cell $add $add$libresoc.v:48726$1458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \dec2_cur_pc + connect \B 3'100 + connect \Y $add$libresoc.v:48726$1458_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:48725$1457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_st__rel_o + connect \B \$12 + connect \Y $and$libresoc.v:48725$1457_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $and $and$libresoc.v:48734$1466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$29 + connect \B \$31 + connect \Y $and$libresoc.v:48734$1466_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + cell $and $and$libresoc.v:48735$1467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \state_nia_wen + connect \B 1'1 + connect \Y $and$libresoc.v:48735$1467_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $and $and$libresoc.v:48743$1475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$47 + connect \B \$49 + connect \Y $and$libresoc.v:48743$1475_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $and $and$libresoc.v:48746$1478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$53 + connect \B \$55 + connect \Y $and$libresoc.v:48746$1478_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $and $and$libresoc.v:48749$1481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$59 + connect \B \$61 + connect \Y $and$libresoc.v:48749$1481_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $and $and$libresoc.v:48753$1485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$65 + connect \B \$67 + connect \Y $and$libresoc.v:48753$1485_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $and $and$libresoc.v:48756$1488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$71 + connect \B \$73 + connect \Y $and$libresoc.v:48756$1488_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $and $and$libresoc.v:48760$1492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$79 + connect \B \$81 + connect \Y $and$libresoc.v:48760$1492_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $and $and$libresoc.v:48765$1497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$87 + connect \B \$89 + connect \Y $and$libresoc.v:48765$1497_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $and $and$libresoc.v:48768$1500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$93 + connect \B \$95 + connect \Y $and$libresoc.v:48768$1500_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $extend$libresoc.v:48720$1450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \full_rd2__data_o + connect \Y $extend$libresoc.v:48720$1450_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $extend$libresoc.v:48721$1452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \full_rd__data_o + connect \Y $extend$libresoc.v:48721$1452_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + cell $mul $mul$libresoc.v:48714$1444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 7 + connect \A \dec2_cur_pc [2] + connect \B 6'100000 + connect \Y $mul$libresoc.v:48714$1444_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + cell $mul $mul$libresoc.v:48716$1446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 7 + connect \A \dec2_cur_pc [2] + connect \B 6'100000 + connect \Y $mul$libresoc.v:48716$1446_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:163" + cell $ne $ne$libresoc.v:48718$1448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \delay + connect \B \$8 + connect \Y $ne$libresoc.v:48718$1448_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + cell $ne $ne$libresoc.v:48719$1449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \core_core_insn_type + connect \B 7'0000001 + connect \Y $ne$libresoc.v:48719$1449_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:158" + cell $ne $ne$libresoc.v:48737$1469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \delay + connect \B 1'0 + connect \Y $ne$libresoc.v:48737$1469_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:257" + cell $not $not$libresoc.v:48713$1443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msr_read + connect \Y $not$libresoc.v:48713$1443_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:48724$1456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_st__rel_o_dly + connect \Y $not$libresoc.v:48724$1456_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:188" + cell $not $not$libresoc.v:48727$1459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_i_ok + connect \Y $not$libresoc.v:48727$1459_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" + cell $not $not$libresoc.v:48728$1460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \corebusy_o + connect \Y $not$libresoc.v:48728$1460_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" + cell $not $not$libresoc.v:48729$1461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_changed + connect \Y $not$libresoc.v:48729$1461_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" + cell $not $not$libresoc.v:48730$1462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \corebusy_o + connect \Y $not$libresoc.v:48730$1462_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" + cell $not $not$libresoc.v:48731$1463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_changed + connect \Y $not$libresoc.v:48731$1463_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $not $not$libresoc.v:48732$1464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:48732$1464_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $not $not$libresoc.v:48733$1465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_reset_i + connect \Y $not$libresoc.v:48733$1465_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" + cell $not $not$libresoc.v:48738$1470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \corebusy_o + connect \Y $not$libresoc.v:48738$1470_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" + cell $not $not$libresoc.v:48739$1471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \corebusy_o + connect \Y $not$libresoc.v:48739$1471_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" + cell $not $not$libresoc.v:48740$1472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \corebusy_o + connect \Y $not$libresoc.v:48740$1472_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $not $not$libresoc.v:48741$1473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:48741$1473_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $not $not$libresoc.v:48742$1474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_reset_i + connect \Y $not$libresoc.v:48742$1474_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $not $not$libresoc.v:48744$1476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:48744$1476_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $not $not$libresoc.v:48745$1477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_reset_i + connect \Y $not$libresoc.v:48745$1477_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $not $not$libresoc.v:48747$1479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:48747$1479_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $not $not$libresoc.v:48748$1480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_reset_i + connect \Y $not$libresoc.v:48748$1480_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $not $not$libresoc.v:48750$1482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:48750$1482_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $not $not$libresoc.v:48751$1483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_reset_i + connect \Y $not$libresoc.v:48751$1483_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $not $not$libresoc.v:48754$1486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:48754$1486_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $not $not$libresoc.v:48755$1487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_reset_i + connect \Y $not$libresoc.v:48755$1487_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:257" + cell $not $not$libresoc.v:48757$1489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msr_read + connect \Y $not$libresoc.v:48757$1489_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $not $not$libresoc.v:48758$1490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:48758$1490_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $not $not$libresoc.v:48759$1491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_reset_i + connect \Y $not$libresoc.v:48759$1491_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" + cell $not $not$libresoc.v:48761$1493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \corebusy_o + connect \Y $not$libresoc.v:48761$1493_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $not $not$libresoc.v:48762$1494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:48762$1494_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $not $not$libresoc.v:48764$1496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_reset_i + connect \Y $not$libresoc.v:48764$1496_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $not $not$libresoc.v:48766$1498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:48766$1498_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + cell $not $not$libresoc.v:48767$1499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_reset_i + connect \Y $not$libresoc.v:48767$1499_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:163" + cell $or $or$libresoc.v:48763$1495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B \dbg_core_rst_o + connect \Y $or$libresoc.v:48763$1495_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $pos$libresoc.v:48720$1451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:48720$1450_Y + connect \Y $pos$libresoc.v:48720$1451_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $pos$libresoc.v:48721$1453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:48721$1452_Y + connect \Y $pos$libresoc.v:48721$1453_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:48736$1468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$36 + connect \Y $reduce_or$libresoc.v:48736$1468_Y + end + attribute \src "libresoc.v:48715.19-48715.42" + cell $shr $shr$libresoc.v:48715$1445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \imem_f_instr_o + connect \B \$102 + connect \Y $shr$libresoc.v:48715$1445_Y + end + attribute \src "libresoc.v:48717.19-48717.42" + cell $shr $shr$libresoc.v:48717$1447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \imem_f_instr_o + connect \B \$106 + connect \Y $shr$libresoc.v:48717$1447_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" + cell $sub $sub$libresoc.v:48722$1454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \issue__data_o + connect \B 1'1 + connect \Y $sub$libresoc.v:48722$1454_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:159" + cell $sub $sub$libresoc.v:48752$1484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \delay + connect \B 1'1 + connect \Y $sub$libresoc.v:48752$1484_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:48925.7-48950.4" + cell \dbg \dbg + connect \core_dbg_msr \dbg_core_dbg_msr + connect \core_dbg_pc \dbg_core_dbg_pc + connect \core_rst_o \dbg_core_rst_o + connect \core_stop_o \dbg_core_stop_o + connect \core_stopped_i \dbg_core_stopped_i + connect \d_cr_ack \dbg_d_cr_ack + connect \d_cr_data \dbg_d_cr_data + connect \d_cr_req \dbg_d_cr_req + connect \d_gpr_ack \dbg_d_gpr_ack + connect \d_gpr_addr \dbg_d_gpr_addr + connect \d_gpr_data \dbg_d_gpr_data + connect \d_gpr_req \dbg_d_gpr_req + connect \d_xer_ack \dbg_d_xer_ack + connect \d_xer_data \dbg_d_xer_data + connect \d_xer_req \dbg_d_xer_req + connect \dmi_ack_o \dbg_dmi_ack_o + connect \dmi_addr_i \dbg_dmi_addr_i + connect \dmi_din \dbg_dmi_din + connect \dmi_dout \dbg_dmi_dout + connect \dmi_req_i \dbg_dmi_req_i + connect \dmi_we_i \dbg_dmi_we_i + connect \intclk_clk \intclk_clk + connect \intclk_rst \intclk_rst + connect \terminate_i \dbg_terminate_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:48951.8-49009.4" + cell \dec2 \dec2 + connect \asmcode \dec2_asmcode + connect \bigendian \dec2_bigendian + connect \cia \dec2_cia + connect \cr_in1 \dec2_cr_in1 + connect \cr_in1_ok \dec2_cr_in1_ok + connect \cr_in2 \dec2_cr_in2 + connect \cr_in2$1 \dec2_cr_in2$1 + connect \cr_in2_ok \dec2_cr_in2_ok + connect \cr_in2_ok$2 \dec2_cr_in2_ok$2 + connect \cr_out \dec2_cr_out + connect \cr_out_ok \dec2_cr_out_ok + connect \cr_rd \dec2_cr_rd + connect \cr_rd_ok \dec2_cr_rd_ok + connect \cr_wr \dec2_cr_wr + connect \cr_wr_ok \dec2_cr_wr_ok + connect \cur_dec \dec2_cur_dec + connect \cur_eint \dec2_cur_eint + connect \cur_msr \dec2_cur_msr + connect \cur_pc \dec2_cur_pc + connect \ea \dec2_ea + connect \ea_ok \dec2_ea_ok + connect \fast1 \dec2_fast1 + connect \fast1_ok \dec2_fast1_ok + connect \fast2 \dec2_fast2 + connect \fast2_ok \dec2_fast2_ok + connect \fasto1 \dec2_fasto1 + connect \fasto1_ok \dec2_fasto1_ok + connect \fasto2 \dec2_fasto2 + connect \fasto2_ok \dec2_fasto2_ok + connect \fn_unit \dec2_fn_unit + connect \input_carry \dec2_input_carry + connect \insn \dec2_insn + connect \insn_type \dec2_insn_type + connect \is_32bit \dec2_is_32bit + connect \lk \dec2_lk + connect \msr \dec2_msr + connect \oe \dec2_oe + connect \oe_ok \dec2_oe_ok + connect \raw_opcode_in \dec2_raw_opcode_in + connect \rc \dec2_rc + connect \rc_ok \dec2_rc_ok + connect \reg1 \dec2_reg1 + connect \reg1_ok \dec2_reg1_ok + connect \reg2 \dec2_reg2 + connect \reg2_ok \dec2_reg2_ok + connect \reg3 \dec2_reg3 + connect \reg3_ok \dec2_reg3_ok + connect \rego \dec2_rego + connect \rego_ok \dec2_rego_ok + connect \spr1 \dec2_spr1 + connect \spr1_ok \dec2_spr1_ok + connect \spro \dec2_spro + connect \spro_ok \dec2_spro_ok + connect \trapaddr \dec2_trapaddr + connect \traptype \dec2_traptype + connect \xer_in \dec2_xer_in + connect \xer_out \dec2_xer_out + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49010.8-49025.4" + cell \imem \imem + connect \a_pc_i \imem_a_pc_i + connect \a_valid_i \imem_a_valid_i + connect \f_busy_o \imem_f_busy_o + connect \f_instr_o \imem_f_instr_o + connect \f_valid_i \imem_f_valid_i + connect \ibus__ack \ibus__ack + connect \ibus__adr \ibus__adr + connect \ibus__cyc \ibus__cyc + connect \ibus__dat_r \ibus__dat_r + connect \ibus__err \ibus__err + connect \ibus__sel \ibus__sel + connect \ibus__stb \ibus__stb + connect \intclk_clk \intclk_clk + connect \intclk_rst \intclk_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49026.8-49147.4" + cell \jtag \jtag + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_bus__tdo \TAP_bus__tdo + connect \TAP_bus__tms \TAP_bus__tms + connect \dmi0_ack_o \jtag_dmi0_ack_o + connect \dmi0_addr_i \jtag_dmi0_addr_i + connect \dmi0_din \jtag_dmi0_din + connect \dmi0_dout \jtag_dmi0_dout + connect \dmi0_req_i \jtag_dmi0_req_i + connect \dmi0_we_i \jtag_dmi0_we_i + connect \gpio_gpio0__core__i \gpio_gpio0__core__i + connect \gpio_gpio0__core__o \gpio_gpio0__core__o + connect \gpio_gpio0__core__oe \gpio_gpio0__core__oe + connect \gpio_gpio0__pad__i \gpio_gpio0__pad__i + connect \gpio_gpio0__pad__o \gpio_gpio0__pad__o + connect \gpio_gpio0__pad__oe \gpio_gpio0__pad__oe + connect \gpio_gpio10__core__i \gpio_gpio10__core__i + connect \gpio_gpio10__core__o \gpio_gpio10__core__o + connect \gpio_gpio10__core__oe \gpio_gpio10__core__oe + connect \gpio_gpio10__pad__i \gpio_gpio10__pad__i + connect \gpio_gpio10__pad__o \gpio_gpio10__pad__o + connect \gpio_gpio10__pad__oe \gpio_gpio10__pad__oe + connect \gpio_gpio11__core__i \gpio_gpio11__core__i + connect \gpio_gpio11__core__o \gpio_gpio11__core__o + connect \gpio_gpio11__core__oe \gpio_gpio11__core__oe + connect \gpio_gpio11__pad__i \gpio_gpio11__pad__i + connect \gpio_gpio11__pad__o \gpio_gpio11__pad__o + connect \gpio_gpio11__pad__oe \gpio_gpio11__pad__oe + connect \gpio_gpio12__core__i \gpio_gpio12__core__i + connect \gpio_gpio12__core__o \gpio_gpio12__core__o + connect \gpio_gpio12__core__oe \gpio_gpio12__core__oe + connect \gpio_gpio12__pad__i \gpio_gpio12__pad__i + connect \gpio_gpio12__pad__o \gpio_gpio12__pad__o + connect \gpio_gpio12__pad__oe \gpio_gpio12__pad__oe + connect \gpio_gpio13__core__i \gpio_gpio13__core__i + connect \gpio_gpio13__core__o \gpio_gpio13__core__o + connect \gpio_gpio13__core__oe \gpio_gpio13__core__oe + connect \gpio_gpio13__pad__i \gpio_gpio13__pad__i + connect \gpio_gpio13__pad__o \gpio_gpio13__pad__o + connect \gpio_gpio13__pad__oe \gpio_gpio13__pad__oe + connect \gpio_gpio14__core__i \gpio_gpio14__core__i + connect \gpio_gpio14__core__o \gpio_gpio14__core__o + connect \gpio_gpio14__core__oe \gpio_gpio14__core__oe + connect \gpio_gpio14__pad__i \gpio_gpio14__pad__i + connect \gpio_gpio14__pad__o \gpio_gpio14__pad__o + connect \gpio_gpio14__pad__oe \gpio_gpio14__pad__oe + connect \gpio_gpio15__core__i \gpio_gpio15__core__i + connect \gpio_gpio15__core__o \gpio_gpio15__core__o + connect \gpio_gpio15__core__oe \gpio_gpio15__core__oe + connect \gpio_gpio15__pad__i \gpio_gpio15__pad__i + connect \gpio_gpio15__pad__o \gpio_gpio15__pad__o + connect \gpio_gpio15__pad__oe \gpio_gpio15__pad__oe + connect \gpio_gpio1__core__i \gpio_gpio1__core__i + connect \gpio_gpio1__core__o \gpio_gpio1__core__o + connect \gpio_gpio1__core__oe \gpio_gpio1__core__oe + connect \gpio_gpio1__pad__i \gpio_gpio1__pad__i + connect \gpio_gpio1__pad__o \gpio_gpio1__pad__o + connect \gpio_gpio1__pad__oe \gpio_gpio1__pad__oe + connect \gpio_gpio2__core__i \gpio_gpio2__core__i + connect \gpio_gpio2__core__o \gpio_gpio2__core__o + connect \gpio_gpio2__core__oe \gpio_gpio2__core__oe + connect \gpio_gpio2__pad__i \gpio_gpio2__pad__i + connect \gpio_gpio2__pad__o \gpio_gpio2__pad__o + connect \gpio_gpio2__pad__oe \gpio_gpio2__pad__oe + connect \gpio_gpio3__core__i \gpio_gpio3__core__i + connect \gpio_gpio3__core__o \gpio_gpio3__core__o + connect \gpio_gpio3__core__oe \gpio_gpio3__core__oe + connect \gpio_gpio3__pad__i \gpio_gpio3__pad__i + connect \gpio_gpio3__pad__o \gpio_gpio3__pad__o + connect \gpio_gpio3__pad__oe \gpio_gpio3__pad__oe + connect \gpio_gpio4__core__i \gpio_gpio4__core__i + connect \gpio_gpio4__core__o \gpio_gpio4__core__o + connect \gpio_gpio4__core__oe \gpio_gpio4__core__oe + connect \gpio_gpio4__pad__i \gpio_gpio4__pad__i + connect \gpio_gpio4__pad__o \gpio_gpio4__pad__o + connect \gpio_gpio4__pad__oe \gpio_gpio4__pad__oe + connect \gpio_gpio5__core__i \gpio_gpio5__core__i + connect \gpio_gpio5__core__o \gpio_gpio5__core__o + connect \gpio_gpio5__core__oe \gpio_gpio5__core__oe + connect \gpio_gpio5__pad__i \gpio_gpio5__pad__i + connect \gpio_gpio5__pad__o \gpio_gpio5__pad__o + connect \gpio_gpio5__pad__oe \gpio_gpio5__pad__oe + connect \gpio_gpio6__core__i \gpio_gpio6__core__i + connect \gpio_gpio6__core__o \gpio_gpio6__core__o + connect \gpio_gpio6__core__oe \gpio_gpio6__core__oe + connect \gpio_gpio6__pad__i \gpio_gpio6__pad__i + connect \gpio_gpio6__pad__o \gpio_gpio6__pad__o + connect \gpio_gpio6__pad__oe \gpio_gpio6__pad__oe + connect \gpio_gpio7__core__i \gpio_gpio7__core__i + connect \gpio_gpio7__core__o \gpio_gpio7__core__o + connect \gpio_gpio7__core__oe \gpio_gpio7__core__oe + connect \gpio_gpio7__pad__i \gpio_gpio7__pad__i + connect \gpio_gpio7__pad__o \gpio_gpio7__pad__o + connect \gpio_gpio7__pad__oe \gpio_gpio7__pad__oe + connect \gpio_gpio8__core__i \gpio_gpio8__core__i + connect \gpio_gpio8__core__o \gpio_gpio8__core__o + connect \gpio_gpio8__core__oe \gpio_gpio8__core__oe + connect \gpio_gpio8__pad__i \gpio_gpio8__pad__i + connect \gpio_gpio8__pad__o \gpio_gpio8__pad__o + connect \gpio_gpio8__pad__oe \gpio_gpio8__pad__oe + connect \gpio_gpio9__core__i \gpio_gpio9__core__i + connect \gpio_gpio9__core__o \gpio_gpio9__core__o + connect \gpio_gpio9__core__oe \gpio_gpio9__core__oe + connect \gpio_gpio9__pad__i \gpio_gpio9__pad__i + connect \gpio_gpio9__pad__o \gpio_gpio9__pad__o + connect \gpio_gpio9__pad__oe \gpio_gpio9__pad__oe + connect \intclk_clk \intclk_clk + connect \intclk_rst \intclk_rst + connect \jtag_wb__ack \jtag_wb__ack + connect \jtag_wb__adr \jtag_wb__adr + connect \jtag_wb__cyc \jtag_wb__cyc + connect \jtag_wb__dat_r \jtag_wb__dat_r + connect \jtag_wb__dat_w \jtag_wb__dat_w + connect \jtag_wb__sel \jtag_wb__sel + connect \jtag_wb__stb \jtag_wb__stb + connect \jtag_wb__we \jtag_wb__we + connect \uart_rx__core__i \uart_rx__core__i + connect \uart_rx__pad__i \uart_rx__pad__i + connect \uart_tx__core__o \uart_tx__core__o + connect \uart_tx__pad__o \uart_tx__pad__o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49148.12-49162.4" + cell \xics_icp \xics_icp + connect \core_irq_o \xics_icp_core_irq_o + connect \icp_wb__ack \icp_wb__ack + connect \icp_wb__adr \icp_wb__adr + connect \icp_wb__cyc \icp_wb__cyc + connect \icp_wb__dat_r \icp_wb__dat_r + connect \icp_wb__dat_w \icp_wb__dat_w + connect \icp_wb__sel \icp_wb__sel + connect \icp_wb__stb \icp_wb__stb + connect \icp_wb__we \icp_wb__we + connect \ics_i_pri \xics_icp_ics_i_pri + connect \ics_i_src \xics_icp_ics_i_src + connect \intclk_clk \intclk_clk + connect \intclk_rst \intclk_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49163.12-49176.4" + cell \xics_ics \xics_ics + connect \icp_o_pri \xics_ics_icp_o_pri + connect \icp_o_src \xics_ics_icp_o_src + connect \ics_wb__ack \ics_wb__ack + connect \ics_wb__adr \ics_wb__adr + connect \ics_wb__cyc \ics_wb__cyc + connect \ics_wb__dat_r \ics_wb__dat_r + connect \ics_wb__dat_w \ics_wb__dat_w + connect \ics_wb__stb \ics_wb__stb + connect \ics_wb__we \ics_wb__we + connect \int_level_i \int_level_i + connect \intclk_clk \intclk_clk + connect \intclk_rst \intclk_rst + end + attribute \src "libresoc.v:47126.7-47126.20" + process $proc$libresoc.v:47126$1944 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:47256.7-47256.25" + process $proc$libresoc.v:47256$1945 + assign { } { } + assign $1\bigendian_i[0:0] 1'0 + sync always + sync init + update \bigendian_i $1\bigendian_i[0:0] + end + attribute \src "libresoc.v:47266.13-47266.33" + process $proc$libresoc.v:47266$1946 + assign { } { } + assign $1\core_asmcode[7:0] 8'00000000 + sync always + sync init + update \core_asmcode $1\core_asmcode[7:0] + end + attribute \src "libresoc.v:47272.14-47272.50" + process $proc$libresoc.v:47272$1947 + assign { } { } + assign $1\core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_core_cia $1\core_core_cia[63:0] + end + attribute \src "libresoc.v:47276.13-47276.36" + process $proc$libresoc.v:47276$1948 + assign { } { } + assign $1\core_core_cr_rd[7:0] 8'00000000 + sync always + sync init + update \core_core_cr_rd $1\core_core_cr_rd[7:0] + end + attribute \src "libresoc.v:47280.7-47280.32" + process $proc$libresoc.v:47280$1949 + assign { } { } + assign $1\core_core_cr_rd_ok[0:0] 1'0 + sync always + sync init + update \core_core_cr_rd_ok $1\core_core_cr_rd_ok[0:0] + end + attribute \src "libresoc.v:47284.13-47284.36" + process $proc$libresoc.v:47284$1950 + assign { } { } + assign $1\core_core_cr_wr[7:0] 8'00000000 + sync always + sync init + update \core_core_cr_wr $1\core_core_cr_wr[7:0] + end + attribute \src "libresoc.v:47288.7-47288.32" + process $proc$libresoc.v:47288$1951 + assign { } { } + assign $1\core_core_cr_wr_ok[0:0] 1'0 + sync always + sync init + update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] + end + attribute \src "libresoc.v:47305.14-47305.41" + process $proc$libresoc.v:47305$1952 + assign { } { } + assign $1\core_core_fn_unit[11:0] 12'000000000000 + sync always + sync init + update \core_core_fn_unit $1\core_core_fn_unit[11:0] + end + attribute \src "libresoc.v:47313.13-47313.41" + process $proc$libresoc.v:47313$1953 + assign { } { } + assign $1\core_core_input_carry[1:0] 2'00 + sync always + sync init + update \core_core_input_carry $1\core_core_input_carry[1:0] + end + attribute \src "libresoc.v:47317.14-47317.36" + process $proc$libresoc.v:47317$1954 + assign { } { } + assign $1\core_core_insn[31:0] 0 + sync always + sync init + update \core_core_insn $1\core_core_insn[31:0] + end + attribute \src "libresoc.v:47395.13-47395.40" + process $proc$libresoc.v:47395$1955 + assign { } { } + assign $1\core_core_insn_type[6:0] 7'0000000 + sync always + sync init + update \core_core_insn_type $1\core_core_insn_type[6:0] + end + attribute \src "libresoc.v:47399.7-47399.32" + process $proc$libresoc.v:47399$1956 + assign { } { } + assign $1\core_core_is_32bit[0:0] 1'0 + sync always + sync init + update \core_core_is_32bit $1\core_core_is_32bit[0:0] + end + attribute \src "libresoc.v:47403.7-47403.26" + process $proc$libresoc.v:47403$1957 + assign { } { } + assign $1\core_core_lk[0:0] 1'0 + sync always + sync init + update \core_core_lk $1\core_core_lk[0:0] + end + attribute \src "libresoc.v:47407.14-47407.50" + process $proc$libresoc.v:47407$1958 + assign { } { } + assign $1\core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_core_msr $1\core_core_msr[63:0] + end + attribute \src "libresoc.v:47411.7-47411.26" + process $proc$libresoc.v:47411$1959 + assign { } { } + assign $1\core_core_oe[0:0] 1'0 + sync always + sync init + update \core_core_oe $1\core_core_oe[0:0] + end + attribute \src "libresoc.v:47415.7-47415.29" + process $proc$libresoc.v:47415$1960 + assign { } { } + assign $1\core_core_oe_ok[0:0] 1'0 + sync always + sync init + update \core_core_oe_ok $1\core_core_oe_ok[0:0] + end + attribute \src "libresoc.v:47419.7-47419.26" + process $proc$libresoc.v:47419$1961 + assign { } { } + assign $1\core_core_rc[0:0] 1'0 + sync always + sync init + update \core_core_rc $1\core_core_rc[0:0] + end + attribute \src "libresoc.v:47423.7-47423.29" + process $proc$libresoc.v:47423$1962 + assign { } { } + assign $1\core_core_rc_ok[0:0] 1'0 + sync always + sync init + update \core_core_rc_ok $1\core_core_rc_ok[0:0] + end + attribute \src "libresoc.v:47427.14-47427.43" + process $proc$libresoc.v:47427$1963 + assign { } { } + assign $1\core_core_trapaddr[12:0] 13'0000000000000 + sync always + sync init + update \core_core_trapaddr $1\core_core_trapaddr[12:0] + end + attribute \src "libresoc.v:47431.13-47431.39" + process $proc$libresoc.v:47431$1964 + assign { } { } + assign $1\core_core_traptype[6:0] 7'0000000 + sync always + sync init + update \core_core_traptype $1\core_core_traptype[6:0] + end + attribute \src "libresoc.v:47435.13-47435.31" + process $proc$libresoc.v:47435$1965 + assign { } { } + assign $1\core_cr_in1[2:0] 3'000 + sync always + sync init + update \core_cr_in1 $1\core_cr_in1[2:0] + end + attribute \src "libresoc.v:47439.7-47439.28" + process $proc$libresoc.v:47439$1966 + assign { } { } + assign $1\core_cr_in1_ok[0:0] 1'0 + sync always + sync init + update \core_cr_in1_ok $1\core_cr_in1_ok[0:0] + end + attribute \src "libresoc.v:47443.13-47443.31" + process $proc$libresoc.v:47443$1967 + assign { } { } + assign $1\core_cr_in2[2:0] 3'000 + sync always + sync init + update \core_cr_in2 $1\core_cr_in2[2:0] + end + attribute \src "libresoc.v:47445.13-47445.36" + process $proc$libresoc.v:47445$1968 + assign { } { } + assign $0\core_cr_in2$39[2:0]$1969 3'000 + sync always + sync init + update \core_cr_in2$39 $0\core_cr_in2$39[2:0]$1969 + end + attribute \src "libresoc.v:47451.7-47451.28" + process $proc$libresoc.v:47451$1970 + assign { } { } + assign $1\core_cr_in2_ok[0:0] 1'0 + sync always + sync init + update \core_cr_in2_ok $1\core_cr_in2_ok[0:0] + end + attribute \src "libresoc.v:47453.7-47453.33" + process $proc$libresoc.v:47453$1971 + assign { } { } + assign $0\core_cr_in2_ok$40[0:0]$1972 1'0 + sync always + sync init + update \core_cr_in2_ok$40 $0\core_cr_in2_ok$40[0:0]$1972 + end + attribute \src "libresoc.v:47459.13-47459.31" + process $proc$libresoc.v:47459$1973 + assign { } { } + assign $1\core_cr_out[2:0] 3'000 + sync always + sync init + update \core_cr_out $1\core_cr_out[2:0] + end + attribute \src "libresoc.v:47463.7-47463.28" + process $proc$libresoc.v:47463$1974 + assign { } { } + assign $1\core_cr_out_ok[0:0] 1'0 + sync always + sync init + update \core_cr_out_ok $1\core_cr_out_ok[0:0] + end + attribute \src "libresoc.v:47467.14-47467.45" + process $proc$libresoc.v:47467$1975 + assign { } { } + assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_dec $1\core_dec[63:0] + end + attribute \src "libresoc.v:47471.13-47471.28" + process $proc$libresoc.v:47471$1976 + assign { } { } + assign $1\core_ea[4:0] 5'00000 + sync always + sync init + update \core_ea $1\core_ea[4:0] + end + attribute \src "libresoc.v:47475.7-47475.24" + process $proc$libresoc.v:47475$1977 + assign { } { } + assign $1\core_ea_ok[0:0] 1'0 + sync always + sync init + update \core_ea_ok $1\core_ea_ok[0:0] + end + attribute \src "libresoc.v:47479.7-47479.23" + process $proc$libresoc.v:47479$1978 + assign { } { } + assign $1\core_eint[0:0] 1'0 + sync always + sync init + update \core_eint $1\core_eint[0:0] + end + attribute \src "libresoc.v:47483.13-47483.30" + process $proc$libresoc.v:47483$1979 + assign { } { } + assign $1\core_fast1[2:0] 3'000 + sync always + sync init + update \core_fast1 $1\core_fast1[2:0] + end + attribute \src "libresoc.v:47487.7-47487.27" + process $proc$libresoc.v:47487$1980 + assign { } { } + assign $1\core_fast1_ok[0:0] 1'0 + sync always + sync init + update \core_fast1_ok $1\core_fast1_ok[0:0] + end + attribute \src "libresoc.v:47491.13-47491.30" + process $proc$libresoc.v:47491$1981 + assign { } { } + assign $1\core_fast2[2:0] 3'000 + sync always + sync init + update \core_fast2 $1\core_fast2[2:0] + end + attribute \src "libresoc.v:47495.7-47495.27" + process $proc$libresoc.v:47495$1982 + assign { } { } + assign $1\core_fast2_ok[0:0] 1'0 + sync always + sync init + update \core_fast2_ok $1\core_fast2_ok[0:0] + end + attribute \src "libresoc.v:47499.13-47499.31" + process $proc$libresoc.v:47499$1983 + assign { } { } + assign $1\core_fasto1[2:0] 3'000 + sync always + sync init + update \core_fasto1 $1\core_fasto1[2:0] + end + attribute \src "libresoc.v:47503.7-47503.28" + process $proc$libresoc.v:47503$1984 + assign { } { } + assign $1\core_fasto1_ok[0:0] 1'0 + sync always + sync init + update \core_fasto1_ok $1\core_fasto1_ok[0:0] + end + attribute \src "libresoc.v:47507.13-47507.31" + process $proc$libresoc.v:47507$1985 + assign { } { } + assign $1\core_fasto2[2:0] 3'000 + sync always + sync init + update \core_fasto2 $1\core_fasto2[2:0] + end + attribute \src "libresoc.v:47511.7-47511.28" + process $proc$libresoc.v:47511$1986 + assign { } { } + assign $1\core_fasto2_ok[0:0] 1'0 + sync always + sync init + update \core_fasto2_ok $1\core_fasto2_ok[0:0] + end + attribute \src "libresoc.v:47515.14-47515.45" + process $proc$libresoc.v:47515$1987 + assign { } { } + assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_msr $1\core_msr[63:0] + end + attribute \src "libresoc.v:47519.14-47519.44" + process $proc$libresoc.v:47519$1988 + assign { } { } + assign $1\core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_pc $1\core_pc[63:0] + end + attribute \src "libresoc.v:47523.13-47523.30" + process $proc$libresoc.v:47523$1989 + assign { } { } + assign $1\core_reg1[4:0] 5'00000 + sync always + sync init + update \core_reg1 $1\core_reg1[4:0] + end + attribute \src "libresoc.v:47527.7-47527.26" + process $proc$libresoc.v:47527$1990 + assign { } { } + assign $1\core_reg1_ok[0:0] 1'0 + sync always + sync init + update \core_reg1_ok $1\core_reg1_ok[0:0] + end + attribute \src "libresoc.v:47531.13-47531.30" + process $proc$libresoc.v:47531$1991 + assign { } { } + assign $1\core_reg2[4:0] 5'00000 + sync always + sync init + update \core_reg2 $1\core_reg2[4:0] + end + attribute \src "libresoc.v:47535.7-47535.26" + process $proc$libresoc.v:47535$1992 + assign { } { } + assign $1\core_reg2_ok[0:0] 1'0 + sync always + sync init + update \core_reg2_ok $1\core_reg2_ok[0:0] + end + attribute \src "libresoc.v:47539.13-47539.30" + process $proc$libresoc.v:47539$1993 + assign { } { } + assign $1\core_reg3[4:0] 5'00000 + sync always + sync init + update \core_reg3 $1\core_reg3[4:0] + end + attribute \src "libresoc.v:47543.7-47543.26" + process $proc$libresoc.v:47543$1994 + assign { } { } + assign $1\core_reg3_ok[0:0] 1'0 + sync always + sync init + update \core_reg3_ok $1\core_reg3_ok[0:0] + end + attribute \src "libresoc.v:47547.13-47547.30" + process $proc$libresoc.v:47547$1995 + assign { } { } + assign $1\core_rego[4:0] 5'00000 + sync always + sync init + update \core_rego $1\core_rego[4:0] + end + attribute \src "libresoc.v:47551.7-47551.26" + process $proc$libresoc.v:47551$1996 + assign { } { } + assign $1\core_rego_ok[0:0] 1'0 + sync always + sync init + update \core_rego_ok $1\core_rego_ok[0:0] + end + attribute \src "libresoc.v:47668.13-47668.32" + process $proc$libresoc.v:47668$1997 + assign { } { } + assign $1\core_spr1[9:0] 10'0000000000 + sync always + sync init + update \core_spr1 $1\core_spr1[9:0] + end + attribute \src "libresoc.v:47672.7-47672.26" + process $proc$libresoc.v:47672$1998 + assign { } { } + assign $1\core_spr1_ok[0:0] 1'0 + sync always + sync init + update \core_spr1_ok $1\core_spr1_ok[0:0] + end + attribute \src "libresoc.v:47787.13-47787.32" + process $proc$libresoc.v:47787$1999 + assign { } { } + assign $1\core_spro[9:0] 10'0000000000 + sync always + sync init + update \core_spro $1\core_spro[9:0] + end + attribute \src "libresoc.v:47791.7-47791.26" + process $proc$libresoc.v:47791$2000 + assign { } { } + assign $1\core_spro_ok[0:0] 1'0 + sync always + sync init + update \core_spro_ok $1\core_spro_ok[0:0] + end + attribute \src "libresoc.v:47799.13-47799.31" + process $proc$libresoc.v:47799$2001 + assign { } { } + assign $1\core_xer_in[2:0] 3'000 + sync always + sync init + update \core_xer_in $1\core_xer_in[2:0] + end + attribute \src "libresoc.v:47803.7-47803.26" + process $proc$libresoc.v:47803$2002 + assign { } { } + assign $1\core_xer_out[0:0] 1'0 + sync always + sync init + update \core_xer_out $1\core_xer_out[0:0] + end + attribute \src "libresoc.v:47819.7-47819.30" + process $proc$libresoc.v:47819$2003 + assign { } { } + assign $1\cu_st__rel_o_dly[0:0] 1'0 + sync always + sync init + update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] + end + attribute \src "libresoc.v:47825.7-47825.24" + process $proc$libresoc.v:47825$2004 + assign { } { } + assign $1\d_cr_delay[0:0] 1'0 + sync always + sync init + update \d_cr_delay $1\d_cr_delay[0:0] + end + attribute \src "libresoc.v:47829.7-47829.25" + process $proc$libresoc.v:47829$2005 + assign { } { } + assign $1\d_reg_delay[0:0] 1'0 + sync always + sync init + update \d_reg_delay $1\d_reg_delay[0:0] + end + attribute \src "libresoc.v:47833.7-47833.25" + process $proc$libresoc.v:47833$2006 + assign { } { } + assign $1\d_xer_delay[0:0] 1'0 + sync always + sync init + update \d_xer_delay $1\d_xer_delay[0:0] + end + attribute \src "libresoc.v:47871.13-47871.34" + process $proc$libresoc.v:47871$2007 + assign { } { } + assign $1\dbg_dmi_addr_i[3:0] 4'0000 + sync always + sync init + update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] + end + attribute \src "libresoc.v:47875.14-47875.48" + process $proc$libresoc.v:47875$2008 + assign { } { } + assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dbg_dmi_din $1\dbg_dmi_din[63:0] + end + attribute \src "libresoc.v:47881.7-47881.27" + process $proc$libresoc.v:47881$2009 + assign { } { } + assign $1\dbg_dmi_req_i[0:0] 1'0 + sync always + sync init + update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] + end + attribute \src "libresoc.v:47885.7-47885.26" + process $proc$libresoc.v:47885$2010 + assign { } { } + assign $1\dbg_dmi_we_i[0:0] 1'0 + sync always + sync init + update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] + end + attribute \src "libresoc.v:47921.14-47921.49" + process $proc$libresoc.v:47921$2011 + assign { } { } + assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_dec $1\dec2_cur_dec[63:0] + end + attribute \src "libresoc.v:47925.7-47925.27" + process $proc$libresoc.v:47925$2012 + assign { } { } + assign $1\dec2_cur_eint[0:0] 1'0 + sync always + sync init + update \dec2_cur_eint $1\dec2_cur_eint[0:0] + end + attribute \src "libresoc.v:47929.14-47929.49" + process $proc$libresoc.v:47929$2013 + assign { } { } + assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_msr $1\dec2_cur_msr[63:0] + end + attribute \src "libresoc.v:47933.14-47933.48" + process $proc$libresoc.v:47933$2014 + assign { } { } + assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_pc $1\dec2_cur_pc[63:0] + end + attribute \src "libresoc.v:48326.13-48326.25" + process $proc$libresoc.v:48326$2015 + assign { } { } + assign $1\delay[1:0] 2'11 + sync always + sync init + update \delay $1\delay[1:0] + end + attribute \src "libresoc.v:48336.13-48336.29" + process $proc$libresoc.v:48336$2016 + assign { } { } + assign $1\fsm_state[1:0] 2'00 + sync always + sync init + update \fsm_state $1\fsm_state[1:0] + end + attribute \src "libresoc.v:48338.13-48338.35" + process $proc$libresoc.v:48338$2017 + assign { } { } + assign $0\fsm_state$115[1:0]$2018 2'00 + sync always + sync init + update \fsm_state$115 $0\fsm_state$115[1:0]$2018 + end + attribute \src "libresoc.v:48588.14-48588.28" + process $proc$libresoc.v:48588$2019 + assign { } { } + assign $1\ilatch[31:0] 0 + sync always + sync init + update \ilatch $1\ilatch[31:0] + end + attribute \src "libresoc.v:48624.7-48624.29" + process $proc$libresoc.v:48624$2020 + assign { } { } + assign $1\jtag_dmi0_ack_o[0:0] 1'0 + sync always + sync init + update \jtag_dmi0_ack_o $1\jtag_dmi0_ack_o[0:0] + end + attribute \src "libresoc.v:48632.14-48632.51" + process $proc$libresoc.v:48632$2021 + assign { } { } + assign $1\jtag_dmi0_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_dmi0_dout $1\jtag_dmi0_dout[63:0] + end + attribute \src "libresoc.v:48660.7-48660.22" + process $proc$libresoc.v:48660$2022 + assign { } { } + assign $1\msr_read[0:0] 1'1 + sync always + sync init + update \msr_read $1\msr_read[0:0] + end + attribute \src "libresoc.v:48672.7-48672.24" + process $proc$libresoc.v:48672$2023 + assign { } { } + assign $1\pc_changed[0:0] 1'0 + sync always + sync init + update \pc_changed $1\pc_changed[0:0] + end + attribute \src "libresoc.v:48682.7-48682.25" + process $proc$libresoc.v:48682$2024 + assign { } { } + assign $1\pc_ok_delay[0:0] 1'0 + sync always + sync init + update \pc_ok_delay $1\pc_ok_delay[0:0] + end + attribute \src "libresoc.v:48688.14-48688.32" + process $proc$libresoc.v:48688$2025 + assign { } { } + assign $1\raw_insn_i[31:0] 0 + sync always + sync init + update \raw_insn_i $1\raw_insn_i[31:0] + end + attribute \src "libresoc.v:48769.3-48770.39" + process $proc$libresoc.v:48769$1501 + assign { } { } + assign $0\d_reg_delay[0:0] \d_reg_delay$next + sync posedge \intclk_clk + update \d_reg_delay $0\d_reg_delay[0:0] + end + attribute \src "libresoc.v:48771.3-48772.29" + process $proc$libresoc.v:48771$1502 + assign { } { } + assign $0\ilatch[31:0] \ilatch$next + sync posedge \intclk_clk + update \ilatch $0\ilatch[31:0] + end + attribute \src "libresoc.v:48773.3-48774.31" + process $proc$libresoc.v:48773$1503 + assign { } { } + assign $0\core_pc[63:0] \core_pc$next + sync posedge \intclk_clk + update \core_pc $0\core_pc[63:0] + end + attribute \src "libresoc.v:48775.3-48776.33" + process $proc$libresoc.v:48775$1504 + assign { } { } + assign $0\core_msr[63:0] \core_msr$next + sync posedge \intclk_clk + update \core_msr $0\core_msr[63:0] + end + attribute \src "libresoc.v:48777.3-48778.35" + process $proc$libresoc.v:48777$1505 + assign { } { } + assign $0\core_eint[0:0] \core_eint$next + sync posedge \intclk_clk + update \core_eint $0\core_eint[0:0] + end + attribute \src "libresoc.v:48779.3-48780.33" + process $proc$libresoc.v:48779$1506 + assign { } { } + assign $0\core_dec[63:0] \core_dec$next + sync posedge \intclk_clk + update \core_dec $0\core_dec[63:0] + end + attribute \src "libresoc.v:48781.3-48782.41" + process $proc$libresoc.v:48781$1507 + assign { } { } + assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next + sync posedge \intclk_clk + update \dec2_cur_msr $0\dec2_cur_msr[63:0] + end + attribute \src "libresoc.v:48783.3-48784.35" + process $proc$libresoc.v:48783$1508 + assign { } { } + assign $0\fsm_state[1:0] \fsm_state$next + sync posedge \intclk_clk + update \fsm_state $0\fsm_state[1:0] + end + attribute \src "libresoc.v:48785.3-48786.33" + process $proc$libresoc.v:48785$1509 + assign { } { } + assign $0\msr_read[0:0] \msr_read$next + sync posedge \intclk_clk + update \msr_read $0\msr_read[0:0] + end + attribute \src "libresoc.v:48787.3-48788.39" + process $proc$libresoc.v:48787$1510 + assign { } { } + assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next + sync posedge \intclk_clk + update \dec2_cur_pc $0\dec2_cur_pc[63:0] + end + attribute \src "libresoc.v:48789.3-48790.39" + process $proc$libresoc.v:48789$1511 + assign { } { } + assign $0\bigendian_i[0:0] \bigendian_i$next + sync posedge \intclk_clk + update \bigendian_i $0\bigendian_i[0:0] + end + attribute \src "libresoc.v:48791.3-48792.37" + process $proc$libresoc.v:48791$1512 + assign { } { } + assign $0\raw_insn_i[31:0] \raw_insn_i$next + sync posedge \intclk_clk + update \raw_insn_i $0\raw_insn_i[31:0] + end + attribute \src "libresoc.v:48793.3-48794.41" + process $proc$libresoc.v:48793$1513 + assign { } { } + assign $0\core_asmcode[7:0] \core_asmcode$next + sync posedge \intclk_clk + update \core_asmcode $0\core_asmcode[7:0] + end + attribute \src "libresoc.v:48795.3-48796.35" + process $proc$libresoc.v:48795$1514 + assign { } { } + assign $0\core_rego[4:0] \core_rego$next + sync posedge \intclk_clk + update \core_rego $0\core_rego[4:0] + end + attribute \src "libresoc.v:48797.3-48798.41" + process $proc$libresoc.v:48797$1515 + assign { } { } + assign $0\core_rego_ok[0:0] \core_rego_ok$next + sync posedge \intclk_clk + update \core_rego_ok $0\core_rego_ok[0:0] + end + attribute \src "libresoc.v:48799.3-48800.31" + process $proc$libresoc.v:48799$1516 + assign { } { } + assign $0\core_ea[4:0] \core_ea$next + sync posedge \intclk_clk + update \core_ea $0\core_ea[4:0] + end + attribute \src "libresoc.v:48801.3-48802.37" + process $proc$libresoc.v:48801$1517 + assign { } { } + assign $0\core_ea_ok[0:0] \core_ea_ok$next + sync posedge \intclk_clk + update \core_ea_ok $0\core_ea_ok[0:0] + end + attribute \src "libresoc.v:48803.3-48804.35" + process $proc$libresoc.v:48803$1518 + assign { } { } + assign $0\core_reg1[4:0] \core_reg1$next + sync posedge \intclk_clk + update \core_reg1 $0\core_reg1[4:0] + end + attribute \src "libresoc.v:48805.3-48806.41" + process $proc$libresoc.v:48805$1519 + assign { } { } + assign $0\core_reg1_ok[0:0] \core_reg1_ok$next + sync posedge \intclk_clk + update \core_reg1_ok $0\core_reg1_ok[0:0] + end + attribute \src "libresoc.v:48807.3-48808.35" + process $proc$libresoc.v:48807$1520 + assign { } { } + assign $0\core_reg2[4:0] \core_reg2$next + sync posedge \intclk_clk + update \core_reg2 $0\core_reg2[4:0] + end + attribute \src "libresoc.v:48809.3-48810.41" + process $proc$libresoc.v:48809$1521 + assign { } { } + assign $0\core_reg2_ok[0:0] \core_reg2_ok$next + sync posedge \intclk_clk + update \core_reg2_ok $0\core_reg2_ok[0:0] + end + attribute \src "libresoc.v:48811.3-48812.35" + process $proc$libresoc.v:48811$1522 + assign { } { } + assign $0\core_reg3[4:0] \core_reg3$next + sync posedge \intclk_clk + update \core_reg3 $0\core_reg3[4:0] + end + attribute \src "libresoc.v:48813.3-48814.41" + process $proc$libresoc.v:48813$1523 + assign { } { } + assign $0\core_reg3_ok[0:0] \core_reg3_ok$next + sync posedge \intclk_clk + update \core_reg3_ok $0\core_reg3_ok[0:0] + end + attribute \src "libresoc.v:48815.3-48816.35" + process $proc$libresoc.v:48815$1524 + assign { } { } + assign $0\core_spro[9:0] \core_spro$next + sync posedge \intclk_clk + update \core_spro $0\core_spro[9:0] + end + attribute \src "libresoc.v:48817.3-48818.41" + process $proc$libresoc.v:48817$1525 + assign { } { } + assign $0\core_spro_ok[0:0] \core_spro_ok$next + sync posedge \intclk_clk + update \core_spro_ok $0\core_spro_ok[0:0] + end + attribute \src "libresoc.v:48819.3-48820.35" + process $proc$libresoc.v:48819$1526 + assign { } { } + assign $0\core_spr1[9:0] \core_spr1$next + sync posedge \intclk_clk + update \core_spr1 $0\core_spr1[9:0] + end + attribute \src "libresoc.v:48821.3-48822.41" + process $proc$libresoc.v:48821$1527 + assign { } { } + assign $0\core_spr1_ok[0:0] \core_spr1_ok$next + sync posedge \intclk_clk + update \core_spr1_ok $0\core_spr1_ok[0:0] + end + attribute \src "libresoc.v:48823.3-48824.39" + process $proc$libresoc.v:48823$1528 + assign { } { } + assign $0\core_xer_in[2:0] \core_xer_in$next + sync posedge \intclk_clk + update \core_xer_in $0\core_xer_in[2:0] + end + attribute \src "libresoc.v:48825.3-48826.41" + process $proc$libresoc.v:48825$1529 + assign { } { } + assign $0\core_xer_out[0:0] \core_xer_out$next + sync posedge \intclk_clk + update \core_xer_out $0\core_xer_out[0:0] + end + attribute \src "libresoc.v:48827.3-48828.37" + process $proc$libresoc.v:48827$1530 + assign { } { } + assign $0\core_fast1[2:0] \core_fast1$next + sync posedge \intclk_clk + update \core_fast1 $0\core_fast1[2:0] + end + attribute \src "libresoc.v:48829.3-48830.43" + process $proc$libresoc.v:48829$1531 + assign { } { } + assign $0\core_fast1_ok[0:0] \core_fast1_ok$next + sync posedge \intclk_clk + update \core_fast1_ok $0\core_fast1_ok[0:0] + end + attribute \src "libresoc.v:48831.3-48832.37" + process $proc$libresoc.v:48831$1532 + assign { } { } + assign $0\core_fast2[2:0] \core_fast2$next + sync posedge \intclk_clk + update \core_fast2 $0\core_fast2[2:0] + end + attribute \src "libresoc.v:48833.3-48834.43" + process $proc$libresoc.v:48833$1533 + assign { } { } + assign $0\core_fast2_ok[0:0] \core_fast2_ok$next + sync posedge \intclk_clk + update \core_fast2_ok $0\core_fast2_ok[0:0] + end + attribute \src "libresoc.v:48835.3-48836.39" + process $proc$libresoc.v:48835$1534 + assign { } { } + assign $0\core_fasto1[2:0] \core_fasto1$next + sync posedge \intclk_clk + update \core_fasto1 $0\core_fasto1[2:0] + end + attribute \src "libresoc.v:48837.3-48838.45" + process $proc$libresoc.v:48837$1535 + assign { } { } + assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next + sync posedge \intclk_clk + update \core_fasto1_ok $0\core_fasto1_ok[0:0] + end + attribute \src "libresoc.v:48839.3-48840.39" + process $proc$libresoc.v:48839$1536 + assign { } { } + assign $0\core_fasto2[2:0] \core_fasto2$next + sync posedge \intclk_clk + update \core_fasto2 $0\core_fasto2[2:0] + end + attribute \src "libresoc.v:48841.3-48842.45" + process $proc$libresoc.v:48841$1537 + assign { } { } + assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next + sync posedge \intclk_clk + update \core_fasto2_ok $0\core_fasto2_ok[0:0] + end + attribute \src "libresoc.v:48843.3-48844.39" + process $proc$libresoc.v:48843$1538 + assign { } { } + assign $0\core_cr_in1[2:0] \core_cr_in1$next + sync posedge \intclk_clk + update \core_cr_in1 $0\core_cr_in1[2:0] + end + attribute \src "libresoc.v:48845.3-48846.45" + process $proc$libresoc.v:48845$1539 + assign { } { } + assign $0\core_cr_in1_ok[0:0] \core_cr_in1_ok$next + sync posedge \intclk_clk + update \core_cr_in1_ok $0\core_cr_in1_ok[0:0] + end + attribute \src "libresoc.v:48847.3-48848.39" + process $proc$libresoc.v:48847$1540 + assign { } { } + assign $0\core_cr_in2[2:0] \core_cr_in2$next + sync posedge \intclk_clk + update \core_cr_in2 $0\core_cr_in2[2:0] + end + attribute \src "libresoc.v:48849.3-48850.45" + process $proc$libresoc.v:48849$1541 + assign { } { } + assign $0\core_cr_in2_ok[0:0] \core_cr_in2_ok$next + sync posedge \intclk_clk + update \core_cr_in2_ok $0\core_cr_in2_ok[0:0] + end + attribute \src "libresoc.v:48851.3-48852.47" + process $proc$libresoc.v:48851$1542 + assign { } { } + assign $0\core_cr_in2$39[2:0]$1543 \core_cr_in2$39$next + sync posedge \intclk_clk + update \core_cr_in2$39 $0\core_cr_in2$39[2:0]$1543 + end + attribute \src "libresoc.v:48853.3-48854.53" + process $proc$libresoc.v:48853$1544 + assign { } { } + assign $0\core_cr_in2_ok$40[0:0]$1545 \core_cr_in2_ok$40$next + sync posedge \intclk_clk + update \core_cr_in2_ok$40 $0\core_cr_in2_ok$40[0:0]$1545 + end + attribute \src "libresoc.v:48855.3-48856.39" + process $proc$libresoc.v:48855$1546 + assign { } { } + assign $0\core_cr_out[2:0] \core_cr_out$next + sync posedge \intclk_clk + update \core_cr_out $0\core_cr_out[2:0] + end + attribute \src "libresoc.v:48857.3-48858.45" + process $proc$libresoc.v:48857$1547 + assign { } { } + assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next + sync posedge \intclk_clk + update \core_cr_out_ok $0\core_cr_out_ok[0:0] + end + attribute \src "libresoc.v:48859.3-48860.43" + process $proc$libresoc.v:48859$1548 + assign { } { } + assign $0\core_core_msr[63:0] \core_core_msr$next + sync posedge \intclk_clk + update \core_core_msr $0\core_core_msr[63:0] + end + attribute \src "libresoc.v:48861.3-48862.43" + process $proc$libresoc.v:48861$1549 + assign { } { } + assign $0\core_core_cia[63:0] \core_core_cia$next + sync posedge \intclk_clk + update \core_core_cia $0\core_core_cia[63:0] + end + attribute \src "libresoc.v:48863.3-48864.45" + process $proc$libresoc.v:48863$1550 + assign { } { } + assign $0\core_core_insn[31:0] \core_core_insn$next + sync posedge \intclk_clk + update \core_core_insn $0\core_core_insn[31:0] + end + attribute \src "libresoc.v:48865.3-48866.55" + process $proc$libresoc.v:48865$1551 + assign { } { } + assign $0\core_core_insn_type[6:0] \core_core_insn_type$next + sync posedge \intclk_clk + update \core_core_insn_type $0\core_core_insn_type[6:0] + end + attribute \src "libresoc.v:48867.3-48868.51" + process $proc$libresoc.v:48867$1552 + assign { } { } + assign $0\core_core_fn_unit[11:0] \core_core_fn_unit$next + sync posedge \intclk_clk + update \core_core_fn_unit $0\core_core_fn_unit[11:0] + end + attribute \src "libresoc.v:48869.3-48870.41" + process $proc$libresoc.v:48869$1553 + assign { } { } + assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next + sync posedge \intclk_clk + update \dec2_cur_dec $0\dec2_cur_dec[63:0] + end + attribute \src "libresoc.v:48871.3-48872.41" + process $proc$libresoc.v:48871$1554 + assign { } { } + assign $0\core_core_lk[0:0] \core_core_lk$next + sync posedge \intclk_clk + update \core_core_lk $0\core_core_lk[0:0] + end + attribute \src "libresoc.v:48873.3-48874.41" + process $proc$libresoc.v:48873$1555 + assign { } { } + assign $0\core_core_rc[0:0] \core_core_rc$next + sync posedge \intclk_clk + update \core_core_rc $0\core_core_rc[0:0] + end + attribute \src "libresoc.v:48875.3-48876.47" + process $proc$libresoc.v:48875$1556 + assign { } { } + assign $0\core_core_rc_ok[0:0] \core_core_rc_ok$next + sync posedge \intclk_clk + update \core_core_rc_ok $0\core_core_rc_ok[0:0] + end + attribute \src "libresoc.v:48877.3-48878.41" + process $proc$libresoc.v:48877$1557 + assign { } { } + assign $0\core_core_oe[0:0] \core_core_oe$next + sync posedge \intclk_clk + update \core_core_oe $0\core_core_oe[0:0] + end + attribute \src "libresoc.v:48879.3-48880.47" + process $proc$libresoc.v:48879$1558 + assign { } { } + assign $0\core_core_oe_ok[0:0] \core_core_oe_ok$next + sync posedge \intclk_clk + update \core_core_oe_ok $0\core_core_oe_ok[0:0] + end + attribute \src "libresoc.v:48881.3-48882.59" + process $proc$libresoc.v:48881$1559 + assign { } { } + assign $0\core_core_input_carry[1:0] \core_core_input_carry$next + sync posedge \intclk_clk + update \core_core_input_carry $0\core_core_input_carry[1:0] + end + attribute \src "libresoc.v:48883.3-48884.53" + process $proc$libresoc.v:48883$1560 + assign { } { } + assign $0\core_core_traptype[6:0] \core_core_traptype$next + sync posedge \intclk_clk + update \core_core_traptype $0\core_core_traptype[6:0] + end + attribute \src "libresoc.v:48885.3-48886.53" + process $proc$libresoc.v:48885$1561 + assign { } { } + assign $0\core_core_trapaddr[12:0] \core_core_trapaddr$next + sync posedge \intclk_clk + update \core_core_trapaddr $0\core_core_trapaddr[12:0] + end + attribute \src "libresoc.v:48887.3-48888.47" + process $proc$libresoc.v:48887$1562 + assign { } { } + assign $0\core_core_cr_rd[7:0] \core_core_cr_rd$next + sync posedge \intclk_clk + update \core_core_cr_rd $0\core_core_cr_rd[7:0] + end + attribute \src "libresoc.v:48889.3-48890.53" + process $proc$libresoc.v:48889$1563 + assign { } { } + assign $0\core_core_cr_rd_ok[0:0] \core_core_cr_rd_ok$next + sync posedge \intclk_clk + update \core_core_cr_rd_ok $0\core_core_cr_rd_ok[0:0] + end + attribute \src "libresoc.v:48891.3-48892.45" + process $proc$libresoc.v:48891$1564 + assign { } { } + assign $0\fsm_state$115[1:0]$1565 \fsm_state$115$next + sync posedge \intclk_clk + update \fsm_state$115 $0\fsm_state$115[1:0]$1565 + end + attribute \src "libresoc.v:48893.3-48894.47" + process $proc$libresoc.v:48893$1566 + assign { } { } + assign $0\core_core_cr_wr[7:0] \core_core_cr_wr$next + sync posedge \intclk_clk + update \core_core_cr_wr $0\core_core_cr_wr[7:0] + end + attribute \src "libresoc.v:48895.3-48896.53" + process $proc$libresoc.v:48895$1567 + assign { } { } + assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next + sync posedge \intclk_clk + update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] + end + attribute \src "libresoc.v:48897.3-48898.53" + process $proc$libresoc.v:48897$1568 + assign { } { } + assign $0\core_core_is_32bit[0:0] \core_core_is_32bit$next + sync posedge \intclk_clk + update \core_core_is_32bit $0\core_core_is_32bit[0:0] + end + attribute \src "libresoc.v:48899.3-48900.37" + process $proc$libresoc.v:48899$1569 + assign { } { } + assign $0\pc_changed[0:0] \pc_changed$next + sync posedge \intclk_clk + update \pc_changed $0\pc_changed[0:0] + end + attribute \src "libresoc.v:48901.3-48902.39" + process $proc$libresoc.v:48901$1570 + assign { } { } + assign $0\pc_ok_delay[0:0] \pc_ok_delay$next + sync posedge \intclk_clk + update \pc_ok_delay $0\pc_ok_delay[0:0] + end + attribute \src "libresoc.v:48903.3-48904.30" + process $proc$libresoc.v:48903$1571 + assign { } { } + assign $0\cu_st__rel_o_dly[0:0] 1'0 + sync posedge \intclk_clk + update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] + end + attribute \src "libresoc.v:48905.3-48906.27" + process $proc$libresoc.v:48905$1572 + assign { } { } + assign $0\delay[1:0] \delay$next + sync posedge \por_clk + update \delay $0\delay[1:0] + end + attribute \src "libresoc.v:48907.3-48908.43" + process $proc$libresoc.v:48907$1573 + assign { } { } + assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next + sync posedge \intclk_clk + update \dec2_cur_eint $0\dec2_cur_eint[0:0] + end + attribute \src "libresoc.v:48909.3-48910.45" + process $proc$libresoc.v:48909$1574 + assign { } { } + assign $0\jtag_dmi0_dout[63:0] \jtag_dmi0_dout$next + sync posedge \intclk_clk + update \jtag_dmi0_dout $0\jtag_dmi0_dout[63:0] + end + attribute \src "libresoc.v:48911.3-48912.47" + process $proc$libresoc.v:48911$1575 + assign { } { } + assign $0\jtag_dmi0_ack_o[0:0] \jtag_dmi0_ack_o$next + sync posedge \intclk_clk + update \jtag_dmi0_ack_o $0\jtag_dmi0_ack_o[0:0] + end + attribute \src "libresoc.v:48913.3-48914.39" + process $proc$libresoc.v:48913$1576 + assign { } { } + assign $0\d_xer_delay[0:0] \d_xer_delay$next + sync posedge \intclk_clk + update \d_xer_delay $0\d_xer_delay[0:0] + end + attribute \src "libresoc.v:48915.3-48916.39" + process $proc$libresoc.v:48915$1577 + assign { } { } + assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next + sync posedge \intclk_clk + update \dbg_dmi_din $0\dbg_dmi_din[63:0] + end + attribute \src "libresoc.v:48917.3-48918.41" + process $proc$libresoc.v:48917$1578 + assign { } { } + assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next + sync posedge \intclk_clk + update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] + end + attribute \src "libresoc.v:48919.3-48920.43" + process $proc$libresoc.v:48919$1579 + assign { } { } + assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next + sync posedge \intclk_clk + update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] + end + attribute \src "libresoc.v:48921.3-48922.45" + process $proc$libresoc.v:48921$1580 + assign { } { } + assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next + sync posedge \intclk_clk + update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] + end + attribute \src "libresoc.v:48923.3-48924.37" + process $proc$libresoc.v:48923$1581 + assign { } { } + assign $0\d_cr_delay[0:0] \d_cr_delay$next + sync posedge \intclk_clk + update \d_cr_delay $0\d_cr_delay[0:0] + end + attribute \src "libresoc.v:49177.3-49185.6" + process $proc$libresoc.v:49177$1582 + assign { } { } + assign { } { } + assign $0\dbg_dmi_addr_i$next[3:0]$1583 $1\dbg_dmi_addr_i$next[3:0]$1584 + attribute \src "libresoc.v:49178.5-49178.29" + switch \initial + attribute \src "libresoc.v:49178.9-49178.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_addr_i$next[3:0]$1584 4'0000 + case + assign $1\dbg_dmi_addr_i$next[3:0]$1584 \jtag_dmi0_addr_i + end + sync always + update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$1583 + end + attribute \src "libresoc.v:49186.3-49194.6" + process $proc$libresoc.v:49186$1585 + assign { } { } + assign { } { } + assign $0\dbg_dmi_req_i$next[0:0]$1586 $1\dbg_dmi_req_i$next[0:0]$1587 + attribute \src "libresoc.v:49187.5-49187.29" + switch \initial + attribute \src "libresoc.v:49187.9-49187.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_req_i$next[0:0]$1587 1'0 + case + assign $1\dbg_dmi_req_i$next[0:0]$1587 \jtag_dmi0_req_i + end + sync always + update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$1586 + end + attribute \src "libresoc.v:49195.3-49205.6" + process $proc$libresoc.v:49195$1588 + assign { } { } + assign { } { } + assign $0\issue_i[0:0] $1\issue_i[0:0] + attribute \src "libresoc.v:49196.5-49196.29" + switch \initial + attribute \src "libresoc.v:49196.9-49196.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\issue_i[0:0] 1'1 + case + assign $1\issue_i[0:0] 1'0 + end + sync always + update \issue_i $0\issue_i[0:0] + end + attribute \src "libresoc.v:49206.3-49215.6" + process $proc$libresoc.v:49206$1589 + assign { } { } + assign { } { } + assign $0\dmi__addr[4:0] $1\dmi__addr[4:0] + attribute \src "libresoc.v:49207.5-49207.29" + switch \initial + attribute \src "libresoc.v:49207.9-49207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" + switch \dbg_d_gpr_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi__addr[4:0] \dbg_d_gpr_addr [4:0] + case + assign $1\dmi__addr[4:0] 5'00000 + end + sync always + update \dmi__addr $0\dmi__addr[4:0] + end + attribute \src "libresoc.v:49216.3-49225.6" + process $proc$libresoc.v:49216$1590 + assign { } { } + assign { } { } + assign $0\dmi__ren[0:0] $1\dmi__ren[0:0] + attribute \src "libresoc.v:49217.5-49217.29" + switch \initial + attribute \src "libresoc.v:49217.9-49217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" + switch \dbg_d_gpr_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi__ren[0:0] 1'1 + case + assign $1\dmi__ren[0:0] 1'0 + end + sync always + update \dmi__ren $0\dmi__ren[0:0] + end + attribute \src "libresoc.v:49226.3-49234.6" + process $proc$libresoc.v:49226$1591 + assign { } { } + assign { } { } + assign $0\d_reg_delay$next[0:0]$1592 $1\d_reg_delay$next[0:0]$1593 + attribute \src "libresoc.v:49227.5-49227.29" + switch \initial + attribute \src "libresoc.v:49227.9-49227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d_reg_delay$next[0:0]$1593 1'0 + case + assign $1\d_reg_delay$next[0:0]$1593 \dbg_d_gpr_req + end + sync always + update \d_reg_delay$next $0\d_reg_delay$next[0:0]$1592 + end + attribute \src "libresoc.v:49235.3-49244.6" + process $proc$libresoc.v:49235$1594 + assign { } { } + assign { } { } + assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:49236.5-49236.29" + switch \initial + attribute \src "libresoc.v:49236.9-49236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" + switch \d_reg_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_gpr_data[63:0] \dmi__data_o + case + assign $1\dbg_d_gpr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] + end + attribute \src "libresoc.v:49245.3-49254.6" + process $proc$libresoc.v:49245$1595 + assign { } { } + assign { } { } + assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:49246.5-49246.29" + switch \initial + attribute \src "libresoc.v:49246.9-49246.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" + switch \d_reg_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_gpr_ack[0:0] 1'1 + case + assign $1\dbg_d_gpr_ack[0:0] 1'0 + end + sync always + update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] + end + attribute \src "libresoc.v:49255.3-49264.6" + process $proc$libresoc.v:49255$1596 + assign { } { } + assign { } { } + assign $0\full_rd2__ren[7:0] $1\full_rd2__ren[7:0] + attribute \src "libresoc.v:49256.5-49256.29" + switch \initial + attribute \src "libresoc.v:49256.9-49256.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" + switch \dbg_d_cr_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\full_rd2__ren[7:0] 8'11111111 + case + assign $1\full_rd2__ren[7:0] 8'00000000 + end + sync always + update \full_rd2__ren $0\full_rd2__ren[7:0] + end + attribute \src "libresoc.v:49265.3-49273.6" + process $proc$libresoc.v:49265$1597 + assign { } { } + assign { } { } + assign $0\d_cr_delay$next[0:0]$1598 $1\d_cr_delay$next[0:0]$1599 + attribute \src "libresoc.v:49266.5-49266.29" + switch \initial + attribute \src "libresoc.v:49266.9-49266.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d_cr_delay$next[0:0]$1599 1'0 + case + assign $1\d_cr_delay$next[0:0]$1599 \dbg_d_cr_req + end + sync always + update \d_cr_delay$next $0\d_cr_delay$next[0:0]$1598 + end + attribute \src "libresoc.v:49274.3-49283.6" + process $proc$libresoc.v:49274$1600 + assign { } { } + assign { } { } + assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:49275.5-49275.29" + switch \initial + attribute \src "libresoc.v:49275.9-49275.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + switch \d_cr_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_cr_data[63:0] \$111 + case + assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] + end + attribute \src "libresoc.v:49284.3-49293.6" + process $proc$libresoc.v:49284$1601 + assign { } { } + assign { } { } + assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:49285.5-49285.29" + switch \initial + attribute \src "libresoc.v:49285.9-49285.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + switch \d_cr_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_cr_ack[0:0] 1'1 + case + assign $1\dbg_d_cr_ack[0:0] 1'0 + end + sync always + update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] + end + attribute \src "libresoc.v:49294.3-49303.6" + process $proc$libresoc.v:49294$1602 + assign { } { } + assign { } { } + assign $0\full_rd__ren[2:0] $1\full_rd__ren[2:0] + attribute \src "libresoc.v:49295.5-49295.29" + switch \initial + attribute \src "libresoc.v:49295.9-49295.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:333" + switch \dbg_d_xer_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\full_rd__ren[2:0] 3'111 + case + assign $1\full_rd__ren[2:0] 3'000 + end + sync always + update \full_rd__ren $0\full_rd__ren[2:0] + end + attribute \src "libresoc.v:49304.3-49312.6" + process $proc$libresoc.v:49304$1603 + assign { } { } + assign { } { } + assign $0\d_xer_delay$next[0:0]$1604 $1\d_xer_delay$next[0:0]$1605 + attribute \src "libresoc.v:49305.5-49305.29" + switch \initial + attribute \src "libresoc.v:49305.9-49305.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d_xer_delay$next[0:0]$1605 1'0 + case + assign $1\d_xer_delay$next[0:0]$1605 \dbg_d_xer_req + end + sync always + update \d_xer_delay$next $0\d_xer_delay$next[0:0]$1604 + end + attribute \src "libresoc.v:49313.3-49322.6" + process $proc$libresoc.v:49313$1606 + assign { } { } + assign { } { } + assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:49314.5-49314.29" + switch \initial + attribute \src "libresoc.v:49314.9-49314.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + switch \d_xer_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_xer_data[63:0] \$113 + case + assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] + end + attribute \src "libresoc.v:49323.3-49332.6" + process $proc$libresoc.v:49323$1607 + assign { } { } + assign { } { } + assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:49324.5-49324.29" + switch \initial + attribute \src "libresoc.v:49324.9-49324.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:337" + switch \d_xer_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_xer_ack[0:0] 1'1 + case + assign $1\dbg_d_xer_ack[0:0] 1'0 + end + sync always + update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] + end + attribute \src "libresoc.v:49333.3-49347.6" + process $proc$libresoc.v:49333$1608 + assign { } { } + assign { } { } + assign $0\issue__addr[2:0] $1\issue__addr[2:0] + attribute \src "libresoc.v:49334.5-49334.29" + switch \initial + attribute \src "libresoc.v:49334.9-49334.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" + switch \fsm_state$115 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\issue__addr[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\issue__addr[2:0] 3'111 + case + assign $1\issue__addr[2:0] 3'000 + end + sync always + update \issue__addr $0\issue__addr[2:0] + end + attribute \src "libresoc.v:49348.3-49362.6" + process $proc$libresoc.v:49348$1609 + assign { } { } + assign { } { } + assign $0\issue__ren[0:0] $1\issue__ren[0:0] + attribute \src "libresoc.v:49349.5-49349.29" + switch \initial + attribute \src "libresoc.v:49349.9-49349.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" + switch \fsm_state$115 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\issue__ren[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\issue__ren[0:0] 1'1 + case + assign $1\issue__ren[0:0] 1'0 + end + sync always + update \issue__ren $0\issue__ren[0:0] + end + attribute \src "libresoc.v:49363.3-49390.6" + process $proc$libresoc.v:49363$1610 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$115$next[1:0]$1611 $2\fsm_state$115$next[1:0]$1613 + attribute \src "libresoc.v:49364.5-49364.29" + switch \initial + attribute \src "libresoc.v:49364.9-49364.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" + switch \fsm_state$115 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$115$next[1:0]$1612 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fsm_state$115$next[1:0]$1612 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$115$next[1:0]$1612 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\fsm_state$115$next[1:0]$1612 2'00 + case + assign $1\fsm_state$115$next[1:0]$1612 \fsm_state$115 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$115$next[1:0]$1613 2'00 + case + assign $2\fsm_state$115$next[1:0]$1613 $1\fsm_state$115$next[1:0]$1612 + end + sync always + update \fsm_state$115$next $0\fsm_state$115$next[1:0]$1611 + end + attribute \src "libresoc.v:49391.3-49401.6" + process $proc$libresoc.v:49391$1614 + assign { } { } + assign { } { } + assign $0\new_dec[63:0] $1\new_dec[63:0] + attribute \src "libresoc.v:49392.5-49392.29" + switch \initial + attribute \src "libresoc.v:49392.9-49392.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" + switch \fsm_state$115 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\new_dec[63:0] \$116 [63:0] + case + assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \new_dec $0\new_dec[63:0] + end + attribute \src "libresoc.v:49402.3-49416.6" + process $proc$libresoc.v:49402$1615 + assign { } { } + assign { } { } + assign $0\issue__addr$119[2:0]$1616 $1\issue__addr$119[2:0]$1617 + attribute \src "libresoc.v:49403.5-49403.29" + switch \initial + attribute \src "libresoc.v:49403.9-49403.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" + switch \fsm_state$115 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\issue__addr$119[2:0]$1617 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\issue__addr$119[2:0]$1617 3'111 + case + assign $1\issue__addr$119[2:0]$1617 3'000 + end + sync always + update \issue__addr$119 $0\issue__addr$119[2:0]$1616 + end + attribute \src "libresoc.v:49417.3-49431.6" + process $proc$libresoc.v:49417$1618 + assign { } { } + assign { } { } + assign $0\issue__wen[0:0] $1\issue__wen[0:0] + attribute \src "libresoc.v:49418.5-49418.29" + switch \initial + attribute \src "libresoc.v:49418.9-49418.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" + switch \fsm_state$115 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\issue__wen[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\issue__wen[0:0] 1'1 + case + assign $1\issue__wen[0:0] 1'0 + end + sync always + update \issue__wen $0\issue__wen[0:0] + end + attribute \src "libresoc.v:49432.3-49446.6" + process $proc$libresoc.v:49432$1619 + assign { } { } + assign { } { } + assign $0\issue__data_i[63:0] $1\issue__data_i[63:0] + attribute \src "libresoc.v:49433.5-49433.29" + switch \initial + attribute \src "libresoc.v:49433.9-49433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" + switch \fsm_state$115 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\issue__data_i[63:0] \new_dec + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\issue__data_i[63:0] \new_tb + case + assign $1\issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \issue__data_i $0\issue__data_i[63:0] + end + attribute \src "libresoc.v:49447.3-49462.6" + process $proc$libresoc.v:49447$1620 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_dec$next[63:0]$1621 $2\dec2_cur_dec$next[63:0]$1623 + attribute \src "libresoc.v:49448.5-49448.29" + switch \initial + attribute \src "libresoc.v:49448.9-49448.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" + switch \fsm_state$115 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_cur_dec$next[63:0]$1622 \new_dec + case + assign $1\dec2_cur_dec$next[63:0]$1622 \dec2_cur_dec + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_dec$next[63:0]$1623 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\dec2_cur_dec$next[63:0]$1623 $1\dec2_cur_dec$next[63:0]$1622 + end + sync always + update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$1621 + end + attribute \src "libresoc.v:49463.3-49473.6" + process $proc$libresoc.v:49463$1624 + assign { } { } + assign { } { } + assign $0\new_tb[63:0] $1\new_tb[63:0] + attribute \src "libresoc.v:49464.5-49464.29" + switch \initial + attribute \src "libresoc.v:49464.9-49464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" + switch \fsm_state$115 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\new_tb[63:0] \$120 [63:0] + case + assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \new_tb $0\new_tb[63:0] + end + attribute \src "libresoc.v:49474.3-49482.6" + process $proc$libresoc.v:49474$1625 + assign { } { } + assign { } { } + assign $0\dbg_dmi_we_i$next[0:0]$1626 $1\dbg_dmi_we_i$next[0:0]$1627 + attribute \src "libresoc.v:49475.5-49475.29" + switch \initial + attribute \src "libresoc.v:49475.9-49475.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_we_i$next[0:0]$1627 1'0 + case + assign $1\dbg_dmi_we_i$next[0:0]$1627 \jtag_dmi0_we_i + end + sync always + update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$1626 + end + attribute \src "libresoc.v:49483.3-49491.6" + process $proc$libresoc.v:49483$1628 + assign { } { } + assign { } { } + assign $0\pc_ok_delay$next[0:0]$1629 $1\pc_ok_delay$next[0:0]$1630 + attribute \src "libresoc.v:49484.5-49484.29" + switch \initial + attribute \src "libresoc.v:49484.9-49484.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pc_ok_delay$next[0:0]$1630 1'0 + case + assign $1\pc_ok_delay$next[0:0]$1630 \$19 + end + sync always + update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$1629 + end + attribute \src "libresoc.v:49492.3-49507.6" + process $proc$libresoc.v:49492$1631 + assign { } { } + assign { } { } + assign { } { } + assign $0\pc[63:0] $2\pc[63:0] + attribute \src "libresoc.v:49493.5-49493.29" + switch \initial + attribute \src "libresoc.v:49493.9-49493.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:189" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pc[63:0] \pc_i + case + assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:196" + switch \pc_ok_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\pc[63:0] \cia__data_o + case + assign $2\pc[63:0] $1\pc[63:0] + end + sync always + update \pc $0\pc[63:0] + end + attribute \src "libresoc.v:49508.3-49520.6" + process $proc$libresoc.v:49508$1632 + assign { } { } + assign { } { } + assign $0\cia__ren[3:0] $1\cia__ren[3:0] + attribute \src "libresoc.v:49509.5-49509.29" + switch \initial + attribute \src "libresoc.v:49509.9-49509.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:189" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\cia__ren[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cia__ren[3:0] 4'0001 + end + sync always + update \cia__ren $0\cia__ren[3:0] + end + attribute \src "libresoc.v:49521.3-49541.6" + process $proc$libresoc.v:49521$1633 + assign { } { } + assign { } { } + assign $0\wen[3:0] $1\wen[3:0] + attribute \src "libresoc.v:49522.5-49522.29" + switch \initial + attribute \src "libresoc.v:49522.9-49522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\wen[3:0] $2\wen[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wen[3:0] $3\wen[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wen[3:0] 4'0001 + case + assign $3\wen[3:0] 4'0000 + end + case + assign $2\wen[3:0] 4'0000 + end + case + assign $1\wen[3:0] 4'0000 + end + sync always + update \wen $0\wen[3:0] + end + attribute \src "libresoc.v:49542.3-49562.6" + process $proc$libresoc.v:49542$1634 + assign { } { } + assign { } { } + assign $0\data_i[63:0] $1\data_i[63:0] + attribute \src "libresoc.v:49543.5-49543.29" + switch \initial + attribute \src "libresoc.v:49543.9-49543.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\data_i[63:0] $2\data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\data_i[63:0] $3\data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_i[63:0] \nia + case + assign $3\data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $2\data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \data_i $0\data_i[63:0] + end + attribute \src "libresoc.v:49563.3-49578.6" + process $proc$libresoc.v:49563$1635 + assign { } { } + assign { } { } + assign $0\msr__ren[3:0] $1\msr__ren[3:0] + attribute \src "libresoc.v:49564.5-49564.29" + switch \initial + attribute \src "libresoc.v:49564.9-49564.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\msr__ren[3:0] $2\msr__ren[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr__ren[3:0] 4'0010 + case + assign $2\msr__ren[3:0] 4'0000 + end + case + assign $1\msr__ren[3:0] 4'0000 + end + sync always + update \msr__ren $0\msr__ren[3:0] + end + attribute \src "libresoc.v:49579.3-49587.6" + process $proc$libresoc.v:49579$1636 + assign { } { } + assign { } { } + assign $0\dbg_dmi_din$next[63:0]$1637 $1\dbg_dmi_din$next[63:0]$1638 + attribute \src "libresoc.v:49580.5-49580.29" + switch \initial + attribute \src "libresoc.v:49580.9-49580.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_din$next[63:0]$1638 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\dbg_dmi_din$next[63:0]$1638 \jtag_dmi0_din + end + sync always + update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$1637 + end + attribute \src "libresoc.v:49588.3-49612.6" + process $proc$libresoc.v:49588$1639 + assign { } { } + assign { } { } + assign { } { } + assign $0\pc_changed$next[0:0]$1640 $3\pc_changed$next[0:0]$1643 + attribute \src "libresoc.v:49589.5-49589.29" + switch \initial + attribute \src "libresoc.v:49589.9-49589.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\pc_changed$next[0:0]$1641 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\pc_changed$next[0:0]$1641 $2\pc_changed$next[0:0]$1642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + switch \$35 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\pc_changed$next[0:0]$1642 1'1 + case + assign $2\pc_changed$next[0:0]$1642 \pc_changed + end + case + assign $1\pc_changed$next[0:0]$1641 \pc_changed + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\pc_changed$next[0:0]$1643 1'0 + case + assign $3\pc_changed$next[0:0]$1643 $1\pc_changed$next[0:0]$1641 + end + sync always + update \pc_changed$next $0\pc_changed$next[0:0]$1640 + end + attribute \src "libresoc.v:49613.3-49719.6" + process $proc$libresoc.v:49613$1644 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_asmcode$next[7:0]$1645 $1\core_asmcode$next[7:0]$1696 + assign $0\core_core_cia$next[63:0]$1646 $1\core_core_cia$next[63:0]$1697 + assign $0\core_core_cr_rd$next[7:0]$1647 $1\core_core_cr_rd$next[7:0]$1698 + assign { } { } + assign $0\core_core_cr_wr$next[7:0]$1649 $1\core_core_cr_wr$next[7:0]$1700 + assign { } { } + assign $0\core_core_fn_unit$next[11:0]$1651 $1\core_core_fn_unit$next[11:0]$1702 + assign $0\core_core_input_carry$next[1:0]$1652 $1\core_core_input_carry$next[1:0]$1703 + assign $0\core_core_insn$next[31:0]$1653 $1\core_core_insn$next[31:0]$1704 + assign $0\core_core_insn_type$next[6:0]$1654 $1\core_core_insn_type$next[6:0]$1705 + assign $0\core_core_is_32bit$next[0:0]$1655 $1\core_core_is_32bit$next[0:0]$1706 + assign $0\core_core_lk$next[0:0]$1656 $1\core_core_lk$next[0:0]$1707 + assign $0\core_core_msr$next[63:0]$1657 $1\core_core_msr$next[63:0]$1708 + assign $0\core_core_oe$next[0:0]$1658 $1\core_core_oe$next[0:0]$1709 + assign { } { } + assign $0\core_core_rc$next[0:0]$1660 $1\core_core_rc$next[0:0]$1711 + assign { } { } + assign $0\core_core_trapaddr$next[12:0]$1662 $1\core_core_trapaddr$next[12:0]$1713 + assign $0\core_core_traptype$next[6:0]$1663 $1\core_core_traptype$next[6:0]$1714 + assign $0\core_cr_in1$next[2:0]$1664 $1\core_cr_in1$next[2:0]$1715 + assign { } { } + assign $0\core_cr_in2$39$next[2:0]$1666 $1\core_cr_in2$39$next[2:0]$1717 + assign $0\core_cr_in2$next[2:0]$1667 $1\core_cr_in2$next[2:0]$1718 + assign { } { } + assign { } { } + assign $0\core_cr_out$next[2:0]$1670 $1\core_cr_out$next[2:0]$1721 + assign { } { } + assign $0\core_ea$next[4:0]$1672 $1\core_ea$next[4:0]$1723 + assign { } { } + assign $0\core_fast1$next[2:0]$1674 $1\core_fast1$next[2:0]$1725 + assign { } { } + assign $0\core_fast2$next[2:0]$1676 $1\core_fast2$next[2:0]$1727 + assign { } { } + assign $0\core_fasto1$next[2:0]$1678 $1\core_fasto1$next[2:0]$1729 + assign { } { } + assign $0\core_fasto2$next[2:0]$1680 $1\core_fasto2$next[2:0]$1731 + assign { } { } + assign $0\core_reg1$next[4:0]$1682 $1\core_reg1$next[4:0]$1733 + assign { } { } + assign $0\core_reg2$next[4:0]$1684 $1\core_reg2$next[4:0]$1735 + assign { } { } + assign $0\core_reg3$next[4:0]$1686 $1\core_reg3$next[4:0]$1737 + assign { } { } + assign $0\core_rego$next[4:0]$1688 $1\core_rego$next[4:0]$1739 + assign { } { } + assign $0\core_spr1$next[9:0]$1690 $1\core_spr1$next[9:0]$1741 + assign { } { } + assign $0\core_spro$next[9:0]$1692 $1\core_spro$next[9:0]$1743 + assign { } { } + assign $0\core_xer_in$next[2:0]$1694 $1\core_xer_in$next[2:0]$1745 + assign $0\core_xer_out$next[0:0]$1695 $1\core_xer_out$next[0:0]$1746 + assign $0\core_core_cr_rd_ok$next[0:0]$1648 $4\core_core_cr_rd_ok$next[0:0]$1849 + assign $0\core_core_cr_wr_ok$next[0:0]$1650 $4\core_core_cr_wr_ok$next[0:0]$1850 + assign $0\core_core_oe_ok$next[0:0]$1659 $4\core_core_oe_ok$next[0:0]$1851 + assign $0\core_core_rc_ok$next[0:0]$1661 $4\core_core_rc_ok$next[0:0]$1852 + assign $0\core_cr_in1_ok$next[0:0]$1665 $4\core_cr_in1_ok$next[0:0]$1853 + assign $0\core_cr_in2_ok$40$next[0:0]$1668 $4\core_cr_in2_ok$40$next[0:0]$1854 + assign $0\core_cr_in2_ok$next[0:0]$1669 $4\core_cr_in2_ok$next[0:0]$1855 + assign $0\core_cr_out_ok$next[0:0]$1671 $4\core_cr_out_ok$next[0:0]$1856 + assign $0\core_ea_ok$next[0:0]$1673 $4\core_ea_ok$next[0:0]$1857 + assign $0\core_fast1_ok$next[0:0]$1675 $4\core_fast1_ok$next[0:0]$1858 + assign $0\core_fast2_ok$next[0:0]$1677 $4\core_fast2_ok$next[0:0]$1859 + assign $0\core_fasto1_ok$next[0:0]$1679 $4\core_fasto1_ok$next[0:0]$1860 + assign $0\core_fasto2_ok$next[0:0]$1681 $4\core_fasto2_ok$next[0:0]$1861 + assign $0\core_reg1_ok$next[0:0]$1683 $4\core_reg1_ok$next[0:0]$1862 + assign $0\core_reg2_ok$next[0:0]$1685 $4\core_reg2_ok$next[0:0]$1863 + assign $0\core_reg3_ok$next[0:0]$1687 $4\core_reg3_ok$next[0:0]$1864 + assign $0\core_rego_ok$next[0:0]$1689 $4\core_rego_ok$next[0:0]$1865 + assign $0\core_spr1_ok$next[0:0]$1691 $4\core_spr1_ok$next[0:0]$1866 + assign $0\core_spro_ok$next[0:0]$1693 $4\core_spro_ok$next[0:0]$1867 + attribute \src "libresoc.v:49614.5-49614.29" + switch \initial + attribute \src "libresoc.v:49614.9-49614.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\core_core_is_32bit$next[0:0]$1706 $1\core_core_cr_wr_ok$next[0:0]$1701 $1\core_core_cr_wr$next[7:0]$1700 $1\core_core_cr_rd_ok$next[0:0]$1699 $1\core_core_cr_rd$next[7:0]$1698 $1\core_core_trapaddr$next[12:0]$1713 $1\core_core_traptype$next[6:0]$1714 $1\core_core_input_carry$next[1:0]$1703 $1\core_core_oe_ok$next[0:0]$1710 $1\core_core_oe$next[0:0]$1709 $1\core_core_rc_ok$next[0:0]$1712 $1\core_core_rc$next[0:0]$1711 $1\core_core_lk$next[0:0]$1707 $1\core_core_fn_unit$next[11:0]$1702 $1\core_core_insn_type$next[6:0]$1705 $1\core_core_insn$next[31:0]$1704 $1\core_core_cia$next[63:0]$1697 $1\core_core_msr$next[63:0]$1708 $1\core_cr_out_ok$next[0:0]$1722 $1\core_cr_out$next[2:0]$1721 $1\core_cr_in2_ok$40$next[0:0]$1719 $1\core_cr_in2$39$next[2:0]$1717 $1\core_cr_in2_ok$next[0:0]$1720 $1\core_cr_in2$next[2:0]$1718 $1\core_cr_in1_ok$next[0:0]$1716 $1\core_cr_in1$next[2:0]$1715 $1\core_fasto2_ok$next[0:0]$1732 $1\core_fasto2$next[2:0]$1731 $1\core_fasto1_ok$next[0:0]$1730 $1\core_fasto1$next[2:0]$1729 $1\core_fast2_ok$next[0:0]$1728 $1\core_fast2$next[2:0]$1727 $1\core_fast1_ok$next[0:0]$1726 $1\core_fast1$next[2:0]$1725 $1\core_xer_out$next[0:0]$1746 $1\core_xer_in$next[2:0]$1745 $1\core_spr1_ok$next[0:0]$1742 $1\core_spr1$next[9:0]$1741 $1\core_spro_ok$next[0:0]$1744 $1\core_spro$next[9:0]$1743 $1\core_reg3_ok$next[0:0]$1738 $1\core_reg3$next[4:0]$1737 $1\core_reg2_ok$next[0:0]$1736 $1\core_reg2$next[4:0]$1735 $1\core_reg1_ok$next[0:0]$1734 $1\core_reg1$next[4:0]$1733 $1\core_ea_ok$next[0:0]$1724 $1\core_ea$next[4:0]$1723 $1\core_rego_ok$next[0:0]$1740 $1\core_rego$next[4:0]$1739 $1\core_asmcode$next[7:0]$1696 } 321'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_asmcode$next[7:0]$1696 $2\core_asmcode$next[7:0]$1747 + assign $1\core_core_cia$next[63:0]$1697 $2\core_core_cia$next[63:0]$1748 + assign $1\core_core_cr_rd$next[7:0]$1698 $2\core_core_cr_rd$next[7:0]$1749 + assign $1\core_core_cr_rd_ok$next[0:0]$1699 $2\core_core_cr_rd_ok$next[0:0]$1750 + assign $1\core_core_cr_wr$next[7:0]$1700 $2\core_core_cr_wr$next[7:0]$1751 + assign $1\core_core_cr_wr_ok$next[0:0]$1701 $2\core_core_cr_wr_ok$next[0:0]$1752 + assign $1\core_core_fn_unit$next[11:0]$1702 $2\core_core_fn_unit$next[11:0]$1753 + assign $1\core_core_input_carry$next[1:0]$1703 $2\core_core_input_carry$next[1:0]$1754 + assign $1\core_core_insn$next[31:0]$1704 $2\core_core_insn$next[31:0]$1755 + assign $1\core_core_insn_type$next[6:0]$1705 $2\core_core_insn_type$next[6:0]$1756 + assign $1\core_core_is_32bit$next[0:0]$1706 $2\core_core_is_32bit$next[0:0]$1757 + assign $1\core_core_lk$next[0:0]$1707 $2\core_core_lk$next[0:0]$1758 + assign $1\core_core_msr$next[63:0]$1708 $2\core_core_msr$next[63:0]$1759 + assign $1\core_core_oe$next[0:0]$1709 $2\core_core_oe$next[0:0]$1760 + assign $1\core_core_oe_ok$next[0:0]$1710 $2\core_core_oe_ok$next[0:0]$1761 + assign $1\core_core_rc$next[0:0]$1711 $2\core_core_rc$next[0:0]$1762 + assign $1\core_core_rc_ok$next[0:0]$1712 $2\core_core_rc_ok$next[0:0]$1763 + assign $1\core_core_trapaddr$next[12:0]$1713 $2\core_core_trapaddr$next[12:0]$1764 + assign $1\core_core_traptype$next[6:0]$1714 $2\core_core_traptype$next[6:0]$1765 + assign $1\core_cr_in1$next[2:0]$1715 $2\core_cr_in1$next[2:0]$1766 + assign $1\core_cr_in1_ok$next[0:0]$1716 $2\core_cr_in1_ok$next[0:0]$1767 + assign $1\core_cr_in2$39$next[2:0]$1717 $2\core_cr_in2$39$next[2:0]$1768 + assign $1\core_cr_in2$next[2:0]$1718 $2\core_cr_in2$next[2:0]$1769 + assign $1\core_cr_in2_ok$40$next[0:0]$1719 $2\core_cr_in2_ok$40$next[0:0]$1770 + assign $1\core_cr_in2_ok$next[0:0]$1720 $2\core_cr_in2_ok$next[0:0]$1771 + assign $1\core_cr_out$next[2:0]$1721 $2\core_cr_out$next[2:0]$1772 + assign $1\core_cr_out_ok$next[0:0]$1722 $2\core_cr_out_ok$next[0:0]$1773 + assign $1\core_ea$next[4:0]$1723 $2\core_ea$next[4:0]$1774 + assign $1\core_ea_ok$next[0:0]$1724 $2\core_ea_ok$next[0:0]$1775 + assign $1\core_fast1$next[2:0]$1725 $2\core_fast1$next[2:0]$1776 + assign $1\core_fast1_ok$next[0:0]$1726 $2\core_fast1_ok$next[0:0]$1777 + assign $1\core_fast2$next[2:0]$1727 $2\core_fast2$next[2:0]$1778 + assign $1\core_fast2_ok$next[0:0]$1728 $2\core_fast2_ok$next[0:0]$1779 + assign $1\core_fasto1$next[2:0]$1729 $2\core_fasto1$next[2:0]$1780 + assign $1\core_fasto1_ok$next[0:0]$1730 $2\core_fasto1_ok$next[0:0]$1781 + assign $1\core_fasto2$next[2:0]$1731 $2\core_fasto2$next[2:0]$1782 + assign $1\core_fasto2_ok$next[0:0]$1732 $2\core_fasto2_ok$next[0:0]$1783 + assign $1\core_reg1$next[4:0]$1733 $2\core_reg1$next[4:0]$1784 + assign $1\core_reg1_ok$next[0:0]$1734 $2\core_reg1_ok$next[0:0]$1785 + assign $1\core_reg2$next[4:0]$1735 $2\core_reg2$next[4:0]$1786 + assign $1\core_reg2_ok$next[0:0]$1736 $2\core_reg2_ok$next[0:0]$1787 + assign $1\core_reg3$next[4:0]$1737 $2\core_reg3$next[4:0]$1788 + assign $1\core_reg3_ok$next[0:0]$1738 $2\core_reg3_ok$next[0:0]$1789 + assign $1\core_rego$next[4:0]$1739 $2\core_rego$next[4:0]$1790 + assign $1\core_rego_ok$next[0:0]$1740 $2\core_rego_ok$next[0:0]$1791 + assign $1\core_spr1$next[9:0]$1741 $2\core_spr1$next[9:0]$1792 + assign $1\core_spr1_ok$next[0:0]$1742 $2\core_spr1_ok$next[0:0]$1793 + assign $1\core_spro$next[9:0]$1743 $2\core_spro$next[9:0]$1794 + assign $1\core_spro_ok$next[0:0]$1744 $2\core_spro_ok$next[0:0]$1795 + assign $1\core_xer_in$next[2:0]$1745 $2\core_xer_in$next[2:0]$1796 + assign $1\core_xer_out$next[0:0]$1746 $2\core_xer_out$next[0:0]$1797 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_asmcode$next[7:0]$1747 \core_asmcode + assign $2\core_core_cia$next[63:0]$1748 \core_core_cia + assign $2\core_core_cr_rd$next[7:0]$1749 \core_core_cr_rd + assign $2\core_core_cr_rd_ok$next[0:0]$1750 \core_core_cr_rd_ok + assign $2\core_core_cr_wr$next[7:0]$1751 \core_core_cr_wr + assign $2\core_core_cr_wr_ok$next[0:0]$1752 \core_core_cr_wr_ok + assign $2\core_core_fn_unit$next[11:0]$1753 \core_core_fn_unit + assign $2\core_core_input_carry$next[1:0]$1754 \core_core_input_carry + assign $2\core_core_insn$next[31:0]$1755 \core_core_insn + assign $2\core_core_insn_type$next[6:0]$1756 \core_core_insn_type + assign $2\core_core_is_32bit$next[0:0]$1757 \core_core_is_32bit + assign $2\core_core_lk$next[0:0]$1758 \core_core_lk + assign $2\core_core_msr$next[63:0]$1759 \core_core_msr + assign $2\core_core_oe$next[0:0]$1760 \core_core_oe + assign $2\core_core_oe_ok$next[0:0]$1761 \core_core_oe_ok + assign $2\core_core_rc$next[0:0]$1762 \core_core_rc + assign $2\core_core_rc_ok$next[0:0]$1763 \core_core_rc_ok + assign $2\core_core_trapaddr$next[12:0]$1764 \core_core_trapaddr + assign $2\core_core_traptype$next[6:0]$1765 \core_core_traptype + assign $2\core_cr_in1$next[2:0]$1766 \core_cr_in1 + assign $2\core_cr_in1_ok$next[0:0]$1767 \core_cr_in1_ok + assign $2\core_cr_in2$39$next[2:0]$1768 \core_cr_in2$39 + assign $2\core_cr_in2$next[2:0]$1769 \core_cr_in2 + assign $2\core_cr_in2_ok$40$next[0:0]$1770 \core_cr_in2_ok$40 + assign $2\core_cr_in2_ok$next[0:0]$1771 \core_cr_in2_ok + assign $2\core_cr_out$next[2:0]$1772 \core_cr_out + assign $2\core_cr_out_ok$next[0:0]$1773 \core_cr_out_ok + assign $2\core_ea$next[4:0]$1774 \core_ea + assign $2\core_ea_ok$next[0:0]$1775 \core_ea_ok + assign $2\core_fast1$next[2:0]$1776 \core_fast1 + assign $2\core_fast1_ok$next[0:0]$1777 \core_fast1_ok + assign $2\core_fast2$next[2:0]$1778 \core_fast2 + assign $2\core_fast2_ok$next[0:0]$1779 \core_fast2_ok + assign $2\core_fasto1$next[2:0]$1780 \core_fasto1 + assign $2\core_fasto1_ok$next[0:0]$1781 \core_fasto1_ok + assign $2\core_fasto2$next[2:0]$1782 \core_fasto2 + assign $2\core_fasto2_ok$next[0:0]$1783 \core_fasto2_ok + assign $2\core_reg1$next[4:0]$1784 \core_reg1 + assign $2\core_reg1_ok$next[0:0]$1785 \core_reg1_ok + assign $2\core_reg2$next[4:0]$1786 \core_reg2 + assign $2\core_reg2_ok$next[0:0]$1787 \core_reg2_ok + assign $2\core_reg3$next[4:0]$1788 \core_reg3 + assign $2\core_reg3_ok$next[0:0]$1789 \core_reg3_ok + assign $2\core_rego$next[4:0]$1790 \core_rego + assign $2\core_rego_ok$next[0:0]$1791 \core_rego_ok + assign $2\core_spr1$next[9:0]$1792 \core_spr1 + assign $2\core_spr1_ok$next[0:0]$1793 \core_spr1_ok + assign $2\core_spro$next[9:0]$1794 \core_spro + assign $2\core_spro_ok$next[0:0]$1795 \core_spro_ok + assign $2\core_xer_in$next[2:0]$1796 \core_xer_in + assign $2\core_xer_out$next[0:0]$1797 \core_xer_out + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\core_core_is_32bit$next[0:0]$1757 $2\core_core_cr_wr_ok$next[0:0]$1752 $2\core_core_cr_wr$next[7:0]$1751 $2\core_core_cr_rd_ok$next[0:0]$1750 $2\core_core_cr_rd$next[7:0]$1749 $2\core_core_trapaddr$next[12:0]$1764 $2\core_core_traptype$next[6:0]$1765 $2\core_core_input_carry$next[1:0]$1754 $2\core_core_oe_ok$next[0:0]$1761 $2\core_core_oe$next[0:0]$1760 $2\core_core_rc_ok$next[0:0]$1763 $2\core_core_rc$next[0:0]$1762 $2\core_core_lk$next[0:0]$1758 $2\core_core_fn_unit$next[11:0]$1753 $2\core_core_insn_type$next[6:0]$1756 $2\core_core_insn$next[31:0]$1755 $2\core_core_cia$next[63:0]$1748 $2\core_core_msr$next[63:0]$1759 $2\core_cr_out_ok$next[0:0]$1773 $2\core_cr_out$next[2:0]$1772 $2\core_cr_in2_ok$40$next[0:0]$1770 $2\core_cr_in2$39$next[2:0]$1768 $2\core_cr_in2_ok$next[0:0]$1771 $2\core_cr_in2$next[2:0]$1769 $2\core_cr_in1_ok$next[0:0]$1767 $2\core_cr_in1$next[2:0]$1766 $2\core_fasto2_ok$next[0:0]$1783 $2\core_fasto2$next[2:0]$1782 $2\core_fasto1_ok$next[0:0]$1781 $2\core_fasto1$next[2:0]$1780 $2\core_fast2_ok$next[0:0]$1779 $2\core_fast2$next[2:0]$1778 $2\core_fast1_ok$next[0:0]$1777 $2\core_fast1$next[2:0]$1776 $2\core_xer_out$next[0:0]$1797 $2\core_xer_in$next[2:0]$1796 $2\core_spr1_ok$next[0:0]$1793 $2\core_spr1$next[9:0]$1792 $2\core_spro_ok$next[0:0]$1795 $2\core_spro$next[9:0]$1794 $2\core_reg3_ok$next[0:0]$1789 $2\core_reg3$next[4:0]$1788 $2\core_reg2_ok$next[0:0]$1787 $2\core_reg2$next[4:0]$1786 $2\core_reg1_ok$next[0:0]$1785 $2\core_reg1$next[4:0]$1784 $2\core_ea_ok$next[0:0]$1775 $2\core_ea$next[4:0]$1774 $2\core_rego_ok$next[0:0]$1791 $2\core_rego$next[4:0]$1790 $2\core_asmcode$next[7:0]$1747 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$2 \dec2_cr_in2$1 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_asmcode$next[7:0]$1696 $3\core_asmcode$next[7:0]$1798 + assign $1\core_core_cia$next[63:0]$1697 $3\core_core_cia$next[63:0]$1799 + assign $1\core_core_cr_rd$next[7:0]$1698 $3\core_core_cr_rd$next[7:0]$1800 + assign $1\core_core_cr_rd_ok$next[0:0]$1699 $3\core_core_cr_rd_ok$next[0:0]$1801 + assign $1\core_core_cr_wr$next[7:0]$1700 $3\core_core_cr_wr$next[7:0]$1802 + assign $1\core_core_cr_wr_ok$next[0:0]$1701 $3\core_core_cr_wr_ok$next[0:0]$1803 + assign $1\core_core_fn_unit$next[11:0]$1702 $3\core_core_fn_unit$next[11:0]$1804 + assign $1\core_core_input_carry$next[1:0]$1703 $3\core_core_input_carry$next[1:0]$1805 + assign $1\core_core_insn$next[31:0]$1704 $3\core_core_insn$next[31:0]$1806 + assign $1\core_core_insn_type$next[6:0]$1705 $3\core_core_insn_type$next[6:0]$1807 + assign $1\core_core_is_32bit$next[0:0]$1706 $3\core_core_is_32bit$next[0:0]$1808 + assign $1\core_core_lk$next[0:0]$1707 $3\core_core_lk$next[0:0]$1809 + assign $1\core_core_msr$next[63:0]$1708 $3\core_core_msr$next[63:0]$1810 + assign $1\core_core_oe$next[0:0]$1709 $3\core_core_oe$next[0:0]$1811 + assign $1\core_core_oe_ok$next[0:0]$1710 $3\core_core_oe_ok$next[0:0]$1812 + assign $1\core_core_rc$next[0:0]$1711 $3\core_core_rc$next[0:0]$1813 + assign $1\core_core_rc_ok$next[0:0]$1712 $3\core_core_rc_ok$next[0:0]$1814 + assign $1\core_core_trapaddr$next[12:0]$1713 $3\core_core_trapaddr$next[12:0]$1815 + assign $1\core_core_traptype$next[6:0]$1714 $3\core_core_traptype$next[6:0]$1816 + assign $1\core_cr_in1$next[2:0]$1715 $3\core_cr_in1$next[2:0]$1817 + assign $1\core_cr_in1_ok$next[0:0]$1716 $3\core_cr_in1_ok$next[0:0]$1818 + assign $1\core_cr_in2$39$next[2:0]$1717 $3\core_cr_in2$39$next[2:0]$1819 + assign $1\core_cr_in2$next[2:0]$1718 $3\core_cr_in2$next[2:0]$1820 + assign $1\core_cr_in2_ok$40$next[0:0]$1719 $3\core_cr_in2_ok$40$next[0:0]$1821 + assign $1\core_cr_in2_ok$next[0:0]$1720 $3\core_cr_in2_ok$next[0:0]$1822 + assign $1\core_cr_out$next[2:0]$1721 $3\core_cr_out$next[2:0]$1823 + assign $1\core_cr_out_ok$next[0:0]$1722 $3\core_cr_out_ok$next[0:0]$1824 + assign $1\core_ea$next[4:0]$1723 $3\core_ea$next[4:0]$1825 + assign $1\core_ea_ok$next[0:0]$1724 $3\core_ea_ok$next[0:0]$1826 + assign $1\core_fast1$next[2:0]$1725 $3\core_fast1$next[2:0]$1827 + assign $1\core_fast1_ok$next[0:0]$1726 $3\core_fast1_ok$next[0:0]$1828 + assign $1\core_fast2$next[2:0]$1727 $3\core_fast2$next[2:0]$1829 + assign $1\core_fast2_ok$next[0:0]$1728 $3\core_fast2_ok$next[0:0]$1830 + assign $1\core_fasto1$next[2:0]$1729 $3\core_fasto1$next[2:0]$1831 + assign $1\core_fasto1_ok$next[0:0]$1730 $3\core_fasto1_ok$next[0:0]$1832 + assign $1\core_fasto2$next[2:0]$1731 $3\core_fasto2$next[2:0]$1833 + assign $1\core_fasto2_ok$next[0:0]$1732 $3\core_fasto2_ok$next[0:0]$1834 + assign $1\core_reg1$next[4:0]$1733 $3\core_reg1$next[4:0]$1835 + assign $1\core_reg1_ok$next[0:0]$1734 $3\core_reg1_ok$next[0:0]$1836 + assign $1\core_reg2$next[4:0]$1735 $3\core_reg2$next[4:0]$1837 + assign $1\core_reg2_ok$next[0:0]$1736 $3\core_reg2_ok$next[0:0]$1838 + assign $1\core_reg3$next[4:0]$1737 $3\core_reg3$next[4:0]$1839 + assign $1\core_reg3_ok$next[0:0]$1738 $3\core_reg3_ok$next[0:0]$1840 + assign $1\core_rego$next[4:0]$1739 $3\core_rego$next[4:0]$1841 + assign $1\core_rego_ok$next[0:0]$1740 $3\core_rego_ok$next[0:0]$1842 + assign $1\core_spr1$next[9:0]$1741 $3\core_spr1$next[9:0]$1843 + assign $1\core_spr1_ok$next[0:0]$1742 $3\core_spr1_ok$next[0:0]$1844 + assign $1\core_spro$next[9:0]$1743 $3\core_spro$next[9:0]$1845 + assign $1\core_spro_ok$next[0:0]$1744 $3\core_spro_ok$next[0:0]$1846 + assign $1\core_xer_in$next[2:0]$1745 $3\core_xer_in$next[2:0]$1847 + assign $1\core_xer_out$next[0:0]$1746 $3\core_xer_out$next[0:0]$1848 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" + switch \$41 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\core_core_is_32bit$next[0:0]$1808 $3\core_core_cr_wr_ok$next[0:0]$1803 $3\core_core_cr_wr$next[7:0]$1802 $3\core_core_cr_rd_ok$next[0:0]$1801 $3\core_core_cr_rd$next[7:0]$1800 $3\core_core_trapaddr$next[12:0]$1815 $3\core_core_traptype$next[6:0]$1816 $3\core_core_input_carry$next[1:0]$1805 $3\core_core_oe_ok$next[0:0]$1812 $3\core_core_oe$next[0:0]$1811 $3\core_core_rc_ok$next[0:0]$1814 $3\core_core_rc$next[0:0]$1813 $3\core_core_lk$next[0:0]$1809 $3\core_core_fn_unit$next[11:0]$1804 $3\core_core_insn_type$next[6:0]$1807 $3\core_core_insn$next[31:0]$1806 $3\core_core_cia$next[63:0]$1799 $3\core_core_msr$next[63:0]$1810 $3\core_cr_out_ok$next[0:0]$1824 $3\core_cr_out$next[2:0]$1823 $3\core_cr_in2_ok$40$next[0:0]$1821 $3\core_cr_in2$39$next[2:0]$1819 $3\core_cr_in2_ok$next[0:0]$1822 $3\core_cr_in2$next[2:0]$1820 $3\core_cr_in1_ok$next[0:0]$1818 $3\core_cr_in1$next[2:0]$1817 $3\core_fasto2_ok$next[0:0]$1834 $3\core_fasto2$next[2:0]$1833 $3\core_fasto1_ok$next[0:0]$1832 $3\core_fasto1$next[2:0]$1831 $3\core_fast2_ok$next[0:0]$1830 $3\core_fast2$next[2:0]$1829 $3\core_fast1_ok$next[0:0]$1828 $3\core_fast1$next[2:0]$1827 $3\core_xer_out$next[0:0]$1848 $3\core_xer_in$next[2:0]$1847 $3\core_spr1_ok$next[0:0]$1844 $3\core_spr1$next[9:0]$1843 $3\core_spro_ok$next[0:0]$1846 $3\core_spro$next[9:0]$1845 $3\core_reg3_ok$next[0:0]$1840 $3\core_reg3$next[4:0]$1839 $3\core_reg2_ok$next[0:0]$1838 $3\core_reg2$next[4:0]$1837 $3\core_reg1_ok$next[0:0]$1836 $3\core_reg1$next[4:0]$1835 $3\core_ea_ok$next[0:0]$1826 $3\core_ea$next[4:0]$1825 $3\core_rego_ok$next[0:0]$1842 $3\core_rego$next[4:0]$1841 $3\core_asmcode$next[7:0]$1798 } 321'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\core_asmcode$next[7:0]$1798 \core_asmcode + assign $3\core_core_cia$next[63:0]$1799 \core_core_cia + assign $3\core_core_cr_rd$next[7:0]$1800 \core_core_cr_rd + assign $3\core_core_cr_rd_ok$next[0:0]$1801 \core_core_cr_rd_ok + assign $3\core_core_cr_wr$next[7:0]$1802 \core_core_cr_wr + assign $3\core_core_cr_wr_ok$next[0:0]$1803 \core_core_cr_wr_ok + assign $3\core_core_fn_unit$next[11:0]$1804 \core_core_fn_unit + assign $3\core_core_input_carry$next[1:0]$1805 \core_core_input_carry + assign $3\core_core_insn$next[31:0]$1806 \core_core_insn + assign $3\core_core_insn_type$next[6:0]$1807 \core_core_insn_type + assign $3\core_core_is_32bit$next[0:0]$1808 \core_core_is_32bit + assign $3\core_core_lk$next[0:0]$1809 \core_core_lk + assign $3\core_core_msr$next[63:0]$1810 \core_core_msr + assign $3\core_core_oe$next[0:0]$1811 \core_core_oe + assign $3\core_core_oe_ok$next[0:0]$1812 \core_core_oe_ok + assign $3\core_core_rc$next[0:0]$1813 \core_core_rc + assign $3\core_core_rc_ok$next[0:0]$1814 \core_core_rc_ok + assign $3\core_core_trapaddr$next[12:0]$1815 \core_core_trapaddr + assign $3\core_core_traptype$next[6:0]$1816 \core_core_traptype + assign $3\core_cr_in1$next[2:0]$1817 \core_cr_in1 + assign $3\core_cr_in1_ok$next[0:0]$1818 \core_cr_in1_ok + assign $3\core_cr_in2$39$next[2:0]$1819 \core_cr_in2$39 + assign $3\core_cr_in2$next[2:0]$1820 \core_cr_in2 + assign $3\core_cr_in2_ok$40$next[0:0]$1821 \core_cr_in2_ok$40 + assign $3\core_cr_in2_ok$next[0:0]$1822 \core_cr_in2_ok + assign $3\core_cr_out$next[2:0]$1823 \core_cr_out + assign $3\core_cr_out_ok$next[0:0]$1824 \core_cr_out_ok + assign $3\core_ea$next[4:0]$1825 \core_ea + assign $3\core_ea_ok$next[0:0]$1826 \core_ea_ok + assign $3\core_fast1$next[2:0]$1827 \core_fast1 + assign $3\core_fast1_ok$next[0:0]$1828 \core_fast1_ok + assign $3\core_fast2$next[2:0]$1829 \core_fast2 + assign $3\core_fast2_ok$next[0:0]$1830 \core_fast2_ok + assign $3\core_fasto1$next[2:0]$1831 \core_fasto1 + assign $3\core_fasto1_ok$next[0:0]$1832 \core_fasto1_ok + assign $3\core_fasto2$next[2:0]$1833 \core_fasto2 + assign $3\core_fasto2_ok$next[0:0]$1834 \core_fasto2_ok + assign $3\core_reg1$next[4:0]$1835 \core_reg1 + assign $3\core_reg1_ok$next[0:0]$1836 \core_reg1_ok + assign $3\core_reg2$next[4:0]$1837 \core_reg2 + assign $3\core_reg2_ok$next[0:0]$1838 \core_reg2_ok + assign $3\core_reg3$next[4:0]$1839 \core_reg3 + assign $3\core_reg3_ok$next[0:0]$1840 \core_reg3_ok + assign $3\core_rego$next[4:0]$1841 \core_rego + assign $3\core_rego_ok$next[0:0]$1842 \core_rego_ok + assign $3\core_spr1$next[9:0]$1843 \core_spr1 + assign $3\core_spr1_ok$next[0:0]$1844 \core_spr1_ok + assign $3\core_spro$next[9:0]$1845 \core_spro + assign $3\core_spro_ok$next[0:0]$1846 \core_spro_ok + assign $3\core_xer_in$next[2:0]$1847 \core_xer_in + assign $3\core_xer_out$next[0:0]$1848 \core_xer_out + end + case + assign $1\core_asmcode$next[7:0]$1696 \core_asmcode + assign $1\core_core_cia$next[63:0]$1697 \core_core_cia + assign $1\core_core_cr_rd$next[7:0]$1698 \core_core_cr_rd + assign $1\core_core_cr_rd_ok$next[0:0]$1699 \core_core_cr_rd_ok + assign $1\core_core_cr_wr$next[7:0]$1700 \core_core_cr_wr + assign $1\core_core_cr_wr_ok$next[0:0]$1701 \core_core_cr_wr_ok + assign $1\core_core_fn_unit$next[11:0]$1702 \core_core_fn_unit + assign $1\core_core_input_carry$next[1:0]$1703 \core_core_input_carry + assign $1\core_core_insn$next[31:0]$1704 \core_core_insn + assign $1\core_core_insn_type$next[6:0]$1705 \core_core_insn_type + assign $1\core_core_is_32bit$next[0:0]$1706 \core_core_is_32bit + assign $1\core_core_lk$next[0:0]$1707 \core_core_lk + assign $1\core_core_msr$next[63:0]$1708 \core_core_msr + assign $1\core_core_oe$next[0:0]$1709 \core_core_oe + assign $1\core_core_oe_ok$next[0:0]$1710 \core_core_oe_ok + assign $1\core_core_rc$next[0:0]$1711 \core_core_rc + assign $1\core_core_rc_ok$next[0:0]$1712 \core_core_rc_ok + assign $1\core_core_trapaddr$next[12:0]$1713 \core_core_trapaddr + assign $1\core_core_traptype$next[6:0]$1714 \core_core_traptype + assign $1\core_cr_in1$next[2:0]$1715 \core_cr_in1 + assign $1\core_cr_in1_ok$next[0:0]$1716 \core_cr_in1_ok + assign $1\core_cr_in2$39$next[2:0]$1717 \core_cr_in2$39 + assign $1\core_cr_in2$next[2:0]$1718 \core_cr_in2 + assign $1\core_cr_in2_ok$40$next[0:0]$1719 \core_cr_in2_ok$40 + assign $1\core_cr_in2_ok$next[0:0]$1720 \core_cr_in2_ok + assign $1\core_cr_out$next[2:0]$1721 \core_cr_out + assign $1\core_cr_out_ok$next[0:0]$1722 \core_cr_out_ok + assign $1\core_ea$next[4:0]$1723 \core_ea + assign $1\core_ea_ok$next[0:0]$1724 \core_ea_ok + assign $1\core_fast1$next[2:0]$1725 \core_fast1 + assign $1\core_fast1_ok$next[0:0]$1726 \core_fast1_ok + assign $1\core_fast2$next[2:0]$1727 \core_fast2 + assign $1\core_fast2_ok$next[0:0]$1728 \core_fast2_ok + assign $1\core_fasto1$next[2:0]$1729 \core_fasto1 + assign $1\core_fasto1_ok$next[0:0]$1730 \core_fasto1_ok + assign $1\core_fasto2$next[2:0]$1731 \core_fasto2 + assign $1\core_fasto2_ok$next[0:0]$1732 \core_fasto2_ok + assign $1\core_reg1$next[4:0]$1733 \core_reg1 + assign $1\core_reg1_ok$next[0:0]$1734 \core_reg1_ok + assign $1\core_reg2$next[4:0]$1735 \core_reg2 + assign $1\core_reg2_ok$next[0:0]$1736 \core_reg2_ok + assign $1\core_reg3$next[4:0]$1737 \core_reg3 + assign $1\core_reg3_ok$next[0:0]$1738 \core_reg3_ok + assign $1\core_rego$next[4:0]$1739 \core_rego + assign $1\core_rego_ok$next[0:0]$1740 \core_rego_ok + assign $1\core_spr1$next[9:0]$1741 \core_spr1 + assign $1\core_spr1_ok$next[0:0]$1742 \core_spr1_ok + assign $1\core_spro$next[9:0]$1743 \core_spro + assign $1\core_spro_ok$next[0:0]$1744 \core_spro_ok + assign $1\core_xer_in$next[2:0]$1745 \core_xer_in + assign $1\core_xer_out$next[0:0]$1746 \core_xer_out + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $4\core_rego_ok$next[0:0]$1865 1'0 + assign $4\core_ea_ok$next[0:0]$1857 1'0 + assign $4\core_reg1_ok$next[0:0]$1862 1'0 + assign $4\core_reg2_ok$next[0:0]$1863 1'0 + assign $4\core_reg3_ok$next[0:0]$1864 1'0 + assign $4\core_spro_ok$next[0:0]$1867 1'0 + assign $4\core_spr1_ok$next[0:0]$1866 1'0 + assign $4\core_fast1_ok$next[0:0]$1858 1'0 + assign $4\core_fast2_ok$next[0:0]$1859 1'0 + assign $4\core_fasto1_ok$next[0:0]$1860 1'0 + assign $4\core_fasto2_ok$next[0:0]$1861 1'0 + assign $4\core_cr_in1_ok$next[0:0]$1853 1'0 + assign $4\core_cr_in2_ok$next[0:0]$1855 1'0 + assign $4\core_cr_in2_ok$40$next[0:0]$1854 1'0 + assign $4\core_cr_out_ok$next[0:0]$1856 1'0 + assign $4\core_core_rc_ok$next[0:0]$1852 1'0 + assign $4\core_core_oe_ok$next[0:0]$1851 1'0 + assign $4\core_core_cr_rd_ok$next[0:0]$1849 1'0 + assign $4\core_core_cr_wr_ok$next[0:0]$1850 1'0 + case + assign $4\core_core_cr_rd_ok$next[0:0]$1849 $1\core_core_cr_rd_ok$next[0:0]$1699 + assign $4\core_core_cr_wr_ok$next[0:0]$1850 $1\core_core_cr_wr_ok$next[0:0]$1701 + assign $4\core_core_oe_ok$next[0:0]$1851 $1\core_core_oe_ok$next[0:0]$1710 + assign $4\core_core_rc_ok$next[0:0]$1852 $1\core_core_rc_ok$next[0:0]$1712 + assign $4\core_cr_in1_ok$next[0:0]$1853 $1\core_cr_in1_ok$next[0:0]$1716 + assign $4\core_cr_in2_ok$40$next[0:0]$1854 $1\core_cr_in2_ok$40$next[0:0]$1719 + assign $4\core_cr_in2_ok$next[0:0]$1855 $1\core_cr_in2_ok$next[0:0]$1720 + assign $4\core_cr_out_ok$next[0:0]$1856 $1\core_cr_out_ok$next[0:0]$1722 + assign $4\core_ea_ok$next[0:0]$1857 $1\core_ea_ok$next[0:0]$1724 + assign $4\core_fast1_ok$next[0:0]$1858 $1\core_fast1_ok$next[0:0]$1726 + assign $4\core_fast2_ok$next[0:0]$1859 $1\core_fast2_ok$next[0:0]$1728 + assign $4\core_fasto1_ok$next[0:0]$1860 $1\core_fasto1_ok$next[0:0]$1730 + assign $4\core_fasto2_ok$next[0:0]$1861 $1\core_fasto2_ok$next[0:0]$1732 + assign $4\core_reg1_ok$next[0:0]$1862 $1\core_reg1_ok$next[0:0]$1734 + assign $4\core_reg2_ok$next[0:0]$1863 $1\core_reg2_ok$next[0:0]$1736 + assign $4\core_reg3_ok$next[0:0]$1864 $1\core_reg3_ok$next[0:0]$1738 + assign $4\core_rego_ok$next[0:0]$1865 $1\core_rego_ok$next[0:0]$1740 + assign $4\core_spr1_ok$next[0:0]$1866 $1\core_spr1_ok$next[0:0]$1742 + assign $4\core_spro_ok$next[0:0]$1867 $1\core_spro_ok$next[0:0]$1744 + end + sync always + update \core_asmcode$next $0\core_asmcode$next[7:0]$1645 + update \core_core_cia$next $0\core_core_cia$next[63:0]$1646 + update \core_core_cr_rd$next $0\core_core_cr_rd$next[7:0]$1647 + update \core_core_cr_rd_ok$next $0\core_core_cr_rd_ok$next[0:0]$1648 + update \core_core_cr_wr$next $0\core_core_cr_wr$next[7:0]$1649 + update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$1650 + update \core_core_fn_unit$next $0\core_core_fn_unit$next[11:0]$1651 + update \core_core_input_carry$next $0\core_core_input_carry$next[1:0]$1652 + update \core_core_insn$next $0\core_core_insn$next[31:0]$1653 + update \core_core_insn_type$next $0\core_core_insn_type$next[6:0]$1654 + update \core_core_is_32bit$next $0\core_core_is_32bit$next[0:0]$1655 + update \core_core_lk$next $0\core_core_lk$next[0:0]$1656 + update \core_core_msr$next $0\core_core_msr$next[63:0]$1657 + update \core_core_oe$next $0\core_core_oe$next[0:0]$1658 + update \core_core_oe_ok$next $0\core_core_oe_ok$next[0:0]$1659 + update \core_core_rc$next $0\core_core_rc$next[0:0]$1660 + update \core_core_rc_ok$next $0\core_core_rc_ok$next[0:0]$1661 + update \core_core_trapaddr$next $0\core_core_trapaddr$next[12:0]$1662 + update \core_core_traptype$next $0\core_core_traptype$next[6:0]$1663 + update \core_cr_in1$next $0\core_cr_in1$next[2:0]$1664 + update \core_cr_in1_ok$next $0\core_cr_in1_ok$next[0:0]$1665 + update \core_cr_in2$39$next $0\core_cr_in2$39$next[2:0]$1666 + update \core_cr_in2$next $0\core_cr_in2$next[2:0]$1667 + update \core_cr_in2_ok$40$next $0\core_cr_in2_ok$40$next[0:0]$1668 + update \core_cr_in2_ok$next $0\core_cr_in2_ok$next[0:0]$1669 + update \core_cr_out$next $0\core_cr_out$next[2:0]$1670 + update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$1671 + update \core_ea$next $0\core_ea$next[4:0]$1672 + update \core_ea_ok$next $0\core_ea_ok$next[0:0]$1673 + update \core_fast1$next $0\core_fast1$next[2:0]$1674 + update \core_fast1_ok$next $0\core_fast1_ok$next[0:0]$1675 + update \core_fast2$next $0\core_fast2$next[2:0]$1676 + update \core_fast2_ok$next $0\core_fast2_ok$next[0:0]$1677 + update \core_fasto1$next $0\core_fasto1$next[2:0]$1678 + update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$1679 + update \core_fasto2$next $0\core_fasto2$next[2:0]$1680 + update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$1681 + update \core_reg1$next $0\core_reg1$next[4:0]$1682 + update \core_reg1_ok$next $0\core_reg1_ok$next[0:0]$1683 + update \core_reg2$next $0\core_reg2$next[4:0]$1684 + update \core_reg2_ok$next $0\core_reg2_ok$next[0:0]$1685 + update \core_reg3$next $0\core_reg3$next[4:0]$1686 + update \core_reg3_ok$next $0\core_reg3_ok$next[0:0]$1687 + update \core_rego$next $0\core_rego$next[4:0]$1688 + update \core_rego_ok$next $0\core_rego_ok$next[0:0]$1689 + update \core_spr1$next $0\core_spr1$next[9:0]$1690 + update \core_spr1_ok$next $0\core_spr1_ok$next[0:0]$1691 + update \core_spro$next $0\core_spro$next[9:0]$1692 + update \core_spro_ok$next $0\core_spro_ok$next[0:0]$1693 + update \core_xer_in$next $0\core_xer_in$next[2:0]$1694 + update \core_xer_out$next $0\core_xer_out$next[0:0]$1695 + end + attribute \src "libresoc.v:49720.3-49728.6" + process $proc$libresoc.v:49720$1868 + assign { } { } + assign { } { } + assign $0\jtag_dmi0_ack_o$next[0:0]$1869 $1\jtag_dmi0_ack_o$next[0:0]$1870 + attribute \src "libresoc.v:49721.5-49721.29" + switch \initial + attribute \src "libresoc.v:49721.9-49721.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_dmi0_ack_o$next[0:0]$1870 1'0 + case + assign $1\jtag_dmi0_ack_o$next[0:0]$1870 \dbg_dmi_ack_o + end + sync always + update \jtag_dmi0_ack_o$next $0\jtag_dmi0_ack_o$next[0:0]$1869 + end + attribute \src "libresoc.v:49729.3-49737.6" + process $proc$libresoc.v:49729$1871 + assign { } { } + assign { } { } + assign $0\jtag_dmi0_dout$next[63:0]$1872 $1\jtag_dmi0_dout$next[63:0]$1873 + attribute \src "libresoc.v:49730.5-49730.29" + switch \initial + attribute \src "libresoc.v:49730.9-49730.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_dmi0_dout$next[63:0]$1873 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\jtag_dmi0_dout$next[63:0]$1873 \dbg_dmi_dout + end + sync always + update \jtag_dmi0_dout$next $0\jtag_dmi0_dout$next[63:0]$1872 + end + attribute \src "libresoc.v:49738.3-49746.6" + process $proc$libresoc.v:49738$1874 + assign { } { } + assign { } { } + assign $0\dec2_cur_eint$next[0:0]$1875 $1\dec2_cur_eint$next[0:0]$1876 + attribute \src "libresoc.v:49739.5-49739.29" + switch \initial + attribute \src "libresoc.v:49739.9-49739.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dec2_cur_eint$next[0:0]$1876 1'0 + case + assign $1\dec2_cur_eint$next[0:0]$1876 \xics_icp_core_irq_o + end + sync always + update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$1875 + end + attribute \src "libresoc.v:49747.3-49783.6" + process $proc$libresoc.v:49747$1877 + assign { } { } + assign { } { } + assign { } { } + assign $0\raw_insn_i$next[31:0]$1878 $4\raw_insn_i$next[31:0]$1882 + attribute \src "libresoc.v:49748.5-49748.29" + switch \initial + attribute \src "libresoc.v:49748.9-49748.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\raw_insn_i$next[31:0]$1879 0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\raw_insn_i$next[31:0]$1879 $2\raw_insn_i$next[31:0]$1880 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\raw_insn_i$next[31:0]$1880 \raw_insn_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\raw_insn_i$next[31:0]$1880 \dec2_raw_opcode_in + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\raw_insn_i$next[31:0]$1879 $3\raw_insn_i$next[31:0]$1881 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" + switch \$43 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\raw_insn_i$next[31:0]$1881 0 + case + assign $3\raw_insn_i$next[31:0]$1881 \raw_insn_i + end + case + assign $1\raw_insn_i$next[31:0]$1879 \raw_insn_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\raw_insn_i$next[31:0]$1882 0 + case + assign $4\raw_insn_i$next[31:0]$1882 $1\raw_insn_i$next[31:0]$1879 + end + sync always + update \raw_insn_i$next $0\raw_insn_i$next[31:0]$1878 + end + attribute \src "libresoc.v:49784.3-49820.6" + process $proc$libresoc.v:49784$1883 + assign { } { } + assign { } { } + assign { } { } + assign $0\bigendian_i$next[0:0]$1884 $4\bigendian_i$next[0:0]$1888 + attribute \src "libresoc.v:49785.5-49785.29" + switch \initial + attribute \src "libresoc.v:49785.9-49785.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\bigendian_i$next[0:0]$1885 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\bigendian_i$next[0:0]$1885 $2\bigendian_i$next[0:0]$1886 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\bigendian_i$next[0:0]$1886 \bigendian_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\bigendian_i$next[0:0]$1886 \core_bigendian_i + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\bigendian_i$next[0:0]$1885 $3\bigendian_i$next[0:0]$1887 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" + switch \$45 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\bigendian_i$next[0:0]$1887 1'0 + case + assign $3\bigendian_i$next[0:0]$1887 \bigendian_i + end + case + assign $1\bigendian_i$next[0:0]$1885 \bigendian_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\bigendian_i$next[0:0]$1888 1'0 + case + assign $4\bigendian_i$next[0:0]$1888 $1\bigendian_i$next[0:0]$1885 + end + sync always + update \bigendian_i$next $0\bigendian_i$next[0:0]$1884 + end + attribute \src "libresoc.v:49821.3-49836.6" + process $proc$libresoc.v:49821$1889 + assign { } { } + assign { } { } + assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] + attribute \src "libresoc.v:49822.5-49822.29" + switch \initial + attribute \src "libresoc.v:49822.9-49822.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + switch \$51 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_a_pc_i[47:0] \pc [47:0] + case + assign $2\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + case + assign $1\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + sync always + update \imem_a_pc_i $0\imem_a_pc_i[47:0] + end + attribute \src "libresoc.v:49837.3-49861.6" + process $proc$libresoc.v:49837$1890 + assign { } { } + assign { } { } + assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] + attribute \src "libresoc.v:49838.5-49838.29" + switch \initial + attribute \src "libresoc.v:49838.9-49838.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + switch \$57 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_a_valid_i[0:0] 1'1 + case + assign $2\imem_a_valid_i[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\imem_a_valid_i[0:0] 1'1 + case + assign $3\imem_a_valid_i[0:0] 1'0 + end + case + assign $1\imem_a_valid_i[0:0] 1'0 + end + sync always + update \imem_a_valid_i $0\imem_a_valid_i[0:0] + end + attribute \src "libresoc.v:49862.3-49886.6" + process $proc$libresoc.v:49862$1891 + assign { } { } + assign { } { } + assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] + attribute \src "libresoc.v:49863.5-49863.29" + switch \initial + attribute \src "libresoc.v:49863.9-49863.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + switch \$63 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_f_valid_i[0:0] 1'1 + case + assign $2\imem_f_valid_i[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\imem_f_valid_i[0:0] 1'1 + case + assign $3\imem_f_valid_i[0:0] 1'0 + end + case + assign $1\imem_f_valid_i[0:0] 1'0 + end + sync always + update \imem_f_valid_i $0\imem_f_valid_i[0:0] + end + attribute \src "libresoc.v:49887.3-49907.6" + process $proc$libresoc.v:49887$1892 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_pc$next[63:0]$1893 $3\dec2_cur_pc$next[63:0]$1896 + attribute \src "libresoc.v:49888.5-49888.29" + switch \initial + attribute \src "libresoc.v:49888.9-49888.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec2_cur_pc$next[63:0]$1894 $2\dec2_cur_pc$next[63:0]$1895 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_pc$next[63:0]$1895 \pc + case + assign $2\dec2_cur_pc$next[63:0]$1895 \dec2_cur_pc + end + case + assign $1\dec2_cur_pc$next[63:0]$1894 \dec2_cur_pc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dec2_cur_pc$next[63:0]$1896 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dec2_cur_pc$next[63:0]$1896 $1\dec2_cur_pc$next[63:0]$1894 + end + sync always + update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$1893 + end + attribute \src "libresoc.v:49908.3-49937.6" + process $proc$libresoc.v:49908$1897 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr_read$next[0:0]$1898 $4\msr_read$next[0:0]$1902 + attribute \src "libresoc.v:49909.5-49909.29" + switch \initial + attribute \src "libresoc.v:49909.9-49909.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\msr_read$next[0:0]$1899 $2\msr_read$next[0:0]$1900 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + switch \$75 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr_read$next[0:0]$1900 1'0 + case + assign $2\msr_read$next[0:0]$1900 \msr_read + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\msr_read$next[0:0]$1899 $3\msr_read$next[0:0]$1901 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:257" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr_read$next[0:0]$1901 1'1 + case + assign $3\msr_read$next[0:0]$1901 \msr_read + end + case + assign $1\msr_read$next[0:0]$1899 \msr_read + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr_read$next[0:0]$1902 1'1 + case + assign $4\msr_read$next[0:0]$1902 $1\msr_read$next[0:0]$1899 + end + sync always + update \msr_read$next $0\msr_read$next[0:0]$1898 + end + attribute \src "libresoc.v:49938.3-49983.6" + process $proc$libresoc.v:49938$1903 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$next[1:0]$1904 $5\fsm_state$next[1:0]$1909 + attribute \src "libresoc.v:49939.5-49939.29" + switch \initial + attribute \src "libresoc.v:49939.9-49939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$next[1:0]$1905 $2\fsm_state$next[1:0]$1906 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + switch \$83 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[1:0]$1906 2'01 + case + assign $2\fsm_state$next[1:0]$1906 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fsm_state$next[1:0]$1905 $3\fsm_state$next[1:0]$1907 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\fsm_state$next[1:0]$1907 \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\fsm_state$next[1:0]$1907 2'10 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$next[1:0]$1905 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\fsm_state$next[1:0]$1905 $4\fsm_state$next[1:0]$1908 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[1:0]$1908 2'00 + case + assign $4\fsm_state$next[1:0]$1908 \fsm_state + end + case + assign $1\fsm_state$next[1:0]$1905 \fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[1:0]$1909 2'00 + case + assign $5\fsm_state$next[1:0]$1909 $1\fsm_state$next[1:0]$1905 + end + sync always + update \fsm_state$next $0\fsm_state$next[1:0]$1904 + end + attribute \src "libresoc.v:49984.3-49993.6" + process $proc$libresoc.v:49984$1910 + assign { } { } + assign { } { } + assign $0\delay$next[1:0]$1911 $1\delay$next[1:0]$1912 + attribute \src "libresoc.v:49985.5-49985.29" + switch \initial + attribute \src "libresoc.v:49985.9-49985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:158" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\delay$next[1:0]$1912 \$5 [1:0] + case + assign $1\delay$next[1:0]$1912 \delay + end + sync always + update \delay$next $0\delay$next[1:0]$1911 + end + attribute \src "libresoc.v:49994.3-50012.6" + process $proc$libresoc.v:49994$1913 + assign { } { } + assign { } { } + assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] + attribute \src "libresoc.v:49995.5-49995.29" + switch \initial + attribute \src "libresoc.v:49995.9-49995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + switch \$91 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\core_stopped_i[0:0] 1'1 + end + case + assign $1\core_stopped_i[0:0] 1'0 + end + sync always + update \core_stopped_i $0\core_stopped_i[0:0] + end + attribute \src "libresoc.v:50013.3-50031.6" + process $proc$libresoc.v:50013$1914 + assign { } { } + assign { } { } + assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:50014.5-50014.29" + switch \initial + attribute \src "libresoc.v:50014.9-50014.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" + switch \$97 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbg_core_stopped_i[0:0] 1'1 + end + case + assign $1\dbg_core_stopped_i[0:0] 1'0 + end + sync always + update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] + end + attribute \src "libresoc.v:50032.3-50052.6" + process $proc$libresoc.v:50032$1915 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_msr$next[63:0]$1916 $3\dec2_cur_msr$next[63:0]$1919 + attribute \src "libresoc.v:50033.5-50033.29" + switch \initial + attribute \src "libresoc.v:50033.9-50033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_cur_msr$next[63:0]$1917 $2\dec2_cur_msr$next[63:0]$1918 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:257" + switch \$99 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_msr$next[63:0]$1918 \msr__data_o + case + assign $2\dec2_cur_msr$next[63:0]$1918 \dec2_cur_msr + end + case + assign $1\dec2_cur_msr$next[63:0]$1917 \dec2_cur_msr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dec2_cur_msr$next[63:0]$1919 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dec2_cur_msr$next[63:0]$1919 $1\dec2_cur_msr$next[63:0]$1917 + end + sync always + update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$1916 + end + attribute \src "libresoc.v:50053.3-50071.6" + process $proc$libresoc.v:50053$1920 + assign { } { } + assign { } { } + assign $0\dec2_raw_opcode_in[31:0] $1\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:50054.5-50054.29" + switch \initial + attribute \src "libresoc.v:50054.9-50054.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_raw_opcode_in[31:0] $2\dec2_raw_opcode_in[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\dec2_raw_opcode_in[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dec2_raw_opcode_in[31:0] \$101 + end + case + assign $1\dec2_raw_opcode_in[31:0] 0 + end + sync always + update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] + end + attribute \src "libresoc.v:50072.3-50103.6" + process $proc$libresoc.v:50072$1921 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_dec$next[63:0]$1922 $3\core_dec$next[63:0]$1934 + assign $0\core_eint$next[0:0]$1923 $3\core_eint$next[0:0]$1935 + assign $0\core_msr$next[63:0]$1924 $3\core_msr$next[63:0]$1936 + assign $0\core_pc$next[63:0]$1925 $3\core_pc$next[63:0]$1937 + attribute \src "libresoc.v:50073.5-50073.29" + switch \initial + attribute \src "libresoc.v:50073.9-50073.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_dec$next[63:0]$1926 $2\core_dec$next[63:0]$1930 + assign $1\core_eint$next[0:0]$1927 $2\core_eint$next[0:0]$1931 + assign $1\core_msr$next[63:0]$1928 $2\core_msr$next[63:0]$1932 + assign $1\core_pc$next[63:0]$1929 $2\core_pc$next[63:0]$1933 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_dec$next[63:0]$1930 \core_dec + assign $2\core_eint$next[0:0]$1931 \core_eint + assign $2\core_msr$next[63:0]$1932 \core_msr + assign $2\core_pc$next[63:0]$1933 \core_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\core_dec$next[63:0]$1930 $2\core_eint$next[0:0]$1931 $2\core_msr$next[63:0]$1932 $2\core_pc$next[63:0]$1933 } { \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + end + case + assign $1\core_dec$next[63:0]$1926 \core_dec + assign $1\core_eint$next[0:0]$1927 \core_eint + assign $1\core_msr$next[63:0]$1928 \core_msr + assign $1\core_pc$next[63:0]$1929 \core_pc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\core_pc$next[63:0]$1937 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_msr$next[63:0]$1936 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_eint$next[0:0]$1935 1'0 + assign $3\core_dec$next[63:0]$1934 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\core_dec$next[63:0]$1934 $1\core_dec$next[63:0]$1926 + assign $3\core_eint$next[0:0]$1935 $1\core_eint$next[0:0]$1927 + assign $3\core_msr$next[63:0]$1936 $1\core_msr$next[63:0]$1928 + assign $3\core_pc$next[63:0]$1937 $1\core_pc$next[63:0]$1929 + end + sync always + update \core_dec$next $0\core_dec$next[63:0]$1922 + update \core_eint$next $0\core_eint$next[0:0]$1923 + update \core_msr$next $0\core_msr$next[63:0]$1924 + update \core_pc$next $0\core_pc$next[63:0]$1925 + end + attribute \src "libresoc.v:50104.3-50127.6" + process $proc$libresoc.v:50104$1938 + assign { } { } + assign { } { } + assign { } { } + assign $0\ilatch$next[31:0]$1939 $3\ilatch$next[31:0]$1942 + attribute \src "libresoc.v:50105.5-50105.29" + switch \initial + attribute \src "libresoc.v:50105.9-50105.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\ilatch$next[31:0]$1940 $2\ilatch$next[31:0]$1941 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:260" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\ilatch$next[31:0]$1941 \ilatch + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\ilatch$next[31:0]$1941 \$105 + end + case + assign $1\ilatch$next[31:0]$1940 \ilatch + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ilatch$next[31:0]$1942 0 + case + assign $3\ilatch$next[31:0]$1942 $1\ilatch$next[31:0]$1940 + end + sync always + update \ilatch$next $0\ilatch$next[31:0]$1939 + end + attribute \src "libresoc.v:50128.3-50147.6" + process $proc$libresoc.v:50128$1943 + assign { } { } + assign { } { } + assign $0\ivalid_i[0:0] $1\ivalid_i[0:0] + attribute \src "libresoc.v:50129.5-50129.29" + switch \initial + attribute \src "libresoc.v:50129.9-50129.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\ivalid_i[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\ivalid_i[0:0] $2\ivalid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + switch \$109 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ivalid_i[0:0] 1'1 + case + assign $2\ivalid_i[0:0] 1'0 + end + case + assign $1\ivalid_i[0:0] 1'0 + end + sync always + update \ivalid_i $0\ivalid_i[0:0] + end + connect \$99 $not$libresoc.v:48713$1443_Y + connect \$102 $mul$libresoc.v:48714$1444_Y + connect \$101 $shr$libresoc.v:48715$1445_Y [31:0] + connect \$106 $mul$libresoc.v:48716$1446_Y + connect \$105 $shr$libresoc.v:48717$1447_Y [31:0] + connect \$10 $ne$libresoc.v:48718$1448_Y + connect \$109 $ne$libresoc.v:48719$1449_Y + connect \$111 $pos$libresoc.v:48720$1451_Y + connect \$113 $pos$libresoc.v:48721$1453_Y + connect \$117 $sub$libresoc.v:48722$1454_Y + connect \$121 $add$libresoc.v:48723$1455_Y + connect \$12 $not$libresoc.v:48724$1456_Y + connect \$14 $and$libresoc.v:48725$1457_Y + connect \$17 $add$libresoc.v:48726$1458_Y + connect \$19 $not$libresoc.v:48727$1459_Y + connect \$21 $not$libresoc.v:48728$1460_Y + connect \$23 $not$libresoc.v:48729$1461_Y + connect \$25 $not$libresoc.v:48730$1462_Y + connect \$27 $not$libresoc.v:48731$1463_Y + connect \$29 $not$libresoc.v:48732$1464_Y + connect \$31 $not$libresoc.v:48733$1465_Y + connect \$33 $and$libresoc.v:48734$1466_Y + connect \$36 $and$libresoc.v:48735$1467_Y + connect \$35 $reduce_or$libresoc.v:48736$1468_Y + connect \$3 $ne$libresoc.v:48737$1469_Y + connect \$41 $not$libresoc.v:48738$1470_Y + connect \$43 $not$libresoc.v:48739$1471_Y + connect \$45 $not$libresoc.v:48740$1472_Y + connect \$47 $not$libresoc.v:48741$1473_Y + connect \$49 $not$libresoc.v:48742$1474_Y + connect \$51 $and$libresoc.v:48743$1475_Y + connect \$53 $not$libresoc.v:48744$1476_Y + connect \$55 $not$libresoc.v:48745$1477_Y + connect \$57 $and$libresoc.v:48746$1478_Y + connect \$59 $not$libresoc.v:48747$1479_Y + connect \$61 $not$libresoc.v:48748$1480_Y + connect \$63 $and$libresoc.v:48749$1481_Y + connect \$65 $not$libresoc.v:48750$1482_Y + connect \$67 $not$libresoc.v:48751$1483_Y + connect \$6 $sub$libresoc.v:48752$1484_Y + connect \$69 $and$libresoc.v:48753$1485_Y + connect \$71 $not$libresoc.v:48754$1486_Y + connect \$73 $not$libresoc.v:48755$1487_Y + connect \$75 $and$libresoc.v:48756$1488_Y + connect \$77 $not$libresoc.v:48757$1489_Y + connect \$79 $not$libresoc.v:48758$1490_Y + connect \$81 $not$libresoc.v:48759$1491_Y + connect \$83 $and$libresoc.v:48760$1492_Y + connect \$85 $not$libresoc.v:48761$1493_Y + connect \$87 $not$libresoc.v:48762$1494_Y + connect \$8 $or$libresoc.v:48763$1495_Y + connect \$89 $not$libresoc.v:48764$1496_Y + connect \$91 $and$libresoc.v:48765$1497_Y + connect \$93 $not$libresoc.v:48766$1498_Y + connect \$95 $not$libresoc.v:48767$1499_Y + connect \$97 $and$libresoc.v:48768$1500_Y + connect \$5 \$6 + connect \$16 \$17 + connect \$116 \$117 + connect \$120 \$121 + connect \intclk_clk 1'0 + connect \intclk_rst 1'0 + connect \corebusy_o 1'0 + connect \cu_st__rel_o 1'0 + connect \cu_ad__rel_o 1'0 + connect \cia__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \core_terminate_o 1'0 + connect \state_nia_wen 4'0000 + connect \msr__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \dmi__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \full_rd2__data_o 0 + connect \full_rd__data_o 6'000000 + connect \issue__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \dbg_core_dbg_msr \dec2_cur_msr + connect \dbg_core_dbg_pc \pc + connect \dbg_terminate_i 1'0 + connect \nia \$17 [63:0] + connect \pc_o \dec2_cur_pc + connect \cu_st__go_i \cu_st__rel_o_rise + connect \cu_ad__go_i 1'0 + connect \cu_st__rel_o_rise \$14 + connect \cu_st__rel_o_dly$next 1'0 + connect \dec2_bigendian \core_bigendian_i + connect \busy_o 1'0 + connect \core_reset_i \$10 + connect \coresync_clk 1'0 + connect \por_clk 1'0 + connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src } +end +attribute \src "libresoc.v:50184.1-50498.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.xics_icp" +attribute \generator "nMigen" +module \xics_icp + attribute \src "libresoc.v:50362.3-50390.6" + wire width 32 $0\be_out[31:0] + attribute \src "libresoc.v:50413.3-50421.6" + wire $0\core_irq_o$next[0:0]$2061 + attribute \src "libresoc.v:50304.3-50305.37" + wire $0\core_irq_o[0:0] + attribute \src "libresoc.v:50432.3-50494.6" + wire width 8 $0\cppr$10[7:0]$2065 + attribute \src "libresoc.v:50318.3-50333.6" + wire width 8 $0\cppr$next[7:0]$2044 + attribute \src "libresoc.v:50308.3-50309.25" + wire width 8 $0\cppr[7:0] + attribute \src "libresoc.v:50422.3-50431.6" + wire width 32 $0\icp_wb__dat_r[31:0] + attribute \src "libresoc.v:50185.7-50185.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:50432.3-50494.6" + wire $0\irq$12[0:0]$2066 + attribute \src "libresoc.v:50318.3-50333.6" + wire $0\irq$next[0:0]$2045 + attribute \src "libresoc.v:50312.3-50313.23" + wire $0\irq[0:0] + attribute \src "libresoc.v:50432.3-50494.6" + wire width 8 $0\mfrr$11[7:0]$2067 + attribute \src "libresoc.v:50318.3-50333.6" + wire width 8 $0\mfrr$next[7:0]$2046 + attribute \src "libresoc.v:50310.3-50311.25" + wire width 8 $0\mfrr[7:0] + attribute \src "libresoc.v:50401.3-50412.6" + wire width 8 $0\min_pri[7:0] + attribute \src "libresoc.v:50391.3-50400.6" + wire width 8 $0\pending_priority[7:0] + attribute \src "libresoc.v:50432.3-50494.6" + wire $0\wb_ack$14[0:0]$2068 + attribute \src "libresoc.v:50318.3-50333.6" + wire $0\wb_ack$next[0:0]$2047 + attribute \src "libresoc.v:50316.3-50317.29" + wire $0\wb_ack[0:0] + attribute \src "libresoc.v:50432.3-50494.6" + wire width 32 $0\wb_rd_data$13[31:0]$2069 + attribute \src "libresoc.v:50318.3-50333.6" + wire width 32 $0\wb_rd_data$next[31:0]$2048 + attribute \src "libresoc.v:50314.3-50315.37" + wire width 32 $0\wb_rd_data[31:0] + attribute \src "libresoc.v:50334.3-50361.6" + wire $0\xirr_accept_rd[0:0] + attribute \src "libresoc.v:50432.3-50494.6" + wire width 24 $0\xisr$9[23:0]$2070 + attribute \src "libresoc.v:50318.3-50333.6" + wire width 24 $0\xisr$next[23:0]$2049 + attribute \src "libresoc.v:50306.3-50307.25" + wire width 24 $0\xisr[23:0] + attribute \src "libresoc.v:50362.3-50390.6" + wire width 32 $1\be_out[31:0] + attribute \src "libresoc.v:50413.3-50421.6" + wire $1\core_irq_o$next[0:0]$2062 + attribute \src "libresoc.v:50212.7-50212.24" + wire $1\core_irq_o[0:0] + attribute \src "libresoc.v:50432.3-50494.6" + wire width 8 $1\cppr$10[7:0]$2071 + attribute \src "libresoc.v:50318.3-50333.6" + wire width 8 $1\cppr$next[7:0]$2050 + attribute \src "libresoc.v:50216.13-50216.25" + wire width 8 $1\cppr[7:0] + attribute \src "libresoc.v:50422.3-50431.6" + wire width 32 $1\icp_wb__dat_r[31:0] + attribute \src "libresoc.v:50432.3-50494.6" + wire $1\irq$12[0:0]$2081 + attribute \src "libresoc.v:50318.3-50333.6" + wire $1\irq$next[0:0]$2051 + attribute \src "libresoc.v:50249.7-50249.17" + wire $1\irq[0:0] + attribute \src "libresoc.v:50432.3-50494.6" + wire width 8 $1\mfrr$11[7:0]$2072 + attribute \src "libresoc.v:50318.3-50333.6" + wire width 8 $1\mfrr$next[7:0]$2052 + attribute \src "libresoc.v:50257.13-50257.25" + wire width 8 $1\mfrr[7:0] + attribute \src "libresoc.v:50401.3-50412.6" + wire width 8 $1\min_pri[7:0] + attribute \src "libresoc.v:50391.3-50400.6" + wire width 8 $1\pending_priority[7:0] + attribute \src "libresoc.v:50432.3-50494.6" + wire $1\wb_ack$14[0:0]$2073 + attribute \src "libresoc.v:50318.3-50333.6" + wire $1\wb_ack$next[0:0]$2053 + attribute \src "libresoc.v:50269.7-50269.20" + wire $1\wb_ack[0:0] + attribute \src "libresoc.v:50318.3-50333.6" + wire width 32 $1\wb_rd_data$next[31:0]$2054 + attribute \src "libresoc.v:50277.14-50277.32" + wire width 32 $1\wb_rd_data[31:0] + attribute \src "libresoc.v:50334.3-50361.6" + wire $1\xirr_accept_rd[0:0] + attribute \src "libresoc.v:50432.3-50494.6" + wire width 24 $1\xisr$9[23:0]$2078 + attribute \src "libresoc.v:50318.3-50333.6" + wire width 24 $1\xisr$next[23:0]$2055 + attribute \src "libresoc.v:50287.14-50287.31" + wire width 24 $1\xisr[23:0] + attribute \src "libresoc.v:50362.3-50390.6" + wire width 32 $2\be_out[31:0] + attribute \src "libresoc.v:50432.3-50494.6" + wire width 8 $2\cppr$10[7:0]$2074 + attribute \src "libresoc.v:50432.3-50494.6" + wire width 8 $2\mfrr$11[7:0]$2075 + attribute \src "libresoc.v:50334.3-50361.6" + wire $2\xirr_accept_rd[0:0] + attribute \src "libresoc.v:50432.3-50494.6" + wire width 24 $2\xisr$9[23:0]$2079 + attribute \src "libresoc.v:50362.3-50390.6" + wire width 32 $3\be_out[31:0] + attribute \src "libresoc.v:50432.3-50494.6" + wire width 8 $3\cppr$10[7:0]$2076 + attribute \src "libresoc.v:50432.3-50494.6" + wire width 8 $3\mfrr$11[7:0]$2077 + attribute \src "libresoc.v:50334.3-50361.6" + wire $3\xirr_accept_rd[0:0] + attribute \src "libresoc.v:50432.3-50494.6" + wire width 8 $4\cppr$10[7:0]$2080 + attribute \src "libresoc.v:50334.3-50361.6" + wire $4\xirr_accept_rd[0:0] + attribute \src "libresoc.v:50294.18-50294.116" + wire $and$libresoc.v:50294$2026_Y + attribute \src "libresoc.v:50298.18-50298.116" + wire $and$libresoc.v:50298$2030_Y + attribute \src "libresoc.v:50300.18-50300.116" + wire $and$libresoc.v:50300$2032_Y + attribute \src "libresoc.v:50303.17-50303.109" + wire $and$libresoc.v:50303$2035_Y + attribute \src "libresoc.v:50299.18-50299.110" + wire $eq$libresoc.v:50299$2031_Y + attribute \src "libresoc.v:50296.18-50296.114" + wire $lt$libresoc.v:50296$2028_Y + attribute \src "libresoc.v:50297.18-50297.109" + wire $lt$libresoc.v:50297$2029_Y + attribute \src "libresoc.v:50302.18-50302.114" + wire $lt$libresoc.v:50302$2034_Y + attribute \src "libresoc.v:50295.18-50295.109" + wire $ne$libresoc.v:50295$2027_Y + attribute \src "libresoc.v:50301.18-50301.109" + wire $ne$libresoc.v:50301$2033_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:103" + wire width 32 \be_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" + wire width 32 \be_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" + wire output 2 \core_irq_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" + wire \core_irq_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 5 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 11 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 6 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 7 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 8 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 12 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 9 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 10 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 input 1 \ics_i_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 input 13 \ics_i_src + attribute \src "libresoc.v:50185.7-50185.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" + wire input 3 \intclk_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" + wire input 4 \intclk_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:107" + wire width 8 \min_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" + wire width 8 \pending_priority + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:101" + wire \xirr_accept_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + cell $and $and$libresoc.v:50294$2026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \icp_wb__cyc + connect \B \icp_wb__stb + connect \Y $and$libresoc.v:50294$2026_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + cell $and $and$libresoc.v:50298$2030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \icp_wb__cyc + connect \B \icp_wb__stb + connect \Y $and$libresoc.v:50298$2030_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + cell $and $and$libresoc.v:50300$2032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \icp_wb__cyc + connect \B \icp_wb__stb + connect \Y $and$libresoc.v:50300$2032_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" + cell $and $and$libresoc.v:50303$2035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wb_ack + connect \B \icp_wb__cyc + connect \Y $and$libresoc.v:50303$2035_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" + cell $eq $eq$libresoc.v:50299$2031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \icp_wb__sel + connect \B 4'1111 + connect \Y $eq$libresoc.v:50299$2031_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + cell $lt $lt$libresoc.v:50296$2028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \mfrr + connect \B \pending_priority + connect \Y $lt$libresoc.v:50296$2028_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" + cell $lt $lt$libresoc.v:50297$2029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \min_pri + connect \B \cppr$10 + connect \Y $lt$libresoc.v:50297$2029_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + cell $lt $lt$libresoc.v:50302$2034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \mfrr + connect \B \pending_priority + connect \Y $lt$libresoc.v:50302$2034_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + cell $ne $ne$libresoc.v:50295$2027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ics_i_pri + connect \B 8'11111111 + connect \Y $ne$libresoc.v:50295$2027_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + cell $ne $ne$libresoc.v:50301$2033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ics_i_pri + connect \B 8'11111111 + connect \Y $ne$libresoc.v:50301$2033_Y + end + attribute \src "libresoc.v:50185.7-50185.20" + process $proc$libresoc.v:50185$2082 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:50212.7-50212.24" + process $proc$libresoc.v:50212$2083 + assign { } { } + assign $1\core_irq_o[0:0] 1'0 + sync always + sync init + update \core_irq_o $1\core_irq_o[0:0] + end + attribute \src "libresoc.v:50216.13-50216.25" + process $proc$libresoc.v:50216$2084 + assign { } { } + assign $1\cppr[7:0] 8'00000000 + sync always + sync init + update \cppr $1\cppr[7:0] + end + attribute \src "libresoc.v:50249.7-50249.17" + process $proc$libresoc.v:50249$2085 + assign { } { } + assign $1\irq[0:0] 1'0 + sync always + sync init + update \irq $1\irq[0:0] + end + attribute \src "libresoc.v:50257.13-50257.25" + process $proc$libresoc.v:50257$2086 + assign { } { } + assign $1\mfrr[7:0] 8'11111111 + sync always + sync init + update \mfrr $1\mfrr[7:0] + end + attribute \src "libresoc.v:50269.7-50269.20" + process $proc$libresoc.v:50269$2087 + assign { } { } + assign $1\wb_ack[0:0] 1'0 + sync always + sync init + update \wb_ack $1\wb_ack[0:0] + end + attribute \src "libresoc.v:50277.14-50277.32" + process $proc$libresoc.v:50277$2088 + assign { } { } + assign $1\wb_rd_data[31:0] 0 + sync always + sync init + update \wb_rd_data $1\wb_rd_data[31:0] + end + attribute \src "libresoc.v:50287.14-50287.31" + process $proc$libresoc.v:50287$2089 + assign { } { } + assign $1\xisr[23:0] 24'000000000000000000000000 + sync always + sync init + update \xisr $1\xisr[23:0] + end + attribute \src "libresoc.v:50304.3-50305.37" + process $proc$libresoc.v:50304$2036 + assign { } { } + assign $0\core_irq_o[0:0] \core_irq_o$next + sync posedge \intclk_clk + update \core_irq_o $0\core_irq_o[0:0] + end + attribute \src "libresoc.v:50306.3-50307.25" + process $proc$libresoc.v:50306$2037 + assign { } { } + assign $0\xisr[23:0] \xisr$next + sync posedge \intclk_clk + update \xisr $0\xisr[23:0] + end + attribute \src "libresoc.v:50308.3-50309.25" + process $proc$libresoc.v:50308$2038 + assign { } { } + assign $0\cppr[7:0] \cppr$next + sync posedge \intclk_clk + update \cppr $0\cppr[7:0] + end + attribute \src "libresoc.v:50310.3-50311.25" + process $proc$libresoc.v:50310$2039 + assign { } { } + assign $0\mfrr[7:0] \mfrr$next + sync posedge \intclk_clk + update \mfrr $0\mfrr[7:0] + end + attribute \src "libresoc.v:50312.3-50313.23" + process $proc$libresoc.v:50312$2040 + assign { } { } + assign $0\irq[0:0] \irq$next + sync posedge \intclk_clk + update \irq $0\irq[0:0] + end + attribute \src "libresoc.v:50314.3-50315.37" + process $proc$libresoc.v:50314$2041 + assign { } { } + assign $0\wb_rd_data[31:0] \wb_rd_data$next + sync posedge \intclk_clk + update \wb_rd_data $0\wb_rd_data[31:0] + end + attribute \src "libresoc.v:50316.3-50317.29" + process $proc$libresoc.v:50316$2042 + assign { } { } + assign $0\wb_ack[0:0] \wb_ack$next + sync posedge \intclk_clk + update \wb_ack $0\wb_ack[0:0] + end + attribute \src "libresoc.v:50318.3-50333.6" + process $proc$libresoc.v:50318$2043 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cppr$next[7:0]$2044 $1\cppr$next[7:0]$2050 + assign $0\irq$next[0:0]$2045 $1\irq$next[0:0]$2051 + assign $0\mfrr$next[7:0]$2046 $1\mfrr$next[7:0]$2052 + assign $0\wb_ack$next[0:0]$2047 $1\wb_ack$next[0:0]$2053 + assign $0\wb_rd_data$next[31:0]$2048 $1\wb_rd_data$next[31:0]$2054 + assign $0\xisr$next[23:0]$2049 $1\xisr$next[23:0]$2055 + attribute \src "libresoc.v:50319.5-50319.29" + switch \initial + attribute \src "libresoc.v:50319.9-50319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\xisr$next[23:0]$2055 24'000000000000000000000000 + assign $1\cppr$next[7:0]$2050 8'00000000 + assign $1\mfrr$next[7:0]$2052 8'11111111 + assign $1\irq$next[0:0]$2051 1'0 + assign $1\wb_rd_data$next[31:0]$2054 0 + assign $1\wb_ack$next[0:0]$2053 1'0 + case + assign $1\cppr$next[7:0]$2050 \cppr$2 + assign $1\irq$next[0:0]$2051 \irq$4 + assign $1\mfrr$next[7:0]$2052 \mfrr$3 + assign $1\wb_ack$next[0:0]$2053 \wb_ack$6 + assign $1\wb_rd_data$next[31:0]$2054 \wb_rd_data$5 + assign $1\xisr$next[23:0]$2055 \xisr$1 + end + sync always + update \cppr$next $0\cppr$next[7:0]$2044 + update \irq$next $0\irq$next[0:0]$2045 + update \mfrr$next $0\mfrr$next[7:0]$2046 + update \wb_ack$next $0\wb_ack$next[0:0]$2047 + update \wb_rd_data$next $0\wb_rd_data$next[31:0]$2048 + update \xisr$next $0\xisr$next[23:0]$2049 + end + attribute \src "libresoc.v:50334.3-50361.6" + process $proc$libresoc.v:50334$2056 + assign { } { } + assign { } { } + assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0] + attribute \src "libresoc.v:50335.5-50335.29" + switch \initial + attribute \src "libresoc.v:50335.9-50335.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xirr_accept_rd[0:0] $2\xirr_accept_rd[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" + switch \icp_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\xirr_accept_rd[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\xirr_accept_rd[0:0] $3\xirr_accept_rd[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" + switch \icp_wb__adr [5:0] + attribute \src "libresoc.v:0.0-0.0" + case 6'000001 + assign { } { } + assign $3\xirr_accept_rd[0:0] $4\xirr_accept_rd[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\xirr_accept_rd[0:0] 1'1 + case + assign $4\xirr_accept_rd[0:0] 1'0 + end + case + assign $3\xirr_accept_rd[0:0] 1'0 + end + end + case + assign $1\xirr_accept_rd[0:0] 1'0 + end + sync always + update \xirr_accept_rd $0\xirr_accept_rd[0:0] + end + attribute \src "libresoc.v:50362.3-50390.6" + process $proc$libresoc.v:50362$2057 + assign { } { } + assign { } { } + assign $0\be_out[31:0] $1\be_out[31:0] + attribute \src "libresoc.v:50363.5-50363.29" + switch \initial + attribute \src "libresoc.v:50363.9-50363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\be_out[31:0] $2\be_out[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" + switch \icp_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\be_out[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\be_out[31:0] $3\be_out[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" + switch \icp_wb__adr [5:0] + attribute \src "libresoc.v:0.0-0.0" + case 6'000000 + assign { } { } + assign $3\be_out[31:0] { \cppr \xisr } + attribute \src "libresoc.v:0.0-0.0" + case 6'000001 + assign { } { } + assign $3\be_out[31:0] { \cppr \xisr } + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign $3\be_out[31:0] [23:0] 24'000000000000000000000000 + assign $3\be_out[31:0] [31:24] \mfrr + case + assign $3\be_out[31:0] 0 + end + end + case + assign $1\be_out[31:0] 0 + end + sync always + update \be_out $0\be_out[31:0] + end + attribute \src "libresoc.v:50391.3-50400.6" + process $proc$libresoc.v:50391$2058 + assign { } { } + assign { } { } + assign $0\pending_priority[7:0] $1\pending_priority[7:0] + attribute \src "libresoc.v:50392.5-50392.29" + switch \initial + attribute \src "libresoc.v:50392.9-50392.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pending_priority[7:0] \ics_i_pri + case + assign $1\pending_priority[7:0] 8'11111111 + end + sync always + update \pending_priority $0\pending_priority[7:0] + end + attribute \src "libresoc.v:50401.3-50412.6" + process $proc$libresoc.v:50401$2059 + assign { } { } + assign $0\min_pri[7:0] $1\min_pri[7:0] + attribute \src "libresoc.v:50402.5-50402.29" + switch \initial + attribute \src "libresoc.v:50402.9-50402.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\min_pri[7:0] \mfrr + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\min_pri[7:0] \pending_priority + end + sync always + update \min_pri $0\min_pri[7:0] + end + attribute \src "libresoc.v:50413.3-50421.6" + process $proc$libresoc.v:50413$2060 + assign { } { } + assign { } { } + assign $0\core_irq_o$next[0:0]$2061 $1\core_irq_o$next[0:0]$2062 + attribute \src "libresoc.v:50414.5-50414.29" + switch \initial + attribute \src "libresoc.v:50414.9-50414.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_irq_o$next[0:0]$2062 1'0 + case + assign $1\core_irq_o$next[0:0]$2062 \irq + end + sync always + update \core_irq_o$next $0\core_irq_o$next[0:0]$2061 + end + attribute \src "libresoc.v:50422.3-50431.6" + process $proc$libresoc.v:50422$2063 + assign { } { } + assign { } { } + assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0] + attribute \src "libresoc.v:50423.5-50423.29" + switch \initial + attribute \src "libresoc.v:50423.9-50423.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:97" + switch \icp_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\icp_wb__dat_r[31:0] \wb_rd_data + case + assign $1\icp_wb__dat_r[31:0] 0 + end + sync always + update \icp_wb__dat_r $0\icp_wb__dat_r[31:0] + end + attribute \src "libresoc.v:50432.3-50494.6" + process $proc$libresoc.v:50432$2064 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mfrr$11[7:0]$2067 $1\mfrr$11[7:0]$2072 + assign $0\wb_ack$14[0:0]$2068 $1\wb_ack$14[0:0]$2073 + assign { } { } + assign { } { } + assign { } { } + assign $0\xisr$9[23:0]$2070 $2\xisr$9[23:0]$2079 + assign $0\cppr$10[7:0]$2065 $4\cppr$10[7:0]$2080 + assign $0\wb_rd_data$13[31:0]$2069 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $0\irq$12[0:0]$2066 $1\irq$12[0:0]$2081 + attribute \src "libresoc.v:50433.5-50433.29" + switch \initial + attribute \src "libresoc.v:50433.9-50433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1\wb_ack$14[0:0]$2073 1'1 + assign $1\cppr$10[7:0]$2071 $2\cppr$10[7:0]$2074 + assign $1\mfrr$11[7:0]$2072 $2\mfrr$11[7:0]$2075 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" + switch \icp_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\cppr$10[7:0]$2074 $3\cppr$10[7:0]$2076 + assign $2\mfrr$11[7:0]$2075 $3\mfrr$11[7:0]$2077 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" + switch \icp_wb__adr [5:0] + attribute \src "libresoc.v:0.0-0.0" + case 6'000000 + assign { } { } + assign $3\mfrr$11[7:0]$2077 \mfrr + assign $3\cppr$10[7:0]$2076 \be_in [31:24] + attribute \src "libresoc.v:0.0-0.0" + case 6'000001 + assign { } { } + assign $3\mfrr$11[7:0]$2077 \mfrr + assign $3\cppr$10[7:0]$2076 \be_in [31:24] + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign $3\cppr$10[7:0]$2076 \cppr + assign { } { } + assign $3\mfrr$11[7:0]$2077 \be_in [31:24] + case + assign $3\cppr$10[7:0]$2076 \cppr + assign $3\mfrr$11[7:0]$2077 \mfrr + end + case + assign $2\cppr$10[7:0]$2074 \cppr + assign $2\mfrr$11[7:0]$2075 \mfrr + end + case + assign $1\cppr$10[7:0]$2071 \cppr + assign $1\mfrr$11[7:0]$2072 \mfrr + assign $1\wb_ack$14[0:0]$2073 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xisr$9[23:0]$2078 { 20'00000000000000000001 \ics_i_src } + case + assign $1\xisr$9[23:0]$2078 24'000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xisr$9[23:0]$2079 24'000000000000000000000010 + case + assign $2\xisr$9[23:0]$2079 $1\xisr$9[23:0]$2078 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" + switch \xirr_accept_rd + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cppr$10[7:0]$2080 \min_pri + case + assign $4\cppr$10[7:0]$2080 $1\cppr$10[7:0]$2071 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" + switch { \irq \$21 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\irq$12[0:0]$2081 1'1 + case + assign $1\irq$12[0:0]$2081 1'0 + end + sync always + update \cppr$10 $0\cppr$10[7:0]$2065 + update \irq$12 $0\irq$12[0:0]$2066 + update \mfrr$11 $0\mfrr$11[7:0]$2067 + update \wb_ack$14 $0\wb_ack$14[0:0]$2068 + update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$2069 + update \xisr$9 $0\xisr$9[23:0]$2070 + end + connect \$15 $and$libresoc.v:50294$2026_Y + connect \$17 $ne$libresoc.v:50295$2027_Y + connect \$19 $lt$libresoc.v:50296$2028_Y + connect \$21 $lt$libresoc.v:50297$2029_Y + connect \$23 $and$libresoc.v:50298$2030_Y + connect \$25 $eq$libresoc.v:50299$2031_Y + connect \$27 $and$libresoc.v:50300$2032_Y + connect \$29 $ne$libresoc.v:50301$2033_Y + connect \$31 $lt$libresoc.v:50302$2034_Y + connect \$7 $and$libresoc.v:50303$2035_Y + connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 } + connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] } + connect \icp_wb__ack \$7 +end +attribute \src "libresoc.v:50502.1-51551.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.xics_ics" +attribute \generator "nMigen" +module \xics_ics + attribute \src "libresoc.v:51432.3-51481.6" + wire width 32 $0\be_out[31:0] + attribute \src "libresoc.v:51143.3-51152.6" + wire width 4 $0\cur_idx0[3:0] + attribute \src "libresoc.v:51352.3-51361.6" + wire width 4 $0\cur_idx10[3:0] + attribute \src "libresoc.v:51372.3-51381.6" + wire width 4 $0\cur_idx11[3:0] + attribute \src "libresoc.v:51392.3-51401.6" + wire width 4 $0\cur_idx12[3:0] + attribute \src "libresoc.v:51412.3-51421.6" + wire width 4 $0\cur_idx13[3:0] + attribute \src "libresoc.v:51482.3-51491.6" + wire width 4 $0\cur_idx14[3:0] + attribute \src "libresoc.v:51502.3-51511.6" + wire width 4 $0\cur_idx15[3:0] + attribute \src "libresoc.v:51163.3-51172.6" + wire width 4 $0\cur_idx1[3:0] + attribute \src "libresoc.v:51183.3-51192.6" + wire width 4 $0\cur_idx2[3:0] + attribute \src "libresoc.v:51203.3-51212.6" + wire width 4 $0\cur_idx3[3:0] + attribute \src "libresoc.v:51232.3-51241.6" + wire width 4 $0\cur_idx4[3:0] + attribute \src "libresoc.v:51252.3-51261.6" + wire width 4 $0\cur_idx5[3:0] + attribute \src "libresoc.v:51272.3-51281.6" + wire width 4 $0\cur_idx6[3:0] + attribute \src "libresoc.v:51292.3-51301.6" + wire width 4 $0\cur_idx7[3:0] + attribute \src "libresoc.v:51312.3-51321.6" + wire width 4 $0\cur_idx8[3:0] + attribute \src "libresoc.v:51332.3-51341.6" + wire width 4 $0\cur_idx9[3:0] + attribute \src "libresoc.v:51133.3-51142.6" + wire width 8 $0\cur_pri0[7:0] + attribute \src "libresoc.v:51342.3-51351.6" + wire width 8 $0\cur_pri10[7:0] + attribute \src "libresoc.v:51362.3-51371.6" + wire width 8 $0\cur_pri11[7:0] + attribute \src "libresoc.v:51382.3-51391.6" + wire width 8 $0\cur_pri12[7:0] + attribute \src "libresoc.v:51402.3-51411.6" + wire width 8 $0\cur_pri13[7:0] + attribute \src "libresoc.v:51422.3-51431.6" + wire width 8 $0\cur_pri14[7:0] + attribute \src "libresoc.v:51492.3-51501.6" + wire width 8 $0\cur_pri15[7:0] + attribute \src "libresoc.v:51153.3-51162.6" + wire width 8 $0\cur_pri1[7:0] + attribute \src "libresoc.v:51173.3-51182.6" + wire width 8 $0\cur_pri2[7:0] + attribute \src "libresoc.v:51193.3-51202.6" + wire width 8 $0\cur_pri3[7:0] + attribute \src "libresoc.v:51213.3-51222.6" + wire width 8 $0\cur_pri4[7:0] + attribute \src "libresoc.v:51242.3-51251.6" + wire width 8 $0\cur_pri5[7:0] + attribute \src "libresoc.v:51262.3-51271.6" + wire width 8 $0\cur_pri6[7:0] + attribute \src "libresoc.v:51282.3-51291.6" + wire width 8 $0\cur_pri7[7:0] + attribute \src "libresoc.v:51302.3-51311.6" + wire width 8 $0\cur_pri8[7:0] + attribute \src "libresoc.v:51322.3-51331.6" + wire width 8 $0\cur_pri9[7:0] + attribute \src "libresoc.v:51512.3-51521.6" + wire $0\ibit[0:0] + attribute \src "libresoc.v:51017.3-51018.25" + wire width 8 $0\icp_o_pri[7:0] + attribute \src "libresoc.v:51015.3-51016.28" + wire width 4 $0\icp_o_src[3:0] + attribute \src "libresoc.v:51531.3-51539.6" + wire $0\ics_wb__ack$next[0:0]$2336 + attribute \src "libresoc.v:51009.3-51010.39" + wire $0\ics_wb__ack[0:0] + attribute \src "libresoc.v:51522.3-51530.6" + wire width 32 $0\ics_wb__dat_r$next[31:0]$2333 + attribute \src "libresoc.v:51011.3-51012.43" + wire width 32 $0\ics_wb__dat_r[31:0] + attribute \src "libresoc.v:50503.7-50503.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:51223.3-51231.6" + wire width 16 $0\int_level_l$next[15:0]$2305 + attribute \src "libresoc.v:51013.3-51014.39" + wire width 16 $0\int_level_l[15:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $0\xive0_pri$next[7:0]$2215 + attribute \src "libresoc.v:51019.3-51020.35" + wire width 8 $0\xive0_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $0\xive10_pri$next[7:0]$2216 + attribute \src "libresoc.v:51039.3-51040.37" + wire width 8 $0\xive10_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $0\xive11_pri$next[7:0]$2217 + attribute \src "libresoc.v:51041.3-51042.37" + wire width 8 $0\xive11_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $0\xive12_pri$next[7:0]$2218 + attribute \src "libresoc.v:51043.3-51044.37" + wire width 8 $0\xive12_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $0\xive13_pri$next[7:0]$2219 + attribute \src "libresoc.v:51045.3-51046.37" + wire width 8 $0\xive13_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $0\xive14_pri$next[7:0]$2220 + attribute \src "libresoc.v:51005.3-51006.37" + wire width 8 $0\xive14_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $0\xive15_pri$next[7:0]$2221 + attribute \src "libresoc.v:51007.3-51008.37" + wire width 8 $0\xive15_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $0\xive1_pri$next[7:0]$2222 + attribute \src "libresoc.v:51021.3-51022.35" + wire width 8 $0\xive1_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $0\xive2_pri$next[7:0]$2223 + attribute \src "libresoc.v:51023.3-51024.35" + wire width 8 $0\xive2_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $0\xive3_pri$next[7:0]$2224 + attribute \src "libresoc.v:51025.3-51026.35" + wire width 8 $0\xive3_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $0\xive4_pri$next[7:0]$2225 + attribute \src "libresoc.v:51027.3-51028.35" + wire width 8 $0\xive4_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $0\xive5_pri$next[7:0]$2226 + attribute \src "libresoc.v:51029.3-51030.35" + wire width 8 $0\xive5_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $0\xive6_pri$next[7:0]$2227 + attribute \src "libresoc.v:51031.3-51032.35" + wire width 8 $0\xive6_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $0\xive7_pri$next[7:0]$2228 + attribute \src "libresoc.v:51033.3-51034.35" + wire width 8 $0\xive7_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $0\xive8_pri$next[7:0]$2229 + attribute \src "libresoc.v:51035.3-51036.35" + wire width 8 $0\xive8_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $0\xive9_pri$next[7:0]$2230 + attribute \src "libresoc.v:51037.3-51038.35" + wire width 8 $0\xive9_pri[7:0] + attribute \src "libresoc.v:51432.3-51481.6" + wire width 32 $1\be_out[31:0] + attribute \src "libresoc.v:51143.3-51152.6" + wire width 4 $1\cur_idx0[3:0] + attribute \src "libresoc.v:51352.3-51361.6" + wire width 4 $1\cur_idx10[3:0] + attribute \src "libresoc.v:51372.3-51381.6" + wire width 4 $1\cur_idx11[3:0] + attribute \src "libresoc.v:51392.3-51401.6" + wire width 4 $1\cur_idx12[3:0] + attribute \src "libresoc.v:51412.3-51421.6" + wire width 4 $1\cur_idx13[3:0] + attribute \src "libresoc.v:51482.3-51491.6" + wire width 4 $1\cur_idx14[3:0] + attribute \src "libresoc.v:51502.3-51511.6" + wire width 4 $1\cur_idx15[3:0] + attribute \src "libresoc.v:51163.3-51172.6" + wire width 4 $1\cur_idx1[3:0] + attribute \src "libresoc.v:51183.3-51192.6" + wire width 4 $1\cur_idx2[3:0] + attribute \src "libresoc.v:51203.3-51212.6" + wire width 4 $1\cur_idx3[3:0] + attribute \src "libresoc.v:51232.3-51241.6" + wire width 4 $1\cur_idx4[3:0] + attribute \src "libresoc.v:51252.3-51261.6" + wire width 4 $1\cur_idx5[3:0] + attribute \src "libresoc.v:51272.3-51281.6" + wire width 4 $1\cur_idx6[3:0] + attribute \src "libresoc.v:51292.3-51301.6" + wire width 4 $1\cur_idx7[3:0] + attribute \src "libresoc.v:51312.3-51321.6" + wire width 4 $1\cur_idx8[3:0] + attribute \src "libresoc.v:51332.3-51341.6" + wire width 4 $1\cur_idx9[3:0] + attribute \src "libresoc.v:51133.3-51142.6" + wire width 8 $1\cur_pri0[7:0] + attribute \src "libresoc.v:51342.3-51351.6" + wire width 8 $1\cur_pri10[7:0] + attribute \src "libresoc.v:51362.3-51371.6" + wire width 8 $1\cur_pri11[7:0] + attribute \src "libresoc.v:51382.3-51391.6" + wire width 8 $1\cur_pri12[7:0] + attribute \src "libresoc.v:51402.3-51411.6" + wire width 8 $1\cur_pri13[7:0] + attribute \src "libresoc.v:51422.3-51431.6" + wire width 8 $1\cur_pri14[7:0] + attribute \src "libresoc.v:51492.3-51501.6" + wire width 8 $1\cur_pri15[7:0] + attribute \src "libresoc.v:51153.3-51162.6" + wire width 8 $1\cur_pri1[7:0] + attribute \src "libresoc.v:51173.3-51182.6" + wire width 8 $1\cur_pri2[7:0] + attribute \src "libresoc.v:51193.3-51202.6" + wire width 8 $1\cur_pri3[7:0] + attribute \src "libresoc.v:51213.3-51222.6" + wire width 8 $1\cur_pri4[7:0] + attribute \src "libresoc.v:51242.3-51251.6" + wire width 8 $1\cur_pri5[7:0] + attribute \src "libresoc.v:51262.3-51271.6" + wire width 8 $1\cur_pri6[7:0] + attribute \src "libresoc.v:51282.3-51291.6" + wire width 8 $1\cur_pri7[7:0] + attribute \src "libresoc.v:51302.3-51311.6" + wire width 8 $1\cur_pri8[7:0] + attribute \src "libresoc.v:51322.3-51331.6" + wire width 8 $1\cur_pri9[7:0] + attribute \src "libresoc.v:51512.3-51521.6" + wire $1\ibit[0:0] + attribute \src "libresoc.v:50782.13-50782.30" + wire width 8 $1\icp_o_pri[7:0] + attribute \src "libresoc.v:50787.13-50787.29" + wire width 4 $1\icp_o_src[3:0] + attribute \src "libresoc.v:51531.3-51539.6" + wire $1\ics_wb__ack$next[0:0]$2337 + attribute \src "libresoc.v:50796.7-50796.25" + wire $1\ics_wb__ack[0:0] + attribute \src "libresoc.v:51522.3-51530.6" + wire width 32 $1\ics_wb__dat_r$next[31:0]$2334 + attribute \src "libresoc.v:50805.14-50805.35" + wire width 32 $1\ics_wb__dat_r[31:0] + attribute \src "libresoc.v:51223.3-51231.6" + wire width 16 $1\int_level_l$next[15:0]$2306 + attribute \src "libresoc.v:50817.14-50817.36" + wire width 16 $1\int_level_l[15:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $1\xive0_pri$next[7:0]$2231 + attribute \src "libresoc.v:50839.13-50839.30" + wire width 8 $1\xive0_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $1\xive10_pri$next[7:0]$2232 + attribute \src "libresoc.v:50843.13-50843.31" + wire width 8 $1\xive10_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $1\xive11_pri$next[7:0]$2233 + attribute \src "libresoc.v:50847.13-50847.31" + wire width 8 $1\xive11_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $1\xive12_pri$next[7:0]$2234 + attribute \src "libresoc.v:50851.13-50851.31" + wire width 8 $1\xive12_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $1\xive13_pri$next[7:0]$2235 + attribute \src "libresoc.v:50855.13-50855.31" + wire width 8 $1\xive13_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $1\xive14_pri$next[7:0]$2236 + attribute \src "libresoc.v:50859.13-50859.31" + wire width 8 $1\xive14_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $1\xive15_pri$next[7:0]$2237 + attribute \src "libresoc.v:50863.13-50863.31" + wire width 8 $1\xive15_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $1\xive1_pri$next[7:0]$2238 + attribute \src "libresoc.v:50867.13-50867.30" + wire width 8 $1\xive1_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $1\xive2_pri$next[7:0]$2239 + attribute \src "libresoc.v:50871.13-50871.30" + wire width 8 $1\xive2_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $1\xive3_pri$next[7:0]$2240 + attribute \src "libresoc.v:50875.13-50875.30" + wire width 8 $1\xive3_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $1\xive4_pri$next[7:0]$2241 + attribute \src "libresoc.v:50879.13-50879.30" + wire width 8 $1\xive4_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $1\xive5_pri$next[7:0]$2242 + attribute \src "libresoc.v:50883.13-50883.30" + wire width 8 $1\xive5_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $1\xive6_pri$next[7:0]$2243 + attribute \src "libresoc.v:50887.13-50887.30" + wire width 8 $1\xive6_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $1\xive7_pri$next[7:0]$2244 + attribute \src "libresoc.v:50891.13-50891.30" + wire width 8 $1\xive7_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $1\xive8_pri$next[7:0]$2245 + attribute \src "libresoc.v:50895.13-50895.30" + wire width 8 $1\xive8_pri[7:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $1\xive9_pri$next[7:0]$2246 + attribute \src "libresoc.v:50899.13-50899.30" + wire width 8 $1\xive9_pri[7:0] + attribute \src "libresoc.v:51432.3-51481.6" + wire width 32 $2\be_out[31:0] + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $2\xive0_pri$next[7:0]$2247 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $2\xive10_pri$next[7:0]$2248 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $2\xive11_pri$next[7:0]$2249 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $2\xive12_pri$next[7:0]$2250 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $2\xive13_pri$next[7:0]$2251 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $2\xive14_pri$next[7:0]$2252 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $2\xive15_pri$next[7:0]$2253 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $2\xive1_pri$next[7:0]$2254 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $2\xive2_pri$next[7:0]$2255 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $2\xive3_pri$next[7:0]$2256 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $2\xive4_pri$next[7:0]$2257 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $2\xive5_pri$next[7:0]$2258 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $2\xive6_pri$next[7:0]$2259 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $2\xive7_pri$next[7:0]$2260 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $2\xive8_pri$next[7:0]$2261 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $2\xive9_pri$next[7:0]$2262 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $3\xive0_pri$next[7:0]$2263 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $3\xive10_pri$next[7:0]$2264 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $3\xive11_pri$next[7:0]$2265 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $3\xive12_pri$next[7:0]$2266 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $3\xive13_pri$next[7:0]$2267 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $3\xive14_pri$next[7:0]$2268 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $3\xive15_pri$next[7:0]$2269 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $3\xive1_pri$next[7:0]$2270 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $3\xive2_pri$next[7:0]$2271 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $3\xive3_pri$next[7:0]$2272 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $3\xive4_pri$next[7:0]$2273 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $3\xive5_pri$next[7:0]$2274 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $3\xive6_pri$next[7:0]$2275 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $3\xive7_pri$next[7:0]$2276 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $3\xive8_pri$next[7:0]$2277 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $3\xive9_pri$next[7:0]$2278 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $4\xive0_pri$next[7:0]$2279 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $4\xive10_pri$next[7:0]$2280 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $4\xive11_pri$next[7:0]$2281 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $4\xive12_pri$next[7:0]$2282 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $4\xive13_pri$next[7:0]$2283 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $4\xive14_pri$next[7:0]$2284 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $4\xive15_pri$next[7:0]$2285 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $4\xive1_pri$next[7:0]$2286 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $4\xive2_pri$next[7:0]$2287 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $4\xive3_pri$next[7:0]$2288 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $4\xive4_pri$next[7:0]$2289 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $4\xive5_pri$next[7:0]$2290 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $4\xive6_pri$next[7:0]$2291 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $4\xive7_pri$next[7:0]$2292 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $4\xive8_pri$next[7:0]$2293 + attribute \src "libresoc.v:51047.3-51132.6" + wire width 8 $4\xive9_pri$next[7:0]$2294 + attribute \src "libresoc.v:50904.19-50904.113" + wire $and$libresoc.v:50904$2092_Y + attribute \src "libresoc.v:50906.19-50906.114" + wire $and$libresoc.v:50906$2094_Y + attribute \src "libresoc.v:50908.19-50908.114" + wire $and$libresoc.v:50908$2096_Y + attribute \src "libresoc.v:50910.19-50910.114" + wire $and$libresoc.v:50910$2098_Y + attribute \src "libresoc.v:50912.19-50912.114" + wire $and$libresoc.v:50912$2100_Y + attribute \src "libresoc.v:50914.19-50914.114" + wire $and$libresoc.v:50914$2102_Y + attribute \src "libresoc.v:50916.19-50916.114" + wire $and$libresoc.v:50916$2104_Y + attribute \src "libresoc.v:50919.19-50919.114" + wire $and$libresoc.v:50919$2107_Y + attribute \src "libresoc.v:50921.19-50921.114" + wire $and$libresoc.v:50921$2109_Y + attribute \src "libresoc.v:50923.19-50923.114" + wire $and$libresoc.v:50923$2111_Y + attribute \src "libresoc.v:50926.19-50926.114" + wire $and$libresoc.v:50926$2114_Y + attribute \src "libresoc.v:50928.19-50928.114" + wire $and$libresoc.v:50928$2116_Y + attribute \src "libresoc.v:50930.19-50930.114" + wire $and$libresoc.v:50930$2118_Y + attribute \src "libresoc.v:50932.19-50932.114" + wire $and$libresoc.v:50932$2120_Y + attribute \src "libresoc.v:50934.19-50934.115" + wire $and$libresoc.v:50934$2122_Y + attribute \src "libresoc.v:50936.19-50936.115" + wire $and$libresoc.v:50936$2124_Y + attribute \src "libresoc.v:50938.19-50938.115" + wire $and$libresoc.v:50938$2126_Y + attribute \src "libresoc.v:50941.19-50941.115" + wire $and$libresoc.v:50941$2129_Y + attribute \src "libresoc.v:50943.19-50943.115" + wire $and$libresoc.v:50943$2131_Y + attribute \src "libresoc.v:50945.19-50945.115" + wire $and$libresoc.v:50945$2133_Y + attribute \src "libresoc.v:50948.19-50948.115" + wire $and$libresoc.v:50948$2136_Y + attribute \src "libresoc.v:50950.19-50950.115" + wire $and$libresoc.v:50950$2138_Y + attribute \src "libresoc.v:50952.19-50952.115" + wire $and$libresoc.v:50952$2140_Y + attribute \src "libresoc.v:50954.19-50954.115" + wire $and$libresoc.v:50954$2142_Y + attribute \src "libresoc.v:50956.19-50956.115" + wire $and$libresoc.v:50956$2144_Y + attribute \src "libresoc.v:50959.19-50959.115" + wire $and$libresoc.v:50959$2147_Y + attribute \src "libresoc.v:50983.17-50983.115" + wire $and$libresoc.v:50983$2171_Y + attribute \src "libresoc.v:50991.18-50991.112" + wire $and$libresoc.v:50991$2179_Y + attribute \src "libresoc.v:50993.18-50993.112" + wire $and$libresoc.v:50993$2181_Y + attribute \src "libresoc.v:50995.18-50995.112" + wire $and$libresoc.v:50995$2183_Y + attribute \src "libresoc.v:50997.18-50997.112" + wire $and$libresoc.v:50997$2185_Y + attribute \src "libresoc.v:51000.18-51000.112" + wire $and$libresoc.v:51000$2188_Y + attribute \src "libresoc.v:51002.18-51002.112" + wire $and$libresoc.v:51002$2190_Y + attribute \src "libresoc.v:51004.18-51004.112" + wire $and$libresoc.v:51004$2192_Y + attribute \src "libresoc.v:50918.18-50918.109" + wire $eq$libresoc.v:50918$2106_Y + attribute \src "libresoc.v:50940.18-50940.109" + wire $eq$libresoc.v:50940$2128_Y + attribute \src "libresoc.v:50957.17-50957.114" + wire $eq$libresoc.v:50957$2145_Y + attribute \src "libresoc.v:50960.19-50960.110" + wire $eq$libresoc.v:50960$2148_Y + attribute \src "libresoc.v:50962.18-50962.109" + wire $eq$libresoc.v:50962$2150_Y + attribute \src "libresoc.v:50964.18-50964.109" + wire $eq$libresoc.v:50964$2152_Y + attribute \src "libresoc.v:50966.18-50966.109" + wire $eq$libresoc.v:50966$2154_Y + attribute \src "libresoc.v:50968.18-50968.109" + wire $eq$libresoc.v:50968$2156_Y + attribute \src "libresoc.v:50970.18-50970.109" + wire $eq$libresoc.v:50970$2158_Y + attribute \src "libresoc.v:50972.17-50972.114" + wire $eq$libresoc.v:50972$2160_Y + attribute \src "libresoc.v:50973.18-50973.109" + wire $eq$libresoc.v:50973$2161_Y + attribute \src "libresoc.v:50975.18-50975.109" + wire $eq$libresoc.v:50975$2163_Y + attribute \src "libresoc.v:50977.18-50977.110" + wire $eq$libresoc.v:50977$2165_Y + attribute \src "libresoc.v:50979.18-50979.110" + wire $eq$libresoc.v:50979$2167_Y + attribute \src "libresoc.v:50981.18-50981.110" + wire $eq$libresoc.v:50981$2169_Y + attribute \src "libresoc.v:50984.18-50984.110" + wire $eq$libresoc.v:50984$2172_Y + attribute \src "libresoc.v:50986.18-50986.110" + wire $eq$libresoc.v:50986$2174_Y + attribute \src "libresoc.v:50988.18-50988.110" + wire $eq$libresoc.v:50988$2176_Y + attribute \src "libresoc.v:50999.17-50999.108" + wire $eq$libresoc.v:50999$2187_Y + attribute \src "libresoc.v:50903.18-50903.111" + wire $lt$libresoc.v:50903$2091_Y + attribute \src "libresoc.v:50905.19-50905.112" + wire $lt$libresoc.v:50905$2093_Y + attribute \src "libresoc.v:50907.19-50907.112" + wire $lt$libresoc.v:50907$2095_Y + attribute \src "libresoc.v:50909.19-50909.112" + wire $lt$libresoc.v:50909$2097_Y + attribute \src "libresoc.v:50911.19-50911.112" + wire $lt$libresoc.v:50911$2099_Y + attribute \src "libresoc.v:50913.19-50913.112" + wire $lt$libresoc.v:50913$2101_Y + attribute \src "libresoc.v:50915.19-50915.112" + wire $lt$libresoc.v:50915$2103_Y + attribute \src "libresoc.v:50917.19-50917.112" + wire $lt$libresoc.v:50917$2105_Y + attribute \src "libresoc.v:50920.19-50920.112" + wire $lt$libresoc.v:50920$2108_Y + attribute \src "libresoc.v:50922.19-50922.112" + wire $lt$libresoc.v:50922$2110_Y + attribute \src "libresoc.v:50925.19-50925.112" + wire $lt$libresoc.v:50925$2113_Y + attribute \src "libresoc.v:50927.19-50927.112" + wire $lt$libresoc.v:50927$2115_Y + attribute \src "libresoc.v:50929.19-50929.112" + wire $lt$libresoc.v:50929$2117_Y + attribute \src "libresoc.v:50931.19-50931.112" + wire $lt$libresoc.v:50931$2119_Y + attribute \src "libresoc.v:50933.19-50933.113" + wire $lt$libresoc.v:50933$2121_Y + attribute \src "libresoc.v:50935.19-50935.113" + wire $lt$libresoc.v:50935$2123_Y + attribute \src "libresoc.v:50937.19-50937.114" + wire $lt$libresoc.v:50937$2125_Y + attribute \src "libresoc.v:50939.19-50939.114" + wire $lt$libresoc.v:50939$2127_Y + attribute \src "libresoc.v:50942.19-50942.114" + wire $lt$libresoc.v:50942$2130_Y + attribute \src "libresoc.v:50944.19-50944.114" + wire $lt$libresoc.v:50944$2132_Y + attribute \src "libresoc.v:50947.19-50947.114" + wire $lt$libresoc.v:50947$2135_Y + attribute \src "libresoc.v:50949.19-50949.114" + wire $lt$libresoc.v:50949$2137_Y + attribute \src "libresoc.v:50951.19-50951.114" + wire $lt$libresoc.v:50951$2139_Y + attribute \src "libresoc.v:50953.19-50953.114" + wire $lt$libresoc.v:50953$2141_Y + attribute \src "libresoc.v:50955.19-50955.114" + wire $lt$libresoc.v:50955$2143_Y + attribute \src "libresoc.v:50958.19-50958.114" + wire $lt$libresoc.v:50958$2146_Y + attribute \src "libresoc.v:50992.18-50992.110" + wire $lt$libresoc.v:50992$2180_Y + attribute \src "libresoc.v:50994.18-50994.110" + wire $lt$libresoc.v:50994$2182_Y + attribute \src "libresoc.v:50996.18-50996.111" + wire $lt$libresoc.v:50996$2184_Y + attribute \src "libresoc.v:50998.18-50998.111" + wire $lt$libresoc.v:50998$2186_Y + attribute \src "libresoc.v:51001.18-51001.111" + wire $lt$libresoc.v:51001$2189_Y + attribute \src "libresoc.v:51003.18-51003.111" + wire $lt$libresoc.v:51003$2191_Y + attribute \src "libresoc.v:50990.18-50990.40" + wire width 16 $shr$libresoc.v:50990$2178_Y + attribute \src "libresoc.v:50902.17-50902.114" + wire width 8 $ternary$libresoc.v:50902$2090_Y + attribute \src "libresoc.v:50924.18-50924.116" + wire width 8 $ternary$libresoc.v:50924$2112_Y + attribute \src "libresoc.v:50946.18-50946.116" + wire width 8 $ternary$libresoc.v:50946$2134_Y + attribute \src "libresoc.v:50961.19-50961.118" + wire width 8 $ternary$libresoc.v:50961$2149_Y + attribute \src "libresoc.v:50963.18-50963.116" + wire width 8 $ternary$libresoc.v:50963$2151_Y + attribute \src "libresoc.v:50965.18-50965.116" + wire width 8 $ternary$libresoc.v:50965$2153_Y + attribute \src "libresoc.v:50967.18-50967.116" + wire width 8 $ternary$libresoc.v:50967$2155_Y + attribute \src "libresoc.v:50969.18-50969.116" + wire width 8 $ternary$libresoc.v:50969$2157_Y + attribute \src "libresoc.v:50971.18-50971.116" + wire width 8 $ternary$libresoc.v:50971$2159_Y + attribute \src "libresoc.v:50974.18-50974.116" + wire width 8 $ternary$libresoc.v:50974$2162_Y + attribute \src "libresoc.v:50976.18-50976.116" + wire width 8 $ternary$libresoc.v:50976$2164_Y + attribute \src "libresoc.v:50978.18-50978.117" + wire width 8 $ternary$libresoc.v:50978$2166_Y + attribute \src "libresoc.v:50980.18-50980.117" + wire width 8 $ternary$libresoc.v:50980$2168_Y + attribute \src "libresoc.v:50982.18-50982.117" + wire width 8 $ternary$libresoc.v:50982$2170_Y + attribute \src "libresoc.v:50985.18-50985.117" + wire width 8 $ternary$libresoc.v:50985$2173_Y + attribute \src "libresoc.v:50987.18-50987.117" + wire width 8 $ternary$libresoc.v:50987$2175_Y + attribute \src "libresoc.v:50989.18-50989.117" + wire width 8 $ternary$libresoc.v:50989$2177_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$189 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$191 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$199 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$201 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$204 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:315" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:337" + wire width 32 \be_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" + wire width 32 \be_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:314" + wire \ibit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 output 1 \icp_o_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 \icp_o_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 output 12 \icp_o_src + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 \icp_o_src$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 \icp_r_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 \icp_r_src + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire output 9 \ics_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire \ics_wb__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 28 input 4 \ics_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 6 \ics_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 output 8 \ics_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 \ics_wb__dat_r$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 input 10 \ics_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 7 \ics_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 11 \ics_wb__we + attribute \src "libresoc.v:50503.7-50503.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" + wire width 16 input 5 \int_level_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:263" + wire width 16 \int_level_l + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:263" + wire width 16 \int_level_l$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" + wire input 2 \intclk_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:153" + wire input 3 \intclk_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:358" + wire width 4 \max_idx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:359" + wire width 8 \max_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:261" + wire width 4 \reg_idx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:287" + wire \reg_is_config + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:288" + wire \reg_is_debug + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" + wire \reg_is_xive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" + wire \wb_valid + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive0_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive0_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive10_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive10_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive11_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive11_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive12_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive12_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive13_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive13_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive14_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive14_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive15_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive15_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive1_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive1_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive2_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive2_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive3_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive3_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive4_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive4_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive5_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive5_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive6_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive6_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive7_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive7_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive8_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive8_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive9_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive9_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50904$2092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [3] + connect \B \$99 + connect \Y $and$libresoc.v:50904$2092_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50906$2094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [3] + connect \B \$103 + connect \Y $and$libresoc.v:50906$2094_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50908$2096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [4] + connect \B \$107 + connect \Y $and$libresoc.v:50908$2096_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50910$2098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [4] + connect \B \$111 + connect \Y $and$libresoc.v:50910$2098_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50912$2100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [5] + connect \B \$115 + connect \Y $and$libresoc.v:50912$2100_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50914$2102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [5] + connect \B \$119 + connect \Y $and$libresoc.v:50914$2102_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50916$2104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [6] + connect \B \$123 + connect \Y $and$libresoc.v:50916$2104_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50919$2107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [6] + connect \B \$127 + connect \Y $and$libresoc.v:50919$2107_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50921$2109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [7] + connect \B \$131 + connect \Y $and$libresoc.v:50921$2109_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50923$2111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [7] + connect \B \$135 + connect \Y $and$libresoc.v:50923$2111_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50926$2114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [8] + connect \B \$139 + connect \Y $and$libresoc.v:50926$2114_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50928$2116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [8] + connect \B \$143 + connect \Y $and$libresoc.v:50928$2116_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50930$2118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [9] + connect \B \$147 + connect \Y $and$libresoc.v:50930$2118_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50932$2120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [9] + connect \B \$151 + connect \Y $and$libresoc.v:50932$2120_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50934$2122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [10] + connect \B \$155 + connect \Y $and$libresoc.v:50934$2122_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50936$2124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [10] + connect \B \$159 + connect \Y $and$libresoc.v:50936$2124_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50938$2126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [11] + connect \B \$163 + connect \Y $and$libresoc.v:50938$2126_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50941$2129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [11] + connect \B \$167 + connect \Y $and$libresoc.v:50941$2129_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50943$2131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [12] + connect \B \$171 + connect \Y $and$libresoc.v:50943$2131_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50945$2133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [12] + connect \B \$175 + connect \Y $and$libresoc.v:50945$2133_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50948$2136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [13] + connect \B \$179 + connect \Y $and$libresoc.v:50948$2136_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50950$2138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [13] + connect \B \$183 + connect \Y $and$libresoc.v:50950$2138_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50952$2140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [14] + connect \B \$187 + connect \Y $and$libresoc.v:50952$2140_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50954$2142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [14] + connect \B \$191 + connect \Y $and$libresoc.v:50954$2142_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50956$2144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [15] + connect \B \$195 + connect \Y $and$libresoc.v:50956$2144_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50959$2147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [15] + connect \B \$199 + connect \Y $and$libresoc.v:50959$2147_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" + cell $and $and$libresoc.v:50983$2171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ics_wb__cyc + connect \B \ics_wb__stb + connect \Y $and$libresoc.v:50983$2171_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" + cell $and $and$libresoc.v:50991$2179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wb_valid + connect \B \ics_wb__we + connect \Y $and$libresoc.v:50991$2179_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50993$2181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [0] + connect \B \$75 + connect \Y $and$libresoc.v:50993$2181_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50995$2183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [0] + connect \B \$79 + connect \Y $and$libresoc.v:50995$2183_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:50997$2185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [1] + connect \B \$83 + connect \Y $and$libresoc.v:50997$2185_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:51000$2188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [1] + connect \B \$87 + connect \Y $and$libresoc.v:51000$2188_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:51002$2190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [2] + connect \B \$91 + connect \Y $and$libresoc.v:51002$2190_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:51004$2192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [2] + connect \B \$95 + connect \Y $and$libresoc.v:51004$2192_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:50918$2106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive1_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:50918$2106_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:50940$2128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive2_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:50940$2128_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" + cell $eq $eq$libresoc.v:50957$2145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ics_wb__adr [9:0] + connect \B 1'0 + connect \Y $eq$libresoc.v:50957$2145_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:50960$2148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \cur_pri15 + connect \B 8'11111111 + connect \Y $eq$libresoc.v:50960$2148_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:50962$2150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive3_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:50962$2150_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:50964$2152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive4_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:50964$2152_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:50966$2154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive5_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:50966$2154_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:50968$2156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive6_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:50968$2156_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:50970$2158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive7_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:50970$2158_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" + cell $eq $eq$libresoc.v:50972$2160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ics_wb__adr [9:0] + connect \B 3'100 + connect \Y $eq$libresoc.v:50972$2160_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:50973$2161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive8_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:50973$2161_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:50975$2163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive9_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:50975$2163_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:50977$2165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive10_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:50977$2165_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:50979$2167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive11_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:50979$2167_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:50981$2169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive12_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:50981$2169_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:50984$2172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive13_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:50984$2172_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:50986$2174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive14_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:50986$2174_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:50988$2176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive15_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:50988$2176_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:50999$2187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive0_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:50999$2187_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50903$2091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive3_pri + connect \B \cur_pri2 + connect \Y $lt$libresoc.v:50903$2091_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50905$2093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive3_pri + connect \B \cur_pri2 + connect \Y $lt$libresoc.v:50905$2093_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50907$2095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive4_pri + connect \B \cur_pri3 + connect \Y $lt$libresoc.v:50907$2095_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50909$2097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive4_pri + connect \B \cur_pri3 + connect \Y $lt$libresoc.v:50909$2097_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50911$2099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive5_pri + connect \B \cur_pri4 + connect \Y $lt$libresoc.v:50911$2099_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50913$2101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive5_pri + connect \B \cur_pri4 + connect \Y $lt$libresoc.v:50913$2101_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50915$2103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive6_pri + connect \B \cur_pri5 + connect \Y $lt$libresoc.v:50915$2103_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50917$2105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive6_pri + connect \B \cur_pri5 + connect \Y $lt$libresoc.v:50917$2105_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50920$2108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive7_pri + connect \B \cur_pri6 + connect \Y $lt$libresoc.v:50920$2108_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50922$2110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive7_pri + connect \B \cur_pri6 + connect \Y $lt$libresoc.v:50922$2110_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50925$2113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive8_pri + connect \B \cur_pri7 + connect \Y $lt$libresoc.v:50925$2113_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50927$2115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive8_pri + connect \B \cur_pri7 + connect \Y $lt$libresoc.v:50927$2115_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50929$2117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive9_pri + connect \B \cur_pri8 + connect \Y $lt$libresoc.v:50929$2117_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50931$2119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive9_pri + connect \B \cur_pri8 + connect \Y $lt$libresoc.v:50931$2119_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50933$2121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive10_pri + connect \B \cur_pri9 + connect \Y $lt$libresoc.v:50933$2121_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50935$2123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive10_pri + connect \B \cur_pri9 + connect \Y $lt$libresoc.v:50935$2123_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50937$2125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive11_pri + connect \B \cur_pri10 + connect \Y $lt$libresoc.v:50937$2125_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50939$2127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive11_pri + connect \B \cur_pri10 + connect \Y $lt$libresoc.v:50939$2127_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50942$2130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive12_pri + connect \B \cur_pri11 + connect \Y $lt$libresoc.v:50942$2130_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50944$2132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive12_pri + connect \B \cur_pri11 + connect \Y $lt$libresoc.v:50944$2132_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50947$2135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive13_pri + connect \B \cur_pri12 + connect \Y $lt$libresoc.v:50947$2135_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50949$2137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive13_pri + connect \B \cur_pri12 + connect \Y $lt$libresoc.v:50949$2137_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50951$2139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive14_pri + connect \B \cur_pri13 + connect \Y $lt$libresoc.v:50951$2139_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50953$2141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive14_pri + connect \B \cur_pri13 + connect \Y $lt$libresoc.v:50953$2141_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50955$2143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive15_pri + connect \B \cur_pri14 + connect \Y $lt$libresoc.v:50955$2143_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50958$2146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive15_pri + connect \B \cur_pri14 + connect \Y $lt$libresoc.v:50958$2146_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50992$2180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive0_pri + connect \B \max_pri + connect \Y $lt$libresoc.v:50992$2180_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50994$2182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive0_pri + connect \B \max_pri + connect \Y $lt$libresoc.v:50994$2182_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50996$2184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive1_pri + connect \B \cur_pri0 + connect \Y $lt$libresoc.v:50996$2184_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:50998$2186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive1_pri + connect \B \cur_pri0 + connect \Y $lt$libresoc.v:50998$2186_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:51001$2189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive2_pri + connect \B \cur_pri1 + connect \Y $lt$libresoc.v:51001$2189_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:51003$2191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive2_pri + connect \B \cur_pri1 + connect \Y $lt$libresoc.v:51003$2191_Y + end + attribute \src "libresoc.v:50990.18-50990.40" + cell $shr $shr$libresoc.v:50990$2178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A \int_level_l + connect \B \reg_idx + connect \Y $shr$libresoc.v:50990$2178_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:50902$2090 + parameter \WIDTH 8 + connect \A \xive0_pri + connect \B 8'11111111 + connect \S \$8 + connect \Y $ternary$libresoc.v:50902$2090_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:50924$2112 + parameter \WIDTH 8 + connect \A \xive1_pri + connect \B 8'11111111 + connect \S \$12 + connect \Y $ternary$libresoc.v:50924$2112_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:50946$2134 + parameter \WIDTH 8 + connect \A \xive2_pri + connect \B 8'11111111 + connect \S \$16 + connect \Y $ternary$libresoc.v:50946$2134_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:50961$2149 + parameter \WIDTH 8 + connect \A \cur_pri15 + connect \B 8'11111111 + connect \S \$204 + connect \Y $ternary$libresoc.v:50961$2149_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:50963$2151 + parameter \WIDTH 8 + connect \A \xive3_pri + connect \B 8'11111111 + connect \S \$20 + connect \Y $ternary$libresoc.v:50963$2151_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:50965$2153 + parameter \WIDTH 8 + connect \A \xive4_pri + connect \B 8'11111111 + connect \S \$24 + connect \Y $ternary$libresoc.v:50965$2153_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:50967$2155 + parameter \WIDTH 8 + connect \A \xive5_pri + connect \B 8'11111111 + connect \S \$28 + connect \Y $ternary$libresoc.v:50967$2155_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:50969$2157 + parameter \WIDTH 8 + connect \A \xive6_pri + connect \B 8'11111111 + connect \S \$32 + connect \Y $ternary$libresoc.v:50969$2157_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:50971$2159 + parameter \WIDTH 8 + connect \A \xive7_pri + connect \B 8'11111111 + connect \S \$36 + connect \Y $ternary$libresoc.v:50971$2159_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:50974$2162 + parameter \WIDTH 8 + connect \A \xive8_pri + connect \B 8'11111111 + connect \S \$40 + connect \Y $ternary$libresoc.v:50974$2162_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:50976$2164 + parameter \WIDTH 8 + connect \A \xive9_pri + connect \B 8'11111111 + connect \S \$44 + connect \Y $ternary$libresoc.v:50976$2164_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:50978$2166 + parameter \WIDTH 8 + connect \A \xive10_pri + connect \B 8'11111111 + connect \S \$48 + connect \Y $ternary$libresoc.v:50978$2166_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:50980$2168 + parameter \WIDTH 8 + connect \A \xive11_pri + connect \B 8'11111111 + connect \S \$52 + connect \Y $ternary$libresoc.v:50980$2168_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:50982$2170 + parameter \WIDTH 8 + connect \A \xive12_pri + connect \B 8'11111111 + connect \S \$56 + connect \Y $ternary$libresoc.v:50982$2170_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:50985$2173 + parameter \WIDTH 8 + connect \A \xive13_pri + connect \B 8'11111111 + connect \S \$60 + connect \Y $ternary$libresoc.v:50985$2173_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:50987$2175 + parameter \WIDTH 8 + connect \A \xive14_pri + connect \B 8'11111111 + connect \S \$64 + connect \Y $ternary$libresoc.v:50987$2175_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:50989$2177 + parameter \WIDTH 8 + connect \A \xive15_pri + connect \B 8'11111111 + connect \S \$68 + connect \Y $ternary$libresoc.v:50989$2177_Y + end + attribute \src "libresoc.v:50503.7-50503.20" + process $proc$libresoc.v:50503$2338 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:50782.13-50782.30" + process $proc$libresoc.v:50782$2339 + assign { } { } + assign $1\icp_o_pri[7:0] 8'00000000 + sync always + sync init + update \icp_o_pri $1\icp_o_pri[7:0] + end + attribute \src "libresoc.v:50787.13-50787.29" + process $proc$libresoc.v:50787$2340 + assign { } { } + assign $1\icp_o_src[3:0] 4'0000 + sync always + sync init + update \icp_o_src $1\icp_o_src[3:0] + end + attribute \src "libresoc.v:50796.7-50796.25" + process $proc$libresoc.v:50796$2341 + assign { } { } + assign $1\ics_wb__ack[0:0] 1'0 + sync always + sync init + update \ics_wb__ack $1\ics_wb__ack[0:0] + end + attribute \src "libresoc.v:50805.14-50805.35" + process $proc$libresoc.v:50805$2342 + assign { } { } + assign $1\ics_wb__dat_r[31:0] 0 + sync always + sync init + update \ics_wb__dat_r $1\ics_wb__dat_r[31:0] + end + attribute \src "libresoc.v:50817.14-50817.36" + process $proc$libresoc.v:50817$2343 + assign { } { } + assign $1\int_level_l[15:0] 16'0000000000000000 + sync always + sync init + update \int_level_l $1\int_level_l[15:0] + end + attribute \src "libresoc.v:50839.13-50839.30" + process $proc$libresoc.v:50839$2344 + assign { } { } + assign $1\xive0_pri[7:0] 8'11111111 + sync always + sync init + update \xive0_pri $1\xive0_pri[7:0] + end + attribute \src "libresoc.v:50843.13-50843.31" + process $proc$libresoc.v:50843$2345 + assign { } { } + assign $1\xive10_pri[7:0] 8'11111111 + sync always + sync init + update \xive10_pri $1\xive10_pri[7:0] + end + attribute \src "libresoc.v:50847.13-50847.31" + process $proc$libresoc.v:50847$2346 + assign { } { } + assign $1\xive11_pri[7:0] 8'11111111 + sync always + sync init + update \xive11_pri $1\xive11_pri[7:0] + end + attribute \src "libresoc.v:50851.13-50851.31" + process $proc$libresoc.v:50851$2347 + assign { } { } + assign $1\xive12_pri[7:0] 8'11111111 + sync always + sync init + update \xive12_pri $1\xive12_pri[7:0] + end + attribute \src "libresoc.v:50855.13-50855.31" + process $proc$libresoc.v:50855$2348 + assign { } { } + assign $1\xive13_pri[7:0] 8'11111111 + sync always + sync init + update \xive13_pri $1\xive13_pri[7:0] + end + attribute \src "libresoc.v:50859.13-50859.31" + process $proc$libresoc.v:50859$2349 + assign { } { } + assign $1\xive14_pri[7:0] 8'11111111 + sync always + sync init + update \xive14_pri $1\xive14_pri[7:0] + end + attribute \src "libresoc.v:50863.13-50863.31" + process $proc$libresoc.v:50863$2350 + assign { } { } + assign $1\xive15_pri[7:0] 8'11111111 + sync always + sync init + update \xive15_pri $1\xive15_pri[7:0] + end + attribute \src "libresoc.v:50867.13-50867.30" + process $proc$libresoc.v:50867$2351 + assign { } { } + assign $1\xive1_pri[7:0] 8'11111111 + sync always + sync init + update \xive1_pri $1\xive1_pri[7:0] + end + attribute \src "libresoc.v:50871.13-50871.30" + process $proc$libresoc.v:50871$2352 + assign { } { } + assign $1\xive2_pri[7:0] 8'11111111 + sync always + sync init + update \xive2_pri $1\xive2_pri[7:0] + end + attribute \src "libresoc.v:50875.13-50875.30" + process $proc$libresoc.v:50875$2353 + assign { } { } + assign $1\xive3_pri[7:0] 8'11111111 + sync always + sync init + update \xive3_pri $1\xive3_pri[7:0] + end + attribute \src "libresoc.v:50879.13-50879.30" + process $proc$libresoc.v:50879$2354 + assign { } { } + assign $1\xive4_pri[7:0] 8'11111111 + sync always + sync init + update \xive4_pri $1\xive4_pri[7:0] + end + attribute \src "libresoc.v:50883.13-50883.30" + process $proc$libresoc.v:50883$2355 + assign { } { } + assign $1\xive5_pri[7:0] 8'11111111 + sync always + sync init + update \xive5_pri $1\xive5_pri[7:0] + end + attribute \src "libresoc.v:50887.13-50887.30" + process $proc$libresoc.v:50887$2356 + assign { } { } + assign $1\xive6_pri[7:0] 8'11111111 + sync always + sync init + update \xive6_pri $1\xive6_pri[7:0] + end + attribute \src "libresoc.v:50891.13-50891.30" + process $proc$libresoc.v:50891$2357 + assign { } { } + assign $1\xive7_pri[7:0] 8'11111111 + sync always + sync init + update \xive7_pri $1\xive7_pri[7:0] + end + attribute \src "libresoc.v:50895.13-50895.30" + process $proc$libresoc.v:50895$2358 + assign { } { } + assign $1\xive8_pri[7:0] 8'11111111 + sync always + sync init + update \xive8_pri $1\xive8_pri[7:0] + end + attribute \src "libresoc.v:50899.13-50899.30" + process $proc$libresoc.v:50899$2359 + assign { } { } + assign $1\xive9_pri[7:0] 8'11111111 + sync always + sync init + update \xive9_pri $1\xive9_pri[7:0] + end + attribute \src "libresoc.v:51005.3-51006.37" + process $proc$libresoc.v:51005$2193 + assign { } { } + assign $0\xive14_pri[7:0] \xive14_pri$next + sync posedge \intclk_clk + update \xive14_pri $0\xive14_pri[7:0] + end + attribute \src "libresoc.v:51007.3-51008.37" + process $proc$libresoc.v:51007$2194 + assign { } { } + assign $0\xive15_pri[7:0] \xive15_pri$next + sync posedge \intclk_clk + update \xive15_pri $0\xive15_pri[7:0] + end + attribute \src "libresoc.v:51009.3-51010.39" + process $proc$libresoc.v:51009$2195 + assign { } { } + assign $0\ics_wb__ack[0:0] \ics_wb__ack$next + sync posedge \intclk_clk + update \ics_wb__ack $0\ics_wb__ack[0:0] + end + attribute \src "libresoc.v:51011.3-51012.43" + process $proc$libresoc.v:51011$2196 + assign { } { } + assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next + sync posedge \intclk_clk + update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] + end + attribute \src "libresoc.v:51013.3-51014.39" + process $proc$libresoc.v:51013$2197 + assign { } { } + assign $0\int_level_l[15:0] \int_level_l$next + sync posedge \intclk_clk + update \int_level_l $0\int_level_l[15:0] + end + attribute \src "libresoc.v:51015.3-51016.28" + process $proc$libresoc.v:51015$2198 + assign { } { } + assign $0\icp_o_src[3:0] \cur_idx15 + sync posedge \intclk_clk + update \icp_o_src $0\icp_o_src[3:0] + end + attribute \src "libresoc.v:51017.3-51018.25" + process $proc$libresoc.v:51017$2199 + assign { } { } + assign $0\icp_o_pri[7:0] \$203 + sync posedge \intclk_clk + update \icp_o_pri $0\icp_o_pri[7:0] + end + attribute \src "libresoc.v:51019.3-51020.35" + process $proc$libresoc.v:51019$2200 + assign { } { } + assign $0\xive0_pri[7:0] \xive0_pri$next + sync posedge \intclk_clk + update \xive0_pri $0\xive0_pri[7:0] + end + attribute \src "libresoc.v:51021.3-51022.35" + process $proc$libresoc.v:51021$2201 + assign { } { } + assign $0\xive1_pri[7:0] \xive1_pri$next + sync posedge \intclk_clk + update \xive1_pri $0\xive1_pri[7:0] + end + attribute \src "libresoc.v:51023.3-51024.35" + process $proc$libresoc.v:51023$2202 + assign { } { } + assign $0\xive2_pri[7:0] \xive2_pri$next + sync posedge \intclk_clk + update \xive2_pri $0\xive2_pri[7:0] + end + attribute \src "libresoc.v:51025.3-51026.35" + process $proc$libresoc.v:51025$2203 + assign { } { } + assign $0\xive3_pri[7:0] \xive3_pri$next + sync posedge \intclk_clk + update \xive3_pri $0\xive3_pri[7:0] + end + attribute \src "libresoc.v:51027.3-51028.35" + process $proc$libresoc.v:51027$2204 + assign { } { } + assign $0\xive4_pri[7:0] \xive4_pri$next + sync posedge \intclk_clk + update \xive4_pri $0\xive4_pri[7:0] + end + attribute \src "libresoc.v:51029.3-51030.35" + process $proc$libresoc.v:51029$2205 + assign { } { } + assign $0\xive5_pri[7:0] \xive5_pri$next + sync posedge \intclk_clk + update \xive5_pri $0\xive5_pri[7:0] + end + attribute \src "libresoc.v:51031.3-51032.35" + process $proc$libresoc.v:51031$2206 + assign { } { } + assign $0\xive6_pri[7:0] \xive6_pri$next + sync posedge \intclk_clk + update \xive6_pri $0\xive6_pri[7:0] + end + attribute \src "libresoc.v:51033.3-51034.35" + process $proc$libresoc.v:51033$2207 + assign { } { } + assign $0\xive7_pri[7:0] \xive7_pri$next + sync posedge \intclk_clk + update \xive7_pri $0\xive7_pri[7:0] + end + attribute \src "libresoc.v:51035.3-51036.35" + process $proc$libresoc.v:51035$2208 + assign { } { } + assign $0\xive8_pri[7:0] \xive8_pri$next + sync posedge \intclk_clk + update \xive8_pri $0\xive8_pri[7:0] + end + attribute \src "libresoc.v:51037.3-51038.35" + process $proc$libresoc.v:51037$2209 + assign { } { } + assign $0\xive9_pri[7:0] \xive9_pri$next + sync posedge \intclk_clk + update \xive9_pri $0\xive9_pri[7:0] + end + attribute \src "libresoc.v:51039.3-51040.37" + process $proc$libresoc.v:51039$2210 + assign { } { } + assign $0\xive10_pri[7:0] \xive10_pri$next + sync posedge \intclk_clk + update \xive10_pri $0\xive10_pri[7:0] + end + attribute \src "libresoc.v:51041.3-51042.37" + process $proc$libresoc.v:51041$2211 + assign { } { } + assign $0\xive11_pri[7:0] \xive11_pri$next + sync posedge \intclk_clk + update \xive11_pri $0\xive11_pri[7:0] + end + attribute \src "libresoc.v:51043.3-51044.37" + process $proc$libresoc.v:51043$2212 + assign { } { } + assign $0\xive12_pri[7:0] \xive12_pri$next + sync posedge \intclk_clk + update \xive12_pri $0\xive12_pri[7:0] + end + attribute \src "libresoc.v:51045.3-51046.37" + process $proc$libresoc.v:51045$2213 + assign { } { } + assign $0\xive13_pri[7:0] \xive13_pri$next + sync posedge \intclk_clk + update \xive13_pri $0\xive13_pri[7:0] + end + attribute \src "libresoc.v:51047.3-51132.6" + process $proc$libresoc.v:51047$2214 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xive0_pri$next[7:0]$2215 $4\xive0_pri$next[7:0]$2279 + assign $0\xive10_pri$next[7:0]$2216 $4\xive10_pri$next[7:0]$2280 + assign $0\xive11_pri$next[7:0]$2217 $4\xive11_pri$next[7:0]$2281 + assign $0\xive12_pri$next[7:0]$2218 $4\xive12_pri$next[7:0]$2282 + assign $0\xive13_pri$next[7:0]$2219 $4\xive13_pri$next[7:0]$2283 + assign $0\xive14_pri$next[7:0]$2220 $4\xive14_pri$next[7:0]$2284 + assign $0\xive15_pri$next[7:0]$2221 $4\xive15_pri$next[7:0]$2285 + assign $0\xive1_pri$next[7:0]$2222 $4\xive1_pri$next[7:0]$2286 + assign $0\xive2_pri$next[7:0]$2223 $4\xive2_pri$next[7:0]$2287 + assign $0\xive3_pri$next[7:0]$2224 $4\xive3_pri$next[7:0]$2288 + assign $0\xive4_pri$next[7:0]$2225 $4\xive4_pri$next[7:0]$2289 + assign $0\xive5_pri$next[7:0]$2226 $4\xive5_pri$next[7:0]$2290 + assign $0\xive6_pri$next[7:0]$2227 $4\xive6_pri$next[7:0]$2291 + assign $0\xive7_pri$next[7:0]$2228 $4\xive7_pri$next[7:0]$2292 + assign $0\xive8_pri$next[7:0]$2229 $4\xive8_pri$next[7:0]$2293 + assign $0\xive9_pri$next[7:0]$2230 $4\xive9_pri$next[7:0]$2294 + attribute \src "libresoc.v:51048.5-51048.29" + switch \initial + attribute \src "libresoc.v:51048.9-51048.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\xive0_pri$next[7:0]$2231 $2\xive0_pri$next[7:0]$2247 + assign $1\xive10_pri$next[7:0]$2232 $2\xive10_pri$next[7:0]$2248 + assign $1\xive11_pri$next[7:0]$2233 $2\xive11_pri$next[7:0]$2249 + assign $1\xive12_pri$next[7:0]$2234 $2\xive12_pri$next[7:0]$2250 + assign $1\xive13_pri$next[7:0]$2235 $2\xive13_pri$next[7:0]$2251 + assign $1\xive14_pri$next[7:0]$2236 $2\xive14_pri$next[7:0]$2252 + assign $1\xive15_pri$next[7:0]$2237 $2\xive15_pri$next[7:0]$2253 + assign $1\xive1_pri$next[7:0]$2238 $2\xive1_pri$next[7:0]$2254 + assign $1\xive2_pri$next[7:0]$2239 $2\xive2_pri$next[7:0]$2255 + assign $1\xive3_pri$next[7:0]$2240 $2\xive3_pri$next[7:0]$2256 + assign $1\xive4_pri$next[7:0]$2241 $2\xive4_pri$next[7:0]$2257 + assign $1\xive5_pri$next[7:0]$2242 $2\xive5_pri$next[7:0]$2258 + assign $1\xive6_pri$next[7:0]$2243 $2\xive6_pri$next[7:0]$2259 + assign $1\xive7_pri$next[7:0]$2244 $2\xive7_pri$next[7:0]$2260 + assign $1\xive8_pri$next[7:0]$2245 $2\xive8_pri$next[7:0]$2261 + assign $1\xive9_pri$next[7:0]$2246 $2\xive9_pri$next[7:0]$2262 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" + switch \reg_is_xive + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\xive0_pri$next[7:0]$2247 $3\xive0_pri$next[7:0]$2263 + assign $2\xive10_pri$next[7:0]$2248 $3\xive10_pri$next[7:0]$2264 + assign $2\xive11_pri$next[7:0]$2249 $3\xive11_pri$next[7:0]$2265 + assign $2\xive12_pri$next[7:0]$2250 $3\xive12_pri$next[7:0]$2266 + assign $2\xive13_pri$next[7:0]$2251 $3\xive13_pri$next[7:0]$2267 + assign $2\xive14_pri$next[7:0]$2252 $3\xive14_pri$next[7:0]$2268 + assign $2\xive15_pri$next[7:0]$2253 $3\xive15_pri$next[7:0]$2269 + assign $2\xive1_pri$next[7:0]$2254 $3\xive1_pri$next[7:0]$2270 + assign $2\xive2_pri$next[7:0]$2255 $3\xive2_pri$next[7:0]$2271 + assign $2\xive3_pri$next[7:0]$2256 $3\xive3_pri$next[7:0]$2272 + assign $2\xive4_pri$next[7:0]$2257 $3\xive4_pri$next[7:0]$2273 + assign $2\xive5_pri$next[7:0]$2258 $3\xive5_pri$next[7:0]$2274 + assign $2\xive6_pri$next[7:0]$2259 $3\xive6_pri$next[7:0]$2275 + assign $2\xive7_pri$next[7:0]$2260 $3\xive7_pri$next[7:0]$2276 + assign $2\xive8_pri$next[7:0]$2261 $3\xive8_pri$next[7:0]$2277 + assign $2\xive9_pri$next[7:0]$2262 $3\xive9_pri$next[7:0]$2278 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" + switch \reg_idx + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $3\xive10_pri$next[7:0]$2264 \xive10_pri + assign $3\xive11_pri$next[7:0]$2265 \xive11_pri + assign $3\xive12_pri$next[7:0]$2266 \xive12_pri + assign $3\xive13_pri$next[7:0]$2267 \xive13_pri + assign $3\xive14_pri$next[7:0]$2268 \xive14_pri + assign $3\xive15_pri$next[7:0]$2269 \xive15_pri + assign $3\xive1_pri$next[7:0]$2270 \xive1_pri + assign $3\xive2_pri$next[7:0]$2271 \xive2_pri + assign $3\xive3_pri$next[7:0]$2272 \xive3_pri + assign $3\xive4_pri$next[7:0]$2273 \xive4_pri + assign $3\xive5_pri$next[7:0]$2274 \xive5_pri + assign $3\xive6_pri$next[7:0]$2275 \xive6_pri + assign $3\xive7_pri$next[7:0]$2276 \xive7_pri + assign $3\xive8_pri$next[7:0]$2277 \xive8_pri + assign $3\xive9_pri$next[7:0]$2278 \xive9_pri + assign $3\xive0_pri$next[7:0]$2263 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign $3\xive0_pri$next[7:0]$2263 \xive0_pri + assign $3\xive10_pri$next[7:0]$2264 \xive10_pri + assign $3\xive11_pri$next[7:0]$2265 \xive11_pri + assign $3\xive12_pri$next[7:0]$2266 \xive12_pri + assign $3\xive13_pri$next[7:0]$2267 \xive13_pri + assign $3\xive14_pri$next[7:0]$2268 \xive14_pri + assign $3\xive15_pri$next[7:0]$2269 \xive15_pri + assign { } { } + assign $3\xive2_pri$next[7:0]$2271 \xive2_pri + assign $3\xive3_pri$next[7:0]$2272 \xive3_pri + assign $3\xive4_pri$next[7:0]$2273 \xive4_pri + assign $3\xive5_pri$next[7:0]$2274 \xive5_pri + assign $3\xive6_pri$next[7:0]$2275 \xive6_pri + assign $3\xive7_pri$next[7:0]$2276 \xive7_pri + assign $3\xive8_pri$next[7:0]$2277 \xive8_pri + assign $3\xive9_pri$next[7:0]$2278 \xive9_pri + assign $3\xive1_pri$next[7:0]$2270 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $3\xive0_pri$next[7:0]$2263 \xive0_pri + assign $3\xive10_pri$next[7:0]$2264 \xive10_pri + assign $3\xive11_pri$next[7:0]$2265 \xive11_pri + assign $3\xive12_pri$next[7:0]$2266 \xive12_pri + assign $3\xive13_pri$next[7:0]$2267 \xive13_pri + assign $3\xive14_pri$next[7:0]$2268 \xive14_pri + assign $3\xive15_pri$next[7:0]$2269 \xive15_pri + assign $3\xive1_pri$next[7:0]$2270 \xive1_pri + assign { } { } + assign $3\xive3_pri$next[7:0]$2272 \xive3_pri + assign $3\xive4_pri$next[7:0]$2273 \xive4_pri + assign $3\xive5_pri$next[7:0]$2274 \xive5_pri + assign $3\xive6_pri$next[7:0]$2275 \xive6_pri + assign $3\xive7_pri$next[7:0]$2276 \xive7_pri + assign $3\xive8_pri$next[7:0]$2277 \xive8_pri + assign $3\xive9_pri$next[7:0]$2278 \xive9_pri + assign $3\xive2_pri$next[7:0]$2271 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $3\xive0_pri$next[7:0]$2263 \xive0_pri + assign $3\xive10_pri$next[7:0]$2264 \xive10_pri + assign $3\xive11_pri$next[7:0]$2265 \xive11_pri + assign $3\xive12_pri$next[7:0]$2266 \xive12_pri + assign $3\xive13_pri$next[7:0]$2267 \xive13_pri + assign $3\xive14_pri$next[7:0]$2268 \xive14_pri + assign $3\xive15_pri$next[7:0]$2269 \xive15_pri + assign $3\xive1_pri$next[7:0]$2270 \xive1_pri + assign $3\xive2_pri$next[7:0]$2271 \xive2_pri + assign { } { } + assign $3\xive4_pri$next[7:0]$2273 \xive4_pri + assign $3\xive5_pri$next[7:0]$2274 \xive5_pri + assign $3\xive6_pri$next[7:0]$2275 \xive6_pri + assign $3\xive7_pri$next[7:0]$2276 \xive7_pri + assign $3\xive8_pri$next[7:0]$2277 \xive8_pri + assign $3\xive9_pri$next[7:0]$2278 \xive9_pri + assign $3\xive3_pri$next[7:0]$2272 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $3\xive0_pri$next[7:0]$2263 \xive0_pri + assign $3\xive10_pri$next[7:0]$2264 \xive10_pri + assign $3\xive11_pri$next[7:0]$2265 \xive11_pri + assign $3\xive12_pri$next[7:0]$2266 \xive12_pri + assign $3\xive13_pri$next[7:0]$2267 \xive13_pri + assign $3\xive14_pri$next[7:0]$2268 \xive14_pri + assign $3\xive15_pri$next[7:0]$2269 \xive15_pri + assign $3\xive1_pri$next[7:0]$2270 \xive1_pri + assign $3\xive2_pri$next[7:0]$2271 \xive2_pri + assign $3\xive3_pri$next[7:0]$2272 \xive3_pri + assign { } { } + assign $3\xive5_pri$next[7:0]$2274 \xive5_pri + assign $3\xive6_pri$next[7:0]$2275 \xive6_pri + assign $3\xive7_pri$next[7:0]$2276 \xive7_pri + assign $3\xive8_pri$next[7:0]$2277 \xive8_pri + assign $3\xive9_pri$next[7:0]$2278 \xive9_pri + assign $3\xive4_pri$next[7:0]$2273 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $3\xive0_pri$next[7:0]$2263 \xive0_pri + assign $3\xive10_pri$next[7:0]$2264 \xive10_pri + assign $3\xive11_pri$next[7:0]$2265 \xive11_pri + assign $3\xive12_pri$next[7:0]$2266 \xive12_pri + assign $3\xive13_pri$next[7:0]$2267 \xive13_pri + assign $3\xive14_pri$next[7:0]$2268 \xive14_pri + assign $3\xive15_pri$next[7:0]$2269 \xive15_pri + assign $3\xive1_pri$next[7:0]$2270 \xive1_pri + assign $3\xive2_pri$next[7:0]$2271 \xive2_pri + assign $3\xive3_pri$next[7:0]$2272 \xive3_pri + assign $3\xive4_pri$next[7:0]$2273 \xive4_pri + assign { } { } + assign $3\xive6_pri$next[7:0]$2275 \xive6_pri + assign $3\xive7_pri$next[7:0]$2276 \xive7_pri + assign $3\xive8_pri$next[7:0]$2277 \xive8_pri + assign $3\xive9_pri$next[7:0]$2278 \xive9_pri + assign $3\xive5_pri$next[7:0]$2274 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $3\xive0_pri$next[7:0]$2263 \xive0_pri + assign $3\xive10_pri$next[7:0]$2264 \xive10_pri + assign $3\xive11_pri$next[7:0]$2265 \xive11_pri + assign $3\xive12_pri$next[7:0]$2266 \xive12_pri + assign $3\xive13_pri$next[7:0]$2267 \xive13_pri + assign $3\xive14_pri$next[7:0]$2268 \xive14_pri + assign $3\xive15_pri$next[7:0]$2269 \xive15_pri + assign $3\xive1_pri$next[7:0]$2270 \xive1_pri + assign $3\xive2_pri$next[7:0]$2271 \xive2_pri + assign $3\xive3_pri$next[7:0]$2272 \xive3_pri + assign $3\xive4_pri$next[7:0]$2273 \xive4_pri + assign $3\xive5_pri$next[7:0]$2274 \xive5_pri + assign { } { } + assign $3\xive7_pri$next[7:0]$2276 \xive7_pri + assign $3\xive8_pri$next[7:0]$2277 \xive8_pri + assign $3\xive9_pri$next[7:0]$2278 \xive9_pri + assign $3\xive6_pri$next[7:0]$2275 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $3\xive0_pri$next[7:0]$2263 \xive0_pri + assign $3\xive10_pri$next[7:0]$2264 \xive10_pri + assign $3\xive11_pri$next[7:0]$2265 \xive11_pri + assign $3\xive12_pri$next[7:0]$2266 \xive12_pri + assign $3\xive13_pri$next[7:0]$2267 \xive13_pri + assign $3\xive14_pri$next[7:0]$2268 \xive14_pri + assign $3\xive15_pri$next[7:0]$2269 \xive15_pri + assign $3\xive1_pri$next[7:0]$2270 \xive1_pri + assign $3\xive2_pri$next[7:0]$2271 \xive2_pri + assign $3\xive3_pri$next[7:0]$2272 \xive3_pri + assign $3\xive4_pri$next[7:0]$2273 \xive4_pri + assign $3\xive5_pri$next[7:0]$2274 \xive5_pri + assign $3\xive6_pri$next[7:0]$2275 \xive6_pri + assign { } { } + assign $3\xive8_pri$next[7:0]$2277 \xive8_pri + assign $3\xive9_pri$next[7:0]$2278 \xive9_pri + assign $3\xive7_pri$next[7:0]$2276 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign $3\xive0_pri$next[7:0]$2263 \xive0_pri + assign $3\xive10_pri$next[7:0]$2264 \xive10_pri + assign $3\xive11_pri$next[7:0]$2265 \xive11_pri + assign $3\xive12_pri$next[7:0]$2266 \xive12_pri + assign $3\xive13_pri$next[7:0]$2267 \xive13_pri + assign $3\xive14_pri$next[7:0]$2268 \xive14_pri + assign $3\xive15_pri$next[7:0]$2269 \xive15_pri + assign $3\xive1_pri$next[7:0]$2270 \xive1_pri + assign $3\xive2_pri$next[7:0]$2271 \xive2_pri + assign $3\xive3_pri$next[7:0]$2272 \xive3_pri + assign $3\xive4_pri$next[7:0]$2273 \xive4_pri + assign $3\xive5_pri$next[7:0]$2274 \xive5_pri + assign $3\xive6_pri$next[7:0]$2275 \xive6_pri + assign $3\xive7_pri$next[7:0]$2276 \xive7_pri + assign { } { } + assign $3\xive9_pri$next[7:0]$2278 \xive9_pri + assign $3\xive8_pri$next[7:0]$2277 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign $3\xive0_pri$next[7:0]$2263 \xive0_pri + assign $3\xive10_pri$next[7:0]$2264 \xive10_pri + assign $3\xive11_pri$next[7:0]$2265 \xive11_pri + assign $3\xive12_pri$next[7:0]$2266 \xive12_pri + assign $3\xive13_pri$next[7:0]$2267 \xive13_pri + assign $3\xive14_pri$next[7:0]$2268 \xive14_pri + assign $3\xive15_pri$next[7:0]$2269 \xive15_pri + assign $3\xive1_pri$next[7:0]$2270 \xive1_pri + assign $3\xive2_pri$next[7:0]$2271 \xive2_pri + assign $3\xive3_pri$next[7:0]$2272 \xive3_pri + assign $3\xive4_pri$next[7:0]$2273 \xive4_pri + assign $3\xive5_pri$next[7:0]$2274 \xive5_pri + assign $3\xive6_pri$next[7:0]$2275 \xive6_pri + assign $3\xive7_pri$next[7:0]$2276 \xive7_pri + assign $3\xive8_pri$next[7:0]$2277 \xive8_pri + assign { } { } + assign $3\xive9_pri$next[7:0]$2278 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign $3\xive0_pri$next[7:0]$2263 \xive0_pri + assign { } { } + assign $3\xive11_pri$next[7:0]$2265 \xive11_pri + assign $3\xive12_pri$next[7:0]$2266 \xive12_pri + assign $3\xive13_pri$next[7:0]$2267 \xive13_pri + assign $3\xive14_pri$next[7:0]$2268 \xive14_pri + assign $3\xive15_pri$next[7:0]$2269 \xive15_pri + assign $3\xive1_pri$next[7:0]$2270 \xive1_pri + assign $3\xive2_pri$next[7:0]$2271 \xive2_pri + assign $3\xive3_pri$next[7:0]$2272 \xive3_pri + assign $3\xive4_pri$next[7:0]$2273 \xive4_pri + assign $3\xive5_pri$next[7:0]$2274 \xive5_pri + assign $3\xive6_pri$next[7:0]$2275 \xive6_pri + assign $3\xive7_pri$next[7:0]$2276 \xive7_pri + assign $3\xive8_pri$next[7:0]$2277 \xive8_pri + assign $3\xive9_pri$next[7:0]$2278 \xive9_pri + assign $3\xive10_pri$next[7:0]$2264 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign $3\xive0_pri$next[7:0]$2263 \xive0_pri + assign $3\xive10_pri$next[7:0]$2264 \xive10_pri + assign { } { } + assign $3\xive12_pri$next[7:0]$2266 \xive12_pri + assign $3\xive13_pri$next[7:0]$2267 \xive13_pri + assign $3\xive14_pri$next[7:0]$2268 \xive14_pri + assign $3\xive15_pri$next[7:0]$2269 \xive15_pri + assign $3\xive1_pri$next[7:0]$2270 \xive1_pri + assign $3\xive2_pri$next[7:0]$2271 \xive2_pri + assign $3\xive3_pri$next[7:0]$2272 \xive3_pri + assign $3\xive4_pri$next[7:0]$2273 \xive4_pri + assign $3\xive5_pri$next[7:0]$2274 \xive5_pri + assign $3\xive6_pri$next[7:0]$2275 \xive6_pri + assign $3\xive7_pri$next[7:0]$2276 \xive7_pri + assign $3\xive8_pri$next[7:0]$2277 \xive8_pri + assign $3\xive9_pri$next[7:0]$2278 \xive9_pri + assign $3\xive11_pri$next[7:0]$2265 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1100 + assign $3\xive0_pri$next[7:0]$2263 \xive0_pri + assign $3\xive10_pri$next[7:0]$2264 \xive10_pri + assign $3\xive11_pri$next[7:0]$2265 \xive11_pri + assign { } { } + assign $3\xive13_pri$next[7:0]$2267 \xive13_pri + assign $3\xive14_pri$next[7:0]$2268 \xive14_pri + assign $3\xive15_pri$next[7:0]$2269 \xive15_pri + assign $3\xive1_pri$next[7:0]$2270 \xive1_pri + assign $3\xive2_pri$next[7:0]$2271 \xive2_pri + assign $3\xive3_pri$next[7:0]$2272 \xive3_pri + assign $3\xive4_pri$next[7:0]$2273 \xive4_pri + assign $3\xive5_pri$next[7:0]$2274 \xive5_pri + assign $3\xive6_pri$next[7:0]$2275 \xive6_pri + assign $3\xive7_pri$next[7:0]$2276 \xive7_pri + assign $3\xive8_pri$next[7:0]$2277 \xive8_pri + assign $3\xive9_pri$next[7:0]$2278 \xive9_pri + assign $3\xive12_pri$next[7:0]$2266 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1101 + assign $3\xive0_pri$next[7:0]$2263 \xive0_pri + assign $3\xive10_pri$next[7:0]$2264 \xive10_pri + assign $3\xive11_pri$next[7:0]$2265 \xive11_pri + assign $3\xive12_pri$next[7:0]$2266 \xive12_pri + assign { } { } + assign $3\xive14_pri$next[7:0]$2268 \xive14_pri + assign $3\xive15_pri$next[7:0]$2269 \xive15_pri + assign $3\xive1_pri$next[7:0]$2270 \xive1_pri + assign $3\xive2_pri$next[7:0]$2271 \xive2_pri + assign $3\xive3_pri$next[7:0]$2272 \xive3_pri + assign $3\xive4_pri$next[7:0]$2273 \xive4_pri + assign $3\xive5_pri$next[7:0]$2274 \xive5_pri + assign $3\xive6_pri$next[7:0]$2275 \xive6_pri + assign $3\xive7_pri$next[7:0]$2276 \xive7_pri + assign $3\xive8_pri$next[7:0]$2277 \xive8_pri + assign $3\xive9_pri$next[7:0]$2278 \xive9_pri + assign $3\xive13_pri$next[7:0]$2267 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1110 + assign $3\xive0_pri$next[7:0]$2263 \xive0_pri + assign $3\xive10_pri$next[7:0]$2264 \xive10_pri + assign $3\xive11_pri$next[7:0]$2265 \xive11_pri + assign $3\xive12_pri$next[7:0]$2266 \xive12_pri + assign $3\xive13_pri$next[7:0]$2267 \xive13_pri + assign { } { } + assign $3\xive15_pri$next[7:0]$2269 \xive15_pri + assign $3\xive1_pri$next[7:0]$2270 \xive1_pri + assign $3\xive2_pri$next[7:0]$2271 \xive2_pri + assign $3\xive3_pri$next[7:0]$2272 \xive3_pri + assign $3\xive4_pri$next[7:0]$2273 \xive4_pri + assign $3\xive5_pri$next[7:0]$2274 \xive5_pri + assign $3\xive6_pri$next[7:0]$2275 \xive6_pri + assign $3\xive7_pri$next[7:0]$2276 \xive7_pri + assign $3\xive8_pri$next[7:0]$2277 \xive8_pri + assign $3\xive9_pri$next[7:0]$2278 \xive9_pri + assign $3\xive14_pri$next[7:0]$2268 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'---- + assign $3\xive0_pri$next[7:0]$2263 \xive0_pri + assign $3\xive10_pri$next[7:0]$2264 \xive10_pri + assign $3\xive11_pri$next[7:0]$2265 \xive11_pri + assign $3\xive12_pri$next[7:0]$2266 \xive12_pri + assign $3\xive13_pri$next[7:0]$2267 \xive13_pri + assign $3\xive14_pri$next[7:0]$2268 \xive14_pri + assign { } { } + assign $3\xive1_pri$next[7:0]$2270 \xive1_pri + assign $3\xive2_pri$next[7:0]$2271 \xive2_pri + assign $3\xive3_pri$next[7:0]$2272 \xive3_pri + assign $3\xive4_pri$next[7:0]$2273 \xive4_pri + assign $3\xive5_pri$next[7:0]$2274 \xive5_pri + assign $3\xive6_pri$next[7:0]$2275 \xive6_pri + assign $3\xive7_pri$next[7:0]$2276 \xive7_pri + assign $3\xive8_pri$next[7:0]$2277 \xive8_pri + assign $3\xive9_pri$next[7:0]$2278 \xive9_pri + assign $3\xive15_pri$next[7:0]$2269 \be_in [7:0] + case + assign $3\xive0_pri$next[7:0]$2263 \xive0_pri + assign $3\xive10_pri$next[7:0]$2264 \xive10_pri + assign $3\xive11_pri$next[7:0]$2265 \xive11_pri + assign $3\xive12_pri$next[7:0]$2266 \xive12_pri + assign $3\xive13_pri$next[7:0]$2267 \xive13_pri + assign $3\xive14_pri$next[7:0]$2268 \xive14_pri + assign $3\xive15_pri$next[7:0]$2269 \xive15_pri + assign $3\xive1_pri$next[7:0]$2270 \xive1_pri + assign $3\xive2_pri$next[7:0]$2271 \xive2_pri + assign $3\xive3_pri$next[7:0]$2272 \xive3_pri + assign $3\xive4_pri$next[7:0]$2273 \xive4_pri + assign $3\xive5_pri$next[7:0]$2274 \xive5_pri + assign $3\xive6_pri$next[7:0]$2275 \xive6_pri + assign $3\xive7_pri$next[7:0]$2276 \xive7_pri + assign $3\xive8_pri$next[7:0]$2277 \xive8_pri + assign $3\xive9_pri$next[7:0]$2278 \xive9_pri + end + case + assign $2\xive0_pri$next[7:0]$2247 \xive0_pri + assign $2\xive10_pri$next[7:0]$2248 \xive10_pri + assign $2\xive11_pri$next[7:0]$2249 \xive11_pri + assign $2\xive12_pri$next[7:0]$2250 \xive12_pri + assign $2\xive13_pri$next[7:0]$2251 \xive13_pri + assign $2\xive14_pri$next[7:0]$2252 \xive14_pri + assign $2\xive15_pri$next[7:0]$2253 \xive15_pri + assign $2\xive1_pri$next[7:0]$2254 \xive1_pri + assign $2\xive2_pri$next[7:0]$2255 \xive2_pri + assign $2\xive3_pri$next[7:0]$2256 \xive3_pri + assign $2\xive4_pri$next[7:0]$2257 \xive4_pri + assign $2\xive5_pri$next[7:0]$2258 \xive5_pri + assign $2\xive6_pri$next[7:0]$2259 \xive6_pri + assign $2\xive7_pri$next[7:0]$2260 \xive7_pri + assign $2\xive8_pri$next[7:0]$2261 \xive8_pri + assign $2\xive9_pri$next[7:0]$2262 \xive9_pri + end + case + assign $1\xive0_pri$next[7:0]$2231 \xive0_pri + assign $1\xive10_pri$next[7:0]$2232 \xive10_pri + assign $1\xive11_pri$next[7:0]$2233 \xive11_pri + assign $1\xive12_pri$next[7:0]$2234 \xive12_pri + assign $1\xive13_pri$next[7:0]$2235 \xive13_pri + assign $1\xive14_pri$next[7:0]$2236 \xive14_pri + assign $1\xive15_pri$next[7:0]$2237 \xive15_pri + assign $1\xive1_pri$next[7:0]$2238 \xive1_pri + assign $1\xive2_pri$next[7:0]$2239 \xive2_pri + assign $1\xive3_pri$next[7:0]$2240 \xive3_pri + assign $1\xive4_pri$next[7:0]$2241 \xive4_pri + assign $1\xive5_pri$next[7:0]$2242 \xive5_pri + assign $1\xive6_pri$next[7:0]$2243 \xive6_pri + assign $1\xive7_pri$next[7:0]$2244 \xive7_pri + assign $1\xive8_pri$next[7:0]$2245 \xive8_pri + assign $1\xive9_pri$next[7:0]$2246 \xive9_pri + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $4\xive0_pri$next[7:0]$2279 8'11111111 + assign $4\xive1_pri$next[7:0]$2286 8'11111111 + assign $4\xive2_pri$next[7:0]$2287 8'11111111 + assign $4\xive3_pri$next[7:0]$2288 8'11111111 + assign $4\xive4_pri$next[7:0]$2289 8'11111111 + assign $4\xive5_pri$next[7:0]$2290 8'11111111 + assign $4\xive6_pri$next[7:0]$2291 8'11111111 + assign $4\xive7_pri$next[7:0]$2292 8'11111111 + assign $4\xive8_pri$next[7:0]$2293 8'11111111 + assign $4\xive9_pri$next[7:0]$2294 8'11111111 + assign $4\xive10_pri$next[7:0]$2280 8'11111111 + assign $4\xive11_pri$next[7:0]$2281 8'11111111 + assign $4\xive12_pri$next[7:0]$2282 8'11111111 + assign $4\xive13_pri$next[7:0]$2283 8'11111111 + assign $4\xive14_pri$next[7:0]$2284 8'11111111 + assign $4\xive15_pri$next[7:0]$2285 8'11111111 + case + assign $4\xive0_pri$next[7:0]$2279 $1\xive0_pri$next[7:0]$2231 + assign $4\xive10_pri$next[7:0]$2280 $1\xive10_pri$next[7:0]$2232 + assign $4\xive11_pri$next[7:0]$2281 $1\xive11_pri$next[7:0]$2233 + assign $4\xive12_pri$next[7:0]$2282 $1\xive12_pri$next[7:0]$2234 + assign $4\xive13_pri$next[7:0]$2283 $1\xive13_pri$next[7:0]$2235 + assign $4\xive14_pri$next[7:0]$2284 $1\xive14_pri$next[7:0]$2236 + assign $4\xive15_pri$next[7:0]$2285 $1\xive15_pri$next[7:0]$2237 + assign $4\xive1_pri$next[7:0]$2286 $1\xive1_pri$next[7:0]$2238 + assign $4\xive2_pri$next[7:0]$2287 $1\xive2_pri$next[7:0]$2239 + assign $4\xive3_pri$next[7:0]$2288 $1\xive3_pri$next[7:0]$2240 + assign $4\xive4_pri$next[7:0]$2289 $1\xive4_pri$next[7:0]$2241 + assign $4\xive5_pri$next[7:0]$2290 $1\xive5_pri$next[7:0]$2242 + assign $4\xive6_pri$next[7:0]$2291 $1\xive6_pri$next[7:0]$2243 + assign $4\xive7_pri$next[7:0]$2292 $1\xive7_pri$next[7:0]$2244 + assign $4\xive8_pri$next[7:0]$2293 $1\xive8_pri$next[7:0]$2245 + assign $4\xive9_pri$next[7:0]$2294 $1\xive9_pri$next[7:0]$2246 + end + sync always + update \xive0_pri$next $0\xive0_pri$next[7:0]$2215 + update \xive10_pri$next $0\xive10_pri$next[7:0]$2216 + update \xive11_pri$next $0\xive11_pri$next[7:0]$2217 + update \xive12_pri$next $0\xive12_pri$next[7:0]$2218 + update \xive13_pri$next $0\xive13_pri$next[7:0]$2219 + update \xive14_pri$next $0\xive14_pri$next[7:0]$2220 + update \xive15_pri$next $0\xive15_pri$next[7:0]$2221 + update \xive1_pri$next $0\xive1_pri$next[7:0]$2222 + update \xive2_pri$next $0\xive2_pri$next[7:0]$2223 + update \xive3_pri$next $0\xive3_pri$next[7:0]$2224 + update \xive4_pri$next $0\xive4_pri$next[7:0]$2225 + update \xive5_pri$next $0\xive5_pri$next[7:0]$2226 + update \xive6_pri$next $0\xive6_pri$next[7:0]$2227 + update \xive7_pri$next $0\xive7_pri$next[7:0]$2228 + update \xive8_pri$next $0\xive8_pri$next[7:0]$2229 + update \xive9_pri$next $0\xive9_pri$next[7:0]$2230 + end + attribute \src "libresoc.v:51133.3-51142.6" + process $proc$libresoc.v:51133$2295 + assign { } { } + assign { } { } + assign $0\cur_pri0[7:0] $1\cur_pri0[7:0] + attribute \src "libresoc.v:51134.5-51134.29" + switch \initial + attribute \src "libresoc.v:51134.9-51134.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri0[7:0] \xive0_pri + case + assign $1\cur_pri0[7:0] \max_pri + end + sync always + update \cur_pri0 $0\cur_pri0[7:0] + end + attribute \src "libresoc.v:51143.3-51152.6" + process $proc$libresoc.v:51143$2296 + assign { } { } + assign { } { } + assign $0\cur_idx0[3:0] $1\cur_idx0[3:0] + attribute \src "libresoc.v:51144.5-51144.29" + switch \initial + attribute \src "libresoc.v:51144.9-51144.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx0[3:0] 4'0000 + case + assign $1\cur_idx0[3:0] \max_idx + end + sync always + update \cur_idx0 $0\cur_idx0[3:0] + end + attribute \src "libresoc.v:51153.3-51162.6" + process $proc$libresoc.v:51153$2297 + assign { } { } + assign { } { } + assign $0\cur_pri1[7:0] $1\cur_pri1[7:0] + attribute \src "libresoc.v:51154.5-51154.29" + switch \initial + attribute \src "libresoc.v:51154.9-51154.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri1[7:0] \xive1_pri + case + assign $1\cur_pri1[7:0] \cur_pri0 + end + sync always + update \cur_pri1 $0\cur_pri1[7:0] + end + attribute \src "libresoc.v:51163.3-51172.6" + process $proc$libresoc.v:51163$2298 + assign { } { } + assign { } { } + assign $0\cur_idx1[3:0] $1\cur_idx1[3:0] + attribute \src "libresoc.v:51164.5-51164.29" + switch \initial + attribute \src "libresoc.v:51164.9-51164.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$89 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx1[3:0] 4'0001 + case + assign $1\cur_idx1[3:0] \cur_idx0 + end + sync always + update \cur_idx1 $0\cur_idx1[3:0] + end + attribute \src "libresoc.v:51173.3-51182.6" + process $proc$libresoc.v:51173$2299 + assign { } { } + assign { } { } + assign $0\cur_pri2[7:0] $1\cur_pri2[7:0] + attribute \src "libresoc.v:51174.5-51174.29" + switch \initial + attribute \src "libresoc.v:51174.9-51174.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri2[7:0] \xive2_pri + case + assign $1\cur_pri2[7:0] \cur_pri1 + end + sync always + update \cur_pri2 $0\cur_pri2[7:0] + end + attribute \src "libresoc.v:51183.3-51192.6" + process $proc$libresoc.v:51183$2300 + assign { } { } + assign { } { } + assign $0\cur_idx2[3:0] $1\cur_idx2[3:0] + attribute \src "libresoc.v:51184.5-51184.29" + switch \initial + attribute \src "libresoc.v:51184.9-51184.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$97 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx2[3:0] 4'0010 + case + assign $1\cur_idx2[3:0] \cur_idx1 + end + sync always + update \cur_idx2 $0\cur_idx2[3:0] + end + attribute \src "libresoc.v:51193.3-51202.6" + process $proc$libresoc.v:51193$2301 + assign { } { } + assign { } { } + assign $0\cur_pri3[7:0] $1\cur_pri3[7:0] + attribute \src "libresoc.v:51194.5-51194.29" + switch \initial + attribute \src "libresoc.v:51194.9-51194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri3[7:0] \xive3_pri + case + assign $1\cur_pri3[7:0] \cur_pri2 + end + sync always + update \cur_pri3 $0\cur_pri3[7:0] + end + attribute \src "libresoc.v:51203.3-51212.6" + process $proc$libresoc.v:51203$2302 + assign { } { } + assign { } { } + assign $0\cur_idx3[3:0] $1\cur_idx3[3:0] + attribute \src "libresoc.v:51204.5-51204.29" + switch \initial + attribute \src "libresoc.v:51204.9-51204.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx3[3:0] 4'0011 + case + assign $1\cur_idx3[3:0] \cur_idx2 + end + sync always + update \cur_idx3 $0\cur_idx3[3:0] + end + attribute \src "libresoc.v:51213.3-51222.6" + process $proc$libresoc.v:51213$2303 + assign { } { } + assign { } { } + assign $0\cur_pri4[7:0] $1\cur_pri4[7:0] + attribute \src "libresoc.v:51214.5-51214.29" + switch \initial + attribute \src "libresoc.v:51214.9-51214.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$109 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri4[7:0] \xive4_pri + case + assign $1\cur_pri4[7:0] \cur_pri3 + end + sync always + update \cur_pri4 $0\cur_pri4[7:0] + end + attribute \src "libresoc.v:51223.3-51231.6" + process $proc$libresoc.v:51223$2304 + assign { } { } + assign { } { } + assign $0\int_level_l$next[15:0]$2305 $1\int_level_l$next[15:0]$2306 + attribute \src "libresoc.v:51224.5-51224.29" + switch \initial + attribute \src "libresoc.v:51224.9-51224.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\int_level_l$next[15:0]$2306 16'0000000000000000 + case + assign $1\int_level_l$next[15:0]$2306 \int_level_i + end + sync always + update \int_level_l$next $0\int_level_l$next[15:0]$2305 + end + attribute \src "libresoc.v:51232.3-51241.6" + process $proc$libresoc.v:51232$2307 + assign { } { } + assign { } { } + assign $0\cur_idx4[3:0] $1\cur_idx4[3:0] + attribute \src "libresoc.v:51233.5-51233.29" + switch \initial + attribute \src "libresoc.v:51233.9-51233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx4[3:0] 4'0100 + case + assign $1\cur_idx4[3:0] \cur_idx3 + end + sync always + update \cur_idx4 $0\cur_idx4[3:0] + end + attribute \src "libresoc.v:51242.3-51251.6" + process $proc$libresoc.v:51242$2308 + assign { } { } + assign { } { } + assign $0\cur_pri5[7:0] $1\cur_pri5[7:0] + attribute \src "libresoc.v:51243.5-51243.29" + switch \initial + attribute \src "libresoc.v:51243.9-51243.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri5[7:0] \xive5_pri + case + assign $1\cur_pri5[7:0] \cur_pri4 + end + sync always + update \cur_pri5 $0\cur_pri5[7:0] + end + attribute \src "libresoc.v:51252.3-51261.6" + process $proc$libresoc.v:51252$2309 + assign { } { } + assign { } { } + assign $0\cur_idx5[3:0] $1\cur_idx5[3:0] + attribute \src "libresoc.v:51253.5-51253.29" + switch \initial + attribute \src "libresoc.v:51253.9-51253.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx5[3:0] 4'0101 + case + assign $1\cur_idx5[3:0] \cur_idx4 + end + sync always + update \cur_idx5 $0\cur_idx5[3:0] + end + attribute \src "libresoc.v:51262.3-51271.6" + process $proc$libresoc.v:51262$2310 + assign { } { } + assign { } { } + assign $0\cur_pri6[7:0] $1\cur_pri6[7:0] + attribute \src "libresoc.v:51263.5-51263.29" + switch \initial + attribute \src "libresoc.v:51263.9-51263.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$125 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri6[7:0] \xive6_pri + case + assign $1\cur_pri6[7:0] \cur_pri5 + end + sync always + update \cur_pri6 $0\cur_pri6[7:0] + end + attribute \src "libresoc.v:51272.3-51281.6" + process $proc$libresoc.v:51272$2311 + assign { } { } + assign { } { } + assign $0\cur_idx6[3:0] $1\cur_idx6[3:0] + attribute \src "libresoc.v:51273.5-51273.29" + switch \initial + attribute \src "libresoc.v:51273.9-51273.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$129 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx6[3:0] 4'0110 + case + assign $1\cur_idx6[3:0] \cur_idx5 + end + sync always + update \cur_idx6 $0\cur_idx6[3:0] + end + attribute \src "libresoc.v:51282.3-51291.6" + process $proc$libresoc.v:51282$2312 + assign { } { } + assign { } { } + assign $0\cur_pri7[7:0] $1\cur_pri7[7:0] + attribute \src "libresoc.v:51283.5-51283.29" + switch \initial + attribute \src "libresoc.v:51283.9-51283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$133 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri7[7:0] \xive7_pri + case + assign $1\cur_pri7[7:0] \cur_pri6 + end + sync always + update \cur_pri7 $0\cur_pri7[7:0] + end + attribute \src "libresoc.v:51292.3-51301.6" + process $proc$libresoc.v:51292$2313 + assign { } { } + assign { } { } + assign $0\cur_idx7[3:0] $1\cur_idx7[3:0] + attribute \src "libresoc.v:51293.5-51293.29" + switch \initial + attribute \src "libresoc.v:51293.9-51293.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$137 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx7[3:0] 4'0111 + case + assign $1\cur_idx7[3:0] \cur_idx6 + end + sync always + update \cur_idx7 $0\cur_idx7[3:0] + end + attribute \src "libresoc.v:51302.3-51311.6" + process $proc$libresoc.v:51302$2314 + assign { } { } + assign { } { } + assign $0\cur_pri8[7:0] $1\cur_pri8[7:0] + attribute \src "libresoc.v:51303.5-51303.29" + switch \initial + attribute \src "libresoc.v:51303.9-51303.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$141 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri8[7:0] \xive8_pri + case + assign $1\cur_pri8[7:0] \cur_pri7 + end + sync always + update \cur_pri8 $0\cur_pri8[7:0] + end + attribute \src "libresoc.v:51312.3-51321.6" + process $proc$libresoc.v:51312$2315 + assign { } { } + assign { } { } + assign $0\cur_idx8[3:0] $1\cur_idx8[3:0] + attribute \src "libresoc.v:51313.5-51313.29" + switch \initial + attribute \src "libresoc.v:51313.9-51313.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$145 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx8[3:0] 4'1000 + case + assign $1\cur_idx8[3:0] \cur_idx7 + end + sync always + update \cur_idx8 $0\cur_idx8[3:0] + end + attribute \src "libresoc.v:51322.3-51331.6" + process $proc$libresoc.v:51322$2316 + assign { } { } + assign { } { } + assign $0\cur_pri9[7:0] $1\cur_pri9[7:0] + attribute \src "libresoc.v:51323.5-51323.29" + switch \initial + attribute \src "libresoc.v:51323.9-51323.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$149 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri9[7:0] \xive9_pri + case + assign $1\cur_pri9[7:0] \cur_pri8 + end + sync always + update \cur_pri9 $0\cur_pri9[7:0] + end + attribute \src "libresoc.v:51332.3-51341.6" + process $proc$libresoc.v:51332$2317 + assign { } { } + assign { } { } + assign $0\cur_idx9[3:0] $1\cur_idx9[3:0] + attribute \src "libresoc.v:51333.5-51333.29" + switch \initial + attribute \src "libresoc.v:51333.9-51333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$153 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx9[3:0] 4'1001 + case + assign $1\cur_idx9[3:0] \cur_idx8 + end + sync always + update \cur_idx9 $0\cur_idx9[3:0] + end + attribute \src "libresoc.v:51342.3-51351.6" + process $proc$libresoc.v:51342$2318 + assign { } { } + assign { } { } + assign $0\cur_pri10[7:0] $1\cur_pri10[7:0] + attribute \src "libresoc.v:51343.5-51343.29" + switch \initial + attribute \src "libresoc.v:51343.9-51343.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$157 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri10[7:0] \xive10_pri + case + assign $1\cur_pri10[7:0] \cur_pri9 + end + sync always + update \cur_pri10 $0\cur_pri10[7:0] + end + attribute \src "libresoc.v:51352.3-51361.6" + process $proc$libresoc.v:51352$2319 + assign { } { } + assign { } { } + assign $0\cur_idx10[3:0] $1\cur_idx10[3:0] + attribute \src "libresoc.v:51353.5-51353.29" + switch \initial + attribute \src "libresoc.v:51353.9-51353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$161 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx10[3:0] 4'1010 + case + assign $1\cur_idx10[3:0] \cur_idx9 + end + sync always + update \cur_idx10 $0\cur_idx10[3:0] + end + attribute \src "libresoc.v:51362.3-51371.6" + process $proc$libresoc.v:51362$2320 + assign { } { } + assign { } { } + assign $0\cur_pri11[7:0] $1\cur_pri11[7:0] + attribute \src "libresoc.v:51363.5-51363.29" + switch \initial + attribute \src "libresoc.v:51363.9-51363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$165 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri11[7:0] \xive11_pri + case + assign $1\cur_pri11[7:0] \cur_pri10 + end + sync always + update \cur_pri11 $0\cur_pri11[7:0] + end + attribute \src "libresoc.v:51372.3-51381.6" + process $proc$libresoc.v:51372$2321 + assign { } { } + assign { } { } + assign $0\cur_idx11[3:0] $1\cur_idx11[3:0] + attribute \src "libresoc.v:51373.5-51373.29" + switch \initial + attribute \src "libresoc.v:51373.9-51373.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$169 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx11[3:0] 4'1011 + case + assign $1\cur_idx11[3:0] \cur_idx10 + end + sync always + update \cur_idx11 $0\cur_idx11[3:0] + end + attribute \src "libresoc.v:51382.3-51391.6" + process $proc$libresoc.v:51382$2322 + assign { } { } + assign { } { } + assign $0\cur_pri12[7:0] $1\cur_pri12[7:0] + attribute \src "libresoc.v:51383.5-51383.29" + switch \initial + attribute \src "libresoc.v:51383.9-51383.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$173 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri12[7:0] \xive12_pri + case + assign $1\cur_pri12[7:0] \cur_pri11 + end + sync always + update \cur_pri12 $0\cur_pri12[7:0] + end + attribute \src "libresoc.v:51392.3-51401.6" + process $proc$libresoc.v:51392$2323 + assign { } { } + assign { } { } + assign $0\cur_idx12[3:0] $1\cur_idx12[3:0] + attribute \src "libresoc.v:51393.5-51393.29" + switch \initial + attribute \src "libresoc.v:51393.9-51393.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$177 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx12[3:0] 4'1100 + case + assign $1\cur_idx12[3:0] \cur_idx11 + end + sync always + update \cur_idx12 $0\cur_idx12[3:0] + end + attribute \src "libresoc.v:51402.3-51411.6" + process $proc$libresoc.v:51402$2324 + assign { } { } + assign { } { } + assign $0\cur_pri13[7:0] $1\cur_pri13[7:0] + attribute \src "libresoc.v:51403.5-51403.29" + switch \initial + attribute \src "libresoc.v:51403.9-51403.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$181 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri13[7:0] \xive13_pri + case + assign $1\cur_pri13[7:0] \cur_pri12 + end + sync always + update \cur_pri13 $0\cur_pri13[7:0] + end + attribute \src "libresoc.v:51412.3-51421.6" + process $proc$libresoc.v:51412$2325 + assign { } { } + assign { } { } + assign $0\cur_idx13[3:0] $1\cur_idx13[3:0] + attribute \src "libresoc.v:51413.5-51413.29" + switch \initial + attribute \src "libresoc.v:51413.9-51413.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$185 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx13[3:0] 4'1101 + case + assign $1\cur_idx13[3:0] \cur_idx12 + end + sync always + update \cur_idx13 $0\cur_idx13[3:0] + end + attribute \src "libresoc.v:51422.3-51431.6" + process $proc$libresoc.v:51422$2326 + assign { } { } + assign { } { } + assign $0\cur_pri14[7:0] $1\cur_pri14[7:0] + attribute \src "libresoc.v:51423.5-51423.29" + switch \initial + attribute \src "libresoc.v:51423.9-51423.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$189 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri14[7:0] \xive14_pri + case + assign $1\cur_pri14[7:0] \cur_pri13 + end + sync always + update \cur_pri14 $0\cur_pri14[7:0] + end + attribute \src "libresoc.v:51432.3-51481.6" + process $proc$libresoc.v:51432$2327 + assign { } { } + assign { } { } + assign $0\be_out[31:0] $1\be_out[31:0] + attribute \src "libresoc.v:51433.5-51433.29" + switch \initial + attribute \src "libresoc.v:51433.9-51433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" + switch { \reg_is_debug \reg_is_config \reg_is_xive } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\be_out[31:0] $2\be_out[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + switch \reg_idx + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$7 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$11 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$15 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$19 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$23 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$27 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$31 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$35 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$39 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$43 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$47 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$51 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1100 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$55 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1101 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$59 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1110 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$63 } + attribute \src "libresoc.v:0.0-0.0" + case 4'---- + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$67 } + case + assign $2\be_out[31:0] 0 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\be_out[31:0] 134217744 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\be_out[31:0] { \icp_r_src 20'00000000000000000000 \icp_r_pri } + case + assign $1\be_out[31:0] 0 + end + sync always + update \be_out $0\be_out[31:0] + end + attribute \src "libresoc.v:51482.3-51491.6" + process $proc$libresoc.v:51482$2328 + assign { } { } + assign { } { } + assign $0\cur_idx14[3:0] $1\cur_idx14[3:0] + attribute \src "libresoc.v:51483.5-51483.29" + switch \initial + attribute \src "libresoc.v:51483.9-51483.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$193 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx14[3:0] 4'1110 + case + assign $1\cur_idx14[3:0] \cur_idx13 + end + sync always + update \cur_idx14 $0\cur_idx14[3:0] + end + attribute \src "libresoc.v:51492.3-51501.6" + process $proc$libresoc.v:51492$2329 + assign { } { } + assign { } { } + assign $0\cur_pri15[7:0] $1\cur_pri15[7:0] + attribute \src "libresoc.v:51493.5-51493.29" + switch \initial + attribute \src "libresoc.v:51493.9-51493.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$197 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri15[7:0] \xive15_pri + case + assign $1\cur_pri15[7:0] \cur_pri14 + end + sync always + update \cur_pri15 $0\cur_pri15[7:0] + end + attribute \src "libresoc.v:51502.3-51511.6" + process $proc$libresoc.v:51502$2330 + assign { } { } + assign { } { } + assign $0\cur_idx15[3:0] $1\cur_idx15[3:0] + attribute \src "libresoc.v:51503.5-51503.29" + switch \initial + attribute \src "libresoc.v:51503.9-51503.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$201 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx15[3:0] 4'1111 + case + assign $1\cur_idx15[3:0] \cur_idx14 + end + sync always + update \cur_idx15 $0\cur_idx15[3:0] + end + attribute \src "libresoc.v:51512.3-51521.6" + process $proc$libresoc.v:51512$2331 + assign { } { } + assign { } { } + assign $0\ibit[0:0] $1\ibit[0:0] + attribute \src "libresoc.v:51513.5-51513.29" + switch \initial + attribute \src "libresoc.v:51513.9-51513.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" + switch { \reg_is_debug \reg_is_config \reg_is_xive } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\ibit[0:0] \$71 + case + assign $1\ibit[0:0] 1'0 + end + sync always + update \ibit $0\ibit[0:0] + end + attribute \src "libresoc.v:51522.3-51530.6" + process $proc$libresoc.v:51522$2332 + assign { } { } + assign { } { } + assign $0\ics_wb__dat_r$next[31:0]$2333 $1\ics_wb__dat_r$next[31:0]$2334 + attribute \src "libresoc.v:51523.5-51523.29" + switch \initial + attribute \src "libresoc.v:51523.9-51523.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ics_wb__dat_r$next[31:0]$2334 0 + case + assign $1\ics_wb__dat_r$next[31:0]$2334 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + end + sync always + update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$2333 + end + attribute \src "libresoc.v:51531.3-51539.6" + process $proc$libresoc.v:51531$2335 + assign { } { } + assign { } { } + assign $0\ics_wb__ack$next[0:0]$2336 $1\ics_wb__ack$next[0:0]$2337 + attribute \src "libresoc.v:51532.5-51532.29" + switch \initial + attribute \src "libresoc.v:51532.9-51532.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \intclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ics_wb__ack$next[0:0]$2337 1'0 + case + assign $1\ics_wb__ack$next[0:0]$2337 \wb_valid + end + sync always + update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$2336 + end + connect \$7 $ternary$libresoc.v:50902$2090_Y + connect \$99 $lt$libresoc.v:50903$2091_Y + connect \$101 $and$libresoc.v:50904$2092_Y + connect \$103 $lt$libresoc.v:50905$2093_Y + connect \$105 $and$libresoc.v:50906$2094_Y + connect \$107 $lt$libresoc.v:50907$2095_Y + connect \$109 $and$libresoc.v:50908$2096_Y + connect \$111 $lt$libresoc.v:50909$2097_Y + connect \$113 $and$libresoc.v:50910$2098_Y + connect \$115 $lt$libresoc.v:50911$2099_Y + connect \$117 $and$libresoc.v:50912$2100_Y + connect \$119 $lt$libresoc.v:50913$2101_Y + connect \$121 $and$libresoc.v:50914$2102_Y + connect \$123 $lt$libresoc.v:50915$2103_Y + connect \$125 $and$libresoc.v:50916$2104_Y + connect \$127 $lt$libresoc.v:50917$2105_Y + connect \$12 $eq$libresoc.v:50918$2106_Y + connect \$129 $and$libresoc.v:50919$2107_Y + connect \$131 $lt$libresoc.v:50920$2108_Y + connect \$133 $and$libresoc.v:50921$2109_Y + connect \$135 $lt$libresoc.v:50922$2110_Y + connect \$137 $and$libresoc.v:50923$2111_Y + connect \$11 $ternary$libresoc.v:50924$2112_Y + connect \$139 $lt$libresoc.v:50925$2113_Y + connect \$141 $and$libresoc.v:50926$2114_Y + connect \$143 $lt$libresoc.v:50927$2115_Y + connect \$145 $and$libresoc.v:50928$2116_Y + connect \$147 $lt$libresoc.v:50929$2117_Y + connect \$149 $and$libresoc.v:50930$2118_Y + connect \$151 $lt$libresoc.v:50931$2119_Y + connect \$153 $and$libresoc.v:50932$2120_Y + connect \$155 $lt$libresoc.v:50933$2121_Y + connect \$157 $and$libresoc.v:50934$2122_Y + connect \$159 $lt$libresoc.v:50935$2123_Y + connect \$161 $and$libresoc.v:50936$2124_Y + connect \$163 $lt$libresoc.v:50937$2125_Y + connect \$165 $and$libresoc.v:50938$2126_Y + connect \$167 $lt$libresoc.v:50939$2127_Y + connect \$16 $eq$libresoc.v:50940$2128_Y + connect \$169 $and$libresoc.v:50941$2129_Y + connect \$171 $lt$libresoc.v:50942$2130_Y + connect \$173 $and$libresoc.v:50943$2131_Y + connect \$175 $lt$libresoc.v:50944$2132_Y + connect \$177 $and$libresoc.v:50945$2133_Y + connect \$15 $ternary$libresoc.v:50946$2134_Y + connect \$179 $lt$libresoc.v:50947$2135_Y + connect \$181 $and$libresoc.v:50948$2136_Y + connect \$183 $lt$libresoc.v:50949$2137_Y + connect \$185 $and$libresoc.v:50950$2138_Y + connect \$187 $lt$libresoc.v:50951$2139_Y + connect \$189 $and$libresoc.v:50952$2140_Y + connect \$191 $lt$libresoc.v:50953$2141_Y + connect \$193 $and$libresoc.v:50954$2142_Y + connect \$195 $lt$libresoc.v:50955$2143_Y + connect \$197 $and$libresoc.v:50956$2144_Y + connect \$1 $eq$libresoc.v:50957$2145_Y + connect \$199 $lt$libresoc.v:50958$2146_Y + connect \$201 $and$libresoc.v:50959$2147_Y + connect \$204 $eq$libresoc.v:50960$2148_Y + connect \$203 $ternary$libresoc.v:50961$2149_Y + connect \$20 $eq$libresoc.v:50962$2150_Y + connect \$19 $ternary$libresoc.v:50963$2151_Y + connect \$24 $eq$libresoc.v:50964$2152_Y + connect \$23 $ternary$libresoc.v:50965$2153_Y + connect \$28 $eq$libresoc.v:50966$2154_Y + connect \$27 $ternary$libresoc.v:50967$2155_Y + connect \$32 $eq$libresoc.v:50968$2156_Y + connect \$31 $ternary$libresoc.v:50969$2157_Y + connect \$36 $eq$libresoc.v:50970$2158_Y + connect \$35 $ternary$libresoc.v:50971$2159_Y + connect \$3 $eq$libresoc.v:50972$2160_Y + connect \$40 $eq$libresoc.v:50973$2161_Y + connect \$39 $ternary$libresoc.v:50974$2162_Y + connect \$44 $eq$libresoc.v:50975$2163_Y + connect \$43 $ternary$libresoc.v:50976$2164_Y + connect \$48 $eq$libresoc.v:50977$2165_Y + connect \$47 $ternary$libresoc.v:50978$2166_Y + connect \$52 $eq$libresoc.v:50979$2167_Y + connect \$51 $ternary$libresoc.v:50980$2168_Y + connect \$56 $eq$libresoc.v:50981$2169_Y + connect \$55 $ternary$libresoc.v:50982$2170_Y + connect \$5 $and$libresoc.v:50983$2171_Y + connect \$60 $eq$libresoc.v:50984$2172_Y + connect \$59 $ternary$libresoc.v:50985$2173_Y + connect \$64 $eq$libresoc.v:50986$2174_Y + connect \$63 $ternary$libresoc.v:50987$2175_Y + connect \$68 $eq$libresoc.v:50988$2176_Y + connect \$67 $ternary$libresoc.v:50989$2177_Y + connect \$71 $shr$libresoc.v:50990$2178_Y [0] + connect \$73 $and$libresoc.v:50991$2179_Y + connect \$75 $lt$libresoc.v:50992$2180_Y + connect \$77 $and$libresoc.v:50993$2181_Y + connect \$79 $lt$libresoc.v:50994$2182_Y + connect \$81 $and$libresoc.v:50995$2183_Y + connect \$83 $lt$libresoc.v:50996$2184_Y + connect \$85 $and$libresoc.v:50997$2185_Y + connect \$87 $lt$libresoc.v:50998$2186_Y + connect \$8 $eq$libresoc.v:50999$2187_Y + connect \$89 $and$libresoc.v:51000$2188_Y + connect \$91 $lt$libresoc.v:51001$2189_Y + connect \$93 $and$libresoc.v:51002$2190_Y + connect \$95 $lt$libresoc.v:51003$2191_Y + connect \$97 $and$libresoc.v:51004$2192_Y + connect \icp_r_pri \$203 + connect \icp_r_src \cur_idx15 + connect \max_idx 4'0000 + connect \max_pri 8'11111111 + connect { \icp_o_pri$next \icp_o_src$next } { \icp_r_pri \icp_r_src } + connect \be_in { \ics_wb__dat_w [7:0] \ics_wb__dat_w [15:8] \ics_wb__dat_w [23:16] \ics_wb__dat_w [31:24] } + connect \wb_valid \$5 + connect \reg_idx \ics_wb__adr [3:0] + connect \reg_is_debug \$3 + connect \reg_is_config \$1 + connect \reg_is_xive \ics_wb__adr [9] +end diff --git a/pinmux b/pinmux index 53a0fdc..9795616 160000 --- a/pinmux +++ b/pinmux @@ -1 +1 @@ -Subproject commit 53a0fdcfa1c8073b7d0e227c5cb14b1d9d87dd49 +Subproject commit 979561656b82cea849876330e659b03388450d94